DevPit-i8254.cpp@ 11284

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1	/** $Id: DevPit-i8254.cpp 11269 2008-08-08 16:24:48Z vboxsync $ */
2	/** @file
3	* DevPIT-i8254 - Intel 8254 Programmable Interval Timer (PIT) And Dummy Speaker Device.
4	*/
5
6	/*
7	* Copyright (C) 2006-2007 Sun Microsystems, Inc.
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*
17	* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
18	* Clara, CA 95054 USA or visit http://www.sun.com if you need
19	* additional information or have any questions.
20	* --------------------------------------------------------------------
21	*
22	* This code is based on:
23	*
24	* QEMU 8253/8254 interval timer emulation
25	*
26	* Copyright (c) 2003-2004 Fabrice Bellard
27	*
28	* Permission is hereby granted, free of charge, to any person obtaining a copy
29	* of this software and associated documentation files (the "Software"), to deal
30	* in the Software without restriction, including without limitation the rights
31	* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
32	* copies of the Software, and to permit persons to whom the Software is
33	* furnished to do so, subject to the following conditions:
34	*
35	* The above copyright notice and this permission notice shall be included in
36	* all copies or substantial portions of the Software.
37	*
38	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
39	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
40	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
41	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
42	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
43	* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
44	* THE SOFTWARE.
45	*/
46
47	/*******************************************************************************
48	* Header Files *
49	*******************************************************************************/
50	#define LOG_GROUP LOG_GROUP_DEV_PIT
51	#include <VBox/pdmdev.h>
52	#include <VBox/log.h>
53	#include <VBox/stam.h>
54	#include <iprt/assert.h>
55	#include <iprt/asm.h>
56
57	#include "../Builtins.h"
58
59
60	/*******************************************************************************
61	* Defined Constants And Macros *
62	*******************************************************************************/
63	/** The PIT frequency. */
64	#define PIT_FREQ 1193182
65
66	#define RW_STATE_LSB 1
67	#define RW_STATE_MSB 2
68	#define RW_STATE_WORD0 3
69	#define RW_STATE_WORD1 4
70
71	/** The version of the saved state. */
72	#define PIT_SAVED_STATE_VERSION 2
73
74	/** @def FAKE_REFRESH_CLOCK
75	* Define this to flip the 15usec refresh bit on every read.
76	* If not defined, it will be flipped correctly. */
77	//#define FAKE_REFRESH_CLOCK
78
79
80	/*******************************************************************************
81	* Structures and Typedefs *
82	*******************************************************************************/
83	typedef struct PITChannelState
84	{
85	/** Pointer to the instance data - R3 Ptr. */
86	R3PTRTYPE(struct PITState *) pPitR3;
87	/** The timer - R3 Ptr. */
88	PTMTIMERR3 pTimerR3;
89	/** Pointer to the instance data - R0 Ptr. */
90	R0PTRTYPE(struct PITState *) pPitR0;
91	/** The timer - R0 Ptr. */
92	PTMTIMERR0 pTimerR0;
93	/** Pointer to the instance data - RC Ptr. */
94	RCPTRTYPE(struct PITState *) pPitRC;
95	/** The timer - RC Ptr. */
96	PTMTIMERRC pTimerRC;
97	/** The virtual time stamp at the last reload. (only used in mode 2 for now) */
98	uint64_t u64ReloadTS;
99	/** The actual time of the next tick.
100	* As apposed to the next_transition_time which contains the correct time of the next tick. */
101	uint64_t u64NextTS;
102
103	/** (count_load_time is only set by TMTimerGet() which returns uint64_t) */
104	uint64_t count_load_time;
105	/* irq handling */
106	int64_t next_transition_time;
107	int32_t irq;
108	/** Number of release log entries. Used to prevent floading. */
109	uint32_t cRelLogEntries;
110
111	uint32_t count; /* can be 65536 */
112	uint16_t latched_count;
113	uint8_t count_latched;
114	uint8_t status_latched;
115
116	uint8_t status;
117	uint8_t read_state;
118	uint8_t write_state;
119	uint8_t write_latch;
120
121	uint8_t rw_mode;
122	uint8_t mode;
123	uint8_t bcd; /* not supported */
124	uint8_t gate; /* timer start */
125
126	} PITChannelState;
127
128	typedef struct PITState
129	{
130	PITChannelState channels[3];
131	/** Speaker data. */
132	int32_t speaker_data_on;
133	#ifdef FAKE_REFRESH_CLOCK
134	/** Speaker dummy. */
135	int32_t dummy_refresh_clock;
136	#else
137	uint32_t Alignment1;
138	#endif
139	/** Pointer to the device instance. */
140	PPDMDEVINSR3 pDevIns;
141	#if HC_ARCH_BITS == 32
142	uint32_t Alignment0;
143	#endif
144	/** Number of IRQs that's been raised. */
145	STAMCOUNTER StatPITIrq;
146	/** Profiling the timer callback handler. */
147	STAMPROFILEADV StatPITHandler;
148	} PITState;
149
150
151	#ifndef VBOX_DEVICE_STRUCT_TESTCASE
152	/*******************************************************************************
153	* Internal Functions *
154	*******************************************************************************/
155	__BEGIN_DECLS
156	PDMBOTHCBDECL(int) pitIOPortRead(PPDMDEVINS pDevIns, void pvUser, RTIOPORT Port, uint32_t pu32, unsigned cb);
157	PDMBOTHCBDECL(int) pitIOPortWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb);
158	PDMBOTHCBDECL(int) pitIOPortSpeakerRead(PPDMDEVINS pDevIns, void pvUser, RTIOPORT Port, uint32_t pu32, unsigned cb);
159	#ifdef IN_RING3
160	PDMBOTHCBDECL(int) pitIOPortSpeakerWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb);
161	static void pit_irq_timer_update(PITChannelState *s, uint64_t current_time);
162	#endif
163	__END_DECLS
164
165
166
167
168	static int pit_get_count(PITChannelState *s)
169	{
170	uint64_t d;
171	int counter;
172	PTMTIMER pTimer = s->CTX_SUFF(pPit)->channels[0].CTX_SUFF(pTimer);
173
174	if (s->mode == 2)
175	{
176	if (s->u64NextTS == UINT64_MAX)
177	return 1; /** @todo check this value. */
178	d = TMTimerGet(pTimer);
179	d = ASMMultU64ByU32DivByU32(d - s->u64ReloadTS, s->count, s->u64NextTS - s->u64ReloadTS);
180	if (d >= s->count)
181	return 1;
182	return s->count - d;
183	}
184	d = ASMMultU64ByU32DivByU32(TMTimerGet(pTimer) - s->count_load_time, PIT_FREQ, TMTimerGetFreq(pTimer));
185	switch(s->mode) {
186	case 0:
187	case 1:
188	case 4:
189	case 5:
190	counter = (s->count - d) & 0xffff;
191	break;
192	case 3:
193	/* XXX: may be incorrect for odd counts */
194	counter = s->count - ((2 * d) % s->count);
195	break;
196	default:
197	counter = s->count - (d % s->count);
198	break;
199	}
200	/** @todo check that we don't return 0, in most modes (all?) the counter shouldn't be zero. */
201	return counter;
202	}
203
204	/* get pit output bit */
205	static int pit_get_out1(PITChannelState *s, int64_t current_time)
206	{
207	uint64_t d;
208	PTMTIMER pTimer = s->CTX_SUFF(pPit)->channels[0].CTX_SUFF(pTimer);
209	int out;
210
211	d = ASMMultU64ByU32DivByU32(current_time - s->count_load_time, PIT_FREQ, TMTimerGetFreq(pTimer));
212	switch(s->mode) {
213	default:
214	case 0:
215	out = (d >= s->count);
216	break;
217	case 1:
218	out = (d < s->count);
219	break;
220	case 2:
221	Log2(("pit_get_out1: d=%llx c=%x %x \n", d, s->count, (unsigned)(d % s->count)));
222	if ((d % s->count) == 0 && d != 0)
223	out = 1;
224	else
225	out = 0;
226	break;
227	case 3:
228	out = (d % s->count) < ((s->count + 1) >> 1);
229	break;
230	case 4:
231	case 5:
232	out = (d == s->count);
233	break;
234	}
235	return out;
236	}
237
238
239	static int pit_get_out(PITState *pit, int channel, int64_t current_time)
240	{
241	PITChannelState *s = &pit->channels[channel];
242	return pit_get_out1(s, current_time);
243	}
244
245
246	static int pit_get_gate(PITState *pit, int channel)
247	{
248	PITChannelState *s = &pit->channels[channel];
249	return s->gate;
250	}
251
252
253	/* if already latched, do not latch again */
254	static void pit_latch_count(PITChannelState *s)
255	{
256	if (!s->count_latched) {
257	s->latched_count = pit_get_count(s);
258	s->count_latched = s->rw_mode;
259	LogFlow(("pit_latch_count: latched_count=%#06x / %10RU64 ns (c=%#06x m=%d)\n",
260	s->latched_count, ASMMultU64ByU32DivByU32(s->count - s->latched_count, 1000000000, PIT_FREQ), s->count, s->mode));
261	}
262	}
263
264	#ifdef IN_RING3
265
266	/* val must be 0 or 1 */
267	static void pit_set_gate(PITState *pit, int channel, int val)
268	{
269	PITChannelState *s = &pit->channels[channel];
270	PTMTIMER pTimer = s->CTX_SUFF(pPit)->channels[0].CTX_SUFF(pTimer);
271	Assert((val & 1) == val);
272
273	switch(s->mode) {
274	default:
275	case 0:
276	case 4:
277	/* XXX: just disable/enable counting */
278	break;
279	case 1:
280	case 5:
281	if (s->gate < val) {
282	/* restart counting on rising edge */
283	s->count_load_time = TMTimerGet(pTimer);
284	pit_irq_timer_update(s, s->count_load_time);
285	}
286	break;
287	case 2:
288	case 3:
289	if (s->gate < val) {
290	/* restart counting on rising edge */
291	s->count_load_time = s->u64ReloadTS = TMTimerGet(pTimer);
292	pit_irq_timer_update(s, s->count_load_time);
293	}
294	/* XXX: disable/enable counting */
295	break;
296	}
297	s->gate = val;
298	}
299
300	DECLINLINE(void) pit_load_count(PITChannelState *s, int val)
301	{
302	PTMTIMER pTimer = s->CTX_SUFF(pPit)->channels[0].CTX_SUFF(pTimer);
303	if (val == 0)
304	val = 0x10000;
305	s->count_load_time = s->u64ReloadTS = TMTimerGet(pTimer);
306	s->count = val;
307	pit_irq_timer_update(s, s->count_load_time);
308
309	/* log the new rate (ch 0 only). */
310	if ( s->pTimerR3 /* ch 0 */
311	&& s->cRelLogEntries++ < 32)
312	LogRel(("PIT: mode=%d count=%#x (%u) - %d.%02d Hz (ch=0)\n",
313	s->mode, s->count, s->count, PIT_FREQ / s->count, (PIT_FREQ * 100 / s->count) % 100));
314	}
315
316	/* return -1 if no transition will occur. */
317	static int64_t pit_get_next_transition_time(PITChannelState *s,
318	uint64_t current_time)
319	{
320	PTMTIMER pTimer = s->CTX_SUFF(pPit)->channels[0].CTX_SUFF(pTimer);
321	uint64_t d, next_time, base;
322	uint32_t period2;
323
324	d = ASMMultU64ByU32DivByU32(current_time - s->count_load_time, PIT_FREQ, TMTimerGetFreq(pTimer));
325	switch(s->mode) {
326	default:
327	case 0:
328	case 1:
329	if (d < s->count)
330	next_time = s->count;
331	else
332	return -1;
333	break;
334	/*
335	* Mode 2: The period is count + 1 PIT ticks.
336	* When the counter reaches 1 we sent the output low (for channel 0 that
337	* means raise an irq). On the next tick, where we should be decrementing
338	* from 1 to 0, the count is loaded and the output goes high (channel 0
339	* means clearing the irq).
340	*
341	* In VBox we simplify the tick cycle between 1 and 0 and immediately clears
342	* the irq. We also don't set it until we reach 0, which is a tick late - will
343	* try fix that later some day.
344	*/
345	case 2:
346	base = (d / s->count) * s->count;
347	#ifndef VBOX /* see above */
348	if ((d - base) == 0 && d != 0)
349	next_time = base + s->count;
350	else
351	#endif
352	next_time = base + s->count + 1;
353	break;
354	case 3:
355	base = (d / s->count) * s->count;
356	period2 = ((s->count + 1) >> 1);
357	if ((d - base) < period2)
358	next_time = base + period2;
359	else
360	next_time = base + s->count;
361	break;
362	case 4:
363	case 5:
364	if (d < s->count)
365	next_time = s->count;
366	else if (d == s->count)
367	next_time = s->count + 1;
368	else
369	return -1;
370	break;
371	}
372	/* convert to timer units */
373	LogFlow(("PIT: next_time=%14RI64 %20RI64 mode=%#x count=%#06x\n", next_time,
374	ASMMultU64ByU32DivByU32(next_time, TMTimerGetFreq(pTimer), PIT_FREQ), s->mode, s->count));
375	next_time = s->count_load_time + ASMMultU64ByU32DivByU32(next_time, TMTimerGetFreq(pTimer), PIT_FREQ);
376	/* fix potential rounding problems */
377	/* XXX: better solution: use a clock at PIT_FREQ Hz */
378	if (next_time <= current_time)
379	next_time = current_time + 1;
380	return next_time;
381	}
382
383	static void pit_irq_timer_update(PITChannelState *s, uint64_t current_time)
384	{
385	uint64_t now;
386	int64_t expire_time;
387	int irq_level;
388	PPDMDEVINS pDevIns;
389	PTMTIMER pTimer = s->CTX_SUFF(pPit)->channels[0].CTX_SUFF(pTimer);
390
391	if (!s->CTX_SUFF(pTimer))
392	return;
393	expire_time = pit_get_next_transition_time(s, current_time);
394	irq_level = pit_get_out1(s, current_time);
395
396	/* We just flip-flop the irq level to save that extra timer call, which isn't generally required (we haven't served it for months). */
397	pDevIns = s->CTX_SUFF(pPit)->pDevIns;
398	PDMDevHlpISASetIrq(pDevIns, s->irq, irq_level);
399	if (irq_level)
400	PDMDevHlpISASetIrq(pDevIns, s->irq, 0);
401	now = TMTimerGet(pTimer);
402	Log3(("pit_irq_timer_update: %lldns late\n", now - s->u64NextTS));
403	if (irq_level)
404	{
405	s->u64ReloadTS = now;
406	STAM_COUNTER_INC(&s->CTX_SUFF(pPit)->StatPITIrq);
407	}
408
409	if (expire_time != -1)
410	{
411	s->u64NextTS = expire_time;
412	TMTimerSet(s->CTX_SUFF(pTimer), s->u64NextTS);
413	}
414	else
415	{
416	LogFlow(("PIT: m=%d count=%#4x irq_level=%#x stopped\n", s->mode, s->count, irq_level));
417	TMTimerStop(s->CTX_SUFF(pTimer));
418	s->u64NextTS = UINT64_MAX;
419	}
420	s->next_transition_time = expire_time;
421	}
422
423	#endif /* IN_RING3 */
424
425
426	/**
427	* Port I/O Handler for IN operations.
428	*
429	* @returns VBox status code.
430	*
431	* @param pDevIns The device instance.
432	* @param pvUser User argument - ignored.
433	* @param Port Port number used for the IN operation.
434	* @param pu32 Where to store the result.
435	* @param cb Number of bytes read.
436	*/
437	PDMBOTHCBDECL(int) pitIOPortRead(PPDMDEVINS pDevIns, void pvUser, RTIOPORT Port, uint32_t pu32, unsigned cb)
438	{
439	Log2(("pitIOPortRead: Port=%#x cb=%x\n", Port, cb));
440	NOREF(pvUser);
441	Port &= 3;
442	if (cb != 1 \|\| Port == 3)
443	{
444	Log(("pitIOPortRead: Port=%#x cb=%x *pu32=unused!\n", Port, cb));
445	return VERR_IOM_IOPORT_UNUSED;
446	}
447
448	PITState pit = PDMINS_2_DATA(pDevIns, PITState );
449	int ret;
450	PITChannelState *s = &pit->channels[Port];
451	if (s->status_latched)
452	{
453	s->status_latched = 0;
454	ret = s->status;
455	}
456	else if (s->count_latched)
457	{
458	switch (s->count_latched)
459	{
460	default:
461	case RW_STATE_LSB:
462	ret = s->latched_count & 0xff;
463	s->count_latched = 0;
464	break;
465	case RW_STATE_MSB:
466	ret = s->latched_count >> 8;
467	s->count_latched = 0;
468	break;
469	case RW_STATE_WORD0:
470	ret = s->latched_count & 0xff;
471	s->count_latched = RW_STATE_MSB;
472	break;
473	}
474	}
475	else
476	{
477	int count;
478	switch (s->read_state)
479	{
480	default:
481	case RW_STATE_LSB:
482	count = pit_get_count(s);
483	ret = count & 0xff;
484	break;
485	case RW_STATE_MSB:
486	count = pit_get_count(s);
487	ret = (count >> 8) & 0xff;
488	break;
489	case RW_STATE_WORD0:
490	count = pit_get_count(s);
491	ret = count & 0xff;
492	s->read_state = RW_STATE_WORD1;
493	break;
494	case RW_STATE_WORD1:
495	count = pit_get_count(s);
496	ret = (count >> 8) & 0xff;
497	s->read_state = RW_STATE_WORD0;
498	break;
499	}
500	}
501
502	*pu32 = ret;
503	Log2(("pitIOPortRead: Port=%#x cb=%x pu32=%#04x\n", Port, cb, pu32));
504	return VINF_SUCCESS;
505	}
506
507
508	/**
509	* Port I/O Handler for OUT operations.
510	*
511	* @returns VBox status code.
512	*
513	* @param pDevIns The device instance.
514	* @param pvUser User argument - ignored.
515	* @param Port Port number used for the IN operation.
516	* @param u32 The value to output.
517	* @param cb The value size in bytes.
518	*/
519	PDMBOTHCBDECL(int) pitIOPortWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb)
520	{
521	Log2(("pitIOPortWrite: Port=%#x cb=%x u32=%#04x\n", Port, cb, u32));
522	NOREF(pvUser);
523	if (cb != 1)
524	return VINF_SUCCESS;
525
526	PITState pit = PDMINS_2_DATA(pDevIns, PITState );
527	Port &= 3;
528	if (Port == 3)
529	{
530	/*
531	* Port 43h - Mode/Command Register.
532	* 7 6 5 4 3 2 1 0
533	* * * . . . . . . Select channel: 0 0 = Channel 0
534	* 0 1 = Channel 1
535	* 1 0 = Channel 2
536	* 1 1 = Read-back command (8254 only)
537	* (Illegal on 8253)
538	* (Illegal on PS/2 {JAM})
539	* . . * * . . . . Command/Access mode: 0 0 = Latch count value command
540	* 0 1 = Access mode: lobyte only
541	* 1 0 = Access mode: hibyte only
542	* 1 1 = Access mode: lobyte/hibyte
543	* . . . . * * * . Operating mode: 0 0 0 = Mode 0, 0 0 1 = Mode 1,
544	* 0 1 0 = Mode 2, 0 1 1 = Mode 3,
545	* 1 0 0 = Mode 4, 1 0 1 = Mode 5,
546	* 1 1 0 = Mode 2, 1 1 1 = Mode 3
547	* . . . . . . . * BCD/Binary mode: 0 = 16-bit binary, 1 = four-digit BCD
548	*/
549	unsigned channel = u32 >> 6;
550	if (channel == 3)
551	{
552	/* read-back command */
553	for (channel = 0; channel < RT_ELEMENTS(pit->channels); channel++)
554	{
555	PITChannelState *s = &pit->channels[channel];
556	if (u32 & (2 << channel)) {
557	if (!(u32 & 0x20))
558	pit_latch_count(s);
559	if (!(u32 & 0x10) && !s->status_latched)
560	{
561	/* status latch */
562	/* XXX: add BCD and null count */
563	PTMTIMER pTimer = s->CTX_SUFF(pPit)->channels[0].CTX_SUFF(pTimer);
564	s->status = (pit_get_out1(s, TMTimerGet(pTimer)) << 7)
565	\| (s->rw_mode << 4)
566	\| (s->mode << 1)
567	\| s->bcd;
568	s->status_latched = 1;
569	}
570	}
571	}
572	}
573	else
574	{
575	PITChannelState *s = &pit->channels[channel];
576	unsigned access = (u32 >> 4) & 3;
577	if (access == 0)
578	pit_latch_count(s);
579	else
580	{
581	s->rw_mode = access;
582	s->read_state = access;
583	s->write_state = access;
584
585	s->mode = (u32 >> 1) & 7;
586	s->bcd = u32 & 1;
587	/* XXX: update irq timer ? */
588	}
589	}
590	}
591	else
592	{
593	#ifndef IN_RING3
594	return VINF_IOM_HC_IOPORT_WRITE;
595	#else /* IN_RING3 */
596	/*
597	* Port 40-42h - Channel Data Ports.
598	*/
599	PITChannelState *s = &pit->channels[Port];
600	switch(s->write_state)
601	{
602	default:
603	case RW_STATE_LSB:
604	pit_load_count(s, u32);
605	break;
606	case RW_STATE_MSB:
607	pit_load_count(s, u32 << 8);
608	break;
609	case RW_STATE_WORD0:
610	s->write_latch = u32;
611	s->write_state = RW_STATE_WORD1;
612	break;
613	case RW_STATE_WORD1:
614	pit_load_count(s, s->write_latch \| (u32 << 8));
615	s->write_state = RW_STATE_WORD0;
616	break;
617	}
618	#endif /* !IN_RING3 */
619	}
620	return VINF_SUCCESS;
621	}
622
623
624	/**
625	* Port I/O Handler for speaker IN operations.
626	*
627	* @returns VBox status code.
628	*
629	* @param pDevIns The device instance.
630	* @param pvUser User argument - ignored.
631	* @param Port Port number used for the IN operation.
632	* @param pu32 Where to store the result.
633	* @param cb Number of bytes read.
634	*/
635	PDMBOTHCBDECL(int) pitIOPortSpeakerRead(PPDMDEVINS pDevIns, void pvUser, RTIOPORT Port, uint32_t pu32, unsigned cb)
636	{
637	NOREF(pvUser);
638	if (cb == 1)
639	{
640	PITState pThis = PDMINS_2_DATA(pDevIns, PITState );
641	const uint64_t u64Now = TMTimerGet(pThis->channels[0].CTX_SUFF(pTimer));
642	Assert(TMTimerGetFreq(pThis->channels[0].CTX_SUFF(pTimer)) == 1000000000); /* lazy bird. */
643
644	/* bit 6,7 Parity error stuff. */
645	/* bit 5 - mirrors timer 2 output condition. */
646	const int fOut = pit_get_out(pThis, 2, u64Now);
647	/* bit 4 - toggled every with each (DRAM?) refresh request, every 15.085 µs. */
648	#ifdef FAKE_REFRESH_CLOCK
649	pThis->dummy_refresh_clock ^= 1;
650	const int fRefresh = pThis->dummy_refresh_clock;
651	#else
652	const int fRefresh = (u64Now / 15085) & 1;
653	#endif
654	/* bit 2,3 NMI / parity status stuff. */
655	/* bit 1 - speaker data status */
656	const int fSpeakerStatus = pThis->speaker_data_on;
657	/* bit 0 - timer 2 clock gate to speaker status. */
658	const int fTimer2GateStatus = pit_get_gate(pThis, 2);
659
660	*pu32 = fTimer2GateStatus
661	\| (fSpeakerStatus << 1)
662	\| (fRefresh << 4)
663	\| (fOut << 5);
664	Log(("pitIOPortSpeakerRead: Port=%#x cb=%x pu32=%#x\n", Port, cb, pu32));
665	return VINF_SUCCESS;
666	}
667	Log(("pitIOPortSpeakerRead: Port=%#x cb=%x *pu32=unused!\n", Port, cb));
668	return VERR_IOM_IOPORT_UNUSED;
669	}
670
671	#ifdef IN_RING3
672
673	/**
674	* Port I/O Handler for speaker OUT operations.
675	*
676	* @returns VBox status code.
677	*
678	* @param pDevIns The device instance.
679	* @param pvUser User argument - ignored.
680	* @param Port Port number used for the IN operation.
681	* @param u32 The value to output.
682	* @param cb The value size in bytes.
683	*/
684	PDMBOTHCBDECL(int) pitIOPortSpeakerWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb)
685	{
686	NOREF(pvUser);
687	if (cb == 1)
688	{
689	PITState pThis = PDMINS_2_DATA(pDevIns, PITState );
690	pThis->speaker_data_on = (u32 >> 1) & 1;
691	pit_set_gate(pThis, 2, u32 & 1);
692	}
693	Log(("pitIOPortSpeakerWrite: Port=%#x cb=%x u32=%#x\n", Port, cb, u32));
694	return VINF_SUCCESS;
695	}
696
697
698	/**
699	* Saves a state of the programmable interval timer device.
700	*
701	* @returns VBox status code.
702	* @param pDevIns The device instance.
703	* @param pSSMHandle The handle to save the state to.
704	*/
705	static DECLCALLBACK(int) pitSaveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSMHandle)
706	{
707	PITState pThis = PDMINS_2_DATA(pDevIns, PITState );
708	unsigned i;
709
710	for (i = 0; i < RT_ELEMENTS(pThis->channels); i++)
711	{
712	PITChannelState *s = &pThis->channels[i];
713	SSMR3PutU32(pSSMHandle, s->count);
714	SSMR3PutU16(pSSMHandle, s->latched_count);
715	SSMR3PutU8(pSSMHandle, s->count_latched);
716	SSMR3PutU8(pSSMHandle, s->status_latched);
717	SSMR3PutU8(pSSMHandle, s->status);
718	SSMR3PutU8(pSSMHandle, s->read_state);
719	SSMR3PutU8(pSSMHandle, s->write_state);
720	SSMR3PutU8(pSSMHandle, s->write_latch);
721	SSMR3PutU8(pSSMHandle, s->rw_mode);
722	SSMR3PutU8(pSSMHandle, s->mode);
723	SSMR3PutU8(pSSMHandle, s->bcd);
724	SSMR3PutU8(pSSMHandle, s->gate);
725	SSMR3PutU64(pSSMHandle, s->count_load_time);
726	SSMR3PutU64(pSSMHandle, s->u64NextTS);
727	SSMR3PutU64(pSSMHandle, s->u64ReloadTS);
728	SSMR3PutS64(pSSMHandle, s->next_transition_time);
729	if (s->CTX_SUFF(pTimer))
730	TMR3TimerSave(s->CTX_SUFF(pTimer), pSSMHandle);
731	}
732
733	SSMR3PutS32(pSSMHandle, pThis->speaker_data_on);
734	#ifdef FAKE_REFRESH_CLOCK
735	return SSMR3PutS32(pSSMHandle, pThis->dummy_refresh_clock);
736	#else
737	return SSMR3PutS32(pSSMHandle, 0);
738	#endif
739	}
740
741
742	/**
743	* Loads a saved programmable interval timer device state.
744	*
745	* @returns VBox status code.
746	* @param pDevIns The device instance.
747	* @param pSSMHandle The handle to the saved state.
748	* @param u32Version The data unit version number.
749	*/
750	static DECLCALLBACK(int) pitLoadExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSMHandle, uint32_t u32Version)
751	{
752	PITState pThis = PDMINS_2_DATA(pDevIns, PITState );
753	unsigned i;
754
755	if (u32Version != PIT_SAVED_STATE_VERSION)
756	return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
757
758	for (i = 0; i < RT_ELEMENTS(pThis->channels); i++)
759	{
760	PITChannelState *s = &pThis->channels[i];
761	SSMR3GetU32(pSSMHandle, &s->count);
762	SSMR3GetU16(pSSMHandle, &s->latched_count);
763	SSMR3GetU8(pSSMHandle, &s->count_latched);
764	SSMR3GetU8(pSSMHandle, &s->status_latched);
765	SSMR3GetU8(pSSMHandle, &s->status);
766	SSMR3GetU8(pSSMHandle, &s->read_state);
767	SSMR3GetU8(pSSMHandle, &s->write_state);
768	SSMR3GetU8(pSSMHandle, &s->write_latch);
769	SSMR3GetU8(pSSMHandle, &s->rw_mode);
770	SSMR3GetU8(pSSMHandle, &s->mode);
771	SSMR3GetU8(pSSMHandle, &s->bcd);
772	SSMR3GetU8(pSSMHandle, &s->gate);
773	SSMR3GetU64(pSSMHandle, &s->count_load_time);
774	SSMR3GetU64(pSSMHandle, &s->u64NextTS);
775	SSMR3GetU64(pSSMHandle, &s->u64ReloadTS);
776	SSMR3GetS64(pSSMHandle, &s->next_transition_time);
777	if (s->CTX_SUFF(pTimer))
778	{
779	TMR3TimerLoad(s->CTX_SUFF(pTimer), pSSMHandle);
780	LogRel(("PIT: mode=%d count=%#x (%u) - %d.%02d Hz (ch=%d) (restore)\n",
781	s->mode, s->count, s->count, PIT_FREQ / s->count, (PIT_FREQ * 100 / s->count) % 100, i));
782	}
783	pThis->channels[0].cRelLogEntries = 0;
784	}
785
786	SSMR3GetS32(pSSMHandle, &pThis->speaker_data_on);
787	#ifdef FAKE_REFRESH_CLOCK
788	return SSMR3GetS32(pSSMHandle, &pThis->dummy_refresh_clock);
789	#else
790	int32_t u32Dummy;
791	return SSMR3GetS32(pSSMHandle, &u32Dummy);
792	#endif
793	}
794
795
796	/**
797	* Device timer callback function.
798	*
799	* @param pDevIns Device instance of the device which registered the timer.
800	* @param pTimer The timer handle.
801	*/
802	static DECLCALLBACK(void) pitTimer(PPDMDEVINS pDevIns, PTMTIMER pTimer)
803	{
804	PITState pThis = PDMINS_2_DATA(pDevIns, PITState );
805	PITChannelState *s = &pThis->channels[0];
806	STAM_PROFILE_ADV_START(&s->CTX_SUFF(pPit)->StatPITHandler, a);
807	pit_irq_timer_update(s, s->next_transition_time);
808	STAM_PROFILE_ADV_STOP(&s->CTX_SUFF(pPit)->StatPITHandler, a);
809	}
810
811
812	/**
813	* Relocation notification.
814	*
815	* @returns VBox status.
816	* @param pDevIns The device instance data.
817	* @param offDelta The delta relative to the old address.
818	*/
819	static DECLCALLBACK(void) pitRelocate(PPDMDEVINS pDevIns, RTGCINTPTR offDelta)
820	{
821	PITState pThis = PDMINS_2_DATA(pDevIns, PITState );
822	unsigned i;
823	LogFlow(("pitRelocate: \n"));
824
825	for (i = 0; i < RT_ELEMENTS(pThis->channels); i++)
826	{
827	PITChannelState *pCh = &pThis->channels[i];
828	if (pCh->pTimerR3)
829	pCh->pTimerRC = TMTimerRCPtr(pCh->pTimerR3);
830	pThis->channels[i].pPitRC = PDMINS_2_DATA_RCPTR(pDevIns);
831	}
832	}
833
834	/** @todo remove this! */
835	static DECLCALLBACK(void) pitInfo(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs);
836
837	/**
838	* Reset notification.
839	*
840	* @returns VBox status.
841	* @param pDevIns The device instance data.
842	*/
843	static DECLCALLBACK(void) pitReset(PPDMDEVINS pDevIns)
844	{
845	PITState pThis = PDMINS_2_DATA(pDevIns, PITState );
846	unsigned i;
847	LogFlow(("pitReset: \n"));
848
849	for (i = 0; i < RT_ELEMENTS(pThis->channels); i++)
850	{
851	PITChannelState *s = &pThis->channels[i];
852
853	#if 1 /* Set everything back to virgin state. (might not be strictly correct) */
854	s->latched_count = 0;
855	s->count_latched = 0;
856	s->status_latched = 0;
857	s->status = 0;
858	s->read_state = 0;
859	s->write_state = 0;
860	s->write_latch = 0;
861	s->rw_mode = 0;
862	s->bcd = 0;
863	#endif
864	s->cRelLogEntries = 0;
865	s->mode = 3;
866	s->gate = (i != 2);
867	pit_load_count(s, 0);
868	}
869	}
870
871
872	/**
873	* Info handler, device version.
874	*
875	* @param pDevIns Device instance which registered the info.
876	* @param pHlp Callback functions for doing output.
877	* @param pszArgs Argument string. Optional and specific to the handler.
878	*/
879	static DECLCALLBACK(void) pitInfo(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
880	{
881	PITState pThis = PDMINS_2_DATA(pDevIns, PITState );
882	unsigned i;
883	for (i = 0; i < RT_ELEMENTS(pThis->channels); i++)
884	{
885	const PITChannelState *pCh = &pThis->channels[i];
886
887	pHlp->pfnPrintf(pHlp,
888	"PIT (i8254) channel %d status: irq=%#x\n"
889	" count=%08x" " latched_count=%04x count_latched=%02x\n"
890	" status=%02x status_latched=%02x read_state=%02x\n"
891	" write_state=%02x write_latch=%02x rw_mode=%02x\n"
892	" mode=%02x bcd=%02x gate=%02x\n"
893	" count_load_time=%016RX64 next_transition_time=%016RX64\n"
894	" u64ReloadTS=%016RX64 u64NextTS=%016RX64\n"
895	,
896	i, pCh->irq,
897	pCh->count, pCh->latched_count, pCh->count_latched,
898	pCh->status, pCh->status_latched, pCh->read_state,
899	pCh->write_state, pCh->write_latch, pCh->rw_mode,
900	pCh->mode, pCh->bcd, pCh->gate,
901	pCh->count_load_time, pCh->next_transition_time,
902	pCh->u64ReloadTS, pCh->u64NextTS);
903	}
904	#ifdef FAKE_REFRESH_CLOCK
905	pHlp->pfnPrintf(pHlp, "speaker_data_on=%#x dummy_refresh_clock=%#x\n",
906	pThis->speaker_data_on, pThis->dummy_refresh_clock);
907	#else
908	pHlp->pfnPrintf(pHlp, "speaker_data_on=%#x\n", pThis->speaker_data_on);
909	#endif
910	}
911
912
913	/**
914	* Construct a device instance for a VM.
915	*
916	* @returns VBox status.
917	* @param pDevIns The device instance data.
918	* If the registration structure is needed, pDevIns->pDevReg points to it.
919	* @param iInstance Instance number. Use this to figure out which registers and such to use.
920	* The device number is also found in pDevIns->iInstance, but since it's
921	* likely to be freqently used PDM passes it as parameter.
922	* @param pCfgHandle Configuration node handle for the device. Use this to obtain the configuration
923	* of the device instance. It's also found in pDevIns->pCfgHandle, but like
924	* iInstance it's expected to be used a bit in this function.
925	*/
926	static DECLCALLBACK(int) pitConstruct(PPDMDEVINS pDevIns, int iInstance, PCFGMNODE pCfgHandle)
927	{
928	PITState pThis = PDMINS_2_DATA(pDevIns, PITState );
929	int rc;
930	uint8_t u8Irq;
931	uint16_t u16Base;
932	bool fSpeaker;
933	bool fGCEnabled;
934	bool fR0Enabled;
935	unsigned i;
936	Assert(iInstance == 0);
937
938	/*
939	* Validate configuration.
940	*/
941	if (!CFGMR3AreValuesValid(pCfgHandle, "Irq\0" "Base\0" "Speaker\0" "GCEnabled\0" "R0Enabled\0"))
942	return VERR_PDM_DEVINS_UNKNOWN_CFG_VALUES;
943
944	/*
945	* Init the data.
946	*/
947	rc = CFGMR3QueryU8Def(pCfgHandle, "Irq", &u8Irq, 0);
948	if (RT_FAILURE(rc))
949	return PDMDEV_SET_ERROR(pDevIns, rc,
950	N_("Configuration error: Querying \"Irq\" as a uint8_t failed"));
951
952	rc = CFGMR3QueryU16Def(pCfgHandle, "Base", &u16Base, 0x40);
953	if (RT_FAILURE(rc))
954	return PDMDEV_SET_ERROR(pDevIns, rc,
955	N_("Configuration error: Querying \"Base\" as a uint16_t failed"));
956
957	rc = CFGMR3QueryBoolDef(pCfgHandle, "SpeakerEnabled", &fSpeaker, true);
958	if (RT_FAILURE(rc))
959	return PDMDEV_SET_ERROR(pDevIns, rc,
960	N_("Configuration error: Querying \"SpeakerEnabled\" as a bool failed"));
961
962	rc = CFGMR3QueryBoolDef(pCfgHandle, "GCEnabled", &fGCEnabled, true);
963	if (RT_FAILURE(rc))
964	return PDMDEV_SET_ERROR(pDevIns, rc,
965	N_("Configuration error: Querying \"GCEnabled\" as a bool failed"));
966
967	rc = CFGMR3QueryBoolDef(pCfgHandle, "R0Enabled", &fR0Enabled, true);
968	if (RT_FAILURE(rc))
969	return PDMDEV_SET_ERROR(pDevIns, rc,
970	N_("Configuration error: failed to read R0Enabled as boolean"));
971
972	pThis->pDevIns = pDevIns;
973	pThis->channels[0].irq = u8Irq;
974	for (i = 0; i < RT_ELEMENTS(pThis->channels); i++)
975	{
976	pThis->channels[i].pPitR3 = pThis;
977	pThis->channels[i].pPitR0 = PDMINS_2_DATA_R0PTR(pDevIns);
978	pThis->channels[i].pPitRC = PDMINS_2_DATA_RCPTR(pDevIns);
979	}
980
981	/*
982	* Create timer, register I/O Ports and save state.
983	*/
984	rc = PDMDevHlpTMTimerCreate(pDevIns, TMCLOCK_VIRTUAL_SYNC, pitTimer, "i8254 Programmable Interval Timer",
985	&pThis->channels[0].pTimerR3);
986	if (RT_FAILURE(rc))
987	return rc;
988	pThis->channels[0].pTimerRC = TMTimerRCPtr(pThis->channels[0].pTimerR3);
989	pThis->channels[0].pTimerR0 = TMTimerR0Ptr(pThis->channels[0].pTimerR3);
990
991	rc = PDMDevHlpIOPortRegister(pDevIns, u16Base, 4, NULL, pitIOPortWrite, pitIOPortRead, NULL, NULL, "i8254 Programmable Interval Timer");
992	if (RT_FAILURE(rc))
993	return rc;
994	if (fGCEnabled)
995	{
996	rc = PDMDevHlpIOPortRegisterGC(pDevIns, u16Base, 4, 0, "pitIOPortWrite", "pitIOPortRead", NULL, NULL, "i8254 Programmable Interval Timer");
997	if (RT_FAILURE(rc))
998	return rc;
999	}
1000	if (fR0Enabled)
1001	{
1002	rc = PDMDevHlpIOPortRegisterR0(pDevIns, u16Base, 4, 0, "pitIOPortWrite", "pitIOPortRead", NULL, NULL, "i8254 Programmable Interval Timer");
1003	if (RT_FAILURE(rc))
1004	return rc;
1005	}
1006
1007	if (fSpeaker)
1008	{
1009	rc = PDMDevHlpIOPortRegister(pDevIns, 0x61, 1, NULL, pitIOPortSpeakerWrite, pitIOPortSpeakerRead, NULL, NULL, "PC Speaker");
1010	if (RT_FAILURE(rc))
1011	return rc;
1012	if (fGCEnabled)
1013	{
1014	rc = PDMDevHlpIOPortRegisterGC(pDevIns, 0x61, 1, 0, NULL, "pitIOPortSpeakerRead", NULL, NULL, "PC Speaker");
1015	if (RT_FAILURE(rc))
1016	return rc;
1017	}
1018	}
1019
1020	rc = PDMDevHlpSSMRegister(pDevIns, pDevIns->pDevReg->szDeviceName, iInstance, PIT_SAVED_STATE_VERSION, sizeof(*pThis),
1021	NULL, pitSaveExec, NULL,
1022	NULL, pitLoadExec, NULL);
1023	if (RT_FAILURE(rc))
1024	return rc;
1025
1026	/*
1027	* Initialize the device state.
1028	*/
1029	pitReset(pDevIns);
1030
1031	/*
1032	* Register statistics and debug info.
1033	*/
1034	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatPITIrq, STAMTYPE_COUNTER, "/TM/PIT/Irq", STAMUNIT_OCCURENCES, "The number of times a timer interrupt was triggered.");
1035	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatPITHandler, STAMTYPE_PROFILE, "/TM/PIT/Handler", STAMUNIT_TICKS_PER_CALL, "Profiling timer callback handler.");
1036
1037	PDMDevHlpDBGFInfoRegister(pDevIns, "pit", "Display PIT (i8254) status. (no arguments)", pitInfo);
1038
1039	return VINF_SUCCESS;
1040	}
1041
1042
1043	/**
1044	* The device registration structure.
1045	*/
1046	const PDMDEVREG g_DeviceI8254 =
1047	{
1048	/* u32Version */
1049	PDM_DEVREG_VERSION,
1050	/* szDeviceName */
1051	"i8254",
1052	/* szGCMod */
1053	"VBoxDDGC.gc",
1054	/* szR0Mod */
1055	"VBoxDDR0.r0",
1056	/* pszDescription */
1057	"Intel 8254 Programmable Interval Timer (PIT) And Dummy Speaker Device",
1058	/* fFlags */
1059	PDM_DEVREG_FLAGS_HOST_BITS_DEFAULT \| PDM_DEVREG_FLAGS_GUEST_BITS_32_64 \| PDM_DEVREG_FLAGS_PAE36 \| PDM_DEVREG_FLAGS_GC \| PDM_DEVREG_FLAGS_R0,
1060	/* fClass */
1061	PDM_DEVREG_CLASS_PIT,
1062	/* cMaxInstances */
1063	1,
1064	/* cbInstance */
1065	sizeof(PITState),
1066	/* pfnConstruct */
1067	pitConstruct,
1068	/* pfnDestruct */
1069	NULL,
1070	/* pfnRelocate */
1071	pitRelocate,
1072	/* pfnIOCtl */
1073	NULL,
1074	/* pfnPowerOn */
1075	NULL,
1076	/* pfnReset */
1077	pitReset,
1078	/* pfnSuspend */
1079	NULL,
1080	/* pfnResume */
1081	NULL,
1082	/* pfnAttach */
1083	NULL,
1084	/* pfnDetach */
1085	NULL,
1086	/* pfnQueryInterface. */
1087	NULL
1088	};
1089
1090	#endif /* IN_RING3 */
1091	#endif /* !VBOX_DEVICE_STRUCT_TESTCASE */
1092

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source: vbox/trunk/src/VBox/Devices/PC/DevPit-i8254.cpp@ 11284

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