DevPIC.cpp@ 91942

Last change on this file since 91942 was 91739, checked in by vboxsync, 3 years ago
DevPIC: Avoid release assertion (see bugref:10109).
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1	/* $Id: DevPIC.cpp 91739 2021-10-14 19:21:57Z vboxsync $ */
2	/** @file
3	* DevPIC - Intel 8259 Programmable Interrupt Controller (PIC) Device.
4	*/
5
6	/*
7	* Copyright (C) 2006-2020 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	* -------------------------------------------------------------------
17	*
18	* This code is based on:
19	*
20	* QEMU 8259 interrupt controller emulation
21	*
22	* Copyright (c) 2003-2004 Fabrice Bellard
23	*
24	* Permission is hereby granted, free of charge, to any person obtaining a copy
25	* of this software and associated documentation files (the "Software"), to deal
26	* in the Software without restriction, including without limitation the rights
27	* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
28	* copies of the Software, and to permit persons to whom the Software is
29	* furnished to do so, subject to the following conditions:
30	*
31	* The above copyright notice and this permission notice shall be included in
32	* all copies or substantial portions of the Software.
33	*
34	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
35	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
36	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
37	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
38	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
39	* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
40	* THE SOFTWARE.
41	*
42	*/
43
44
45	/*********************************************************************************************************************************
46	* Header Files *
47	*********************************************************************************************************************************/
48	#define LOG_GROUP LOG_GROUP_DEV_PIC
49	#include <VBox/vmm/pdmdev.h>
50	#include <VBox/log.h>
51	#include <iprt/assert.h>
52	#include <iprt/string.h>
53
54	#include "VBoxDD.h"
55
56
57	/*********************************************************************************************************************************
58	* Defined Constants And Macros *
59	*********************************************************************************************************************************/
60	/** @def PIC_LOCK_RET
61	* Acquires the PDM lock. This is a NOP if locking is disabled. */
62	#define PIC_LOCK_RET(a_pDevIns, a_pThisCC, rcBusy) \
63	do { \
64	int const rcLock = (a_pThisCC)->pPicHlp->pfnLock((a_pDevIns), rcBusy); \
65	if (rcLock == VINF_SUCCESS) \
66	{ /* likely */ } \
67	else \
68	return rcLock; \
69	} while (0)
70	/** @def PIC_UNLOCK
71	* Releases the PDM lock. This is a NOP if locking is disabled. */
72	#define PIC_UNLOCK(a_pDevIns, a_pThisCC) \
73	(a_pThisCC)->pPicHlp->pfnUnlock((a_pDevIns))
74
75
76	/*********************************************************************************************************************************
77	* Structures and Typedefs *
78	*********************************************************************************************************************************/
79	/**
80	* The instance data of one (1) PIC.
81	*/
82	typedef struct PICSTATE
83	{
84	uint8_t last_irr; /*< edge detection /
85	uint8_t irr; /*< interrupt request register /
86	uint8_t imr; /*< interrupt mask register /
87	uint8_t isr; /*< interrupt service register /
88	uint8_t priority_add; /*< highest irq priority /
89	uint8_t irq_base;
90	uint8_t read_reg_select;
91	uint8_t poll;
92	uint8_t special_mask;
93	uint8_t init_state;
94	uint8_t auto_eoi;
95	uint8_t rotate_on_auto_eoi;
96	uint8_t special_fully_nested_mode;
97	uint8_t init4; /*< true if 4 byte init /
98	uint8_t elcr; /*< PIIX edge/trigger selection/
99	uint8_t elcr_mask;
100	/** The IRQ tags and source IDs for each (tracing purposes). */
101	uint32_t auTags[8];
102	/** The PIC index (0 or 1). */
103	uint8_t idxPic;
104	uint8_t abAlignment0[7]; /*< Alignment padding. /
105	/** The two I/O ports at 0x20 or 0xa0. */
106	IOMIOPORTHANDLE hIoPorts0;
107	/** The ELCR I/O port at 0x4d0 or 0x4d1. */
108	IOMIOPORTHANDLE hIoPorts1;
109	} PICSTATE;
110	AssertCompileMemberAlignment(PICSTATE, hIoPorts0, 8);
111	/** Pointer to the state of one PIC. */
112	typedef PICSTATE *PPICSTATE;
113
114
115	/**
116	* The shared PIC device instance data.
117	*/
118	typedef struct DEVPIC
119	{
120	/** The two interrupt controllers. */
121	PICSTATE aPics[2];
122	/** Number of release log entries. Used to prevent flooding. */
123	uint32_t cRelLogEntries;
124	uint32_t u32Padding;
125	#ifdef VBOX_WITH_STATISTICS
126	STAMCOUNTER StatSetIrqRZ;
127	STAMCOUNTER StatSetIrqR3;
128	STAMCOUNTER StatClearedActiveIRQ2;
129	STAMCOUNTER StatClearedActiveMasterIRQ;
130	STAMCOUNTER StatClearedActiveSlaveIRQ;
131	#endif
132	} DEVPIC;
133	/** Pointer to the shared PIC instance data. */
134	typedef DEVPIC *PDEVPIC;
135
136
137	/**
138	* The PIC device instance data for ring-3.
139	*/
140	typedef struct DEVPICR3
141	{
142	/** Pointer to the PIC ring-3 helpers. */
143	R3PTRTYPE(PCPDMPICHLP) pPicHlp;
144	} DEVPICR3;
145	/** Pointer to the ring-3 PIC instance data. */
146	typedef DEVPICR3 *PDEVPICR3;
147
148
149	/**
150	* The PIC device instance data for ring-0.
151	*/
152	typedef struct DEVPICR0
153	{
154	/** Pointer to the PIC ring-0 helpers. */
155	R0PTRTYPE(PCPDMPICHLP) pPicHlp;
156	} DEVPICR0;
157	/** Pointer to the ring-0 PIC instance data. */
158	typedef DEVPICR0 *PDEVPICR0;
159
160
161	/**
162	* The PIC device instance data for raw-mode.
163	*/
164	typedef struct DEVPICRC
165	{
166	/** Pointer to the PIC raw-mode helpers. */
167	RCPTRTYPE(PCPDMPICHLP) pPicHlp;
168	} DEVPICRC;
169	/** Pointer to the raw-mode PIC instance data. */
170	typedef DEVPICRC *PDEVPICRC;
171
172
173	/** The PIC instance data for the current context. */
174	typedef CTX_SUFF(DEVPIC) DEVPICCC;
175	/** Pointer to the PIC instance data for the current context. */
176	typedef CTX_SUFF(PDEVPIC) PDEVPICCC;
177
178
179
180	#ifndef VBOX_DEVICE_STRUCT_TESTCASE /* The rest of the file! */
181
182	#ifdef LOG_ENABLED
183	DECLINLINE(void) DumpPICState(PPICSTATE pPic, const char *pszFn)
184	{
185	Log2(("%s: pic%d: elcr=%x last_irr=%x irr=%x imr=%x isr=%x irq_base=%x\n",
186	pszFn, pPic->idxPic, pPic->elcr, pPic->last_irr, pPic->irr, pPic->imr, pPic->isr, pPic->irq_base));
187	}
188	#else
189	# define DumpPICState(pThis, szFn) do { } while (0)
190	#endif
191
192	/* set irq level. If an edge is detected, then the IRR is set to 1 */
193	DECLINLINE(void) pic_set_irq1(PPICSTATE pPic, int irq, int level, uint32_t uTagSrc)
194	{
195	Log(("pic_set_irq1: irq=%d level=%d\n", irq, level));
196	int mask = 1 << irq;
197	if (pPic->elcr & mask)
198	{
199	/* level triggered */
200	if (level)
201	{
202	Log2(("pic_set_irq1(ls) irr=%d irrnew=%d\n", pPic->irr, pPic->irr \| mask));
203	pPic->irr \|= mask;
204	pPic->last_irr \|= mask;
205	}
206	else
207	{
208	Log2(("pic_set_irq1(lc) irr=%d irrnew=%d\n", pPic->irr, pPic->irr & ~mask));
209	pPic->irr &= ~mask;
210	pPic->last_irr &= ~mask;
211	}
212	}
213	else
214	{
215	/* edge triggered */
216	if (level)
217	{
218	if ((pPic->last_irr & mask) == 0)
219	{
220	Log2(("pic_set_irq1 irr=%x last_irr=%x\n", pPic->irr \| mask, pPic->last_irr));
221	pPic->irr \|= mask;
222	}
223	pPic->last_irr \|= mask;
224	}
225	else
226	{
227	pPic->irr &= ~mask;
228	pPic->last_irr &= ~mask;
229	}
230	}
231
232	/* Save the tag. */
233	if (level)
234	{
235	if (!pPic->auTags[irq])
236	pPic->auTags[irq] = uTagSrc;
237	else
238	pPic->auTags[irq] \|= RT_BIT_32(31);
239	}
240
241	DumpPICState(pPic, "pic_set_irq1");
242	}
243
244	/* return the highest priority found in mask (highest = smallest
245	number). Return 8 if no irq */
246	DECLINLINE(int) get_priority(PPICSTATE pPic, int mask)
247	{
248	int priority;
249	if (mask == 0)
250	return 8;
251	priority = 0;
252	while ((mask & (1 << ((priority + pPic->priority_add) & 7))) == 0)
253	priority++;
254	return priority;
255	}
256
257	/* return the pic wanted interrupt. return -1 if none */
258	static int pic_get_irq(PPICSTATE pPic)
259	{
260	int mask, cur_priority, priority;
261	Log(("pic_get_irq%d: mask=%x\n", pPic->idxPic, pPic->irr & ~pPic->imr));
262	DumpPICState(pPic, "pic_get_irq");
263
264	mask = pPic->irr & ~pPic->imr;
265	priority = get_priority(pPic, mask);
266	Log(("pic_get_irq: priority=%x\n", priority));
267	if (priority == 8)
268	return -1;
269	/* compute current priority. If special fully nested mode on the
270	master, the IRQ coming from the slave is not taken into account
271	for the priority computation. */
272	mask = pPic->isr;
273	if (pPic->special_mask)
274	mask &= ~pPic->imr;
275	if (pPic->special_fully_nested_mode && pPic->idxPic == 0)
276	mask &= ~(1 << 2);
277	cur_priority = get_priority(pPic, mask);
278	Log(("pic_get_irq%d: cur_priority=%x pending=%d\n", pPic->idxPic,
279	cur_priority, (priority == 8) ? -1 : (priority + pPic->priority_add) & 7));
280	if (priority < cur_priority)
281	{
282	/* higher priority found: an irq should be generated */
283	return (priority + pPic->priority_add) & 7;
284	}
285	return -1;
286	}
287
288	/* raise irq to CPU if necessary. must be called every time the active
289	irq may change */
290	static int pic_update_irq(PPDMDEVINS pDevIns, PDEVPIC pThis, PDEVPICCC pThisCC)
291	{
292	int irq2, irq;
293
294	/* first look at slave pic */
295	irq2 = pic_get_irq(&pThis->aPics[1]);
296	Log(("pic_update_irq irq2=%d\n", irq2));
297	if (irq2 >= 0)
298	{
299	/* if irq request by slave pic, signal master PIC */
300	pic_set_irq1(&pThis->aPics[0], 2, 1, pThis->aPics[1].auTags[irq2]);
301	}
302	else
303	{
304	/* If not, clear the IR on the master PIC. */
305	pic_set_irq1(&pThis->aPics[0], 2, 0, 0 /uTagSrc/);
306	}
307	/* look at requested irq */
308	irq = pic_get_irq(&pThis->aPics[0]);
309	if (irq >= 0)
310	{
311	/* If irq 2 is pending on the master pic, then there must be one pending on the slave pic too! Otherwise we'll get
312	* spurious slave interrupts in picGetInterrupt.
313	*/
314	if (irq != 2 \|\| irq2 != -1)
315	{
316	for (int i = 0; i < 2; i++)
317	Log(("pic%d: imr=%x irr=%x padd=%d\n", i, pThis->aPics[i].imr, pThis->aPics[i].irr, pThis->aPics[i].priority_add));
318	Log(("pic: cpu_interrupt\n"));
319	pThisCC->pPicHlp->pfnSetInterruptFF(pDevIns);
320	}
321	else
322	{
323	STAM_COUNTER_INC(&pThis->StatClearedActiveIRQ2);
324	Log(("pic_update_irq: irq 2 is active, but no interrupt is pending on the slave pic!!\n"));
325	/* Clear it here, so lower priority interrupts can still be dispatched. */
326
327	/* if this was the only pending irq, then we must clear the interrupt ff flag */
328	pThisCC->pPicHlp->pfnClearInterruptFF(pDevIns);
329
330	/** @todo Is this correct? */
331	pThis->aPics[0].irr &= ~(1 << 2);
332
333	/* Call ourselves again just in case other interrupts are pending */
334	return pic_update_irq(pDevIns, pThis, pThisCC);
335	}
336	}
337	else
338	{
339	Log(("pic_update_irq: no interrupt is pending!!\n"));
340
341	/* we must clear the interrupt ff flag */
342	pThisCC->pPicHlp->pfnClearInterruptFF(pDevIns);
343	}
344	return VINF_SUCCESS;
345	}
346
347	/**
348	* Set the an IRQ.
349	*
350	* @param pDevIns Device instance of the PICs.
351	* @param iIrq IRQ number to set.
352	* @param iLevel IRQ level.
353	* @param uTagSrc The IRQ tag and source ID (for tracing).
354	*/
355	static DECLCALLBACK(void) picSetIrq(PPDMDEVINS pDevIns, int iIrq, int iLevel, uint32_t uTagSrc)
356	{
357	PDEVPIC pThis = PDMDEVINS_2_DATA(pDevIns, PDEVPIC);
358	PDEVPICCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PDEVPICCC);
359	AssertMsgReturnVoid(iIrq < 16, ("iIrq=%d\n", iIrq));
360
361	Log(("picSetIrq %d %d\n", iIrq, iLevel));
362	DumpPICState(&pThis->aPics[0], "picSetIrq");
363	DumpPICState(&pThis->aPics[1], "picSetIrq");
364	STAM_COUNTER_INC(&pThis->CTX_SUFF_Z(StatSetIrq));
365	if ((iLevel & PDM_IRQ_LEVEL_FLIP_FLOP) == PDM_IRQ_LEVEL_FLIP_FLOP)
366	{
367	/* A flip-flop lowers the IRQ line and immediately raises it, so
368	* that a rising edge is guaranteed to occur. Note that the IRQ
369	* line must be held high for a while to avoid spurious interrupts.
370	*/
371	pic_set_irq1(&RT_SAFE_SUBSCRIPT(pThis->aPics, iIrq >> 3), iIrq & 7, 0, uTagSrc);
372	pic_update_irq(pDevIns, pThis, pThisCC);
373	}
374	pic_set_irq1(&RT_SAFE_SUBSCRIPT(pThis->aPics, iIrq >> 3), iIrq & 7, iLevel & PDM_IRQ_LEVEL_HIGH, uTagSrc);
375	pic_update_irq(pDevIns, pThis, pThisCC);
376	}
377
378
379	/* acknowledge interrupt 'irq' */
380	DECLINLINE(void) pic_intack(PPICSTATE pPic, int irq)
381	{
382	if (pPic->auto_eoi)
383	{
384	if (pPic->rotate_on_auto_eoi)
385	pPic->priority_add = (irq + 1) & 7;
386	}
387	else
388	pPic->isr \|= (1 << irq);
389
390	/* We don't clear a level sensitive interrupt here */
391	if (!(pPic->elcr & (1 << irq)))
392	{
393	Log2(("pic_intack: irr=%x irrnew=%x\n", pPic->irr, pPic->irr & ~(1 << irq)));
394	pPic->irr &= ~(1 << irq);
395	}
396	}
397
398
399	/**
400	* Get a pending interrupt.
401	*
402	* @returns Pending interrupt number.
403	* @param pDevIns Device instance of the PICs.
404	* @param puTagSrc Where to return the IRQ tag and source ID.
405	*/
406	static DECLCALLBACK(int) picGetInterrupt(PPDMDEVINS pDevIns, uint32_t *puTagSrc)
407	{
408	PDEVPIC pThis = PDMDEVINS_2_DATA(pDevIns, PDEVPIC);
409	PDEVPICCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PDEVPICCC);
410	int irq;
411	int irq2;
412	int intno;
413
414	/* read the irq from the PIC */
415	DumpPICState(&pThis->aPics[0], "picGetInterrupt");
416	DumpPICState(&pThis->aPics[1], "picGetInterrupt");
417
418	irq = pic_get_irq(&pThis->aPics[0]);
419	if (irq >= 0)
420	{
421	pic_intack(&pThis->aPics[0], irq);
422	if (irq == 2)
423	{
424	irq2 = pic_get_irq(&pThis->aPics[1]);
425	if (irq2 >= 0)
426	pic_intack(&pThis->aPics[1], irq2);
427	else
428	{
429	/* Interrupt went away or is now masked. */
430	Log(("picGetInterrupt: spurious IRQ on slave controller, converted to IRQ15\n"));
431	irq2 = 7;
432	}
433	intno = pThis->aPics[1].irq_base + irq2;
434	*puTagSrc = pThis->aPics[0].auTags[irq2];
435	pThis->aPics[0].auTags[irq2] = 0;
436	Log2(("picGetInterrupt1: %x base=%x irq=%x uTagSrc=%#x\n", intno, pThis->aPics[1].irq_base, irq2, *puTagSrc));
437	irq = irq2 + 8;
438	}
439	else
440	{
441	intno = pThis->aPics[0].irq_base + irq;
442	*puTagSrc = pThis->aPics[0].auTags[irq];
443	pThis->aPics[0].auTags[irq] = 0;
444	Log2(("picGetInterrupt0: %x base=%x irq=%x uTagSrc=%#x\n", intno, pThis->aPics[0].irq_base, irq, *puTagSrc));
445	}
446	}
447	else
448	{
449	/* Interrupt went away or is now masked. */
450	Log(("picGetInterrupt: spurious IRQ on master controller, converted to IRQ7\n"));
451	irq = 7;
452	intno = pThis->aPics[0].irq_base + irq;
453	*puTagSrc = 0;
454	}
455	pic_update_irq(pDevIns, pThis, pThisCC);
456
457	Log(("picGetInterrupt: 0x%02x pending 0:%d 1:%d\n", intno, pic_get_irq(&pThis->aPics[0]), pic_get_irq(&pThis->aPics[1])));
458
459	return intno;
460	}
461
462	static void pic_reset(PPICSTATE pPic)
463	{
464	pPic->last_irr = 0;
465	pPic->irr = 0;
466	pPic->imr = 0;
467	pPic->isr = 0;
468	pPic->priority_add = 0;
469	pPic->irq_base = 0;
470	pPic->read_reg_select = 0;
471	pPic->poll = 0;
472	pPic->special_mask = 0;
473	pPic->init_state = 0;
474	pPic->auto_eoi = 0;
475	pPic->rotate_on_auto_eoi = 0;
476	pPic->special_fully_nested_mode = 0;
477	pPic->init4 = 0;
478	//pPic->elcr - not cleared;
479	//pPic->elcr_mask - not cleared;
480	RT_ZERO(pPic->auTags);
481	}
482
483
484	static VBOXSTRICTRC pic_ioport_write(PPDMDEVINS pDevIns, PDEVPIC pThis, PDEVPICCC pThisCC, PPICSTATE pPic,
485	uint32_t addr, uint32_t val)
486	{
487	VBOXSTRICTRC rc = VINF_SUCCESS;
488	int irq;
489
490	Log(("pic_write/%zu: addr=0x%02x val=0x%02x\n", pPic - pThis->aPics, addr, val));
491	addr &= 1;
492	if (addr == 0)
493	{
494	if (val & 0x10)
495	{
496	/* init */
497	pic_reset(pPic);
498	/* deassert a pending interrupt */
499	pThisCC->pPicHlp->pfnClearInterruptFF(pDevIns);
500
501	pPic->init_state = 1;
502	pPic->init4 = val & 1;
503	if (!(val & 0x0a))
504	{ /* likely */ }
505	else if (pThis->cRelLogEntries++ < 64)
506	{
507	if (val & 0x02)
508	LogRel(("PIC: Single mode not supported, ignored.\n"));
509	if (val & 0x08)
510	LogRel(("PIC: Level sensitive IRQ setting ignored.\n"));
511	}
512	}
513	else if (val & 0x08)
514	{
515	if (val & 0x04)
516	pPic->poll = 1;
517	if (val & 0x02)
518	pPic->read_reg_select = val & 1;
519	if (val & 0x40)
520	pPic->special_mask = (val >> 5) & 1;
521	}
522	else
523	{
524	int cmd = val >> 5;
525	switch (cmd)
526	{
527	case 0:
528	case 4:
529	pPic->rotate_on_auto_eoi = cmd >> 2;
530	break;
531	case 1: /* end of interrupt */
532	case 5:
533	{
534	int priority = get_priority(pPic, pPic->isr);
535	if (priority != 8) {
536	irq = (priority + pPic->priority_add) & 7;
537	Log(("pic_write: EOI prio=%d irq=%d\n", priority, irq));
538	pPic->isr &= ~(1 << irq);
539	if (cmd == 5)
540	pPic->priority_add = (irq + 1) & 7;
541	rc = pic_update_irq(pDevIns, pThis, pThisCC);
542	Assert(rc == VINF_SUCCESS);
543	DumpPICState(pPic, "eoi");
544	}
545	break;
546	}
547	case 3:
548	{
549	irq = val & 7;
550	Log(("pic_write: EOI2 for irq %d\n", irq));
551	pPic->isr &= ~(1 << irq);
552	rc = pic_update_irq(pDevIns, pThis, pThisCC);
553	Assert(rc == VINF_SUCCESS);
554	DumpPICState(pPic, "eoi2");
555	break;
556	}
557	case 6:
558	{
559	pPic->priority_add = (val + 1) & 7;
560	Log(("pic_write: lowest priority %d (highest %d)\n", val & 7, pPic->priority_add));
561	rc = pic_update_irq(pDevIns, pThis, pThisCC);
562	Assert(rc == VINF_SUCCESS);
563	break;
564	}
565	case 7:
566	{
567	irq = val & 7;
568	Log(("pic_write: EOI3 for irq %d\n", irq));
569	pPic->isr &= ~(1 << irq);
570	pPic->priority_add = (irq + 1) & 7;
571	rc = pic_update_irq(pDevIns, pThis, pThisCC);
572	Assert(rc == VINF_SUCCESS);
573	DumpPICState(pPic, "eoi3");
574	break;
575	}
576	default:
577	/* no operation */
578	break;
579	}
580	}
581	}
582	else
583	{
584	switch (pPic->init_state)
585	{
586	case 0:
587	/* normal mode */
588	pPic->imr = val;
589	rc = pic_update_irq(pDevIns, pThis, pThisCC);
590	Assert(rc == VINF_SUCCESS);
591	break;
592	case 1:
593	pPic->irq_base = val & 0xf8;
594	pPic->init_state = 2;
595	Log(("pic_write: set irq base to %x\n", pPic->irq_base));
596	break;
597	case 2:
598	if (pPic->init4)
599	pPic->init_state = 3;
600	else
601	pPic->init_state = 0;
602	break;
603	case 3:
604	pPic->special_fully_nested_mode = (val >> 4) & 1;
605	pPic->auto_eoi = (val >> 1) & 1;
606	pPic->init_state = 0;
607	Log(("pic_write: special_fully_nested_mode=%d auto_eoi=%d\n", pPic->special_fully_nested_mode, pPic->auto_eoi));
608	break;
609	}
610	}
611	return rc;
612	}
613
614
615	static uint32_t pic_poll_read(PPDMDEVINS pDevIns, PDEVPIC pThis, PDEVPICCC pThisCC, PPICSTATE pPic, uint32_t addr1)
616	{
617	int ret = pic_get_irq(pPic);
618	if (ret >= 0)
619	{
620	if (addr1 >> 7)
621	{
622	Log2(("pic_poll_read: clear slave irq (isr)\n"));
623	pThis->aPics[0].isr &= ~(1 << 2);
624	pThis->aPics[0].irr &= ~(1 << 2);
625	}
626	Log2(("pic_poll_read: clear irq %d (isr)\n", ret));
627	pPic->irr &= ~(1 << ret);
628	pPic->isr &= ~(1 << ret);
629	if (addr1 >> 7 \|\| ret != 2)
630	pic_update_irq(pDevIns, pThis, pThisCC);
631	}
632	else
633	{
634	ret = 0;
635	pic_update_irq(pDevIns, pThis, pThisCC);
636	}
637
638	return ret;
639	}
640
641
642	static uint32_t pic_ioport_read(PPDMDEVINS pDevIns, PDEVPIC pThis, PDEVPICCC pThisCC, PPICSTATE pPic, uint32_t addr1, int *pRC)
643	{
644	unsigned int addr;
645	int ret;
646
647	*pRC = VINF_SUCCESS;
648
649	addr = addr1;
650	addr &= 1;
651	if (pPic->poll)
652	{
653	ret = pic_poll_read(pDevIns, pThis, pThisCC, pPic, addr1);
654	pPic->poll = 0;
655	}
656	else
657	{
658	if (addr == 0)
659	{
660	if (pPic->read_reg_select)
661	ret = pPic->isr;
662	else
663	ret = pPic->irr;
664	}
665	else
666	ret = pPic->imr;
667	}
668	Log(("pic_read: addr=0x%02x val=0x%02x\n", addr1, ret));
669	return ret;
670	}
671
672
673
674	/* -=-=-=-=-=- I/O ports -=-=-=-=-=- */
675
676	/**
677	* @callback_method_impl{FNIOMIOPORTNEWIN}
678	*/
679	static DECLCALLBACK(VBOXSTRICTRC) picIOPortRead(PPDMDEVINS pDevIns, void pvUser, RTIOPORT offPort, uint32_t pu32, unsigned cb)
680	{
681	PDEVPIC pThis = PDMDEVINS_2_DATA(pDevIns, PDEVPIC);
682	PDEVPICCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PDEVPICCC);
683	uint32_t iPic = (uint32_t)(uintptr_t)pvUser;
684
685	Assert(iPic == 0 \|\| iPic == 1);
686	if (cb == 1)
687	{
688	int rc;
689	PIC_LOCK_RET(pDevIns, pThisCC, VINF_IOM_R3_IOPORT_READ);
690	*pu32 = pic_ioport_read(pDevIns, pThis, pThisCC, &RT_SAFE_SUBSCRIPT(pThis->aPics, iPic), offPort, &rc);
691	PIC_UNLOCK(pDevIns, pThisCC);
692	return rc;
693	}
694	return VERR_IOM_IOPORT_UNUSED;
695	}
696
697
698	/**
699	* @callback_method_impl{FNIOMIOPORTNEWOUT}
700	*/
701	static DECLCALLBACK(VBOXSTRICTRC) picIOPortWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT offPort, uint32_t u32, unsigned cb)
702	{
703	PDEVPIC pThis = PDMDEVINS_2_DATA(pDevIns, PDEVPIC);
704	PDEVPICCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PDEVPICCC);
705	uint32_t iPic = (uint32_t)(uintptr_t)pvUser;
706
707	Assert(iPic == 0 \|\| iPic == 1);
708
709	if (cb == 1)
710	{
711	VBOXSTRICTRC rc;
712	PIC_LOCK_RET(pDevIns, pThisCC, VINF_IOM_R3_IOPORT_WRITE);
713	rc = pic_ioport_write(pDevIns, pThis, pThisCC, &RT_SAFE_SUBSCRIPT(pThis->aPics, iPic), offPort, u32);
714	PIC_UNLOCK(pDevIns, pThisCC);
715	return rc;
716	}
717	return VINF_SUCCESS;
718	}
719
720
721	/**
722	* @callback_method_impl{FNIOMIOPORTNEWIN, ELCR}
723	*/
724	static DECLCALLBACK(VBOXSTRICTRC) picIOPortElcrRead(PPDMDEVINS pDevIns, void pvUser, RTIOPORT offPort, uint32_t pu32, unsigned cb)
725	{
726	if (cb == 1)
727	{
728	PDEVPICCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PDEVPICCC);
729	PPICSTATE pPic = (PPICSTATE)pvUser;
730	PIC_LOCK_RET(pDevIns, pThisCC, VINF_IOM_R3_IOPORT_READ);
731	*pu32 = pPic->elcr;
732	PIC_UNLOCK(pDevIns, pThisCC);
733	return VINF_SUCCESS;
734	}
735	RT_NOREF(offPort);
736	return VERR_IOM_IOPORT_UNUSED;
737	}
738
739
740	/**
741	* @callback_method_impl{FNIOMIOPORTNEWOUT, ELCR}
742	*/
743	static DECLCALLBACK(VBOXSTRICTRC) picIOPortElcrWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT offPort, uint32_t u32, unsigned cb)
744	{
745	if (cb == 1)
746	{
747	PDEVPICCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PDEVPICCC);
748	PPICSTATE pPic = (PPICSTATE)pvUser;
749	PIC_LOCK_RET(pDevIns, pThisCC, VINF_IOM_R3_IOPORT_WRITE);
750	pPic->elcr = u32 & pPic->elcr_mask;
751	PIC_UNLOCK(pDevIns, pThisCC);
752	}
753	RT_NOREF(offPort);
754	return VINF_SUCCESS;
755	}
756
757
758	#ifdef IN_RING3
759
760	/**
761	* @callback_method_impl{FNDBGFHANDLERDEV}
762	*/
763	static DECLCALLBACK(void) picR3Info(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
764	{
765	PDEVPIC pThis = PDMDEVINS_2_DATA(pDevIns, PDEVPIC);
766	NOREF(pszArgs);
767
768	/*
769	* Show info.
770	*/
771	for (unsigned i = 0; i < RT_ELEMENTS(pThis->aPics); i++)
772	{
773	PPICSTATE pPic = &pThis->aPics[i];
774
775	pHlp->pfnPrintf(pHlp, "PIC%d:\n", i);
776	pHlp->pfnPrintf(pHlp, " IMR :%02x ISR :%02x IRR :%02x LIRR:%02x\n",
777	pPic->imr, pPic->isr, pPic->irr, pPic->last_irr);
778	pHlp->pfnPrintf(pHlp, " Base:%02x PriAdd:%02x RegSel:%02x\n",
779	pPic->irq_base, pPic->priority_add, pPic->read_reg_select);
780	pHlp->pfnPrintf(pHlp, " Poll:%02x SpMask:%02x IState:%02x\n",
781	pPic->poll, pPic->special_mask, pPic->init_state);
782	pHlp->pfnPrintf(pHlp, " AEOI:%02x Rotate:%02x FNest :%02x Ini4:%02x\n",
783	pPic->auto_eoi, pPic->rotate_on_auto_eoi,
784	pPic->special_fully_nested_mode, pPic->init4);
785	pHlp->pfnPrintf(pHlp, " ELCR:%02x ELMask:%02x\n", pPic->elcr, pPic->elcr_mask);
786	}
787	}
788
789
790	/* -=-=-=-=-=- Saved State -=-=-=-=-=- */
791
792	/**
793	* @callback_method_impl{FNSSMDEVSAVEEXEC}
794	*/
795	static DECLCALLBACK(int) picR3SaveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
796	{
797	PDEVPIC pThis = PDMDEVINS_2_DATA(pDevIns, PDEVPIC);
798	PCPDMDEVHLPR3 pHlp = pDevIns->pHlpR3;
799
800	for (unsigned i = 0; i < RT_ELEMENTS(pThis->aPics); i++)
801	{
802	pHlp->pfnSSMPutU8(pSSM, pThis->aPics[i].last_irr);
803	pHlp->pfnSSMPutU8(pSSM, pThis->aPics[i].irr);
804	pHlp->pfnSSMPutU8(pSSM, pThis->aPics[i].imr);
805	pHlp->pfnSSMPutU8(pSSM, pThis->aPics[i].isr);
806	pHlp->pfnSSMPutU8(pSSM, pThis->aPics[i].priority_add);
807	pHlp->pfnSSMPutU8(pSSM, pThis->aPics[i].irq_base);
808	pHlp->pfnSSMPutU8(pSSM, pThis->aPics[i].read_reg_select);
809	pHlp->pfnSSMPutU8(pSSM, pThis->aPics[i].poll);
810	pHlp->pfnSSMPutU8(pSSM, pThis->aPics[i].special_mask);
811	pHlp->pfnSSMPutU8(pSSM, pThis->aPics[i].init_state);
812	pHlp->pfnSSMPutU8(pSSM, pThis->aPics[i].auto_eoi);
813	pHlp->pfnSSMPutU8(pSSM, pThis->aPics[i].rotate_on_auto_eoi);
814	pHlp->pfnSSMPutU8(pSSM, pThis->aPics[i].special_fully_nested_mode);
815	pHlp->pfnSSMPutU8(pSSM, pThis->aPics[i].init4);
816	pHlp->pfnSSMPutU8(pSSM, pThis->aPics[i].elcr);
817	}
818	return VINF_SUCCESS;
819	}
820
821
822	/**
823	* @callback_method_impl{FNSSMDEVLOADEXEC}
824	*/
825	static DECLCALLBACK(int) picR3LoadExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
826	{
827	PDEVPIC pThis = PDMDEVINS_2_DATA(pDevIns, PDEVPIC);
828	PCPDMDEVHLPR3 pHlp = pDevIns->pHlpR3;
829
830	if (uVersion != 1)
831	return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
832	Assert(uPass == SSM_PASS_FINAL); NOREF(uPass);
833
834	for (unsigned i = 0; i < RT_ELEMENTS(pThis->aPics); i++)
835	{
836	pHlp->pfnSSMGetU8(pSSM, &pThis->aPics[i].last_irr);
837	pHlp->pfnSSMGetU8(pSSM, &pThis->aPics[i].irr);
838	pHlp->pfnSSMGetU8(pSSM, &pThis->aPics[i].imr);
839	pHlp->pfnSSMGetU8(pSSM, &pThis->aPics[i].isr);
840	pHlp->pfnSSMGetU8(pSSM, &pThis->aPics[i].priority_add);
841	pHlp->pfnSSMGetU8(pSSM, &pThis->aPics[i].irq_base);
842	pHlp->pfnSSMGetU8(pSSM, &pThis->aPics[i].read_reg_select);
843	pHlp->pfnSSMGetU8(pSSM, &pThis->aPics[i].poll);
844	pHlp->pfnSSMGetU8(pSSM, &pThis->aPics[i].special_mask);
845	pHlp->pfnSSMGetU8(pSSM, &pThis->aPics[i].init_state);
846	pHlp->pfnSSMGetU8(pSSM, &pThis->aPics[i].auto_eoi);
847	pHlp->pfnSSMGetU8(pSSM, &pThis->aPics[i].rotate_on_auto_eoi);
848	pHlp->pfnSSMGetU8(pSSM, &pThis->aPics[i].special_fully_nested_mode);
849	pHlp->pfnSSMGetU8(pSSM, &pThis->aPics[i].init4);
850	pHlp->pfnSSMGetU8(pSSM, &pThis->aPics[i].elcr);
851	}
852
853	/* Note! PDM will restore the VMCPU_FF_INTERRUPT_PIC state. */
854	return VINF_SUCCESS;
855	}
856
857
858	/* -=-=-=-=-=- PDMDEVREG -=-=-=-=-=- */
859
860	/**
861	* @interface_method_impl{PDMDEVREG,pfnReset}
862	*/
863	static DECLCALLBACK(void) picR3Reset(PPDMDEVINS pDevIns)
864	{
865	PDEVPIC pThis = PDMDEVINS_2_DATA(pDevIns, PDEVPIC);
866	PDEVPICCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PDEVPICCC);
867	unsigned i;
868	LogFlow(("picR3Reset:\n"));
869	pThisCC->pPicHlp->pfnLock(pDevIns, VERR_INTERNAL_ERROR);
870
871	for (i = 0; i < RT_ELEMENTS(pThis->aPics); i++)
872	pic_reset(&pThis->aPics[i]);
873
874	PIC_UNLOCK(pDevIns, pThisCC);
875	}
876
877
878	/**
879	* @interface_method_impl{PDMDEVREG,pfnRelocate}
880	*/
881	static DECLCALLBACK(void) picR3Relocate(PPDMDEVINS pDevIns, RTGCINTPTR offDelta)
882	{
883	PDEVPICRC pThisRC = PDMINS_2_DATA_RC(pDevIns, PDEVPICRC);
884	pThisRC->pPicHlp += offDelta;
885	}
886
887
888	/**
889	* @interface_method_impl{PDMDEVREG,pfnConstruct}
890	*/
891	static DECLCALLBACK(int) picR3Construct(PPDMDEVINS pDevIns, int iInstance, PCFGMNODE pCfg)
892	{
893	PDMDEV_CHECK_VERSIONS_RETURN(pDevIns);
894	PDEVPIC pThis = PDMDEVINS_2_DATA(pDevIns, PDEVPIC);
895	PDEVPICCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PDEVPICCC);
896	int rc;
897	RT_NOREF(iInstance, pCfg);
898
899	Assert(iInstance == 0);
900
901	/*
902	* Validate and read configuration.
903	*/
904	PDMDEV_VALIDATE_CONFIG_RETURN(pDevIns, "", "");
905	Log(("DevPIC: fRCEnabled=%RTbool fR0Enabled=%RTbool\n", pDevIns->fRCEnabled, pDevIns->fR0Enabled));
906
907	/*
908	* Init the data.
909	*/
910	Assert(RT_ELEMENTS(pThis->aPics) == 2);
911	pThis->aPics[0].elcr_mask = 0xf8;
912	pThis->aPics[1].elcr_mask = 0xde;
913	pThis->aPics[0].idxPic = 0;
914	pThis->aPics[1].idxPic = 1;
915	pThis->cRelLogEntries = 0;
916
917	/*
918	* Register us as the PIC with PDM.
919	*/
920	PDMPICREG PicReg;
921	PicReg.u32Version = PDM_PICREG_VERSION;
922	PicReg.pfnSetIrq = picSetIrq;
923	PicReg.pfnGetInterrupt = picGetInterrupt;
924	PicReg.u32TheEnd = PDM_PICREG_VERSION;
925	rc = PDMDevHlpPICRegister(pDevIns, &PicReg, &pThisCC->pPicHlp);
926	AssertLogRelMsgRCReturn(rc, ("PDMDevHlpPICRegister -> %Rrc\n", rc), rc);
927	AssertReturn(pThisCC->pPicHlp->u32Version == PDM_PICHLP_VERSION, VERR_VERSION_MISMATCH);
928	AssertReturn(pThisCC->pPicHlp->u32TheEnd == PDM_PICHLP_VERSION, VERR_VERSION_MISMATCH);
929
930	/*
931	* Since the PIC helper interface provides access to the PDM lock,
932	* we need no device level critical section.
933	*/
934	rc = PDMDevHlpSetDeviceCritSect(pDevIns, PDMDevHlpCritSectGetNop(pDevIns));
935	AssertRCReturn(rc, rc);
936
937	/*
938	* Register I/O ports and save state.
939	*/
940	rc = PDMDevHlpIoPortCreateUAndMap(pDevIns, 0x20 /uPort/, 2 /cPorts/, picIOPortWrite, picIOPortRead, (void *)0,
941	"i8259 PIC #0", NULL /paExtDesc/, &pThis->aPics[0].hIoPorts0);
942	AssertRCReturn(rc, rc);
943	rc = PDMDevHlpIoPortCreateUAndMap(pDevIns, 0xa0 /uPort/, 2 /cPorts/, picIOPortWrite, picIOPortRead, (void *)1,
944	"i8259 PIC #1", NULL /paExtDesc/, &pThis->aPics[1].hIoPorts0);
945	AssertRCReturn(rc, rc);
946
947
948	rc = PDMDevHlpIoPortCreateUAndMap(pDevIns, 0x4d0 /uPort/, 1 /cPorts/, picIOPortElcrWrite, picIOPortElcrRead,
949	&pThis->aPics[0], "i8259 PIC #0 - elcr", NULL /paExtDesc/, &pThis->aPics[0].hIoPorts1);
950	AssertRCReturn(rc, rc);
951	rc = PDMDevHlpIoPortCreateUAndMap(pDevIns, 0x4d1 /uPort/, 1 /cPorts/, picIOPortElcrWrite, picIOPortElcrRead,
952	&pThis->aPics[1], "i8259 PIC #1 - elcr", NULL /paExtDesc/, &pThis->aPics[1].hIoPorts1);
953	AssertRCReturn(rc, rc);
954
955	/*
956	* Saved state.
957	*/
958	rc = PDMDevHlpSSMRegister(pDevIns, 1 /* uVersion /, sizeof(pThis), picR3SaveExec, picR3LoadExec);
959	AssertRCReturn(rc, rc);
960
961	/*
962	* Register the info item.
963	*/
964	PDMDevHlpDBGFInfoRegister(pDevIns, "pic", "PIC info.", picR3Info);
965
966	/*
967	* Initialize the device state.
968	*/
969	picR3Reset(pDevIns);
970
971	# ifdef VBOX_WITH_STATISTICS
972	/*
973	* Statistics.
974	*/
975	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatSetIrqRZ, STAMTYPE_COUNTER, "SetIrqRZ", STAMUNIT_OCCURENCES, "Number of PIC SetIrq calls in ring-0/raw-mode.");
976	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatSetIrqR3, STAMTYPE_COUNTER, "SetIrqR3", STAMUNIT_OCCURENCES, "Number of PIC SetIrq calls in ring-3.");
977
978	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatClearedActiveIRQ2, STAMTYPE_COUNTER, "Masked/ActiveIRQ2", STAMUNIT_OCCURENCES, "Number of cleared irq 2.");
979	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatClearedActiveMasterIRQ, STAMTYPE_COUNTER, "Masked/ActiveMaster", STAMUNIT_OCCURENCES, "Number of cleared master irqs.");
980	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatClearedActiveSlaveIRQ, STAMTYPE_COUNTER, "Masked/ActiveSlave", STAMUNIT_OCCURENCES, "Number of cleared slave irqs.");
981	# endif
982
983	return VINF_SUCCESS;
984	}
985
986	#else /* !IN_RING3 */
987
988	/**
989	* @callback_method_impl{PDMDEVREGR0,pfnConstruct}
990	*/
991	static DECLCALLBACK(int) picRZConstruct(PPDMDEVINS pDevIns)
992	{
993	PDMDEV_CHECK_VERSIONS_RETURN(pDevIns);
994	PDEVPIC pThis = PDMDEVINS_2_DATA(pDevIns, PDEVPIC);
995	PDEVPICCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PDEVPICCC);
996
997	/* NOP the critsect: */
998	int rc = PDMDevHlpSetDeviceCritSect(pDevIns, PDMDevHlpCritSectGetNop(pDevIns));
999	AssertRCReturn(rc, rc);
1000
1001	/* Set up the PIC callbacks: */
1002	PDMPICREG PicReg;
1003	PicReg.u32Version = PDM_PICREG_VERSION;
1004	PicReg.pfnSetIrq = picSetIrq;
1005	PicReg.pfnGetInterrupt = picGetInterrupt;
1006	PicReg.u32TheEnd = PDM_PICREG_VERSION;
1007	rc = PDMDevHlpPICSetUpContext(pDevIns, &PicReg, &pThisCC->pPicHlp);
1008	AssertLogRelMsgRCReturn(rc, ("PDMDevHlpPICSetUpContext -> %Rrc\n", rc), rc);
1009	AssertPtrReturn(pThisCC->pPicHlp, VERR_INTERNAL_ERROR_3);
1010	AssertReturn(pThisCC->pPicHlp->u32Version == PDM_PICHLP_VERSION, VERR_VERSION_MISMATCH);
1011	AssertReturn(pThisCC->pPicHlp->u32TheEnd == PDM_PICHLP_VERSION, VERR_VERSION_MISMATCH);
1012
1013	/* I/O port callbacks: */
1014	Assert(RT_ELEMENTS(pThis->aPics) == 2);
1015	rc = PDMDevHlpIoPortSetUpContext(pDevIns, pThis->aPics[0].hIoPorts0, picIOPortWrite, picIOPortRead, (void *)0);
1016	AssertRCReturn(rc, rc);
1017	rc = PDMDevHlpIoPortSetUpContext(pDevIns, pThis->aPics[1].hIoPorts0, picIOPortWrite, picIOPortRead, (void *)1);
1018	AssertRCReturn(rc, rc);
1019
1020	rc = PDMDevHlpIoPortSetUpContext(pDevIns, pThis->aPics[0].hIoPorts1, picIOPortElcrWrite, picIOPortElcrRead, &pThis->aPics[0]);
1021	AssertRCReturn(rc, rc);
1022	rc = PDMDevHlpIoPortSetUpContext(pDevIns, pThis->aPics[1].hIoPorts1, picIOPortElcrWrite, picIOPortElcrRead, &pThis->aPics[1]);
1023	AssertRCReturn(rc, rc);
1024
1025	return VINF_SUCCESS;
1026	}
1027
1028	#endif /* !IN_RING3 */
1029
1030	/**
1031	* The device registration structure.
1032	*/
1033	const PDMDEVREG g_DeviceI8259 =
1034	{
1035	/* .u32Version = */ PDM_DEVREG_VERSION,
1036	/* .uReserved0 = */ 0,
1037	/* .szName = */ "i8259",
1038	/* .fFlags = */ PDM_DEVREG_FLAGS_DEFAULT_BITS \| PDM_DEVREG_FLAGS_RZ \| PDM_DEVREG_FLAGS_NEW_STYLE
1039	\| PDM_DEVREG_FLAGS_REQUIRE_R0 \| PDM_DEVREG_FLAGS_REQUIRE_RC,
1040	/* .fClass = */ PDM_DEVREG_CLASS_PIC,
1041	/* .cMaxInstances = */ 1,
1042	/* .uSharedVersion = */ 42,
1043	/* .cbInstanceShared = */ sizeof(DEVPIC),
1044	/* .cbInstanceCC = */ sizeof(DEVPICCC),
1045	/* .cbInstanceRC = */ sizeof(DEVPICRC),
1046	/* .cMaxPciDevices = */ 0,
1047	/* .cMaxMsixVectors = */ 0,
1048	/* .pszDescription = */ "Intel 8259 Programmable Interrupt Controller (PIC) Device.",
1049	#if defined(IN_RING3)
1050	/* .pszRCMod = */ "VBoxDDRC.rc",
1051	/* .pszR0Mod = */ "VBoxDDR0.r0",
1052	/* .pfnConstruct = */ picR3Construct,
1053	/* .pfnDestruct = */ NULL,
1054	/* .pfnRelocate = */ picR3Relocate,
1055	/* .pfnMemSetup = */ NULL,
1056	/* .pfnPowerOn = */ NULL,
1057	/* .pfnReset = */ picR3Reset,
1058	/* .pfnSuspend = */ NULL,
1059	/* .pfnResume = */ NULL,
1060	/* .pfnAttach = */ NULL,
1061	/* .pfnDetach = */ NULL,
1062	/* .pfnQueryInterface = */ NULL,
1063	/* .pfnInitComplete = */ NULL,
1064	/* .pfnPowerOff = */ NULL,
1065	/* .pfnSoftReset = */ NULL,
1066	/* .pfnReserved0 = */ NULL,
1067	/* .pfnReserved1 = */ NULL,
1068	/* .pfnReserved2 = */ NULL,
1069	/* .pfnReserved3 = */ NULL,
1070	/* .pfnReserved4 = */ NULL,
1071	/* .pfnReserved5 = */ NULL,
1072	/* .pfnReserved6 = */ NULL,
1073	/* .pfnReserved7 = */ NULL,
1074	#elif defined(IN_RING0)
1075	/* .pfnEarlyConstruct = */ NULL,
1076	/* .pfnConstruct = */ picRZConstruct,
1077	/* .pfnDestruct = */ NULL,
1078	/* .pfnFinalDestruct = */ NULL,
1079	/* .pfnRequest = */ NULL,
1080	/* .pfnReserved0 = */ NULL,
1081	/* .pfnReserved1 = */ NULL,
1082	/* .pfnReserved2 = */ NULL,
1083	/* .pfnReserved3 = */ NULL,
1084	/* .pfnReserved4 = */ NULL,
1085	/* .pfnReserved5 = */ NULL,
1086	/* .pfnReserved6 = */ NULL,
1087	/* .pfnReserved7 = */ NULL,
1088	#elif defined(IN_RC)
1089	/* .pfnConstruct = */ picRZConstruct,
1090	/* .pfnReserved0 = */ NULL,
1091	/* .pfnReserved1 = */ NULL,
1092	/* .pfnReserved2 = */ NULL,
1093	/* .pfnReserved3 = */ NULL,
1094	/* .pfnReserved4 = */ NULL,
1095	/* .pfnReserved5 = */ NULL,
1096	/* .pfnReserved6 = */ NULL,
1097	/* .pfnReserved7 = */ NULL,
1098	#else
1099	# error "Not in IN_RING3, IN_RING0 or IN_RC!"
1100	#endif
1101	/* .u32VersionEnd = */ PDM_DEVREG_VERSION
1102	};
1103
1104	#endif /* !VBOX_DEVICE_STRUCT_TESTCASE */
1105

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source: vbox/trunk/src/VBox/Devices/PC/DevPIC.cpp@ 91942

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