VirtualBox

source: vbox/trunk/src/VBox/Devices/PC/DevPIC.cpp@ 78208

Last change on this file since 78208 was 78208, checked in by vboxsync, 6 years ago

PDM,APIC,PIC: Don't use AssertRelease on VMCPU_FF_INTERRUPT_PIC, VMCPU_FF_INTERRUPT_APIC and friends during restore. Instead added debug assertions in the relevant functions causing these to be set by misbehaving device state loaders. ticketref:18331 ticketref:18265
  • Property svn:eol-style set to native
  • Property svn:keywords set to Id Revision
File size: 35.5 KB
Line 
1/* $Id: DevPIC.cpp 78208 2019-04-18 15:54:40Z vboxsync $ */
2/** @file
3 * DevPIC - Intel 8259 Programmable Interrupt Controller (PIC) Device.
4 */
5
6/*
7 * Copyright (C) 2006-2019 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 * -------------------------------------------------------------------
17 *
18 * This code is based on:
19 *
20 * QEMU 8259 interrupt controller emulation
21 *
22 * Copyright (c) 2003-2004 Fabrice Bellard
23 *
24 * Permission is hereby granted, free of charge, to any person obtaining a copy
25 * of this software and associated documentation files (the "Software"), to deal
26 * in the Software without restriction, including without limitation the rights
27 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
28 * copies of the Software, and to permit persons to whom the Software is
29 * furnished to do so, subject to the following conditions:
30 *
31 * The above copyright notice and this permission notice shall be included in
32 * all copies or substantial portions of the Software.
33 *
34 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
35 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
36 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
37 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
38 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
39 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
40 * THE SOFTWARE.
41 *
42 */
43
44
45/*********************************************************************************************************************************
46* Header Files *
47*********************************************************************************************************************************/
48#define LOG_GROUP LOG_GROUP_DEV_PIC
49#include <VBox/vmm/pdmdev.h>
50#include <VBox/log.h>
51#include <iprt/assert.h>
52#include <iprt/string.h>
53
54#include "VBoxDD.h"
55
56
57/*********************************************************************************************************************************
58* Defined Constants And Macros *
59*********************************************************************************************************************************/
60/** @def PIC_LOCK
61 * Acquires the PDM lock. This is a NOP if locking is disabled. */
62/** @def PIC_UNLOCK
63 * Releases the PDM lock. This is a NOP if locking is disabled. */
64#define PIC_LOCK(pThis, rc) \
65 do { \
66 int rc2 = (pThis)->CTX_SUFF(pPicHlp)->pfnLock((pThis)->CTX_SUFF(pDevIns), rc); \
67 if (rc2 != VINF_SUCCESS) \
68 return rc2; \
69 } while (0)
70#define PIC_UNLOCK(pThis) \
71 (pThis)->CTX_SUFF(pPicHlp)->pfnUnlock((pThis)->CTX_SUFF(pDevIns))
72
73
74/* debug PIC */
75#define DEBUG_PIC
76
77/*#define DEBUG_IRQ_COUNT*/
78
79/**
80 * The instance data of one (1) PIC.
81 */
82typedef struct PICSTATE
83{
84 uint8_t last_irr; /**< edge detection */
85 uint8_t irr; /**< interrupt request register */
86 uint8_t imr; /**< interrupt mask register */
87 uint8_t isr; /**< interrupt service register */
88 uint8_t priority_add; /**< highest irq priority */
89 uint8_t irq_base;
90 uint8_t read_reg_select;
91 uint8_t poll;
92 uint8_t special_mask;
93 uint8_t init_state;
94 uint8_t auto_eoi;
95 uint8_t rotate_on_auto_eoi;
96 uint8_t special_fully_nested_mode;
97 uint8_t init4; /**< true if 4 byte init */
98 uint8_t elcr; /**< PIIX edge/trigger selection*/
99 uint8_t elcr_mask;
100 /** Pointer to the device instance, R3 Ptr. */
101 PPDMDEVINSR3 pDevInsR3;
102 /** Pointer to the device instance, R0 Ptr. */
103 PPDMDEVINSR0 pDevInsR0;
104 /** Pointer to the device instance, RC Ptr. */
105 PPDMDEVINSRC pDevInsRC;
106 /** The PIC index (0 or 1). */
107 uint8_t idxPic;
108 uint8_t abAlignment0[3]; /**< Alignment padding. */
109 /** The IRQ tags and source IDs for each (tracing purposes). */
110 uint32_t auTags[8];
111} PICSTATE;
112/** Pointer to the state of one PIC. */
113typedef PICSTATE *PPICSTATE;
114
115
116/**
117 * The whole PIC device instance data.
118 */
119typedef struct DEVPIC
120{
121 /** The two interrupt controllers. */
122 PICSTATE aPics[2];
123 /** Pointer to the device instance - R3 Ptr. */
124 PPDMDEVINSR3 pDevInsR3;
125 /** Pointer to the PIC R3 helpers. */
126 PCPDMPICHLPR3 pPicHlpR3;
127 /** Pointer to the device instance - R0 Ptr. */
128 PPDMDEVINSR0 pDevInsR0;
129 /** Pointer to the PIC R0 helpers. */
130 PCPDMPICHLPR0 pPicHlpR0;
131 /** Pointer to the device instance - RC Ptr. */
132 PPDMDEVINSRC pDevInsRC;
133 /** Pointer to the PIC RC helpers. */
134 PCPDMPICHLPRC pPicHlpRC;
135 /** Number of release log entries. Used to prevent flooding. */
136 uint32_t cRelLogEntries;
137 uint32_t u32AlignmentPadding;
138#ifdef VBOX_WITH_STATISTICS
139 STAMCOUNTER StatSetIrqGC;
140 STAMCOUNTER StatSetIrqHC;
141 STAMCOUNTER StatClearedActiveIRQ2;
142 STAMCOUNTER StatClearedActiveMasterIRQ;
143 STAMCOUNTER StatClearedActiveSlaveIRQ;
144#endif
145} DEVPIC;
146/** Pointer to the whole PIC instance data. */
147typedef DEVPIC *PDEVPIC;
148
149
150#ifndef VBOX_DEVICE_STRUCT_TESTCASE
151#ifdef LOG_ENABLED
152DECLINLINE(void) DumpPICState(PPICSTATE pPic, const char *pszFn)
153{
154 PDEVPIC pThis = PDMINS_2_DATA(pPic->CTX_SUFF(pDevIns), PDEVPIC);
155
156 Log2(("%s: pic%d: elcr=%x last_irr=%x irr=%x imr=%x isr=%x irq_base=%x\n",
157 pszFn, (&pThis->aPics[0] == pPic) ? 0 : 1,
158 pPic->elcr, pPic->last_irr, pPic->irr, pPic->imr, pPic->isr, pPic->irq_base));
159}
160#else
161# define DumpPICState(pThis, szFn) do { } while (0)
162#endif
163
164/* set irq level. If an edge is detected, then the IRR is set to 1 */
165DECLINLINE(void) pic_set_irq1(PPICSTATE pPic, int irq, int level, uint32_t uTagSrc)
166{
167 Log(("pic_set_irq1: irq=%d level=%d\n", irq, level));
168 int mask = 1 << irq;
169 if (pPic->elcr & mask)
170 {
171 /* level triggered */
172 if (level)
173 {
174 Log2(("pic_set_irq1(ls) irr=%d irrnew=%d\n", pPic->irr, pPic->irr | mask));
175 pPic->irr |= mask;
176 pPic->last_irr |= mask;
177 }
178 else
179 {
180 Log2(("pic_set_irq1(lc) irr=%d irrnew=%d\n", pPic->irr, pPic->irr & ~mask));
181 pPic->irr &= ~mask;
182 pPic->last_irr &= ~mask;
183 }
184 }
185 else
186 {
187 /* edge triggered */
188 if (level)
189 {
190 if ((pPic->last_irr & mask) == 0)
191 {
192 Log2(("pic_set_irq1 irr=%x last_irr=%x\n", pPic->irr | mask, pPic->last_irr));
193 pPic->irr |= mask;
194 }
195 pPic->last_irr |= mask;
196 }
197 else
198 {
199 pPic->irr &= ~mask;
200 pPic->last_irr &= ~mask;
201 }
202 }
203
204 /* Save the tag. */
205 if (level)
206 {
207 if (!pPic->auTags[irq])
208 pPic->auTags[irq] = uTagSrc;
209 else
210 pPic->auTags[irq] |= RT_BIT_32(31);
211 }
212
213 DumpPICState(pPic, "pic_set_irq1");
214}
215
216/* return the highest priority found in mask (highest = smallest
217 number). Return 8 if no irq */
218DECLINLINE(int) get_priority(PPICSTATE pPic, int mask)
219{
220 int priority;
221 if (mask == 0)
222 return 8;
223 priority = 0;
224 while ((mask & (1 << ((priority + pPic->priority_add) & 7))) == 0)
225 priority++;
226 return priority;
227}
228
229/* return the pic wanted interrupt. return -1 if none */
230static int pic_get_irq(PPICSTATE pPic)
231{
232 int mask, cur_priority, priority;
233 Log(("pic_get_irq%d: mask=%x\n", pPic->idxPic, pPic->irr & ~pPic->imr));
234 DumpPICState(pPic, "pic_get_irq");
235
236 mask = pPic->irr & ~pPic->imr;
237 priority = get_priority(pPic, mask);
238 Log(("pic_get_irq: priority=%x\n", priority));
239 if (priority == 8)
240 return -1;
241 /* compute current priority. If special fully nested mode on the
242 master, the IRQ coming from the slave is not taken into account
243 for the priority computation. */
244 mask = pPic->isr;
245 if (pPic->special_mask)
246 mask &= ~pPic->imr;
247 if (pPic->special_fully_nested_mode && pPic->idxPic == 0)
248 mask &= ~(1 << 2);
249 cur_priority = get_priority(pPic, mask);
250 Log(("pic_get_irq%d: cur_priority=%x pending=%d\n", pPic->idxPic,
251 cur_priority, (priority == 8) ? -1 : (priority + pPic->priority_add) & 7));
252 if (priority < cur_priority)
253 {
254 /* higher priority found: an irq should be generated */
255 return (priority + pPic->priority_add) & 7;
256 }
257 return -1;
258}
259
260/* raise irq to CPU if necessary. must be called every time the active
261 irq may change */
262static int pic_update_irq(PDEVPIC pThis)
263{
264 int irq2, irq;
265
266 /* first look at slave pic */
267 irq2 = pic_get_irq(&pThis->aPics[1]);
268 Log(("pic_update_irq irq2=%d\n", irq2));
269 if (irq2 >= 0)
270 {
271 /* if irq request by slave pic, signal master PIC */
272 pic_set_irq1(&pThis->aPics[0], 2, 1, pThis->aPics[1].auTags[irq2]);
273 }
274 else
275 {
276 /* If not, clear the IR on the master PIC. */
277 pic_set_irq1(&pThis->aPics[0], 2, 0, 0 /*uTagSrc*/);
278 }
279 /* look at requested irq */
280 irq = pic_get_irq(&pThis->aPics[0]);
281 if (irq >= 0)
282 {
283 /* If irq 2 is pending on the master pic, then there must be one pending on the slave pic too! Otherwise we'll get
284 * spurious slave interrupts in picGetInterrupt.
285 */
286 if (irq != 2 || irq2 != -1)
287 {
288#if defined(DEBUG_PIC)
289 for (int i = 0; i < 2; i++)
290 Log(("pic%d: imr=%x irr=%x padd=%d\n", i, pThis->aPics[i].imr, pThis->aPics[i].irr, pThis->aPics[i].priority_add));
291 Log(("pic: cpu_interrupt\n"));
292#endif
293 pThis->CTX_SUFF(pPicHlp)->pfnSetInterruptFF(pThis->CTX_SUFF(pDevIns));
294 }
295 else
296 {
297 STAM_COUNTER_INC(&pThis->StatClearedActiveIRQ2);
298 Log(("pic_update_irq: irq 2 is active, but no interrupt is pending on the slave pic!!\n"));
299 /* Clear it here, so lower priority interrupts can still be dispatched. */
300
301 /* if this was the only pending irq, then we must clear the interrupt ff flag */
302 pThis->CTX_SUFF(pPicHlp)->pfnClearInterruptFF(pThis->CTX_SUFF(pDevIns));
303
304 /** @todo Is this correct? */
305 pThis->aPics[0].irr &= ~(1 << 2);
306
307 /* Call ourselves again just in case other interrupts are pending */
308 return pic_update_irq(pThis);
309 }
310 }
311 else
312 {
313 Log(("pic_update_irq: no interrupt is pending!!\n"));
314
315 /* we must clear the interrupt ff flag */
316 pThis->CTX_SUFF(pPicHlp)->pfnClearInterruptFF(pThis->CTX_SUFF(pDevIns));
317 }
318 return VINF_SUCCESS;
319}
320
321/**
322 * Set the an IRQ.
323 *
324 * @param pDevIns Device instance of the PICs.
325 * @param iIrq IRQ number to set.
326 * @param iLevel IRQ level.
327 * @param uTagSrc The IRQ tag and source ID (for tracing).
328 */
329PDMBOTHCBDECL(void) picSetIrq(PPDMDEVINS pDevIns, int iIrq, int iLevel, uint32_t uTagSrc)
330{
331 PDEVPIC pThis = PDMINS_2_DATA(pDevIns, PDEVPIC);
332 Assert(pThis->CTX_SUFF(pDevIns) == pDevIns);
333 Assert(pThis->aPics[0].CTX_SUFF(pDevIns) == pDevIns);
334 Assert(pThis->aPics[1].CTX_SUFF(pDevIns) == pDevIns);
335 AssertMsg(iIrq < 16, ("iIrq=%d\n", iIrq));
336
337 Log(("picSetIrq %d %d\n", iIrq, iLevel));
338 DumpPICState(&pThis->aPics[0], "picSetIrq");
339 DumpPICState(&pThis->aPics[1], "picSetIrq");
340 STAM_COUNTER_INC(&pThis->CTXSUFF(StatSetIrq));
341 if ((iLevel & PDM_IRQ_LEVEL_FLIP_FLOP) == PDM_IRQ_LEVEL_FLIP_FLOP)
342 {
343 /* A flip-flop lowers the IRQ line and immediately raises it, so
344 * that a rising edge is guaranteed to occur. Note that the IRQ
345 * line must be held high for a while to avoid spurious interrupts.
346 */
347 pic_set_irq1(&pThis->aPics[iIrq >> 3], iIrq & 7, 0, uTagSrc);
348 pic_update_irq(pThis);
349 }
350 pic_set_irq1(&pThis->aPics[iIrq >> 3], iIrq & 7, iLevel & PDM_IRQ_LEVEL_HIGH, uTagSrc);
351 pic_update_irq(pThis);
352}
353
354
355/* acknowledge interrupt 'irq' */
356DECLINLINE(void) pic_intack(PPICSTATE pPic, int irq)
357{
358 if (pPic->auto_eoi)
359 {
360 if (pPic->rotate_on_auto_eoi)
361 pPic->priority_add = (irq + 1) & 7;
362 }
363 else
364 pPic->isr |= (1 << irq);
365
366 /* We don't clear a level sensitive interrupt here */
367 if (!(pPic->elcr & (1 << irq)))
368 {
369 Log2(("pic_intack: irr=%x irrnew=%x\n", pPic->irr, pPic->irr & ~(1 << irq)));
370 pPic->irr &= ~(1 << irq);
371 }
372}
373
374
375/**
376 * Get a pending interrupt.
377 *
378 * @returns Pending interrupt number.
379 * @param pDevIns Device instance of the PICs.
380 * @param puTagSrc Where to return the IRQ tag and source ID.
381 */
382PDMBOTHCBDECL(int) picGetInterrupt(PPDMDEVINS pDevIns, uint32_t *puTagSrc)
383{
384 PDEVPIC pThis = PDMINS_2_DATA(pDevIns, PDEVPIC);
385 int irq;
386 int irq2;
387 int intno;
388
389 /* read the irq from the PIC */
390 DumpPICState(&pThis->aPics[0], "picGetInterrupt");
391 DumpPICState(&pThis->aPics[1], "picGetInterrupt");
392
393 irq = pic_get_irq(&pThis->aPics[0]);
394 if (irq >= 0)
395 {
396 pic_intack(&pThis->aPics[0], irq);
397 if (irq == 2)
398 {
399 irq2 = pic_get_irq(&pThis->aPics[1]);
400 if (irq2 >= 0)
401 pic_intack(&pThis->aPics[1], irq2);
402 else
403 {
404 /* Interrupt went away or is now masked. */
405 Log(("picGetInterrupt: spurious IRQ on slave controller, converted to IRQ15\n"));
406 irq2 = 7;
407 }
408 intno = pThis->aPics[1].irq_base + irq2;
409 *puTagSrc = pThis->aPics[0].auTags[irq2];
410 pThis->aPics[0].auTags[irq2] = 0;
411 Log2(("picGetInterrupt1: %x base=%x irq=%x uTagSrc=%#x\n", intno, pThis->aPics[1].irq_base, irq2, *puTagSrc));
412 irq = irq2 + 8;
413 }
414 else
415 {
416 intno = pThis->aPics[0].irq_base + irq;
417 *puTagSrc = pThis->aPics[0].auTags[irq];
418 pThis->aPics[0].auTags[irq] = 0;
419 Log2(("picGetInterrupt0: %x base=%x irq=%x uTagSrc=%#x\n", intno, pThis->aPics[0].irq_base, irq, *puTagSrc));
420 }
421 }
422 else
423 {
424 /* Interrupt went away or is now masked. */
425 Log(("picGetInterrupt: spurious IRQ on master controller, converted to IRQ7\n"));
426 irq = 7;
427 intno = pThis->aPics[0].irq_base + irq;
428 *puTagSrc = 0;
429 }
430 pic_update_irq(pThis);
431
432 Log(("picGetInterrupt: 0x%02x pending 0:%d 1:%d\n", intno, pic_get_irq(&pThis->aPics[0]), pic_get_irq(&pThis->aPics[1])));
433
434 return intno;
435}
436
437static void pic_reset(PPICSTATE pPic)
438{
439 PPDMDEVINSR3 pDevInsR3 = pPic->pDevInsR3;
440 PPDMDEVINSR0 pDevInsR0 = pPic->pDevInsR0;
441 PPDMDEVINSRC pDevInsRC = pPic->pDevInsRC;
442 int elcr_mask = pPic->elcr_mask;
443 int elcr = pPic->elcr;
444
445 memset(pPic, 0, sizeof(*pPic));
446
447 pPic->elcr = elcr;
448 pPic->elcr_mask = elcr_mask;
449 pPic->pDevInsRC = pDevInsRC;
450 pPic->pDevInsR0 = pDevInsR0;
451 pPic->pDevInsR3 = pDevInsR3;
452}
453
454
455static int pic_ioport_write(PDEVPIC pThis, PPICSTATE pPic, uint32_t addr, uint32_t val)
456{
457 int rc = VINF_SUCCESS;
458 int irq;
459
460 Log(("pic_write: addr=0x%02x val=0x%02x\n", addr, val));
461 addr &= 1;
462 if (addr == 0)
463 {
464 if (val & 0x10)
465 {
466 /* init */
467 pic_reset(pPic);
468 /* deassert a pending interrupt */
469 pThis->CTX_SUFF(pPicHlp)->pfnClearInterruptFF(pThis->CTX_SUFF(pDevIns));
470
471 pPic->init_state = 1;
472 pPic->init4 = val & 1;
473 if (val & 0x02)
474 AssertReleaseMsgFailed(("single mode not supported"));
475 if (val & 0x08)
476 if (pThis->cRelLogEntries++ < 64)
477 LogRel(("pic_write: Level sensitive IRQ setting ignored.\n"));
478 }
479 else if (val & 0x08)
480 {
481 if (val & 0x04)
482 pPic->poll = 1;
483 if (val & 0x02)
484 pPic->read_reg_select = val & 1;
485 if (val & 0x40)
486 pPic->special_mask = (val >> 5) & 1;
487 }
488 else
489 {
490 int cmd = val >> 5;
491 switch (cmd)
492 {
493 case 0:
494 case 4:
495 pPic->rotate_on_auto_eoi = cmd >> 2;
496 break;
497 case 1: /* end of interrupt */
498 case 5:
499 {
500 int priority = get_priority(pPic, pPic->isr);
501 if (priority != 8) {
502 irq = (priority + pPic->priority_add) & 7;
503 Log(("pic_write: EOI prio=%d irq=%d\n", priority, irq));
504 pPic->isr &= ~(1 << irq);
505 if (cmd == 5)
506 pPic->priority_add = (irq + 1) & 7;
507 rc = pic_update_irq(pThis);
508 Assert(rc == VINF_SUCCESS);
509 DumpPICState(pPic, "eoi");
510 }
511 break;
512 }
513 case 3:
514 {
515 irq = val & 7;
516 Log(("pic_write: EOI2 for irq %d\n", irq));
517 pPic->isr &= ~(1 << irq);
518 rc = pic_update_irq(pThis);
519 Assert(rc == VINF_SUCCESS);
520 DumpPICState(pPic, "eoi2");
521 break;
522 }
523 case 6:
524 {
525 pPic->priority_add = (val + 1) & 7;
526 Log(("pic_write: lowest priority %d (highest %d)\n", val & 7, pPic->priority_add));
527 rc = pic_update_irq(pThis);
528 Assert(rc == VINF_SUCCESS);
529 break;
530 }
531 case 7:
532 {
533 irq = val & 7;
534 Log(("pic_write: EOI3 for irq %d\n", irq));
535 pPic->isr &= ~(1 << irq);
536 pPic->priority_add = (irq + 1) & 7;
537 rc = pic_update_irq(pThis);
538 Assert(rc == VINF_SUCCESS);
539 DumpPICState(pPic, "eoi3");
540 break;
541 }
542 default:
543 /* no operation */
544 break;
545 }
546 }
547 }
548 else
549 {
550 switch (pPic->init_state)
551 {
552 case 0:
553 /* normal mode */
554 pPic->imr = val;
555 rc = pic_update_irq(pThis);
556 Assert(rc == VINF_SUCCESS);
557 break;
558 case 1:
559 pPic->irq_base = val & 0xf8;
560 pPic->init_state = 2;
561 Log(("pic_write: set irq base to %x\n", pPic->irq_base));
562 break;
563 case 2:
564 if (pPic->init4)
565 pPic->init_state = 3;
566 else
567 pPic->init_state = 0;
568 break;
569 case 3:
570 pPic->special_fully_nested_mode = (val >> 4) & 1;
571 pPic->auto_eoi = (val >> 1) & 1;
572 pPic->init_state = 0;
573 Log(("pic_write: special_fully_nested_mode=%d auto_eoi=%d\n", pPic->special_fully_nested_mode, pPic->auto_eoi));
574 break;
575 }
576 }
577 return rc;
578}
579
580
581static uint32_t pic_poll_read(PPICSTATE pPic, uint32_t addr1)
582{
583 PDEVPIC pThis = RT_FROM_MEMBER_DYN(pPic, DEVPIC, aPics[pPic->idxPic]);
584
585 int ret = pic_get_irq(pPic);
586 if (ret >= 0)
587 {
588 if (addr1 >> 7)
589 {
590 Log2(("pic_poll_read: clear slave irq (isr)\n"));
591 pThis->aPics[0].isr &= ~(1 << 2);
592 pThis->aPics[0].irr &= ~(1 << 2);
593 }
594 Log2(("pic_poll_read: clear irq %d (isr)\n", ret));
595 pPic->irr &= ~(1 << ret);
596 pPic->isr &= ~(1 << ret);
597 if (addr1 >> 7 || ret != 2)
598 pic_update_irq(pThis);
599 }
600 else
601 {
602 ret = 0;
603 pic_update_irq(pThis);
604 }
605
606 return ret;
607}
608
609
610static uint32_t pic_ioport_read(PPICSTATE pPic, uint32_t addr1, int *pRC)
611{
612 unsigned int addr;
613 int ret;
614
615 *pRC = VINF_SUCCESS;
616
617 addr = addr1;
618 addr &= 1;
619 if (pPic->poll)
620 {
621 ret = pic_poll_read(pPic, addr1);
622 pPic->poll = 0;
623 }
624 else
625 {
626 if (addr == 0)
627 {
628 if (pPic->read_reg_select)
629 ret = pPic->isr;
630 else
631 ret = pPic->irr;
632 }
633 else
634 ret = pPic->imr;
635 }
636 Log(("pic_read: addr=0x%02x val=0x%02x\n", addr1, ret));
637 return ret;
638}
639
640
641
642/* -=-=-=-=-=- I/O ports -=-=-=-=-=- */
643
644/**
645 * @callback_method_impl{FNIOMIOPORTIN}
646 */
647PDMBOTHCBDECL(int) picIOPortRead(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT uPort, uint32_t *pu32, unsigned cb)
648{
649 PDEVPIC pThis = PDMINS_2_DATA(pDevIns, PDEVPIC);
650 uint32_t iPic = (uint32_t)(uintptr_t)pvUser;
651
652 Assert(iPic == 0 || iPic == 1);
653 if (cb == 1)
654 {
655 int rc;
656 PIC_LOCK(pThis, VINF_IOM_R3_IOPORT_READ);
657 *pu32 = pic_ioport_read(&pThis->aPics[iPic], uPort, &rc);
658 PIC_UNLOCK(pThis);
659 return rc;
660 }
661 return VERR_IOM_IOPORT_UNUSED;
662}
663
664
665/**
666 * @callback_method_impl{FNIOMIOPORTOUT}
667 */
668PDMBOTHCBDECL(int) picIOPortWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT uPort, uint32_t u32, unsigned cb)
669{
670 PDEVPIC pThis = PDMINS_2_DATA(pDevIns, PDEVPIC);
671 uint32_t iPic = (uint32_t)(uintptr_t)pvUser;
672
673 Assert(iPic == 0 || iPic == 1);
674
675 if (cb == 1)
676 {
677 int rc;
678 PIC_LOCK(pThis, VINF_IOM_R3_IOPORT_WRITE);
679 rc = pic_ioport_write(pThis, &pThis->aPics[iPic], uPort, u32);
680 PIC_UNLOCK(pThis);
681 return rc;
682 }
683 return VINF_SUCCESS;
684}
685
686
687/**
688 * @callback_method_impl{FNIOMIOPORTIN, ELCR}
689 */
690PDMBOTHCBDECL(int) picIOPortElcrRead(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t *pu32, unsigned cb)
691{
692 if (cb == 1)
693 {
694 PPICSTATE pPic = (PPICSTATE)pvUser;
695 PIC_LOCK(PDMINS_2_DATA(pDevIns, PDEVPIC), VINF_IOM_R3_IOPORT_READ);
696 *pu32 = pPic->elcr;
697 PIC_UNLOCK(PDMINS_2_DATA(pDevIns, PDEVPIC));
698 return VINF_SUCCESS;
699 }
700 NOREF(Port);
701 return VERR_IOM_IOPORT_UNUSED;
702}
703
704
705/**
706 * @callback_method_impl{FNIOMIOPORTOUT, ELCR}
707 */
708PDMBOTHCBDECL(int) picIOPortElcrWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb)
709{
710 if (cb == 1)
711 {
712 PPICSTATE pPic = (PPICSTATE)pvUser;
713 PIC_LOCK(PDMINS_2_DATA(pDevIns, PDEVPIC), VINF_IOM_R3_IOPORT_WRITE);
714 pPic->elcr = u32 & pPic->elcr_mask;
715 PIC_UNLOCK(PDMINS_2_DATA(pDevIns, PDEVPIC));
716 }
717 NOREF(Port);
718 return VINF_SUCCESS;
719}
720
721
722#ifdef IN_RING3
723
724/**
725 * @callback_method_impl{FNDBGFHANDLERDEV}
726 */
727static DECLCALLBACK(void) picInfo(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
728{
729 PDEVPIC pThis = PDMINS_2_DATA(pDevIns, PDEVPIC);
730 NOREF(pszArgs);
731
732 /*
733 * Show info.
734 */
735 for (int i = 0; i < 2; i++)
736 {
737 PPICSTATE pPic = &pThis->aPics[i];
738
739 pHlp->pfnPrintf(pHlp, "PIC%d:\n", i);
740 pHlp->pfnPrintf(pHlp, " IMR :%02x ISR :%02x IRR :%02x LIRR:%02x\n",
741 pPic->imr, pPic->isr, pPic->irr, pPic->last_irr);
742 pHlp->pfnPrintf(pHlp, " Base:%02x PriAdd:%02x RegSel:%02x\n",
743 pPic->irq_base, pPic->priority_add, pPic->read_reg_select);
744 pHlp->pfnPrintf(pHlp, " Poll:%02x SpMask:%02x IState:%02x\n",
745 pPic->poll, pPic->special_mask, pPic->init_state);
746 pHlp->pfnPrintf(pHlp, " AEOI:%02x Rotate:%02x FNest :%02x Ini4:%02x\n",
747 pPic->auto_eoi, pPic->rotate_on_auto_eoi,
748 pPic->special_fully_nested_mode, pPic->init4);
749 pHlp->pfnPrintf(pHlp, " ELCR:%02x ELMask:%02x\n", pPic->elcr, pPic->elcr_mask);
750 }
751}
752
753
754/* -=-=-=-=-=- Saved State -=-=-=-=-=- */
755
756/**
757 * @callback_method_impl{FNSSMDEVSAVEEXEC}
758 */
759static DECLCALLBACK(int) picSaveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
760{
761 PDEVPIC pThis = PDMINS_2_DATA(pDevIns, PDEVPIC);
762 for (unsigned i = 0; i < RT_ELEMENTS(pThis->aPics); i++)
763 {
764 SSMR3PutU8(pSSM, pThis->aPics[i].last_irr);
765 SSMR3PutU8(pSSM, pThis->aPics[i].irr);
766 SSMR3PutU8(pSSM, pThis->aPics[i].imr);
767 SSMR3PutU8(pSSM, pThis->aPics[i].isr);
768 SSMR3PutU8(pSSM, pThis->aPics[i].priority_add);
769 SSMR3PutU8(pSSM, pThis->aPics[i].irq_base);
770 SSMR3PutU8(pSSM, pThis->aPics[i].read_reg_select);
771 SSMR3PutU8(pSSM, pThis->aPics[i].poll);
772 SSMR3PutU8(pSSM, pThis->aPics[i].special_mask);
773 SSMR3PutU8(pSSM, pThis->aPics[i].init_state);
774 SSMR3PutU8(pSSM, pThis->aPics[i].auto_eoi);
775 SSMR3PutU8(pSSM, pThis->aPics[i].rotate_on_auto_eoi);
776 SSMR3PutU8(pSSM, pThis->aPics[i].special_fully_nested_mode);
777 SSMR3PutU8(pSSM, pThis->aPics[i].init4);
778 SSMR3PutU8(pSSM, pThis->aPics[i].elcr);
779 }
780 return VINF_SUCCESS;
781}
782
783
784/**
785 * @callback_method_impl{FNSSMDEVLOADEXEC}
786 */
787static DECLCALLBACK(int) picLoadExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
788{
789 PDEVPIC pThis = PDMINS_2_DATA(pDevIns, PDEVPIC);
790
791 if (uVersion != 1)
792 return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
793 Assert(uPass == SSM_PASS_FINAL); NOREF(uPass);
794
795 for (unsigned i = 0; i < RT_ELEMENTS(pThis->aPics); i++)
796 {
797 SSMR3GetU8(pSSM, &pThis->aPics[i].last_irr);
798 SSMR3GetU8(pSSM, &pThis->aPics[i].irr);
799 SSMR3GetU8(pSSM, &pThis->aPics[i].imr);
800 SSMR3GetU8(pSSM, &pThis->aPics[i].isr);
801 SSMR3GetU8(pSSM, &pThis->aPics[i].priority_add);
802 SSMR3GetU8(pSSM, &pThis->aPics[i].irq_base);
803 SSMR3GetU8(pSSM, &pThis->aPics[i].read_reg_select);
804 SSMR3GetU8(pSSM, &pThis->aPics[i].poll);
805 SSMR3GetU8(pSSM, &pThis->aPics[i].special_mask);
806 SSMR3GetU8(pSSM, &pThis->aPics[i].init_state);
807 SSMR3GetU8(pSSM, &pThis->aPics[i].auto_eoi);
808 SSMR3GetU8(pSSM, &pThis->aPics[i].rotate_on_auto_eoi);
809 SSMR3GetU8(pSSM, &pThis->aPics[i].special_fully_nested_mode);
810 SSMR3GetU8(pSSM, &pThis->aPics[i].init4);
811 SSMR3GetU8(pSSM, &pThis->aPics[i].elcr);
812 }
813
814 /* Note! PDM will restore the VMCPU_FF_INTERRUPT_PIC state. */
815 return VINF_SUCCESS;
816}
817
818
819/* -=-=-=-=-=- PDMDEVREG -=-=-=-=-=- */
820
821/**
822 * @interface_method_impl{PDMDEVREG,pfnReset}
823 */
824static DECLCALLBACK(void) picReset(PPDMDEVINS pDevIns)
825{
826 PDEVPIC pThis = PDMINS_2_DATA(pDevIns, PDEVPIC);
827 unsigned i;
828 LogFlow(("picReset:\n"));
829 pThis->pPicHlpR3->pfnLock(pDevIns, VERR_INTERNAL_ERROR);
830
831 for (i = 0; i < RT_ELEMENTS(pThis->aPics); i++)
832 pic_reset(&pThis->aPics[i]);
833
834 PIC_UNLOCK(pThis);
835}
836
837
838/**
839 * @interface_method_impl{PDMDEVREG,pfnRelocate}
840 */
841static DECLCALLBACK(void) picRelocate(PPDMDEVINS pDevIns, RTGCINTPTR offDelta)
842{
843 RT_NOREF1(offDelta);
844 PDEVPIC pThis = PDMINS_2_DATA(pDevIns, PDEVPIC);
845 unsigned i;
846
847 pThis->pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
848 pThis->pPicHlpRC = pThis->pPicHlpR3->pfnGetRCHelpers(pDevIns);
849 for (i = 0; i < RT_ELEMENTS(pThis->aPics); i++)
850 pThis->aPics[i].pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
851}
852
853
854/**
855 * @interface_method_impl{PDMDEVREG,pfnConstruct}
856 */
857static DECLCALLBACK(int) picConstruct(PPDMDEVINS pDevIns, int iInstance, PCFGMNODE pCfg)
858{
859 PDMDEV_CHECK_VERSIONS_RETURN(pDevIns);
860 RT_NOREF1(iInstance);
861 PDEVPIC pThis = PDMINS_2_DATA(pDevIns, PDEVPIC);
862 int rc;
863 bool fGCEnabled;
864 bool fR0Enabled;
865 Assert(iInstance == 0);
866
867 /*
868 * Validate and read configuration.
869 */
870 if (!CFGMR3AreValuesValid(pCfg, "GCEnabled\0" "R0Enabled\0"))
871 return VERR_PDM_DEVINS_UNKNOWN_CFG_VALUES;
872
873 rc = CFGMR3QueryBoolDef(pCfg, "GCEnabled", &fGCEnabled, true);
874 if (RT_FAILURE(rc))
875 return PDMDEV_SET_ERROR(pDevIns, rc,
876 N_("Configuration error: failed to read GCEnabled as boolean"));
877
878 rc = CFGMR3QueryBoolDef(pCfg, "R0Enabled", &fR0Enabled, true);
879 if (RT_FAILURE(rc))
880 return PDMDEV_SET_ERROR(pDevIns, rc,
881 N_("Configuration error: failed to read R0Enabled as boolean"));
882
883 Log(("DevPIC: fGCEnabled=%RTbool fR0Enabled=%RTbool\n", fGCEnabled, fR0Enabled));
884
885 /*
886 * Init the data.
887 */
888 Assert(RT_ELEMENTS(pThis->aPics) == 2);
889 pThis->pDevInsR3 = pDevIns;
890 pThis->pDevInsR0 = PDMDEVINS_2_R0PTR(pDevIns);
891 pThis->pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
892 pThis->aPics[0].elcr_mask = 0xf8;
893 pThis->aPics[1].elcr_mask = 0xde;
894 pThis->aPics[0].pDevInsR3 = pDevIns;
895 pThis->aPics[1].pDevInsR3 = pDevIns;
896 pThis->aPics[0].pDevInsR0 = PDMDEVINS_2_R0PTR(pDevIns);
897 pThis->aPics[1].pDevInsR0 = PDMDEVINS_2_R0PTR(pDevIns);
898 pThis->aPics[0].pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
899 pThis->aPics[1].pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
900 pThis->aPics[0].idxPic = 0;
901 pThis->aPics[1].idxPic = 1;
902 pThis->cRelLogEntries = 0;
903
904 /*
905 * Register us as the PIC with PDM.
906 */
907 PDMPICREG PicReg;
908 PicReg.u32Version = PDM_PICREG_VERSION;
909 PicReg.pfnSetIrqR3 = picSetIrq;
910 PicReg.pfnGetInterruptR3 = picGetInterrupt;
911
912 if (fGCEnabled)
913 {
914 PicReg.pszSetIrqRC = "picSetIrq";
915 PicReg.pszGetInterruptRC = "picGetInterrupt";
916 }
917 else
918 {
919 PicReg.pszSetIrqRC = NULL;
920 PicReg.pszGetInterruptRC = NULL;
921 }
922
923 if (fR0Enabled)
924 {
925 PicReg.pszSetIrqR0 = "picSetIrq";
926 PicReg.pszGetInterruptR0 = "picGetInterrupt";
927 }
928 else
929 {
930 PicReg.pszSetIrqR0 = NULL;
931 PicReg.pszGetInterruptR0 = NULL;
932 }
933
934 rc = PDMDevHlpPICRegister(pDevIns, &PicReg, &pThis->pPicHlpR3);
935 AssertLogRelMsgRCReturn(rc, ("PICRegister -> %Rrc\n", rc), rc);
936 if (fGCEnabled)
937 pThis->pPicHlpRC = pThis->pPicHlpR3->pfnGetRCHelpers(pDevIns);
938 if (fR0Enabled)
939 pThis->pPicHlpR0 = pThis->pPicHlpR3->pfnGetR0Helpers(pDevIns);
940
941 /*
942 * Since the PIC helper interface provides access to the PDM lock,
943 * we need no device level critical section.
944 */
945 rc = PDMDevHlpSetDeviceCritSect(pDevIns, PDMDevHlpCritSectGetNop(pDevIns));
946 AssertRCReturn(rc, rc);
947
948 /*
949 * Register I/O ports and save state.
950 */
951 rc = PDMDevHlpIOPortRegister(pDevIns, 0x20, 2, (void *)0, picIOPortWrite, picIOPortRead, NULL, NULL, "i8259 PIC #0");
952 if (RT_FAILURE(rc))
953 return rc;
954 rc = PDMDevHlpIOPortRegister(pDevIns, 0xa0, 2, (void *)1, picIOPortWrite, picIOPortRead, NULL, NULL, "i8259 PIC #1");
955 if (RT_FAILURE(rc))
956 return rc;
957 if (fGCEnabled)
958 {
959 rc = PDMDevHlpIOPortRegisterRC(pDevIns, 0x20, 2, 0, "picIOPortWrite", "picIOPortRead", NULL, NULL, "i8259 PIC #0");
960 if (RT_FAILURE(rc))
961 return rc;
962 rc = PDMDevHlpIOPortRegisterRC(pDevIns, 0xa0, 2, 1, "picIOPortWrite", "picIOPortRead", NULL, NULL, "i8259 PIC #1");
963 if (RT_FAILURE(rc))
964 return rc;
965 }
966 if (fR0Enabled)
967 {
968 rc = PDMDevHlpIOPortRegisterR0(pDevIns, 0x20, 2, 0, "picIOPortWrite", "picIOPortRead", NULL, NULL, "i8259 PIC #0");
969 if (RT_FAILURE(rc))
970 return rc;
971 rc = PDMDevHlpIOPortRegisterR0(pDevIns, 0xa0, 2, 1, "picIOPortWrite", "picIOPortRead", NULL, NULL, "i8259 PIC #1");
972 if (RT_FAILURE(rc))
973 return rc;
974 }
975
976 rc = PDMDevHlpIOPortRegister(pDevIns, 0x4d0, 1, &pThis->aPics[0],
977 picIOPortElcrWrite, picIOPortElcrRead, NULL, NULL, "i8259 PIC #0 - elcr");
978 if (RT_FAILURE(rc))
979 return rc;
980 rc = PDMDevHlpIOPortRegister(pDevIns, 0x4d1, 1, &pThis->aPics[1],
981 picIOPortElcrWrite, picIOPortElcrRead, NULL, NULL, "i8259 PIC #1 - elcr");
982 if (RT_FAILURE(rc))
983 return rc;
984 if (fGCEnabled)
985 {
986 RTRCPTR pDataRC = PDMINS_2_DATA_RCPTR(pDevIns);
987 rc = PDMDevHlpIOPortRegisterRC(pDevIns, 0x4d0, 1, pDataRC + RT_OFFSETOF(DEVPIC, aPics[0]),
988 "picIOPortElcrWrite", "picIOPortElcrRead", NULL, NULL, "i8259 PIC #0 - elcr");
989 if (RT_FAILURE(rc))
990 return rc;
991 rc = PDMDevHlpIOPortRegisterRC(pDevIns, 0x4d1, 1, pDataRC + RT_OFFSETOF(DEVPIC, aPics[1]),
992 "picIOPortElcrWrite", "picIOPortElcrRead", NULL, NULL, "i8259 PIC #1 - elcr");
993 if (RT_FAILURE(rc))
994 return rc;
995 }
996 if (fR0Enabled)
997 {
998 RTR0PTR pDataR0 = PDMINS_2_DATA_R0PTR(pDevIns);
999 rc = PDMDevHlpIOPortRegisterR0(pDevIns, 0x4d0, 1, pDataR0 + RT_OFFSETOF(DEVPIC, aPics[0]),
1000 "picIOPortElcrWrite", "picIOPortElcrRead", NULL, NULL, "i8259 PIC #0 - elcr");
1001 if (RT_FAILURE(rc))
1002 return rc;
1003 rc = PDMDevHlpIOPortRegisterR0(pDevIns, 0x4d1, 1, pDataR0 + RT_OFFSETOF(DEVPIC, aPics[1]),
1004 "picIOPortElcrWrite", "picIOPortElcrRead", NULL, NULL, "i8259 PIC #1 - elcr");
1005 if (RT_FAILURE(rc))
1006 return rc;
1007 }
1008
1009 rc = PDMDevHlpSSMRegister(pDevIns, 1 /* uVersion */, sizeof(*pThis), picSaveExec, picLoadExec);
1010 if (RT_FAILURE(rc))
1011 return rc;
1012
1013
1014 /*
1015 * Register the info item.
1016 */
1017 PDMDevHlpDBGFInfoRegister(pDevIns, "pic", "PIC info.", picInfo);
1018
1019 /*
1020 * Initialize the device state.
1021 */
1022 picReset(pDevIns);
1023
1024#ifdef VBOX_WITH_STATISTICS
1025 /*
1026 * Statistics.
1027 */
1028 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatSetIrqGC, STAMTYPE_COUNTER, "/Devices/PIC/SetIrqGC", STAMUNIT_OCCURENCES, "Number of PIC SetIrq calls in GC.");
1029 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatSetIrqHC, STAMTYPE_COUNTER, "/Devices/PIC/SetIrqHC", STAMUNIT_OCCURENCES, "Number of PIC SetIrq calls in HC.");
1030
1031 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatClearedActiveIRQ2, STAMTYPE_COUNTER, "/Devices/PIC/Masked/ActiveIRQ2", STAMUNIT_OCCURENCES, "Number of cleared irq 2.");
1032 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatClearedActiveMasterIRQ, STAMTYPE_COUNTER, "/Devices/PIC/Masked/ActiveMaster", STAMUNIT_OCCURENCES, "Number of cleared master irqs.");
1033 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatClearedActiveSlaveIRQ, STAMTYPE_COUNTER, "/Devices/PIC/Masked/ActiveSlave", STAMUNIT_OCCURENCES, "Number of cleared slave irqs.");
1034#endif
1035
1036 return VINF_SUCCESS;
1037}
1038
1039
1040/**
1041 * The device registration structure.
1042 */
1043const PDMDEVREG g_DeviceI8259 =
1044{
1045 /* u32Version */
1046 PDM_DEVREG_VERSION,
1047 /* szName */
1048 "i8259",
1049 /* szRCMod */
1050 "VBoxDDRC.rc",
1051 /* szR0Mod */
1052 "VBoxDDR0.r0",
1053 /* pszDescription */
1054 "Intel 8259 Programmable Interrupt Controller (PIC) Device.",
1055 /* fFlags */
1056 PDM_DEVREG_FLAGS_HOST_BITS_DEFAULT | PDM_DEVREG_FLAGS_GUEST_BITS_32_64 | PDM_DEVREG_FLAGS_PAE36 | PDM_DEVREG_FLAGS_RC | PDM_DEVREG_FLAGS_R0,
1057 /* fClass */
1058 PDM_DEVREG_CLASS_PIC,
1059 /* cMaxInstances */
1060 1,
1061 /* cbInstance */
1062 sizeof(DEVPIC),
1063 /* pfnConstruct */
1064 picConstruct,
1065 /* pfnDestruct */
1066 NULL,
1067 /* pfnRelocate */
1068 picRelocate,
1069 /* pfnMemSetup */
1070 NULL,
1071 /* pfnPowerOn */
1072 NULL,
1073 /* pfnReset */
1074 picReset,
1075 /* pfnSuspend */
1076 NULL,
1077 /* pfnResume */
1078 NULL,
1079 /* pfnAttach */
1080 NULL,
1081 /* pfnDetach */
1082 NULL,
1083 /* pfnQueryInterface. */
1084 NULL,
1085 /* pfnInitComplete */
1086 NULL,
1087 /* pfnPowerOff */
1088 NULL,
1089 /* pfnSoftReset */
1090 NULL,
1091 /* u32VersionEnd */
1092 PDM_DEVREG_VERSION
1093};
1094
1095#endif /* IN_RING3 */
1096#endif /* !VBOX_DEVICE_STRUCT_TESTCASE */
1097
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