DevPIC.cpp@ 62564

Last change on this file since 62564 was 62509, checked in by vboxsync, 8 years ago
(C) 2016
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1	/* $Id: DevPIC.cpp 62509 2016-07-22 19:12:22Z vboxsync $ */
2	/** @file
3	* DevPIC - Intel 8259 Programmable Interrupt Controller (PIC) Device.
4	*/
5
6	/*
7	* Copyright (C) 2006-2016 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	* -------------------------------------------------------------------
17	*
18	* This code is based on:
19	*
20	* QEMU 8259 interrupt controller emulation
21	*
22	* Copyright (c) 2003-2004 Fabrice Bellard
23	*
24	* Permission is hereby granted, free of charge, to any person obtaining a copy
25	* of this software and associated documentation files (the "Software"), to deal
26	* in the Software without restriction, including without limitation the rights
27	* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
28	* copies of the Software, and to permit persons to whom the Software is
29	* furnished to do so, subject to the following conditions:
30	*
31	* The above copyright notice and this permission notice shall be included in
32	* all copies or substantial portions of the Software.
33	*
34	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
35	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
36	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
37	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
38	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
39	* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
40	* THE SOFTWARE.
41	*
42	*/
43
44
45	/*********************************************************************************************************************************
46	* Header Files *
47	*********************************************************************************************************************************/
48	#define LOG_GROUP LOG_GROUP_DEV_PIC
49	#include <VBox/vmm/pdmdev.h>
50	#include <VBox/log.h>
51	#include <iprt/assert.h>
52	#include <iprt/string.h>
53
54	#include "VBoxDD.h"
55
56
57	/*********************************************************************************************************************************
58	* Defined Constants And Macros *
59	*********************************************************************************************************************************/
60	/** @def PIC_LOCK
61	* Acquires the PDM lock. This is a NOP if locking is disabled. */
62	/** @def PIC_UNLOCK
63	* Releases the PDM lock. This is a NOP if locking is disabled. */
64	#define PIC_LOCK(pThis, rc) \
65	do { \
66	int rc2 = (pThis)->CTX_SUFF(pPicHlp)->pfnLock((pThis)->CTX_SUFF(pDevIns), rc); \
67	if (rc2 != VINF_SUCCESS) \
68	return rc2; \
69	} while (0)
70	#define PIC_UNLOCK(pThis) \
71	(pThis)->CTX_SUFF(pPicHlp)->pfnUnlock((pThis)->CTX_SUFF(pDevIns))
72
73
74	/* debug PIC */
75	#define DEBUG_PIC
76
77	/#define DEBUG_IRQ_COUNT/
78
79	/**
80	* The instance data of one (1) PIC.
81	*/
82	typedef struct PICSTATE
83	{
84	uint8_t last_irr; /*< edge detection /
85	uint8_t irr; /*< interrupt request register /
86	uint8_t imr; /*< interrupt mask register /
87	uint8_t isr; /*< interrupt service register /
88	uint8_t priority_add; /*< highest irq priority /
89	uint8_t irq_base;
90	uint8_t read_reg_select;
91	uint8_t poll;
92	uint8_t special_mask;
93	uint8_t init_state;
94	uint8_t auto_eoi;
95	uint8_t rotate_on_auto_eoi;
96	uint8_t special_fully_nested_mode;
97	uint8_t init4; /*< true if 4 byte init /
98	uint8_t elcr; /*< PIIX edge/trigger selection/
99	uint8_t elcr_mask;
100	/** Pointer to the device instance, R3 Ptr. */
101	PPDMDEVINSR3 pDevInsR3;
102	/** Pointer to the device instance, R0 Ptr. */
103	PPDMDEVINSR0 pDevInsR0;
104	/** Pointer to the device instance, RC Ptr. */
105	PPDMDEVINSRC pDevInsRC;
106	/** The PIC index (0 or 1). */
107	uint8_t idxPic;
108	uint8_t abAlignment0[3]; /*< Alignment padding. /
109	/** The IRQ tags and source IDs for each (tracing purposes). */
110	uint32_t auTags[8];
111	} PICSTATE;
112	/** Pointer to the state of one PIC. */
113	typedef PICSTATE *PPICSTATE;
114
115
116	/**
117	* The whole PIC device instance data.
118	*/
119	typedef struct DEVPIC
120	{
121	/** The two interrupt controllers. */
122	PICSTATE aPics[2];
123	/** Pointer to the device instance - R3 Ptr. */
124	PPDMDEVINSR3 pDevInsR3;
125	/** Pointer to the PIC R3 helpers. */
126	PCPDMPICHLPR3 pPicHlpR3;
127	/** Pointer to the device instance - R0 Ptr. */
128	PPDMDEVINSR0 pDevInsR0;
129	/** Pointer to the PIC R0 helpers. */
130	PCPDMPICHLPR0 pPicHlpR0;
131	/** Pointer to the device instance - RC Ptr. */
132	PPDMDEVINSRC pDevInsRC;
133	/** Pointer to the PIC RC helpers. */
134	PCPDMPICHLPRC pPicHlpRC;
135	/** Number of release log entries. Used to prevent flooding. */
136	uint32_t cRelLogEntries;
137	uint32_t u32AlignmentPadding;
138	#ifdef VBOX_WITH_STATISTICS
139	STAMCOUNTER StatSetIrqGC;
140	STAMCOUNTER StatSetIrqHC;
141	STAMCOUNTER StatClearedActiveIRQ2;
142	STAMCOUNTER StatClearedActiveMasterIRQ;
143	STAMCOUNTER StatClearedActiveSlaveIRQ;
144	#endif
145	} DEVPIC;
146	/** Pointer to the whole PIC instance data. */
147	typedef DEVPIC *PDEVPIC;
148
149
150	#ifndef VBOX_DEVICE_STRUCT_TESTCASE
151	#ifdef LOG_ENABLED
152	DECLINLINE(void) DumpPICState(PPICSTATE pPic, const char *pszFn)
153	{
154	PDEVPIC pThis = PDMINS_2_DATA(pPic->CTX_SUFF(pDevIns), PDEVPIC);
155
156	Log2(("%s: pic%d: elcr=%x last_irr=%x irr=%x imr=%x isr=%x irq_base=%x\n",
157	pszFn, (&pThis->aPics[0] == pPic) ? 0 : 1,
158	pPic->elcr, pPic->last_irr, pPic->irr, pPic->imr, pPic->isr, pPic->irq_base));
159	}
160	#else
161	# define DumpPICState(pThis, szFn) do { } while (0)
162	#endif
163
164	/* set irq level. If an edge is detected, then the IRR is set to 1 */
165	DECLINLINE(void) pic_set_irq1(PPICSTATE pPic, int irq, int level, uint32_t uTagSrc)
166	{
167	Log(("pic_set_irq1: irq=%d level=%d\n", irq, level));
168	int mask = 1 << irq;
169	if (pPic->elcr & mask)
170	{
171	/* level triggered */
172	if (level)
173	{
174	Log2(("pic_set_irq1(ls) irr=%d irrnew=%d\n", pPic->irr, pPic->irr \| mask));
175	pPic->irr \|= mask;
176	pPic->last_irr \|= mask;
177	}
178	else
179	{
180	Log2(("pic_set_irq1(lc) irr=%d irrnew=%d\n", pPic->irr, pPic->irr & ~mask));
181	pPic->irr &= ~mask;
182	pPic->last_irr &= ~mask;
183	}
184	}
185	else
186	{
187	/* edge triggered */
188	if (level)
189	{
190	if ((pPic->last_irr & mask) == 0)
191	{
192	Log2(("pic_set_irq1 irr=%x last_irr=%x\n", pPic->irr \| mask, pPic->last_irr));
193	pPic->irr \|= mask;
194	}
195	pPic->last_irr \|= mask;
196	}
197	else
198	{
199	pPic->irr &= ~mask;
200	pPic->last_irr &= ~mask;
201	}
202	}
203
204	/* Save the tag. */
205	if (level)
206	{
207	if (!pPic->auTags[irq])
208	pPic->auTags[irq] = uTagSrc;
209	else
210	pPic->auTags[irq] \|= RT_BIT_32(31);
211	}
212
213	DumpPICState(pPic, "pic_set_irq1");
214	}
215
216	/* return the highest priority found in mask (highest = smallest
217	number). Return 8 if no irq */
218	DECLINLINE(int) get_priority(PPICSTATE pPic, int mask)
219	{
220	int priority;
221	if (mask == 0)
222	return 8;
223	priority = 0;
224	while ((mask & (1 << ((priority + pPic->priority_add) & 7))) == 0)
225	priority++;
226	return priority;
227	}
228
229	/* return the pic wanted interrupt. return -1 if none */
230	static int pic_get_irq(PPICSTATE pPic)
231	{
232	int mask, cur_priority, priority;
233	Log(("pic_get_irq%d: mask=%x\n", pPic->idxPic, pPic->irr & ~pPic->imr));
234	DumpPICState(pPic, "pic_get_irq");
235
236	mask = pPic->irr & ~pPic->imr;
237	priority = get_priority(pPic, mask);
238	Log(("pic_get_irq: priority=%x\n", priority));
239	if (priority == 8)
240	return -1;
241	/* compute current priority. If special fully nested mode on the
242	master, the IRQ coming from the slave is not taken into account
243	for the priority computation. */
244	mask = pPic->isr;
245	if (pPic->special_fully_nested_mode && pPic->idxPic == 0)
246	mask &= ~(1 << 2);
247	cur_priority = get_priority(pPic, mask);
248	Log(("pic_get_irq%d: cur_priority=%x pending=%d\n", pPic->idxPic,
249	cur_priority, (priority == 8) ? -1 : (priority + pPic->priority_add) & 7));
250	if (priority < cur_priority)
251	{
252	/* higher priority found: an irq should be generated */
253	return (priority + pPic->priority_add) & 7;
254	}
255	return -1;
256	}
257
258	/* raise irq to CPU if necessary. must be called every time the active
259	irq may change */
260	static int pic_update_irq(PDEVPIC pThis)
261	{
262	int irq2, irq;
263
264	/* first look at slave pic */
265	irq2 = pic_get_irq(&pThis->aPics[1]);
266	Log(("pic_update_irq irq2=%d\n", irq2));
267	if (irq2 >= 0)
268	{
269	/* if irq request by slave pic, signal master PIC */
270	pic_set_irq1(&pThis->aPics[0], 2, 1, pThis->aPics[1].auTags[irq2]);
271	}
272	else
273	{
274	/* If not, clear the IR on the master PIC. */
275	pic_set_irq1(&pThis->aPics[0], 2, 0, 0 /uTagSrc/);
276	}
277	/* look at requested irq */
278	irq = pic_get_irq(&pThis->aPics[0]);
279	if (irq >= 0)
280	{
281	/* If irq 2 is pending on the master pic, then there must be one pending on the slave pic too! Otherwise we'll get
282	* spurious slave interrupts in picGetInterrupt.
283	*/
284	if (irq != 2 \|\| irq2 != -1)
285	{
286	#if defined(DEBUG_PIC)
287	for (int i = 0; i < 2; i++)
288	Log(("pic%d: imr=%x irr=%x padd=%d\n", i, pThis->aPics[i].imr, pThis->aPics[i].irr, pThis->aPics[i].priority_add));
289	Log(("pic: cpu_interrupt\n"));
290	#endif
291	pThis->CTX_SUFF(pPicHlp)->pfnSetInterruptFF(pThis->CTX_SUFF(pDevIns));
292	}
293	else
294	{
295	STAM_COUNTER_INC(&pThis->StatClearedActiveIRQ2);
296	Log(("pic_update_irq: irq 2 is active, but no interrupt is pending on the slave pic!!\n"));
297	/* Clear it here, so lower priority interrupts can still be dispatched. */
298
299	/* if this was the only pending irq, then we must clear the interrupt ff flag */
300	pThis->CTX_SUFF(pPicHlp)->pfnClearInterruptFF(pThis->CTX_SUFF(pDevIns));
301
302	/** @todo Is this correct? */
303	pThis->aPics[0].irr &= ~(1 << 2);
304
305	/* Call ourselves again just in case other interrupts are pending */
306	return pic_update_irq(pThis);
307	}
308	}
309	else
310	{
311	Log(("pic_update_irq: no interrupt is pending!!\n"));
312
313	/* we must clear the interrupt ff flag */
314	pThis->CTX_SUFF(pPicHlp)->pfnClearInterruptFF(pThis->CTX_SUFF(pDevIns));
315	}
316	return VINF_SUCCESS;
317	}
318
319	/** @note if an interrupt line state changes from unmasked to masked, then it must be deactivated when currently pending! */
320	static void pic_update_imr(PDEVPIC pThis, PPICSTATE pPic, uint8_t val)
321	{
322	int irq, intno;
323	PPICSTATE pActivePIC;
324
325	/* Query the current pending irq, if any. */
326	pActivePIC = &pThis->aPics[0];
327	intno = irq = pic_get_irq(pActivePIC);
328	if (irq == 2)
329	{
330	pActivePIC = &pThis->aPics[1];
331	irq = pic_get_irq(pActivePIC);
332	intno = irq + 8;
333	}
334
335	/* Update IMR */
336	Log(("pic_update_imr: pic%u %#x -> %#x\n", pPic->idxPic, pPic->imr, val));
337	pPic->imr = val;
338
339	/* If an interrupt is pending and now masked, then clear the FF flag. */
340	if ( irq >= 0
341	&& ((1 << irq) & ~pActivePIC->imr) == 0)
342	{
343	Log(("pic_update_imr: pic0: elcr=%x last_irr=%x irr=%x imr=%x isr=%x irq_base=%x\n",
344	pThis->aPics[0].elcr, pThis->aPics[0].last_irr, pThis->aPics[0].irr, pThis->aPics[0].imr, pThis->aPics[0].isr, pThis->aPics[0].irq_base));
345	Log(("pic_update_imr: pic1: elcr=%x last_irr=%x irr=%x imr=%x isr=%x irq_base=%x\n",
346	pThis->aPics[1].elcr, pThis->aPics[1].last_irr, pThis->aPics[1].irr, pThis->aPics[1].imr, pThis->aPics[1].isr, pThis->aPics[1].irq_base));
347
348	/* Clear pending IRQ 2 on master controller in case of slave interrupt. */
349	/** @todo Is this correct? */
350	if (intno > 7)
351	{
352	pThis->aPics[0].irr &= ~(1 << 2);
353	STAM_COUNTER_INC(&pThis->StatClearedActiveSlaveIRQ);
354	}
355	else
356	STAM_COUNTER_INC(&pThis->StatClearedActiveMasterIRQ);
357
358	Log(("pic_update_imr: clear pending interrupt %d\n", intno));
359	pThis->CTX_SUFF(pPicHlp)->pfnClearInterruptFF(pThis->CTX_SUFF(pDevIns));
360	}
361	}
362
363
364	/**
365	* Set the an IRQ.
366	*
367	* @param pDevIns Device instance of the PICs.
368	* @param iIrq IRQ number to set.
369	* @param iLevel IRQ level.
370	* @param uTagSrc The IRQ tag and source ID (for tracing).
371	*/
372	PDMBOTHCBDECL(void) picSetIrq(PPDMDEVINS pDevIns, int iIrq, int iLevel, uint32_t uTagSrc)
373	{
374	PDEVPIC pThis = PDMINS_2_DATA(pDevIns, PDEVPIC);
375	Assert(pThis->CTX_SUFF(pDevIns) == pDevIns);
376	Assert(pThis->aPics[0].CTX_SUFF(pDevIns) == pDevIns);
377	Assert(pThis->aPics[1].CTX_SUFF(pDevIns) == pDevIns);
378	AssertMsg(iIrq < 16, ("iIrq=%d\n", iIrq));
379
380	Log(("picSetIrq %d %d\n", iIrq, iLevel));
381	DumpPICState(&pThis->aPics[0], "picSetIrq");
382	DumpPICState(&pThis->aPics[1], "picSetIrq");
383	STAM_COUNTER_INC(&pThis->CTXSUFF(StatSetIrq));
384	if ((iLevel & PDM_IRQ_LEVEL_FLIP_FLOP) == PDM_IRQ_LEVEL_FLIP_FLOP)
385	{
386	/* A flip-flop lowers the IRQ line and immediately raises it, so
387	* that a rising edge is guaranteed to occur. Note that the IRQ
388	* line must be held high for a while to avoid spurious interrupts.
389	*/
390	pic_set_irq1(&pThis->aPics[iIrq >> 3], iIrq & 7, 0, uTagSrc);
391	pic_update_irq(pThis);
392	}
393	pic_set_irq1(&pThis->aPics[iIrq >> 3], iIrq & 7, iLevel & PDM_IRQ_LEVEL_HIGH, uTagSrc);
394	pic_update_irq(pThis);
395	}
396
397
398	/* acknowledge interrupt 'irq' */
399	DECLINLINE(void) pic_intack(PPICSTATE pPic, int irq)
400	{
401	if (pPic->auto_eoi)
402	{
403	if (pPic->rotate_on_auto_eoi)
404	pPic->priority_add = (irq + 1) & 7;
405	}
406	else
407	pPic->isr \|= (1 << irq);
408
409	/* We don't clear a level sensitive interrupt here */
410	if (!(pPic->elcr & (1 << irq)))
411	{
412	Log2(("pic_intack: irr=%x irrnew=%x\n", pPic->irr, pPic->irr & ~(1 << irq)));
413	pPic->irr &= ~(1 << irq);
414	}
415	}
416
417
418	/**
419	* Get a pending interrupt.
420	*
421	* @returns Pending interrupt number.
422	* @param pDevIns Device instance of the PICs.
423	* @param puTagSrc Where to return the IRQ tag and source ID.
424	*/
425	PDMBOTHCBDECL(int) picGetInterrupt(PPDMDEVINS pDevIns, uint32_t *puTagSrc)
426	{
427	PDEVPIC pThis = PDMINS_2_DATA(pDevIns, PDEVPIC);
428	int irq;
429	int irq2;
430	int intno;
431
432	/* read the irq from the PIC */
433	DumpPICState(&pThis->aPics[0], "picGetInterrupt");
434	DumpPICState(&pThis->aPics[1], "picGetInterrupt");
435
436	irq = pic_get_irq(&pThis->aPics[0]);
437	if (irq >= 0)
438	{
439	pic_intack(&pThis->aPics[0], irq);
440	if (irq == 2)
441	{
442	irq2 = pic_get_irq(&pThis->aPics[1]);
443	if (irq2 >= 0)
444	pic_intack(&pThis->aPics[1], irq2);
445	else
446	{
447	/* Interrupt went away or is now masked. */
448	Log(("picGetInterrupt: spurious IRQ on slave controller, converted to IRQ15\n"));
449	irq2 = 7;
450	}
451	intno = pThis->aPics[1].irq_base + irq2;
452	*puTagSrc = pThis->aPics[0].auTags[irq2];
453	pThis->aPics[0].auTags[irq2] = 0;
454	Log2(("picGetInterrupt1: %x base=%x irq=%x uTagSrc=%#x\n", intno, pThis->aPics[1].irq_base, irq2, *puTagSrc));
455	irq = irq2 + 8;
456	}
457	else
458	{
459	intno = pThis->aPics[0].irq_base + irq;
460	*puTagSrc = pThis->aPics[0].auTags[irq];
461	pThis->aPics[0].auTags[irq] = 0;
462	Log2(("picGetInterrupt0: %x base=%x irq=%x uTagSrc=%#x\n", intno, pThis->aPics[0].irq_base, irq, *puTagSrc));
463	}
464	}
465	else
466	{
467	/* Interrupt went away or is now masked. */
468	Log(("picGetInterrupt: spurious IRQ on master controller, converted to IRQ7\n"));
469	irq = 7;
470	intno = pThis->aPics[0].irq_base + irq;
471	*puTagSrc = 0;
472	}
473	pic_update_irq(pThis);
474
475	Log(("picGetInterrupt: 0x%02x pending 0:%d 1:%d\n", intno, pic_get_irq(&pThis->aPics[0]), pic_get_irq(&pThis->aPics[1])));
476
477	return intno;
478	}
479
480	static void pic_reset(PPICSTATE pPic)
481	{
482	PPDMDEVINSR3 pDevInsR3 = pPic->pDevInsR3;
483	PPDMDEVINSR0 pDevInsR0 = pPic->pDevInsR0;
484	PPDMDEVINSRC pDevInsRC = pPic->pDevInsRC;
485	int elcr_mask = pPic->elcr_mask;
486	int elcr = pPic->elcr;
487
488	memset(pPic, 0, sizeof(*pPic));
489
490	pPic->elcr = elcr;
491	pPic->elcr_mask = elcr_mask;
492	pPic->pDevInsRC = pDevInsRC;
493	pPic->pDevInsR0 = pDevInsR0;
494	pPic->pDevInsR3 = pDevInsR3;
495	}
496
497
498	static int pic_ioport_write(PDEVPIC pThis, PPICSTATE pPic, uint32_t addr, uint32_t val)
499	{
500	int rc = VINF_SUCCESS;
501	int irq;
502
503	Log(("pic_write: addr=0x%02x val=0x%02x\n", addr, val));
504	addr &= 1;
505	if (addr == 0)
506	{
507	if (val & 0x10)
508	{
509	/* init */
510	pic_reset(pPic);
511	/* deassert a pending interrupt */
512	pThis->CTX_SUFF(pPicHlp)->pfnClearInterruptFF(pThis->CTX_SUFF(pDevIns));
513
514	pPic->init_state = 1;
515	pPic->init4 = val & 1;
516	if (val & 0x02)
517	AssertReleaseMsgFailed(("single mode not supported"));
518	if (val & 0x08)
519	if (pThis->cRelLogEntries++ < 64)
520	LogRel(("pic_write: Level sensitive IRQ setting ignored.\n"));
521	}
522	else if (val & 0x08)
523	{
524	if (val & 0x04)
525	pPic->poll = 1;
526	if (val & 0x02)
527	pPic->read_reg_select = val & 1;
528	if (val & 0x40)
529	pPic->special_mask = (val >> 5) & 1;
530	}
531	else
532	{
533	int cmd = val >> 5;
534	switch (cmd)
535	{
536	case 0:
537	case 4:
538	pPic->rotate_on_auto_eoi = cmd >> 2;
539	break;
540	case 1: /* end of interrupt */
541	case 5:
542	{
543	int priority = get_priority(pPic, pPic->isr);
544	if (priority != 8) {
545	irq = (priority + pPic->priority_add) & 7;
546	Log(("pic_write: EOI prio=%d irq=%d\n", priority, irq));
547	pPic->isr &= ~(1 << irq);
548	if (cmd == 5)
549	pPic->priority_add = (irq + 1) & 7;
550	rc = pic_update_irq(pThis);
551	Assert(rc == VINF_SUCCESS);
552	DumpPICState(pPic, "eoi");
553	}
554	break;
555	}
556	case 3:
557	{
558	irq = val & 7;
559	Log(("pic_write: EOI2 for irq %d\n", irq));
560	pPic->isr &= ~(1 << irq);
561	rc = pic_update_irq(pThis);
562	Assert(rc == VINF_SUCCESS);
563	DumpPICState(pPic, "eoi2");
564	break;
565	}
566	case 6:
567	{
568	pPic->priority_add = (val + 1) & 7;
569	Log(("pic_write: lowest priority %d (highest %d)\n", val & 7, pPic->priority_add));
570	rc = pic_update_irq(pThis);
571	Assert(rc == VINF_SUCCESS);
572	break;
573	}
574	case 7:
575	{
576	irq = val & 7;
577	Log(("pic_write: EOI3 for irq %d\n", irq));
578	pPic->isr &= ~(1 << irq);
579	pPic->priority_add = (irq + 1) & 7;
580	rc = pic_update_irq(pThis);
581	Assert(rc == VINF_SUCCESS);
582	DumpPICState(pPic, "eoi3");
583	break;
584	}
585	default:
586	/* no operation */
587	break;
588	}
589	}
590	}
591	else
592	{
593	switch (pPic->init_state)
594	{
595	case 0:
596	/* normal mode */
597	pic_update_imr(pThis, pPic, val);
598
599	rc = pic_update_irq(pThis);
600	Assert(rc == VINF_SUCCESS);
601	break;
602	case 1:
603	pPic->irq_base = val & 0xf8;
604	pPic->init_state = 2;
605	Log(("pic_write: set irq base to %x\n", pPic->irq_base));
606	break;
607	case 2:
608	if (pPic->init4)
609	pPic->init_state = 3;
610	else
611	pPic->init_state = 0;
612	break;
613	case 3:
614	pPic->special_fully_nested_mode = (val >> 4) & 1;
615	pPic->auto_eoi = (val >> 1) & 1;
616	pPic->init_state = 0;
617	Log(("pic_write: special_fully_nested_mode=%d auto_eoi=%d\n", pPic->special_fully_nested_mode, pPic->auto_eoi));
618	break;
619	}
620	}
621	return rc;
622	}
623
624
625	static uint32_t pic_poll_read(PPICSTATE pPic, uint32_t addr1)
626	{
627	PDEVPIC pThis = RT_FROM_MEMBER(pPic, DEVPIC, aPics[pPic->idxPic]);
628
629	int ret = pic_get_irq(pPic);
630	if (ret >= 0)
631	{
632	if (addr1 >> 7)
633	{
634	Log2(("pic_poll_read: clear slave irq (isr)\n"));
635	pThis->aPics[0].isr &= ~(1 << 2);
636	pThis->aPics[0].irr &= ~(1 << 2);
637	}
638	Log2(("pic_poll_read: clear irq %d (isr)\n", ret));
639	pPic->irr &= ~(1 << ret);
640	pPic->isr &= ~(1 << ret);
641	if (addr1 >> 7 \|\| ret != 2)
642	pic_update_irq(pThis);
643	}
644	else
645	{
646	ret = 0;
647	pic_update_irq(pThis);
648	}
649
650	return ret;
651	}
652
653
654	static uint32_t pic_ioport_read(PPICSTATE pPic, uint32_t addr1, int *pRC)
655	{
656	unsigned int addr;
657	int ret;
658
659	*pRC = VINF_SUCCESS;
660
661	addr = addr1;
662	addr &= 1;
663	if (pPic->poll)
664	{
665	ret = pic_poll_read(pPic, addr1);
666	pPic->poll = 0;
667	}
668	else
669	{
670	if (addr == 0)
671	{
672	if (pPic->read_reg_select)
673	ret = pPic->isr;
674	else
675	ret = pPic->irr;
676	}
677	else
678	ret = pPic->imr;
679	}
680	Log(("pic_read: addr=0x%02x val=0x%02x\n", addr1, ret));
681	return ret;
682	}
683
684
685
686	/* -=-=-=-=-=- I/O ports -=-=-=-=-=- */
687
688	/**
689	* @callback_method_impl{FNIOMIOPORTIN}
690	*/
691	PDMBOTHCBDECL(int) picIOPortRead(PPDMDEVINS pDevIns, void pvUser, RTIOPORT Port, uint32_t pu32, unsigned cb)
692	{
693	PDEVPIC pThis = PDMINS_2_DATA(pDevIns, PDEVPIC);
694	uint32_t iPic = (uint32_t)(uintptr_t)pvUser;
695
696	Assert(iPic == 0 \|\| iPic == 1);
697	if (cb == 1)
698	{
699	int rc;
700	PIC_LOCK(pThis, VINF_IOM_R3_IOPORT_READ);
701	*pu32 = pic_ioport_read(&pThis->aPics[iPic], Port, &rc);
702	PIC_UNLOCK(pThis);
703	return rc;
704	}
705	return VERR_IOM_IOPORT_UNUSED;
706	}
707
708
709	/**
710	* @callback_method_impl{FNIOMIOPORTOUT}
711	*/
712	PDMBOTHCBDECL(int) picIOPortWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb)
713	{
714	PDEVPIC pThis = PDMINS_2_DATA(pDevIns, PDEVPIC);
715	uint32_t iPic = (uint32_t)(uintptr_t)pvUser;
716
717	Assert(iPic == 0 \|\| iPic == 1);
718
719	if (cb == 1)
720	{
721	int rc;
722	PIC_LOCK(pThis, VINF_IOM_R3_IOPORT_WRITE);
723	rc = pic_ioport_write(pThis, &pThis->aPics[iPic], Port, u32);
724	PIC_UNLOCK(pThis);
725	return rc;
726	}
727	return VINF_SUCCESS;
728	}
729
730
731	/**
732	* @callback_method_impl{FNIOMIOPORTIN, ELCR}
733	*/
734	PDMBOTHCBDECL(int) picIOPortElcrRead(PPDMDEVINS pDevIns, void pvUser, RTIOPORT Port, uint32_t pu32, unsigned cb)
735	{
736	if (cb == 1)
737	{
738	PPICSTATE pPic = (PPICSTATE)pvUser;
739	PIC_LOCK(PDMINS_2_DATA(pDevIns, PDEVPIC), VINF_IOM_R3_IOPORT_READ);
740	*pu32 = pPic->elcr;
741	PIC_UNLOCK(PDMINS_2_DATA(pDevIns, PDEVPIC));
742	return VINF_SUCCESS;
743	}
744	NOREF(Port);
745	return VERR_IOM_IOPORT_UNUSED;
746	}
747
748
749	/**
750	* @callback_method_impl{FNIOMIOPORTOUT, ELCR}
751	*/
752	PDMBOTHCBDECL(int) picIOPortElcrWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb)
753	{
754	if (cb == 1)
755	{
756	PPICSTATE pPic = (PPICSTATE)pvUser;
757	PIC_LOCK(PDMINS_2_DATA(pDevIns, PDEVPIC), VINF_IOM_R3_IOPORT_WRITE);
758	pPic->elcr = u32 & pPic->elcr_mask;
759	PIC_UNLOCK(PDMINS_2_DATA(pDevIns, PDEVPIC));
760	}
761	NOREF(Port);
762	return VINF_SUCCESS;
763	}
764
765
766	#ifdef IN_RING3
767
768	/**
769	* @callback_method_impl{FNDBGFHANDLERDEV}
770	*/
771	static DECLCALLBACK(void) picInfo(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
772	{
773	PDEVPIC pThis = PDMINS_2_DATA(pDevIns, PDEVPIC);
774	NOREF(pszArgs);
775
776	/*
777	* Show info.
778	*/
779	for (int i = 0; i < 2; i++)
780	{
781	PPICSTATE pPic = &pThis->aPics[i];
782
783	pHlp->pfnPrintf(pHlp, "PIC%d:\n", i);
784	pHlp->pfnPrintf(pHlp, " IMR :%02x ISR :%02x IRR :%02x LIRR:%02x\n",
785	pPic->imr, pPic->isr, pPic->irr, pPic->last_irr);
786	pHlp->pfnPrintf(pHlp, " Base:%02x PriAdd:%02x RegSel:%02x\n",
787	pPic->irq_base, pPic->priority_add, pPic->read_reg_select);
788	pHlp->pfnPrintf(pHlp, " Poll:%02x SpMask:%02x IState:%02x\n",
789	pPic->poll, pPic->special_mask, pPic->init_state);
790	pHlp->pfnPrintf(pHlp, " AEOI:%02x Rotate:%02x FNest :%02x Ini4:%02x\n",
791	pPic->auto_eoi, pPic->rotate_on_auto_eoi,
792	pPic->special_fully_nested_mode, pPic->init4);
793	pHlp->pfnPrintf(pHlp, " ELCR:%02x ELMask:%02x\n", pPic->elcr, pPic->elcr_mask);
794	}
795	}
796
797
798	/* -=-=-=-=-=- Saved State -=-=-=-=-=- */
799
800	/**
801	* @callback_method_impl{FNSSMDEVSAVEEXEC}
802	*/
803	static DECLCALLBACK(int) picSaveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
804	{
805	PDEVPIC pThis = PDMINS_2_DATA(pDevIns, PDEVPIC);
806	for (unsigned i = 0; i < RT_ELEMENTS(pThis->aPics); i++)
807	{
808	SSMR3PutU8(pSSM, pThis->aPics[i].last_irr);
809	SSMR3PutU8(pSSM, pThis->aPics[i].irr);
810	SSMR3PutU8(pSSM, pThis->aPics[i].imr);
811	SSMR3PutU8(pSSM, pThis->aPics[i].isr);
812	SSMR3PutU8(pSSM, pThis->aPics[i].priority_add);
813	SSMR3PutU8(pSSM, pThis->aPics[i].irq_base);
814	SSMR3PutU8(pSSM, pThis->aPics[i].read_reg_select);
815	SSMR3PutU8(pSSM, pThis->aPics[i].poll);
816	SSMR3PutU8(pSSM, pThis->aPics[i].special_mask);
817	SSMR3PutU8(pSSM, pThis->aPics[i].init_state);
818	SSMR3PutU8(pSSM, pThis->aPics[i].auto_eoi);
819	SSMR3PutU8(pSSM, pThis->aPics[i].rotate_on_auto_eoi);
820	SSMR3PutU8(pSSM, pThis->aPics[i].special_fully_nested_mode);
821	SSMR3PutU8(pSSM, pThis->aPics[i].init4);
822	SSMR3PutU8(pSSM, pThis->aPics[i].elcr);
823	}
824	return VINF_SUCCESS;
825	}
826
827
828	/**
829	* @callback_method_impl{FNSSMDEVLOADEXEC}
830	*/
831	static DECLCALLBACK(int) picLoadExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
832	{
833	PDEVPIC pThis = PDMINS_2_DATA(pDevIns, PDEVPIC);
834
835	if (uVersion != 1)
836	return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
837	Assert(uPass == SSM_PASS_FINAL); NOREF(uPass);
838
839	for (unsigned i = 0; i < RT_ELEMENTS(pThis->aPics); i++)
840	{
841	SSMR3GetU8(pSSM, &pThis->aPics[i].last_irr);
842	SSMR3GetU8(pSSM, &pThis->aPics[i].irr);
843	SSMR3GetU8(pSSM, &pThis->aPics[i].imr);
844	SSMR3GetU8(pSSM, &pThis->aPics[i].isr);
845	SSMR3GetU8(pSSM, &pThis->aPics[i].priority_add);
846	SSMR3GetU8(pSSM, &pThis->aPics[i].irq_base);
847	SSMR3GetU8(pSSM, &pThis->aPics[i].read_reg_select);
848	SSMR3GetU8(pSSM, &pThis->aPics[i].poll);
849	SSMR3GetU8(pSSM, &pThis->aPics[i].special_mask);
850	SSMR3GetU8(pSSM, &pThis->aPics[i].init_state);
851	SSMR3GetU8(pSSM, &pThis->aPics[i].auto_eoi);
852	SSMR3GetU8(pSSM, &pThis->aPics[i].rotate_on_auto_eoi);
853	SSMR3GetU8(pSSM, &pThis->aPics[i].special_fully_nested_mode);
854	SSMR3GetU8(pSSM, &pThis->aPics[i].init4);
855	SSMR3GetU8(pSSM, &pThis->aPics[i].elcr);
856	}
857	return VINF_SUCCESS;
858	}
859
860
861	/* -=-=-=-=-=- PDMDEVREG -=-=-=-=-=- */
862
863	/**
864	* @interface_method_impl{PDMDEVREG,pfnReset}
865	*/
866	static DECLCALLBACK(void) picReset(PPDMDEVINS pDevIns)
867	{
868	PDEVPIC pThis = PDMINS_2_DATA(pDevIns, PDEVPIC);
869	unsigned i;
870	LogFlow(("picReset:\n"));
871	pThis->pPicHlpR3->pfnLock(pDevIns, VERR_INTERNAL_ERROR);
872
873	for (i = 0; i < RT_ELEMENTS(pThis->aPics); i++)
874	pic_reset(&pThis->aPics[i]);
875
876	PIC_UNLOCK(pThis);
877	}
878
879
880	/**
881	* @interface_method_impl{PDMDEVREG,pfnRelocate}
882	*/
883	static DECLCALLBACK(void) picRelocate(PPDMDEVINS pDevIns, RTGCINTPTR offDelta)
884	{
885	PDEVPIC pThis = PDMINS_2_DATA(pDevIns, PDEVPIC);
886	unsigned i;
887
888	pThis->pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
889	pThis->pPicHlpRC = pThis->pPicHlpR3->pfnGetRCHelpers(pDevIns);
890	for (i = 0; i < RT_ELEMENTS(pThis->aPics); i++)
891	pThis->aPics[i].pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
892	}
893
894
895	/**
896	* @interface_method_impl{PDMDEVREG,pfnConstruct}
897	*/
898	static DECLCALLBACK(int) picConstruct(PPDMDEVINS pDevIns, int iInstance, PCFGMNODE pCfg)
899	{
900	PDEVPIC pThis = PDMINS_2_DATA(pDevIns, PDEVPIC);
901	int rc;
902	bool fGCEnabled;
903	bool fR0Enabled;
904	Assert(iInstance == 0);
905
906	/*
907	* Validate and read configuration.
908	*/
909	if (!CFGMR3AreValuesValid(pCfg, "GCEnabled\0" "R0Enabled\0"))
910	return VERR_PDM_DEVINS_UNKNOWN_CFG_VALUES;
911
912	rc = CFGMR3QueryBoolDef(pCfg, "GCEnabled", &fGCEnabled, true);
913	if (RT_FAILURE(rc))
914	return PDMDEV_SET_ERROR(pDevIns, rc,
915	N_("Configuration error: failed to read GCEnabled as boolean"));
916
917	rc = CFGMR3QueryBoolDef(pCfg, "R0Enabled", &fR0Enabled, true);
918	if (RT_FAILURE(rc))
919	return PDMDEV_SET_ERROR(pDevIns, rc,
920	N_("Configuration error: failed to read R0Enabled as boolean"));
921
922	Log(("DevPIC: fGCEnabled=%RTbool fR0Enabled=%RTbool\n", fGCEnabled, fR0Enabled));
923
924	/*
925	* Init the data.
926	*/
927	Assert(RT_ELEMENTS(pThis->aPics) == 2);
928	pThis->pDevInsR3 = pDevIns;
929	pThis->pDevInsR0 = PDMDEVINS_2_R0PTR(pDevIns);
930	pThis->pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
931	pThis->aPics[0].elcr_mask = 0xf8;
932	pThis->aPics[1].elcr_mask = 0xde;
933	pThis->aPics[0].pDevInsR3 = pDevIns;
934	pThis->aPics[1].pDevInsR3 = pDevIns;
935	pThis->aPics[0].pDevInsR0 = PDMDEVINS_2_R0PTR(pDevIns);
936	pThis->aPics[1].pDevInsR0 = PDMDEVINS_2_R0PTR(pDevIns);
937	pThis->aPics[0].pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
938	pThis->aPics[1].pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
939	pThis->aPics[0].idxPic = 0;
940	pThis->aPics[1].idxPic = 1;
941	pThis->cRelLogEntries = 0;
942
943	/*
944	* Register us as the PIC with PDM.
945	*/
946	PDMPICREG PicReg;
947	PicReg.u32Version = PDM_PICREG_VERSION;
948	PicReg.pfnSetIrqR3 = picSetIrq;
949	PicReg.pfnGetInterruptR3 = picGetInterrupt;
950
951	if (fGCEnabled)
952	{
953	PicReg.pszSetIrqRC = "picSetIrq";
954	PicReg.pszGetInterruptRC = "picGetInterrupt";
955	}
956	else
957	{
958	PicReg.pszSetIrqRC = NULL;
959	PicReg.pszGetInterruptRC = NULL;
960	}
961
962	if (fR0Enabled)
963	{
964	PicReg.pszSetIrqR0 = "picSetIrq";
965	PicReg.pszGetInterruptR0 = "picGetInterrupt";
966	}
967	else
968	{
969	PicReg.pszSetIrqR0 = NULL;
970	PicReg.pszGetInterruptR0 = NULL;
971	}
972
973	rc = PDMDevHlpPICRegister(pDevIns, &PicReg, &pThis->pPicHlpR3);
974	AssertLogRelMsgRCReturn(rc, ("PICRegister -> %Rrc\n", rc), rc);
975	if (fGCEnabled)
976	pThis->pPicHlpRC = pThis->pPicHlpR3->pfnGetRCHelpers(pDevIns);
977	if (fR0Enabled)
978	pThis->pPicHlpR0 = pThis->pPicHlpR3->pfnGetR0Helpers(pDevIns);
979
980	/*
981	* Since the PIC helper interface provides access to the PDM lock,
982	* we need no device level critical section.
983	*/
984	rc = PDMDevHlpSetDeviceCritSect(pDevIns, PDMDevHlpCritSectGetNop(pDevIns));
985	AssertRCReturn(rc, rc);
986
987	/*
988	* Register I/O ports and save state.
989	*/
990	rc = PDMDevHlpIOPortRegister(pDevIns, 0x20, 2, (void *)0, picIOPortWrite, picIOPortRead, NULL, NULL, "i8259 PIC #0");
991	if (RT_FAILURE(rc))
992	return rc;
993	rc = PDMDevHlpIOPortRegister(pDevIns, 0xa0, 2, (void *)1, picIOPortWrite, picIOPortRead, NULL, NULL, "i8259 PIC #1");
994	if (RT_FAILURE(rc))
995	return rc;
996	if (fGCEnabled)
997	{
998	rc = PDMDevHlpIOPortRegisterRC(pDevIns, 0x20, 2, 0, "picIOPortWrite", "picIOPortRead", NULL, NULL, "i8259 PIC #0");
999	if (RT_FAILURE(rc))
1000	return rc;
1001	rc = PDMDevHlpIOPortRegisterRC(pDevIns, 0xa0, 2, 1, "picIOPortWrite", "picIOPortRead", NULL, NULL, "i8259 PIC #1");
1002	if (RT_FAILURE(rc))
1003	return rc;
1004	}
1005	if (fR0Enabled)
1006	{
1007	rc = PDMDevHlpIOPortRegisterR0(pDevIns, 0x20, 2, 0, "picIOPortWrite", "picIOPortRead", NULL, NULL, "i8259 PIC #0");
1008	if (RT_FAILURE(rc))
1009	return rc;
1010	rc = PDMDevHlpIOPortRegisterR0(pDevIns, 0xa0, 2, 1, "picIOPortWrite", "picIOPortRead", NULL, NULL, "i8259 PIC #1");
1011	if (RT_FAILURE(rc))
1012	return rc;
1013	}
1014
1015	rc = PDMDevHlpIOPortRegister(pDevIns, 0x4d0, 1, &pThis->aPics[0],
1016	picIOPortElcrWrite, picIOPortElcrRead, NULL, NULL, "i8259 PIC #0 - elcr");
1017	if (RT_FAILURE(rc))
1018	return rc;
1019	rc = PDMDevHlpIOPortRegister(pDevIns, 0x4d1, 1, &pThis->aPics[1],
1020	picIOPortElcrWrite, picIOPortElcrRead, NULL, NULL, "i8259 PIC #1 - elcr");
1021	if (RT_FAILURE(rc))
1022	return rc;
1023	if (fGCEnabled)
1024	{
1025	RTRCPTR pDataRC = PDMINS_2_DATA_RCPTR(pDevIns);
1026	rc = PDMDevHlpIOPortRegisterRC(pDevIns, 0x4d0, 1, pDataRC + RT_OFFSETOF(DEVPIC, aPics[0]),
1027	"picIOPortElcrWrite", "picIOPortElcrRead", NULL, NULL, "i8259 PIC #0 - elcr");
1028	if (RT_FAILURE(rc))
1029	return rc;
1030	rc = PDMDevHlpIOPortRegisterRC(pDevIns, 0x4d1, 1, pDataRC + RT_OFFSETOF(DEVPIC, aPics[1]),
1031	"picIOPortElcrWrite", "picIOPortElcrRead", NULL, NULL, "i8259 PIC #1 - elcr");
1032	if (RT_FAILURE(rc))
1033	return rc;
1034	}
1035	if (fR0Enabled)
1036	{
1037	RTR0PTR pDataR0 = PDMINS_2_DATA_R0PTR(pDevIns);
1038	rc = PDMDevHlpIOPortRegisterR0(pDevIns, 0x4d0, 1, pDataR0 + RT_OFFSETOF(DEVPIC, aPics[0]),
1039	"picIOPortElcrWrite", "picIOPortElcrRead", NULL, NULL, "i8259 PIC #0 - elcr");
1040	if (RT_FAILURE(rc))
1041	return rc;
1042	rc = PDMDevHlpIOPortRegisterR0(pDevIns, 0x4d1, 1, pDataR0 + RT_OFFSETOF(DEVPIC, aPics[1]),
1043	"picIOPortElcrWrite", "picIOPortElcrRead", NULL, NULL, "i8259 PIC #1 - elcr");
1044	if (RT_FAILURE(rc))
1045	return rc;
1046	}
1047
1048	rc = PDMDevHlpSSMRegister(pDevIns, 1 /* uVersion /, sizeof(pThis), picSaveExec, picLoadExec);
1049	if (RT_FAILURE(rc))
1050	return rc;
1051
1052
1053	/*
1054	* Register the info item.
1055	*/
1056	PDMDevHlpDBGFInfoRegister(pDevIns, "pic", "PIC info.", picInfo);
1057
1058	/*
1059	* Initialize the device state.
1060	*/
1061	picReset(pDevIns);
1062
1063	#ifdef VBOX_WITH_STATISTICS
1064	/*
1065	* Statistics.
1066	*/
1067	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatSetIrqGC, STAMTYPE_COUNTER, "/Devices/PIC/SetIrqGC", STAMUNIT_OCCURENCES, "Number of PIC SetIrq calls in GC.");
1068	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatSetIrqHC, STAMTYPE_COUNTER, "/Devices/PIC/SetIrqHC", STAMUNIT_OCCURENCES, "Number of PIC SetIrq calls in HC.");
1069
1070	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatClearedActiveIRQ2, STAMTYPE_COUNTER, "/Devices/PIC/Masked/ActiveIRQ2", STAMUNIT_OCCURENCES, "Number of cleared irq 2.");
1071	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatClearedActiveMasterIRQ, STAMTYPE_COUNTER, "/Devices/PIC/Masked/ActiveMaster", STAMUNIT_OCCURENCES, "Number of cleared master irqs.");
1072	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatClearedActiveSlaveIRQ, STAMTYPE_COUNTER, "/Devices/PIC/Masked/ActiveSlave", STAMUNIT_OCCURENCES, "Number of cleared slave irqs.");
1073	#endif
1074
1075	return VINF_SUCCESS;
1076	}
1077
1078
1079	/**
1080	* The device registration structure.
1081	*/
1082	const PDMDEVREG g_DeviceI8259 =
1083	{
1084	/* u32Version */
1085	PDM_DEVREG_VERSION,
1086	/* szName */
1087	"i8259",
1088	/* szRCMod */
1089	"VBoxDDRC.rc",
1090	/* szR0Mod */
1091	"VBoxDDR0.r0",
1092	/* pszDescription */
1093	"Intel 8259 Programmable Interrupt Controller (PIC) Device.",
1094	/* fFlags */
1095	PDM_DEVREG_FLAGS_HOST_BITS_DEFAULT \| PDM_DEVREG_FLAGS_GUEST_BITS_32_64 \| PDM_DEVREG_FLAGS_PAE36 \| PDM_DEVREG_FLAGS_RC \| PDM_DEVREG_FLAGS_R0,
1096	/* fClass */
1097	PDM_DEVREG_CLASS_PIC,
1098	/* cMaxInstances */
1099	1,
1100	/* cbInstance */
1101	sizeof(DEVPIC),
1102	/* pfnConstruct */
1103	picConstruct,
1104	/* pfnDestruct */
1105	NULL,
1106	/* pfnRelocate */
1107	picRelocate,
1108	/* pfnMemSetup */
1109	NULL,
1110	/* pfnPowerOn */
1111	NULL,
1112	/* pfnReset */
1113	picReset,
1114	/* pfnSuspend */
1115	NULL,
1116	/* pfnResume */
1117	NULL,
1118	/* pfnAttach */
1119	NULL,
1120	/* pfnDetach */
1121	NULL,
1122	/* pfnQueryInterface. */
1123	NULL,
1124	/* pfnInitComplete */
1125	NULL,
1126	/* pfnPowerOff */
1127	NULL,
1128	/* pfnSoftReset */
1129	NULL,
1130	/* u32VersionEnd */
1131	PDM_DEVREG_VERSION
1132	};
1133
1134	#endif /* IN_RING3 */
1135	#endif /* !VBOX_DEVICE_STRUCT_TESTCASE */
1136

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source: vbox/trunk/src/VBox/Devices/PC/DevPIC.cpp@ 62564

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