DevPIC.cpp@ 61

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1	/** @file
2	*
3	* VBox basic PC devices:
4	* Intel 8259 Programmable Interrupt Controller.
5	*/
6
7	/*
8	* Copyright (C) 2006 InnoTek Systemberatung GmbH
9	*
10	* This file is part of VirtualBox Open Source Edition (OSE), as
11	* available from http://www.virtualbox.org. This file is free software;
12	* you can redistribute it and/or modify it under the terms of the GNU
13	* General Public License as published by the Free Software Foundation,
14	* in version 2 as it comes in the "COPYING" file of the VirtualBox OSE
15	* distribution. VirtualBox OSE is distributed in the hope that it will
16	* be useful, but WITHOUT ANY WARRANTY of any kind.
17	*
18	* If you received this file as part of a commercial VirtualBox
19	* distribution, then only the terms of your commercial VirtualBox
20	* license agreement apply instead of the previous paragraph.
21	*/
22
23	/*******************************************************************************
24	* Header Files *
25	*******************************************************************************/
26	#define LOG_GROUP LOG_GROUP_DEV_PIC
27	#include <VBox/pdm.h>
28	#include <VBox/log.h>
29	#include <iprt/assert.h>
30
31	#include "vl_vbox.h"
32
33
34	/*******************************************************************************
35	* Defined Constants And Macros *
36	*******************************************************************************/
37	/** @def PIC_LOCK
38	* Acquires the PDM lock. This is a NOP if locking is disabled. */
39	/** @def PIC_UNLOCK
40	* Releases the PDM lock. This is a NOP if locking is disabled. */
41	#ifdef VBOX_WITH_PDM_LOCK
42	# define PIC_LOCK(pThis, rc) \
43	do { \
44	int rc2 = (pThis)->CTXALLSUFF(pPicHlp)->pfnLock((pThis)->CTXSUFF(pDevIns), rc); \
45	if (rc2 != VINF_SUCCESS) \
46	return rc2; \
47	} while (0)
48	# define PIC_UNLOCK(pThis) \
49	(pThis)->CTXALLSUFF(pPicHlp)->pfnUnlock((pThis)->CTXSUFF(pDevIns))
50	#else /* !VBOX_WITH_PDM_LOCK */
51	# define PIC_LOCK(pThis, rc) do { } while (0)
52	# define PIC_UNLOCK(pThis) do { } while (0)
53	#endif /* !VBOX_WITH_PDM_LOCK */
54
55
56	/*******************************************************************************
57	* Internal Functions *
58	*******************************************************************************/
59	__BEGIN_DECLS
60
61	PDMBOTHCBDECL(void) picSetIrq(PPDMDEVINS pDevIns, int iIrq, int iLevel);
62	PDMBOTHCBDECL(int) picGetInterrupt(PPDMDEVINS pDevIns);
63	PDMBOTHCBDECL(int) picIOPortRead(PPDMDEVINS pDevIns, void pvUser, RTIOPORT Port, uint32_t pu32, unsigned cb);
64	PDMBOTHCBDECL(int) picIOPortWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb);
65	PDMBOTHCBDECL(int) picIOPortElcrRead(PPDMDEVINS pDevIns, void pvUser, RTIOPORT Port, uint32_t pu32, unsigned cb);
66	PDMBOTHCBDECL(int) picIOPortElcrWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb);
67
68	__END_DECLS
69
70
71	/*
72	* QEMU 8259 interrupt controller emulation
73	*
74	* Copyright (c) 2003-2004 Fabrice Bellard
75	*
76	* Permission is hereby granted, free of charge, to any person obtaining a copy
77	* of this software and associated documentation files (the "Software"), to deal
78	* in the Software without restriction, including without limitation the rights
79	* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
80	* copies of the Software, and to permit persons to whom the Software is
81	* furnished to do so, subject to the following conditions:
82	*
83	* The above copyright notice and this permission notice shall be included in
84	* all copies or substantial portions of the Software.
85	*
86	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
87	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
88	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
89	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
90	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
91	* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
92	* THE SOFTWARE.
93	*/
94
95	/* debug PIC */
96	#define DEBUG_PIC
97
98	/#define DEBUG_IRQ_COUNT/
99
100	typedef struct PicState {
101	uint8_t last_irr; /* edge detection */
102	uint8_t irr; /* interrupt request register */
103	uint8_t imr; /* interrupt mask register */
104	uint8_t isr; /* interrupt service register */
105	uint8_t priority_add; /* highest irq priority */
106	uint8_t irq_base;
107	uint8_t read_reg_select;
108	uint8_t poll;
109	uint8_t special_mask;
110	uint8_t init_state;
111	uint8_t auto_eoi;
112	uint8_t rotate_on_auto_eoi;
113	uint8_t special_fully_nested_mode;
114	uint8_t init4; /* true if 4 byte init */
115	uint8_t elcr; /* PIIX edge/trigger selection*/
116	uint8_t elcr_mask;
117	/** Pointer to the device instance, HCPtr. */
118	HCPTRTYPE(PPDMDEVINS) pDevInsHC;
119	/** Pointer to the device instance, GCPtr. */
120	GCPTRTYPE(PPDMDEVINS) pDevInsGC;
121	} PicState;
122
123	/**
124	* A PIC device instance data.
125	*/
126	typedef struct DEVPIC
127	{
128	/** The two interrupt controllers. */
129	PicState aPics[2];
130	/** Pointer to the device instance - GC Ptr. */
131	HCPTRTYPE(PPDMDEVINS) pDevInsHC;
132	/** Pointer to the device instance - GC Ptr. */
133	GCPTRTYPE(PPDMDEVINS) pDevInsGC;
134	/** Pointer to the PIC R3 helpers. */
135	PCPDMPICHLPR3 pPicHlpR3;
136	/** Pointer to the PIC GC helpers. */
137	PCPDMPICHLPGC pPicHlpGC;
138	/** Pointer to the PIC R0 helpers. */
139	PCPDMPICHLPR0 pPicHlpR0;
140	#ifdef VBOX_WITH_STATISTICS
141	STAMCOUNTER StatSetIrqGC;
142	STAMCOUNTER StatSetIrqHC;
143	STAMCOUNTER StatClearedActiveIRQ2;
144	STAMCOUNTER StatClearedActiveMasterIRQ;
145	STAMCOUNTER StatClearedActiveSlaveIRQ;
146	#endif
147	} DEVPIC, *PDEVPIC;
148
149	#ifdef LOG_ENABLED
150	static inline void DumpPICState(PicState s, char szFn)
151	{
152	PDEVPIC pData = PDMINS2DATA(CTXSUFF(s->pDevIns), PDEVPIC);
153
154	Log2(("%s: pic%d: elcr=%x last_irr=%x irr=%x imr=%x isr=%x irq_base=%x\n",
155	szFn, (&pData->aPics[0] == s) ? 0 : 1,
156	s->elcr, s->last_irr, s->irr, s->imr, s->isr, s->irq_base));
157	}
158	#else
159	# define DumpPICState(pData, szFn) do { } while (0)
160	#endif
161
162	/* set irq level. If an edge is detected, then the IRR is set to 1 */
163	static inline void pic_set_irq1(PicState *s, int irq, int level)
164	{
165	int mask;
166	Log(("pic_set_irq1: irq=%d level=%d\n", irq, level));
167	mask = 1 << irq;
168	if (s->elcr & mask) {
169	/* level triggered */
170	if (level) {
171	s->irr \|= mask;
172	s->last_irr \|= mask;
173	} else {
174	s->irr &= ~mask;
175	s->last_irr &= ~mask;
176	}
177	} else {
178	/* edge triggered */
179	if (level) {
180	if ((s->last_irr & mask) == 0)
181	{
182	Log2(("pic_set_irq1 irr=%x last_irr=%x\n", s->irr \| mask, s->last_irr));
183	s->irr \|= mask;
184	}
185	s->last_irr \|= mask;
186	} else {
187	s->last_irr &= ~mask;
188	}
189	}
190	DumpPICState(s, "pic_set_irq1");
191	}
192
193	/* return the highest priority found in mask (highest = smallest
194	number). Return 8 if no irq */
195	static inline int get_priority(PicState *s, int mask)
196	{
197	int priority;
198	if (mask == 0)
199	return 8;
200	priority = 0;
201	while ((mask & (1 << ((priority + s->priority_add) & 7))) == 0)
202	priority++;
203	return priority;
204	}
205
206	/* return the pic wanted interrupt. return -1 if none */
207	static int pic_get_irq(PicState *s)
208	{
209	PicState *pics = &(PDMINS2DATA(CTXSUFF(s->pDevIns), PDEVPIC))->aPics[0];
210	int mask, cur_priority, priority;
211	Log(("pic_get_irq%d: mask=%x\n", (s == pics) ? 0 : 1, s->irr & ~s->imr));
212	DumpPICState(s, "pic_get_irq");
213
214	mask = s->irr & ~s->imr;
215	priority = get_priority(s, mask);
216	Log(("pic_get_irq: priority=%x\n", priority));
217	if (priority == 8)
218	return -1;
219	/* compute current priority. If special fully nested mode on the
220	master, the IRQ coming from the slave is not taken into account
221	for the priority computation. */
222	mask = s->isr;
223	if (s->special_fully_nested_mode && s == &pics[0])
224	mask &= ~(1 << 2);
225	cur_priority = get_priority(s, mask);
226	Log(("pic_get_irq%d: cur_priority=%x pending=%d\n", (s == pics) ? 0 : 1, cur_priority, (priority == 8) ? -1 : (priority + s->priority_add) & 7));
227	if (priority < cur_priority) {
228	/* higher priority found: an irq should be generated */
229	return (priority + s->priority_add) & 7;
230	} else {
231	return -1;
232	}
233	}
234
235	/* raise irq to CPU if necessary. must be called every time the active
236	irq may change */
237	static int pic_update_irq(PDEVPIC pData)
238	{
239	PicState *pics = &pData->aPics[0];
240	int irq2, irq;
241
242	/* first look at slave pic */
243	irq2 = pic_get_irq(&pics[1]);
244	Log(("pic_update_irq irq2=%d\n", irq2));
245	if (irq2 >= 0) {
246	/* if irq request by slave pic, signal master PIC */
247	pic_set_irq1(&pics[0], 2, 1);
248	pic_set_irq1(&pics[0], 2, 0);
249	}
250	/* look at requested irq */
251	irq = pic_get_irq(&pics[0]);
252	if (irq >= 0)
253	{
254	/* If irq 2 is pending on the master pic, then there must be one pending on the slave pic too! Otherwise we'll get
255	* spurious slave interrupts in picGetInterrupt.
256	*/
257	if (irq != 2 \|\| irq2 != -1)
258	{
259	#if defined(DEBUG_PIC)
260	int i;
261	for(i = 0; i < 2; i++) {
262	Log(("pic%d: imr=%x irr=%x padd=%d\n",
263	i, pics[i].imr, pics[i].irr,
264	pics[i].priority_add));
265	}
266	Log(("pic: cpu_interrupt\n"));
267	#endif
268	pData->CTXALLSUFF(pPicHlp)->pfnSetInterruptFF(pData->CTXSUFF(pDevIns));
269	}
270	else
271	{
272	STAM_COUNTER_INC(&pData->StatClearedActiveIRQ2);
273	Log(("pic_update_irq: irq 2 is active, but no interrupt is pending on the slave pic!!\n"));
274	/* Clear it here, so lower priority interrupts can still be dispatched. */
275	/** @note Is this correct? */
276	pics[0].irr &= ~(1 << 2);
277	}
278	}
279	return VINF_SUCCESS;
280	}
281
282	/** @note if an interrupt line state changes from unmasked to masked, then it must be deactivated when currently pending! */
283	static void pic_update_imr(PDEVPIC pData, PicState *s, uint8_t val)
284	{
285	int irq, intno;
286	PicState *pActivePIC;
287
288	/* Query the current pending irq, if any. */
289	pActivePIC = &pData->aPics[0];
290	intno = irq = pic_get_irq(pActivePIC);
291	if (irq == 2)
292	{
293	pActivePIC = &pData->aPics[1];
294	irq = pic_get_irq(pActivePIC);
295	intno = irq + 8;
296	}
297
298	/* Update IMR */
299	s->imr = val;
300
301	/* If an interrupt is pending and now masked, then clear the FF flag. */
302	if ( irq >= 0
303	&& ((1 << irq) & ~pActivePIC->imr) == 0)
304	{
305	Log(("pic_update_imr: pic0: elcr=%x last_irr=%x irr=%x imr=%x isr=%x irq_base=%x\n",
306	pData->aPics[0].elcr, pData->aPics[0].last_irr, pData->aPics[0].irr, pData->aPics[0].imr, pData->aPics[0].isr, pData->aPics[0].irq_base));
307	Log(("pic_update_imr: pic1: elcr=%x last_irr=%x irr=%x imr=%x isr=%x irq_base=%x\n",
308	pData->aPics[1].elcr, pData->aPics[1].last_irr, pData->aPics[1].irr, pData->aPics[1].imr, pData->aPics[1].isr, pData->aPics[1].irq_base));
309
310	/* Clear pending IRQ 2 on master controller in case of slave interrupt. */
311	/** @todo Is this correct? */
312	if (intno > 7)
313	{
314	pData->aPics[0].irr &= ~(1 << 2);
315	STAM_COUNTER_INC(&pData->StatClearedActiveSlaveIRQ);
316	}
317	else
318	STAM_COUNTER_INC(&pData->StatClearedActiveMasterIRQ);
319
320	Log(("pic_update_imr: clear pending interrupt %d\n", intno));
321	pData->CTXALLSUFF(pPicHlp)->pfnClearInterruptFF(pData->CTXSUFF(pDevIns));
322	}
323	}
324
325
326	/**
327	* Set the an IRQ.
328	*
329	* @param pDevIns Device instance of the PICs.
330	* @param iIrq IRQ number to set.
331	* @param iLevel IRQ level.
332	*/
333	PDMBOTHCBDECL(void) picSetIrq(PPDMDEVINS pDevIns, int iIrq, int iLevel)
334	{
335	PDEVPIC pData = PDMINS2DATA(pDevIns, PDEVPIC);
336	Assert(pData->CTXSUFF(pDevIns) == pDevIns);
337	Assert(pData->aPics[0].CTXSUFF(pDevIns) == pDevIns);
338	Assert(pData->aPics[1].CTXSUFF(pDevIns) == pDevIns);
339	AssertMsg(iIrq < 16, ("iIrq=%d\n", iIrq));
340
341	Log(("picSetIrq %d %d\n", iIrq, iLevel));
342	DumpPICState(&pData->aPics[0], "picSetIrq");
343	DumpPICState(&pData->aPics[1], "picSetIrq");
344	STAM_COUNTER_INC(&pData->CTXSUFF(StatSetIrq));
345	pic_set_irq1(&pData->aPics[iIrq >> 3], iIrq & 7, iLevel);
346	pic_update_irq(pData);
347	}
348
349
350	/* acknowledge interrupt 'irq' */
351	static inline void pic_intack(PicState *s, int irq)
352	{
353	if (s->auto_eoi) {
354	if (s->rotate_on_auto_eoi)
355	s->priority_add = (irq + 1) & 7;
356	} else {
357	s->isr \|= (1 << irq);
358	}
359	/* We don't clear a level sensitive interrupt here */
360	if (!(s->elcr & (1 << irq)))
361	s->irr &= ~(1 << irq);
362	}
363
364
365	/**
366	* Get a pending interrupt.
367	*
368	* @returns Pending interrupt number.
369	* @param pDevIns Device instance of the PICs.
370	*/
371	PDMBOTHCBDECL(int) picGetInterrupt(PPDMDEVINS pDevIns)
372	{
373	PDEVPIC pData = PDMINS2DATA(pDevIns, PDEVPIC);
374	int irq;
375	int irq2;
376	int intno;
377
378	/* read the irq from the PIC */
379	DumpPICState(&pData->aPics[0], "picGetInterrupt");
380	DumpPICState(&pData->aPics[1], "picGetInterrupt");
381
382	irq = pic_get_irq(&pData->aPics[0]);
383	if (irq >= 0)
384	{
385	pic_intack(&pData->aPics[0], irq);
386	if (irq == 2)
387	{
388	irq2 = pic_get_irq(&pData->aPics[1]);
389	if (irq2 >= 0) {
390	pic_intack(&pData->aPics[1], irq2);
391	}
392	else
393	{
394	/* spurious IRQ on slave controller (impossible) */
395	AssertMsgFailed(("picGetInterrupt: spurious IRQ on slave controller\n"));
396	irq2 = 7;
397	}
398	intno = pData->aPics[1].irq_base + irq2;
399	Log2(("picGetInterrupt1: %x base=%x irq=%x\n", intno, pData->aPics[1].irq_base, irq2));
400	irq = irq2 + 8;
401	}
402	else {
403	intno = pData->aPics[0].irq_base + irq;
404	Log2(("picGetInterrupt0: %x base=%x irq=%x\n", intno, pData->aPics[0].irq_base, irq));
405	}
406	}
407	else
408	{
409	/* spurious IRQ on host controller (impossible) */
410	AssertMsgFailed(("picGetInterrupt: spurious IRQ on master controller\n"));
411	irq = 7;
412	intno = pData->aPics[0].irq_base + irq;
413	}
414	pic_update_irq(pData);
415
416	Log(("picGetInterrupt: pending 0:%d 1:%d\n", pic_get_irq(&pData->aPics[0]), pic_get_irq(&pData->aPics[1])));
417
418	return intno;
419	}
420
421	static void pic_reset(PicState *s)
422	{
423	HCPTRTYPE(PPDMDEVINS) pDevInsHC = s->pDevInsHC;
424	GCPTRTYPE(PPDMDEVINS) pDevInsGC = s->pDevInsGC;
425	int tmp, tmp2;
426
427	tmp = s->elcr_mask;
428	tmp2 = s->elcr;
429	memset(s, 0, sizeof(PicState));
430	s->elcr_mask = tmp;
431	s->elcr = tmp2;
432	s->pDevInsHC = pDevInsHC;
433	s->pDevInsGC = pDevInsGC;
434	}
435
436
437	static int pic_ioport_write(void *opaque, uint32_t addr, uint32_t val)
438	{
439	PicState s = (PicState)opaque;
440	PDEVPIC pData = PDMINS2DATA(CTXSUFF(s->pDevIns), PDEVPIC);
441	int rc = VINF_SUCCESS;
442	int priority, cmd, irq;
443
444	Log(("pic_write: addr=0x%02x val=0x%02x\n", addr, val));
445	addr &= 1;
446	if (addr == 0) {
447	if (val & 0x10) {
448	/* init */
449	pic_reset(s);
450	/* deassert a pending interrupt */
451	pData->CTXALLSUFF(pPicHlp)->pfnClearInterruptFF(pData->CTXSUFF(pDevIns));
452
453	s->init_state = 1;
454	s->init4 = val & 1;
455	if (val & 0x02)
456	AssertReleaseMsgFailed(("single mode not supported"));
457	if (val & 0x08)
458	AssertReleaseMsgFailed(("level sensitive irq not supported"));
459	} else if (val & 0x08) {
460	if (val & 0x04)
461	s->poll = 1;
462	if (val & 0x02)
463	s->read_reg_select = val & 1;
464	if (val & 0x40)
465	s->special_mask = (val >> 5) & 1;
466	} else {
467	cmd = val >> 5;
468	switch(cmd) {
469	case 0:
470	case 4:
471	s->rotate_on_auto_eoi = cmd >> 2;
472	break;
473	case 1: /* end of interrupt */
474	case 5:
475	{
476	priority = get_priority(s, s->isr);
477	if (priority != 8) {
478	irq = (priority + s->priority_add) & 7;
479	Log(("pic_write: EOI prio=%d irq=%d\n", priority, irq));
480	s->isr &= ~(1 << irq);
481	if (cmd == 5)
482	s->priority_add = (irq + 1) & 7;
483	rc = pic_update_irq(pData);
484	Assert(rc == VINF_SUCCESS);
485	}
486	break;
487	}
488	case 3:
489	{
490	irq = val & 7;
491	Log(("pic_write: EOI2 for irq %d\n", irq));
492	s->isr &= ~(1 << irq);
493	rc = pic_update_irq(pData);
494	Assert(rc == VINF_SUCCESS);
495	break;
496	}
497	case 6:
498	{
499	s->priority_add = (val + 1) & 7;
500	rc = pic_update_irq(pData);
501	Assert(rc == VINF_SUCCESS);
502	break;
503	}
504	case 7:
505	{
506	irq = val & 7;
507	Log(("pic_write: EOI3 for irq %d\n", irq));
508	s->isr &= ~(1 << irq);
509	s->priority_add = (irq + 1) & 7;
510	rc = pic_update_irq(pData);
511	Assert(rc == VINF_SUCCESS);
512	break;
513	}
514	default:
515	/* no operation */
516	break;
517	}
518	}
519	} else {
520	switch(s->init_state) {
521	case 0:
522	{
523	/* normal mode */
524	pic_update_imr(pData, s, val);
525
526	rc = pic_update_irq(pData);
527	Assert(rc == VINF_SUCCESS);
528	break;
529	}
530	case 1:
531	s->irq_base = val & 0xf8;
532	s->init_state = 2;
533	Log(("pic_write: set irq base to %x\n", s->irq_base));
534	break;
535	case 2:
536	if (s->init4) {
537	s->init_state = 3;
538	} else {
539	s->init_state = 0;
540	}
541	break;
542	case 3:
543	s->special_fully_nested_mode = (val >> 4) & 1;
544	s->auto_eoi = (val >> 1) & 1;
545	s->init_state = 0;
546	Log(("pic_write: special_fully_nested_mode=%d auto_eoi=%d\n", s->special_fully_nested_mode, s->auto_eoi));
547	break;
548	}
549	}
550	return rc;
551	}
552
553
554	static uint32_t pic_poll_read (PicState *s, uint32_t addr1)
555	{
556	PDEVPIC pData = PDMINS2DATA(CTXSUFF(s->pDevIns), PDEVPIC);
557	PicState *pics = &pData->aPics[0];
558	int ret;
559
560	ret = pic_get_irq(s);
561	if (ret >= 0) {
562	if (addr1 >> 7) {
563	Log2(("pic_poll_read: clear slave irq (isr)\n"));
564	pics[0].isr &= ~(1 << 2);
565	pics[0].irr &= ~(1 << 2);
566	}
567	Log2(("pic_poll_read: clear irq %d (isr)\n", ret));
568	s->irr &= ~(1 << ret);
569	s->isr &= ~(1 << ret);
570	if (addr1 >> 7 \|\| ret != 2)
571	pic_update_irq(pData);
572	} else {
573	ret = 0x07;
574	pic_update_irq(pData);
575	}
576
577	return ret;
578	}
579
580
581	static uint32_t pic_ioport_read(void opaque, uint32_t addr1, int pRC)
582	{
583	PicState s = (PicState)opaque;
584	unsigned int addr;
585	int ret;
586
587	*pRC = VINF_SUCCESS;
588
589	addr = addr1;
590	addr &= 1;
591	if (s->poll) {
592	ret = pic_poll_read(s, addr1);
593	s->poll = 0;
594	} else {
595	if (addr == 0) {
596	if (s->read_reg_select)
597	ret = s->isr;
598	else
599	ret = s->irr;
600	} else {
601	ret = s->imr;
602	}
603	}
604	Log(("pic_read: addr=0x%02x val=0x%02x\n", addr1, ret));
605	return ret;
606	}
607
608
609
610	#ifdef IN_RING3
611
612	static void pic_save(QEMUFile f, void opaque)
613	{
614	PicState s = (PicState)opaque;
615
616	qemu_put_8s(f, &s->last_irr);
617	qemu_put_8s(f, &s->irr);
618	qemu_put_8s(f, &s->imr);
619	qemu_put_8s(f, &s->isr);
620	qemu_put_8s(f, &s->priority_add);
621	qemu_put_8s(f, &s->irq_base);
622	qemu_put_8s(f, &s->read_reg_select);
623	qemu_put_8s(f, &s->poll);
624	qemu_put_8s(f, &s->special_mask);
625	qemu_put_8s(f, &s->init_state);
626	qemu_put_8s(f, &s->auto_eoi);
627	qemu_put_8s(f, &s->rotate_on_auto_eoi);
628	qemu_put_8s(f, &s->special_fully_nested_mode);
629	qemu_put_8s(f, &s->init4);
630	qemu_put_8s(f, &s->elcr);
631	}
632
633	static int pic_load(QEMUFile f, void opaque, int version_id)
634	{
635	PicState s = (PicState)opaque;
636
637	if (version_id != 1)
638	return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
639
640	qemu_get_8s(f, &s->last_irr);
641	qemu_get_8s(f, &s->irr);
642	qemu_get_8s(f, &s->imr);
643	qemu_get_8s(f, &s->isr);
644	qemu_get_8s(f, &s->priority_add);
645	qemu_get_8s(f, &s->irq_base);
646	qemu_get_8s(f, &s->read_reg_select);
647	qemu_get_8s(f, &s->poll);
648	qemu_get_8s(f, &s->special_mask);
649	qemu_get_8s(f, &s->init_state);
650	qemu_get_8s(f, &s->auto_eoi);
651	qemu_get_8s(f, &s->rotate_on_auto_eoi);
652	qemu_get_8s(f, &s->special_fully_nested_mode);
653	qemu_get_8s(f, &s->init4);
654	qemu_get_8s(f, &s->elcr);
655	return 0;
656	}
657	#endif /* IN_RING3 */
658
659
660	/* -=-=-=-=-=- wrappers -=-=-=-=-=- */
661
662	/**
663	* Port I/O Handler for IN operations.
664	*
665	* @returns VBox status code.
666	*
667	* @param pDevIns The device instance.
668	* @param pvUser User argument - pointer to the PIC in question.
669	* @param uPort Port number used for the IN operation.
670	* @param pu32 Where to store the result.
671	* @param cb Number of bytes read.
672	*/
673	PDMBOTHCBDECL(int) picIOPortRead(PPDMDEVINS pDevIns, void pvUser, RTIOPORT Port, uint32_t pu32, unsigned cb)
674	{
675	PDEVPIC pData = PDMINS2DATA(pDevIns, PDEVPIC);
676	uint32_t iPic = (uint32_t)pvUser;
677
678	Assert(iPic == 0 \|\| iPic == 1);
679	if (cb == 1)
680	{
681	int rc;
682	PIC_LOCK(pData, VINF_IOM_HC_IOPORT_READ);
683	*pu32 = pic_ioport_read(&pData->aPics[iPic], Port, &rc);
684	PIC_UNLOCK(pData);
685	return rc;
686	}
687	return VERR_IOM_IOPORT_UNUSED;
688	}
689
690	/**
691	* Port I/O Handler for OUT operations.
692	*
693	* @returns VBox status code.
694	*
695	* @param pDevIns The device instance.
696	* @param pvUser User argument - pointer to the PIC in question.
697	* @param uPort Port number used for the IN operation.
698	* @param u32 The value to output.
699	* @param cb The value size in bytes.
700	*/
701	PDMBOTHCBDECL(int) picIOPortWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb)
702	{
703	PDEVPIC pData = PDMINS2DATA(pDevIns, PDEVPIC);
704	uint32_t iPic = (uint32_t)pvUser;
705
706	Assert(iPic == 0 \|\| iPic == 1);
707
708	if (cb == 1)
709	{
710	int rc;
711	PIC_LOCK(pData, VINF_IOM_HC_IOPORT_WRITE);
712	rc = pic_ioport_write(&pData->aPics[iPic], Port, u32);
713	PIC_UNLOCK(pData);
714	return rc;
715	}
716	return VINF_SUCCESS;
717	}
718
719
720	/**
721	* Port I/O Handler for IN operations.
722	*
723	* @returns VBox status code.
724	*
725	* @param pDevIns The device instance.
726	* @param pvUser User argument - pointer to the PIC in question.
727	* @param uPort Port number used for the IN operation.
728	* @param pu32 Where to store the result.
729	* @param cb Number of bytes read.
730	*/
731	PDMBOTHCBDECL(int) picIOPortElcrRead(PPDMDEVINS pDevIns, void pvUser, RTIOPORT Port, uint32_t pu32, unsigned cb)
732	{
733	if (cb == 1)
734	{
735	PicState s = (PicState)pvUser;
736	PIC_LOCK(PDMINS2DATA(pDevIns, PDEVPIC), VINF_IOM_HC_IOPORT_READ);
737	*pu32 = s->elcr;
738	PIC_UNLOCK(PDMINS2DATA(pDevIns, PDEVPIC));
739	return VINF_SUCCESS;
740	}
741	return VERR_IOM_IOPORT_UNUSED;
742	}
743
744	/**
745	* Port I/O Handler for OUT operations.
746	*
747	* @returns VBox status code.
748	*
749	* @param pDevIns The device instance.
750	* @param pvUser User argument - pointer to the PIC in question.
751	* @param uPort Port number used for the IN operation.
752	* @param u32 The value to output.
753	* @param cb The value size in bytes.
754	*/
755	PDMBOTHCBDECL(int) picIOPortElcrWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb)
756	{
757	if (cb == 1)
758	{
759	PicState s = (PicState)pvUser;
760	PIC_LOCK(PDMINS2DATA(pDevIns, PDEVPIC), VINF_IOM_HC_IOPORT_WRITE);
761	s->elcr = u32 & s->elcr_mask;
762	PIC_UNLOCK(PDMINS2DATA(pDevIns, PDEVPIC));
763	}
764	return VINF_SUCCESS;
765	}
766
767
768	#ifdef IN_RING3
769
770	#ifdef DEBUG
771	/**
772	* PIC status info callback.
773	*
774	* @param pDevIns The device instance.
775	* @param pHlp The output helpers.
776	* @param pszArgs The arguments.
777	*/
778	static DECLCALLBACK(void) picInfo(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
779	{
780	PDEVPIC pData = PDMINS2DATA(pDevIns, PDEVPIC);
781
782	/*
783	* Show info.
784	*/
785	for (int i=0;i<2;i++)
786	{
787	pHlp->pfnPrintf(pHlp, "PIC%d:\n", i);
788	pHlp->pfnPrintf(pHlp, " last_irr = %02x\n", pData->aPics[i].last_irr);
789	pHlp->pfnPrintf(pHlp, " irr = %02x\n", pData->aPics[i].irr);
790	pHlp->pfnPrintf(pHlp, " imr = %02x\n", pData->aPics[i].imr);
791	pHlp->pfnPrintf(pHlp, " isr = %02x\n", pData->aPics[i].isr);
792	pHlp->pfnPrintf(pHlp, " priority_add = %02x\n", pData->aPics[i].priority_add);
793	pHlp->pfnPrintf(pHlp, " irq_base = %02x\n", pData->aPics[i].irq_base);
794	pHlp->pfnPrintf(pHlp, " read_reg_select = %02x\n", pData->aPics[i].read_reg_select);
795	pHlp->pfnPrintf(pHlp, " poll = %02x\n", pData->aPics[i].poll);
796	pHlp->pfnPrintf(pHlp, " special_mask = %02x\n", pData->aPics[i].special_mask);
797	pHlp->pfnPrintf(pHlp, " init_state = %02x\n", pData->aPics[i].init_state);
798	pHlp->pfnPrintf(pHlp, " auto_eoi = %02x\n", pData->aPics[i].auto_eoi);
799	pHlp->pfnPrintf(pHlp, " rotate_on_auto_eoi = %02x\n", pData->aPics[i].rotate_on_auto_eoi);
800	pHlp->pfnPrintf(pHlp, " special_fully_nested_mode = %02x\n", pData->aPics[i].special_fully_nested_mode);
801	pHlp->pfnPrintf(pHlp, " init4 = %02x\n", pData->aPics[i].init4);
802	pHlp->pfnPrintf(pHlp, " elcr = %02x\n", pData->aPics[i].elcr);
803	pHlp->pfnPrintf(pHlp, " elcr_mask = %02x\n", pData->aPics[i].elcr_mask);
804	}
805	}
806	#endif /* DEBUG */
807
808	/**
809	* Saves a state of the programmable interrupt controller device.
810	*
811	* @returns VBox status code.
812	* @param pDevIns The device instance.
813	* @param pSSMHandle The handle to save the state to.
814	*/
815	static DECLCALLBACK(int) picSaveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSMHandle)
816	{
817	PDEVPIC pData = PDMINS2DATA(pDevIns, PDEVPIC);
818	pic_save(pSSMHandle, &pData->aPics[0]);
819	pic_save(pSSMHandle, &pData->aPics[1]);
820	return VINF_SUCCESS;
821	}
822
823
824	/**
825	* Loads a saved programmable interrupt controller device state.
826	*
827	* @returns VBox status code.
828	* @param pDevIns The device instance.
829	* @param pSSMHandle The handle to the saved state.
830	* @param u32Version The data unit version number.
831	*/
832	static DECLCALLBACK(int) picLoadExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSMHandle, uint32_t u32Version)
833	{
834	PDEVPIC pData = PDMINS2DATA(pDevIns, PDEVPIC);
835	int rc = pic_load(pSSMHandle, &pData->aPics[0], u32Version);
836	if (VBOX_SUCCESS(rc))
837	rc = pic_load(pSSMHandle, &pData->aPics[1], u32Version);
838	return rc;
839	}
840
841
842	/* -=-=-=-=-=- real code -=-=-=-=-=- */
843
844	/**
845	* Reset notification.
846	*
847	* @returns VBox status.
848	* @param pDevIns The device instance data.
849	*/
850	static DECLCALLBACK(void) picReset(PPDMDEVINS pDevIns)
851	{
852	PDEVPIC pData = PDMINS2DATA(pDevIns, PDEVPIC);
853	unsigned i;
854	LogFlow(("picReset:\n"));
855	#ifdef VBOX_WITH_PDM_LOCK
856	pData->pPicHlpR3->pfnLock(pDevIns, VERR_INTERNAL_ERROR);
857	#endif
858
859	for (i = 0; i < ELEMENTS(pData->aPics); i++)
860	pic_reset(&pData->aPics[i]);
861
862	PIC_UNLOCK(pData);
863	}
864
865
866	/**
867	* @copydoc FNPDMDEVRELOCATE
868	*/
869	static DECLCALLBACK(void) picRelocate(PPDMDEVINS pDevIns, RTGCINTPTR offDelta)
870	{
871	PDEVPIC pData = PDMINS2DATA(pDevIns, PDEVPIC);
872	unsigned i;
873
874	pData->pDevInsGC = PDMDEVINS_2_GCPTR(pDevIns);
875	pData->pPicHlpGC = pData->pPicHlpR3->pfnGetGCHelpers(pDevIns);
876	for (i = 0; i < ELEMENTS(pData->aPics); i++)
877	pData->aPics[i].pDevInsGC = PDMDEVINS_2_GCPTR(pDevIns);
878	}
879
880
881	/**
882	* @copydoc FNPDMDEVCONSTRUCT
883	*/
884	static DECLCALLBACK(int) picConstruct(PPDMDEVINS pDevIns, int iInstance, PCFGMNODE pCfgHandle)
885	{
886	PDEVPIC pData = PDMINS2DATA(pDevIns, PDEVPIC);
887	PDMPICREG PicReg;
888	int rc;
889	bool fGCEnabled;
890	bool fR0Enabled;
891	Assert(iInstance == 0);
892
893	/*
894	* Validate and read configuration.
895	*/
896	if (!CFGMR3AreValuesValid(pCfgHandle, "GCEnabled\0R0Enabled\0"))
897	return VERR_PDM_DEVINS_UNKNOWN_CFG_VALUES;
898
899	rc = CFGMR3QueryBool(pCfgHandle, "GCEnabled", &fGCEnabled);
900	if (rc == VERR_CFGM_VALUE_NOT_FOUND)
901	fGCEnabled = true;
902	else if (VBOX_FAILURE(rc))
903	return PDMDEV_SET_ERROR(pDevIns, rc,
904	N_("Configuration error: failed to read GCEnabled as boolean"));
905
906	rc = CFGMR3QueryBool(pCfgHandle, "R0Enabled", &fR0Enabled);
907	if (rc == VERR_CFGM_VALUE_NOT_FOUND)
908	fR0Enabled = true;
909	else if (VBOX_FAILURE(rc))
910	return PDMDEV_SET_ERROR(pDevIns, rc,
911	N_("Configuration error: failed to read R0Enabled as boolean"));
912
913	Log(("i8259: fGCEnabled=%d fR0Enabled=%d\n", fGCEnabled, fR0Enabled));
914
915	/*
916	* Init the data.
917	*/
918	Assert(ELEMENTS(pData->aPics) == 2);
919	pData->pDevInsHC = pDevIns;
920	pData->pDevInsGC = PDMDEVINS_2_GCPTR(pDevIns);
921	pData->aPics[0].elcr_mask = 0xf8;
922	pData->aPics[1].elcr_mask = 0xde;
923	pData->aPics[0].pDevInsHC = pDevIns;
924	pData->aPics[1].pDevInsHC = pDevIns;
925	pData->aPics[0].pDevInsGC = PDMDEVINS_2_GCPTR(pDevIns);
926	pData->aPics[1].pDevInsGC = PDMDEVINS_2_GCPTR(pDevIns);
927
928	/*
929	* Register PIC, I/O ports and save state.
930	*/
931	PicReg.u32Version = PDM_PICREG_VERSION;
932	PicReg.pfnSetIrqHC = picSetIrq;
933	PicReg.pfnGetInterruptHC = picGetInterrupt;
934	if (fGCEnabled)
935	{
936	PicReg.pszSetIrqGC = "picSetIrq";
937	PicReg.pszGetInterruptGC = "picGetInterrupt";
938	}
939	else
940	{
941	PicReg.pszSetIrqGC = NULL;
942	PicReg.pszGetInterruptGC = NULL;
943	}
944
945	if (fR0Enabled)
946	{
947	PicReg.pszSetIrqR0 = "picSetIrq";
948	PicReg.pszGetInterruptR0 = "picGetInterrupt";
949	}
950	else
951	{
952	PicReg.pszSetIrqR0 = NULL;
953	PicReg.pszGetInterruptR0 = NULL;
954	}
955
956	Assert(pDevIns->pDevHlp->pfnPICRegister);
957	rc = pDevIns->pDevHlp->pfnPICRegister(pDevIns, &PicReg, &pData->pPicHlpR3);
958	if (VBOX_FAILURE(rc))
959	{
960	AssertMsgFailed(("PICRegister -> %Vrc\n", rc));
961	return rc;
962	}
963	if (fGCEnabled)
964	pData->pPicHlpGC = pData->pPicHlpR3->pfnGetGCHelpers(pDevIns);
965	rc = PDMDevHlpIOPortRegister(pDevIns, 0x20, 2, (void *)0, picIOPortWrite, picIOPortRead, NULL, NULL, "i8259 PIC #0");
966	if (VBOX_FAILURE(rc))
967	return rc;
968	rc = PDMDevHlpIOPortRegister(pDevIns, 0xa0, 2, (void *)1, picIOPortWrite, picIOPortRead, NULL, NULL, "i8259 PIC #1");
969	if (VBOX_FAILURE(rc))
970	return rc;
971	if (fGCEnabled)
972	{
973	rc = PDMDevHlpIOPortRegisterGC(pDevIns, 0x20, 2, 0, "picIOPortWrite", "picIOPortRead", NULL, NULL, "i8259 PIC #0");
974	if (VBOX_FAILURE(rc))
975	return rc;
976	rc = PDMDevHlpIOPortRegisterGC(pDevIns, 0xa0, 2, 1, "picIOPortWrite", "picIOPortRead", NULL, NULL, "i8259 PIC #1");
977	if (VBOX_FAILURE(rc))
978	return rc;
979	}
980	if (fR0Enabled)
981	{
982	pData->pPicHlpR0 = pData->pPicHlpR3->pfnGetR0Helpers(pDevIns);
983
984	rc = PDMDevHlpIOPortRegisterR0(pDevIns, 0x20, 2, (void *)0, "picIOPortWrite", "picIOPortRead", NULL, NULL, "i8259 PIC #0");
985	if (VBOX_FAILURE(rc))
986	return rc;
987	rc = PDMDevHlpIOPortRegisterR0(pDevIns, 0xa0, 2, (void *)1, "picIOPortWrite", "picIOPortRead", NULL, NULL, "i8259 PIC #1");
988	if (VBOX_FAILURE(rc))
989	return rc;
990	}
991
992	rc = PDMDevHlpIOPortRegister(pDevIns, 0x4d0, 1, &pData->aPics[0],
993	picIOPortElcrWrite, picIOPortElcrRead, NULL, NULL, "i8259 PIC #0 - elcr");
994	if (VBOX_FAILURE(rc))
995	return rc;
996	rc = PDMDevHlpIOPortRegister(pDevIns, 0x4d1, 1, &pData->aPics[1],
997	picIOPortElcrWrite, picIOPortElcrRead, NULL, NULL, "i8259 PIC #1 - elcr");
998	if (VBOX_FAILURE(rc))
999	return rc;
1000	if (fGCEnabled)
1001	{
1002	RTGCPTR pDataGC = PDMINS2DATA_GCPTR(pDevIns);
1003	rc = PDMDevHlpIOPortRegisterGC(pDevIns, 0x4d0, 1, pDataGC + RT_OFFSETOF(DEVPIC, aPics[0]),
1004	"picIOPortElcrWrite", "picIOPortElcrRead", NULL, NULL, "i8259 PIC #0 - elcr");
1005	if (VBOX_FAILURE(rc))
1006	return rc;
1007	rc = PDMDevHlpIOPortRegisterGC(pDevIns, 0x4d1, 1, pDataGC + RT_OFFSETOF(DEVPIC, aPics[1]),
1008	"picIOPortElcrWrite", "picIOPortElcrRead", NULL, NULL, "i8259 PIC #1 - elcr");
1009	if (VBOX_FAILURE(rc))
1010	return rc;
1011	}
1012	if (fR0Enabled)
1013	{
1014	rc = PDMDevHlpIOPortRegisterR0(pDevIns, 0x4d0, 1, &pData->aPics[0],
1015	"picIOPortElcrWrite", "picIOPortElcrRead", NULL, NULL, "i8259 PIC #0 - elcr");
1016	if (VBOX_FAILURE(rc))
1017	return rc;
1018	rc = PDMDevHlpIOPortRegisterR0(pDevIns, 0x4d1, 1, &pData->aPics[1],
1019	"picIOPortElcrWrite", "picIOPortElcrRead", NULL, NULL, "i8259 PIC #1 - elcr");
1020	if (VBOX_FAILURE(rc))
1021	return rc;
1022	}
1023
1024	rc = PDMDevHlpSSMRegister(pDevIns, pDevIns->pDevReg->szDeviceName, iInstance, 1 /* version /, sizeof(pData),
1025	NULL, picSaveExec, NULL,
1026	NULL, picLoadExec, NULL);
1027	if (VBOX_FAILURE(rc))
1028	return rc;
1029
1030
1031	#ifdef DEBUG
1032	/*
1033	* Register the info item.
1034	*/
1035	PDMDevHlpDBGFInfoRegister(pDevIns, "pic", "PIC info.", picInfo);
1036	#endif
1037
1038	/*
1039	* Initialize the device state.
1040	*/
1041	picReset(pDevIns);
1042
1043	#ifdef VBOX_WITH_STATISTICS
1044	/*
1045	* Statistics.
1046	*/
1047	PDMDevHlpSTAMRegister(pDevIns, &pData->StatSetIrqGC, STAMTYPE_COUNTER, "/PDM/PIC/SetIrqGC", STAMUNIT_OCCURENCES, "Number of PIC SetIrq calls in GC.");
1048	PDMDevHlpSTAMRegister(pDevIns, &pData->StatSetIrqHC, STAMTYPE_COUNTER, "/PDM/PIC/SetIrqHC", STAMUNIT_OCCURENCES, "Number of PIC SetIrq calls in HC.");
1049
1050	PDMDevHlpSTAMRegister(pDevIns, &pData->StatClearedActiveIRQ2, STAMTYPE_COUNTER, "/PDM/PIC/Masked/ActiveIRQ2", STAMUNIT_OCCURENCES, "Number of cleared irq 2.");
1051	PDMDevHlpSTAMRegister(pDevIns, &pData->StatClearedActiveMasterIRQ, STAMTYPE_COUNTER, "/PDM/PIC/Masked/ActiveMaster", STAMUNIT_OCCURENCES, "Number of cleared master irqs.");
1052	PDMDevHlpSTAMRegister(pDevIns, &pData->StatClearedActiveSlaveIRQ, STAMTYPE_COUNTER, "/PDM/PIC/Masked/ActiveSlave", STAMUNIT_OCCURENCES, "Number of cleared slave irqs.");
1053	#endif
1054
1055	return VINF_SUCCESS;
1056	}
1057
1058
1059	/**
1060	* The device registration structure.
1061	*/
1062	const PDMDEVREG g_DeviceI8259 =
1063	{
1064	/* u32Version */
1065	PDM_DEVREG_VERSION,
1066	/* szDeviceName */
1067	"i8259",
1068	/* szGCMod */
1069	"VBoxDDGC.gc",
1070	/* szR0Mod */
1071	"VBoxDDR0.r0",
1072	/* pszDescription */
1073	"i8259 Programmable Interrupt Controller",
1074	/* fFlags */
1075	PDM_DEVREG_FLAGS_HOST_BITS_DEFAULT \| PDM_DEVREG_FLAGS_GUEST_BITS_32_64 \| PDM_DEVREG_FLAGS_PAE36 \| PDM_DEVREG_FLAGS_GC \| PDM_DEVREG_FLAGS_R0,
1076	/* fClass */
1077	PDM_DEVREG_CLASS_PIC,
1078	/* cMaxInstances */
1079	1,
1080	/* cbInstance */
1081	sizeof(DEVPIC),
1082	/* pfnConstruct */
1083	picConstruct,
1084	/* pfnDestruct */
1085	NULL,
1086	/* pfnRelocate */
1087	picRelocate,
1088	/* pfnIOCtl */
1089	NULL,
1090	/* pfnPowerOn */
1091	NULL,
1092	/* pfnReset */
1093	picReset,
1094	/* pfnSuspend */
1095	NULL,
1096	/* pfnResume */
1097	NULL,
1098	/* pfnAttach */
1099	NULL,
1100	/* pfnDetach */
1101	NULL,
1102	/* pfnQueryInterface. */
1103	NULL
1104	};
1105
1106	#endif /* IN_RING3 */
1107
1108

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source: vbox/trunk/src/VBox/Devices/PC/DevPIC.cpp@ 61

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