DevPIC.cpp@ 46845

Last change on this file since 46845 was 45025, checked in by vboxsync, 12 years ago
Update PDMDEVREG initialization comment so they refer to pfnMemSetup instead of pfnIOCtl.
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1	/* $Id: DevPIC.cpp 45025 2013-03-13 16:45:15Z vboxsync $ */
2	/** @file
3	* DevPIC - Intel 8259 Programmable Interrupt Controller (PIC) Device.
4	*/
5
6	/*
7	* Copyright (C) 2006-2013 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	* -------------------------------------------------------------------
17	*
18	* This code is based on:
19	*
20	* QEMU 8259 interrupt controller emulation
21	*
22	* Copyright (c) 2003-2004 Fabrice Bellard
23	*
24	* Permission is hereby granted, free of charge, to any person obtaining a copy
25	* of this software and associated documentation files (the "Software"), to deal
26	* in the Software without restriction, including without limitation the rights
27	* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
28	* copies of the Software, and to permit persons to whom the Software is
29	* furnished to do so, subject to the following conditions:
30	*
31	* The above copyright notice and this permission notice shall be included in
32	* all copies or substantial portions of the Software.
33	*
34	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
35	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
36	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
37	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
38	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
39	* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
40	* THE SOFTWARE.
41	*
42	*/
43
44
45	/*******************************************************************************
46	* Header Files *
47	*******************************************************************************/
48	#define LOG_GROUP LOG_GROUP_DEV_PIC
49	#include <VBox/vmm/pdmdev.h>
50	#include <VBox/log.h>
51	#include <iprt/assert.h>
52	#include <iprt/string.h>
53
54	#include "VBoxDD.h"
55
56
57	/*******************************************************************************
58	* Defined Constants And Macros *
59	*******************************************************************************/
60	/** @def PIC_LOCK
61	* Acquires the PDM lock. This is a NOP if locking is disabled. */
62	/** @def PIC_UNLOCK
63	* Releases the PDM lock. This is a NOP if locking is disabled. */
64	#define PIC_LOCK(pThis, rc) \
65	do { \
66	int rc2 = (pThis)->CTX_SUFF(pPicHlp)->pfnLock((pThis)->CTX_SUFF(pDevIns), rc); \
67	if (rc2 != VINF_SUCCESS) \
68	return rc2; \
69	} while (0)
70	#define PIC_UNLOCK(pThis) \
71	(pThis)->CTX_SUFF(pPicHlp)->pfnUnlock((pThis)->CTX_SUFF(pDevIns))
72
73
74	/* debug PIC */
75	#define DEBUG_PIC
76
77	/#define DEBUG_IRQ_COUNT/
78
79	/**
80	* The instance data of one (1) PIC.
81	*/
82	typedef struct PICSTATE
83	{
84	uint8_t last_irr; /*< edge detection /
85	uint8_t irr; /*< interrupt request register /
86	uint8_t imr; /*< interrupt mask register /
87	uint8_t isr; /*< interrupt service register /
88	uint8_t priority_add; /*< highest irq priority /
89	uint8_t irq_base;
90	uint8_t read_reg_select;
91	uint8_t poll;
92	uint8_t special_mask;
93	uint8_t init_state;
94	uint8_t auto_eoi;
95	uint8_t rotate_on_auto_eoi;
96	uint8_t special_fully_nested_mode;
97	uint8_t init4; /*< true if 4 byte init /
98	uint8_t elcr; /*< PIIX edge/trigger selection/
99	uint8_t elcr_mask;
100	/** Pointer to the device instance, R3 Ptr. */
101	PPDMDEVINSR3 pDevInsR3;
102	/** Pointer to the device instance, R0 Ptr. */
103	PPDMDEVINSR0 pDevInsR0;
104	/** Pointer to the device instance, RC Ptr. */
105	PPDMDEVINSRC pDevInsRC;
106	/** The PIC index (0 or 1). */
107	uint8_t idxPic;
108	uint8_t abAlignment0[3]; /*< Alignment padding. /
109	/** The IRQ tags and source IDs for each (tracing purposes). */
110	uint32_t auTags[8];
111	} PICSTATE;
112	/** Pointer to the state of one PIC. */
113	typedef PICSTATE *PPICSTATE;
114
115
116	/**
117	* The whole PIC device instance data.
118	*/
119	typedef struct DEVPIC
120	{
121	/** The two interrupt controllers. */
122	PICSTATE aPics[2];
123	/** Pointer to the device instance - R3 Ptr. */
124	PPDMDEVINSR3 pDevInsR3;
125	/** Pointer to the PIC R3 helpers. */
126	PCPDMPICHLPR3 pPicHlpR3;
127	/** Pointer to the device instance - R0 Ptr. */
128	PPDMDEVINSR0 pDevInsR0;
129	/** Pointer to the PIC R0 helpers. */
130	PCPDMPICHLPR0 pPicHlpR0;
131	/** Pointer to the device instance - RC Ptr. */
132	PPDMDEVINSRC pDevInsRC;
133	/** Pointer to the PIC RC helpers. */
134	PCPDMPICHLPRC pPicHlpRC;
135	/** Number of release log entries. Used to prevent flooding. */
136	uint32_t cRelLogEntries;
137	uint32_t u32AlignmentPadding;
138	#ifdef VBOX_WITH_STATISTICS
139	STAMCOUNTER StatSetIrqGC;
140	STAMCOUNTER StatSetIrqHC;
141	STAMCOUNTER StatClearedActiveIRQ2;
142	STAMCOUNTER StatClearedActiveMasterIRQ;
143	STAMCOUNTER StatClearedActiveSlaveIRQ;
144	#endif
145	} DEVPIC;
146	/** Pointer to the whole PIC instance data. */
147	typedef DEVPIC *PDEVPIC;
148
149
150	#ifndef VBOX_DEVICE_STRUCT_TESTCASE
151	#ifdef LOG_ENABLED
152	DECLINLINE(void) DumpPICState(PPICSTATE pPic, const char *pszFn)
153	{
154	PDEVPIC pThis = PDMINS_2_DATA(pPic->CTX_SUFF(pDevIns), PDEVPIC);
155
156	Log2(("%s: pic%d: elcr=%x last_irr=%x irr=%x imr=%x isr=%x irq_base=%x\n",
157	pszFn, (&pThis->aPics[0] == pPic) ? 0 : 1,
158	pPic->elcr, pPic->last_irr, pPic->irr, pPic->imr, pPic->isr, pPic->irq_base));
159	}
160	#else
161	# define DumpPICState(pThis, szFn) do { } while (0)
162	#endif
163
164	/* set irq level. If an edge is detected, then the IRR is set to 1 */
165	DECLINLINE(void) pic_set_irq1(PPICSTATE pPic, int irq, int level, uint32_t uTagSrc)
166	{
167	Log(("pic_set_irq1: irq=%d level=%d\n", irq, level));
168	int mask = 1 << irq;
169	if (pPic->elcr & mask)
170	{
171	/* level triggered */
172	if (level)
173	{
174	Log2(("pic_set_irq1(ls) irr=%d irrnew=%d\n", pPic->irr, pPic->irr \| mask));
175	pPic->irr \|= mask;
176	pPic->last_irr \|= mask;
177	}
178	else
179	{
180	Log2(("pic_set_irq1(lc) irr=%d irrnew=%d\n", pPic->irr, pPic->irr & ~mask));
181	pPic->irr &= ~mask;
182	pPic->last_irr &= ~mask;
183	}
184	}
185	else
186	{
187	/* edge triggered */
188	if (level)
189	{
190	if ((pPic->last_irr & mask) == 0)
191	{
192	Log2(("pic_set_irq1 irr=%x last_irr=%x\n", pPic->irr \| mask, pPic->last_irr));
193	pPic->irr \|= mask;
194	}
195	pPic->last_irr \|= mask;
196	}
197	else
198	{
199	pPic->irr &= ~mask;
200	pPic->last_irr &= ~mask;
201	}
202	}
203
204	/* Save the tag. */
205	if (level)
206	{
207	if (!pPic->auTags[irq])
208	pPic->auTags[irq] = uTagSrc;
209	else
210	pPic->auTags[irq] \|= RT_BIT_32(31);
211	}
212
213	DumpPICState(pPic, "pic_set_irq1");
214	}
215
216	/* return the highest priority found in mask (highest = smallest
217	number). Return 8 if no irq */
218	DECLINLINE(int) get_priority(PPICSTATE pPic, int mask)
219	{
220	int priority;
221	if (mask == 0)
222	return 8;
223	priority = 0;
224	while ((mask & (1 << ((priority + pPic->priority_add) & 7))) == 0)
225	priority++;
226	return priority;
227	}
228
229	/* return the pic wanted interrupt. return -1 if none */
230	static int pic_get_irq(PPICSTATE pPic)
231	{
232	int mask, cur_priority, priority;
233	Log(("pic_get_irq%d: mask=%x\n", pPic->idxPic, pPic->irr & ~pPic->imr));
234	DumpPICState(pPic, "pic_get_irq");
235
236	mask = pPic->irr & ~pPic->imr;
237	priority = get_priority(pPic, mask);
238	Log(("pic_get_irq: priority=%x\n", priority));
239	if (priority == 8)
240	return -1;
241	/* compute current priority. If special fully nested mode on the
242	master, the IRQ coming from the slave is not taken into account
243	for the priority computation. */
244	mask = pPic->isr;
245	if (pPic->special_fully_nested_mode && pPic->idxPic == 0)
246	mask &= ~(1 << 2);
247	cur_priority = get_priority(pPic, mask);
248	Log(("pic_get_irq%d: cur_priority=%x pending=%d\n", pPic->idxPic,
249	cur_priority, (priority == 8) ? -1 : (priority + pPic->priority_add) & 7));
250	if (priority < cur_priority)
251	{
252	/* higher priority found: an irq should be generated */
253	return (priority + pPic->priority_add) & 7;
254	}
255	return -1;
256	}
257
258	/* raise irq to CPU if necessary. must be called every time the active
259	irq may change */
260	static int pic_update_irq(PDEVPIC pThis)
261	{
262	int irq2, irq;
263
264	/* first look at slave pic */
265	irq2 = pic_get_irq(&pThis->aPics[1]);
266	Log(("pic_update_irq irq2=%d\n", irq2));
267	if (irq2 >= 0)
268	{
269	/* if irq request by slave pic, signal master PIC */
270	pic_set_irq1(&pThis->aPics[0], 2, 1, pThis->aPics[1].auTags[irq2]);
271	}
272	else
273	{
274	/* If not, clear the IR on the master PIC. */
275	pic_set_irq1(&pThis->aPics[0], 2, 0, 0 /uTagSrc/);
276	}
277	/* look at requested irq */
278	irq = pic_get_irq(&pThis->aPics[0]);
279	if (irq >= 0)
280	{
281	/* If irq 2 is pending on the master pic, then there must be one pending on the slave pic too! Otherwise we'll get
282	* spurious slave interrupts in picGetInterrupt.
283	*/
284	if (irq != 2 \|\| irq2 != -1)
285	{
286	#if defined(DEBUG_PIC)
287	for (int i = 0; i < 2; i++)
288	Log(("pic%d: imr=%x irr=%x padd=%d\n", i, pThis->aPics[i].imr, pThis->aPics[i].irr, pThis->aPics[i].priority_add));
289	Log(("pic: cpu_interrupt\n"));
290	#endif
291	pThis->CTX_SUFF(pPicHlp)->pfnSetInterruptFF(pThis->CTX_SUFF(pDevIns));
292	}
293	else
294	{
295	STAM_COUNTER_INC(&pThis->StatClearedActiveIRQ2);
296	Log(("pic_update_irq: irq 2 is active, but no interrupt is pending on the slave pic!!\n"));
297	/* Clear it here, so lower priority interrupts can still be dispatched. */
298
299	/* if this was the only pending irq, then we must clear the interrupt ff flag */
300	pThis->CTX_SUFF(pPicHlp)->pfnClearInterruptFF(pThis->CTX_SUFF(pDevIns));
301
302	/** @todo Is this correct? */
303	pThis->aPics[0].irr &= ~(1 << 2);
304
305	/* Call ourselves again just in case other interrupts are pending */
306	return pic_update_irq(pThis);
307	}
308	}
309	else
310	{
311	Log(("pic_update_irq: no interrupt is pending!!\n"));
312
313	/* we must clear the interrupt ff flag */
314	pThis->CTX_SUFF(pPicHlp)->pfnClearInterruptFF(pThis->CTX_SUFF(pDevIns));
315	}
316	return VINF_SUCCESS;
317	}
318
319	/** @note if an interrupt line state changes from unmasked to masked, then it must be deactivated when currently pending! */
320	static void pic_update_imr(PDEVPIC pThis, PPICSTATE pPic, uint8_t val)
321	{
322	int irq, intno;
323	PPICSTATE pActivePIC;
324
325	/* Query the current pending irq, if any. */
326	pActivePIC = &pThis->aPics[0];
327	intno = irq = pic_get_irq(pActivePIC);
328	if (irq == 2)
329	{
330	pActivePIC = &pThis->aPics[1];
331	irq = pic_get_irq(pActivePIC);
332	intno = irq + 8;
333	}
334
335	/* Update IMR */
336	pPic->imr = val;
337
338	/* If an interrupt is pending and now masked, then clear the FF flag. */
339	if ( irq >= 0
340	&& ((1 << irq) & ~pActivePIC->imr) == 0)
341	{
342	Log(("pic_update_imr: pic0: elcr=%x last_irr=%x irr=%x imr=%x isr=%x irq_base=%x\n",
343	pThis->aPics[0].elcr, pThis->aPics[0].last_irr, pThis->aPics[0].irr, pThis->aPics[0].imr, pThis->aPics[0].isr, pThis->aPics[0].irq_base));
344	Log(("pic_update_imr: pic1: elcr=%x last_irr=%x irr=%x imr=%x isr=%x irq_base=%x\n",
345	pThis->aPics[1].elcr, pThis->aPics[1].last_irr, pThis->aPics[1].irr, pThis->aPics[1].imr, pThis->aPics[1].isr, pThis->aPics[1].irq_base));
346
347	/* Clear pending IRQ 2 on master controller in case of slave interrupt. */
348	/** @todo Is this correct? */
349	if (intno > 7)
350	{
351	pThis->aPics[0].irr &= ~(1 << 2);
352	STAM_COUNTER_INC(&pThis->StatClearedActiveSlaveIRQ);
353	}
354	else
355	STAM_COUNTER_INC(&pThis->StatClearedActiveMasterIRQ);
356
357	Log(("pic_update_imr: clear pending interrupt %d\n", intno));
358	pThis->CTX_SUFF(pPicHlp)->pfnClearInterruptFF(pThis->CTX_SUFF(pDevIns));
359	}
360	}
361
362
363	/**
364	* Set the an IRQ.
365	*
366	* @param pDevIns Device instance of the PICs.
367	* @param iIrq IRQ number to set.
368	* @param iLevel IRQ level.
369	* @param uTagSrc The IRQ tag and source ID (for tracing).
370	*/
371	PDMBOTHCBDECL(void) picSetIrq(PPDMDEVINS pDevIns, int iIrq, int iLevel, uint32_t uTagSrc)
372	{
373	PDEVPIC pThis = PDMINS_2_DATA(pDevIns, PDEVPIC);
374	Assert(pThis->CTX_SUFF(pDevIns) == pDevIns);
375	Assert(pThis->aPics[0].CTX_SUFF(pDevIns) == pDevIns);
376	Assert(pThis->aPics[1].CTX_SUFF(pDevIns) == pDevIns);
377	AssertMsg(iIrq < 16, ("iIrq=%d\n", iIrq));
378
379	Log(("picSetIrq %d %d\n", iIrq, iLevel));
380	DumpPICState(&pThis->aPics[0], "picSetIrq");
381	DumpPICState(&pThis->aPics[1], "picSetIrq");
382	STAM_COUNTER_INC(&pThis->CTXSUFF(StatSetIrq));
383	if ((iLevel & PDM_IRQ_LEVEL_FLIP_FLOP) == PDM_IRQ_LEVEL_FLIP_FLOP)
384	{
385	/* A flip-flop lowers the IRQ line and immediately raises it, so
386	* that a rising edge is guaranteed to occur. Note that the IRQ
387	* line must be held high for a while to avoid spurious interrupts.
388	*/
389	pic_set_irq1(&pThis->aPics[iIrq >> 3], iIrq & 7, 0, uTagSrc);
390	pic_update_irq(pThis);
391	}
392	pic_set_irq1(&pThis->aPics[iIrq >> 3], iIrq & 7, iLevel & PDM_IRQ_LEVEL_HIGH, uTagSrc);
393	pic_update_irq(pThis);
394	}
395
396
397	/* acknowledge interrupt 'irq' */
398	DECLINLINE(void) pic_intack(PPICSTATE pPic, int irq)
399	{
400	if (pPic->auto_eoi)
401	{
402	if (pPic->rotate_on_auto_eoi)
403	pPic->priority_add = (irq + 1) & 7;
404	}
405	else
406	pPic->isr \|= (1 << irq);
407
408	/* We don't clear a level sensitive interrupt here */
409	if (!(pPic->elcr & (1 << irq)))
410	{
411	Log2(("pic_intack: irr=%x irrnew=%x\n", pPic->irr, pPic->irr & ~(1 << irq)));
412	pPic->irr &= ~(1 << irq);
413	}
414	}
415
416
417	/**
418	* Get a pending interrupt.
419	*
420	* @returns Pending interrupt number.
421	* @param pDevIns Device instance of the PICs.
422	* @param puTagSrc Where to return the IRQ tag and source ID.
423	*/
424	PDMBOTHCBDECL(int) picGetInterrupt(PPDMDEVINS pDevIns, uint32_t *puTagSrc)
425	{
426	PDEVPIC pThis = PDMINS_2_DATA(pDevIns, PDEVPIC);
427	int irq;
428	int irq2;
429	int intno;
430
431	/* read the irq from the PIC */
432	DumpPICState(&pThis->aPics[0], "picGetInterrupt");
433	DumpPICState(&pThis->aPics[1], "picGetInterrupt");
434
435	irq = pic_get_irq(&pThis->aPics[0]);
436	if (irq >= 0)
437	{
438	pic_intack(&pThis->aPics[0], irq);
439	if (irq == 2)
440	{
441	irq2 = pic_get_irq(&pThis->aPics[1]);
442	if (irq2 >= 0)
443	pic_intack(&pThis->aPics[1], irq2);
444	else
445	{
446	/* Interrupt went away or is now masked. */
447	Log(("picGetInterrupt: spurious IRQ on slave controller, converted to IRQ15\n"));
448	irq2 = 7;
449	}
450	intno = pThis->aPics[1].irq_base + irq2;
451	*puTagSrc = pThis->aPics[0].auTags[irq2];
452	pThis->aPics[0].auTags[irq2] = 0;
453	Log2(("picGetInterrupt1: %x base=%x irq=%x uTagSrc=%#x\n", intno, pThis->aPics[1].irq_base, irq2, *puTagSrc));
454	irq = irq2 + 8;
455	}
456	else
457	{
458	intno = pThis->aPics[0].irq_base + irq;
459	*puTagSrc = pThis->aPics[0].auTags[irq];
460	pThis->aPics[0].auTags[irq] = 0;
461	Log2(("picGetInterrupt0: %x base=%x irq=%x uTagSrc=%#x\n", intno, pThis->aPics[0].irq_base, irq, *puTagSrc));
462	}
463	}
464	else
465	{
466	/* Interrupt went away or is now masked. */
467	Log(("picGetInterrupt: spurious IRQ on master controller, converted to IRQ7\n"));
468	irq = 7;
469	intno = pThis->aPics[0].irq_base + irq;
470	*puTagSrc = 0;
471	}
472	pic_update_irq(pThis);
473
474	Log(("picGetInterrupt: 0x%02x pending 0:%d 1:%d\n", intno, pic_get_irq(&pThis->aPics[0]), pic_get_irq(&pThis->aPics[1])));
475
476	return intno;
477	}
478
479	static void pic_reset(PPICSTATE pPic)
480	{
481	PPDMDEVINSR3 pDevInsR3 = pPic->pDevInsR3;
482	PPDMDEVINSR0 pDevInsR0 = pPic->pDevInsR0;
483	PPDMDEVINSRC pDevInsRC = pPic->pDevInsRC;
484	int elcr_mask = pPic->elcr_mask;
485	int elcr = pPic->elcr;
486
487	memset(pPic, 0, sizeof(*pPic));
488
489	pPic->elcr = elcr;
490	pPic->elcr_mask = elcr_mask;
491	pPic->pDevInsRC = pDevInsRC;
492	pPic->pDevInsR0 = pDevInsR0;
493	pPic->pDevInsR3 = pDevInsR3;
494	}
495
496
497	static int pic_ioport_write(PDEVPIC pThis, PPICSTATE pPic, uint32_t addr, uint32_t val)
498	{
499	int rc = VINF_SUCCESS;
500	int irq;
501
502	Log(("pic_write: addr=0x%02x val=0x%02x\n", addr, val));
503	addr &= 1;
504	if (addr == 0)
505	{
506	if (val & 0x10)
507	{
508	/* init */
509	pic_reset(pPic);
510	/* deassert a pending interrupt */
511	pThis->CTX_SUFF(pPicHlp)->pfnClearInterruptFF(pThis->CTX_SUFF(pDevIns));
512
513	pPic->init_state = 1;
514	pPic->init4 = val & 1;
515	if (val & 0x02)
516	AssertReleaseMsgFailed(("single mode not supported"));
517	if (val & 0x08)
518	if (pThis->cRelLogEntries++ < 64)
519	LogRel(("pic_write: Level sensitive IRQ setting ignored.\n"));
520	}
521	else if (val & 0x08)
522	{
523	if (val & 0x04)
524	pPic->poll = 1;
525	if (val & 0x02)
526	pPic->read_reg_select = val & 1;
527	if (val & 0x40)
528	pPic->special_mask = (val >> 5) & 1;
529	}
530	else
531	{
532	int cmd = val >> 5;
533	switch (cmd)
534	{
535	case 0:
536	case 4:
537	pPic->rotate_on_auto_eoi = cmd >> 2;
538	break;
539	case 1: /* end of interrupt */
540	case 5:
541	{
542	int priority = get_priority(pPic, pPic->isr);
543	if (priority != 8) {
544	irq = (priority + pPic->priority_add) & 7;
545	Log(("pic_write: EOI prio=%d irq=%d\n", priority, irq));
546	pPic->isr &= ~(1 << irq);
547	if (cmd == 5)
548	pPic->priority_add = (irq + 1) & 7;
549	rc = pic_update_irq(pThis);
550	Assert(rc == VINF_SUCCESS);
551	DumpPICState(pPic, "eoi");
552	}
553	break;
554	}
555	case 3:
556	{
557	irq = val & 7;
558	Log(("pic_write: EOI2 for irq %d\n", irq));
559	pPic->isr &= ~(1 << irq);
560	rc = pic_update_irq(pThis);
561	Assert(rc == VINF_SUCCESS);
562	DumpPICState(pPic, "eoi2");
563	break;
564	}
565	case 6:
566	{
567	pPic->priority_add = (val + 1) & 7;
568	Log(("pic_write: lowest priority %d (highest %d)\n", val & 7, pPic->priority_add));
569	rc = pic_update_irq(pThis);
570	Assert(rc == VINF_SUCCESS);
571	break;
572	}
573	case 7:
574	{
575	irq = val & 7;
576	Log(("pic_write: EOI3 for irq %d\n", irq));
577	pPic->isr &= ~(1 << irq);
578	pPic->priority_add = (irq + 1) & 7;
579	rc = pic_update_irq(pThis);
580	Assert(rc == VINF_SUCCESS);
581	DumpPICState(pPic, "eoi3");
582	break;
583	}
584	default:
585	/* no operation */
586	break;
587	}
588	}
589	}
590	else
591	{
592	switch (pPic->init_state)
593	{
594	case 0:
595	/* normal mode */
596	pic_update_imr(pThis, pPic, val);
597
598	rc = pic_update_irq(pThis);
599	Assert(rc == VINF_SUCCESS);
600	break;
601	case 1:
602	pPic->irq_base = val & 0xf8;
603	pPic->init_state = 2;
604	Log(("pic_write: set irq base to %x\n", pPic->irq_base));
605	break;
606	case 2:
607	if (pPic->init4)
608	pPic->init_state = 3;
609	else
610	pPic->init_state = 0;
611	break;
612	case 3:
613	pPic->special_fully_nested_mode = (val >> 4) & 1;
614	pPic->auto_eoi = (val >> 1) & 1;
615	pPic->init_state = 0;
616	Log(("pic_write: special_fully_nested_mode=%d auto_eoi=%d\n", pPic->special_fully_nested_mode, pPic->auto_eoi));
617	break;
618	}
619	}
620	return rc;
621	}
622
623
624	static uint32_t pic_poll_read(PPICSTATE pPic, uint32_t addr1)
625	{
626	PDEVPIC pThis = RT_FROM_MEMBER(pPic, DEVPIC, aPics[pPic->idxPic]);
627
628	int ret = pic_get_irq(pPic);
629	if (ret >= 0)
630	{
631	if (addr1 >> 7)
632	{
633	Log2(("pic_poll_read: clear slave irq (isr)\n"));
634	pThis->aPics[0].isr &= ~(1 << 2);
635	pThis->aPics[0].irr &= ~(1 << 2);
636	}
637	Log2(("pic_poll_read: clear irq %d (isr)\n", ret));
638	pPic->irr &= ~(1 << ret);
639	pPic->isr &= ~(1 << ret);
640	if (addr1 >> 7 \|\| ret != 2)
641	pic_update_irq(pThis);
642	}
643	else
644	{
645	ret = 0;
646	pic_update_irq(pThis);
647	}
648
649	return ret;
650	}
651
652
653	static uint32_t pic_ioport_read(PPICSTATE pPic, uint32_t addr1, int *pRC)
654	{
655	unsigned int addr;
656	int ret;
657
658	*pRC = VINF_SUCCESS;
659
660	addr = addr1;
661	addr &= 1;
662	if (pPic->poll)
663	{
664	ret = pic_poll_read(pPic, addr1);
665	pPic->poll = 0;
666	}
667	else
668	{
669	if (addr == 0)
670	{
671	if (pPic->read_reg_select)
672	ret = pPic->isr;
673	else
674	ret = pPic->irr;
675	}
676	else
677	ret = pPic->imr;
678	}
679	Log(("pic_read: addr=0x%02x val=0x%02x\n", addr1, ret));
680	return ret;
681	}
682
683
684
685	/* -=-=-=-=-=- I/O ports -=-=-=-=-=- */
686
687	/**
688	* @callback_method_impl{FNIOMIOPORTIN}
689	*/
690	PDMBOTHCBDECL(int) picIOPortRead(PPDMDEVINS pDevIns, void pvUser, RTIOPORT Port, uint32_t pu32, unsigned cb)
691	{
692	PDEVPIC pThis = PDMINS_2_DATA(pDevIns, PDEVPIC);
693	uint32_t iPic = (uint32_t)(uintptr_t)pvUser;
694
695	Assert(iPic == 0 \|\| iPic == 1);
696	if (cb == 1)
697	{
698	int rc;
699	PIC_LOCK(pThis, VINF_IOM_R3_IOPORT_READ);
700	*pu32 = pic_ioport_read(&pThis->aPics[iPic], Port, &rc);
701	PIC_UNLOCK(pThis);
702	return rc;
703	}
704	return VERR_IOM_IOPORT_UNUSED;
705	}
706
707
708	/**
709	* @callback_method_impl{FNIOMIOPORTOUT}
710	*/
711	PDMBOTHCBDECL(int) picIOPortWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb)
712	{
713	PDEVPIC pThis = PDMINS_2_DATA(pDevIns, PDEVPIC);
714	uint32_t iPic = (uint32_t)(uintptr_t)pvUser;
715
716	Assert(iPic == 0 \|\| iPic == 1);
717
718	if (cb == 1)
719	{
720	int rc;
721	PIC_LOCK(pThis, VINF_IOM_R3_IOPORT_WRITE);
722	rc = pic_ioport_write(pThis, &pThis->aPics[iPic], Port, u32);
723	PIC_UNLOCK(pThis);
724	return rc;
725	}
726	return VINF_SUCCESS;
727	}
728
729
730	/**
731	* @callback_method_impl{FNIOMIOPORTIN, ELCR}
732	*/
733	PDMBOTHCBDECL(int) picIOPortElcrRead(PPDMDEVINS pDevIns, void pvUser, RTIOPORT Port, uint32_t pu32, unsigned cb)
734	{
735	if (cb == 1)
736	{
737	PPICSTATE pPic = (PPICSTATE)pvUser;
738	PIC_LOCK(PDMINS_2_DATA(pDevIns, PDEVPIC), VINF_IOM_R3_IOPORT_READ);
739	*pu32 = pPic->elcr;
740	PIC_UNLOCK(PDMINS_2_DATA(pDevIns, PDEVPIC));
741	return VINF_SUCCESS;
742	}
743	NOREF(Port);
744	return VERR_IOM_IOPORT_UNUSED;
745	}
746
747
748	/**
749	* @callback_method_impl{FNIOMIOPORTOUT, ELCR}
750	*/
751	PDMBOTHCBDECL(int) picIOPortElcrWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb)
752	{
753	if (cb == 1)
754	{
755	PPICSTATE pPic = (PPICSTATE)pvUser;
756	PIC_LOCK(PDMINS_2_DATA(pDevIns, PDEVPIC), VINF_IOM_R3_IOPORT_WRITE);
757	pPic->elcr = u32 & pPic->elcr_mask;
758	PIC_UNLOCK(PDMINS_2_DATA(pDevIns, PDEVPIC));
759	}
760	NOREF(Port);
761	return VINF_SUCCESS;
762	}
763
764
765	#ifdef IN_RING3
766
767	/**
768	* @callback_method_impl{FNDBGFINFOHANDLERDEV}
769	*/
770	static DECLCALLBACK(void) picInfo(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
771	{
772	PDEVPIC pThis = PDMINS_2_DATA(pDevIns, PDEVPIC);
773	NOREF(pszArgs);
774
775	/*
776	* Show info.
777	*/
778	for (int i = 0; i < 2; i++)
779	{
780	PPICSTATE pPic = &pThis->aPics[i];
781
782	pHlp->pfnPrintf(pHlp, "PIC%d:\n", i);
783	pHlp->pfnPrintf(pHlp, " IMR :%02x ISR :%02x IRR :%02x LIRR:%02x\n",
784	pPic->imr, pPic->isr, pPic->irr, pPic->last_irr);
785	pHlp->pfnPrintf(pHlp, " Base:%02x PriAdd:%02x RegSel:%02x\n",
786	pPic->irq_base, pPic->priority_add, pPic->read_reg_select);
787	pHlp->pfnPrintf(pHlp, " Poll:%02x SpMask:%02x IState:%02x\n",
788	pPic->poll, pPic->special_mask, pPic->init_state);
789	pHlp->pfnPrintf(pHlp, " AEOI:%02x Rotate:%02x FNest :%02x Ini4:%02x\n",
790	pPic->auto_eoi, pPic->rotate_on_auto_eoi,
791	pPic->special_fully_nested_mode, pPic->init4);
792	pHlp->pfnPrintf(pHlp, " ELCR:%02x ELMask:%02x\n", pPic->elcr, pPic->elcr_mask);
793	}
794	}
795
796
797	/* -=-=-=-=-=- Saved State -=-=-=-=-=- */
798
799	/**
800	* @callback_method_impl{FNSSMDEVSAVEEXEC}
801	*/
802	static DECLCALLBACK(int) picSaveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
803	{
804	PDEVPIC pThis = PDMINS_2_DATA(pDevIns, PDEVPIC);
805	for (unsigned i = 0; i < RT_ELEMENTS(pThis->aPics); i++)
806	{
807	SSMR3PutU8(pSSM, pThis->aPics[i].last_irr);
808	SSMR3PutU8(pSSM, pThis->aPics[i].irr);
809	SSMR3PutU8(pSSM, pThis->aPics[i].imr);
810	SSMR3PutU8(pSSM, pThis->aPics[i].isr);
811	SSMR3PutU8(pSSM, pThis->aPics[i].priority_add);
812	SSMR3PutU8(pSSM, pThis->aPics[i].irq_base);
813	SSMR3PutU8(pSSM, pThis->aPics[i].read_reg_select);
814	SSMR3PutU8(pSSM, pThis->aPics[i].poll);
815	SSMR3PutU8(pSSM, pThis->aPics[i].special_mask);
816	SSMR3PutU8(pSSM, pThis->aPics[i].init_state);
817	SSMR3PutU8(pSSM, pThis->aPics[i].auto_eoi);
818	SSMR3PutU8(pSSM, pThis->aPics[i].rotate_on_auto_eoi);
819	SSMR3PutU8(pSSM, pThis->aPics[i].special_fully_nested_mode);
820	SSMR3PutU8(pSSM, pThis->aPics[i].init4);
821	SSMR3PutU8(pSSM, pThis->aPics[i].elcr);
822	}
823	return VINF_SUCCESS;
824	}
825
826
827	/**
828	* @callback_method_impl{FNSSMDEVLOADEXEC}
829	*/
830	static DECLCALLBACK(int) picLoadExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
831	{
832	PDEVPIC pThis = PDMINS_2_DATA(pDevIns, PDEVPIC);
833
834	if (uVersion != 1)
835	return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
836	Assert(uPass == SSM_PASS_FINAL); NOREF(uPass);
837
838	for (unsigned i = 0; i < RT_ELEMENTS(pThis->aPics); i++)
839	{
840	SSMR3GetU8(pSSM, &pThis->aPics[i].last_irr);
841	SSMR3GetU8(pSSM, &pThis->aPics[i].irr);
842	SSMR3GetU8(pSSM, &pThis->aPics[i].imr);
843	SSMR3GetU8(pSSM, &pThis->aPics[i].isr);
844	SSMR3GetU8(pSSM, &pThis->aPics[i].priority_add);
845	SSMR3GetU8(pSSM, &pThis->aPics[i].irq_base);
846	SSMR3GetU8(pSSM, &pThis->aPics[i].read_reg_select);
847	SSMR3GetU8(pSSM, &pThis->aPics[i].poll);
848	SSMR3GetU8(pSSM, &pThis->aPics[i].special_mask);
849	SSMR3GetU8(pSSM, &pThis->aPics[i].init_state);
850	SSMR3GetU8(pSSM, &pThis->aPics[i].auto_eoi);
851	SSMR3GetU8(pSSM, &pThis->aPics[i].rotate_on_auto_eoi);
852	SSMR3GetU8(pSSM, &pThis->aPics[i].special_fully_nested_mode);
853	SSMR3GetU8(pSSM, &pThis->aPics[i].init4);
854	SSMR3GetU8(pSSM, &pThis->aPics[i].elcr);
855	}
856	return VINF_SUCCESS;
857	}
858
859
860	/* -=-=-=-=-=- PDMDEVREG -=-=-=-=-=- */
861
862	/**
863	* @interface_method_impl{PDMDEVREG,pfnReset}
864	*/
865	static DECLCALLBACK(void) picReset(PPDMDEVINS pDevIns)
866	{
867	PDEVPIC pThis = PDMINS_2_DATA(pDevIns, PDEVPIC);
868	unsigned i;
869	LogFlow(("picReset:\n"));
870	pThis->pPicHlpR3->pfnLock(pDevIns, VERR_INTERNAL_ERROR);
871
872	for (i = 0; i < RT_ELEMENTS(pThis->aPics); i++)
873	pic_reset(&pThis->aPics[i]);
874
875	PIC_UNLOCK(pThis);
876	}
877
878
879	/**
880	* @interface_method_impl{PDMDEVREG,pfnRelocate}
881	*/
882	static DECLCALLBACK(void) picRelocate(PPDMDEVINS pDevIns, RTGCINTPTR offDelta)
883	{
884	PDEVPIC pThis = PDMINS_2_DATA(pDevIns, PDEVPIC);
885	unsigned i;
886
887	pThis->pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
888	pThis->pPicHlpRC = pThis->pPicHlpR3->pfnGetRCHelpers(pDevIns);
889	for (i = 0; i < RT_ELEMENTS(pThis->aPics); i++)
890	pThis->aPics[i].pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
891	}
892
893
894	/**
895	* @interface_method_impl{PDMDEVREG,pfnConstruct}
896	*/
897	static DECLCALLBACK(int) picConstruct(PPDMDEVINS pDevIns, int iInstance, PCFGMNODE pCfg)
898	{
899	PDEVPIC pThis = PDMINS_2_DATA(pDevIns, PDEVPIC);
900	int rc;
901	bool fGCEnabled;
902	bool fR0Enabled;
903	Assert(iInstance == 0);
904
905	/*
906	* Validate and read configuration.
907	*/
908	if (!CFGMR3AreValuesValid(pCfg, "GCEnabled\0" "R0Enabled\0"))
909	return VERR_PDM_DEVINS_UNKNOWN_CFG_VALUES;
910
911	rc = CFGMR3QueryBoolDef(pCfg, "GCEnabled", &fGCEnabled, true);
912	if (RT_FAILURE(rc))
913	return PDMDEV_SET_ERROR(pDevIns, rc,
914	N_("Configuration error: failed to read GCEnabled as boolean"));
915
916	rc = CFGMR3QueryBoolDef(pCfg, "R0Enabled", &fR0Enabled, true);
917	if (RT_FAILURE(rc))
918	return PDMDEV_SET_ERROR(pDevIns, rc,
919	N_("Configuration error: failed to read R0Enabled as boolean"));
920
921	Log(("DevPIC: fGCEnabled=%RTbool fR0Enabled=%RTbool\n", fGCEnabled, fR0Enabled));
922
923	/*
924	* Init the data.
925	*/
926	Assert(RT_ELEMENTS(pThis->aPics) == 2);
927	pThis->pDevInsR3 = pDevIns;
928	pThis->pDevInsR0 = PDMDEVINS_2_R0PTR(pDevIns);
929	pThis->pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
930	pThis->aPics[0].elcr_mask = 0xf8;
931	pThis->aPics[1].elcr_mask = 0xde;
932	pThis->aPics[0].pDevInsR3 = pDevIns;
933	pThis->aPics[1].pDevInsR3 = pDevIns;
934	pThis->aPics[0].pDevInsR0 = PDMDEVINS_2_R0PTR(pDevIns);
935	pThis->aPics[1].pDevInsR0 = PDMDEVINS_2_R0PTR(pDevIns);
936	pThis->aPics[0].pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
937	pThis->aPics[1].pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
938	pThis->aPics[0].idxPic = 0;
939	pThis->aPics[1].idxPic = 1;
940	pThis->cRelLogEntries = 0;
941
942	/*
943	* Register us as the PIC with PDM.
944	*/
945	PDMPICREG PicReg;
946	PicReg.u32Version = PDM_PICREG_VERSION;
947	PicReg.pfnSetIrqR3 = picSetIrq;
948	PicReg.pfnGetInterruptR3 = picGetInterrupt;
949
950	if (fGCEnabled)
951	{
952	PicReg.pszSetIrqRC = "picSetIrq";
953	PicReg.pszGetInterruptRC = "picGetInterrupt";
954	}
955	else
956	{
957	PicReg.pszSetIrqRC = NULL;
958	PicReg.pszGetInterruptRC = NULL;
959	}
960
961	if (fR0Enabled)
962	{
963	PicReg.pszSetIrqR0 = "picSetIrq";
964	PicReg.pszGetInterruptR0 = "picGetInterrupt";
965	}
966	else
967	{
968	PicReg.pszSetIrqR0 = NULL;
969	PicReg.pszGetInterruptR0 = NULL;
970	}
971
972	rc = PDMDevHlpPICRegister(pDevIns, &PicReg, &pThis->pPicHlpR3);
973	AssertLogRelMsgRCReturn(rc, ("PICRegister -> %Rrc\n", rc), rc);
974	if (fGCEnabled)
975	pThis->pPicHlpRC = pThis->pPicHlpR3->pfnGetRCHelpers(pDevIns);
976	if (fR0Enabled)
977	pThis->pPicHlpR0 = pThis->pPicHlpR3->pfnGetR0Helpers(pDevIns);
978
979	/*
980	* Since the PIC helper interface provides access to the PDM lock,
981	* we need no device level critical section.
982	*/
983	rc = PDMDevHlpSetDeviceCritSect(pDevIns, PDMDevHlpCritSectGetNop(pDevIns));
984	AssertRCReturn(rc, rc);
985
986	/*
987	* Register I/O ports and save state.
988	*/
989	rc = PDMDevHlpIOPortRegister(pDevIns, 0x20, 2, (void *)0, picIOPortWrite, picIOPortRead, NULL, NULL, "i8259 PIC #0");
990	if (RT_FAILURE(rc))
991	return rc;
992	rc = PDMDevHlpIOPortRegister(pDevIns, 0xa0, 2, (void *)1, picIOPortWrite, picIOPortRead, NULL, NULL, "i8259 PIC #1");
993	if (RT_FAILURE(rc))
994	return rc;
995	if (fGCEnabled)
996	{
997	rc = PDMDevHlpIOPortRegisterRC(pDevIns, 0x20, 2, 0, "picIOPortWrite", "picIOPortRead", NULL, NULL, "i8259 PIC #0");
998	if (RT_FAILURE(rc))
999	return rc;
1000	rc = PDMDevHlpIOPortRegisterRC(pDevIns, 0xa0, 2, 1, "picIOPortWrite", "picIOPortRead", NULL, NULL, "i8259 PIC #1");
1001	if (RT_FAILURE(rc))
1002	return rc;
1003	}
1004	if (fR0Enabled)
1005	{
1006	rc = PDMDevHlpIOPortRegisterR0(pDevIns, 0x20, 2, 0, "picIOPortWrite", "picIOPortRead", NULL, NULL, "i8259 PIC #0");
1007	if (RT_FAILURE(rc))
1008	return rc;
1009	rc = PDMDevHlpIOPortRegisterR0(pDevIns, 0xa0, 2, 1, "picIOPortWrite", "picIOPortRead", NULL, NULL, "i8259 PIC #1");
1010	if (RT_FAILURE(rc))
1011	return rc;
1012	}
1013
1014	rc = PDMDevHlpIOPortRegister(pDevIns, 0x4d0, 1, &pThis->aPics[0],
1015	picIOPortElcrWrite, picIOPortElcrRead, NULL, NULL, "i8259 PIC #0 - elcr");
1016	if (RT_FAILURE(rc))
1017	return rc;
1018	rc = PDMDevHlpIOPortRegister(pDevIns, 0x4d1, 1, &pThis->aPics[1],
1019	picIOPortElcrWrite, picIOPortElcrRead, NULL, NULL, "i8259 PIC #1 - elcr");
1020	if (RT_FAILURE(rc))
1021	return rc;
1022	if (fGCEnabled)
1023	{
1024	RTRCPTR pDataRC = PDMINS_2_DATA_RCPTR(pDevIns);
1025	rc = PDMDevHlpIOPortRegisterRC(pDevIns, 0x4d0, 1, pDataRC + RT_OFFSETOF(DEVPIC, aPics[0]),
1026	"picIOPortElcrWrite", "picIOPortElcrRead", NULL, NULL, "i8259 PIC #0 - elcr");
1027	if (RT_FAILURE(rc))
1028	return rc;
1029	rc = PDMDevHlpIOPortRegisterRC(pDevIns, 0x4d1, 1, pDataRC + RT_OFFSETOF(DEVPIC, aPics[1]),
1030	"picIOPortElcrWrite", "picIOPortElcrRead", NULL, NULL, "i8259 PIC #1 - elcr");
1031	if (RT_FAILURE(rc))
1032	return rc;
1033	}
1034	if (fR0Enabled)
1035	{
1036	RTR0PTR pDataR0 = PDMINS_2_DATA_R0PTR(pDevIns);
1037	rc = PDMDevHlpIOPortRegisterR0(pDevIns, 0x4d0, 1, pDataR0 + RT_OFFSETOF(DEVPIC, aPics[0]),
1038	"picIOPortElcrWrite", "picIOPortElcrRead", NULL, NULL, "i8259 PIC #0 - elcr");
1039	if (RT_FAILURE(rc))
1040	return rc;
1041	rc = PDMDevHlpIOPortRegisterR0(pDevIns, 0x4d1, 1, pDataR0 + RT_OFFSETOF(DEVPIC, aPics[1]),
1042	"picIOPortElcrWrite", "picIOPortElcrRead", NULL, NULL, "i8259 PIC #1 - elcr");
1043	if (RT_FAILURE(rc))
1044	return rc;
1045	}
1046
1047	rc = PDMDevHlpSSMRegister(pDevIns, 1 /* uVersion /, sizeof(pThis), picSaveExec, picLoadExec);
1048	if (RT_FAILURE(rc))
1049	return rc;
1050
1051
1052	/*
1053	* Register the info item.
1054	*/
1055	PDMDevHlpDBGFInfoRegister(pDevIns, "pic", "PIC info.", picInfo);
1056
1057	/*
1058	* Initialize the device state.
1059	*/
1060	picReset(pDevIns);
1061
1062	#ifdef VBOX_WITH_STATISTICS
1063	/*
1064	* Statistics.
1065	*/
1066	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatSetIrqGC, STAMTYPE_COUNTER, "/Devices/PIC/SetIrqGC", STAMUNIT_OCCURENCES, "Number of PIC SetIrq calls in GC.");
1067	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatSetIrqHC, STAMTYPE_COUNTER, "/Devices/PIC/SetIrqHC", STAMUNIT_OCCURENCES, "Number of PIC SetIrq calls in HC.");
1068
1069	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatClearedActiveIRQ2, STAMTYPE_COUNTER, "/Devices/PIC/Masked/ActiveIRQ2", STAMUNIT_OCCURENCES, "Number of cleared irq 2.");
1070	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatClearedActiveMasterIRQ, STAMTYPE_COUNTER, "/Devices/PIC/Masked/ActiveMaster", STAMUNIT_OCCURENCES, "Number of cleared master irqs.");
1071	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatClearedActiveSlaveIRQ, STAMTYPE_COUNTER, "/Devices/PIC/Masked/ActiveSlave", STAMUNIT_OCCURENCES, "Number of cleared slave irqs.");
1072	#endif
1073
1074	return VINF_SUCCESS;
1075	}
1076
1077
1078	/**
1079	* The device registration structure.
1080	*/
1081	const PDMDEVREG g_DeviceI8259 =
1082	{
1083	/* u32Version */
1084	PDM_DEVREG_VERSION,
1085	/* szName */
1086	"i8259",
1087	/* szRCMod */
1088	"VBoxDDGC.gc",
1089	/* szR0Mod */
1090	"VBoxDDR0.r0",
1091	/* pszDescription */
1092	"Intel 8259 Programmable Interrupt Controller (PIC) Device.",
1093	/* fFlags */
1094	PDM_DEVREG_FLAGS_HOST_BITS_DEFAULT \| PDM_DEVREG_FLAGS_GUEST_BITS_32_64 \| PDM_DEVREG_FLAGS_PAE36 \| PDM_DEVREG_FLAGS_RC \| PDM_DEVREG_FLAGS_R0,
1095	/* fClass */
1096	PDM_DEVREG_CLASS_PIC,
1097	/* cMaxInstances */
1098	1,
1099	/* cbInstance */
1100	sizeof(DEVPIC),
1101	/* pfnConstruct */
1102	picConstruct,
1103	/* pfnDestruct */
1104	NULL,
1105	/* pfnRelocate */
1106	picRelocate,
1107	/* pfnMemSetup */
1108	NULL,
1109	/* pfnPowerOn */
1110	NULL,
1111	/* pfnReset */
1112	picReset,
1113	/* pfnSuspend */
1114	NULL,
1115	/* pfnResume */
1116	NULL,
1117	/* pfnAttach */
1118	NULL,
1119	/* pfnDetach */
1120	NULL,
1121	/* pfnQueryInterface. */
1122	NULL,
1123	/* pfnInitComplete */
1124	NULL,
1125	/* pfnPowerOff */
1126	NULL,
1127	/* pfnSoftReset */
1128	NULL,
1129	/* u32VersionEnd */
1130	PDM_DEVREG_VERSION
1131	};
1132
1133	#endif /* IN_RING3 */
1134	#endif /* !VBOX_DEVICE_STRUCT_TESTCASE */
1135

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source: vbox/trunk/src/VBox/Devices/PC/DevPIC.cpp@ 46845

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