DevPIC.cpp@ 3429

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1	/* $Id: DevPIC.cpp 3308 2007-06-27 08:53:31Z vboxsync $ */
2	/** @file
3	* Intel 8259 Programmable Interrupt Controller (PIC) Device.
4	*/
5
6	/*
7	* Copyright (C) 2006-2007 innotek GmbH
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License as published by the Free Software Foundation,
13	* in version 2 as it comes in the "COPYING" file of the VirtualBox OSE
14	* distribution. VirtualBox OSE is distributed in the hope that it will
15	* be useful, but WITHOUT ANY WARRANTY of any kind.
16	*
17	* If you received this file as part of a commercial VirtualBox
18	* distribution, then only the terms of your commercial VirtualBox
19	* license agreement apply instead of the previous paragraph.
20	*/
21
22	/*******************************************************************************
23	* Header Files *
24	*******************************************************************************/
25	#define LOG_GROUP LOG_GROUP_DEV_PIC
26	#include <VBox/pdm.h>
27	#include <VBox/log.h>
28	#include <iprt/assert.h>
29
30	#include "vl_vbox.h"
31
32
33	/*******************************************************************************
34	* Defined Constants And Macros *
35	*******************************************************************************/
36	/** @def PIC_LOCK
37	* Acquires the PDM lock. This is a NOP if locking is disabled. */
38	/** @def PIC_UNLOCK
39	* Releases the PDM lock. This is a NOP if locking is disabled. */
40	#ifdef VBOX_WITH_PDM_LOCK
41	# define PIC_LOCK(pThis, rc) \
42	do { \
43	int rc2 = (pThis)->CTXALLSUFF(pPicHlp)->pfnLock((pThis)->CTXSUFF(pDevIns), rc); \
44	if (rc2 != VINF_SUCCESS) \
45	return rc2; \
46	} while (0)
47	# define PIC_UNLOCK(pThis) \
48	(pThis)->CTXALLSUFF(pPicHlp)->pfnUnlock((pThis)->CTXSUFF(pDevIns))
49	#else /* !VBOX_WITH_PDM_LOCK */
50	# define PIC_LOCK(pThis, rc) do { } while (0)
51	# define PIC_UNLOCK(pThis) do { } while (0)
52	#endif /* !VBOX_WITH_PDM_LOCK */
53
54
55	#ifndef VBOX_DEVICE_STRUCT_TESTCASE
56	/*******************************************************************************
57	* Internal Functions *
58	*******************************************************************************/
59	__BEGIN_DECLS
60
61	PDMBOTHCBDECL(void) picSetIrq(PPDMDEVINS pDevIns, int iIrq, int iLevel);
62	PDMBOTHCBDECL(int) picGetInterrupt(PPDMDEVINS pDevIns);
63	PDMBOTHCBDECL(int) picIOPortRead(PPDMDEVINS pDevIns, void pvUser, RTIOPORT Port, uint32_t pu32, unsigned cb);
64	PDMBOTHCBDECL(int) picIOPortWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb);
65	PDMBOTHCBDECL(int) picIOPortElcrRead(PPDMDEVINS pDevIns, void pvUser, RTIOPORT Port, uint32_t pu32, unsigned cb);
66	PDMBOTHCBDECL(int) picIOPortElcrWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb);
67
68	__END_DECLS
69	#endif /* !VBOX_DEVICE_STRUCT_TESTCASE */
70
71
72	/*
73	* QEMU 8259 interrupt controller emulation
74	*
75	* Copyright (c) 2003-2004 Fabrice Bellard
76	*
77	* Permission is hereby granted, free of charge, to any person obtaining a copy
78	* of this software and associated documentation files (the "Software"), to deal
79	* in the Software without restriction, including without limitation the rights
80	* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
81	* copies of the Software, and to permit persons to whom the Software is
82	* furnished to do so, subject to the following conditions:
83	*
84	* The above copyright notice and this permission notice shall be included in
85	* all copies or substantial portions of the Software.
86	*
87	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
88	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
89	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
90	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
91	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
92	* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
93	* THE SOFTWARE.
94	*/
95
96	/* debug PIC */
97	#define DEBUG_PIC
98
99	/#define DEBUG_IRQ_COUNT/
100
101	typedef struct PicState {
102	uint8_t last_irr; /* edge detection */
103	uint8_t irr; /* interrupt request register */
104	uint8_t imr; /* interrupt mask register */
105	uint8_t isr; /* interrupt service register */
106	uint8_t priority_add; /* highest irq priority */
107	uint8_t irq_base;
108	uint8_t read_reg_select;
109	uint8_t poll;
110	uint8_t special_mask;
111	uint8_t init_state;
112	uint8_t auto_eoi;
113	uint8_t rotate_on_auto_eoi;
114	uint8_t special_fully_nested_mode;
115	uint8_t init4; /* true if 4 byte init */
116	uint8_t elcr; /* PIIX edge/trigger selection*/
117	uint8_t elcr_mask;
118	/** Pointer to the device instance, HCPtr. */
119	HCPTRTYPE(PPDMDEVINS) pDevInsHC;
120	/** Pointer to the device instance, GCPtr. */
121	GCPTRTYPE(PPDMDEVINS) pDevInsGC;
122	#if HC_ARCH_BITS == 64 && GC_ARCH_BITS != 64
123	RTGCPTR Alignment0;
124	#endif
125	} PicState;
126
127	/**
128	* A PIC device instance data.
129	*/
130	typedef struct DEVPIC
131	{
132	/** The two interrupt controllers. */
133	PicState aPics[2];
134	/** Pointer to the PIC R3 helpers. */
135	PCPDMPICHLPR3 pPicHlpR3;
136	/** Pointer to the PIC R0 helpers. */
137	PCPDMPICHLPR0 pPicHlpR0;
138	/** Pointer to the PIC GC helpers. */
139	PCPDMPICHLPGC pPicHlpGC;
140	/** Pointer to the device instance - GC Ptr. */
141	GCPTRTYPE(PPDMDEVINS) pDevInsGC;
142	/** Pointer to the device instance - GC Ptr. */
143	HCPTRTYPE(PPDMDEVINS) pDevInsHC;
144	#if HC_ARCH_BITS == 32
145	uint32_t Alignmnet0;
146	#endif
147	#ifdef VBOX_WITH_STATISTICS
148	STAMCOUNTER StatSetIrqGC;
149	STAMCOUNTER StatSetIrqHC;
150	STAMCOUNTER StatClearedActiveIRQ2;
151	STAMCOUNTER StatClearedActiveMasterIRQ;
152	STAMCOUNTER StatClearedActiveSlaveIRQ;
153	#endif
154	} DEVPIC, *PDEVPIC;
155
156
157	#ifndef VBOX_DEVICE_STRUCT_TESTCASE
158	#ifdef LOG_ENABLED
159	static inline void DumpPICState(PicState s, const char szFn)
160	{
161	PDEVPIC pData = PDMINS2DATA(CTXSUFF(s->pDevIns), PDEVPIC);
162
163	Log2(("%s: pic%d: elcr=%x last_irr=%x irr=%x imr=%x isr=%x irq_base=%x\n",
164	szFn, (&pData->aPics[0] == s) ? 0 : 1,
165	s->elcr, s->last_irr, s->irr, s->imr, s->isr, s->irq_base));
166	}
167	#else
168	# define DumpPICState(pData, szFn) do { } while (0)
169	#endif
170
171	/* set irq level. If an edge is detected, then the IRR is set to 1 */
172	static inline void pic_set_irq1(PicState *s, int irq, int level)
173	{
174	int mask;
175	Log(("pic_set_irq1: irq=%d level=%d\n", irq, level));
176	mask = 1 << irq;
177	if (s->elcr & mask) {
178	/* level triggered */
179	if (level) {
180	s->irr \|= mask;
181	s->last_irr \|= mask;
182	} else {
183	s->irr &= ~mask;
184	s->last_irr &= ~mask;
185	}
186	} else {
187	/* edge triggered */
188	if (level) {
189	if ((s->last_irr & mask) == 0)
190	{
191	Log2(("pic_set_irq1 irr=%x last_irr=%x\n", s->irr \| mask, s->last_irr));
192	s->irr \|= mask;
193	}
194	s->last_irr \|= mask;
195	} else {
196	s->last_irr &= ~mask;
197	}
198	}
199	DumpPICState(s, "pic_set_irq1");
200	}
201
202	/* return the highest priority found in mask (highest = smallest
203	number). Return 8 if no irq */
204	static inline int get_priority(PicState *s, int mask)
205	{
206	int priority;
207	if (mask == 0)
208	return 8;
209	priority = 0;
210	while ((mask & (1 << ((priority + s->priority_add) & 7))) == 0)
211	priority++;
212	return priority;
213	}
214
215	/* return the pic wanted interrupt. return -1 if none */
216	static int pic_get_irq(PicState *s)
217	{
218	PicState *pics = &(PDMINS2DATA(CTXSUFF(s->pDevIns), PDEVPIC))->aPics[0];
219	int mask, cur_priority, priority;
220	Log(("pic_get_irq%d: mask=%x\n", (s == pics) ? 0 : 1, s->irr & ~s->imr));
221	DumpPICState(s, "pic_get_irq");
222
223	mask = s->irr & ~s->imr;
224	priority = get_priority(s, mask);
225	Log(("pic_get_irq: priority=%x\n", priority));
226	if (priority == 8)
227	return -1;
228	/* compute current priority. If special fully nested mode on the
229	master, the IRQ coming from the slave is not taken into account
230	for the priority computation. */
231	mask = s->isr;
232	if (s->special_fully_nested_mode && s == &pics[0])
233	mask &= ~(1 << 2);
234	cur_priority = get_priority(s, mask);
235	Log(("pic_get_irq%d: cur_priority=%x pending=%d\n", (s == pics) ? 0 : 1, cur_priority, (priority == 8) ? -1 : (priority + s->priority_add) & 7));
236	if (priority < cur_priority) {
237	/* higher priority found: an irq should be generated */
238	return (priority + s->priority_add) & 7;
239	} else {
240	return -1;
241	}
242	}
243
244	/* raise irq to CPU if necessary. must be called every time the active
245	irq may change */
246	static int pic_update_irq(PDEVPIC pData)
247	{
248	PicState *pics = &pData->aPics[0];
249	int irq2, irq;
250
251	/* first look at slave pic */
252	irq2 = pic_get_irq(&pics[1]);
253	Log(("pic_update_irq irq2=%d\n", irq2));
254	if (irq2 >= 0) {
255	/* if irq request by slave pic, signal master PIC */
256	pic_set_irq1(&pics[0], 2, 1);
257	pic_set_irq1(&pics[0], 2, 0);
258	}
259	/* look at requested irq */
260	irq = pic_get_irq(&pics[0]);
261	if (irq >= 0)
262	{
263	/* If irq 2 is pending on the master pic, then there must be one pending on the slave pic too! Otherwise we'll get
264	* spurious slave interrupts in picGetInterrupt.
265	*/
266	if (irq != 2 \|\| irq2 != -1)
267	{
268	#if defined(DEBUG_PIC)
269	int i;
270	for(i = 0; i < 2; i++) {
271	Log(("pic%d: imr=%x irr=%x padd=%d\n",
272	i, pics[i].imr, pics[i].irr,
273	pics[i].priority_add));
274	}
275	Log(("pic: cpu_interrupt\n"));
276	#endif
277	pData->CTXALLSUFF(pPicHlp)->pfnSetInterruptFF(pData->CTXSUFF(pDevIns));
278	}
279	else
280	{
281	STAM_COUNTER_INC(&pData->StatClearedActiveIRQ2);
282	Log(("pic_update_irq: irq 2 is active, but no interrupt is pending on the slave pic!!\n"));
283	/* Clear it here, so lower priority interrupts can still be dispatched. */
284	/** @note Is this correct? */
285	pics[0].irr &= ~(1 << 2);
286	}
287	}
288	return VINF_SUCCESS;
289	}
290
291	/** @note if an interrupt line state changes from unmasked to masked, then it must be deactivated when currently pending! */
292	static void pic_update_imr(PDEVPIC pData, PicState *s, uint8_t val)
293	{
294	int irq, intno;
295	PicState *pActivePIC;
296
297	/* Query the current pending irq, if any. */
298	pActivePIC = &pData->aPics[0];
299	intno = irq = pic_get_irq(pActivePIC);
300	if (irq == 2)
301	{
302	pActivePIC = &pData->aPics[1];
303	irq = pic_get_irq(pActivePIC);
304	intno = irq + 8;
305	}
306
307	/* Update IMR */
308	s->imr = val;
309
310	/* If an interrupt is pending and now masked, then clear the FF flag. */
311	if ( irq >= 0
312	&& ((1 << irq) & ~pActivePIC->imr) == 0)
313	{
314	Log(("pic_update_imr: pic0: elcr=%x last_irr=%x irr=%x imr=%x isr=%x irq_base=%x\n",
315	pData->aPics[0].elcr, pData->aPics[0].last_irr, pData->aPics[0].irr, pData->aPics[0].imr, pData->aPics[0].isr, pData->aPics[0].irq_base));
316	Log(("pic_update_imr: pic1: elcr=%x last_irr=%x irr=%x imr=%x isr=%x irq_base=%x\n",
317	pData->aPics[1].elcr, pData->aPics[1].last_irr, pData->aPics[1].irr, pData->aPics[1].imr, pData->aPics[1].isr, pData->aPics[1].irq_base));
318
319	/* Clear pending IRQ 2 on master controller in case of slave interrupt. */
320	/** @todo Is this correct? */
321	if (intno > 7)
322	{
323	pData->aPics[0].irr &= ~(1 << 2);
324	STAM_COUNTER_INC(&pData->StatClearedActiveSlaveIRQ);
325	}
326	else
327	STAM_COUNTER_INC(&pData->StatClearedActiveMasterIRQ);
328
329	Log(("pic_update_imr: clear pending interrupt %d\n", intno));
330	pData->CTXALLSUFF(pPicHlp)->pfnClearInterruptFF(pData->CTXSUFF(pDevIns));
331	}
332	}
333
334
335	/**
336	* Set the an IRQ.
337	*
338	* @param pDevIns Device instance of the PICs.
339	* @param iIrq IRQ number to set.
340	* @param iLevel IRQ level.
341	*/
342	PDMBOTHCBDECL(void) picSetIrq(PPDMDEVINS pDevIns, int iIrq, int iLevel)
343	{
344	PDEVPIC pData = PDMINS2DATA(pDevIns, PDEVPIC);
345	Assert(pData->CTXSUFF(pDevIns) == pDevIns);
346	Assert(pData->aPics[0].CTXSUFF(pDevIns) == pDevIns);
347	Assert(pData->aPics[1].CTXSUFF(pDevIns) == pDevIns);
348	AssertMsg(iIrq < 16, ("iIrq=%d\n", iIrq));
349
350	Log(("picSetIrq %d %d\n", iIrq, iLevel));
351	DumpPICState(&pData->aPics[0], "picSetIrq");
352	DumpPICState(&pData->aPics[1], "picSetIrq");
353	STAM_COUNTER_INC(&pData->CTXSUFF(StatSetIrq));
354	pic_set_irq1(&pData->aPics[iIrq >> 3], iIrq & 7, iLevel & PDM_IRQ_LEVEL_HIGH);
355	pic_update_irq(pData);
356	if ((iLevel & PDM_IRQ_LEVEL_FLIP_FLOP) == PDM_IRQ_LEVEL_FLIP_FLOP)
357	{
358	pic_set_irq1(&pData->aPics[iIrq >> 3], iIrq & 7, 0);
359	pic_update_irq(pData);
360	}
361	}
362
363
364	/* acknowledge interrupt 'irq' */
365	static inline void pic_intack(PicState *s, int irq)
366	{
367	if (s->auto_eoi) {
368	if (s->rotate_on_auto_eoi)
369	s->priority_add = (irq + 1) & 7;
370	} else {
371	s->isr \|= (1 << irq);
372	}
373	/* We don't clear a level sensitive interrupt here */
374	if (!(s->elcr & (1 << irq)))
375	s->irr &= ~(1 << irq);
376	}
377
378
379	/**
380	* Get a pending interrupt.
381	*
382	* @returns Pending interrupt number.
383	* @param pDevIns Device instance of the PICs.
384	*/
385	PDMBOTHCBDECL(int) picGetInterrupt(PPDMDEVINS pDevIns)
386	{
387	PDEVPIC pData = PDMINS2DATA(pDevIns, PDEVPIC);
388	int irq;
389	int irq2;
390	int intno;
391
392	/* read the irq from the PIC */
393	DumpPICState(&pData->aPics[0], "picGetInterrupt");
394	DumpPICState(&pData->aPics[1], "picGetInterrupt");
395
396	irq = pic_get_irq(&pData->aPics[0]);
397	if (irq >= 0)
398	{
399	pic_intack(&pData->aPics[0], irq);
400	if (irq == 2)
401	{
402	irq2 = pic_get_irq(&pData->aPics[1]);
403	if (irq2 >= 0) {
404	pic_intack(&pData->aPics[1], irq2);
405	}
406	else
407	{
408	/* spurious IRQ on slave controller (impossible) */
409	AssertMsgFailed(("picGetInterrupt: spurious IRQ on slave controller\n"));
410	irq2 = 7;
411	}
412	intno = pData->aPics[1].irq_base + irq2;
413	Log2(("picGetInterrupt1: %x base=%x irq=%x\n", intno, pData->aPics[1].irq_base, irq2));
414	irq = irq2 + 8;
415	}
416	else {
417	intno = pData->aPics[0].irq_base + irq;
418	Log2(("picGetInterrupt0: %x base=%x irq=%x\n", intno, pData->aPics[0].irq_base, irq));
419	}
420	}
421	else
422	{
423	/* spurious IRQ on host controller (impossible) */
424	AssertMsgFailed(("picGetInterrupt: spurious IRQ on master controller\n"));
425	irq = 7;
426	intno = pData->aPics[0].irq_base + irq;
427	}
428	pic_update_irq(pData);
429
430	Log(("picGetInterrupt: pending 0:%d 1:%d\n", pic_get_irq(&pData->aPics[0]), pic_get_irq(&pData->aPics[1])));
431
432	return intno;
433	}
434
435	static void pic_reset(PicState *s)
436	{
437	HCPTRTYPE(PPDMDEVINS) pDevInsHC = s->pDevInsHC;
438	GCPTRTYPE(PPDMDEVINS) pDevInsGC = s->pDevInsGC;
439	int tmp, tmp2;
440
441	tmp = s->elcr_mask;
442	tmp2 = s->elcr;
443	memset(s, 0, sizeof(PicState));
444	s->elcr_mask = tmp;
445	s->elcr = tmp2;
446	s->pDevInsHC = pDevInsHC;
447	s->pDevInsGC = pDevInsGC;
448	}
449
450
451	static int pic_ioport_write(void *opaque, uint32_t addr, uint32_t val)
452	{
453	PicState s = (PicState)opaque;
454	PDEVPIC pData = PDMINS2DATA(CTXSUFF(s->pDevIns), PDEVPIC);
455	int rc = VINF_SUCCESS;
456	int priority, cmd, irq;
457
458	Log(("pic_write: addr=0x%02x val=0x%02x\n", addr, val));
459	addr &= 1;
460	if (addr == 0) {
461	if (val & 0x10) {
462	/* init */
463	pic_reset(s);
464	/* deassert a pending interrupt */
465	pData->CTXALLSUFF(pPicHlp)->pfnClearInterruptFF(pData->CTXSUFF(pDevIns));
466
467	s->init_state = 1;
468	s->init4 = val & 1;
469	if (val & 0x02)
470	AssertReleaseMsgFailed(("single mode not supported"));
471	if (val & 0x08)
472	AssertReleaseMsgFailed(("level sensitive irq not supported"));
473	} else if (val & 0x08) {
474	if (val & 0x04)
475	s->poll = 1;
476	if (val & 0x02)
477	s->read_reg_select = val & 1;
478	if (val & 0x40)
479	s->special_mask = (val >> 5) & 1;
480	} else {
481	cmd = val >> 5;
482	switch(cmd) {
483	case 0:
484	case 4:
485	s->rotate_on_auto_eoi = cmd >> 2;
486	break;
487	case 1: /* end of interrupt */
488	case 5:
489	{
490	priority = get_priority(s, s->isr);
491	if (priority != 8) {
492	irq = (priority + s->priority_add) & 7;
493	Log(("pic_write: EOI prio=%d irq=%d\n", priority, irq));
494	s->isr &= ~(1 << irq);
495	if (cmd == 5)
496	s->priority_add = (irq + 1) & 7;
497	rc = pic_update_irq(pData);
498	Assert(rc == VINF_SUCCESS);
499	}
500	break;
501	}
502	case 3:
503	{
504	irq = val & 7;
505	Log(("pic_write: EOI2 for irq %d\n", irq));
506	s->isr &= ~(1 << irq);
507	rc = pic_update_irq(pData);
508	Assert(rc == VINF_SUCCESS);
509	break;
510	}
511	case 6:
512	{
513	s->priority_add = (val + 1) & 7;
514	rc = pic_update_irq(pData);
515	Assert(rc == VINF_SUCCESS);
516	break;
517	}
518	case 7:
519	{
520	irq = val & 7;
521	Log(("pic_write: EOI3 for irq %d\n", irq));
522	s->isr &= ~(1 << irq);
523	s->priority_add = (irq + 1) & 7;
524	rc = pic_update_irq(pData);
525	Assert(rc == VINF_SUCCESS);
526	break;
527	}
528	default:
529	/* no operation */
530	break;
531	}
532	}
533	} else {
534	switch(s->init_state) {
535	case 0:
536	{
537	/* normal mode */
538	pic_update_imr(pData, s, val);
539
540	rc = pic_update_irq(pData);
541	Assert(rc == VINF_SUCCESS);
542	break;
543	}
544	case 1:
545	s->irq_base = val & 0xf8;
546	s->init_state = 2;
547	Log(("pic_write: set irq base to %x\n", s->irq_base));
548	break;
549	case 2:
550	if (s->init4) {
551	s->init_state = 3;
552	} else {
553	s->init_state = 0;
554	}
555	break;
556	case 3:
557	s->special_fully_nested_mode = (val >> 4) & 1;
558	s->auto_eoi = (val >> 1) & 1;
559	s->init_state = 0;
560	Log(("pic_write: special_fully_nested_mode=%d auto_eoi=%d\n", s->special_fully_nested_mode, s->auto_eoi));
561	break;
562	}
563	}
564	return rc;
565	}
566
567
568	static uint32_t pic_poll_read (PicState *s, uint32_t addr1)
569	{
570	PDEVPIC pData = PDMINS2DATA(CTXSUFF(s->pDevIns), PDEVPIC);
571	PicState *pics = &pData->aPics[0];
572	int ret;
573
574	ret = pic_get_irq(s);
575	if (ret >= 0) {
576	if (addr1 >> 7) {
577	Log2(("pic_poll_read: clear slave irq (isr)\n"));
578	pics[0].isr &= ~(1 << 2);
579	pics[0].irr &= ~(1 << 2);
580	}
581	Log2(("pic_poll_read: clear irq %d (isr)\n", ret));
582	s->irr &= ~(1 << ret);
583	s->isr &= ~(1 << ret);
584	if (addr1 >> 7 \|\| ret != 2)
585	pic_update_irq(pData);
586	} else {
587	ret = 0x07;
588	pic_update_irq(pData);
589	}
590
591	return ret;
592	}
593
594
595	static uint32_t pic_ioport_read(void opaque, uint32_t addr1, int pRC)
596	{
597	PicState s = (PicState)opaque;
598	unsigned int addr;
599	int ret;
600
601	*pRC = VINF_SUCCESS;
602
603	addr = addr1;
604	addr &= 1;
605	if (s->poll) {
606	ret = pic_poll_read(s, addr1);
607	s->poll = 0;
608	} else {
609	if (addr == 0) {
610	if (s->read_reg_select)
611	ret = s->isr;
612	else
613	ret = s->irr;
614	} else {
615	ret = s->imr;
616	}
617	}
618	Log(("pic_read: addr=0x%02x val=0x%02x\n", addr1, ret));
619	return ret;
620	}
621
622
623
624	#ifdef IN_RING3
625
626	static void pic_save(QEMUFile f, void opaque)
627	{
628	PicState s = (PicState)opaque;
629
630	qemu_put_8s(f, &s->last_irr);
631	qemu_put_8s(f, &s->irr);
632	qemu_put_8s(f, &s->imr);
633	qemu_put_8s(f, &s->isr);
634	qemu_put_8s(f, &s->priority_add);
635	qemu_put_8s(f, &s->irq_base);
636	qemu_put_8s(f, &s->read_reg_select);
637	qemu_put_8s(f, &s->poll);
638	qemu_put_8s(f, &s->special_mask);
639	qemu_put_8s(f, &s->init_state);
640	qemu_put_8s(f, &s->auto_eoi);
641	qemu_put_8s(f, &s->rotate_on_auto_eoi);
642	qemu_put_8s(f, &s->special_fully_nested_mode);
643	qemu_put_8s(f, &s->init4);
644	qemu_put_8s(f, &s->elcr);
645	}
646
647	static int pic_load(QEMUFile f, void opaque, int version_id)
648	{
649	PicState s = (PicState)opaque;
650
651	if (version_id != 1)
652	return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
653
654	qemu_get_8s(f, &s->last_irr);
655	qemu_get_8s(f, &s->irr);
656	qemu_get_8s(f, &s->imr);
657	qemu_get_8s(f, &s->isr);
658	qemu_get_8s(f, &s->priority_add);
659	qemu_get_8s(f, &s->irq_base);
660	qemu_get_8s(f, &s->read_reg_select);
661	qemu_get_8s(f, &s->poll);
662	qemu_get_8s(f, &s->special_mask);
663	qemu_get_8s(f, &s->init_state);
664	qemu_get_8s(f, &s->auto_eoi);
665	qemu_get_8s(f, &s->rotate_on_auto_eoi);
666	qemu_get_8s(f, &s->special_fully_nested_mode);
667	qemu_get_8s(f, &s->init4);
668	qemu_get_8s(f, &s->elcr);
669	return 0;
670	}
671	#endif /* IN_RING3 */
672
673
674	/* -=-=-=-=-=- wrappers -=-=-=-=-=- */
675
676	/**
677	* Port I/O Handler for IN operations.
678	*
679	* @returns VBox status code.
680	*
681	* @param pDevIns The device instance.
682	* @param pvUser User argument - pointer to the PIC in question.
683	* @param uPort Port number used for the IN operation.
684	* @param pu32 Where to store the result.
685	* @param cb Number of bytes read.
686	*/
687	PDMBOTHCBDECL(int) picIOPortRead(PPDMDEVINS pDevIns, void pvUser, RTIOPORT Port, uint32_t pu32, unsigned cb)
688	{
689	PDEVPIC pData = PDMINS2DATA(pDevIns, PDEVPIC);
690	uint32_t iPic = (uint32_t)(uintptr_t)pvUser;
691
692	Assert(iPic == 0 \|\| iPic == 1);
693	if (cb == 1)
694	{
695	int rc;
696	PIC_LOCK(pData, VINF_IOM_HC_IOPORT_READ);
697	*pu32 = pic_ioport_read(&pData->aPics[iPic], Port, &rc);
698	PIC_UNLOCK(pData);
699	return rc;
700	}
701	return VERR_IOM_IOPORT_UNUSED;
702	}
703
704	/**
705	* Port I/O Handler for OUT operations.
706	*
707	* @returns VBox status code.
708	*
709	* @param pDevIns The device instance.
710	* @param pvUser User argument - pointer to the PIC in question.
711	* @param uPort Port number used for the IN operation.
712	* @param u32 The value to output.
713	* @param cb The value size in bytes.
714	*/
715	PDMBOTHCBDECL(int) picIOPortWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb)
716	{
717	PDEVPIC pData = PDMINS2DATA(pDevIns, PDEVPIC);
718	uint32_t iPic = (uint32_t)(uintptr_t)pvUser;
719
720	Assert(iPic == 0 \|\| iPic == 1);
721
722	if (cb == 1)
723	{
724	int rc;
725	PIC_LOCK(pData, VINF_IOM_HC_IOPORT_WRITE);
726	rc = pic_ioport_write(&pData->aPics[iPic], Port, u32);
727	PIC_UNLOCK(pData);
728	return rc;
729	}
730	return VINF_SUCCESS;
731	}
732
733
734	/**
735	* Port I/O Handler for IN operations.
736	*
737	* @returns VBox status code.
738	*
739	* @param pDevIns The device instance.
740	* @param pvUser User argument - pointer to the PIC in question.
741	* @param uPort Port number used for the IN operation.
742	* @param pu32 Where to store the result.
743	* @param cb Number of bytes read.
744	*/
745	PDMBOTHCBDECL(int) picIOPortElcrRead(PPDMDEVINS pDevIns, void pvUser, RTIOPORT Port, uint32_t pu32, unsigned cb)
746	{
747	if (cb == 1)
748	{
749	PicState s = (PicState)pvUser;
750	PIC_LOCK(PDMINS2DATA(pDevIns, PDEVPIC), VINF_IOM_HC_IOPORT_READ);
751	*pu32 = s->elcr;
752	PIC_UNLOCK(PDMINS2DATA(pDevIns, PDEVPIC));
753	return VINF_SUCCESS;
754	}
755	return VERR_IOM_IOPORT_UNUSED;
756	}
757
758	/**
759	* Port I/O Handler for OUT operations.
760	*
761	* @returns VBox status code.
762	*
763	* @param pDevIns The device instance.
764	* @param pvUser User argument - pointer to the PIC in question.
765	* @param uPort Port number used for the IN operation.
766	* @param u32 The value to output.
767	* @param cb The value size in bytes.
768	*/
769	PDMBOTHCBDECL(int) picIOPortElcrWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb)
770	{
771	if (cb == 1)
772	{
773	PicState s = (PicState)pvUser;
774	PIC_LOCK(PDMINS2DATA(pDevIns, PDEVPIC), VINF_IOM_HC_IOPORT_WRITE);
775	s->elcr = u32 & s->elcr_mask;
776	PIC_UNLOCK(PDMINS2DATA(pDevIns, PDEVPIC));
777	}
778	return VINF_SUCCESS;
779	}
780
781
782	#ifdef IN_RING3
783
784	#ifdef DEBUG
785	/**
786	* PIC status info callback.
787	*
788	* @param pDevIns The device instance.
789	* @param pHlp The output helpers.
790	* @param pszArgs The arguments.
791	*/
792	static DECLCALLBACK(void) picInfo(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
793	{
794	PDEVPIC pData = PDMINS2DATA(pDevIns, PDEVPIC);
795
796	/*
797	* Show info.
798	*/
799	for (int i=0;i<2;i++)
800	{
801	pHlp->pfnPrintf(pHlp, "PIC%d:\n", i);
802	pHlp->pfnPrintf(pHlp, " last_irr = %02x\n", pData->aPics[i].last_irr);
803	pHlp->pfnPrintf(pHlp, " irr = %02x\n", pData->aPics[i].irr);
804	pHlp->pfnPrintf(pHlp, " imr = %02x\n", pData->aPics[i].imr);
805	pHlp->pfnPrintf(pHlp, " isr = %02x\n", pData->aPics[i].isr);
806	pHlp->pfnPrintf(pHlp, " priority_add = %02x\n", pData->aPics[i].priority_add);
807	pHlp->pfnPrintf(pHlp, " irq_base = %02x\n", pData->aPics[i].irq_base);
808	pHlp->pfnPrintf(pHlp, " read_reg_select = %02x\n", pData->aPics[i].read_reg_select);
809	pHlp->pfnPrintf(pHlp, " poll = %02x\n", pData->aPics[i].poll);
810	pHlp->pfnPrintf(pHlp, " special_mask = %02x\n", pData->aPics[i].special_mask);
811	pHlp->pfnPrintf(pHlp, " init_state = %02x\n", pData->aPics[i].init_state);
812	pHlp->pfnPrintf(pHlp, " auto_eoi = %02x\n", pData->aPics[i].auto_eoi);
813	pHlp->pfnPrintf(pHlp, " rotate_on_auto_eoi = %02x\n", pData->aPics[i].rotate_on_auto_eoi);
814	pHlp->pfnPrintf(pHlp, " special_fully_nested_mode = %02x\n", pData->aPics[i].special_fully_nested_mode);
815	pHlp->pfnPrintf(pHlp, " init4 = %02x\n", pData->aPics[i].init4);
816	pHlp->pfnPrintf(pHlp, " elcr = %02x\n", pData->aPics[i].elcr);
817	pHlp->pfnPrintf(pHlp, " elcr_mask = %02x\n", pData->aPics[i].elcr_mask);
818	}
819	}
820	#endif /* DEBUG */
821
822	/**
823	* Saves a state of the programmable interrupt controller device.
824	*
825	* @returns VBox status code.
826	* @param pDevIns The device instance.
827	* @param pSSMHandle The handle to save the state to.
828	*/
829	static DECLCALLBACK(int) picSaveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSMHandle)
830	{
831	PDEVPIC pData = PDMINS2DATA(pDevIns, PDEVPIC);
832	pic_save(pSSMHandle, &pData->aPics[0]);
833	pic_save(pSSMHandle, &pData->aPics[1]);
834	return VINF_SUCCESS;
835	}
836
837
838	/**
839	* Loads a saved programmable interrupt controller device state.
840	*
841	* @returns VBox status code.
842	* @param pDevIns The device instance.
843	* @param pSSMHandle The handle to the saved state.
844	* @param u32Version The data unit version number.
845	*/
846	static DECLCALLBACK(int) picLoadExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSMHandle, uint32_t u32Version)
847	{
848	PDEVPIC pData = PDMINS2DATA(pDevIns, PDEVPIC);
849	int rc = pic_load(pSSMHandle, &pData->aPics[0], u32Version);
850	if (VBOX_SUCCESS(rc))
851	rc = pic_load(pSSMHandle, &pData->aPics[1], u32Version);
852	return rc;
853	}
854
855
856	/* -=-=-=-=-=- real code -=-=-=-=-=- */
857
858	/**
859	* Reset notification.
860	*
861	* @returns VBox status.
862	* @param pDevIns The device instance data.
863	*/
864	static DECLCALLBACK(void) picReset(PPDMDEVINS pDevIns)
865	{
866	PDEVPIC pData = PDMINS2DATA(pDevIns, PDEVPIC);
867	unsigned i;
868	LogFlow(("picReset:\n"));
869	#ifdef VBOX_WITH_PDM_LOCK
870	pData->pPicHlpR3->pfnLock(pDevIns, VERR_INTERNAL_ERROR);
871	#endif
872
873	for (i = 0; i < ELEMENTS(pData->aPics); i++)
874	pic_reset(&pData->aPics[i]);
875
876	PIC_UNLOCK(pData);
877	}
878
879
880	/**
881	* @copydoc FNPDMDEVRELOCATE
882	*/
883	static DECLCALLBACK(void) picRelocate(PPDMDEVINS pDevIns, RTGCINTPTR offDelta)
884	{
885	PDEVPIC pData = PDMINS2DATA(pDevIns, PDEVPIC);
886	unsigned i;
887
888	pData->pDevInsGC = PDMDEVINS_2_GCPTR(pDevIns);
889	pData->pPicHlpGC = pData->pPicHlpR3->pfnGetGCHelpers(pDevIns);
890	for (i = 0; i < ELEMENTS(pData->aPics); i++)
891	pData->aPics[i].pDevInsGC = PDMDEVINS_2_GCPTR(pDevIns);
892	}
893
894
895	/**
896	* @copydoc FNPDMDEVCONSTRUCT
897	*/
898	static DECLCALLBACK(int) picConstruct(PPDMDEVINS pDevIns, int iInstance, PCFGMNODE pCfgHandle)
899	{
900	PDEVPIC pData = PDMINS2DATA(pDevIns, PDEVPIC);
901	PDMPICREG PicReg;
902	int rc;
903	bool fGCEnabled;
904	bool fR0Enabled;
905	Assert(iInstance == 0);
906
907	/*
908	* Validate and read configuration.
909	*/
910	if (!CFGMR3AreValuesValid(pCfgHandle, "GCEnabled\0R0Enabled\0"))
911	return VERR_PDM_DEVINS_UNKNOWN_CFG_VALUES;
912
913	rc = CFGMR3QueryBool(pCfgHandle, "GCEnabled", &fGCEnabled);
914	if (rc == VERR_CFGM_VALUE_NOT_FOUND)
915	fGCEnabled = true;
916	else if (VBOX_FAILURE(rc))
917	return PDMDEV_SET_ERROR(pDevIns, rc,
918	N_("Configuration error: failed to read GCEnabled as boolean"));
919
920	rc = CFGMR3QueryBool(pCfgHandle, "R0Enabled", &fR0Enabled);
921	if (rc == VERR_CFGM_VALUE_NOT_FOUND)
922	fR0Enabled = true;
923	else if (VBOX_FAILURE(rc))
924	return PDMDEV_SET_ERROR(pDevIns, rc,
925	N_("Configuration error: failed to read R0Enabled as boolean"));
926
927	Log(("i8259: fGCEnabled=%d fR0Enabled=%d\n", fGCEnabled, fR0Enabled));
928
929	/*
930	* Init the data.
931	*/
932	Assert(ELEMENTS(pData->aPics) == 2);
933	pData->pDevInsHC = pDevIns;
934	pData->pDevInsGC = PDMDEVINS_2_GCPTR(pDevIns);
935	pData->aPics[0].elcr_mask = 0xf8;
936	pData->aPics[1].elcr_mask = 0xde;
937	pData->aPics[0].pDevInsHC = pDevIns;
938	pData->aPics[1].pDevInsHC = pDevIns;
939	pData->aPics[0].pDevInsGC = PDMDEVINS_2_GCPTR(pDevIns);
940	pData->aPics[1].pDevInsGC = PDMDEVINS_2_GCPTR(pDevIns);
941
942	/*
943	* Register PIC, I/O ports and save state.
944	*/
945	PicReg.u32Version = PDM_PICREG_VERSION;
946	PicReg.pfnSetIrqHC = picSetIrq;
947	PicReg.pfnGetInterruptHC = picGetInterrupt;
948	if (fGCEnabled)
949	{
950	PicReg.pszSetIrqGC = "picSetIrq";
951	PicReg.pszGetInterruptGC = "picGetInterrupt";
952	}
953	else
954	{
955	PicReg.pszSetIrqGC = NULL;
956	PicReg.pszGetInterruptGC = NULL;
957	}
958
959	if (fR0Enabled)
960	{
961	PicReg.pszSetIrqR0 = "picSetIrq";
962	PicReg.pszGetInterruptR0 = "picGetInterrupt";
963	}
964	else
965	{
966	PicReg.pszSetIrqR0 = NULL;
967	PicReg.pszGetInterruptR0 = NULL;
968	}
969
970	Assert(pDevIns->pDevHlp->pfnPICRegister);
971	rc = pDevIns->pDevHlp->pfnPICRegister(pDevIns, &PicReg, &pData->pPicHlpR3);
972	if (VBOX_FAILURE(rc))
973	{
974	AssertMsgFailed(("PICRegister -> %Vrc\n", rc));
975	return rc;
976	}
977	if (fGCEnabled)
978	pData->pPicHlpGC = pData->pPicHlpR3->pfnGetGCHelpers(pDevIns);
979	rc = PDMDevHlpIOPortRegister(pDevIns, 0x20, 2, (void *)0, picIOPortWrite, picIOPortRead, NULL, NULL, "i8259 PIC #0");
980	if (VBOX_FAILURE(rc))
981	return rc;
982	rc = PDMDevHlpIOPortRegister(pDevIns, 0xa0, 2, (void *)1, picIOPortWrite, picIOPortRead, NULL, NULL, "i8259 PIC #1");
983	if (VBOX_FAILURE(rc))
984	return rc;
985	if (fGCEnabled)
986	{
987	rc = PDMDevHlpIOPortRegisterGC(pDevIns, 0x20, 2, 0, "picIOPortWrite", "picIOPortRead", NULL, NULL, "i8259 PIC #0");
988	if (VBOX_FAILURE(rc))
989	return rc;
990	rc = PDMDevHlpIOPortRegisterGC(pDevIns, 0xa0, 2, 1, "picIOPortWrite", "picIOPortRead", NULL, NULL, "i8259 PIC #1");
991	if (VBOX_FAILURE(rc))
992	return rc;
993	}
994	if (fR0Enabled)
995	{
996	pData->pPicHlpR0 = pData->pPicHlpR3->pfnGetR0Helpers(pDevIns);
997
998	rc = PDMDevHlpIOPortRegisterR0(pDevIns, 0x20, 2, 0, "picIOPortWrite", "picIOPortRead", NULL, NULL, "i8259 PIC #0");
999	if (VBOX_FAILURE(rc))
1000	return rc;
1001	rc = PDMDevHlpIOPortRegisterR0(pDevIns, 0xa0, 2, 1, "picIOPortWrite", "picIOPortRead", NULL, NULL, "i8259 PIC #1");
1002	if (VBOX_FAILURE(rc))
1003	return rc;
1004	}
1005
1006	rc = PDMDevHlpIOPortRegister(pDevIns, 0x4d0, 1, &pData->aPics[0],
1007	picIOPortElcrWrite, picIOPortElcrRead, NULL, NULL, "i8259 PIC #0 - elcr");
1008	if (VBOX_FAILURE(rc))
1009	return rc;
1010	rc = PDMDevHlpIOPortRegister(pDevIns, 0x4d1, 1, &pData->aPics[1],
1011	picIOPortElcrWrite, picIOPortElcrRead, NULL, NULL, "i8259 PIC #1 - elcr");
1012	if (VBOX_FAILURE(rc))
1013	return rc;
1014	if (fGCEnabled)
1015	{
1016	RTGCPTR pDataGC = PDMINS2DATA_GCPTR(pDevIns);
1017	rc = PDMDevHlpIOPortRegisterGC(pDevIns, 0x4d0, 1, pDataGC + RT_OFFSETOF(DEVPIC, aPics[0]),
1018	"picIOPortElcrWrite", "picIOPortElcrRead", NULL, NULL, "i8259 PIC #0 - elcr");
1019	if (VBOX_FAILURE(rc))
1020	return rc;
1021	rc = PDMDevHlpIOPortRegisterGC(pDevIns, 0x4d1, 1, pDataGC + RT_OFFSETOF(DEVPIC, aPics[1]),
1022	"picIOPortElcrWrite", "picIOPortElcrRead", NULL, NULL, "i8259 PIC #1 - elcr");
1023	if (VBOX_FAILURE(rc))
1024	return rc;
1025	}
1026	if (fR0Enabled)
1027	{
1028	RTR0PTR pDataR0 = PDMINS2DATA_R0PTR(pDevIns);
1029	rc = PDMDevHlpIOPortRegisterR0(pDevIns, 0x4d0, 1, pDataR0 + RT_OFFSETOF(DEVPIC, aPics[0]),
1030	"picIOPortElcrWrite", "picIOPortElcrRead", NULL, NULL, "i8259 PIC #0 - elcr");
1031	if (VBOX_FAILURE(rc))
1032	return rc;
1033	rc = PDMDevHlpIOPortRegisterR0(pDevIns, 0x4d1, 1, pDataR0 + RT_OFFSETOF(DEVPIC, aPics[1]),
1034	"picIOPortElcrWrite", "picIOPortElcrRead", NULL, NULL, "i8259 PIC #1 - elcr");
1035	if (VBOX_FAILURE(rc))
1036	return rc;
1037	}
1038
1039	rc = PDMDevHlpSSMRegister(pDevIns, pDevIns->pDevReg->szDeviceName, iInstance, 1 /* version /, sizeof(pData),
1040	NULL, picSaveExec, NULL,
1041	NULL, picLoadExec, NULL);
1042	if (VBOX_FAILURE(rc))
1043	return rc;
1044
1045
1046	#ifdef DEBUG
1047	/*
1048	* Register the info item.
1049	*/
1050	PDMDevHlpDBGFInfoRegister(pDevIns, "pic", "PIC info.", picInfo);
1051	#endif
1052
1053	/*
1054	* Initialize the device state.
1055	*/
1056	picReset(pDevIns);
1057
1058	#ifdef VBOX_WITH_STATISTICS
1059	/*
1060	* Statistics.
1061	*/
1062	PDMDevHlpSTAMRegister(pDevIns, &pData->StatSetIrqGC, STAMTYPE_COUNTER, "/PDM/PIC/SetIrqGC", STAMUNIT_OCCURENCES, "Number of PIC SetIrq calls in GC.");
1063	PDMDevHlpSTAMRegister(pDevIns, &pData->StatSetIrqHC, STAMTYPE_COUNTER, "/PDM/PIC/SetIrqHC", STAMUNIT_OCCURENCES, "Number of PIC SetIrq calls in HC.");
1064
1065	PDMDevHlpSTAMRegister(pDevIns, &pData->StatClearedActiveIRQ2, STAMTYPE_COUNTER, "/PDM/PIC/Masked/ActiveIRQ2", STAMUNIT_OCCURENCES, "Number of cleared irq 2.");
1066	PDMDevHlpSTAMRegister(pDevIns, &pData->StatClearedActiveMasterIRQ, STAMTYPE_COUNTER, "/PDM/PIC/Masked/ActiveMaster", STAMUNIT_OCCURENCES, "Number of cleared master irqs.");
1067	PDMDevHlpSTAMRegister(pDevIns, &pData->StatClearedActiveSlaveIRQ, STAMTYPE_COUNTER, "/PDM/PIC/Masked/ActiveSlave", STAMUNIT_OCCURENCES, "Number of cleared slave irqs.");
1068	#endif
1069
1070	return VINF_SUCCESS;
1071	}
1072
1073
1074	/**
1075	* The device registration structure.
1076	*/
1077	const PDMDEVREG g_DeviceI8259 =
1078	{
1079	/* u32Version */
1080	PDM_DEVREG_VERSION,
1081	/* szDeviceName */
1082	"i8259",
1083	/* szGCMod */
1084	"VBoxDDGC.gc",
1085	/* szR0Mod */
1086	"VBoxDDR0.r0",
1087	/* pszDescription */
1088	"Intel 8259 Programmable Interrupt Controller (PIC) Device.",
1089	/* fFlags */
1090	PDM_DEVREG_FLAGS_HOST_BITS_DEFAULT \| PDM_DEVREG_FLAGS_GUEST_BITS_32_64 \| PDM_DEVREG_FLAGS_PAE36 \| PDM_DEVREG_FLAGS_GC \| PDM_DEVREG_FLAGS_R0,
1091	/* fClass */
1092	PDM_DEVREG_CLASS_PIC,
1093	/* cMaxInstances */
1094	1,
1095	/* cbInstance */
1096	sizeof(DEVPIC),
1097	/* pfnConstruct */
1098	picConstruct,
1099	/* pfnDestruct */
1100	NULL,
1101	/* pfnRelocate */
1102	picRelocate,
1103	/* pfnIOCtl */
1104	NULL,
1105	/* pfnPowerOn */
1106	NULL,
1107	/* pfnReset */
1108	picReset,
1109	/* pfnSuspend */
1110	NULL,
1111	/* pfnResume */
1112	NULL,
1113	/* pfnAttach */
1114	NULL,
1115	/* pfnDetach */
1116	NULL,
1117	/* pfnQueryInterface. */
1118	NULL
1119	};
1120
1121	#endif /* IN_RING3 */
1122	#endif /* !VBOX_DEVICE_STRUCT_TESTCASE */
1123

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source: vbox/trunk/src/VBox/Devices/PC/DevPIC.cpp@ 3429

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