DevPIC.cpp@ 6290

Last change on this file since 6290 was 5999, checked in by vboxsync, 17 years ago
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1	/* $Id: DevPIC.cpp 5999 2007-12-07 15:05:06Z vboxsync $ */
2	/** @file
3	* Intel 8259 Programmable Interrupt Controller (PIC) Device.
4	*/
5
6	/*
7	* Copyright (C) 2006-2007 innotek GmbH
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18	/*******************************************************************************
19	* Header Files *
20	*******************************************************************************/
21	#define LOG_GROUP LOG_GROUP_DEV_PIC
22	#include <VBox/pdmdev.h>
23	#include <VBox/log.h>
24	#include <iprt/assert.h>
25
26	#include "vl_vbox.h"
27
28
29	/*******************************************************************************
30	* Defined Constants And Macros *
31	*******************************************************************************/
32	/** @def PIC_LOCK
33	* Acquires the PDM lock. This is a NOP if locking is disabled. */
34	/** @def PIC_UNLOCK
35	* Releases the PDM lock. This is a NOP if locking is disabled. */
36	#ifdef VBOX_WITH_PDM_LOCK
37	# define PIC_LOCK(pThis, rc) \
38	do { \
39	int rc2 = (pThis)->CTXALLSUFF(pPicHlp)->pfnLock((pThis)->CTXSUFF(pDevIns), rc); \
40	if (rc2 != VINF_SUCCESS) \
41	return rc2; \
42	} while (0)
43	# define PIC_UNLOCK(pThis) \
44	(pThis)->CTXALLSUFF(pPicHlp)->pfnUnlock((pThis)->CTXSUFF(pDevIns))
45	#else /* !VBOX_WITH_PDM_LOCK */
46	# define PIC_LOCK(pThis, rc) do { } while (0)
47	# define PIC_UNLOCK(pThis) do { } while (0)
48	#endif /* !VBOX_WITH_PDM_LOCK */
49
50
51	#ifndef VBOX_DEVICE_STRUCT_TESTCASE
52	/*******************************************************************************
53	* Internal Functions *
54	*******************************************************************************/
55	__BEGIN_DECLS
56
57	PDMBOTHCBDECL(void) picSetIrq(PPDMDEVINS pDevIns, int iIrq, int iLevel);
58	PDMBOTHCBDECL(int) picGetInterrupt(PPDMDEVINS pDevIns);
59	PDMBOTHCBDECL(int) picIOPortRead(PPDMDEVINS pDevIns, void pvUser, RTIOPORT Port, uint32_t pu32, unsigned cb);
60	PDMBOTHCBDECL(int) picIOPortWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb);
61	PDMBOTHCBDECL(int) picIOPortElcrRead(PPDMDEVINS pDevIns, void pvUser, RTIOPORT Port, uint32_t pu32, unsigned cb);
62	PDMBOTHCBDECL(int) picIOPortElcrWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb);
63
64	__END_DECLS
65	#endif /* !VBOX_DEVICE_STRUCT_TESTCASE */
66
67
68	/*
69	* QEMU 8259 interrupt controller emulation
70	*
71	* Copyright (c) 2003-2004 Fabrice Bellard
72	*
73	* Permission is hereby granted, free of charge, to any person obtaining a copy
74	* of this software and associated documentation files (the "Software"), to deal
75	* in the Software without restriction, including without limitation the rights
76	* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
77	* copies of the Software, and to permit persons to whom the Software is
78	* furnished to do so, subject to the following conditions:
79	*
80	* The above copyright notice and this permission notice shall be included in
81	* all copies or substantial portions of the Software.
82	*
83	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
84	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
85	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
86	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
87	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
88	* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
89	* THE SOFTWARE.
90	*/
91
92	/* debug PIC */
93	#define DEBUG_PIC
94
95	/#define DEBUG_IRQ_COUNT/
96
97	typedef struct PicState {
98	uint8_t last_irr; /* edge detection */
99	uint8_t irr; /* interrupt request register */
100	uint8_t imr; /* interrupt mask register */
101	uint8_t isr; /* interrupt service register */
102	uint8_t priority_add; /* highest irq priority */
103	uint8_t irq_base;
104	uint8_t read_reg_select;
105	uint8_t poll;
106	uint8_t special_mask;
107	uint8_t init_state;
108	uint8_t auto_eoi;
109	uint8_t rotate_on_auto_eoi;
110	uint8_t special_fully_nested_mode;
111	uint8_t init4; /* true if 4 byte init */
112	uint8_t elcr; /* PIIX edge/trigger selection*/
113	uint8_t elcr_mask;
114	/** Pointer to the device instance, HCPtr. */
115	R3R0PTRTYPE(PPDMDEVINS) pDevInsHC;
116	/** Pointer to the device instance, GCPtr. */
117	GCPTRTYPE(PPDMDEVINS) pDevInsGC;
118	#if HC_ARCH_BITS == 64 && GC_ARCH_BITS != 64
119	RTGCPTR Alignment0;
120	#endif
121	} PicState;
122
123	/**
124	* A PIC device instance data.
125	*/
126	typedef struct DEVPIC
127	{
128	/** The two interrupt controllers. */
129	PicState aPics[2];
130	/** Pointer to the PIC R3 helpers. */
131	PCPDMPICHLPR3 pPicHlpR3;
132	/** Pointer to the PIC R0 helpers. */
133	PCPDMPICHLPR0 pPicHlpR0;
134	/** Pointer to the PIC GC helpers. */
135	PCPDMPICHLPGC pPicHlpGC;
136	/** Pointer to the device instance - GC Ptr. */
137	GCPTRTYPE(PPDMDEVINS) pDevInsGC;
138	/** Pointer to the device instance - GC Ptr. */
139	R3R0PTRTYPE(PPDMDEVINS) pDevInsHC;
140	#if HC_ARCH_BITS == 32
141	uint32_t Alignmnet0;
142	#endif
143	#ifdef VBOX_WITH_STATISTICS
144	STAMCOUNTER StatSetIrqGC;
145	STAMCOUNTER StatSetIrqHC;
146	STAMCOUNTER StatClearedActiveIRQ2;
147	STAMCOUNTER StatClearedActiveMasterIRQ;
148	STAMCOUNTER StatClearedActiveSlaveIRQ;
149	#endif
150	} DEVPIC, *PDEVPIC;
151
152
153	#ifndef VBOX_DEVICE_STRUCT_TESTCASE
154	#ifdef LOG_ENABLED
155	static inline void DumpPICState(PicState s, const char szFn)
156	{
157	PDEVPIC pData = PDMINS2DATA(CTXSUFF(s->pDevIns), PDEVPIC);
158
159	Log2(("%s: pic%d: elcr=%x last_irr=%x irr=%x imr=%x isr=%x irq_base=%x\n",
160	szFn, (&pData->aPics[0] == s) ? 0 : 1,
161	s->elcr, s->last_irr, s->irr, s->imr, s->isr, s->irq_base));
162	}
163	#else
164	# define DumpPICState(pData, szFn) do { } while (0)
165	#endif
166
167	/* set irq level. If an edge is detected, then the IRR is set to 1 */
168	static inline void pic_set_irq1(PicState *s, int irq, int level)
169	{
170	int mask;
171	Log(("pic_set_irq1: irq=%d level=%d\n", irq, level));
172	mask = 1 << irq;
173	if (s->elcr & mask) {
174	/* level triggered */
175	if (level) {
176	Log2(("pic_set_irq1(ls) irr=%d irrnew=%d\n", s->irr, s->irr \| mask));
177	s->irr \|= mask;
178	s->last_irr \|= mask;
179	} else {
180	Log2(("pic_set_irq1(lc) irr=%d irrnew=%d\n", s->irr, s->irr & ~mask));
181	s->irr &= ~mask;
182	s->last_irr &= ~mask;
183	}
184	} else {
185	/* edge triggered */
186	if (level) {
187	if ((s->last_irr & mask) == 0)
188	{
189	Log2(("pic_set_irq1 irr=%x last_irr=%x\n", s->irr \| mask, s->last_irr));
190	s->irr \|= mask;
191	}
192	s->last_irr \|= mask;
193	} else {
194	s->last_irr &= ~mask;
195	}
196	}
197	DumpPICState(s, "pic_set_irq1");
198	}
199
200	/* return the highest priority found in mask (highest = smallest
201	number). Return 8 if no irq */
202	static inline int get_priority(PicState *s, int mask)
203	{
204	int priority;
205	if (mask == 0)
206	return 8;
207	priority = 0;
208	while ((mask & (1 << ((priority + s->priority_add) & 7))) == 0)
209	priority++;
210	return priority;
211	}
212
213	/* return the pic wanted interrupt. return -1 if none */
214	static int pic_get_irq(PicState *s)
215	{
216	PicState *pics = &(PDMINS2DATA(CTXSUFF(s->pDevIns), PDEVPIC))->aPics[0];
217	int mask, cur_priority, priority;
218	Log(("pic_get_irq%d: mask=%x\n", (s == pics) ? 0 : 1, s->irr & ~s->imr));
219	DumpPICState(s, "pic_get_irq");
220
221	mask = s->irr & ~s->imr;
222	priority = get_priority(s, mask);
223	Log(("pic_get_irq: priority=%x\n", priority));
224	if (priority == 8)
225	return -1;
226	/* compute current priority. If special fully nested mode on the
227	master, the IRQ coming from the slave is not taken into account
228	for the priority computation. */
229	mask = s->isr;
230	if (s->special_fully_nested_mode && s == &pics[0])
231	mask &= ~(1 << 2);
232	cur_priority = get_priority(s, mask);
233	Log(("pic_get_irq%d: cur_priority=%x pending=%d\n", (s == pics) ? 0 : 1, cur_priority, (priority == 8) ? -1 : (priority + s->priority_add) & 7));
234	if (priority < cur_priority) {
235	/* higher priority found: an irq should be generated */
236	return (priority + s->priority_add) & 7;
237	} else {
238	return -1;
239	}
240	}
241
242	/* raise irq to CPU if necessary. must be called every time the active
243	irq may change */
244	static int pic_update_irq(PDEVPIC pData)
245	{
246	PicState *pics = &pData->aPics[0];
247	int irq2, irq;
248
249	/* first look at slave pic */
250	irq2 = pic_get_irq(&pics[1]);
251	Log(("pic_update_irq irq2=%d\n", irq2));
252	if (irq2 >= 0) {
253	/* if irq request by slave pic, signal master PIC */
254	pic_set_irq1(&pics[0], 2, 1);
255	pic_set_irq1(&pics[0], 2, 0);
256	}
257	/* look at requested irq */
258	irq = pic_get_irq(&pics[0]);
259	if (irq >= 0)
260	{
261	/* If irq 2 is pending on the master pic, then there must be one pending on the slave pic too! Otherwise we'll get
262	* spurious slave interrupts in picGetInterrupt.
263	*/
264	if (irq != 2 \|\| irq2 != -1)
265	{
266	#if defined(DEBUG_PIC)
267	int i;
268	for(i = 0; i < 2; i++) {
269	Log(("pic%d: imr=%x irr=%x padd=%d\n",
270	i, pics[i].imr, pics[i].irr,
271	pics[i].priority_add));
272	}
273	Log(("pic: cpu_interrupt\n"));
274	#endif
275	pData->CTXALLSUFF(pPicHlp)->pfnSetInterruptFF(pData->CTXSUFF(pDevIns));
276	}
277	else
278	{
279	STAM_COUNTER_INC(&pData->StatClearedActiveIRQ2);
280	Log(("pic_update_irq: irq 2 is active, but no interrupt is pending on the slave pic!!\n"));
281	/* Clear it here, so lower priority interrupts can still be dispatched. */
282
283	/* if this was the only pending irq, then we must clear the interrupt ff flag */
284	pData->CTXALLSUFF(pPicHlp)->pfnClearInterruptFF(pData->CTXSUFF(pDevIns));
285
286	/** @note Is this correct? */
287	pics[0].irr &= ~(1 << 2);
288
289	/* Call ourselves again just in case other interrupts are pending */
290	return pic_update_irq(pData);
291	}
292	}
293	return VINF_SUCCESS;
294	}
295
296	/** @note if an interrupt line state changes from unmasked to masked, then it must be deactivated when currently pending! */
297	static void pic_update_imr(PDEVPIC pData, PicState *s, uint8_t val)
298	{
299	int irq, intno;
300	PicState *pActivePIC;
301
302	/* Query the current pending irq, if any. */
303	pActivePIC = &pData->aPics[0];
304	intno = irq = pic_get_irq(pActivePIC);
305	if (irq == 2)
306	{
307	pActivePIC = &pData->aPics[1];
308	irq = pic_get_irq(pActivePIC);
309	intno = irq + 8;
310	}
311
312	/* Update IMR */
313	s->imr = val;
314
315	/* If an interrupt is pending and now masked, then clear the FF flag. */
316	if ( irq >= 0
317	&& ((1 << irq) & ~pActivePIC->imr) == 0)
318	{
319	Log(("pic_update_imr: pic0: elcr=%x last_irr=%x irr=%x imr=%x isr=%x irq_base=%x\n",
320	pData->aPics[0].elcr, pData->aPics[0].last_irr, pData->aPics[0].irr, pData->aPics[0].imr, pData->aPics[0].isr, pData->aPics[0].irq_base));
321	Log(("pic_update_imr: pic1: elcr=%x last_irr=%x irr=%x imr=%x isr=%x irq_base=%x\n",
322	pData->aPics[1].elcr, pData->aPics[1].last_irr, pData->aPics[1].irr, pData->aPics[1].imr, pData->aPics[1].isr, pData->aPics[1].irq_base));
323
324	/* Clear pending IRQ 2 on master controller in case of slave interrupt. */
325	/** @todo Is this correct? */
326	if (intno > 7)
327	{
328	pData->aPics[0].irr &= ~(1 << 2);
329	STAM_COUNTER_INC(&pData->StatClearedActiveSlaveIRQ);
330	}
331	else
332	STAM_COUNTER_INC(&pData->StatClearedActiveMasterIRQ);
333
334	Log(("pic_update_imr: clear pending interrupt %d\n", intno));
335	pData->CTXALLSUFF(pPicHlp)->pfnClearInterruptFF(pData->CTXSUFF(pDevIns));
336	}
337	}
338
339
340	/**
341	* Set the an IRQ.
342	*
343	* @param pDevIns Device instance of the PICs.
344	* @param iIrq IRQ number to set.
345	* @param iLevel IRQ level.
346	*/
347	PDMBOTHCBDECL(void) picSetIrq(PPDMDEVINS pDevIns, int iIrq, int iLevel)
348	{
349	PDEVPIC pData = PDMINS2DATA(pDevIns, PDEVPIC);
350	Assert(pData->CTXSUFF(pDevIns) == pDevIns);
351	Assert(pData->aPics[0].CTXSUFF(pDevIns) == pDevIns);
352	Assert(pData->aPics[1].CTXSUFF(pDevIns) == pDevIns);
353	AssertMsg(iIrq < 16, ("iIrq=%d\n", iIrq));
354
355	Log(("picSetIrq %d %d\n", iIrq, iLevel));
356	DumpPICState(&pData->aPics[0], "picSetIrq");
357	DumpPICState(&pData->aPics[1], "picSetIrq");
358	STAM_COUNTER_INC(&pData->CTXSUFF(StatSetIrq));
359	pic_set_irq1(&pData->aPics[iIrq >> 3], iIrq & 7, iLevel & PDM_IRQ_LEVEL_HIGH);
360	pic_update_irq(pData);
361	if ((iLevel & PDM_IRQ_LEVEL_FLIP_FLOP) == PDM_IRQ_LEVEL_FLIP_FLOP)
362	{
363	pic_set_irq1(&pData->aPics[iIrq >> 3], iIrq & 7, 0);
364	pic_update_irq(pData);
365	}
366	}
367
368
369	/* acknowledge interrupt 'irq' */
370	static inline void pic_intack(PicState *s, int irq)
371	{
372	if (s->auto_eoi) {
373	if (s->rotate_on_auto_eoi)
374	s->priority_add = (irq + 1) & 7;
375	} else {
376	s->isr \|= (1 << irq);
377	}
378	/* We don't clear a level sensitive interrupt here */
379	if (!(s->elcr & (1 << irq)))
380	{
381	Log2(("pic_intack: irr=%x irrnew=%x\n", s->irr, s->irr & ~(1 << irq)));
382	s->irr &= ~(1 << irq);
383	}
384	}
385
386
387	/**
388	* Get a pending interrupt.
389	*
390	* @returns Pending interrupt number.
391	* @param pDevIns Device instance of the PICs.
392	*/
393	PDMBOTHCBDECL(int) picGetInterrupt(PPDMDEVINS pDevIns)
394	{
395	PDEVPIC pData = PDMINS2DATA(pDevIns, PDEVPIC);
396	int irq;
397	int irq2;
398	int intno;
399
400	/* read the irq from the PIC */
401	DumpPICState(&pData->aPics[0], "picGetInterrupt");
402	DumpPICState(&pData->aPics[1], "picGetInterrupt");
403
404	irq = pic_get_irq(&pData->aPics[0]);
405	if (irq >= 0)
406	{
407	pic_intack(&pData->aPics[0], irq);
408	if (irq == 2)
409	{
410	irq2 = pic_get_irq(&pData->aPics[1]);
411	if (irq2 >= 0) {
412	pic_intack(&pData->aPics[1], irq2);
413	}
414	else
415	{
416	/* spurious IRQ on slave controller (impossible) */
417	AssertMsgFailed(("picGetInterrupt: spurious IRQ on slave controller\n"));
418	irq2 = 7;
419	}
420	intno = pData->aPics[1].irq_base + irq2;
421	Log2(("picGetInterrupt1: %x base=%x irq=%x\n", intno, pData->aPics[1].irq_base, irq2));
422	irq = irq2 + 8;
423	}
424	else {
425	intno = pData->aPics[0].irq_base + irq;
426	Log2(("picGetInterrupt0: %x base=%x irq=%x\n", intno, pData->aPics[0].irq_base, irq));
427	}
428	}
429	else
430	{
431	/* spurious IRQ on host controller (impossible) */
432	AssertMsgFailed(("picGetInterrupt: spurious IRQ on master controller\n"));
433	irq = 7;
434	intno = pData->aPics[0].irq_base + irq;
435	}
436	pic_update_irq(pData);
437
438	Log(("picGetInterrupt: pending 0:%d 1:%d\n", pic_get_irq(&pData->aPics[0]), pic_get_irq(&pData->aPics[1])));
439
440	return intno;
441	}
442
443	static void pic_reset(PicState *s)
444	{
445	R3R0PTRTYPE(PPDMDEVINS) pDevInsHC = s->pDevInsHC;
446	GCPTRTYPE(PPDMDEVINS) pDevInsGC = s->pDevInsGC;
447	int tmp, tmp2;
448
449	tmp = s->elcr_mask;
450	tmp2 = s->elcr;
451	memset(s, 0, sizeof(PicState));
452	s->elcr_mask = tmp;
453	s->elcr = tmp2;
454	s->pDevInsHC = pDevInsHC;
455	s->pDevInsGC = pDevInsGC;
456	}
457
458
459	static int pic_ioport_write(void *opaque, uint32_t addr, uint32_t val)
460	{
461	PicState s = (PicState)opaque;
462	PDEVPIC pData = PDMINS2DATA(CTXSUFF(s->pDevIns), PDEVPIC);
463	int rc = VINF_SUCCESS;
464	int priority, cmd, irq;
465
466	Log(("pic_write: addr=0x%02x val=0x%02x\n", addr, val));
467	addr &= 1;
468	if (addr == 0) {
469	if (val & 0x10) {
470	/* init */
471	pic_reset(s);
472	/* deassert a pending interrupt */
473	pData->CTXALLSUFF(pPicHlp)->pfnClearInterruptFF(pData->CTXSUFF(pDevIns));
474
475	s->init_state = 1;
476	s->init4 = val & 1;
477	if (val & 0x02)
478	AssertReleaseMsgFailed(("single mode not supported"));
479	if (val & 0x08)
480	AssertReleaseMsgFailed(("level sensitive irq not supported"));
481	} else if (val & 0x08) {
482	if (val & 0x04)
483	s->poll = 1;
484	if (val & 0x02)
485	s->read_reg_select = val & 1;
486	if (val & 0x40)
487	s->special_mask = (val >> 5) & 1;
488	} else {
489	cmd = val >> 5;
490	switch(cmd) {
491	case 0:
492	case 4:
493	s->rotate_on_auto_eoi = cmd >> 2;
494	break;
495	case 1: /* end of interrupt */
496	case 5:
497	{
498	priority = get_priority(s, s->isr);
499	if (priority != 8) {
500	irq = (priority + s->priority_add) & 7;
501	Log(("pic_write: EOI prio=%d irq=%d\n", priority, irq));
502	s->isr &= ~(1 << irq);
503	if (cmd == 5)
504	s->priority_add = (irq + 1) & 7;
505	rc = pic_update_irq(pData);
506	Assert(rc == VINF_SUCCESS);
507	DumpPICState(s, "eoi");
508	}
509	break;
510	}
511	case 3:
512	{
513	irq = val & 7;
514	Log(("pic_write: EOI2 for irq %d\n", irq));
515	s->isr &= ~(1 << irq);
516	rc = pic_update_irq(pData);
517	Assert(rc == VINF_SUCCESS);
518	DumpPICState(s, "eoi2");
519	break;
520	}
521	case 6:
522	{
523	s->priority_add = (val + 1) & 7;
524	rc = pic_update_irq(pData);
525	Assert(rc == VINF_SUCCESS);
526	break;
527	}
528	case 7:
529	{
530	irq = val & 7;
531	Log(("pic_write: EOI3 for irq %d\n", irq));
532	s->isr &= ~(1 << irq);
533	s->priority_add = (irq + 1) & 7;
534	rc = pic_update_irq(pData);
535	Assert(rc == VINF_SUCCESS);
536	DumpPICState(s, "eoi3");
537	break;
538	}
539	default:
540	/* no operation */
541	break;
542	}
543	}
544	} else {
545	switch(s->init_state) {
546	case 0:
547	{
548	/* normal mode */
549	pic_update_imr(pData, s, val);
550
551	rc = pic_update_irq(pData);
552	Assert(rc == VINF_SUCCESS);
553	break;
554	}
555	case 1:
556	s->irq_base = val & 0xf8;
557	s->init_state = 2;
558	Log(("pic_write: set irq base to %x\n", s->irq_base));
559	break;
560	case 2:
561	if (s->init4) {
562	s->init_state = 3;
563	} else {
564	s->init_state = 0;
565	}
566	break;
567	case 3:
568	s->special_fully_nested_mode = (val >> 4) & 1;
569	s->auto_eoi = (val >> 1) & 1;
570	s->init_state = 0;
571	Log(("pic_write: special_fully_nested_mode=%d auto_eoi=%d\n", s->special_fully_nested_mode, s->auto_eoi));
572	break;
573	}
574	}
575	return rc;
576	}
577
578
579	static uint32_t pic_poll_read (PicState *s, uint32_t addr1)
580	{
581	PDEVPIC pData = PDMINS2DATA(CTXSUFF(s->pDevIns), PDEVPIC);
582	PicState *pics = &pData->aPics[0];
583	int ret;
584
585	ret = pic_get_irq(s);
586	if (ret >= 0) {
587	if (addr1 >> 7) {
588	Log2(("pic_poll_read: clear slave irq (isr)\n"));
589	pics[0].isr &= ~(1 << 2);
590	pics[0].irr &= ~(1 << 2);
591	}
592	Log2(("pic_poll_read: clear irq %d (isr)\n", ret));
593	s->irr &= ~(1 << ret);
594	s->isr &= ~(1 << ret);
595	if (addr1 >> 7 \|\| ret != 2)
596	pic_update_irq(pData);
597	} else {
598	ret = 0x07;
599	pic_update_irq(pData);
600	}
601
602	return ret;
603	}
604
605
606	static uint32_t pic_ioport_read(void opaque, uint32_t addr1, int pRC)
607	{
608	PicState s = (PicState)opaque;
609	unsigned int addr;
610	int ret;
611
612	*pRC = VINF_SUCCESS;
613
614	addr = addr1;
615	addr &= 1;
616	if (s->poll) {
617	ret = pic_poll_read(s, addr1);
618	s->poll = 0;
619	} else {
620	if (addr == 0) {
621	if (s->read_reg_select)
622	ret = s->isr;
623	else
624	ret = s->irr;
625	} else {
626	ret = s->imr;
627	}
628	}
629	Log(("pic_read: addr=0x%02x val=0x%02x\n", addr1, ret));
630	return ret;
631	}
632
633
634
635	#ifdef IN_RING3
636
637	static void pic_save(QEMUFile f, void opaque)
638	{
639	PicState s = (PicState)opaque;
640
641	qemu_put_8s(f, &s->last_irr);
642	qemu_put_8s(f, &s->irr);
643	qemu_put_8s(f, &s->imr);
644	qemu_put_8s(f, &s->isr);
645	qemu_put_8s(f, &s->priority_add);
646	qemu_put_8s(f, &s->irq_base);
647	qemu_put_8s(f, &s->read_reg_select);
648	qemu_put_8s(f, &s->poll);
649	qemu_put_8s(f, &s->special_mask);
650	qemu_put_8s(f, &s->init_state);
651	qemu_put_8s(f, &s->auto_eoi);
652	qemu_put_8s(f, &s->rotate_on_auto_eoi);
653	qemu_put_8s(f, &s->special_fully_nested_mode);
654	qemu_put_8s(f, &s->init4);
655	qemu_put_8s(f, &s->elcr);
656	}
657
658	static int pic_load(QEMUFile f, void opaque, int version_id)
659	{
660	PicState s = (PicState)opaque;
661
662	if (version_id != 1)
663	return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
664
665	qemu_get_8s(f, &s->last_irr);
666	qemu_get_8s(f, &s->irr);
667	qemu_get_8s(f, &s->imr);
668	qemu_get_8s(f, &s->isr);
669	qemu_get_8s(f, &s->priority_add);
670	qemu_get_8s(f, &s->irq_base);
671	qemu_get_8s(f, &s->read_reg_select);
672	qemu_get_8s(f, &s->poll);
673	qemu_get_8s(f, &s->special_mask);
674	qemu_get_8s(f, &s->init_state);
675	qemu_get_8s(f, &s->auto_eoi);
676	qemu_get_8s(f, &s->rotate_on_auto_eoi);
677	qemu_get_8s(f, &s->special_fully_nested_mode);
678	qemu_get_8s(f, &s->init4);
679	qemu_get_8s(f, &s->elcr);
680	return 0;
681	}
682	#endif /* IN_RING3 */
683
684
685	/* -=-=-=-=-=- wrappers -=-=-=-=-=- */
686
687	/**
688	* Port I/O Handler for IN operations.
689	*
690	* @returns VBox status code.
691	*
692	* @param pDevIns The device instance.
693	* @param pvUser User argument - pointer to the PIC in question.
694	* @param uPort Port number used for the IN operation.
695	* @param pu32 Where to store the result.
696	* @param cb Number of bytes read.
697	*/
698	PDMBOTHCBDECL(int) picIOPortRead(PPDMDEVINS pDevIns, void pvUser, RTIOPORT Port, uint32_t pu32, unsigned cb)
699	{
700	PDEVPIC pData = PDMINS2DATA(pDevIns, PDEVPIC);
701	uint32_t iPic = (uint32_t)(uintptr_t)pvUser;
702
703	Assert(iPic == 0 \|\| iPic == 1);
704	if (cb == 1)
705	{
706	int rc;
707	PIC_LOCK(pData, VINF_IOM_HC_IOPORT_READ);
708	*pu32 = pic_ioport_read(&pData->aPics[iPic], Port, &rc);
709	PIC_UNLOCK(pData);
710	return rc;
711	}
712	return VERR_IOM_IOPORT_UNUSED;
713	}
714
715	/**
716	* Port I/O Handler for OUT operations.
717	*
718	* @returns VBox status code.
719	*
720	* @param pDevIns The device instance.
721	* @param pvUser User argument - pointer to the PIC in question.
722	* @param uPort Port number used for the IN operation.
723	* @param u32 The value to output.
724	* @param cb The value size in bytes.
725	*/
726	PDMBOTHCBDECL(int) picIOPortWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb)
727	{
728	PDEVPIC pData = PDMINS2DATA(pDevIns, PDEVPIC);
729	uint32_t iPic = (uint32_t)(uintptr_t)pvUser;
730
731	Assert(iPic == 0 \|\| iPic == 1);
732
733	if (cb == 1)
734	{
735	int rc;
736	PIC_LOCK(pData, VINF_IOM_HC_IOPORT_WRITE);
737	rc = pic_ioport_write(&pData->aPics[iPic], Port, u32);
738	PIC_UNLOCK(pData);
739	return rc;
740	}
741	return VINF_SUCCESS;
742	}
743
744
745	/**
746	* Port I/O Handler for IN operations.
747	*
748	* @returns VBox status code.
749	*
750	* @param pDevIns The device instance.
751	* @param pvUser User argument - pointer to the PIC in question.
752	* @param uPort Port number used for the IN operation.
753	* @param pu32 Where to store the result.
754	* @param cb Number of bytes read.
755	*/
756	PDMBOTHCBDECL(int) picIOPortElcrRead(PPDMDEVINS pDevIns, void pvUser, RTIOPORT Port, uint32_t pu32, unsigned cb)
757	{
758	if (cb == 1)
759	{
760	PicState s = (PicState)pvUser;
761	PIC_LOCK(PDMINS2DATA(pDevIns, PDEVPIC), VINF_IOM_HC_IOPORT_READ);
762	*pu32 = s->elcr;
763	PIC_UNLOCK(PDMINS2DATA(pDevIns, PDEVPIC));
764	return VINF_SUCCESS;
765	}
766	return VERR_IOM_IOPORT_UNUSED;
767	}
768
769	/**
770	* Port I/O Handler for OUT operations.
771	*
772	* @returns VBox status code.
773	*
774	* @param pDevIns The device instance.
775	* @param pvUser User argument - pointer to the PIC in question.
776	* @param uPort Port number used for the IN operation.
777	* @param u32 The value to output.
778	* @param cb The value size in bytes.
779	*/
780	PDMBOTHCBDECL(int) picIOPortElcrWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb)
781	{
782	if (cb == 1)
783	{
784	PicState s = (PicState)pvUser;
785	PIC_LOCK(PDMINS2DATA(pDevIns, PDEVPIC), VINF_IOM_HC_IOPORT_WRITE);
786	s->elcr = u32 & s->elcr_mask;
787	PIC_UNLOCK(PDMINS2DATA(pDevIns, PDEVPIC));
788	}
789	return VINF_SUCCESS;
790	}
791
792
793	#ifdef IN_RING3
794
795	#ifdef DEBUG
796	/**
797	* PIC status info callback.
798	*
799	* @param pDevIns The device instance.
800	* @param pHlp The output helpers.
801	* @param pszArgs The arguments.
802	*/
803	static DECLCALLBACK(void) picInfo(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
804	{
805	PDEVPIC pData = PDMINS2DATA(pDevIns, PDEVPIC);
806
807	/*
808	* Show info.
809	*/
810	for (int i=0;i<2;i++)
811	{
812	pHlp->pfnPrintf(pHlp, "PIC%d:\n", i);
813	pHlp->pfnPrintf(pHlp, " last_irr = %02x\n", pData->aPics[i].last_irr);
814	pHlp->pfnPrintf(pHlp, " irr = %02x\n", pData->aPics[i].irr);
815	pHlp->pfnPrintf(pHlp, " imr = %02x\n", pData->aPics[i].imr);
816	pHlp->pfnPrintf(pHlp, " isr = %02x\n", pData->aPics[i].isr);
817	pHlp->pfnPrintf(pHlp, " priority_add = %02x\n", pData->aPics[i].priority_add);
818	pHlp->pfnPrintf(pHlp, " irq_base = %02x\n", pData->aPics[i].irq_base);
819	pHlp->pfnPrintf(pHlp, " read_reg_select = %02x\n", pData->aPics[i].read_reg_select);
820	pHlp->pfnPrintf(pHlp, " poll = %02x\n", pData->aPics[i].poll);
821	pHlp->pfnPrintf(pHlp, " special_mask = %02x\n", pData->aPics[i].special_mask);
822	pHlp->pfnPrintf(pHlp, " init_state = %02x\n", pData->aPics[i].init_state);
823	pHlp->pfnPrintf(pHlp, " auto_eoi = %02x\n", pData->aPics[i].auto_eoi);
824	pHlp->pfnPrintf(pHlp, " rotate_on_auto_eoi = %02x\n", pData->aPics[i].rotate_on_auto_eoi);
825	pHlp->pfnPrintf(pHlp, " special_fully_nested_mode = %02x\n", pData->aPics[i].special_fully_nested_mode);
826	pHlp->pfnPrintf(pHlp, " init4 = %02x\n", pData->aPics[i].init4);
827	pHlp->pfnPrintf(pHlp, " elcr = %02x\n", pData->aPics[i].elcr);
828	pHlp->pfnPrintf(pHlp, " elcr_mask = %02x\n", pData->aPics[i].elcr_mask);
829	}
830	}
831	#endif /* DEBUG */
832
833	/**
834	* Saves a state of the programmable interrupt controller device.
835	*
836	* @returns VBox status code.
837	* @param pDevIns The device instance.
838	* @param pSSMHandle The handle to save the state to.
839	*/
840	static DECLCALLBACK(int) picSaveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSMHandle)
841	{
842	PDEVPIC pData = PDMINS2DATA(pDevIns, PDEVPIC);
843	pic_save(pSSMHandle, &pData->aPics[0]);
844	pic_save(pSSMHandle, &pData->aPics[1]);
845	return VINF_SUCCESS;
846	}
847
848
849	/**
850	* Loads a saved programmable interrupt controller device state.
851	*
852	* @returns VBox status code.
853	* @param pDevIns The device instance.
854	* @param pSSMHandle The handle to the saved state.
855	* @param u32Version The data unit version number.
856	*/
857	static DECLCALLBACK(int) picLoadExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSMHandle, uint32_t u32Version)
858	{
859	PDEVPIC pData = PDMINS2DATA(pDevIns, PDEVPIC);
860	int rc = pic_load(pSSMHandle, &pData->aPics[0], u32Version);
861	if (VBOX_SUCCESS(rc))
862	rc = pic_load(pSSMHandle, &pData->aPics[1], u32Version);
863	return rc;
864	}
865
866
867	/* -=-=-=-=-=- real code -=-=-=-=-=- */
868
869	/**
870	* Reset notification.
871	*
872	* @returns VBox status.
873	* @param pDevIns The device instance data.
874	*/
875	static DECLCALLBACK(void) picReset(PPDMDEVINS pDevIns)
876	{
877	PDEVPIC pData = PDMINS2DATA(pDevIns, PDEVPIC);
878	unsigned i;
879	LogFlow(("picReset:\n"));
880	#ifdef VBOX_WITH_PDM_LOCK
881	pData->pPicHlpR3->pfnLock(pDevIns, VERR_INTERNAL_ERROR);
882	#endif
883
884	for (i = 0; i < ELEMENTS(pData->aPics); i++)
885	pic_reset(&pData->aPics[i]);
886
887	PIC_UNLOCK(pData);
888	}
889
890
891	/**
892	* @copydoc FNPDMDEVRELOCATE
893	*/
894	static DECLCALLBACK(void) picRelocate(PPDMDEVINS pDevIns, RTGCINTPTR offDelta)
895	{
896	PDEVPIC pData = PDMINS2DATA(pDevIns, PDEVPIC);
897	unsigned i;
898
899	pData->pDevInsGC = PDMDEVINS_2_GCPTR(pDevIns);
900	pData->pPicHlpGC = pData->pPicHlpR3->pfnGetGCHelpers(pDevIns);
901	for (i = 0; i < ELEMENTS(pData->aPics); i++)
902	pData->aPics[i].pDevInsGC = PDMDEVINS_2_GCPTR(pDevIns);
903	}
904
905
906	/**
907	* @copydoc FNPDMDEVCONSTRUCT
908	*/
909	static DECLCALLBACK(int) picConstruct(PPDMDEVINS pDevIns, int iInstance, PCFGMNODE pCfgHandle)
910	{
911	PDEVPIC pData = PDMINS2DATA(pDevIns, PDEVPIC);
912	PDMPICREG PicReg;
913	int rc;
914	bool fGCEnabled;
915	bool fR0Enabled;
916	Assert(iInstance == 0);
917
918	/*
919	* Validate and read configuration.
920	*/
921	if (!CFGMR3AreValuesValid(pCfgHandle, "GCEnabled\0R0Enabled\0"))
922	return VERR_PDM_DEVINS_UNKNOWN_CFG_VALUES;
923
924	rc = CFGMR3QueryBool(pCfgHandle, "GCEnabled", &fGCEnabled);
925	if (rc == VERR_CFGM_VALUE_NOT_FOUND)
926	fGCEnabled = true;
927	else if (VBOX_FAILURE(rc))
928	return PDMDEV_SET_ERROR(pDevIns, rc,
929	N_("Configuration error: failed to read GCEnabled as boolean"));
930
931	rc = CFGMR3QueryBool(pCfgHandle, "R0Enabled", &fR0Enabled);
932	if (rc == VERR_CFGM_VALUE_NOT_FOUND)
933	fR0Enabled = true;
934	else if (VBOX_FAILURE(rc))
935	return PDMDEV_SET_ERROR(pDevIns, rc,
936	N_("Configuration error: failed to read R0Enabled as boolean"));
937
938	Log(("i8259: fGCEnabled=%d fR0Enabled=%d\n", fGCEnabled, fR0Enabled));
939
940	/*
941	* Init the data.
942	*/
943	Assert(ELEMENTS(pData->aPics) == 2);
944	pData->pDevInsHC = pDevIns;
945	pData->pDevInsGC = PDMDEVINS_2_GCPTR(pDevIns);
946	pData->aPics[0].elcr_mask = 0xf8;
947	pData->aPics[1].elcr_mask = 0xde;
948	pData->aPics[0].pDevInsHC = pDevIns;
949	pData->aPics[1].pDevInsHC = pDevIns;
950	pData->aPics[0].pDevInsGC = PDMDEVINS_2_GCPTR(pDevIns);
951	pData->aPics[1].pDevInsGC = PDMDEVINS_2_GCPTR(pDevIns);
952
953	/*
954	* Register PIC, I/O ports and save state.
955	*/
956	PicReg.u32Version = PDM_PICREG_VERSION;
957	PicReg.pfnSetIrqHC = picSetIrq;
958	PicReg.pfnGetInterruptHC = picGetInterrupt;
959	if (fGCEnabled)
960	{
961	PicReg.pszSetIrqGC = "picSetIrq";
962	PicReg.pszGetInterruptGC = "picGetInterrupt";
963	}
964	else
965	{
966	PicReg.pszSetIrqGC = NULL;
967	PicReg.pszGetInterruptGC = NULL;
968	}
969
970	if (fR0Enabled)
971	{
972	PicReg.pszSetIrqR0 = "picSetIrq";
973	PicReg.pszGetInterruptR0 = "picGetInterrupt";
974	}
975	else
976	{
977	PicReg.pszSetIrqR0 = NULL;
978	PicReg.pszGetInterruptR0 = NULL;
979	}
980
981	Assert(pDevIns->pDevHlp->pfnPICRegister);
982	rc = pDevIns->pDevHlp->pfnPICRegister(pDevIns, &PicReg, &pData->pPicHlpR3);
983	if (VBOX_FAILURE(rc))
984	{
985	AssertMsgFailed(("PICRegister -> %Vrc\n", rc));
986	return rc;
987	}
988	if (fGCEnabled)
989	pData->pPicHlpGC = pData->pPicHlpR3->pfnGetGCHelpers(pDevIns);
990	rc = PDMDevHlpIOPortRegister(pDevIns, 0x20, 2, (void *)0, picIOPortWrite, picIOPortRead, NULL, NULL, "i8259 PIC #0");
991	if (VBOX_FAILURE(rc))
992	return rc;
993	rc = PDMDevHlpIOPortRegister(pDevIns, 0xa0, 2, (void *)1, picIOPortWrite, picIOPortRead, NULL, NULL, "i8259 PIC #1");
994	if (VBOX_FAILURE(rc))
995	return rc;
996	if (fGCEnabled)
997	{
998	rc = PDMDevHlpIOPortRegisterGC(pDevIns, 0x20, 2, 0, "picIOPortWrite", "picIOPortRead", NULL, NULL, "i8259 PIC #0");
999	if (VBOX_FAILURE(rc))
1000	return rc;
1001	rc = PDMDevHlpIOPortRegisterGC(pDevIns, 0xa0, 2, 1, "picIOPortWrite", "picIOPortRead", NULL, NULL, "i8259 PIC #1");
1002	if (VBOX_FAILURE(rc))
1003	return rc;
1004	}
1005	if (fR0Enabled)
1006	{
1007	pData->pPicHlpR0 = pData->pPicHlpR3->pfnGetR0Helpers(pDevIns);
1008
1009	rc = PDMDevHlpIOPortRegisterR0(pDevIns, 0x20, 2, 0, "picIOPortWrite", "picIOPortRead", NULL, NULL, "i8259 PIC #0");
1010	if (VBOX_FAILURE(rc))
1011	return rc;
1012	rc = PDMDevHlpIOPortRegisterR0(pDevIns, 0xa0, 2, 1, "picIOPortWrite", "picIOPortRead", NULL, NULL, "i8259 PIC #1");
1013	if (VBOX_FAILURE(rc))
1014	return rc;
1015	}
1016
1017	rc = PDMDevHlpIOPortRegister(pDevIns, 0x4d0, 1, &pData->aPics[0],
1018	picIOPortElcrWrite, picIOPortElcrRead, NULL, NULL, "i8259 PIC #0 - elcr");
1019	if (VBOX_FAILURE(rc))
1020	return rc;
1021	rc = PDMDevHlpIOPortRegister(pDevIns, 0x4d1, 1, &pData->aPics[1],
1022	picIOPortElcrWrite, picIOPortElcrRead, NULL, NULL, "i8259 PIC #1 - elcr");
1023	if (VBOX_FAILURE(rc))
1024	return rc;
1025	if (fGCEnabled)
1026	{
1027	RTGCPTR pDataGC = PDMINS2DATA_GCPTR(pDevIns);
1028	rc = PDMDevHlpIOPortRegisterGC(pDevIns, 0x4d0, 1, pDataGC + RT_OFFSETOF(DEVPIC, aPics[0]),
1029	"picIOPortElcrWrite", "picIOPortElcrRead", NULL, NULL, "i8259 PIC #0 - elcr");
1030	if (VBOX_FAILURE(rc))
1031	return rc;
1032	rc = PDMDevHlpIOPortRegisterGC(pDevIns, 0x4d1, 1, pDataGC + RT_OFFSETOF(DEVPIC, aPics[1]),
1033	"picIOPortElcrWrite", "picIOPortElcrRead", NULL, NULL, "i8259 PIC #1 - elcr");
1034	if (VBOX_FAILURE(rc))
1035	return rc;
1036	}
1037	if (fR0Enabled)
1038	{
1039	RTR0PTR pDataR0 = PDMINS2DATA_R0PTR(pDevIns);
1040	rc = PDMDevHlpIOPortRegisterR0(pDevIns, 0x4d0, 1, pDataR0 + RT_OFFSETOF(DEVPIC, aPics[0]),
1041	"picIOPortElcrWrite", "picIOPortElcrRead", NULL, NULL, "i8259 PIC #0 - elcr");
1042	if (VBOX_FAILURE(rc))
1043	return rc;
1044	rc = PDMDevHlpIOPortRegisterR0(pDevIns, 0x4d1, 1, pDataR0 + RT_OFFSETOF(DEVPIC, aPics[1]),
1045	"picIOPortElcrWrite", "picIOPortElcrRead", NULL, NULL, "i8259 PIC #1 - elcr");
1046	if (VBOX_FAILURE(rc))
1047	return rc;
1048	}
1049
1050	rc = PDMDevHlpSSMRegister(pDevIns, pDevIns->pDevReg->szDeviceName, iInstance, 1 /* version /, sizeof(pData),
1051	NULL, picSaveExec, NULL,
1052	NULL, picLoadExec, NULL);
1053	if (VBOX_FAILURE(rc))
1054	return rc;
1055
1056
1057	#ifdef DEBUG
1058	/*
1059	* Register the info item.
1060	*/
1061	PDMDevHlpDBGFInfoRegister(pDevIns, "pic", "PIC info.", picInfo);
1062	#endif
1063
1064	/*
1065	* Initialize the device state.
1066	*/
1067	picReset(pDevIns);
1068
1069	#ifdef VBOX_WITH_STATISTICS
1070	/*
1071	* Statistics.
1072	*/
1073	PDMDevHlpSTAMRegister(pDevIns, &pData->StatSetIrqGC, STAMTYPE_COUNTER, "/PDM/PIC/SetIrqGC", STAMUNIT_OCCURENCES, "Number of PIC SetIrq calls in GC.");
1074	PDMDevHlpSTAMRegister(pDevIns, &pData->StatSetIrqHC, STAMTYPE_COUNTER, "/PDM/PIC/SetIrqHC", STAMUNIT_OCCURENCES, "Number of PIC SetIrq calls in HC.");
1075
1076	PDMDevHlpSTAMRegister(pDevIns, &pData->StatClearedActiveIRQ2, STAMTYPE_COUNTER, "/PDM/PIC/Masked/ActiveIRQ2", STAMUNIT_OCCURENCES, "Number of cleared irq 2.");
1077	PDMDevHlpSTAMRegister(pDevIns, &pData->StatClearedActiveMasterIRQ, STAMTYPE_COUNTER, "/PDM/PIC/Masked/ActiveMaster", STAMUNIT_OCCURENCES, "Number of cleared master irqs.");
1078	PDMDevHlpSTAMRegister(pDevIns, &pData->StatClearedActiveSlaveIRQ, STAMTYPE_COUNTER, "/PDM/PIC/Masked/ActiveSlave", STAMUNIT_OCCURENCES, "Number of cleared slave irqs.");
1079	#endif
1080
1081	return VINF_SUCCESS;
1082	}
1083
1084
1085	/**
1086	* The device registration structure.
1087	*/
1088	const PDMDEVREG g_DeviceI8259 =
1089	{
1090	/* u32Version */
1091	PDM_DEVREG_VERSION,
1092	/* szDeviceName */
1093	"i8259",
1094	/* szGCMod */
1095	"VBoxDDGC.gc",
1096	/* szR0Mod */
1097	"VBoxDDR0.r0",
1098	/* pszDescription */
1099	"Intel 8259 Programmable Interrupt Controller (PIC) Device.",
1100	/* fFlags */
1101	PDM_DEVREG_FLAGS_HOST_BITS_DEFAULT \| PDM_DEVREG_FLAGS_GUEST_BITS_32_64 \| PDM_DEVREG_FLAGS_PAE36 \| PDM_DEVREG_FLAGS_GC \| PDM_DEVREG_FLAGS_R0,
1102	/* fClass */
1103	PDM_DEVREG_CLASS_PIC,
1104	/* cMaxInstances */
1105	1,
1106	/* cbInstance */
1107	sizeof(DEVPIC),
1108	/* pfnConstruct */
1109	picConstruct,
1110	/* pfnDestruct */
1111	NULL,
1112	/* pfnRelocate */
1113	picRelocate,
1114	/* pfnIOCtl */
1115	NULL,
1116	/* pfnPowerOn */
1117	NULL,
1118	/* pfnReset */
1119	picReset,
1120	/* pfnSuspend */
1121	NULL,
1122	/* pfnResume */
1123	NULL,
1124	/* pfnAttach */
1125	NULL,
1126	/* pfnDetach */
1127	NULL,
1128	/* pfnQueryInterface. */
1129	NULL
1130	};
1131
1132	#endif /* IN_RING3 */
1133	#endif /* !VBOX_DEVICE_STRUCT_TESTCASE */
1134

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source: vbox/trunk/src/VBox/Devices/PC/DevPIC.cpp@ 6290

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