DevPIC.cpp@ 4753

Last change on this file since 4753 was 4071, checked in by vboxsync, 17 years ago
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1	/* $Id: DevPIC.cpp 4071 2007-08-07 17:07:59Z vboxsync $ */
2	/** @file
3	* Intel 8259 Programmable Interrupt Controller (PIC) Device.
4	*/
5
6	/*
7	* Copyright (C) 2006-2007 innotek GmbH
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License as published by the Free Software Foundation,
13	* in version 2 as it comes in the "COPYING" file of the VirtualBox OSE
14	* distribution. VirtualBox OSE is distributed in the hope that it will
15	* be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18	/*******************************************************************************
19	* Header Files *
20	*******************************************************************************/
21	#define LOG_GROUP LOG_GROUP_DEV_PIC
22	#include <VBox/pdmdev.h>
23	#include <VBox/log.h>
24	#include <iprt/assert.h>
25
26	#include "vl_vbox.h"
27
28
29	/*******************************************************************************
30	* Defined Constants And Macros *
31	*******************************************************************************/
32	/** @def PIC_LOCK
33	* Acquires the PDM lock. This is a NOP if locking is disabled. */
34	/** @def PIC_UNLOCK
35	* Releases the PDM lock. This is a NOP if locking is disabled. */
36	#ifdef VBOX_WITH_PDM_LOCK
37	# define PIC_LOCK(pThis, rc) \
38	do { \
39	int rc2 = (pThis)->CTXALLSUFF(pPicHlp)->pfnLock((pThis)->CTXSUFF(pDevIns), rc); \
40	if (rc2 != VINF_SUCCESS) \
41	return rc2; \
42	} while (0)
43	# define PIC_UNLOCK(pThis) \
44	(pThis)->CTXALLSUFF(pPicHlp)->pfnUnlock((pThis)->CTXSUFF(pDevIns))
45	#else /* !VBOX_WITH_PDM_LOCK */
46	# define PIC_LOCK(pThis, rc) do { } while (0)
47	# define PIC_UNLOCK(pThis) do { } while (0)
48	#endif /* !VBOX_WITH_PDM_LOCK */
49
50
51	#ifndef VBOX_DEVICE_STRUCT_TESTCASE
52	/*******************************************************************************
53	* Internal Functions *
54	*******************************************************************************/
55	__BEGIN_DECLS
56
57	PDMBOTHCBDECL(void) picSetIrq(PPDMDEVINS pDevIns, int iIrq, int iLevel);
58	PDMBOTHCBDECL(int) picGetInterrupt(PPDMDEVINS pDevIns);
59	PDMBOTHCBDECL(int) picIOPortRead(PPDMDEVINS pDevIns, void pvUser, RTIOPORT Port, uint32_t pu32, unsigned cb);
60	PDMBOTHCBDECL(int) picIOPortWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb);
61	PDMBOTHCBDECL(int) picIOPortElcrRead(PPDMDEVINS pDevIns, void pvUser, RTIOPORT Port, uint32_t pu32, unsigned cb);
62	PDMBOTHCBDECL(int) picIOPortElcrWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb);
63
64	__END_DECLS
65	#endif /* !VBOX_DEVICE_STRUCT_TESTCASE */
66
67
68	/*
69	* QEMU 8259 interrupt controller emulation
70	*
71	* Copyright (c) 2003-2004 Fabrice Bellard
72	*
73	* Permission is hereby granted, free of charge, to any person obtaining a copy
74	* of this software and associated documentation files (the "Software"), to deal
75	* in the Software without restriction, including without limitation the rights
76	* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
77	* copies of the Software, and to permit persons to whom the Software is
78	* furnished to do so, subject to the following conditions:
79	*
80	* The above copyright notice and this permission notice shall be included in
81	* all copies or substantial portions of the Software.
82	*
83	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
84	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
85	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
86	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
87	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
88	* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
89	* THE SOFTWARE.
90	*/
91
92	/* debug PIC */
93	#define DEBUG_PIC
94
95	/#define DEBUG_IRQ_COUNT/
96
97	typedef struct PicState {
98	uint8_t last_irr; /* edge detection */
99	uint8_t irr; /* interrupt request register */
100	uint8_t imr; /* interrupt mask register */
101	uint8_t isr; /* interrupt service register */
102	uint8_t priority_add; /* highest irq priority */
103	uint8_t irq_base;
104	uint8_t read_reg_select;
105	uint8_t poll;
106	uint8_t special_mask;
107	uint8_t init_state;
108	uint8_t auto_eoi;
109	uint8_t rotate_on_auto_eoi;
110	uint8_t special_fully_nested_mode;
111	uint8_t init4; /* true if 4 byte init */
112	uint8_t elcr; /* PIIX edge/trigger selection*/
113	uint8_t elcr_mask;
114	/** Pointer to the device instance, HCPtr. */
115	HCPTRTYPE(PPDMDEVINS) pDevInsHC;
116	/** Pointer to the device instance, GCPtr. */
117	GCPTRTYPE(PPDMDEVINS) pDevInsGC;
118	#if HC_ARCH_BITS == 64 && GC_ARCH_BITS != 64
119	RTGCPTR Alignment0;
120	#endif
121	} PicState;
122
123	/**
124	* A PIC device instance data.
125	*/
126	typedef struct DEVPIC
127	{
128	/** The two interrupt controllers. */
129	PicState aPics[2];
130	/** Pointer to the PIC R3 helpers. */
131	PCPDMPICHLPR3 pPicHlpR3;
132	/** Pointer to the PIC R0 helpers. */
133	PCPDMPICHLPR0 pPicHlpR0;
134	/** Pointer to the PIC GC helpers. */
135	PCPDMPICHLPGC pPicHlpGC;
136	/** Pointer to the device instance - GC Ptr. */
137	GCPTRTYPE(PPDMDEVINS) pDevInsGC;
138	/** Pointer to the device instance - GC Ptr. */
139	HCPTRTYPE(PPDMDEVINS) pDevInsHC;
140	#if HC_ARCH_BITS == 32
141	uint32_t Alignmnet0;
142	#endif
143	#ifdef VBOX_WITH_STATISTICS
144	STAMCOUNTER StatSetIrqGC;
145	STAMCOUNTER StatSetIrqHC;
146	STAMCOUNTER StatClearedActiveIRQ2;
147	STAMCOUNTER StatClearedActiveMasterIRQ;
148	STAMCOUNTER StatClearedActiveSlaveIRQ;
149	#endif
150	} DEVPIC, *PDEVPIC;
151
152
153	#ifndef VBOX_DEVICE_STRUCT_TESTCASE
154	#ifdef LOG_ENABLED
155	static inline void DumpPICState(PicState s, const char szFn)
156	{
157	PDEVPIC pData = PDMINS2DATA(CTXSUFF(s->pDevIns), PDEVPIC);
158
159	Log2(("%s: pic%d: elcr=%x last_irr=%x irr=%x imr=%x isr=%x irq_base=%x\n",
160	szFn, (&pData->aPics[0] == s) ? 0 : 1,
161	s->elcr, s->last_irr, s->irr, s->imr, s->isr, s->irq_base));
162	}
163	#else
164	# define DumpPICState(pData, szFn) do { } while (0)
165	#endif
166
167	/* set irq level. If an edge is detected, then the IRR is set to 1 */
168	static inline void pic_set_irq1(PicState *s, int irq, int level)
169	{
170	int mask;
171	Log(("pic_set_irq1: irq=%d level=%d\n", irq, level));
172	mask = 1 << irq;
173	if (s->elcr & mask) {
174	/* level triggered */
175	if (level) {
176	s->irr \|= mask;
177	s->last_irr \|= mask;
178	} else {
179	s->irr &= ~mask;
180	s->last_irr &= ~mask;
181	}
182	} else {
183	/* edge triggered */
184	if (level) {
185	if ((s->last_irr & mask) == 0)
186	{
187	Log2(("pic_set_irq1 irr=%x last_irr=%x\n", s->irr \| mask, s->last_irr));
188	s->irr \|= mask;
189	}
190	s->last_irr \|= mask;
191	} else {
192	s->last_irr &= ~mask;
193	}
194	}
195	DumpPICState(s, "pic_set_irq1");
196	}
197
198	/* return the highest priority found in mask (highest = smallest
199	number). Return 8 if no irq */
200	static inline int get_priority(PicState *s, int mask)
201	{
202	int priority;
203	if (mask == 0)
204	return 8;
205	priority = 0;
206	while ((mask & (1 << ((priority + s->priority_add) & 7))) == 0)
207	priority++;
208	return priority;
209	}
210
211	/* return the pic wanted interrupt. return -1 if none */
212	static int pic_get_irq(PicState *s)
213	{
214	PicState *pics = &(PDMINS2DATA(CTXSUFF(s->pDevIns), PDEVPIC))->aPics[0];
215	int mask, cur_priority, priority;
216	Log(("pic_get_irq%d: mask=%x\n", (s == pics) ? 0 : 1, s->irr & ~s->imr));
217	DumpPICState(s, "pic_get_irq");
218
219	mask = s->irr & ~s->imr;
220	priority = get_priority(s, mask);
221	Log(("pic_get_irq: priority=%x\n", priority));
222	if (priority == 8)
223	return -1;
224	/* compute current priority. If special fully nested mode on the
225	master, the IRQ coming from the slave is not taken into account
226	for the priority computation. */
227	mask = s->isr;
228	if (s->special_fully_nested_mode && s == &pics[0])
229	mask &= ~(1 << 2);
230	cur_priority = get_priority(s, mask);
231	Log(("pic_get_irq%d: cur_priority=%x pending=%d\n", (s == pics) ? 0 : 1, cur_priority, (priority == 8) ? -1 : (priority + s->priority_add) & 7));
232	if (priority < cur_priority) {
233	/* higher priority found: an irq should be generated */
234	return (priority + s->priority_add) & 7;
235	} else {
236	return -1;
237	}
238	}
239
240	/* raise irq to CPU if necessary. must be called every time the active
241	irq may change */
242	static int pic_update_irq(PDEVPIC pData)
243	{
244	PicState *pics = &pData->aPics[0];
245	int irq2, irq;
246
247	/* first look at slave pic */
248	irq2 = pic_get_irq(&pics[1]);
249	Log(("pic_update_irq irq2=%d\n", irq2));
250	if (irq2 >= 0) {
251	/* if irq request by slave pic, signal master PIC */
252	pic_set_irq1(&pics[0], 2, 1);
253	pic_set_irq1(&pics[0], 2, 0);
254	}
255	/* look at requested irq */
256	irq = pic_get_irq(&pics[0]);
257	if (irq >= 0)
258	{
259	/* If irq 2 is pending on the master pic, then there must be one pending on the slave pic too! Otherwise we'll get
260	* spurious slave interrupts in picGetInterrupt.
261	*/
262	if (irq != 2 \|\| irq2 != -1)
263	{
264	#if defined(DEBUG_PIC)
265	int i;
266	for(i = 0; i < 2; i++) {
267	Log(("pic%d: imr=%x irr=%x padd=%d\n",
268	i, pics[i].imr, pics[i].irr,
269	pics[i].priority_add));
270	}
271	Log(("pic: cpu_interrupt\n"));
272	#endif
273	pData->CTXALLSUFF(pPicHlp)->pfnSetInterruptFF(pData->CTXSUFF(pDevIns));
274	}
275	else
276	{
277	STAM_COUNTER_INC(&pData->StatClearedActiveIRQ2);
278	Log(("pic_update_irq: irq 2 is active, but no interrupt is pending on the slave pic!!\n"));
279	/* Clear it here, so lower priority interrupts can still be dispatched. */
280
281	/* if this was the only pending irq, then we must clear the interrupt ff flag */
282	pData->CTXALLSUFF(pPicHlp)->pfnClearInterruptFF(pData->CTXSUFF(pDevIns));
283
284	/** @note Is this correct? */
285	pics[0].irr &= ~(1 << 2);
286
287	/* Call ourselves again just in case other interrupts are pending */
288	return pic_update_irq(pData);
289	}
290	}
291	return VINF_SUCCESS;
292	}
293
294	/** @note if an interrupt line state changes from unmasked to masked, then it must be deactivated when currently pending! */
295	static void pic_update_imr(PDEVPIC pData, PicState *s, uint8_t val)
296	{
297	int irq, intno;
298	PicState *pActivePIC;
299
300	/* Query the current pending irq, if any. */
301	pActivePIC = &pData->aPics[0];
302	intno = irq = pic_get_irq(pActivePIC);
303	if (irq == 2)
304	{
305	pActivePIC = &pData->aPics[1];
306	irq = pic_get_irq(pActivePIC);
307	intno = irq + 8;
308	}
309
310	/* Update IMR */
311	s->imr = val;
312
313	/* If an interrupt is pending and now masked, then clear the FF flag. */
314	if ( irq >= 0
315	&& ((1 << irq) & ~pActivePIC->imr) == 0)
316	{
317	Log(("pic_update_imr: pic0: elcr=%x last_irr=%x irr=%x imr=%x isr=%x irq_base=%x\n",
318	pData->aPics[0].elcr, pData->aPics[0].last_irr, pData->aPics[0].irr, pData->aPics[0].imr, pData->aPics[0].isr, pData->aPics[0].irq_base));
319	Log(("pic_update_imr: pic1: elcr=%x last_irr=%x irr=%x imr=%x isr=%x irq_base=%x\n",
320	pData->aPics[1].elcr, pData->aPics[1].last_irr, pData->aPics[1].irr, pData->aPics[1].imr, pData->aPics[1].isr, pData->aPics[1].irq_base));
321
322	/* Clear pending IRQ 2 on master controller in case of slave interrupt. */
323	/** @todo Is this correct? */
324	if (intno > 7)
325	{
326	pData->aPics[0].irr &= ~(1 << 2);
327	STAM_COUNTER_INC(&pData->StatClearedActiveSlaveIRQ);
328	}
329	else
330	STAM_COUNTER_INC(&pData->StatClearedActiveMasterIRQ);
331
332	Log(("pic_update_imr: clear pending interrupt %d\n", intno));
333	pData->CTXALLSUFF(pPicHlp)->pfnClearInterruptFF(pData->CTXSUFF(pDevIns));
334	}
335	}
336
337
338	/**
339	* Set the an IRQ.
340	*
341	* @param pDevIns Device instance of the PICs.
342	* @param iIrq IRQ number to set.
343	* @param iLevel IRQ level.
344	*/
345	PDMBOTHCBDECL(void) picSetIrq(PPDMDEVINS pDevIns, int iIrq, int iLevel)
346	{
347	PDEVPIC pData = PDMINS2DATA(pDevIns, PDEVPIC);
348	Assert(pData->CTXSUFF(pDevIns) == pDevIns);
349	Assert(pData->aPics[0].CTXSUFF(pDevIns) == pDevIns);
350	Assert(pData->aPics[1].CTXSUFF(pDevIns) == pDevIns);
351	AssertMsg(iIrq < 16, ("iIrq=%d\n", iIrq));
352
353	Log(("picSetIrq %d %d\n", iIrq, iLevel));
354	DumpPICState(&pData->aPics[0], "picSetIrq");
355	DumpPICState(&pData->aPics[1], "picSetIrq");
356	STAM_COUNTER_INC(&pData->CTXSUFF(StatSetIrq));
357	pic_set_irq1(&pData->aPics[iIrq >> 3], iIrq & 7, iLevel & PDM_IRQ_LEVEL_HIGH);
358	pic_update_irq(pData);
359	if ((iLevel & PDM_IRQ_LEVEL_FLIP_FLOP) == PDM_IRQ_LEVEL_FLIP_FLOP)
360	{
361	pic_set_irq1(&pData->aPics[iIrq >> 3], iIrq & 7, 0);
362	pic_update_irq(pData);
363	}
364	}
365
366
367	/* acknowledge interrupt 'irq' */
368	static inline void pic_intack(PicState *s, int irq)
369	{
370	if (s->auto_eoi) {
371	if (s->rotate_on_auto_eoi)
372	s->priority_add = (irq + 1) & 7;
373	} else {
374	s->isr \|= (1 << irq);
375	}
376	/* We don't clear a level sensitive interrupt here */
377	if (!(s->elcr & (1 << irq)))
378	s->irr &= ~(1 << irq);
379	}
380
381
382	/**
383	* Get a pending interrupt.
384	*
385	* @returns Pending interrupt number.
386	* @param pDevIns Device instance of the PICs.
387	*/
388	PDMBOTHCBDECL(int) picGetInterrupt(PPDMDEVINS pDevIns)
389	{
390	PDEVPIC pData = PDMINS2DATA(pDevIns, PDEVPIC);
391	int irq;
392	int irq2;
393	int intno;
394
395	/* read the irq from the PIC */
396	DumpPICState(&pData->aPics[0], "picGetInterrupt");
397	DumpPICState(&pData->aPics[1], "picGetInterrupt");
398
399	irq = pic_get_irq(&pData->aPics[0]);
400	if (irq >= 0)
401	{
402	pic_intack(&pData->aPics[0], irq);
403	if (irq == 2)
404	{
405	irq2 = pic_get_irq(&pData->aPics[1]);
406	if (irq2 >= 0) {
407	pic_intack(&pData->aPics[1], irq2);
408	}
409	else
410	{
411	/* spurious IRQ on slave controller (impossible) */
412	AssertMsgFailed(("picGetInterrupt: spurious IRQ on slave controller\n"));
413	irq2 = 7;
414	}
415	intno = pData->aPics[1].irq_base + irq2;
416	Log2(("picGetInterrupt1: %x base=%x irq=%x\n", intno, pData->aPics[1].irq_base, irq2));
417	irq = irq2 + 8;
418	}
419	else {
420	intno = pData->aPics[0].irq_base + irq;
421	Log2(("picGetInterrupt0: %x base=%x irq=%x\n", intno, pData->aPics[0].irq_base, irq));
422	}
423	}
424	else
425	{
426	/* spurious IRQ on host controller (impossible) */
427	AssertMsgFailed(("picGetInterrupt: spurious IRQ on master controller\n"));
428	irq = 7;
429	intno = pData->aPics[0].irq_base + irq;
430	}
431	pic_update_irq(pData);
432
433	Log(("picGetInterrupt: pending 0:%d 1:%d\n", pic_get_irq(&pData->aPics[0]), pic_get_irq(&pData->aPics[1])));
434
435	return intno;
436	}
437
438	static void pic_reset(PicState *s)
439	{
440	HCPTRTYPE(PPDMDEVINS) pDevInsHC = s->pDevInsHC;
441	GCPTRTYPE(PPDMDEVINS) pDevInsGC = s->pDevInsGC;
442	int tmp, tmp2;
443
444	tmp = s->elcr_mask;
445	tmp2 = s->elcr;
446	memset(s, 0, sizeof(PicState));
447	s->elcr_mask = tmp;
448	s->elcr = tmp2;
449	s->pDevInsHC = pDevInsHC;
450	s->pDevInsGC = pDevInsGC;
451	}
452
453
454	static int pic_ioport_write(void *opaque, uint32_t addr, uint32_t val)
455	{
456	PicState s = (PicState)opaque;
457	PDEVPIC pData = PDMINS2DATA(CTXSUFF(s->pDevIns), PDEVPIC);
458	int rc = VINF_SUCCESS;
459	int priority, cmd, irq;
460
461	Log(("pic_write: addr=0x%02x val=0x%02x\n", addr, val));
462	addr &= 1;
463	if (addr == 0) {
464	if (val & 0x10) {
465	/* init */
466	pic_reset(s);
467	/* deassert a pending interrupt */
468	pData->CTXALLSUFF(pPicHlp)->pfnClearInterruptFF(pData->CTXSUFF(pDevIns));
469
470	s->init_state = 1;
471	s->init4 = val & 1;
472	if (val & 0x02)
473	AssertReleaseMsgFailed(("single mode not supported"));
474	if (val & 0x08)
475	AssertReleaseMsgFailed(("level sensitive irq not supported"));
476	} else if (val & 0x08) {
477	if (val & 0x04)
478	s->poll = 1;
479	if (val & 0x02)
480	s->read_reg_select = val & 1;
481	if (val & 0x40)
482	s->special_mask = (val >> 5) & 1;
483	} else {
484	cmd = val >> 5;
485	switch(cmd) {
486	case 0:
487	case 4:
488	s->rotate_on_auto_eoi = cmd >> 2;
489	break;
490	case 1: /* end of interrupt */
491	case 5:
492	{
493	priority = get_priority(s, s->isr);
494	if (priority != 8) {
495	irq = (priority + s->priority_add) & 7;
496	Log(("pic_write: EOI prio=%d irq=%d\n", priority, irq));
497	s->isr &= ~(1 << irq);
498	if (cmd == 5)
499	s->priority_add = (irq + 1) & 7;
500	rc = pic_update_irq(pData);
501	Assert(rc == VINF_SUCCESS);
502	}
503	break;
504	}
505	case 3:
506	{
507	irq = val & 7;
508	Log(("pic_write: EOI2 for irq %d\n", irq));
509	s->isr &= ~(1 << irq);
510	rc = pic_update_irq(pData);
511	Assert(rc == VINF_SUCCESS);
512	break;
513	}
514	case 6:
515	{
516	s->priority_add = (val + 1) & 7;
517	rc = pic_update_irq(pData);
518	Assert(rc == VINF_SUCCESS);
519	break;
520	}
521	case 7:
522	{
523	irq = val & 7;
524	Log(("pic_write: EOI3 for irq %d\n", irq));
525	s->isr &= ~(1 << irq);
526	s->priority_add = (irq + 1) & 7;
527	rc = pic_update_irq(pData);
528	Assert(rc == VINF_SUCCESS);
529	break;
530	}
531	default:
532	/* no operation */
533	break;
534	}
535	}
536	} else {
537	switch(s->init_state) {
538	case 0:
539	{
540	/* normal mode */
541	pic_update_imr(pData, s, val);
542
543	rc = pic_update_irq(pData);
544	Assert(rc == VINF_SUCCESS);
545	break;
546	}
547	case 1:
548	s->irq_base = val & 0xf8;
549	s->init_state = 2;
550	Log(("pic_write: set irq base to %x\n", s->irq_base));
551	break;
552	case 2:
553	if (s->init4) {
554	s->init_state = 3;
555	} else {
556	s->init_state = 0;
557	}
558	break;
559	case 3:
560	s->special_fully_nested_mode = (val >> 4) & 1;
561	s->auto_eoi = (val >> 1) & 1;
562	s->init_state = 0;
563	Log(("pic_write: special_fully_nested_mode=%d auto_eoi=%d\n", s->special_fully_nested_mode, s->auto_eoi));
564	break;
565	}
566	}
567	return rc;
568	}
569
570
571	static uint32_t pic_poll_read (PicState *s, uint32_t addr1)
572	{
573	PDEVPIC pData = PDMINS2DATA(CTXSUFF(s->pDevIns), PDEVPIC);
574	PicState *pics = &pData->aPics[0];
575	int ret;
576
577	ret = pic_get_irq(s);
578	if (ret >= 0) {
579	if (addr1 >> 7) {
580	Log2(("pic_poll_read: clear slave irq (isr)\n"));
581	pics[0].isr &= ~(1 << 2);
582	pics[0].irr &= ~(1 << 2);
583	}
584	Log2(("pic_poll_read: clear irq %d (isr)\n", ret));
585	s->irr &= ~(1 << ret);
586	s->isr &= ~(1 << ret);
587	if (addr1 >> 7 \|\| ret != 2)
588	pic_update_irq(pData);
589	} else {
590	ret = 0x07;
591	pic_update_irq(pData);
592	}
593
594	return ret;
595	}
596
597
598	static uint32_t pic_ioport_read(void opaque, uint32_t addr1, int pRC)
599	{
600	PicState s = (PicState)opaque;
601	unsigned int addr;
602	int ret;
603
604	*pRC = VINF_SUCCESS;
605
606	addr = addr1;
607	addr &= 1;
608	if (s->poll) {
609	ret = pic_poll_read(s, addr1);
610	s->poll = 0;
611	} else {
612	if (addr == 0) {
613	if (s->read_reg_select)
614	ret = s->isr;
615	else
616	ret = s->irr;
617	} else {
618	ret = s->imr;
619	}
620	}
621	Log(("pic_read: addr=0x%02x val=0x%02x\n", addr1, ret));
622	return ret;
623	}
624
625
626
627	#ifdef IN_RING3
628
629	static void pic_save(QEMUFile f, void opaque)
630	{
631	PicState s = (PicState)opaque;
632
633	qemu_put_8s(f, &s->last_irr);
634	qemu_put_8s(f, &s->irr);
635	qemu_put_8s(f, &s->imr);
636	qemu_put_8s(f, &s->isr);
637	qemu_put_8s(f, &s->priority_add);
638	qemu_put_8s(f, &s->irq_base);
639	qemu_put_8s(f, &s->read_reg_select);
640	qemu_put_8s(f, &s->poll);
641	qemu_put_8s(f, &s->special_mask);
642	qemu_put_8s(f, &s->init_state);
643	qemu_put_8s(f, &s->auto_eoi);
644	qemu_put_8s(f, &s->rotate_on_auto_eoi);
645	qemu_put_8s(f, &s->special_fully_nested_mode);
646	qemu_put_8s(f, &s->init4);
647	qemu_put_8s(f, &s->elcr);
648	}
649
650	static int pic_load(QEMUFile f, void opaque, int version_id)
651	{
652	PicState s = (PicState)opaque;
653
654	if (version_id != 1)
655	return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
656
657	qemu_get_8s(f, &s->last_irr);
658	qemu_get_8s(f, &s->irr);
659	qemu_get_8s(f, &s->imr);
660	qemu_get_8s(f, &s->isr);
661	qemu_get_8s(f, &s->priority_add);
662	qemu_get_8s(f, &s->irq_base);
663	qemu_get_8s(f, &s->read_reg_select);
664	qemu_get_8s(f, &s->poll);
665	qemu_get_8s(f, &s->special_mask);
666	qemu_get_8s(f, &s->init_state);
667	qemu_get_8s(f, &s->auto_eoi);
668	qemu_get_8s(f, &s->rotate_on_auto_eoi);
669	qemu_get_8s(f, &s->special_fully_nested_mode);
670	qemu_get_8s(f, &s->init4);
671	qemu_get_8s(f, &s->elcr);
672	return 0;
673	}
674	#endif /* IN_RING3 */
675
676
677	/* -=-=-=-=-=- wrappers -=-=-=-=-=- */
678
679	/**
680	* Port I/O Handler for IN operations.
681	*
682	* @returns VBox status code.
683	*
684	* @param pDevIns The device instance.
685	* @param pvUser User argument - pointer to the PIC in question.
686	* @param uPort Port number used for the IN operation.
687	* @param pu32 Where to store the result.
688	* @param cb Number of bytes read.
689	*/
690	PDMBOTHCBDECL(int) picIOPortRead(PPDMDEVINS pDevIns, void pvUser, RTIOPORT Port, uint32_t pu32, unsigned cb)
691	{
692	PDEVPIC pData = PDMINS2DATA(pDevIns, PDEVPIC);
693	uint32_t iPic = (uint32_t)(uintptr_t)pvUser;
694
695	Assert(iPic == 0 \|\| iPic == 1);
696	if (cb == 1)
697	{
698	int rc;
699	PIC_LOCK(pData, VINF_IOM_HC_IOPORT_READ);
700	*pu32 = pic_ioport_read(&pData->aPics[iPic], Port, &rc);
701	PIC_UNLOCK(pData);
702	return rc;
703	}
704	return VERR_IOM_IOPORT_UNUSED;
705	}
706
707	/**
708	* Port I/O Handler for OUT operations.
709	*
710	* @returns VBox status code.
711	*
712	* @param pDevIns The device instance.
713	* @param pvUser User argument - pointer to the PIC in question.
714	* @param uPort Port number used for the IN operation.
715	* @param u32 The value to output.
716	* @param cb The value size in bytes.
717	*/
718	PDMBOTHCBDECL(int) picIOPortWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb)
719	{
720	PDEVPIC pData = PDMINS2DATA(pDevIns, PDEVPIC);
721	uint32_t iPic = (uint32_t)(uintptr_t)pvUser;
722
723	Assert(iPic == 0 \|\| iPic == 1);
724
725	if (cb == 1)
726	{
727	int rc;
728	PIC_LOCK(pData, VINF_IOM_HC_IOPORT_WRITE);
729	rc = pic_ioport_write(&pData->aPics[iPic], Port, u32);
730	PIC_UNLOCK(pData);
731	return rc;
732	}
733	return VINF_SUCCESS;
734	}
735
736
737	/**
738	* Port I/O Handler for IN operations.
739	*
740	* @returns VBox status code.
741	*
742	* @param pDevIns The device instance.
743	* @param pvUser User argument - pointer to the PIC in question.
744	* @param uPort Port number used for the IN operation.
745	* @param pu32 Where to store the result.
746	* @param cb Number of bytes read.
747	*/
748	PDMBOTHCBDECL(int) picIOPortElcrRead(PPDMDEVINS pDevIns, void pvUser, RTIOPORT Port, uint32_t pu32, unsigned cb)
749	{
750	if (cb == 1)
751	{
752	PicState s = (PicState)pvUser;
753	PIC_LOCK(PDMINS2DATA(pDevIns, PDEVPIC), VINF_IOM_HC_IOPORT_READ);
754	*pu32 = s->elcr;
755	PIC_UNLOCK(PDMINS2DATA(pDevIns, PDEVPIC));
756	return VINF_SUCCESS;
757	}
758	return VERR_IOM_IOPORT_UNUSED;
759	}
760
761	/**
762	* Port I/O Handler for OUT operations.
763	*
764	* @returns VBox status code.
765	*
766	* @param pDevIns The device instance.
767	* @param pvUser User argument - pointer to the PIC in question.
768	* @param uPort Port number used for the IN operation.
769	* @param u32 The value to output.
770	* @param cb The value size in bytes.
771	*/
772	PDMBOTHCBDECL(int) picIOPortElcrWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb)
773	{
774	if (cb == 1)
775	{
776	PicState s = (PicState)pvUser;
777	PIC_LOCK(PDMINS2DATA(pDevIns, PDEVPIC), VINF_IOM_HC_IOPORT_WRITE);
778	s->elcr = u32 & s->elcr_mask;
779	PIC_UNLOCK(PDMINS2DATA(pDevIns, PDEVPIC));
780	}
781	return VINF_SUCCESS;
782	}
783
784
785	#ifdef IN_RING3
786
787	#ifdef DEBUG
788	/**
789	* PIC status info callback.
790	*
791	* @param pDevIns The device instance.
792	* @param pHlp The output helpers.
793	* @param pszArgs The arguments.
794	*/
795	static DECLCALLBACK(void) picInfo(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
796	{
797	PDEVPIC pData = PDMINS2DATA(pDevIns, PDEVPIC);
798
799	/*
800	* Show info.
801	*/
802	for (int i=0;i<2;i++)
803	{
804	pHlp->pfnPrintf(pHlp, "PIC%d:\n", i);
805	pHlp->pfnPrintf(pHlp, " last_irr = %02x\n", pData->aPics[i].last_irr);
806	pHlp->pfnPrintf(pHlp, " irr = %02x\n", pData->aPics[i].irr);
807	pHlp->pfnPrintf(pHlp, " imr = %02x\n", pData->aPics[i].imr);
808	pHlp->pfnPrintf(pHlp, " isr = %02x\n", pData->aPics[i].isr);
809	pHlp->pfnPrintf(pHlp, " priority_add = %02x\n", pData->aPics[i].priority_add);
810	pHlp->pfnPrintf(pHlp, " irq_base = %02x\n", pData->aPics[i].irq_base);
811	pHlp->pfnPrintf(pHlp, " read_reg_select = %02x\n", pData->aPics[i].read_reg_select);
812	pHlp->pfnPrintf(pHlp, " poll = %02x\n", pData->aPics[i].poll);
813	pHlp->pfnPrintf(pHlp, " special_mask = %02x\n", pData->aPics[i].special_mask);
814	pHlp->pfnPrintf(pHlp, " init_state = %02x\n", pData->aPics[i].init_state);
815	pHlp->pfnPrintf(pHlp, " auto_eoi = %02x\n", pData->aPics[i].auto_eoi);
816	pHlp->pfnPrintf(pHlp, " rotate_on_auto_eoi = %02x\n", pData->aPics[i].rotate_on_auto_eoi);
817	pHlp->pfnPrintf(pHlp, " special_fully_nested_mode = %02x\n", pData->aPics[i].special_fully_nested_mode);
818	pHlp->pfnPrintf(pHlp, " init4 = %02x\n", pData->aPics[i].init4);
819	pHlp->pfnPrintf(pHlp, " elcr = %02x\n", pData->aPics[i].elcr);
820	pHlp->pfnPrintf(pHlp, " elcr_mask = %02x\n", pData->aPics[i].elcr_mask);
821	}
822	}
823	#endif /* DEBUG */
824
825	/**
826	* Saves a state of the programmable interrupt controller device.
827	*
828	* @returns VBox status code.
829	* @param pDevIns The device instance.
830	* @param pSSMHandle The handle to save the state to.
831	*/
832	static DECLCALLBACK(int) picSaveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSMHandle)
833	{
834	PDEVPIC pData = PDMINS2DATA(pDevIns, PDEVPIC);
835	pic_save(pSSMHandle, &pData->aPics[0]);
836	pic_save(pSSMHandle, &pData->aPics[1]);
837	return VINF_SUCCESS;
838	}
839
840
841	/**
842	* Loads a saved programmable interrupt controller device state.
843	*
844	* @returns VBox status code.
845	* @param pDevIns The device instance.
846	* @param pSSMHandle The handle to the saved state.
847	* @param u32Version The data unit version number.
848	*/
849	static DECLCALLBACK(int) picLoadExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSMHandle, uint32_t u32Version)
850	{
851	PDEVPIC pData = PDMINS2DATA(pDevIns, PDEVPIC);
852	int rc = pic_load(pSSMHandle, &pData->aPics[0], u32Version);
853	if (VBOX_SUCCESS(rc))
854	rc = pic_load(pSSMHandle, &pData->aPics[1], u32Version);
855	return rc;
856	}
857
858
859	/* -=-=-=-=-=- real code -=-=-=-=-=- */
860
861	/**
862	* Reset notification.
863	*
864	* @returns VBox status.
865	* @param pDevIns The device instance data.
866	*/
867	static DECLCALLBACK(void) picReset(PPDMDEVINS pDevIns)
868	{
869	PDEVPIC pData = PDMINS2DATA(pDevIns, PDEVPIC);
870	unsigned i;
871	LogFlow(("picReset:\n"));
872	#ifdef VBOX_WITH_PDM_LOCK
873	pData->pPicHlpR3->pfnLock(pDevIns, VERR_INTERNAL_ERROR);
874	#endif
875
876	for (i = 0; i < ELEMENTS(pData->aPics); i++)
877	pic_reset(&pData->aPics[i]);
878
879	PIC_UNLOCK(pData);
880	}
881
882
883	/**
884	* @copydoc FNPDMDEVRELOCATE
885	*/
886	static DECLCALLBACK(void) picRelocate(PPDMDEVINS pDevIns, RTGCINTPTR offDelta)
887	{
888	PDEVPIC pData = PDMINS2DATA(pDevIns, PDEVPIC);
889	unsigned i;
890
891	pData->pDevInsGC = PDMDEVINS_2_GCPTR(pDevIns);
892	pData->pPicHlpGC = pData->pPicHlpR3->pfnGetGCHelpers(pDevIns);
893	for (i = 0; i < ELEMENTS(pData->aPics); i++)
894	pData->aPics[i].pDevInsGC = PDMDEVINS_2_GCPTR(pDevIns);
895	}
896
897
898	/**
899	* @copydoc FNPDMDEVCONSTRUCT
900	*/
901	static DECLCALLBACK(int) picConstruct(PPDMDEVINS pDevIns, int iInstance, PCFGMNODE pCfgHandle)
902	{
903	PDEVPIC pData = PDMINS2DATA(pDevIns, PDEVPIC);
904	PDMPICREG PicReg;
905	int rc;
906	bool fGCEnabled;
907	bool fR0Enabled;
908	Assert(iInstance == 0);
909
910	/*
911	* Validate and read configuration.
912	*/
913	if (!CFGMR3AreValuesValid(pCfgHandle, "GCEnabled\0R0Enabled\0"))
914	return VERR_PDM_DEVINS_UNKNOWN_CFG_VALUES;
915
916	rc = CFGMR3QueryBool(pCfgHandle, "GCEnabled", &fGCEnabled);
917	if (rc == VERR_CFGM_VALUE_NOT_FOUND)
918	fGCEnabled = true;
919	else if (VBOX_FAILURE(rc))
920	return PDMDEV_SET_ERROR(pDevIns, rc,
921	N_("Configuration error: failed to read GCEnabled as boolean"));
922
923	rc = CFGMR3QueryBool(pCfgHandle, "R0Enabled", &fR0Enabled);
924	if (rc == VERR_CFGM_VALUE_NOT_FOUND)
925	fR0Enabled = true;
926	else if (VBOX_FAILURE(rc))
927	return PDMDEV_SET_ERROR(pDevIns, rc,
928	N_("Configuration error: failed to read R0Enabled as boolean"));
929
930	Log(("i8259: fGCEnabled=%d fR0Enabled=%d\n", fGCEnabled, fR0Enabled));
931
932	/*
933	* Init the data.
934	*/
935	Assert(ELEMENTS(pData->aPics) == 2);
936	pData->pDevInsHC = pDevIns;
937	pData->pDevInsGC = PDMDEVINS_2_GCPTR(pDevIns);
938	pData->aPics[0].elcr_mask = 0xf8;
939	pData->aPics[1].elcr_mask = 0xde;
940	pData->aPics[0].pDevInsHC = pDevIns;
941	pData->aPics[1].pDevInsHC = pDevIns;
942	pData->aPics[0].pDevInsGC = PDMDEVINS_2_GCPTR(pDevIns);
943	pData->aPics[1].pDevInsGC = PDMDEVINS_2_GCPTR(pDevIns);
944
945	/*
946	* Register PIC, I/O ports and save state.
947	*/
948	PicReg.u32Version = PDM_PICREG_VERSION;
949	PicReg.pfnSetIrqHC = picSetIrq;
950	PicReg.pfnGetInterruptHC = picGetInterrupt;
951	if (fGCEnabled)
952	{
953	PicReg.pszSetIrqGC = "picSetIrq";
954	PicReg.pszGetInterruptGC = "picGetInterrupt";
955	}
956	else
957	{
958	PicReg.pszSetIrqGC = NULL;
959	PicReg.pszGetInterruptGC = NULL;
960	}
961
962	if (fR0Enabled)
963	{
964	PicReg.pszSetIrqR0 = "picSetIrq";
965	PicReg.pszGetInterruptR0 = "picGetInterrupt";
966	}
967	else
968	{
969	PicReg.pszSetIrqR0 = NULL;
970	PicReg.pszGetInterruptR0 = NULL;
971	}
972
973	Assert(pDevIns->pDevHlp->pfnPICRegister);
974	rc = pDevIns->pDevHlp->pfnPICRegister(pDevIns, &PicReg, &pData->pPicHlpR3);
975	if (VBOX_FAILURE(rc))
976	{
977	AssertMsgFailed(("PICRegister -> %Vrc\n", rc));
978	return rc;
979	}
980	if (fGCEnabled)
981	pData->pPicHlpGC = pData->pPicHlpR3->pfnGetGCHelpers(pDevIns);
982	rc = PDMDevHlpIOPortRegister(pDevIns, 0x20, 2, (void *)0, picIOPortWrite, picIOPortRead, NULL, NULL, "i8259 PIC #0");
983	if (VBOX_FAILURE(rc))
984	return rc;
985	rc = PDMDevHlpIOPortRegister(pDevIns, 0xa0, 2, (void *)1, picIOPortWrite, picIOPortRead, NULL, NULL, "i8259 PIC #1");
986	if (VBOX_FAILURE(rc))
987	return rc;
988	if (fGCEnabled)
989	{
990	rc = PDMDevHlpIOPortRegisterGC(pDevIns, 0x20, 2, 0, "picIOPortWrite", "picIOPortRead", NULL, NULL, "i8259 PIC #0");
991	if (VBOX_FAILURE(rc))
992	return rc;
993	rc = PDMDevHlpIOPortRegisterGC(pDevIns, 0xa0, 2, 1, "picIOPortWrite", "picIOPortRead", NULL, NULL, "i8259 PIC #1");
994	if (VBOX_FAILURE(rc))
995	return rc;
996	}
997	if (fR0Enabled)
998	{
999	pData->pPicHlpR0 = pData->pPicHlpR3->pfnGetR0Helpers(pDevIns);
1000
1001	rc = PDMDevHlpIOPortRegisterR0(pDevIns, 0x20, 2, 0, "picIOPortWrite", "picIOPortRead", NULL, NULL, "i8259 PIC #0");
1002	if (VBOX_FAILURE(rc))
1003	return rc;
1004	rc = PDMDevHlpIOPortRegisterR0(pDevIns, 0xa0, 2, 1, "picIOPortWrite", "picIOPortRead", NULL, NULL, "i8259 PIC #1");
1005	if (VBOX_FAILURE(rc))
1006	return rc;
1007	}
1008
1009	rc = PDMDevHlpIOPortRegister(pDevIns, 0x4d0, 1, &pData->aPics[0],
1010	picIOPortElcrWrite, picIOPortElcrRead, NULL, NULL, "i8259 PIC #0 - elcr");
1011	if (VBOX_FAILURE(rc))
1012	return rc;
1013	rc = PDMDevHlpIOPortRegister(pDevIns, 0x4d1, 1, &pData->aPics[1],
1014	picIOPortElcrWrite, picIOPortElcrRead, NULL, NULL, "i8259 PIC #1 - elcr");
1015	if (VBOX_FAILURE(rc))
1016	return rc;
1017	if (fGCEnabled)
1018	{
1019	RTGCPTR pDataGC = PDMINS2DATA_GCPTR(pDevIns);
1020	rc = PDMDevHlpIOPortRegisterGC(pDevIns, 0x4d0, 1, pDataGC + RT_OFFSETOF(DEVPIC, aPics[0]),
1021	"picIOPortElcrWrite", "picIOPortElcrRead", NULL, NULL, "i8259 PIC #0 - elcr");
1022	if (VBOX_FAILURE(rc))
1023	return rc;
1024	rc = PDMDevHlpIOPortRegisterGC(pDevIns, 0x4d1, 1, pDataGC + RT_OFFSETOF(DEVPIC, aPics[1]),
1025	"picIOPortElcrWrite", "picIOPortElcrRead", NULL, NULL, "i8259 PIC #1 - elcr");
1026	if (VBOX_FAILURE(rc))
1027	return rc;
1028	}
1029	if (fR0Enabled)
1030	{
1031	RTR0PTR pDataR0 = PDMINS2DATA_R0PTR(pDevIns);
1032	rc = PDMDevHlpIOPortRegisterR0(pDevIns, 0x4d0, 1, pDataR0 + RT_OFFSETOF(DEVPIC, aPics[0]),
1033	"picIOPortElcrWrite", "picIOPortElcrRead", NULL, NULL, "i8259 PIC #0 - elcr");
1034	if (VBOX_FAILURE(rc))
1035	return rc;
1036	rc = PDMDevHlpIOPortRegisterR0(pDevIns, 0x4d1, 1, pDataR0 + RT_OFFSETOF(DEVPIC, aPics[1]),
1037	"picIOPortElcrWrite", "picIOPortElcrRead", NULL, NULL, "i8259 PIC #1 - elcr");
1038	if (VBOX_FAILURE(rc))
1039	return rc;
1040	}
1041
1042	rc = PDMDevHlpSSMRegister(pDevIns, pDevIns->pDevReg->szDeviceName, iInstance, 1 /* version /, sizeof(pData),
1043	NULL, picSaveExec, NULL,
1044	NULL, picLoadExec, NULL);
1045	if (VBOX_FAILURE(rc))
1046	return rc;
1047
1048
1049	#ifdef DEBUG
1050	/*
1051	* Register the info item.
1052	*/
1053	PDMDevHlpDBGFInfoRegister(pDevIns, "pic", "PIC info.", picInfo);
1054	#endif
1055
1056	/*
1057	* Initialize the device state.
1058	*/
1059	picReset(pDevIns);
1060
1061	#ifdef VBOX_WITH_STATISTICS
1062	/*
1063	* Statistics.
1064	*/
1065	PDMDevHlpSTAMRegister(pDevIns, &pData->StatSetIrqGC, STAMTYPE_COUNTER, "/PDM/PIC/SetIrqGC", STAMUNIT_OCCURENCES, "Number of PIC SetIrq calls in GC.");
1066	PDMDevHlpSTAMRegister(pDevIns, &pData->StatSetIrqHC, STAMTYPE_COUNTER, "/PDM/PIC/SetIrqHC", STAMUNIT_OCCURENCES, "Number of PIC SetIrq calls in HC.");
1067
1068	PDMDevHlpSTAMRegister(pDevIns, &pData->StatClearedActiveIRQ2, STAMTYPE_COUNTER, "/PDM/PIC/Masked/ActiveIRQ2", STAMUNIT_OCCURENCES, "Number of cleared irq 2.");
1069	PDMDevHlpSTAMRegister(pDevIns, &pData->StatClearedActiveMasterIRQ, STAMTYPE_COUNTER, "/PDM/PIC/Masked/ActiveMaster", STAMUNIT_OCCURENCES, "Number of cleared master irqs.");
1070	PDMDevHlpSTAMRegister(pDevIns, &pData->StatClearedActiveSlaveIRQ, STAMTYPE_COUNTER, "/PDM/PIC/Masked/ActiveSlave", STAMUNIT_OCCURENCES, "Number of cleared slave irqs.");
1071	#endif
1072
1073	return VINF_SUCCESS;
1074	}
1075
1076
1077	/**
1078	* The device registration structure.
1079	*/
1080	const PDMDEVREG g_DeviceI8259 =
1081	{
1082	/* u32Version */
1083	PDM_DEVREG_VERSION,
1084	/* szDeviceName */
1085	"i8259",
1086	/* szGCMod */
1087	"VBoxDDGC.gc",
1088	/* szR0Mod */
1089	"VBoxDDR0.r0",
1090	/* pszDescription */
1091	"Intel 8259 Programmable Interrupt Controller (PIC) Device.",
1092	/* fFlags */
1093	PDM_DEVREG_FLAGS_HOST_BITS_DEFAULT \| PDM_DEVREG_FLAGS_GUEST_BITS_32_64 \| PDM_DEVREG_FLAGS_PAE36 \| PDM_DEVREG_FLAGS_GC \| PDM_DEVREG_FLAGS_R0,
1094	/* fClass */
1095	PDM_DEVREG_CLASS_PIC,
1096	/* cMaxInstances */
1097	1,
1098	/* cbInstance */
1099	sizeof(DEVPIC),
1100	/* pfnConstruct */
1101	picConstruct,
1102	/* pfnDestruct */
1103	NULL,
1104	/* pfnRelocate */
1105	picRelocate,
1106	/* pfnIOCtl */
1107	NULL,
1108	/* pfnPowerOn */
1109	NULL,
1110	/* pfnReset */
1111	picReset,
1112	/* pfnSuspend */
1113	NULL,
1114	/* pfnResume */
1115	NULL,
1116	/* pfnAttach */
1117	NULL,
1118	/* pfnDetach */
1119	NULL,
1120	/* pfnQueryInterface. */
1121	NULL
1122	};
1123
1124	#endif /* IN_RING3 */
1125	#endif /* !VBOX_DEVICE_STRUCT_TESTCASE */
1126

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source: vbox/trunk/src/VBox/Devices/PC/DevPIC.cpp@ 4753

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