VirtualBox

source: vbox/trunk/src/VBox/Devices/PC/DevLpc.cpp@ 93492

Last change on this file since 93492 was 93115, checked in by vboxsync, 3 years ago

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1/* $Id: DevLpc.cpp 93115 2022-01-01 11:31:46Z vboxsync $ */
2/** @file
3 * DevLPC - Minimal ICH9 LPC device emulation.
4 */
5
6/*
7 * Copyright (C) 2018-2022 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18
19/*********************************************************************************************************************************
20* Header Files *
21*********************************************************************************************************************************/
22#define LOG_GROUP LOG_GROUP_DEV_LPC
23#include <VBox/vmm/pdmdev.h>
24#include <VBox/vmm/stam.h>
25#include <VBox/log.h>
26
27#include <iprt/assert.h>
28#include <iprt/string.h>
29
30#include "VBoxDD.h"
31
32
33/*********************************************************************************************************************************
34* Defined Constants And Macros *
35*********************************************************************************************************************************/
36#define LPC_REG_HPET_CONFIG_POINTER 0x3404
37#define LPC_REG_GCS 0x3410
38
39
40/*********************************************************************************************************************************
41* Structures and Typedefs *
42*********************************************************************************************************************************/
43/**
44 * The ICH9 LPC state.
45 */
46typedef struct LPCSTATE
47{
48 /** The root complex base address. */
49 RTGCPHYS32 GCPhys32Rcba;
50 /** The ICH version (7 or 9). */
51 uint8_t uIchVersion;
52 /** Explicit padding. */
53 uint8_t abPadding[HC_ARCH_BITS == 32 ? 3 : 7];
54
55 /** Number of MMIO reads. */
56 STAMCOUNTER StatMmioReads;
57 /** Number of MMIO writes. */
58 STAMCOUNTER StatMmioWrites;
59 /** Number of PCI config space reads. */
60 STAMCOUNTER StatPciCfgReads;
61 /** Number of PCI config space writes. */
62 STAMCOUNTER StatPciCfgWrites;
63
64 /** Handle to the MMIO region. */
65 IOMMMIOHANDLE hMmio;
66} LPCSTATE;
67/** Pointer to the LPC state. */
68typedef LPCSTATE *PLPCSTATE;
69
70
71#ifndef VBOX_DEVICE_STRUCT_TESTCASE
72
73/**
74 * @callback_method_impl{FNIOMMMIONEWREAD}
75 */
76static DECLCALLBACK(VBOXSTRICTRC) lpcMmioRead(PPDMDEVINS pDevIns, void *pvUser, RTGCPHYS off, void *pv, unsigned cb)
77{
78 RT_NOREF(pvUser, cb);
79 PLPCSTATE pThis = PDMDEVINS_2_DATA(pDevIns, PLPCSTATE);
80 Assert(cb == 4); Assert(!(off & 3)); /* IOMMMIO_FLAGS_READ_DWORD should make sure of this */
81
82 uint32_t *puValue = (uint32_t *)pv;
83 if (off == LPC_REG_HPET_CONFIG_POINTER)
84 {
85 *puValue = 0xf0;
86 Log(("lpcMmioRead: HPET_CONFIG_POINTER: %#x\n", *puValue));
87 }
88 else if (off == LPC_REG_GCS)
89 {
90 *puValue = 0;
91 Log(("lpcMmioRead: GCS: %#x\n", *puValue));
92 }
93 else
94 {
95 *puValue = 0;
96 Log(("lpcMmioRead: WARNING! Unknown register %#RGp!\n", off));
97 }
98
99 STAM_REL_COUNTER_INC(&pThis->StatMmioReads);
100 return VINF_SUCCESS;
101}
102
103
104/**
105 * @callback_method_impl{FNIOMMMIONEWWRITE}
106 */
107static DECLCALLBACK(VBOXSTRICTRC) lpcMmioWrite(PPDMDEVINS pDevIns, void *pvUser, RTGCPHYS off, void const *pv, unsigned cb)
108{
109 PLPCSTATE pThis = PDMDEVINS_2_DATA(pDevIns, PLPCSTATE);
110 RT_NOREF(pvUser, pv);
111
112 if (cb == 4)
113 {
114 if (off == LPC_REG_GCS)
115 Log(("lpcMmioWrite: Ignorning write to GCS: %.*Rhxs\n", cb, pv));
116 else
117 Log(("lpcMmioWrite: Ignorning write to unknown register %#RGp: %.*Rhxs\n", off, cb, pv));
118 }
119 else
120 Log(("lpcMmioWrite: WARNING! Ignoring non-DWORD write to off=%#RGp: %.*Rhxs\n", off, cb, pv));
121
122 STAM_REL_COUNTER_INC(&pThis->StatMmioWrites);
123 return VINF_SUCCESS;
124}
125
126#ifdef IN_RING3
127
128/**
129 * @callback_method_impl{FNPCICONFIGREAD}
130 */
131static DECLCALLBACK(VBOXSTRICTRC) lpcR3PciConfigRead(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev,
132 uint32_t uAddress, unsigned cb, uint32_t *pu32Value)
133{
134 PLPCSTATE pThis = PDMDEVINS_2_DATA(pDevIns, PLPCSTATE);
135 Assert(pPciDev == pDevIns->apPciDevs[0]);
136
137 STAM_REL_COUNTER_INC(&pThis->StatPciCfgReads);
138 VBOXSTRICTRC rcStrict = PDMDevHlpPCIConfigRead(pDevIns, pPciDev, uAddress, cb, pu32Value);
139 switch (cb)
140 {
141 case 1: Log(("lpcR3PciConfigRead: %#04x -> %#04x (%Rrc)\n", uAddress, *pu32Value, VBOXSTRICTRC_VAL(rcStrict))); break;
142 case 2: Log(("lpcR3PciConfigRead: %#04x -> %#06x (%Rrc)\n", uAddress, *pu32Value, VBOXSTRICTRC_VAL(rcStrict))); break;
143 case 4: Log(("lpcR3PciConfigRead: %#04x -> %#010x (%Rrc)\n", uAddress, *pu32Value, VBOXSTRICTRC_VAL(rcStrict))); break;
144 }
145 return rcStrict;
146}
147
148
149/**
150 * @callback_method_impl{FNPCICONFIGWRITE}
151 */
152static DECLCALLBACK(VBOXSTRICTRC) lpcR3PciConfigWrite(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev,
153 uint32_t uAddress, unsigned cb, uint32_t u32Value)
154{
155 PLPCSTATE pThis = PDMDEVINS_2_DATA(pDevIns, PLPCSTATE);
156 Assert(pPciDev == pDevIns->apPciDevs[0]);
157
158 STAM_REL_COUNTER_INC(&pThis->StatPciCfgWrites);
159 switch (cb)
160 {
161 case 1: Log(("lpcR3PciConfigWrite: %#04x <- %#04x\n", uAddress, u32Value)); break;
162 case 2: Log(("lpcR3PciConfigWrite: %#04x <- %#06x\n", uAddress, u32Value)); break;
163 case 4: Log(("lpcR3PciConfigWrite: %#04x <- %#010x\n", uAddress, u32Value)); break;
164 }
165
166 return PDMDevHlpPCIConfigWrite(pDevIns, pPciDev, uAddress, cb, u32Value);
167}
168
169
170/**
171 * Info handler, device version.
172 *
173 * @param pDevIns Device instance which registered the info.
174 * @param pHlp Callback functions for doing output.
175 * @param pszArgs Argument string. Optional and specific to the handler.
176 */
177static DECLCALLBACK(void) lpcInfo(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
178{
179 PLPCSTATE pThis = PDMDEVINS_2_DATA(pDevIns, PLPCSTATE);
180 PPDMPCIDEV pPciDev = pDevIns->apPciDevs[0];
181 RT_NOREF(pszArgs);
182
183 if (pThis->uIchVersion == 7)
184 {
185 uint8_t b1 = PDMPciDevGetByte(pPciDev, 0xde);
186 uint8_t b2 = PDMPciDevGetByte(pPciDev, 0xad);
187 if ( b1 == 0xbe
188 && b2 == 0xef)
189 pHlp->pfnPrintf(pHlp, "APIC backdoor activated\n");
190 else
191 pHlp->pfnPrintf(pHlp, "APIC backdoor closed: %02x %02x\n", b1, b2);
192 }
193
194 for (unsigned iLine = 0; iLine < 8; iLine++)
195 {
196 unsigned offBase = iLine < 4 ? 0x60 : 0x68 - 4;
197 uint8_t bMap = PDMPciDevGetByte(pPciDev, offBase + iLine);
198 if (bMap & 0x80)
199 pHlp->pfnPrintf(pHlp, "PIRQ%c_ROUT disabled\n", 'A' + iLine);
200 else
201 pHlp->pfnPrintf(pHlp, "PIRQ%c_ROUT -> IRQ%d\n", 'A' + iLine, bMap & 0xf);
202 }
203}
204
205
206/**
207 * @interface_method_impl{PDMDEVREG,pfnConstruct}
208 */
209static DECLCALLBACK(int) lpcConstruct(PPDMDEVINS pDevIns, int iInstance, PCFGMNODE pCfg)
210{
211 PDMDEV_CHECK_VERSIONS_RETURN(pDevIns);
212 PLPCSTATE pThis = PDMDEVINS_2_DATA(pDevIns, PLPCSTATE);
213 PCPDMDEVHLPR3 pHlp = pDevIns->pHlpR3;
214 Assert(iInstance == 0); RT_NOREF(iInstance);
215
216 /*
217 * Read configuration.
218 */
219 PDMDEV_VALIDATE_CONFIG_RETURN(pDevIns, "RCBA|ICHVersion", "");
220
221 int rc = pHlp->pfnCFGMQueryU8Def(pCfg, "ICHVersion", &pThis->uIchVersion, 7 /** @todo 9 */);
222 if (RT_FAILURE(rc))
223 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to query boolean value \"ICHVersion\""));
224 if ( pThis->uIchVersion != 7
225 && pThis->uIchVersion != 9)
226 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Invalid \"ICHVersion\" value (must be 7 or 9)"));
227
228 rc = pHlp->pfnCFGMQueryU32Def(pCfg, "RCBA", &pThis->GCPhys32Rcba, UINT32_C(0xfed1c000));
229 if (RT_FAILURE(rc))
230 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to query boolean value \"RCBA\""));
231
232
233 /*
234 * Register the PCI device.
235 *
236 * See sections 13.1 (page 371) and section 13.8.1 (page 429) in the ICH9
237 * specification.
238 *
239 * We set these up so they don't need much/any configuration from the
240 * guest. This is quite possibly wrong, but at the moment we just need to
241 * have this device working w/o lots of firmware fun.
242 */
243 PPDMPCIDEV pPciDev = pDevIns->apPciDevs[0];
244 PDMPCIDEV_ASSERT_VALID(pDevIns, pPciDev);
245
246 PDMPciDevSetVendorId(pPciDev, 0x8086); /* Intel */
247 if (pThis->uIchVersion == 7)
248 PDMPciDevSetDeviceId(pPciDev, 0x27b9);
249 else if (pThis->uIchVersion == 9)
250 PDMPciDevSetDeviceId(pPciDev, 0x2918); /** @todo unsure if 0x2918 is the right PCI ID... */
251 else
252 AssertFailedReturn(VERR_INTERNAL_ERROR_3);
253 PDMPciDevSetCommand(pPciDev, PCI_COMMAND_IOACCESS | PCI_COMMAND_MEMACCESS | PCI_COMMAND_BUSMASTER);
254 PDMPciDevSetStatus(pPciDev, 0x0210); /* Note! Used to be 0x0200 for ICH7. */
255 PDMPciDevSetRevisionId(pPciDev, 0x02);
256 PDMPciDevSetClassSub(pPciDev, 0x01); /* PCI-to-ISA bridge */
257 PDMPciDevSetClassBase(pPciDev, 0x06); /* bridge */
258 PDMPciDevSetHeaderType(pPciDev, 0x80); /* Normal, multifunction device (so that other devices can be its functions) */
259 if (pThis->uIchVersion == 7)
260 {
261 PDMPciDevSetSubSystemVendorId(pPciDev, 0x8086);
262 PDMPciDevSetSubSystemId(pPciDev, 0x7270);
263 }
264 else if (pThis->uIchVersion == 9)
265 {
266 PDMPciDevSetSubSystemVendorId(pPciDev, 0x0000); /** @todo docs stays subsystem IDs are zero, check real HW */
267 PDMPciDevSetSubSystemId(pPciDev, 0x0000);
268 }
269 PDMPciDevSetInterruptPin(pPciDev, 0x00); /* The LPC device itself generates no interrupts */
270 PDMPciDevSetDWord(pPciDev, 0x40, 0x00008001); /* PMBASE: ACPI base address; (PM_PORT_BASE (?) * 2 | PCI_ADDRESS_SPACE_IO) */
271 PDMPciDevSetByte(pPciDev, 0x44, 0x80); /* ACPI_CNTL: SCI is IRQ9, ACPI enabled */ /** @todo documented as defaulting to 0x00. */
272 PDMPciDevSetDWord(pPciDev, 0x48, 0x00000001); /* GPIOBASE (note: used to be zero) */
273 PDMPciDevSetByte(pPciDev, 0x4c, 0x4d); /* GC - GPIO control: ??? */ /** @todo documented as defaulting to 0x00. */
274 if (pThis->uIchVersion == 7)
275 PDMPciDevSetByte(pPciDev, 0x4e, 0x03); /* ??? */
276 PDMPciDevSetByte(pPciDev, 0x60, 0x0b); /* PIRQA_ROUT: PCI A -> IRQ 11 (documented default is 0x80) */
277 PDMPciDevSetByte(pPciDev, 0x61, 0x09); /* PIRQB_ROUT: PCI B -> IRQ 9 (documented default is 0x80) */
278 PDMPciDevSetByte(pPciDev, 0x62, 0x0b); /* PIRQC_ROUT: PCI C -> IRQ 11 (documented default is 0x80) */
279 PDMPciDevSetByte(pPciDev, 0x63, 0x09); /* PIRQD_ROUT: PCI D -> IRQ 9 (documented default is 0x80) */
280 PDMPciDevSetByte(pPciDev, 0x64, 0x10); /* SIRQ_CNTL: Serial IRQ Control 10h R/W, RO */
281 PDMPciDevSetByte(pPciDev, 0x68, 0x80); /* PIRQE_ROUT */
282 PDMPciDevSetByte(pPciDev, 0x69, 0x80); /* PIRQF_ROUT */
283 PDMPciDevSetByte(pPciDev, 0x6a, 0x80); /* PIRQG_ROUT */
284 PDMPciDevSetByte(pPciDev, 0x6b, 0x80); /* PIRQH_ROUT */
285 PDMPciDevSetWord(pPciDev, 0x6c, 0x00f8); /* IPC_IBDF: IOxAPIC bus:device:function. (Note! Used to be zero.) */
286 if (pThis->uIchVersion == 7)
287 {
288 /* No idea what this is/was yet: */
289 PDMPciDevSetByte(pPciDev, 0x70, 0x80);
290 PDMPciDevSetByte(pPciDev, 0x76, 0x0c);
291 PDMPciDevSetByte(pPciDev, 0x77, 0x0c);
292 PDMPciDevSetByte(pPciDev, 0x78, 0x02);
293 PDMPciDevSetByte(pPciDev, 0x79, 0x00);
294 }
295 PDMPciDevSetWord(pPciDev, 0x80, 0x0000); /* LPC_I/O_DEC: I/O decode ranges. */
296 PDMPciDevSetWord(pPciDev, 0x82, 0x0000); /* LPC_EN: LPC I/F enables. */
297 PDMPciDevSetDWord(pPciDev, 0x84, 0x00000000); /* GEN1_DEC: LPC I/F generic decode range 1. */
298 PDMPciDevSetDWord(pPciDev, 0x88, 0x00000000); /* GEN2_DEC: LPC I/F generic decode range 2. */
299 PDMPciDevSetDWord(pPciDev, 0x8c, 0x00000000); /* GEN3_DEC: LPC I/F generic decode range 3. */
300 PDMPciDevSetDWord(pPciDev, 0x90, 0x00000000); /* GEN4_DEC: LPC I/F generic decode range 4. */
301
302 PDMPciDevSetWord(pPciDev, 0xa0, 0x0008); /* GEN_PMCON_1: Documented default is 0x0000 */
303 PDMPciDevSetByte(pPciDev, 0xa2, 0x00); /* GEN_PMON_2: */
304 PDMPciDevSetByte(pPciDev, 0xa4, 0x00); /* GEN_PMON_3: */
305 PDMPciDevSetByte(pPciDev, 0xa6, 0x00); /* GEN_PMON_LOCK: Configuration lock. */
306 if (pThis->uIchVersion == 7)
307 PDMPciDevSetByte(pPciDev, 0xa8, 0x0f); /* Is this part of GEN_PMON_LOCK? */
308 PDMPciDevSetByte(pPciDev, 0xab, 0x00); /* BM_BREAK_EN */
309 PDMPciDevSetDWord(pPciDev, 0xac, 0x00000000); /* PMIR: Power */
310 PDMPciDevSetDWord(pPciDev, 0xb8, 0x00000000); /* GPI_ROUT: GPI Route Control */
311 if (pThis->uIchVersion == 9)
312 {
313 /** @todo the next two values looks bogus. */
314 PDMPciDevSetDWord(pPciDev, 0xd0, 0x00112233); /* FWH_SEL1: Firmware Hub Select 1 */
315 PDMPciDevSetWord(pPciDev, 0xd4, 0x4567); /* FWH_SEL2: Firmware Hub Select 2 */
316 PDMPciDevSetWord(pPciDev, 0xd8, 0xffcf); /* FWH_DEC_EN1: Firmware Hub Decode Enable 1 */
317 PDMPciDevSetByte(pPciDev, 0xdc, 0x00); /* BIOS_CNTL: BIOS control */
318 PDMPciDevSetWord(pPciDev, 0xe0, 0x0009); /* FDCAP: Feature Detection Capability ID */
319 PDMPciDevSetByte(pPciDev, 0xe2, 0x0c); /* FDLEN: Feature Detection Capability Length */
320 PDMPciDevSetByte(pPciDev, 0xe3, 0x10); /* FDVER: Feature Detection Version */
321 PDMPciDevSetByte(pPciDev, 0xe4, 0x20); /* FDVCT[0]: 5=SATA RAID 0/1/5/10 capability (1=disabled) */
322 PDMPciDevSetByte(pPciDev, 0xe5, 0x00); /* FDVCT[1]: */
323 PDMPciDevSetByte(pPciDev, 0xe6, 0x00); /* FDVCT[2]: */
324 PDMPciDevSetByte(pPciDev, 0xe7, 0x00); /* FDVCT[3]: */
325 PDMPciDevSetByte(pPciDev, 0xe8, 0xc0); /* FDVCT[4]: 6-7=Intel active magament technology capability (11=disabled). */
326 PDMPciDevSetByte(pPciDev, 0xe9, 0x00); /* FDVCT[5]: */
327 PDMPciDevSetByte(pPciDev, 0xea, 0x00); /* FDVCT[6]: */
328 PDMPciDevSetByte(pPciDev, 0xeb, 0x00); /* FDVCT[7]: */
329 PDMPciDevSetByte(pPciDev, 0xec, 0x00); /* FDVCT[8]: */
330 PDMPciDevSetByte(pPciDev, 0xed, 0x00); /* FDVCT[9]: */
331 PDMPciDevSetByte(pPciDev, 0xee, 0x00); /* FDVCT[a]: */
332 PDMPciDevSetByte(pPciDev, 0xef, 0x00); /* FDVCT[b]: */
333 }
334
335 /* RCBA: Root complex base address (documented default is 0x00000000). Bit 0 is enable bit. */
336 Assert(!(pThis->GCPhys32Rcba & 0x3fff)); /* 16KB aligned */
337 PDMPciDevSetDWord(pPciDev, 0xf0, pThis->GCPhys32Rcba | 1);
338
339 rc = PDMDevHlpPCIRegisterEx(pDevIns, pPciDev, PDMPCIDEVREG_F_NOT_MANDATORY_NO, 31 /*uPciDevNo*/, 0 /*uPciFunNo*/, "lpc");
340 AssertRCReturn(rc, rc);
341 rc = PDMDevHlpPCIInterceptConfigAccesses(pDevIns, pPciDev, lpcR3PciConfigRead, lpcR3PciConfigWrite);
342 AssertRCReturn(rc, rc);
343
344 /*
345 * Register the MMIO regions.
346 */
347 /** @todo This should actually be done when RCBA is enabled, but was
348 * mentioned above we just want this working. */
349 rc = PDMDevHlpMmioCreateAndMap(pDevIns, pThis->GCPhys32Rcba, 0x4000, lpcMmioWrite, lpcMmioRead,
350 IOMMMIO_FLAGS_READ_DWORD | IOMMMIO_FLAGS_WRITE_PASSTHRU,
351 "LPC Memory", &pThis->hMmio);
352 AssertRCReturn(rc, rc);
353
354
355 /*
356 * Debug info and stats.
357 */
358 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMmioReads, STAMTYPE_COUNTER, "MMIOReads", STAMUNIT_OCCURENCES, "MMIO reads");
359 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMmioWrites, STAMTYPE_COUNTER, "MMIOWrites", STAMUNIT_OCCURENCES, "MMIO writes");
360 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatPciCfgReads, STAMTYPE_COUNTER, "ConfigReads", STAMUNIT_OCCURENCES, "PCI config reads");
361 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatPciCfgWrites, STAMTYPE_COUNTER, "ConfigWrites", STAMUNIT_OCCURENCES, "PCI config writes");
362
363 PDMDevHlpDBGFInfoRegister(pDevIns, "lpc", "Display LPC status. (no arguments)", lpcInfo);
364
365 return VINF_SUCCESS;
366}
367
368#endif /* IN_RING3 */
369
370/**
371 * The device registration structure.
372 */
373const PDMDEVREG g_DeviceLPC =
374{
375 /* .u32Version = */ PDM_DEVREG_VERSION,
376 /* .uReserved0 = */ 0,
377 /* .szName = */ "lpc",
378 /* .fFlags = */ PDM_DEVREG_FLAGS_DEFAULT_BITS | PDM_DEVREG_FLAGS_NEW_STYLE,
379 /* .fClass = */ PDM_DEVREG_CLASS_MISC,
380 /* .cMaxInstances = */ 1,
381 /* .uSharedVersion = */ 42,
382 /* .cbInstanceShared = */ sizeof(LPCSTATE),
383 /* .cbInstanceCC = */ 0,
384 /* .cbInstanceRC = */ 0,
385 /* .cMaxPciDevices = */ 1,
386 /* .cMaxMsixVectors = */ 0,
387 /* .pszDescription = */ "Low Pin Count (LPC) Bus",
388#if defined(IN_RING3)
389 /* .pszRCMod = */ "",
390 /* .pszR0Mod = */ "",
391 /* .pfnConstruct = */ lpcConstruct,
392 /* .pfnDestruct = */ NULL,
393 /* .pfnRelocate = */ NULL,
394 /* .pfnMemSetup = */ NULL,
395 /* .pfnPowerOn = */ NULL,
396 /* .pfnReset = */ NULL,
397 /* .pfnSuspend = */ NULL,
398 /* .pfnResume = */ NULL,
399 /* .pfnAttach = */ NULL,
400 /* .pfnDetach = */ NULL,
401 /* .pfnQueryInterface = */ NULL,
402 /* .pfnInitComplete = */ NULL,
403 /* .pfnPowerOff = */ NULL,
404 /* .pfnSoftReset = */ NULL,
405 /* .pfnReserved0 = */ NULL,
406 /* .pfnReserved1 = */ NULL,
407 /* .pfnReserved2 = */ NULL,
408 /* .pfnReserved3 = */ NULL,
409 /* .pfnReserved4 = */ NULL,
410 /* .pfnReserved5 = */ NULL,
411 /* .pfnReserved6 = */ NULL,
412 /* .pfnReserved7 = */ NULL,
413#elif defined(IN_RING0)
414 /* .pfnEarlyConstruct = */ NULL,
415 /* .pfnConstruct = */ NULL,
416 /* .pfnDestruct = */ NULL,
417 /* .pfnFinalDestruct = */ NULL,
418 /* .pfnRequest = */ NULL,
419 /* .pfnReserved0 = */ NULL,
420 /* .pfnReserved1 = */ NULL,
421 /* .pfnReserved2 = */ NULL,
422 /* .pfnReserved3 = */ NULL,
423 /* .pfnReserved4 = */ NULL,
424 /* .pfnReserved5 = */ NULL,
425 /* .pfnReserved6 = */ NULL,
426 /* .pfnReserved7 = */ NULL,
427#elif defined(IN_RC)
428 /* .pfnConstruct = */ NULL,
429 /* .pfnReserved0 = */ NULL,
430 /* .pfnReserved1 = */ NULL,
431 /* .pfnReserved2 = */ NULL,
432 /* .pfnReserved3 = */ NULL,
433 /* .pfnReserved4 = */ NULL,
434 /* .pfnReserved5 = */ NULL,
435 /* .pfnReserved6 = */ NULL,
436 /* .pfnReserved7 = */ NULL,
437#else
438# error "Not in IN_RING3, IN_RING0 or IN_RC!"
439#endif
440 /* .u32VersionEnd = */ PDM_DEVREG_VERSION
441};
442
443#endif /* VBOX_DEVICE_STRUCT_TESTCASE */
444
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