VirtualBox

source: vbox/trunk/src/VBox/Devices/PC/DevLpc-new.cpp@ 80986

Last change on this file since 80986 was 80943, checked in by vboxsync, 5 years ago

Devices/PCI: Device model refactoring, part I. bugref:9218
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1/* $Id: DevLpc-new.cpp 80943 2019-09-23 09:36:14Z vboxsync $ */
2/** @file
3 * DevLPC - Minimal ICH9 LPC device emulation.
4 */
5
6/*
7 * Copyright (C) 2018-2019 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18
19/*********************************************************************************************************************************
20* Header Files *
21*********************************************************************************************************************************/
22#define LOG_GROUP LOG_GROUP_DEV_LPC
23#include <VBox/vmm/pdmdev.h>
24#include <VBox/vmm/stam.h>
25#include <VBox/log.h>
26
27#include <iprt/assert.h>
28#include <iprt/string.h>
29
30#include "VBoxDD.h"
31
32
33/*********************************************************************************************************************************
34* Defined Constants And Macros *
35*********************************************************************************************************************************/
36#define LPC_REG_HPET_CONFIG_POINTER 0x3404
37#define LPC_REG_GCS 0x3410
38
39
40/*********************************************************************************************************************************
41* Structures and Typedefs *
42*********************************************************************************************************************************/
43/**
44 * The ICH9 LPC state.
45 */
46typedef struct LPCSTATE
47{
48 /** The PCI device. */
49 PDMPCIDEV PciDev;
50 /** Pointer to the ring-3 device instance. */
51 PPDMDEVINSR3 pDevInsR3;
52
53 /** The root complex base address. */
54 RTGCPHYS32 GCPhys32Rcba;
55 /** Set if R0/RC context is enabled. */
56 bool fRZEnabled;
57 /** The ICH version (7 or 9). */
58 uint8_t uIchVersion;
59 /** Explicit padding. */
60 uint8_t abPadding[HC_ARCH_BITS == 32 ? 2 : 6];
61
62 /** Number of MMIO reads. */
63 STAMCOUNTER StatMmioReads;
64 /** Number of MMIO writes. */
65 STAMCOUNTER StatMmioWrites;
66 /** Number of PCI config space reads. */
67 STAMCOUNTER StatPciCfgReads;
68 /** Number of PCI config space writes. */
69 STAMCOUNTER StatPciCfgWrites;
70} LPCSTATE;
71/** Pointer to the LPC state. */
72typedef LPCSTATE *PLPCSTATE;
73
74
75#ifndef VBOX_DEVICE_STRUCT_TESTCASE
76
77/**
78 * @callback_method_impl{FNIOMMMIOREAD}
79 */
80PDMBOTHCBDECL(int) lpcMmioRead(PPDMDEVINS pDevIns, void *pvUser, RTGCPHYS GCPhysAddr, void *pv, unsigned cb)
81{
82 RT_NOREF(pvUser, cb);
83 PLPCSTATE pThis = PDMINS_2_DATA(pDevIns, PLPCSTATE);
84 RTGCPHYS32 const offReg = (RTGCPHYS32)GCPhysAddr - pThis->GCPhys32Rcba;
85 Assert(cb == 4); Assert(!(GCPhysAddr & 3)); /* IOMMMIO_FLAGS_READ_DWORD should make sure of this */
86
87 uint32_t *puValue = (uint32_t *)pv;
88 if (offReg == LPC_REG_HPET_CONFIG_POINTER)
89 {
90 *puValue = 0xf0;
91 Log(("lpcMmioRead: HPET_CONFIG_POINTER: %#x\n", *puValue));
92 }
93 else if (offReg == LPC_REG_GCS)
94 {
95 *puValue = 0;
96 Log(("lpcMmioRead: GCS: %#x\n", *puValue));
97 }
98 else
99 {
100 *puValue = 0;
101 Log(("lpcMmioRead: WARNING! Unknown register %#x!\n", offReg));
102 }
103
104 STAM_REL_COUNTER_INC(&pThis->StatMmioReads);
105 return VINF_SUCCESS;
106}
107
108
109/**
110 * @callback_method_impl{FNIOMMMIOWRITE}
111 */
112PDMBOTHCBDECL(int) lpcMmioWrite(PPDMDEVINS pDevIns, void *pvUser, RTGCPHYS GCPhysAddr, void const *pv, unsigned cb)
113{
114 RT_NOREF(pvUser, pv);
115 PLPCSTATE pThis = PDMINS_2_DATA(pDevIns, PLPCSTATE);
116 RTGCPHYS32 const offReg = (RTGCPHYS32)GCPhysAddr - pThis->GCPhys32Rcba;
117
118 if (cb == 4)
119 {
120 if (offReg == LPC_REG_GCS)
121 Log(("lpcMmioWrite: Ignorning write to GCS: %.*Rhxs\n", cb, pv));
122 else
123 Log(("lpcMmioWrite: Ignorning write to unknown register %#x: %.*Rhxs\n", offReg, cb, pv));
124 }
125 else
126 Log(("lpcMmioWrite: WARNING! Ignoring non-DWORD write to offReg=%#x: %.*Rhxs\n", offReg, cb, pv));
127
128 STAM_REL_COUNTER_INC(&pThis->StatMmioWrites);
129 return VINF_SUCCESS;
130}
131
132#ifdef IN_RING3
133
134/**
135 * @callback_method_impl{FNPCICONFIGREAD}
136 */
137static DECLCALLBACK(VBOXSTRICTRC) lpcR3PciConfigRead(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev,
138 uint32_t uAddress, unsigned cb, uint32_t *pu32Value)
139{
140 PLPCSTATE pThis = PDMINS_2_DATA(pDevIns, PLPCSTATE);
141 Assert(pPciDev == &pThis->PciDev);
142
143 STAM_REL_COUNTER_INC(&pThis->StatPciCfgReads);
144 VBOXSTRICTRC rcStrict = PDMDevHlpPCIConfigRead(pDevIns, pPciDev, uAddress, cb, pu32Value);
145 switch (cb)
146 {
147 case 1: Log(("lpcR3PciConfigRead: %#04x -> %#04x (%Rrc)\n", uAddress, *pu32Value, VBOXSTRICTRC_VAL(rcStrict))); break;
148 case 2: Log(("lpcR3PciConfigRead: %#04x -> %#06x (%Rrc)\n", uAddress, *pu32Value, VBOXSTRICTRC_VAL(rcStrict))); break;
149 case 4: Log(("lpcR3PciConfigRead: %#04x -> %#010x (%Rrc)\n", uAddress, *pu32Value, VBOXSTRICTRC_VAL(rcStrict))); break;
150 }
151 return rcStrict;
152}
153
154
155/**
156 * @callback_method_impl{FNPCICONFIGWRITE}
157 */
158static DECLCALLBACK(VBOXSTRICTRC) lpcR3PciConfigWrite(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev,
159 uint32_t uAddress, unsigned cb, uint32_t u32Value)
160{
161 PLPCSTATE pThis = PDMINS_2_DATA(pDevIns, PLPCSTATE);
162 Assert(pPciDev == &pThis->PciDev);
163
164 STAM_REL_COUNTER_INC(&pThis->StatPciCfgWrites);
165 switch (cb)
166 {
167 case 1: Log(("lpcR3PciConfigWrite: %#04x <- %#04x\n", uAddress, u32Value)); break;
168 case 2: Log(("lpcR3PciConfigWrite: %#04x <- %#06x\n", uAddress, u32Value)); break;
169 case 4: Log(("lpcR3PciConfigWrite: %#04x <- %#010x\n", uAddress, u32Value)); break;
170 }
171
172 return PDMDevHlpPCIConfigWrite(pDevIns, pPciDev, uAddress, cb, u32Value);
173}
174
175
176/**
177 * Info handler, device version.
178 *
179 * @param pDevIns Device instance which registered the info.
180 * @param pHlp Callback functions for doing output.
181 * @param pszArgs Argument string. Optional and specific to the handler.
182 */
183static DECLCALLBACK(void) lpcInfo(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
184{
185 PLPCSTATE pThis = PDMINS_2_DATA(pDevIns, PLPCSTATE);
186 RT_NOREF(pszArgs);
187
188 if (pThis->uIchVersion == 7)
189 {
190 uint8_t b1 = PDMPciDevGetByte(&pThis->PciDev, 0xde);
191 uint8_t b2 = PDMPciDevGetByte(&pThis->PciDev, 0xad);
192 if ( b1 == 0xbe
193 && b2 == 0xef)
194 pHlp->pfnPrintf(pHlp, "APIC backdoor activated\n");
195 else
196 pHlp->pfnPrintf(pHlp, "APIC backdoor closed: %02x %02x\n", b1, b2);
197 }
198
199 for (unsigned iLine = 0; iLine < 8; iLine++)
200 {
201 unsigned offBase = iLine < 4 ? 0x60 : 0x68 - 4;
202 uint8_t bMap = PDMPciDevGetByte(&pThis->PciDev, offBase + iLine);
203 if (bMap & 0x80)
204 pHlp->pfnPrintf(pHlp, "PIRQ%c_ROUT disabled\n", 'A' + iLine);
205 else
206 pHlp->pfnPrintf(pHlp, "PIRQ%c_ROUT -> IRQ%d\n", 'A' + iLine, bMap & 0xf);
207 }
208}
209
210
211/**
212 * @interface_method_impl{PDMDEVREG,pfnConstruct}
213 */
214static DECLCALLBACK(int) lpcConstruct(PPDMDEVINS pDevIns, int iInstance, PCFGMNODE pCfg)
215{
216 PDMDEV_CHECK_VERSIONS_RETURN(pDevIns);
217 PLPCSTATE pThis = PDMINS_2_DATA(pDevIns, PLPCSTATE);
218 Assert(iInstance == 0); RT_NOREF(iInstance);
219
220 /*
221 * Initialize state.
222 */
223 pThis->pDevInsR3 = pDevIns;
224
225 /*
226 * Read configuration.
227 */
228 PDMDEV_VALIDATE_CONFIG_RETURN(pDevIns, "RZEnabled|RCBA|ICHVersion", "");
229
230 int rc = CFGMR3QueryBoolDef(pCfg, "RZEnabled", &pThis->fRZEnabled, true);
231 if (RT_FAILURE(rc))
232 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to query boolean value \"RZEnabled\""));
233
234 rc = CFGMR3QueryU8Def(pCfg, "ICHVersion", &pThis->uIchVersion, 7 /** @todo 9 */);
235 if (RT_FAILURE(rc))
236 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to query boolean value \"ICHVersion\""));
237 if ( pThis->uIchVersion != 7
238 && pThis->uIchVersion != 9)
239 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Invalid \"ICHVersion\" value (must be 7 or 9)"));
240
241 rc = CFGMR3QueryU32Def(pCfg, "RCBA", &pThis->GCPhys32Rcba, UINT32_C(0xfed1c000));
242 if (RT_FAILURE(rc))
243 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to query boolean value \"RCBA\""));
244
245
246 /*
247 * Register the PCI device.
248 *
249 * See sections 13.1 (page 371) and section 13.8.1 (page 429) in the ICH9
250 * specification.
251 *
252 * We set these up so they don't need much/any configuration from the
253 * guest. This is quite possibly wrong, but at the moment we just need to
254 * have this device working w/o lots of firmware fun.
255 */
256 PDMPciDevSetVendorId( &pThis->PciDev, 0x8086); /* Intel */
257 if (pThis->uIchVersion == 7)
258 PDMPciDevSetDeviceId( &pThis->PciDev, 0x27b9);
259 else if (pThis->uIchVersion == 9)
260 PDMPciDevSetDeviceId( &pThis->PciDev, 0x2918); /** @todo unsure if 0x2918 is the right PCI ID... */
261 else
262 AssertFailedReturn(VERR_INTERNAL_ERROR_3);
263 PDMPciDevSetCommand( &pThis->PciDev, PCI_COMMAND_IOACCESS | PCI_COMMAND_MEMACCESS | PCI_COMMAND_BUSMASTER);
264 PDMPciDevSetStatus( &pThis->PciDev, 0x0210); /* Note! Used to be 0x0200 for ICH7. */
265 PDMPciDevSetRevisionId( &pThis->PciDev, 0x02);
266 PDMPciDevSetClassSub( &pThis->PciDev, 0x01); /* PCI-to-ISA bridge */
267 PDMPciDevSetClassBase( &pThis->PciDev, 0x06); /* bridge */
268 PDMPciDevSetHeaderType( &pThis->PciDev, 0x80); /* Normal, multifunction device (so that other devices can be its functions) */
269 if (pThis->uIchVersion == 7)
270 {
271 PDMPciDevSetSubSystemVendorId(&pThis->PciDev, 0x8086);
272 PDMPciDevSetSubSystemId( &pThis->PciDev, 0x7270);
273 }
274 else if (pThis->uIchVersion == 9)
275 {
276 PDMPciDevSetSubSystemVendorId(&pThis->PciDev, 0x0000); /** @todo docs stays subsystem IDs are zero, check real HW */
277 PDMPciDevSetSubSystemId( &pThis->PciDev, 0x0000);
278 }
279 PDMPciDevSetInterruptPin( &pThis->PciDev, 0x00); /* The LPC device itself generates no interrupts */
280 PDMPciDevSetDWord( &pThis->PciDev, 0x40, 0x00008001); /* PMBASE: ACPI base address; (PM_PORT_BASE (?) * 2 | PCI_ADDRESS_SPACE_IO) */
281 PDMPciDevSetByte( &pThis->PciDev, 0x44, 0x80); /* ACPI_CNTL: SCI is IRQ9, ACPI enabled */ /** @todo documented as defaulting to 0x00. */
282 PDMPciDevSetDWord( &pThis->PciDev, 0x48, 0x00000001); /* GPIOBASE (note: used to be zero) */
283 PDMPciDevSetByte( &pThis->PciDev, 0x4c, 0x4d); /* GC - GPIO control: ??? */ /** @todo documented as defaulting to 0x00. */
284 if (pThis->uIchVersion == 7)
285 PDMPciDevSetByte(&pThis->PciDev, 0x4e, 0x03); /* ??? */
286 PDMPciDevSetByte( &pThis->PciDev, 0x60, 0x0b); /* PIRQA_ROUT: PCI A -> IRQ 11 (documented default is 0x80) */
287 PDMPciDevSetByte( &pThis->PciDev, 0x61, 0x09); /* PIRQB_ROUT: PCI B -> IRQ 9 (documented default is 0x80) */
288 PDMPciDevSetByte( &pThis->PciDev, 0x62, 0x0b); /* PIRQC_ROUT: PCI C -> IRQ 11 (documented default is 0x80) */
289 PDMPciDevSetByte( &pThis->PciDev, 0x63, 0x09); /* PIRQD_ROUT: PCI D -> IRQ 9 (documented default is 0x80) */
290 PDMPciDevSetByte( &pThis->PciDev, 0x64, 0x10); /* SIRQ_CNTL: Serial IRQ Control 10h R/W, RO */
291 PDMPciDevSetByte( &pThis->PciDev, 0x68, 0x80); /* PIRQE_ROUT */
292 PDMPciDevSetByte( &pThis->PciDev, 0x69, 0x80); /* PIRQF_ROUT */
293 PDMPciDevSetByte( &pThis->PciDev, 0x6a, 0x80); /* PIRQG_ROUT */
294 PDMPciDevSetByte( &pThis->PciDev, 0x6b, 0x80); /* PIRQH_ROUT */
295 PDMPciDevSetWord( &pThis->PciDev, 0x6c, 0x00f8); /* IPC_IBDF: IOxAPIC bus:device:function. (Note! Used to be zero.) */
296 if (pThis->uIchVersion == 7)
297 {
298 /* No idea what this is/was yet: */
299 PDMPciDevSetByte( &pThis->PciDev, 0x70, 0x80);
300 PDMPciDevSetByte( &pThis->PciDev, 0x76, 0x0c);
301 PDMPciDevSetByte( &pThis->PciDev, 0x77, 0x0c);
302 PDMPciDevSetByte( &pThis->PciDev, 0x78, 0x02);
303 PDMPciDevSetByte( &pThis->PciDev, 0x79, 0x00);
304 }
305 PDMPciDevSetWord( &pThis->PciDev, 0x80, 0x0000); /* LPC_I/O_DEC: I/O decode ranges. */
306 PDMPciDevSetWord( &pThis->PciDev, 0x82, 0x0000); /* LPC_EN: LPC I/F enables. */
307 PDMPciDevSetDWord( &pThis->PciDev, 0x84, 0x00000000); /* GEN1_DEC: LPC I/F generic decode range 1. */
308 PDMPciDevSetDWord( &pThis->PciDev, 0x88, 0x00000000); /* GEN2_DEC: LPC I/F generic decode range 2. */
309 PDMPciDevSetDWord( &pThis->PciDev, 0x8c, 0x00000000); /* GEN3_DEC: LPC I/F generic decode range 3. */
310 PDMPciDevSetDWord( &pThis->PciDev, 0x90, 0x00000000); /* GEN4_DEC: LPC I/F generic decode range 4. */
311
312 PDMPciDevSetWord( &pThis->PciDev, 0xa0, 0x0008); /* GEN_PMCON_1: Documented default is 0x0000 */
313 PDMPciDevSetByte( &pThis->PciDev, 0xa2, 0x00); /* GEN_PMON_2: */
314 PDMPciDevSetByte( &pThis->PciDev, 0xa4, 0x00); /* GEN_PMON_3: */
315 PDMPciDevSetByte( &pThis->PciDev, 0xa6, 0x00); /* GEN_PMON_LOCK: Configuration lock. */
316 if (pThis->uIchVersion == 7)
317 PDMPciDevSetByte(&pThis->PciDev, 0xa8, 0x0f); /* Is this part of GEN_PMON_LOCK? */
318 PDMPciDevSetByte( &pThis->PciDev, 0xab, 0x00); /* BM_BREAK_EN */
319 PDMPciDevSetDWord( &pThis->PciDev, 0xac, 0x00000000); /* PMIR: Power */
320 PDMPciDevSetDWord( &pThis->PciDev, 0xb8, 0x00000000); /* GPI_ROUT: GPI Route Control */
321 if (pThis->uIchVersion == 9)
322 {
323 /** @todo the next two values looks bogus. */
324 PDMPciDevSetDWord(&pThis->PciDev, 0xd0, 0x00112233); /* FWH_SEL1: Firmware Hub Select 1 */
325 PDMPciDevSetWord( &pThis->PciDev, 0xd4, 0x4567); /* FWH_SEL2: Firmware Hub Select 2 */
326 PDMPciDevSetWord( &pThis->PciDev, 0xd8, 0xffcf); /* FWH_DEC_EN1: Firmware Hub Decode Enable 1 */
327 PDMPciDevSetByte( &pThis->PciDev, 0xdc, 0x00); /* BIOS_CNTL: BIOS control */
328 PDMPciDevSetWord( &pThis->PciDev, 0xe0, 0x0009); /* FDCAP: Feature Detection Capability ID */
329 PDMPciDevSetByte( &pThis->PciDev, 0xe2, 0x0c); /* FDLEN: Feature Detection Capability Length */
330 PDMPciDevSetByte( &pThis->PciDev, 0xe3, 0x10); /* FDVER: Feature Detection Version */
331 PDMPciDevSetByte( &pThis->PciDev, 0xe4, 0x20); /* FDVCT[0]: 5=SATA RAID 0/1/5/10 capability (1=disabled) */
332 PDMPciDevSetByte( &pThis->PciDev, 0xe5, 0x00); /* FDVCT[1]: */
333 PDMPciDevSetByte( &pThis->PciDev, 0xe6, 0x00); /* FDVCT[2]: */
334 PDMPciDevSetByte( &pThis->PciDev, 0xe7, 0x00); /* FDVCT[3]: */
335 PDMPciDevSetByte( &pThis->PciDev, 0xe8, 0xc0); /* FDVCT[4]: 6-7=Intel active magament technology capability (11=disabled). */
336 PDMPciDevSetByte( &pThis->PciDev, 0xe9, 0x00); /* FDVCT[5]: */
337 PDMPciDevSetByte( &pThis->PciDev, 0xea, 0x00); /* FDVCT[6]: */
338 PDMPciDevSetByte( &pThis->PciDev, 0xeb, 0x00); /* FDVCT[7]: */
339 PDMPciDevSetByte( &pThis->PciDev, 0xec, 0x00); /* FDVCT[8]: */
340 PDMPciDevSetByte( &pThis->PciDev, 0xed, 0x00); /* FDVCT[9]: */
341 PDMPciDevSetByte( &pThis->PciDev, 0xee, 0x00); /* FDVCT[a]: */
342 PDMPciDevSetByte( &pThis->PciDev, 0xef, 0x00); /* FDVCT[b]: */
343 }
344
345 /* RCBA: Root complex base address (documented default is 0x00000000). Bit 0 is enable bit. */
346 Assert(!(pThis->GCPhys32Rcba & 0x3fff)); /* 16KB aligned */
347 PDMPciDevSetDWord(&pThis->PciDev, 0xf0, pThis->GCPhys32Rcba | 1);
348
349 rc = PDMDevHlpPCIRegisterEx(pDevIns, &pThis->PciDev, PDMPCIDEVREG_CFG_PRIMARY, PDMPCIDEVREG_F_NOT_MANDATORY_NO,
350 31 /*uPciDevNo*/, 0 /*uPciFunNo*/, "lpc");
351 AssertRCReturn(rc, rc);
352 rc = PDMDevHlpPCIInterceptConfigAccesses(pDevIns, &pThis->PciDev, lpcR3PciConfigRead, lpcR3PciConfigWrite);
353 AssertRCReturn(rc, rc);
354
355 /*
356 * Register the MMIO regions.
357 */
358 /** @todo This should actually be done when RCBA is enabled, but was
359 * mentioned above we just want this working. */
360 rc = PDMDevHlpMMIORegister(pDevIns, pThis->GCPhys32Rcba, 0x4000, pThis,
361 IOMMMIO_FLAGS_READ_DWORD | IOMMMIO_FLAGS_WRITE_PASSTHRU,
362 lpcMmioWrite, lpcMmioRead, "LPC Memory");
363 AssertRCReturn(rc, rc);
364
365
366 /*
367 * Debug info and stats.
368 */
369 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMmioReads, STAMTYPE_COUNTER, "/Devices/LPC/MMIOReads", STAMUNIT_OCCURENCES, "MMIO reads");
370 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMmioWrites, STAMTYPE_COUNTER, "/Devices/LPC/MMIOWrites", STAMUNIT_OCCURENCES, "MMIO writes");
371 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatPciCfgReads, STAMTYPE_COUNTER, "/Devices/LPC/ConfigReads", STAMUNIT_OCCURENCES, "PCI config reads");
372 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatPciCfgWrites, STAMTYPE_COUNTER, "/Devices/LPC/ConfigWrites", STAMUNIT_OCCURENCES, "PCI config writes");
373
374 PDMDevHlpDBGFInfoRegister(pDevIns, "lpc", "Display LPC status. (no arguments)", lpcInfo);
375
376 return VINF_SUCCESS;
377}
378
379#endif /* IN_RING3 */
380
381/**
382 * The device registration structure.
383 */
384const PDMDEVREG g_DeviceLPC =
385{
386 /* .u32Version = */ PDM_DEVREG_VERSION,
387 /* .uReserved0 = */ 0,
388 /* .szName = */ "lpc",
389 /* .fFlags = */ PDM_DEVREG_FLAGS_DEFAULT_BITS,
390 /* .fClass = */ PDM_DEVREG_CLASS_MISC,
391 /* .cMaxInstances = */ 1,
392 /* .uSharedVersion = */ 42,
393 /* .cbInstanceShared = */ sizeof(LPCSTATE),
394 /* .cbInstanceCC = */ 0,
395 /* .cbInstanceRC = */ 0,
396 /* .cMaxPciDevices = */ 1,
397 /* .cMaxMsixVectors = */ 0,
398 /* .pszDescription = */ "Low Pin Count (LPC) Bus",
399#if defined(IN_RING3)
400 /* .pszRCMod = */ "",
401 /* .pszR0Mod = */ "",
402 /* .pfnConstruct = */ lpcConstruct,
403 /* .pfnDestruct = */ NULL,
404 /* .pfnRelocate = */ NULL,
405 /* .pfnMemSetup = */ NULL,
406 /* .pfnPowerOn = */ NULL,
407 /* .pfnReset = */ NULL,
408 /* .pfnSuspend = */ NULL,
409 /* .pfnResume = */ NULL,
410 /* .pfnAttach = */ NULL,
411 /* .pfnDetach = */ NULL,
412 /* .pfnQueryInterface = */ NULL,
413 /* .pfnInitComplete = */ NULL,
414 /* .pfnPowerOff = */ NULL,
415 /* .pfnSoftReset = */ NULL,
416 /* .pfnReserved0 = */ NULL,
417 /* .pfnReserved1 = */ NULL,
418 /* .pfnReserved2 = */ NULL,
419 /* .pfnReserved3 = */ NULL,
420 /* .pfnReserved4 = */ NULL,
421 /* .pfnReserved5 = */ NULL,
422 /* .pfnReserved6 = */ NULL,
423 /* .pfnReserved7 = */ NULL,
424#elif defined(IN_RING0)
425 /* .pfnEarlyConstruct = */ NULL,
426 /* .pfnConstruct = */ NULL,
427 /* .pfnDestruct = */ NULL,
428 /* .pfnFinalDestruct = */ NULL,
429 /* .pfnRequest = */ NULL,
430 /* .pfnReserved0 = */ NULL,
431 /* .pfnReserved1 = */ NULL,
432 /* .pfnReserved2 = */ NULL,
433 /* .pfnReserved3 = */ NULL,
434 /* .pfnReserved4 = */ NULL,
435 /* .pfnReserved5 = */ NULL,
436 /* .pfnReserved6 = */ NULL,
437 /* .pfnReserved7 = */ NULL,
438#elif defined(IN_RC)
439 /* .pfnConstruct = */ NULL,
440 /* .pfnReserved0 = */ NULL,
441 /* .pfnReserved1 = */ NULL,
442 /* .pfnReserved2 = */ NULL,
443 /* .pfnReserved3 = */ NULL,
444 /* .pfnReserved4 = */ NULL,
445 /* .pfnReserved5 = */ NULL,
446 /* .pfnReserved6 = */ NULL,
447 /* .pfnReserved7 = */ NULL,
448#else
449# error "Not in IN_RING3, IN_RING0 or IN_RC!"
450#endif
451 /* .u32VersionEnd = */ PDM_DEVREG_VERSION
452};
453
454#endif /* VBOX_DEVICE_STRUCT_TESTCASE */
455
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