VirtualBox

source: vbox/trunk/src/VBox/Devices/PC/DevLpc-new.cpp@ 75229

Last change on this file since 75229 was 71831, checked in by vboxsync, 7 years ago

DevLPC-new: Build fix. bugref:7000
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1/* $Id: DevLpc-new.cpp 71831 2018-04-11 17:23:35Z vboxsync $ */
2/** @file
3 * DevLPC - Minimal ICH9 LPC device emulation.
4 */
5
6/*
7 * Copyright (C) 2018 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18
19/*********************************************************************************************************************************
20* Header Files *
21*********************************************************************************************************************************/
22#define LOG_GROUP LOG_GROUP_DEV_LPC
23#include <VBox/vmm/pdmdev.h>
24#include <VBox/vmm/stam.h>
25#include <VBox/log.h>
26
27#include <iprt/assert.h>
28#include <iprt/string.h>
29
30#include "VBoxDD.h"
31
32
33/*********************************************************************************************************************************
34* Defined Constants And Macros *
35*********************************************************************************************************************************/
36#define LPC_REG_HPET_CONFIG_POINTER 0x3404
37#define LPC_REG_GCS 0x3410
38
39
40/*********************************************************************************************************************************
41* Structures and Typedefs *
42*********************************************************************************************************************************/
43/**
44 * The ICH9 LPC state.
45 */
46typedef struct LPCSTATE
47{
48 /** The PCI device. */
49 PDMPCIDEV PciDev;
50 /** Pointer to the ring-3 device instance. */
51 PPDMDEVINSR3 pDevInsR3;
52
53 /** The root complex base address. */
54 RTGCPHYS32 GCPhys32Rcba;
55 /** Set if R0/RC context is enabled. */
56 bool fRZEnabled;
57 /** The ICH version (7 or 9). */
58 uint8_t uIchVersion;
59 /** Explicit padding. */
60 uint8_t abPadding[HC_ARCH_BITS == 32 ? 2 : 6];
61
62 /** Pointer to generic PCI config reader. */
63 R3PTRTYPE(PFNPCICONFIGREAD) pfnPciConfigReadFallback;
64 /** Pointer to generic PCI config write. */
65 R3PTRTYPE(PFNPCICONFIGWRITE) pfnPciConfigWriteFallback;
66
67 /** Number of MMIO reads. */
68 STAMCOUNTER StatMmioReads;
69 /** Number of MMIO writes. */
70 STAMCOUNTER StatMmioWrites;
71 /** Number of PCI config space reads. */
72 STAMCOUNTER StatPciCfgReads;
73 /** Number of PCI config space writes. */
74 STAMCOUNTER StatPciCfgWrites;
75} LPCSTATE;
76/** Pointer to the LPC state. */
77typedef LPCSTATE *PLPCSTATE;
78
79
80#ifndef VBOX_DEVICE_STRUCT_TESTCASE
81
82/**
83 * @callback_method_impl{FNIOMMMIOREAD}
84 */
85PDMBOTHCBDECL(int) lpcMmioRead(PPDMDEVINS pDevIns, void *pvUser, RTGCPHYS GCPhysAddr, void *pv, unsigned cb)
86{
87 RT_NOREF(pvUser, cb);
88 PLPCSTATE pThis = PDMINS_2_DATA(pDevIns, PLPCSTATE);
89 RTGCPHYS32 const offReg = (RTGCPHYS32)GCPhysAddr - pThis->GCPhys32Rcba;
90 Assert(cb == 4); Assert(!(GCPhysAddr & 3)); /* IOMMMIO_FLAGS_READ_DWORD should make sure of this */
91
92 uint32_t *puValue = (uint32_t *)pv;
93 if (offReg == LPC_REG_HPET_CONFIG_POINTER)
94 {
95 *puValue = 0xf0;
96 Log(("lpcMmioRead: HPET_CONFIG_POINTER: %#x\n", *puValue));
97 }
98 else if (offReg == LPC_REG_GCS)
99 {
100 *puValue = 0;
101 Log(("lpcMmioRead: GCS: %#x\n", *puValue));
102 }
103 else
104 {
105 *puValue = 0;
106 Log(("lpcMmioRead: WARNING! Unknown register %#x!\n", offReg));
107 }
108
109 STAM_REL_COUNTER_INC(&pThis->StatMmioReads);
110 return VINF_SUCCESS;
111}
112
113
114/**
115 * @callback_method_impl{FNIOMMMIOWRITE}
116 */
117PDMBOTHCBDECL(int) lpcMmioWrite(PPDMDEVINS pDevIns, void *pvUser, RTGCPHYS GCPhysAddr, void const *pv, unsigned cb)
118{
119 RT_NOREF(pvUser, pv);
120 PLPCSTATE pThis = PDMINS_2_DATA(pDevIns, PLPCSTATE);
121 RTGCPHYS32 const offReg = (RTGCPHYS32)GCPhysAddr - pThis->GCPhys32Rcba;
122
123 if (cb == 4)
124 {
125 if (offReg == LPC_REG_GCS)
126 Log(("lpcMmioWrite: Ignorning write to GCS: %.*Rhxs\n", cb, pv));
127 else
128 Log(("lpcMmioWrite: Ignorning write to unknown register %#x: %.*Rhxs\n", offReg, cb, pv));
129 }
130 else
131 Log(("lpcMmioWrite: WARNING! Ignoring non-DWORD write to offReg=%#x: %.*Rhxs\n", offReg, cb, pv));
132
133 STAM_REL_COUNTER_INC(&pThis->StatMmioWrites);
134 return VINF_SUCCESS;
135}
136
137#ifdef IN_RING3
138
139/**
140 * @callback_method_impl{FNPCICONFIGREAD}
141 */
142static DECLCALLBACK(uint32_t) lpcPciConfigRead(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t uAddress, unsigned cb)
143{
144 PLPCSTATE pThis = PDMINS_2_DATA(pDevIns, PLPCSTATE);
145 Assert(pPciDev == &pThis->PciDev);
146
147 STAM_REL_COUNTER_INC(&pThis->StatPciCfgReads);
148 uint32_t uValue = pThis->pfnPciConfigReadFallback(pDevIns, pPciDev, uAddress, cb);
149 switch (cb)
150 {
151 case 1: Log(("lpcPciConfigRead: %#04x -> %#04x\n", uAddress, uValue)); break;
152 case 2: Log(("lpcPciConfigRead: %#04x -> %#06x\n", uAddress, uValue)); break;
153 case 4: Log(("lpcPciConfigRead: %#04x -> %#010x\n", uAddress, uValue)); break;
154 }
155 return uValue;
156}
157
158
159/**
160 * @callback_method_impl{FNPCICONFIGWRITE}
161 */
162static DECLCALLBACK(VBOXSTRICTRC)
163lpcPciConfigWrite(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t uAddress, uint32_t u32Value, unsigned cb)
164{
165 PLPCSTATE pThis = PDMINS_2_DATA(pDevIns, PLPCSTATE);
166 Assert(pPciDev == &pThis->PciDev);
167
168 STAM_REL_COUNTER_INC(&pThis->StatPciCfgWrites);
169 switch (cb)
170 {
171 case 1: Log(("lpcPciConfigWrite: %#04x <- %#04x\n", uAddress, u32Value)); break;
172 case 2: Log(("lpcPciConfigWrite: %#04x <- %#06x\n", uAddress, u32Value)); break;
173 case 4: Log(("lpcPciConfigWrite: %#04x <- %#010x\n", uAddress, u32Value)); break;
174 }
175
176 return pThis->pfnPciConfigWriteFallback(pDevIns, pPciDev, uAddress, u32Value, cb);
177}
178
179
180/**
181 * Info handler, device version.
182 *
183 * @param pDevIns Device instance which registered the info.
184 * @param pHlp Callback functions for doing output.
185 * @param pszArgs Argument string. Optional and specific to the handler.
186 */
187static DECLCALLBACK(void) lpcInfo(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
188{
189 PLPCSTATE pThis = PDMINS_2_DATA(pDevIns, PLPCSTATE);
190 RT_NOREF(pszArgs);
191
192 if (pThis->uIchVersion == 7)
193 {
194 uint8_t b1 = PDMPciDevGetByte(&pThis->PciDev, 0xde);
195 uint8_t b2 = PDMPciDevGetByte(&pThis->PciDev, 0xad);
196 if ( b1 == 0xbe
197 && b2 == 0xef)
198 pHlp->pfnPrintf(pHlp, "APIC backdoor activated\n");
199 else
200 pHlp->pfnPrintf(pHlp, "APIC backdoor closed: %02x %02x\n", b1, b2);
201 }
202
203 for (unsigned iLine = 0; iLine < 8; iLine++)
204 {
205 unsigned offBase = iLine < 4 ? 0x60 : 0x68 - 4;
206 uint8_t bMap = PDMPciDevGetByte(&pThis->PciDev, offBase + iLine);
207 if (bMap & 0x80)
208 pHlp->pfnPrintf(pHlp, "PIRQ%c_ROUT disabled\n", 'A' + iLine);
209 else
210 pHlp->pfnPrintf(pHlp, "PIRQ%c_ROUT -> IRQ%d\n", 'A' + iLine, bMap & 0xf);
211 }
212}
213
214
215/**
216 * @interface_method_impl{PDMDEVREG,pfnConstruct}
217 */
218static DECLCALLBACK(int) lpcConstruct(PPDMDEVINS pDevIns, int iInstance, PCFGMNODE pCfg)
219{
220 PDMDEV_CHECK_VERSIONS_RETURN(pDevIns);
221 PLPCSTATE pThis = PDMINS_2_DATA(pDevIns, PLPCSTATE);
222 Assert(iInstance == 0); RT_NOREF(iInstance);
223
224 /*
225 * Initialize state.
226 */
227 pThis->pDevInsR3 = pDevIns;
228
229 /*
230 * Read configuration.
231 */
232 PDMDEV_VALIDATE_CONFIG_RETURN(pDevIns, "RZEnabled|RCBA|ICHVersion", "");
233
234 int rc = CFGMR3QueryBoolDef(pCfg, "RZEnabled", &pThis->fRZEnabled, true);
235 if (RT_FAILURE(rc))
236 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to query boolean value \"RZEnabled\""));
237
238 rc = CFGMR3QueryU8Def(pCfg, "ICHVersion", &pThis->uIchVersion, 7 /** @todo 9 */);
239 if (RT_FAILURE(rc))
240 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to query boolean value \"ICHVersion\""));
241 if ( pThis->uIchVersion != 7
242 && pThis->uIchVersion != 9)
243 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Invalid \"ICHVersion\" value (must be 7 or 9)"));
244
245 rc = CFGMR3QueryU32Def(pCfg, "RCBA", &pThis->GCPhys32Rcba, UINT32_C(0xfed1c000));
246 if (RT_FAILURE(rc))
247 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to query boolean value \"RCBA\""));
248
249
250 /*
251 * Register the PCI device.
252 *
253 * See sections 13.1 (page 371) and section 13.8.1 (page 429) in the ICH9
254 * specification.
255 *
256 * We set these up so they don't need much/any configuration from the
257 * guest. This is quite possibly wrong, but at the moment we just need to
258 * have this device working w/o lots of firmware fun.
259 */
260 PDMPciDevSetVendorId( &pThis->PciDev, 0x8086); /* Intel */
261 if (pThis->uIchVersion == 7)
262 PDMPciDevSetDeviceId( &pThis->PciDev, 0x27b9);
263 else if (pThis->uIchVersion == 9)
264 PDMPciDevSetDeviceId( &pThis->PciDev, 0x2918); /** @todo unsure if 0x2918 is the right PCI ID... */
265 else
266 AssertFailedReturn(VERR_INTERNAL_ERROR_3);
267 PDMPciDevSetCommand( &pThis->PciDev, PCI_COMMAND_IOACCESS | PCI_COMMAND_MEMACCESS | PCI_COMMAND_BUSMASTER);
268 PDMPciDevSetStatus( &pThis->PciDev, 0x0210); /* Note! Used to be 0x0200 for ICH7. */
269 PDMPciDevSetRevisionId( &pThis->PciDev, 0x02);
270 PDMPciDevSetClassSub( &pThis->PciDev, 0x01); /* PCI-to-ISA bridge */
271 PDMPciDevSetClassBase( &pThis->PciDev, 0x06); /* bridge */
272 PDMPciDevSetHeaderType( &pThis->PciDev, 0x80); /* Normal, multifunction device (so that other devices can be its functions) */
273 if (pThis->uIchVersion == 7)
274 {
275 PDMPciDevSetSubSystemVendorId(&pThis->PciDev, 0x8086);
276 PDMPciDevSetSubSystemId( &pThis->PciDev, 0x7270);
277 }
278 else if (pThis->uIchVersion == 9)
279 {
280 PDMPciDevSetSubSystemVendorId(&pThis->PciDev, 0x0000); /** @todo docs stays subsystem IDs are zero, check real HW */
281 PDMPciDevSetSubSystemId( &pThis->PciDev, 0x0000);
282 }
283 PDMPciDevSetInterruptPin( &pThis->PciDev, 0x00); /* The LPC device itself generates no interrupts */
284 PDMPciDevSetDWord( &pThis->PciDev, 0x40, 0x00008001); /* PMBASE: ACPI base address; (PM_PORT_BASE (?) * 2 | PCI_ADDRESS_SPACE_IO) */
285 PDMPciDevSetByte( &pThis->PciDev, 0x44, 0x80); /* ACPI_CNTL: SCI is IRQ9, ACPI enabled */ /** @todo documented as defaulting to 0x00. */
286 PDMPciDevSetDWord( &pThis->PciDev, 0x48, 0x00000001); /* GPIOBASE (note: used to be zero) */
287 PDMPciDevSetByte( &pThis->PciDev, 0x4c, 0x4d); /* GC - GPIO control: ??? */ /** @todo documented as defaulting to 0x00. */
288 if (pThis->uIchVersion == 7)
289 PDMPciDevSetByte(&pThis->PciDev, 0x4e, 0x03); /* ??? */
290 PDMPciDevSetByte( &pThis->PciDev, 0x60, 0x0b); /* PIRQA_ROUT: PCI A -> IRQ 11 (documented default is 0x80) */
291 PDMPciDevSetByte( &pThis->PciDev, 0x61, 0x09); /* PIRQB_ROUT: PCI B -> IRQ 9 (documented default is 0x80) */
292 PDMPciDevSetByte( &pThis->PciDev, 0x62, 0x0b); /* PIRQC_ROUT: PCI C -> IRQ 11 (documented default is 0x80) */
293 PDMPciDevSetByte( &pThis->PciDev, 0x63, 0x09); /* PIRQD_ROUT: PCI D -> IRQ 9 (documented default is 0x80) */
294 PDMPciDevSetByte( &pThis->PciDev, 0x64, 0x10); /* SIRQ_CNTL: Serial IRQ Control 10h R/W, RO */
295 PDMPciDevSetByte( &pThis->PciDev, 0x68, 0x80); /* PIRQE_ROUT */
296 PDMPciDevSetByte( &pThis->PciDev, 0x69, 0x80); /* PIRQF_ROUT */
297 PDMPciDevSetByte( &pThis->PciDev, 0x6a, 0x80); /* PIRQG_ROUT */
298 PDMPciDevSetByte( &pThis->PciDev, 0x6b, 0x80); /* PIRQH_ROUT */
299 PDMPciDevSetWord( &pThis->PciDev, 0x6c, 0x00f8); /* IPC_IBDF: IOxAPIC bus:device:function. (Note! Used to be zero.) */
300 if (pThis->uIchVersion == 7)
301 {
302 /* No idea what this is/was yet: */
303 PDMPciDevSetByte( &pThis->PciDev, 0x70, 0x80);
304 PDMPciDevSetByte( &pThis->PciDev, 0x76, 0x0c);
305 PDMPciDevSetByte( &pThis->PciDev, 0x77, 0x0c);
306 PDMPciDevSetByte( &pThis->PciDev, 0x78, 0x02);
307 PDMPciDevSetByte( &pThis->PciDev, 0x79, 0x00);
308 }
309 PDMPciDevSetWord( &pThis->PciDev, 0x80, 0x0000); /* LPC_I/O_DEC: I/O decode ranges. */
310 PDMPciDevSetWord( &pThis->PciDev, 0x82, 0x0000); /* LPC_EN: LPC I/F enables. */
311 PDMPciDevSetDWord( &pThis->PciDev, 0x84, 0x00000000); /* GEN1_DEC: LPC I/F generic decode range 1. */
312 PDMPciDevSetDWord( &pThis->PciDev, 0x88, 0x00000000); /* GEN2_DEC: LPC I/F generic decode range 2. */
313 PDMPciDevSetDWord( &pThis->PciDev, 0x8c, 0x00000000); /* GEN3_DEC: LPC I/F generic decode range 3. */
314 PDMPciDevSetDWord( &pThis->PciDev, 0x90, 0x00000000); /* GEN4_DEC: LPC I/F generic decode range 4. */
315
316 PDMPciDevSetWord( &pThis->PciDev, 0xa0, 0x0008); /* GEN_PMCON_1: Documented default is 0x0000 */
317 PDMPciDevSetByte( &pThis->PciDev, 0xa2, 0x00); /* GEN_PMON_2: */
318 PDMPciDevSetByte( &pThis->PciDev, 0xa4, 0x00); /* GEN_PMON_3: */
319 PDMPciDevSetByte( &pThis->PciDev, 0xa6, 0x00); /* GEN_PMON_LOCK: Configuration lock. */
320 if (pThis->uIchVersion == 7)
321 PDMPciDevSetByte(&pThis->PciDev, 0xa8, 0x0f); /* Is this part of GEN_PMON_LOCK? */
322 PDMPciDevSetByte( &pThis->PciDev, 0xab, 0x00); /* BM_BREAK_EN */
323 PDMPciDevSetDWord( &pThis->PciDev, 0xac, 0x00000000); /* PMIR: Power */
324 PDMPciDevSetDWord( &pThis->PciDev, 0xb8, 0x00000000); /* GPI_ROUT: GPI Route Control */
325 if (pThis->uIchVersion == 9)
326 {
327 /** @todo the next two values looks bogus. */
328 PDMPciDevSetDWord(&pThis->PciDev, 0xd0, 0x00112233); /* FWH_SEL1: Firmware Hub Select 1 */
329 PDMPciDevSetWord( &pThis->PciDev, 0xd4, 0x4567); /* FWH_SEL2: Firmware Hub Select 2 */
330 PDMPciDevSetWord( &pThis->PciDev, 0xd8, 0xffcf); /* FWH_DEC_EN1: Firmware Hub Decode Enable 1 */
331 PDMPciDevSetByte( &pThis->PciDev, 0xdc, 0x00); /* BIOS_CNTL: BIOS control */
332 PDMPciDevSetWord( &pThis->PciDev, 0xe0, 0x0009); /* FDCAP: Feature Detection Capability ID */
333 PDMPciDevSetByte( &pThis->PciDev, 0xe2, 0x0c); /* FDLEN: Feature Detection Capability Length */
334 PDMPciDevSetByte( &pThis->PciDev, 0xe3, 0x10); /* FDVER: Feature Detection Version */
335 PDMPciDevSetByte( &pThis->PciDev, 0xe4, 0x20); /* FDVCT[0]: 5=SATA RAID 0/1/5/10 capability (1=disabled) */
336 PDMPciDevSetByte( &pThis->PciDev, 0xe5, 0x00); /* FDVCT[1]: */
337 PDMPciDevSetByte( &pThis->PciDev, 0xe6, 0x00); /* FDVCT[2]: */
338 PDMPciDevSetByte( &pThis->PciDev, 0xe7, 0x00); /* FDVCT[3]: */
339 PDMPciDevSetByte( &pThis->PciDev, 0xe8, 0xc0); /* FDVCT[4]: 6-7=Intel active magament technology capability (11=disabled). */
340 PDMPciDevSetByte( &pThis->PciDev, 0xe9, 0x00); /* FDVCT[5]: */
341 PDMPciDevSetByte( &pThis->PciDev, 0xea, 0x00); /* FDVCT[6]: */
342 PDMPciDevSetByte( &pThis->PciDev, 0xeb, 0x00); /* FDVCT[7]: */
343 PDMPciDevSetByte( &pThis->PciDev, 0xec, 0x00); /* FDVCT[8]: */
344 PDMPciDevSetByte( &pThis->PciDev, 0xed, 0x00); /* FDVCT[9]: */
345 PDMPciDevSetByte( &pThis->PciDev, 0xee, 0x00); /* FDVCT[a]: */
346 PDMPciDevSetByte( &pThis->PciDev, 0xef, 0x00); /* FDVCT[b]: */
347 }
348
349 /* RCBA: Root complex base address (documented default is 0x00000000). Bit 0 is enable bit. */
350 Assert(!(pThis->GCPhys32Rcba & 0x3fff)); /* 16KB aligned */
351 PDMPciDevSetDWord(&pThis->PciDev, 0xf0, pThis->GCPhys32Rcba | 1);
352
353 rc = PDMDevHlpPCIRegisterEx(pDevIns, &pThis->PciDev, PDMPCIDEVREG_CFG_PRIMARY, PDMPCIDEVREG_F_NOT_MANDATORY_NO,
354 31 /*uPciDevNo*/, 0 /*uPciFunNo*/, "lpc");
355 AssertRCReturn(rc, rc);
356 PDMDevHlpPCISetConfigCallbacks(pDevIns, &pThis->PciDev,
357 lpcPciConfigRead, &pThis->pfnPciConfigReadFallback,
358 lpcPciConfigWrite, &pThis->pfnPciConfigWriteFallback);
359
360 /*
361 * Register the MMIO regions.
362 */
363 /** @todo This should actually be done when RCBA is enabled, but was
364 * mentioned above we just want this working. */
365 rc = PDMDevHlpMMIORegister(pDevIns, pThis->GCPhys32Rcba, 0x4000, pThis,
366 IOMMMIO_FLAGS_READ_DWORD | IOMMMIO_FLAGS_WRITE_PASSTHRU,
367 lpcMmioWrite, lpcMmioRead, "LPC Memory");
368 AssertRCReturn(rc, rc);
369
370
371 /*
372 * Debug info and stats.
373 */
374 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMmioReads, STAMTYPE_COUNTER, "/Devices/LPC/MMIOReads", STAMUNIT_OCCURENCES, "MMIO reads");
375 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMmioWrites, STAMTYPE_COUNTER, "/Devices/LPC/MMIOWrites", STAMUNIT_OCCURENCES, "MMIO writes");
376 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatPciCfgReads, STAMTYPE_COUNTER, "/Devices/LPC/ConfigReads", STAMUNIT_OCCURENCES, "PCI config reads");
377 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatPciCfgWrites, STAMTYPE_COUNTER, "/Devices/LPC/ConfigWrites", STAMUNIT_OCCURENCES, "PCI config writes");
378
379 PDMDevHlpDBGFInfoRegister(pDevIns, "lpc", "Display LPC status. (no arguments)", lpcInfo);
380
381 return VINF_SUCCESS;
382}
383
384
385/**
386 * The device registration structure.
387 */
388const PDMDEVREG g_DeviceLPC =
389{
390 /* u32Version */
391 PDM_DEVREG_VERSION,
392 /* szName */
393 "lpc",
394 /* szRCMod */
395 "",
396 /* szR0Mod */
397 "",
398 /* pszDescription */
399 "Low Pin Count (LPC) Bus",
400 /* fFlags */
401 PDM_DEVREG_FLAGS_HOST_BITS_DEFAULT | PDM_DEVREG_FLAGS_GUEST_BITS_32_64 | PDM_DEVREG_FLAGS_PAE36,
402 /* fClass */
403 PDM_DEVREG_CLASS_MISC,
404 /* cMaxInstances */
405 1,
406 /* cbInstance */
407 sizeof(LPCSTATE),
408 /* pfnConstruct */
409 lpcConstruct,
410 /* pfnDestruct */
411 NULL,
412 /* pfnRelocate */
413 NULL,
414 /* pfnMemSetup */
415 NULL,
416 /* pfnPowerOn */
417 NULL,
418 /* pfnReset */
419 NULL,
420 /* pfnSuspend */
421 NULL,
422 /* pfnResume */
423 NULL,
424 /* pfnAttach */
425 NULL,
426 /* pfnDetach */
427 NULL,
428 /* pfnQueryInterface. */
429 NULL,
430 /* pfnInitComplete */
431 NULL,
432 /* pfnPowerOff */
433 NULL,
434 /* pfnSoftReset */
435 NULL,
436 /* u32VersionEnd */
437 PDM_DEVREG_VERSION
438};
439
440#endif /* IN_RING3 */
441#endif /* VBOX_DEVICE_STRUCT_TESTCASE */
442
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