VirtualBox

source: vbox/trunk/src/VBox/Devices/PC/DevLPC.cpp@ 32204

Last change on this file since 32204 was 29522, checked in by vboxsync, 14 years ago

Devices: move to the right place.
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1/* $Id: DevLPC.cpp 29522 2010-05-17 10:15:48Z vboxsync $ */
2/** @file
3 * DevLPC - LPC device emulation
4 */
5
6/*
7 * Copyright (C) 2006-2010 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 * --------------------------------------------------------------------
17 *
18 * This code is based on:
19 *
20 * Low Pin Count emulation
21 *
22 * Copyright (c) 2007 Alexander Graf
23 *
24 * This library is free software; you can redistribute it and/or
25 * modify it under the terms of the GNU Lesser General Public
26 * License as published by the Free Software Foundation; either
27 * version 2 of the License, or (at your option) any later version.
28 *
29 * This library is distributed in the hope that it will be useful,
30 * but WITHOUT ANY WARRANTY; without even the implied warranty of
31 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
32 * Lesser General Public License for more details.
33 *
34 * You should have received a copy of the GNU Lesser General Public
35 * License along with this library; if not, write to the Free Software
36 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
37 *
38 * *****************************************************************
39 *
40 * This driver emulates an ICH-7 LPC partially. The LPC is basically the
41 * same as the ISA-bridge in the existing PIIX implementation, but
42 * more recent and includes support for HPET and Power Management.
43 *
44 */
45
46/*******************************************************************************
47* Header Files *
48*******************************************************************************/
49#define LOG_GROUP LOG_GROUP_DEV_LPC
50#include <VBox/pdmdev.h>
51#include <VBox/log.h>
52#include <VBox/stam.h>
53#include <iprt/assert.h>
54#include <iprt/string.h>
55
56#include "../Builtins2.h"
57
58#define RCBA_BASE 0xFED1C000
59
60typedef struct
61{
62 /** PCI device structure. */
63 PCIDEVICE dev;
64
65 /** Pointer to the device instance. - R3 ptr. */
66 PPDMDEVINSR3 pDevIns;
67
68 /* So far, not much of a state */
69} LPCState;
70
71
72#ifndef VBOX_DEVICE_STRUCT_TESTCASE
73
74
75static uint32_t rcba_ram_readl(LPCState* s, RTGCPHYS addr)
76{
77 Log(("rcba_read at %llx\n", (uint64_t)addr));
78 int32_t iIndex = (addr - RCBA_BASE);
79 uint32_t value = 0;
80
81 /* This is the HPET config pointer, HPAS in DSDT */
82 switch (iIndex)
83 {
84 case 0x3404:
85 Log(("rcba_read HPET_CONFIG_POINTER\n"));
86 value = 0xf0; /* enabled at 0xfed00000 */
87 break;
88 case 0x3410:
89 /* This is the HPET config pointer */
90 Log(("rcba_read GCS\n"));
91 value = 0;
92 break;
93 default:
94 Log(("Unknown RCBA read\n"));
95 break;
96 }
97
98 return value;
99}
100
101static void rcba_ram_writel(LPCState* s, RTGCPHYS addr, uint32_t value)
102{
103 Log(("rcba_write %llx = %#x\n", (uint64_t)addr, value));
104 int32_t iIndex = (addr - RCBA_BASE);
105
106 switch (iIndex)
107 {
108 case 0x3410:
109 Log(("rcba_write GCS\n"));
110 break;
111 default:
112 Log(("Unknown RCBA write\n"));
113 break;
114 }
115}
116
117/**
118 * I/O handler for memory-mapped read operations.
119 *
120 * @returns VBox status code.
121 *
122 * @param pDevIns The device instance.
123 * @param pvUser User argument.
124 * @param GCPhysAddr Physical address (in GC) where the read starts.
125 * @param pv Where to store the result.
126 * @param cb Number of bytes read.
127 * @thread EMT
128 */
129PDMBOTHCBDECL(int) lpcMMIORead(PPDMDEVINS pDevIns, void *pvUser, RTGCPHYS GCPhysAddr, void *pv, unsigned cb)
130{
131 LPCState *s = PDMINS_2_DATA(pDevIns, LPCState*);
132 switch (cb)
133 {
134 case 1:
135 case 2:
136 break;
137
138 case 4:
139 {
140 *(uint32_t*)pv = rcba_ram_readl(s, GCPhysAddr);
141 break;
142 }
143
144 default:
145 AssertReleaseMsgFailed(("cb=%d\n", cb)); /* for now we assume simple accesses. */
146 return VERR_INTERNAL_ERROR;
147 }
148 return VINF_SUCCESS;
149}
150
151/**
152 * Memory mapped I/O Handler for write operations.
153 *
154 * @returns VBox status code.
155 *
156 * @param pDevIns The device instance.
157 * @param pvUser User argument.
158 * @param GCPhysAddr Physical address (in GC) where the read starts.
159 * @param pv Where to fetch the value.
160 * @param cb Number of bytes to write.
161 * @thread EMT
162 */
163PDMBOTHCBDECL(int) lpcMMIOWrite(PPDMDEVINS pDevIns, void *pvUser, RTGCPHYS GCPhysAddr, void *pv, unsigned cb)
164{
165 LPCState *s = PDMINS_2_DATA(pDevIns, LPCState*);
166
167 switch (cb)
168 {
169 case 1:
170 case 2:
171 break;
172 case 4:
173 {
174 /** @todo: locking? */
175 rcba_ram_writel(s, GCPhysAddr, *(uint32_t *)pv);
176 break;
177 }
178
179 default:
180 AssertReleaseMsgFailed(("cb=%d\n", cb)); /* for now we assume simple accesses. */
181 return VERR_INTERNAL_ERROR;
182 }
183 return VINF_SUCCESS;
184}
185
186#ifdef IN_RING3
187/**
188 * Reset notification.
189 *
190 * @returns VBox status.
191 * @param pDevIns The device instance data.
192 */
193static DECLCALLBACK(void) lpcReset(PPDMDEVINS pDevIns)
194{
195 LPCState *pThis = PDMINS_2_DATA(pDevIns, LPCState *);
196 LogFlow(("lpcReset: \n"));
197}
198
199/**
200 * Info handler, device version.
201 *
202 * @param pDevIns Device instance which registered the info.
203 * @param pHlp Callback functions for doing output.
204 * @param pszArgs Argument string. Optional and specific to the handler.
205 */
206static DECLCALLBACK(void) lpcInfo(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
207{
208 LPCState *pThis = PDMINS_2_DATA(pDevIns, LPCState *);
209 LogFlow(("lpcInfo: \n"));
210}
211
212/**
213 * @interface_method_impl{PDMDEVREG,pfnConstruct}
214 */
215static DECLCALLBACK(int) lpcConstruct(PPDMDEVINS pDevIns, int iInstance, PCFGMNODE pCfg)
216{
217 LPCState *pThis = PDMINS_2_DATA(pDevIns, LPCState *);
218 int rc;
219 Assert(iInstance == 0);
220
221 pThis->pDevIns = pDevIns;
222
223 /*
224 * Register the PCI device.
225 */
226 PCIDevSetVendorId (&pThis->dev, 0x8086); /* Intel */
227 PCIDevSetDeviceId (&pThis->dev, 0x27b9);
228 PCIDevSetCommand (&pThis->dev, 0x0007); /* master, memory and I/O */
229 PCIDevSetRevisionId (&pThis->dev, 0x02);
230 PCIDevSetClassSub (&pThis->dev, 0x01); /* PCI-to-ISA Bridge */
231 PCIDevSetClassBase (&pThis->dev, 0x06); /* Bridge */
232 PCIDevSetHeaderType (&pThis->dev, 0xf0); /* ??? */
233 PCIDevSetSubSystemVendorId(&pThis->dev, 0x8086);
234 PCIDevSetSubSystemId (&pThis->dev, 0x7270);
235 PCIDevSetInterruptPin (&pThis->dev, 0x03);
236 PCIDevSetStatus (&pThis->dev, 0x0200); /* PCI_status_devsel_medium */
237
238 /** @todo: rewrite using PCI accessors */
239 pThis->dev.config[0x40] = 0x01;
240 pThis->dev.config[0x41] = 0x0b;
241
242 pThis->dev.config[0x4c] = 0x4d;
243 pThis->dev.config[0x4e] = 0x03;
244 pThis->dev.config[0x4f] = 0x00;
245
246 pThis->dev.config[0x60] = 0x0a; /* PCI A -> IRQ 10 */
247 pThis->dev.config[0x61] = 0x0a; /* PCI B -> IRQ 10 */
248 pThis->dev.config[0x62] = 0x0b; /* PCI C -> IRQ 11 */
249 pThis->dev.config[0x63] = 0x0b; /* PCI D -> IRQ 11 */
250
251 pThis->dev.config[0x69] = 0x02;
252 pThis->dev.config[0x70] = 0x80;
253 pThis->dev.config[0x76] = 0x0c;
254 pThis->dev.config[0x77] = 0x0c;
255 pThis->dev.config[0x78] = 0x02;
256 pThis->dev.config[0x79] = 0x00;
257 pThis->dev.config[0x80] = 0x00;
258 pThis->dev.config[0x82] = 0x00;
259 pThis->dev.config[0xa0] = 0x08;
260 pThis->dev.config[0xa2] = 0x00;
261 pThis->dev.config[0xa3] = 0x00;
262 pThis->dev.config[0xa4] = 0x00;
263 pThis->dev.config[0xa5] = 0x00;
264 pThis->dev.config[0xa6] = 0x00;
265 pThis->dev.config[0xa7] = 0x00;
266 pThis->dev.config[0xa8] = 0x0f;
267 pThis->dev.config[0xaa] = 0x00;
268 pThis->dev.config[0xab] = 0x00;
269 pThis->dev.config[0xac] = 0x00;
270 pThis->dev.config[0xae] = 0x00;
271
272
273 /* We need to allow direct config reading from this address */
274 pThis->dev.config[0xf0] = (uint8_t)(RCBA_BASE | 1); /* enabled */
275 pThis->dev.config[0xf1] = (uint8_t)(RCBA_BASE >> 8);
276 pThis->dev.config[0xf2] = (uint8_t)(RCBA_BASE >> 16);
277 pThis->dev.config[0xf3] = (uint8_t)(RCBA_BASE >> 24);
278
279 rc = PDMDevHlpPCIRegister (pDevIns, &pThis->dev);
280 if (RT_FAILURE(rc))
281 return rc;
282
283 /*
284 * Register the MMIO regions.
285 */
286 rc = PDMDevHlpMMIORegister(pDevIns, RCBA_BASE, 0x4000, pThis,
287 lpcMMIOWrite, lpcMMIORead, NULL, "LPC Memory");
288 if (RT_FAILURE(rc))
289 return rc;
290
291 /* No state in the LPC right now */
292
293 /*
294 * Initialize the device state.
295 */
296 lpcReset(pDevIns);
297
298 /**
299 * @todo: Register statistics.
300 */
301 PDMDevHlpDBGFInfoRegister(pDevIns, "lpc", "Display LPC status. (no arguments)", lpcInfo);
302
303 return VINF_SUCCESS;
304}
305
306
307/**
308 * The device registration structure.
309 */
310const PDMDEVREG g_DeviceLPC =
311{
312 /* u32Version */
313 PDM_DEVREG_VERSION,
314 /* szName */
315 "lpc",
316 /* szRCMod */
317 "VBoxDD2GC.gc",
318 /* szR0Mod */
319 "VBoxDD2R0.r0",
320 /* pszDescription */
321 "Low Pin Count (LPC) Bus",
322 /* fFlags */
323 PDM_DEVREG_FLAGS_HOST_BITS_DEFAULT | PDM_DEVREG_FLAGS_GUEST_BITS_32_64 | PDM_DEVREG_FLAGS_PAE36,
324 /* fClass */
325 PDM_DEVREG_CLASS_MISC,
326 /* cMaxInstances */
327 1,
328 /* cbInstance */
329 sizeof(LPCState),
330 /* pfnConstruct */
331 lpcConstruct,
332 /* pfnDestruct */
333 NULL,
334 /* pfnRelocate */
335 NULL,
336 /* pfnIOCtl */
337 NULL,
338 /* pfnPowerOn */
339 NULL,
340 /* pfnReset */
341 lpcReset,
342 /* pfnSuspend */
343 NULL,
344 /* pfnResume */
345 NULL,
346 /* pfnAttach */
347 NULL,
348 /* pfnDetach */
349 NULL,
350 /* pfnQueryInterface. */
351 NULL,
352 /* pfnInitComplete */
353 NULL,
354 /* pfnPowerOff */
355 NULL,
356 /* pfnSoftReset */
357 NULL,
358 /* u32VersionEnd */
359 PDM_DEVREG_VERSION
360};
361
362#endif /* IN_RING3 */
363
364#endif /* VBOX_DEVICE_STRUCT_TESTCASE */
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