VirtualBox

source: vbox/trunk/src/VBox/Devices/PC/DevLPC.cpp@ 29085

Last change on this file since 29085 was 29085, checked in by vboxsync, 14 years ago

OSE header fixes
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1/* $Id: DevLPC.cpp 29085 2010-05-05 14:03:59Z vboxsync $ */
2/** @file
3 * DevLPC - LPC device emulation
4 */
5/*
6 * Copyright (C) 2006-2010 Oracle Corporation
7 *
8 * This file is part of VirtualBox Open Source Edition (OSE), as
9 * available from http://www.virtualbox.org. This file is free software;
10 * you can redistribute it and/or modify it under the terms of the GNU
11 * General Public License (GPL) as published by the Free Software
12 * Foundation, in version 2 as it comes in the "COPYING" file of the
13 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
14 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
15 * --------------------------------------------------------------------
16 *
17 * This code is based on:
18 *
19 * Low Pin Count emulation
20 *
21 * Copyright (c) 2007 Alexander Graf
22 *
23 * This library is free software; you can redistribute it and/or
24 * modify it under the terms of the GNU Lesser General Public
25 * License as published by the Free Software Foundation; either
26 * version 2 of the License, or (at your option) any later version.
27 *
28 * This library is distributed in the hope that it will be useful,
29 * but WITHOUT ANY WARRANTY; without even the implied warranty of
30 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
31 * Lesser General Public License for more details.
32 *
33 * You should have received a copy of the GNU Lesser General Public
34 * License along with this library; if not, write to the Free Software
35 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
36 *
37 * *****************************************************************
38 *
39 * This driver emulates an ICH-7 LPC partially. The LPC is basically the
40 * same as the ISA-bridge in the existing PIIX implementation, but
41 * more recent and includes support for HPET and Power Management.
42 *
43 */
44
45/*******************************************************************************
46* Header Files *
47*******************************************************************************/
48#define LOG_GROUP LOG_GROUP_DEV_LPC
49#include <VBox/pdmdev.h>
50#include <VBox/log.h>
51#include <VBox/stam.h>
52#include <iprt/assert.h>
53#include <iprt/string.h>
54
55#include "../Builtins.h"
56
57#define RCBA_BASE 0xFED1C000
58
59typedef struct
60{
61 /** PCI device structure. */
62 PCIDEVICE dev;
63
64 /** Pointer to the device instance. - R3 ptr. */
65 PPDMDEVINSR3 pDevIns;
66
67 /* So far, not much of a state */
68} LPCState;
69
70
71#ifndef VBOX_DEVICE_STRUCT_TESTCASE
72
73
74static uint32_t rcba_ram_readl(LPCState* s, RTGCPHYS addr)
75{
76 Log(("rcba_read at %llx\n", (uint64_t)addr));
77 int32_t iIndex = (addr - RCBA_BASE);
78 uint32_t value = 0;
79
80 /* This is the HPET config pointer, HPAS in DSDT */
81 switch (iIndex)
82 {
83 case 0x3404:
84 Log(("rcba_read HPET_CONFIG_POINTER\n"));
85 value = 0xf0; /* enabled at 0xfed00000 */
86 break;
87 case 0x3410:
88 /* This is the HPET config pointer */
89 Log(("rcba_read GCS\n"));
90 value = 0;
91 break;
92 default:
93 Log(("Unknown RCBA read\n"));
94 break;
95 }
96
97 return value;
98}
99
100static void rcba_ram_writel(LPCState* s, RTGCPHYS addr, uint32_t value)
101{
102 Log(("rcba_write %llx = %#x\n", (uint64_t)addr, value));
103 int32_t iIndex = (addr - RCBA_BASE);
104
105 switch (iIndex)
106 {
107 case 0x3410:
108 Log(("rcba_write GCS\n"));
109 break;
110 default:
111 Log(("Unknown RCBA write\n"));
112 break;
113 }
114}
115
116/**
117 * I/O handler for memory-mapped read operations.
118 *
119 * @returns VBox status code.
120 *
121 * @param pDevIns The device instance.
122 * @param pvUser User argument.
123 * @param GCPhysAddr Physical address (in GC) where the read starts.
124 * @param pv Where to store the result.
125 * @param cb Number of bytes read.
126 * @thread EMT
127 */
128PDMBOTHCBDECL(int) lpcMMIORead(PPDMDEVINS pDevIns, void *pvUser, RTGCPHYS GCPhysAddr, void *pv, unsigned cb)
129{
130 LPCState *s = PDMINS_2_DATA(pDevIns, LPCState*);
131 switch (cb)
132 {
133 case 1:
134 case 2:
135 break;
136
137 case 4:
138 {
139 *(uint32_t*)pv = rcba_ram_readl(s, GCPhysAddr);
140 break;
141 }
142
143 default:
144 AssertReleaseMsgFailed(("cb=%d\n", cb)); /* for now we assume simple accesses. */
145 return VERR_INTERNAL_ERROR;
146 }
147 return VINF_SUCCESS;
148}
149
150/**
151 * Memory mapped I/O Handler for write operations.
152 *
153 * @returns VBox status code.
154 *
155 * @param pDevIns The device instance.
156 * @param pvUser User argument.
157 * @param GCPhysAddr Physical address (in GC) where the read starts.
158 * @param pv Where to fetch the value.
159 * @param cb Number of bytes to write.
160 * @thread EMT
161 */
162PDMBOTHCBDECL(int) lpcMMIOWrite(PPDMDEVINS pDevIns, void *pvUser, RTGCPHYS GCPhysAddr, void *pv, unsigned cb)
163{
164 LPCState *s = PDMINS_2_DATA(pDevIns, LPCState*);
165
166 switch (cb)
167 {
168 case 1:
169 case 2:
170 break;
171 case 4:
172 {
173 /** @todo: locking? */
174 rcba_ram_writel(s, GCPhysAddr, *(uint32_t *)pv);
175 break;
176 }
177
178 default:
179 AssertReleaseMsgFailed(("cb=%d\n", cb)); /* for now we assume simple accesses. */
180 return VERR_INTERNAL_ERROR;
181 }
182 return VINF_SUCCESS;
183}
184
185#ifdef IN_RING3
186/**
187 * Reset notification.
188 *
189 * @returns VBox status.
190 * @param pDevIns The device instance data.
191 */
192static DECLCALLBACK(void) lpcReset(PPDMDEVINS pDevIns)
193{
194 LPCState *pThis = PDMINS_2_DATA(pDevIns, LPCState *);
195 LogFlow(("lpcReset: \n"));
196}
197
198/**
199 * Info handler, device version.
200 *
201 * @param pDevIns Device instance which registered the info.
202 * @param pHlp Callback functions for doing output.
203 * @param pszArgs Argument string. Optional and specific to the handler.
204 */
205static DECLCALLBACK(void) lpcInfo(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
206{
207 LPCState *pThis = PDMINS_2_DATA(pDevIns, LPCState *);
208 LogFlow(("lpcInfo: \n"));
209}
210
211/**
212 * @interface_method_impl{PDMDEVREG,pfnConstruct}
213 */
214static DECLCALLBACK(int) lpcConstruct(PPDMDEVINS pDevIns, int iInstance, PCFGMNODE pCfg)
215{
216 LPCState *pThis = PDMINS_2_DATA(pDevIns, LPCState *);
217 int rc;
218 Assert(iInstance == 0);
219
220 pThis->pDevIns = pDevIns;
221
222 /*
223 * Register the PCI device.
224 */
225 PCIDevSetVendorId (&pThis->dev, 0x8086); /* Intel */
226 PCIDevSetDeviceId (&pThis->dev, 0x27b9);
227 PCIDevSetCommand (&pThis->dev, 0x0007); /* master, memory and I/O */
228 PCIDevSetRevisionId (&pThis->dev, 0x02);
229 PCIDevSetClassSub (&pThis->dev, 0x01); /* PCI-to-ISA Bridge */
230 PCIDevSetClassBase (&pThis->dev, 0x06); /* Bridge */
231 PCIDevSetHeaderType (&pThis->dev, 0xf0); /* ??? */
232 PCIDevSetSubSystemVendorId(&pThis->dev, 0x8086);
233 PCIDevSetSubSystemId (&pThis->dev, 0x7270);
234 PCIDevSetInterruptPin (&pThis->dev, 0x03);
235 PCIDevSetStatus (&pThis->dev, 0x0200); /* PCI_status_devsel_medium */
236
237 /** @todo: rewrite using PCI accessors */
238 pThis->dev.config[0x40] = 0x01;
239 pThis->dev.config[0x41] = 0x0b;
240
241 pThis->dev.config[0x4c] = 0x4d;
242 pThis->dev.config[0x4e] = 0x03;
243 pThis->dev.config[0x4f] = 0x00;
244
245 pThis->dev.config[0x60] = 0x0a; /* PCI A -> IRQ 10 */
246 pThis->dev.config[0x61] = 0x0a; /* PCI B -> IRQ 10 */
247 pThis->dev.config[0x62] = 0x0b; /* PCI C -> IRQ 11 */
248 pThis->dev.config[0x63] = 0x0b; /* PCI D -> IRQ 11 */
249
250 pThis->dev.config[0x69] = 0x02;
251 pThis->dev.config[0x70] = 0x80;
252 pThis->dev.config[0x76] = 0x0c;
253 pThis->dev.config[0x77] = 0x0c;
254 pThis->dev.config[0x78] = 0x02;
255 pThis->dev.config[0x79] = 0x00;
256 pThis->dev.config[0x80] = 0x00;
257 pThis->dev.config[0x82] = 0x00;
258 pThis->dev.config[0xa0] = 0x08;
259 pThis->dev.config[0xa2] = 0x00;
260 pThis->dev.config[0xa3] = 0x00;
261 pThis->dev.config[0xa4] = 0x00;
262 pThis->dev.config[0xa5] = 0x00;
263 pThis->dev.config[0xa6] = 0x00;
264 pThis->dev.config[0xa7] = 0x00;
265 pThis->dev.config[0xa8] = 0x0f;
266 pThis->dev.config[0xaa] = 0x00;
267 pThis->dev.config[0xab] = 0x00;
268 pThis->dev.config[0xac] = 0x00;
269 pThis->dev.config[0xae] = 0x00;
270
271
272 /* We need to allow direct config reading from this address */
273 pThis->dev.config[0xf0] = (uint8_t)(RCBA_BASE | 1); /* enabled */
274 pThis->dev.config[0xf1] = (uint8_t)(RCBA_BASE >> 8);
275 pThis->dev.config[0xf2] = (uint8_t)(RCBA_BASE >> 16);
276 pThis->dev.config[0xf3] = (uint8_t)(RCBA_BASE >> 24);
277
278 rc = PDMDevHlpPCIRegister (pDevIns, &pThis->dev);
279 if (RT_FAILURE(rc))
280 return rc;
281
282 /*
283 * Register the MMIO regions.
284 */
285 rc = PDMDevHlpMMIORegister(pDevIns, RCBA_BASE, 0x4000, pThis,
286 lpcMMIOWrite, lpcMMIORead, NULL, "LPC Memory");
287 if (RT_FAILURE(rc))
288 return rc;
289
290 /* No state in the LPC right now */
291
292 /*
293 * Initialize the device state.
294 */
295 lpcReset(pDevIns);
296
297 /**
298 * @todo: Register statistics.
299 */
300 PDMDevHlpDBGFInfoRegister(pDevIns, "lpc", "Display LPC status. (no arguments)", lpcInfo);
301
302 return VINF_SUCCESS;
303}
304
305
306/**
307 * The device registration structure.
308 */
309const PDMDEVREG g_DeviceLPC =
310{
311 /* u32Version */
312 PDM_DEVREG_VERSION,
313 /* szName */
314 "lpc",
315 /* szRCMod */
316 "VBoxDDGC.gc",
317 /* szR0Mod */
318 "VBoxDDR0.r0",
319 /* pszDescription */
320 " Low Pin Count (LPC) Bus",
321 /* fFlags */
322 PDM_DEVREG_FLAGS_HOST_BITS_DEFAULT | PDM_DEVREG_FLAGS_GUEST_BITS_32_64 | PDM_DEVREG_FLAGS_PAE36,
323 /* fClass */
324 PDM_DEVREG_CLASS_MISC,
325 /* cMaxInstances */
326 1,
327 /* cbInstance */
328 sizeof(LPCState),
329 /* pfnConstruct */
330 lpcConstruct,
331 /* pfnDestruct */
332 NULL,
333 /* pfnRelocate */
334 NULL,
335 /* pfnIOCtl */
336 NULL,
337 /* pfnPowerOn */
338 NULL,
339 /* pfnReset */
340 lpcReset,
341 /* pfnSuspend */
342 NULL,
343 /* pfnResume */
344 NULL,
345 /* pfnAttach */
346 NULL,
347 /* pfnDetach */
348 NULL,
349 /* pfnQueryInterface. */
350 NULL,
351 /* pfnInitComplete */
352 NULL,
353 /* pfnPowerOff */
354 NULL,
355 /* pfnSoftReset */
356 NULL,
357 /* u32VersionEnd */
358 PDM_DEVREG_VERSION
359};
360
361#endif /* IN_RING3 */
362
363#endif /* VBOX_DEVICE_STRUCT_TESTCASE */
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