DevIoApic_Old.cpp@ 62564

Last change on this file since 62564 was 62563, checked in by vboxsync, 8 years ago
Devices: Rename I/O APIC files.
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1	/* $Id: DevIoApic_Old.cpp 62563 2016-07-26 14:12:44Z vboxsync $ */
2	/** @file
3	* I/O Advanced Programmable Interrupt Controller (IO-APIC) Device.
4	*/
5
6	/*
7	* Copyright (C) 2006-2016 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	* --------------------------------------------------------------------
17	*
18	* This code is based on:
19	*
20	* apic.c revision 1.5 @@OSETODO
21	*
22	* APIC support
23	*
24	* Copyright (c) 2004-2005 Fabrice Bellard
25	*
26	* This library is free software; you can redistribute it and/or
27	* modify it under the terms of the GNU Lesser General Public
28	* License as published by the Free Software Foundation; either
29	* version 2 of the License, or (at your option) any later version.
30	*
31	* This library is distributed in the hope that it will be useful,
32	* but WITHOUT ANY WARRANTY; without even the implied warranty of
33	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
34	* Lesser General Public License for more details.
35	*
36	* You should have received a copy of the GNU Lesser General Public
37	* License along with this library; if not, write to the Free Software
38	* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
39	*/
40
41
42	/*********************************************************************************************************************************
43	* Header Files *
44	*********************************************************************************************************************************/
45	#define LOG_GROUP LOG_GROUP_DEV_IOAPIC
46	#include <VBox/vmm/pdmdev.h>
47
48	#include <VBox/log.h>
49	#include <VBox/vmm/stam.h>
50	#include <iprt/assert.h>
51	#include <iprt/asm.h>
52
53	#include <VBox/msi.h>
54
55	#include "VBoxDD2.h"
56	#include "DevApic.h"
57
58
59	/*********************************************************************************************************************************
60	* Defined Constants And Macros *
61	*********************************************************************************************************************************/
62	/** @def IOAPIC_LOCK
63	* Acquires the PDM lock. */
64	#define IOAPIC_LOCK(pThis, rc) \
65	do { \
66	int rc2 = (pThis)->CTX_SUFF(pIoApicHlp)->pfnLock((pThis)->CTX_SUFF(pDevIns), rc); \
67	if (rc2 != VINF_SUCCESS) \
68	return rc2; \
69	} while (0)
70
71	/** @def IOAPIC_UNLOCK
72	* Releases the PDM lock. */
73	#define IOAPIC_UNLOCK(pThis) (pThis)->CTX_SUFF(pIoApicHlp)->pfnUnlock((pThis)->CTX_SUFF(pDevIns))
74
75	#define DEBUG_IOAPIC
76	#define IOAPIC_NUM_PINS 0x18
77
78	/** The old code (this file) */
79	#define IOAPIC_SAVED_STATE_VERSION_VBOX_50 1
80	/** The new code (DevIOAPIC_New). We need to be able to load this SSM as well. */
81	#define IOAPIC_SAVED_STATE_VERSION_NEW_CODE 2
82
83
84	/*********************************************************************************************************************************
85	* Structures and Typedefs *
86	*********************************************************************************************************************************/
87	typedef struct IOAPIC
88	{
89	uint8_t id;
90	uint8_t ioregsel;
91	uint8_t cCpus;
92
93	uint32_t irr;
94	uint64_t ioredtbl[IOAPIC_NUM_PINS];
95	/** The IRQ tags and source IDs for each pin (tracing purposes). */
96	uint32_t auTagSrc[IOAPIC_NUM_PINS];
97
98	/** The device instance - R3 Ptr. */
99	PPDMDEVINSR3 pDevInsR3;
100	/** The IOAPIC helpers - R3 Ptr. */
101	PCPDMIOAPICHLPR3 pIoApicHlpR3;
102
103	/** The device instance - R0 Ptr. */
104	PPDMDEVINSR0 pDevInsR0;
105	/** The IOAPIC helpers - R0 Ptr. */
106	PCPDMIOAPICHLPR0 pIoApicHlpR0;
107
108	/** The device instance - RC Ptr. */
109	PPDMDEVINSRC pDevInsRC;
110	/** The IOAPIC helpers - RC Ptr. */
111	PCPDMIOAPICHLPRC pIoApicHlpRC;
112
113	# ifdef VBOX_WITH_STATISTICS
114	STAMCOUNTER StatMMIOReadGC;
115	STAMCOUNTER StatMMIOReadHC;
116	STAMCOUNTER StatMMIOWriteGC;
117	STAMCOUNTER StatMMIOWriteHC;
118	STAMCOUNTER StatSetIrqGC;
119	STAMCOUNTER StatSetIrqHC;
120	# endif
121	} IOAPIC;
122	typedef IOAPIC *PIOAPIC;
123
124	#ifndef VBOX_DEVICE_STRUCT_TESTCASE
125
126
127	/*********************************************************************************************************************************
128	* Internal Functions *
129	*********************************************************************************************************************************/
130
131
132	static void ioapic_service(PIOAPIC pThis)
133	{
134	uint8_t i;
135	uint8_t trig_mode;
136	uint8_t vector;
137	uint8_t delivery_mode;
138	uint32_t mask;
139	uint64_t entry;
140	uint8_t dest;
141	uint8_t dest_mode;
142	uint8_t polarity;
143
144	for (i = 0; i < IOAPIC_NUM_PINS; i++)
145	{
146	mask = 1 << i;
147	if (pThis->irr & mask)
148	{
149	entry = pThis->ioredtbl[i];
150	if (!(entry & APIC_LVT_MASKED))
151	{
152	trig_mode = ((entry >> 15) & 1);
153	dest = entry >> 56;
154	dest_mode = (entry >> 11) & 1;
155	delivery_mode = (entry >> 8) & 7;
156	polarity = (entry >> 13) & 1;
157	uint32_t uTagSrc = pThis->auTagSrc[i];
158	if (trig_mode == APIC_TRIGGER_EDGE)
159	{
160	pThis->auTagSrc[i] = 0;
161	pThis->irr &= ~mask;
162	}
163	if (delivery_mode == APIC_DM_EXTINT)
164	/* malc: i'm still not so sure about ExtINT delivery */
165	{
166	AssertMsgFailed(("Delivery mode ExtINT"));
167	vector = 0xff; /* incorrect but shuts up gcc. */
168	}
169	else
170	vector = entry & 0xff;
171
172	int rc = pThis->CTX_SUFF(pIoApicHlp)->pfnApicBusDeliver(pThis->CTX_SUFF(pDevIns),
173	dest,
174	dest_mode,
175	delivery_mode,
176	vector,
177	polarity,
178	trig_mode,
179	uTagSrc);
180	/* We must be sure that attempts to reschedule in R3
181	never get here */
182	Assert(rc == VINF_SUCCESS \|\| rc == VERR_APIC_INTR_DISCARDED); NOREF(rc);
183	}
184	}
185	}
186	}
187
188
189	static void ioapic_set_irq(PIOAPIC pThis, int vector, int level, uint32_t uTagSrc)
190	{
191	if (vector >= 0 && vector < IOAPIC_NUM_PINS)
192	{
193	uint32_t mask = 1 << vector;
194	uint64_t entry = pThis->ioredtbl[vector];
195
196	if ((entry >> 15) & 1)
197	{
198	/* level triggered */
199	if (level)
200	{
201	pThis->irr \|= mask;
202	if (!pThis->auTagSrc[vector])
203	pThis->auTagSrc[vector] = uTagSrc;
204	else
205	pThis->auTagSrc[vector] = RT_BIT_32(31);
206
207	ioapic_service(pThis);
208
209	if ((level & PDM_IRQ_LEVEL_FLIP_FLOP) == PDM_IRQ_LEVEL_FLIP_FLOP)
210	{
211	pThis->irr &= ~mask;
212	pThis->auTagSrc[vector] = 0;
213	}
214	}
215	else
216	{
217	pThis->irr &= ~mask;
218	pThis->auTagSrc[vector] = 0;
219	}
220	}
221	else
222	{
223	/* edge triggered */
224	if (level)
225	{
226	pThis->irr \|= mask;
227	if (!pThis->auTagSrc[vector])
228	pThis->auTagSrc[vector] = uTagSrc;
229	else
230	pThis->auTagSrc[vector] = RT_BIT_32(31);
231
232	ioapic_service(pThis);
233	}
234	}
235	}
236	}
237
238
239	/**
240	* Handles a read from the IOAPICID register.
241	*/
242	static int ioapic_IoApicId_r(PIOAPIC pThis, uint32_t *pu32Value)
243	{
244	*pu32Value = (uint32_t)pThis->id << 24;
245	return VINF_SUCCESS;
246	}
247
248
249	/**
250	* Handles a write to the IOAPICID register.
251	*/
252	static int ioapic_IoApicId_w(PIOAPIC pThis, uint32_t u32Value)
253	{
254	/* Note! Compared to the 82093AA spec, we've extended the IOAPIC
255	identification from bits 27:24 to bits 31:24. */
256	Log(("ioapic: IOAPICID %#x -> %#x\n", pThis->id, u32Value >> 24));
257	pThis->id = u32Value >> 24;
258	return VINF_SUCCESS;
259	}
260
261
262	/**
263	* Handles a read from the IOAPICVER register.
264	*/
265	static int ioapic_IoApicVer_r(PIOAPIC pThis, uint32_t *pu32Value)
266	{
267	pu32Value = RT_MAKE_U32(0x11, IOAPIC_NUM_PINS - 1); / (0x11 is the version.) */
268	return VINF_SUCCESS;
269	}
270
271
272	/**
273	* Handles a read from the IOAPICARB register.
274	*/
275	static int ioapic_IoApicArb_r(PIOAPIC pThis, uint32_t *pu32Value)
276	{
277	pu32Value = 0; / (arbitration winner) */
278	return VINF_SUCCESS;
279	}
280
281
282	/**
283	* Handles a read from the IOREGSEL register.
284	*/
285	static int ioapic_IoRegSel_r(PIOAPIC pThis, uint32_t *pu32Value)
286	{
287	*pu32Value = pThis->ioregsel;
288	return VINF_SUCCESS;
289	}
290
291	/**
292	* Handles a write to the IOREGSEL register.
293	*/
294	static int ioapic_IoRegSel_w(PIOAPIC pThis, uint32_t u32Value)
295	{
296	Log2(("ioapic: IOREGSEL %#04x -> %#04x\n", pThis->ioregsel, u32Value & 0xff));
297	/* Bits 7:0 are writable, the rest aren't. Confirmed on recent AMD box. */
298	pThis->ioregsel = u32Value & 0xff;
299	return VINF_SUCCESS;
300	}
301
302
303	/**
304	* Handles a write to the IOWIN register.
305	*/
306	static int ioapic_IoWin_r(PIOAPIC pThis, uint32_t *pu32Value)
307	{
308	int rc = VINF_SUCCESS;
309	uint32_t const uIoRegSel = pThis->ioregsel;
310
311	if (uIoRegSel == 0)
312	rc = ioapic_IoApicId_r(pThis, pu32Value);
313	else if (uIoRegSel == 1)
314	rc = ioapic_IoApicVer_r(pThis, pu32Value);
315	else if (uIoRegSel == 2)
316	rc = ioapic_IoApicArb_r(pThis, pu32Value);
317	/*
318	* IOREDTBL0..IOREDTBL23.
319	*/
320	else if (uIoRegSel - UINT32_C(0x10) < IOAPIC_NUM_PINS * 2)
321	{
322	uint32_t const idxIoRedTbl = (uIoRegSel - UINT32_C(0x10)) >> 1;
323	if (!(uIoRegSel & 1))
324	/** @todo r=bird: Do we need to emulate DELIVS or/and Remote IRR? */
325	*pu32Value = RT_LODWORD(pThis->ioredtbl[idxIoRedTbl]);
326	else
327	*pu32Value = RT_HIDWORD(pThis->ioredtbl[idxIoRedTbl]);
328	}
329	else
330	{
331	Log(("ioapic: Attempt to read from register %#x.\n", uIoRegSel));
332	*pu32Value = UINT32_MAX;
333	}
334
335	Log(("ioapic: IOWIN rd -> %#010x (%Rrc)\n", *pu32Value, rc));
336	return rc;
337	}
338
339
340	/**
341	* Handles a write to the IOWIN register.
342	*/
343	static int ioapic_IoWin_w(PIOAPIC pThis, uint32_t u32Value)
344	{
345	int rc = VINF_SUCCESS;
346	uint32_t const uIoRegSel = pThis->ioregsel;
347	Log2(("ioapic: IOWIN[%#04x] = %#x\n", uIoRegSel, u32Value));
348
349	/*
350	* IOAPICID.
351	*/
352	if (uIoRegSel == 0)
353	rc = ioapic_IoApicId_w(pThis, u32Value);
354	/*
355	* IOREDTBL0..IOREDTBL23.
356	*/
357	else if (uIoRegSel - UINT32_C(0x10) < IOAPIC_NUM_PINS * 2)
358	{
359	uint32_t const idxIoRedTbl = (uIoRegSel - UINT32_C(0x10)) >> 1;
360	uint64_t u64NewValue;
361	if (!(uIoRegSel & 1))
362	{
363	/*
364	* Low DWORD.
365	*
366	* Have to do some sanity checks here because Linux 2.6 kernels
367	* writes seemingly bogus value (u32Value = 0) in their
368	* unlock_ExtINT_logic() function. Not sure what it's good for, but
369	* we ran into trouble with INTVEC = 0. Luckily the 82093AA specs
370	* limits the INTVEC range to 0x10 thru 0xfe, so we use this to
371	* ignore harmful values.
372	*
373	* Update: Looking at real hw (recent AMD), they don't reject
374	* invalid vector numbers, at least not at this point. Could be that
375	* some other code path needs to refuse something instead. Results:
376	* - Writing 0 to lo+hi -> 0.
377	* - Writing ~0 to lo+hi -> 0xff0000000001afff.
378	* - Writing ~0 w/ DELMOD set to 011b or 110b (both reserved)
379	* results in DELMOD containing the reserved values.
380	* - Ditto with same + DELMOD in [0..7], DELMOD is stored as written.
381	*/
382	if ( (u32Value & APIC_LVT_MASKED)
383	\|\| ((u32Value & UINT32_C(0xff)) - UINT32_C(0x10)) <= UINT32_C(0xee) /* (0xfe - 0x10 = 0xee) */ )
384	u64NewValue = (pThis->ioredtbl[idxIoRedTbl] & (UINT64_C(0xffffffff00000000) \| RT_BIT(14) \| RT_BIT(12)))
385	\| (u32Value & ~(RT_BIT(14) \| RT_BIT(12)));
386	else
387	{
388	LogRel(("IOAPIC GUEST BUG: bad vector writing %x(sel=%x) to %u\n", u32Value, uIoRegSel, idxIoRedTbl));
389	u64NewValue = pThis->ioredtbl[idxIoRedTbl];
390	}
391	}
392	else
393	{
394	/*
395	* High DWORD.
396	*/
397	u64NewValue = (pThis->ioredtbl[idxIoRedTbl] & UINT64_C(0x00000000ffffffff))
398	\| ((uint64_t)(u32Value & UINT32_C(0xff000000)) << 32);
399	}
400
401	Log(("ioapic: IOREDTBL%u %#018llx -> %#018llx\n", idxIoRedTbl, pThis->ioredtbl[idxIoRedTbl], u64NewValue));
402	pThis->ioredtbl[idxIoRedTbl] = u64NewValue;
403
404	ioapic_service(pThis);
405	}
406	/*
407	* Read-only or unknown registers. Log it.
408	*/
409	else if (uIoRegSel == 1)
410	Log(("ioapic: Attempt to write (%#x) to IOAPICVER.\n", u32Value));
411	else if (uIoRegSel == 2)
412	Log(("ioapic: Attempt to write (%#x) to IOAPICARB.\n", u32Value));
413	else
414	Log(("ioapic: Attempt to write (%#x) to register %#x.\n", u32Value, uIoRegSel));
415
416	return rc;
417	}
418
419
420	PDMBOTHCBDECL(int) ioapicMMIORead(PPDMDEVINS pDevIns, void pvUser, RTGCPHYS GCPhysAddr, void pv, unsigned cb)
421	{
422	PIOAPIC pThis = PDMINS_2_DATA(pDevIns, PIOAPIC);
423	IOAPIC_LOCK(pThis, VINF_IOM_R3_MMIO_READ);
424
425	STAM_COUNTER_INC(&CTXSUFF(pThis->StatMMIORead));
426
427	/*
428	* Pass it on to the register read handlers.
429	* (See 0xff comments in ioapicMMIOWrite.)
430	*/
431	int rc;
432	uint32_t offReg = GCPhysAddr & 0xff;
433	if (offReg == 0)
434	rc = ioapic_IoRegSel_r(pThis, (uint32_t *)pv);
435	else if (offReg == 0x10)
436	rc = ioapic_IoWin_r(pThis, (uint32_t *)pv);
437	else
438	{
439	Log(("ioapicMMIORead: Invalid access: offReg=%#x\n", offReg));
440	rc = VINF_IOM_MMIO_UNUSED_FF;
441	}
442	Log3(("ioapicMMIORead: @%#x -> %#x %Rrc\n", offReg, (uint32_t )pv, rc));
443
444	IOAPIC_UNLOCK(pThis);
445	return rc;
446	}
447
448	PDMBOTHCBDECL(int) ioapicMMIOWrite(PPDMDEVINS pDevIns, void pvUser, RTGCPHYS GCPhysAddr, void const pv, unsigned cb)
449	{
450	PIOAPIC pThis = PDMINS_2_DATA(pDevIns, PIOAPIC);
451
452	STAM_COUNTER_INC(&CTXSUFF(pThis->StatMMIOWrite));
453	IOAPIC_LOCK(pThis, VINF_IOM_R3_MMIO_WRITE);
454
455	/*
456	* Fetch the value.
457	*
458	* We've told IOM to only give us DWORD accesses. Observations on AMD
459	* indicates that unaligned writes get their missing bytes written as zero.
460	*/
461	Assert(!(GCPhysAddr & 3)); Assert(cb == 4);
462	uint32_t u32Value = (uint32_t const )pv;
463
464	/*
465	* The 0xff mask is because we don't really implement the APICBASE register
466	* in the PIIX3, so if the guest tries to relocate the IOAPIC via PIIX3 we
467	* won't know. The I/O APIC address is on the form FEC0xy00h, where xy is
468	* programmable. Masking 0xff means we cover the y. The x would require
469	* reregistering MMIO memory, which means the guest is out of luck there.
470	*/
471	int rc;
472	uint32_t offReg = GCPhysAddr & 0xff;
473	if (offReg == 0)
474	rc = ioapic_IoRegSel_w(pThis, u32Value);
475	else if (offReg == 0x10)
476	rc = ioapic_IoWin_w(pThis, u32Value);
477	else
478	{
479	Log(("ioapicMMIOWrite: Invalid access: offReg=%#x u32Value=%#x\n", offReg, u32Value));
480	rc = VINF_SUCCESS;
481	}
482	Log3(("ioapicMMIOWrite: @%#x := %#x %Rrc\n", offReg, u32Value, rc));
483
484	IOAPIC_UNLOCK(pThis);
485	return rc;
486	}
487
488	PDMBOTHCBDECL(void) ioapicSetIrq(PPDMDEVINS pDevIns, int iIrq, int iLevel, uint32_t uTagSrc)
489	{
490	/* PDM lock is taken here; / /* @todo add assertion */
491	PIOAPIC pThis = PDMINS_2_DATA(pDevIns, PIOAPIC);
492	STAM_COUNTER_INC(&pThis->CTXSUFF(StatSetIrq));
493	LogFlow(("ioapicSetIrq: iIrq=%d iLevel=%d uTagSrc=%#x\n", iIrq, iLevel, uTagSrc));
494	ioapic_set_irq(pThis, iIrq, iLevel, uTagSrc);
495	}
496
497	PDMBOTHCBDECL(void) ioapicSendMsi(PPDMDEVINS pDevIns, RTGCPHYS GCAddr, uint32_t uValue, uint32_t uTagSrc)
498	{
499	PIOAPIC pThis = PDMINS_2_DATA(pDevIns, PIOAPIC);
500
501	LogFlow(("ioapicSendMsi: Address=%p uValue=%u\n", GCAddr, uValue));
502
503	uint8_t dest = (GCAddr & VBOX_MSI_ADDR_DEST_ID_MASK) >> VBOX_MSI_ADDR_DEST_ID_SHIFT;
504	uint8_t vector_num = (uValue & VBOX_MSI_DATA_VECTOR_MASK) >> VBOX_MSI_DATA_VECTOR_SHIFT;
505	uint8_t dest_mode = (GCAddr >> VBOX_MSI_ADDR_DEST_MODE_SHIFT) & 0x1;
506	uint8_t trigger_mode = (uValue >> VBOX_MSI_DATA_TRIGGER_SHIFT) & 0x1;
507	uint8_t delivery_mode = (uValue >> VBOX_MSI_DATA_DELIVERY_MODE_SHIFT) & 0x7;
508	#if 0
509	/*
510	* This bit indicates whether the message should be directed to the
511	* processor with the lowest interrupt priority among
512	* processors that can receive the interrupt, ignored ATM.
513	*/
514	uint8_t redir_hint = (GCAddr >> VBOX_MSI_ADDR_REDIRECTION_SHIFT) & 0x1;
515	#endif
516	int rc = pThis->CTX_SUFF(pIoApicHlp)->pfnApicBusDeliver(pDevIns,
517	dest,
518	dest_mode,
519	delivery_mode,
520	vector_num,
521	0 /* polarity, n/a */,
522	trigger_mode,
523	uTagSrc);
524	/* We must be sure that attempts to reschedule in R3
525	never get here */
526	Assert(rc == VINF_SUCCESS \|\| rc == VERR_APIC_INTR_DISCARDED); NOREF(rc);
527	}
528
529	#ifdef IN_RING3
530
531	/** @interface_method_impl{DBGFREGDESC,pfnGet} */
532	static DECLCALLBACK(int) ioapicDbgReg_IoRegSel_r(void *pvUser, PCDBGFREGDESC pDesc, PDBGFREGVAL pValue)
533	{
534	return ioapic_IoRegSel_r(PDMINS_2_DATA((PPDMDEVINS)pvUser, PIOAPIC), &pValue->u32);
535	}
536
537	/** @interface_method_impl{DBGFREGDESC,pfnSet} */
538	static DECLCALLBACK(int) ioapicDbgReg_IoRegSel_w(void *pvUser, PCDBGFREGDESC pDesc, PCDBGFREGVAL pValue, PCDBGFREGVAL pfMask)
539	{
540	return ioapic_IoRegSel_w(PDMINS_2_DATA((PPDMDEVINS)pvUser, PIOAPIC), pValue->u8);
541	}
542
543	/** @interface_method_impl{DBGFREGDESC,pfnGet} */
544	static DECLCALLBACK(int) ioapicDbgReg_IoWin_r(void *pvUser, PCDBGFREGDESC pDesc, PDBGFREGVAL pValue)
545	{
546	return ioapic_IoWin_r(PDMINS_2_DATA((PPDMDEVINS)pvUser, PIOAPIC), &pValue->u32);
547	}
548
549	/** @interface_method_impl{DBGFREGDESC,pfnSet} */
550	static DECLCALLBACK(int) ioapicDbgReg_IoWin_w(void *pvUser, PCDBGFREGDESC pDesc, PCDBGFREGVAL pValue, PCDBGFREGVAL pfMask)
551	{
552	return ioapic_IoWin_w(PDMINS_2_DATA((PPDMDEVINS)pvUser, PIOAPIC), pValue->u32);
553	}
554
555	/** @interface_method_impl{DBGFREGDESC,pfnGet} */
556	static DECLCALLBACK(int) ioapicDbgReg_IoApicVer_r(void *pvUser, PCDBGFREGDESC pDesc, PDBGFREGVAL pValue)
557	{
558	return ioapic_IoApicVer_r(PDMINS_2_DATA((PPDMDEVINS)pvUser, PIOAPIC), &pValue->u32);
559	}
560
561	/** @interface_method_impl{DBGFREGDESC,pfnGet} */
562	static DECLCALLBACK(int) ioapicDbgReg_IoApicArb_r(void *pvUser, PCDBGFREGDESC pDesc, PDBGFREGVAL pValue)
563	{
564	return ioapic_IoApicArb_r(PDMINS_2_DATA((PPDMDEVINS)pvUser, PIOAPIC), &pValue->u32);
565	}
566
567	/** @interface_method_impl{DBGFREGDESC,pfnGet} */
568	static DECLCALLBACK(int) ioapicDbgReg_IoRedRblN_r(void *pvUser, PCDBGFREGDESC pDesc, PDBGFREGVAL pValue)
569	{
570	PIOAPIC pThis = PDMINS_2_DATA((PPDMDEVINS)pvUser, PIOAPIC);
571	pValue->u64 = pThis->ioredtbl[pDesc->offRegister];
572	return VINF_SUCCESS;
573	}
574
575	/** @interface_method_impl{DBGFREGDESC,pfnSet} */
576	static DECLCALLBACK(int) ioapicDbgReg_IoRedRblN_w(void *pvUser, PCDBGFREGDESC pDesc, PCDBGFREGVAL pValue, PCDBGFREGVAL pfMask)
577	{
578	PIOAPIC pThis = PDMINS_2_DATA((PPDMDEVINS)pvUser, PIOAPIC);
579	pThis->ioredtbl[pDesc->offRegister] = pValue->u64 \| (~pfMask->u64 &pThis->ioredtbl[pDesc->offRegister]);
580	return VINF_SUCCESS;
581	}
582
583	/** IOREDTBLn sub fields. */
584	static DBGFREGSUBFIELD const g_aIoRedTblSubs[] =
585	{
586	{ "intvec", 0, 8, 0, 0, NULL, NULL },
587	{ "delmode", 8, 3, 0, 0, NULL, NULL },
588	{ "destmode", 11, 1, 0, 0, NULL, NULL },
589	{ "delivs", 12, 1, 0, DBGFREGSUBFIELD_FLAGS_READ_ONLY, NULL, NULL },
590	{ "intpol", 13, 1, 0, 0, NULL, NULL },
591	{ "remoteirr", 14, 1, 0, DBGFREGSUBFIELD_FLAGS_READ_ONLY, NULL, NULL },
592	{ "triggermode", 15, 1, 0, 0, NULL, NULL },
593	{ "intmask", 16, 1, 0, 0, NULL, NULL },
594	{ "dst", 56, 8, 0, 0, NULL, NULL },
595	DBGFREGSUBFIELD_TERMINATOR()
596	};
597
598	/** Register descriptors for DBGF. */
599	static DBGFREGDESC const g_aRegDesc[] =
600	{
601	{ "ioregsel", DBGFREG_END, DBGFREGVALTYPE_U8, 0, 0, ioapicDbgReg_IoRegSel_r, ioapicDbgReg_IoRegSel_w, NULL, NULL },
602	{ "iowin", DBGFREG_END, DBGFREGVALTYPE_U32, 0, 0, ioapicDbgReg_IoWin_r, ioapicDbgReg_IoWin_w, NULL, NULL },
603	{ "ioapicver", DBGFREG_END, DBGFREGVALTYPE_U32, DBGFREG_FLAGS_READ_ONLY, 0, ioapicDbgReg_IoApicVer_r, NULL, NULL, NULL },
604	{ "ioapicarb", DBGFREG_END, DBGFREGVALTYPE_U32, DBGFREG_FLAGS_READ_ONLY, 0, ioapicDbgReg_IoApicArb_r, NULL, NULL, NULL },
605	{ "ioredtbl0", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 0, ioapicDbgReg_IoRedRblN_r, ioapicDbgReg_IoRedRblN_w, NULL, &g_aIoRedTblSubs[0] },
606	{ "ioredtbl1", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 1, ioapicDbgReg_IoRedRblN_r, ioapicDbgReg_IoRedRblN_w, NULL, &g_aIoRedTblSubs[0] },
607	{ "ioredtbl2", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 2, ioapicDbgReg_IoRedRblN_r, ioapicDbgReg_IoRedRblN_w, NULL, &g_aIoRedTblSubs[0] },
608	{ "ioredtbl3", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 3, ioapicDbgReg_IoRedRblN_r, ioapicDbgReg_IoRedRblN_w, NULL, &g_aIoRedTblSubs[0] },
609	{ "ioredtbl4", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 4, ioapicDbgReg_IoRedRblN_r, ioapicDbgReg_IoRedRblN_w, NULL, &g_aIoRedTblSubs[0] },
610	{ "ioredtbl5", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 5, ioapicDbgReg_IoRedRblN_r, ioapicDbgReg_IoRedRblN_w, NULL, &g_aIoRedTblSubs[0] },
611	{ "ioredtbl6", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 6, ioapicDbgReg_IoRedRblN_r, ioapicDbgReg_IoRedRblN_w, NULL, &g_aIoRedTblSubs[0] },
612	{ "ioredtbl7", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 7, ioapicDbgReg_IoRedRblN_r, ioapicDbgReg_IoRedRblN_w, NULL, &g_aIoRedTblSubs[0] },
613	{ "ioredtbl8", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 8, ioapicDbgReg_IoRedRblN_r, ioapicDbgReg_IoRedRblN_w, NULL, &g_aIoRedTblSubs[0] },
614	{ "ioredtbl9", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 9, ioapicDbgReg_IoRedRblN_r, ioapicDbgReg_IoRedRblN_w, NULL, &g_aIoRedTblSubs[0] },
615	{ "ioredtbl10", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 10, ioapicDbgReg_IoRedRblN_r, ioapicDbgReg_IoRedRblN_w, NULL, &g_aIoRedTblSubs[0] },
616	{ "ioredtbl11", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 11, ioapicDbgReg_IoRedRblN_r, ioapicDbgReg_IoRedRblN_w, NULL, &g_aIoRedTblSubs[0] },
617	{ "ioredtbl12", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 12, ioapicDbgReg_IoRedRblN_r, ioapicDbgReg_IoRedRblN_w, NULL, &g_aIoRedTblSubs[0] },
618	{ "ioredtbl13", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 13, ioapicDbgReg_IoRedRblN_r, ioapicDbgReg_IoRedRblN_w, NULL, &g_aIoRedTblSubs[0] },
619	{ "ioredtbl14", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 14, ioapicDbgReg_IoRedRblN_r, ioapicDbgReg_IoRedRblN_w, NULL, &g_aIoRedTblSubs[0] },
620	{ "ioredtbl15", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 15, ioapicDbgReg_IoRedRblN_r, ioapicDbgReg_IoRedRblN_w, NULL, &g_aIoRedTblSubs[0] },
621	{ "ioredtbl16", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 16, ioapicDbgReg_IoRedRblN_r, ioapicDbgReg_IoRedRblN_w, NULL, &g_aIoRedTblSubs[0] },
622	{ "ioredtbl17", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 17, ioapicDbgReg_IoRedRblN_r, ioapicDbgReg_IoRedRblN_w, NULL, &g_aIoRedTblSubs[0] },
623	{ "ioredtbl18", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 18, ioapicDbgReg_IoRedRblN_r, ioapicDbgReg_IoRedRblN_w, NULL, &g_aIoRedTblSubs[0] },
624	{ "ioredtbl19", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 19, ioapicDbgReg_IoRedRblN_r, ioapicDbgReg_IoRedRblN_w, NULL, &g_aIoRedTblSubs[0] },
625	{ "ioredtbl20", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 20, ioapicDbgReg_IoRedRblN_r, ioapicDbgReg_IoRedRblN_w, NULL, &g_aIoRedTblSubs[0] },
626	{ "ioredtbl21", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 21, ioapicDbgReg_IoRedRblN_r, ioapicDbgReg_IoRedRblN_w, NULL, &g_aIoRedTblSubs[0] },
627	{ "ioredtbl22", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 22, ioapicDbgReg_IoRedRblN_r, ioapicDbgReg_IoRedRblN_w, NULL, &g_aIoRedTblSubs[0] },
628	{ "ioredtbl23", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 23, ioapicDbgReg_IoRedRblN_r, ioapicDbgReg_IoRedRblN_w, NULL, &g_aIoRedTblSubs[0] },
629	DBGFREGDESC_TERMINATOR()
630	};
631
632
633	/**
634	* Info handler, device version. Dumps I/O APIC state.
635	*
636	* @param pDevIns Device instance which registered the info.
637	* @param pHlp Callback functions for doing output.
638	* @param pszArgs Argument string. Optional and specific to the handler.
639	*/
640	static DECLCALLBACK(void) ioapicInfo(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
641	{
642	PIOAPIC pThis = PDMINS_2_DATA(pDevIns, PIOAPIC);
643	uint32_t uVal;
644
645	pHlp->pfnPrintf(pHlp, "I/O APIC at %#010x:\n", 0xfec00000);
646
647	ioapic_IoApicId_r(pThis, &uVal);
648	pHlp->pfnPrintf(pHlp, " IOAPICID : %#010x\n", uVal);
649	pHlp->pfnPrintf(pHlp, " APIC ID = %#04x\n", (uVal >> 24) & 0xff);
650
651	ioapic_IoApicVer_r(pThis, &uVal);
652	unsigned iLastRedir = RT_BYTE3(uVal);
653	pHlp->pfnPrintf(pHlp, " IOAPICVER : %#010x\n", uVal);
654	pHlp->pfnPrintf(pHlp, " version = %#04x\n", uVal & 0xff);
655	pHlp->pfnPrintf(pHlp, " redirs = %u\n", iLastRedir + 1);
656
657	ioapic_IoApicArb_r(pThis, &uVal);
658	pHlp->pfnPrintf(pHlp, " arb ID = %#010x\n", RT_BYTE4(uVal));
659	pHlp->pfnPrintf(pHlp, " IOAPICARB : %#08x\n", uVal);
660
661	Assert(sizeof(pThis->ioredtbl) / sizeof(pThis->ioredtbl[0]) > iLastRedir);
662	pHlp->pfnPrintf(pHlp, "I/O redirection table\n");
663	pHlp->pfnPrintf(pHlp, " idx dst_mode dst_addr mask trigger rirr polarity dlvr_st dlvr_mode vector\n");
664	for (unsigned i = 0; i <= iLastRedir; ++i)
665	{
666	static const char * const s_apszDModes[] =
667	{
668	"Fixed ", "LowPri", "SMI ", "Resrvd", "NMI ", "INIT ", "Resrvd", "ExtINT"
669	};
670
671	pHlp->pfnPrintf(pHlp, " %02d %s %02x %d %s %d %s %s %s %3d (%016llx)\n",
672	i,
673	pThis->ioredtbl[i] & RT_BIT(11) ? "log " : "phys", /* dest mode */
674	(int)(pThis->ioredtbl[i] >> 56), /* dest addr */
675	(int)(pThis->ioredtbl[i] >> 16) & 1, /* mask */
676	pThis->ioredtbl[i] & RT_BIT(15) ? "level" : "edge ", /* trigger */
677	(int)(pThis->ioredtbl[i] >> 14) & 1, /* remote IRR */
678	pThis->ioredtbl[i] & RT_BIT(13) ? "activelo" : "activehi", /* polarity */
679	pThis->ioredtbl[i] & RT_BIT(12) ? "pend" : "idle", /* delivery status */
680	s_apszDModes[(pThis->ioredtbl[i] >> 8) & 0x07], /* delivery mode */
681	(int)pThis->ioredtbl[i] & 0xff, /* vector */
682	pThis->ioredtbl[i] /* entire register */
683	);
684	}
685	}
686
687	/**
688	* @copydoc FNSSMDEVSAVEEXEC
689	*/
690	static DECLCALLBACK(int) ioapicSaveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
691	{
692	PIOAPIC pThis = PDMINS_2_DATA(pDevIns, PIOAPIC);
693
694	SSMR3PutU8(pSSM, pThis->id);
695	SSMR3PutU8(pSSM, pThis->ioregsel);
696	for (unsigned i = 0; i < IOAPIC_NUM_PINS; i++)
697	SSMR3PutU64(pSSM, pThis->ioredtbl[i]);
698
699	return VINF_SUCCESS;
700	}
701
702	/**
703	* @copydoc FNSSMDEVLOADEXEC
704	*/
705	static DECLCALLBACK(int) ioapicLoadExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
706	{
707	PIOAPIC pThis = PDMINS_2_DATA(pDevIns, PIOAPIC);
708	if ( uVersion != IOAPIC_SAVED_STATE_VERSION_VBOX_50
709	&& uVersion != IOAPIC_SAVED_STATE_VERSION_NEW_CODE)
710	return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
711
712	uint32_t ignore;
713	if (uVersion == IOAPIC_SAVED_STATE_VERSION_NEW_CODE)
714	SSMR3GetU32(pSSM, &ignore);
715
716	SSMR3GetU8(pSSM, &pThis->id);
717	SSMR3GetU8(pSSM, &pThis->ioregsel);
718	for (unsigned i = 0; i < IOAPIC_NUM_PINS; i++)
719	SSMR3GetU64(pSSM, &pThis->ioredtbl[i]);
720
721	Assert(uPass == SSM_PASS_FINAL); NOREF(uPass);
722	return VINF_SUCCESS;
723	}
724
725	/**
726	* @copydoc FNPDMDEVRESET
727	*/
728	static DECLCALLBACK(void) ioapicReset(PPDMDEVINS pDevIns)
729	{
730	PIOAPIC pThis = PDMINS_2_DATA(pDevIns, PIOAPIC);
731	pThis->pIoApicHlpR3->pfnLock(pDevIns, VERR_INTERNAL_ERROR);
732
733	pThis->id = pThis->cCpus;
734	pThis->ioregsel = 0;
735	pThis->irr = 0;
736	for (unsigned i = 0; i < IOAPIC_NUM_PINS; i++)
737	{
738	pThis->ioredtbl[i] = 1 << 16; /* mask LVT */
739	pThis->auTagSrc[i] = 0;
740	}
741
742	IOAPIC_UNLOCK(pThis);
743	}
744
745	/**
746	* @copydoc FNPDMDEVRELOCATE
747	*/
748	static DECLCALLBACK(void) ioapicRelocate(PPDMDEVINS pDevIns, RTGCINTPTR offDelta)
749	{
750	PIOAPIC pThis = PDMINS_2_DATA(pDevIns, PIOAPIC);
751	pThis->pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
752	pThis->pIoApicHlpRC = pThis->pIoApicHlpR3->pfnGetRCHelpers(pDevIns);
753	}
754
755	/**
756	* @copydoc FNPDMDEVCONSTRUCT
757	*/
758	static DECLCALLBACK(int) ioapicConstruct(PPDMDEVINS pDevIns, int iInstance, PCFGMNODE pCfg)
759	{
760	PIOAPIC pThis = PDMINS_2_DATA(pDevIns, PIOAPIC);
761	Assert(iInstance == 0);
762
763	/*
764	* Initialize the state data.
765	*/
766	pThis->pDevInsR3 = pDevIns;
767	pThis->pDevInsR0 = PDMDEVINS_2_R0PTR(pDevIns);
768	pThis->pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
769	/* (the rest is done by the reset call at the end) */
770
771	/* PDM provides locking via the IOAPIC helpers. */
772	int rc = PDMDevHlpSetDeviceCritSect(pDevIns, PDMDevHlpCritSectGetNop(pDevIns));
773	AssertRCReturn(rc, rc);
774
775	/*
776	* Validate and read the configuration.
777	*/
778	PDMDEV_VALIDATE_CONFIG_RETURN(pDevIns, "NumCPUs\|RZEnabled", "");
779
780	uint32_t cCpus;
781	rc = CFGMR3QueryU32Def(pCfg, "NumCPUs", &cCpus, 1);
782	if (RT_FAILURE(rc))
783	return PDMDEV_SET_ERROR(pDevIns, rc,
784	N_("Configuration error: Failed to query integer value \"NumCPUs\""));
785	if (cCpus > UINT8_MAX - 2) /* ID 255 is broadcast and the IO-APIC needs one (ID=cCpus). */
786	return PDMDevHlpVMSetError(pDevIns, rc, RT_SRC_POS,
787	N_("Configuration error: Max %u CPUs, %u specified"), UINT8_MAX - 1, cCpus);
788	pThis->cCpus = (uint8_t)cCpus;
789
790	bool fRZEnabled;
791	rc = CFGMR3QueryBoolDef(pCfg, "RZEnabled", &fRZEnabled, true);
792	if (RT_FAILURE(rc))
793	return PDMDEV_SET_ERROR(pDevIns, rc,
794	N_("Configuration error: Failed to query boolean value \"RZEnabled\""));
795
796	Log(("IOAPIC: cCpus=%u fRZEnabled=%RTbool\n", cCpus, fRZEnabled));
797
798	/*
799	* Register the IOAPIC and get helpers.
800	*/
801	PDMIOAPICREG IoApicReg;
802	IoApicReg.u32Version = PDM_IOAPICREG_VERSION;
803	IoApicReg.pfnSetIrqR3 = ioapicSetIrq;
804	IoApicReg.pszSetIrqRC = fRZEnabled ? "ioapicSetIrq" : NULL;
805	IoApicReg.pszSetIrqR0 = fRZEnabled ? "ioapicSetIrq" : NULL;
806	IoApicReg.pfnSendMsiR3 = ioapicSendMsi;
807	IoApicReg.pszSendMsiRC = fRZEnabled ? "ioapicSendMsi" : NULL;
808	IoApicReg.pszSendMsiR0 = fRZEnabled ? "ioapicSendMsi" : NULL;
809	IoApicReg.pfnSetEoiR3 = NULL;
810	IoApicReg.pszSetEoiR0 = NULL;
811	IoApicReg.pszSetEoiRC = NULL;
812
813	rc = PDMDevHlpIOAPICRegister(pDevIns, &IoApicReg, &pThis->pIoApicHlpR3);
814	if (RT_FAILURE(rc))
815	{
816	AssertMsgFailed(("IOAPICRegister -> %Rrc\n", rc));
817	return rc;
818	}
819
820	/*
821	* Register MMIO callbacks and saved state.
822	* Note! The write ZEROing was observed on a real AMD system.
823	*/
824	rc = PDMDevHlpMMIORegister(pDevIns, UINT32_C(0xfec00000), 0x1000, pThis,
825	IOMMMIO_FLAGS_READ_DWORD \| IOMMMIO_FLAGS_WRITE_DWORD_ZEROED,
826	ioapicMMIOWrite, ioapicMMIORead, "I/O APIC Memory");
827	if (RT_FAILURE(rc))
828	return rc;
829
830	if (fRZEnabled)
831	{
832	pThis->pIoApicHlpRC = pThis->pIoApicHlpR3->pfnGetRCHelpers(pDevIns);
833	rc = PDMDevHlpMMIORegisterRC(pDevIns, UINT32_C(0xfec00000), 0x1000, NIL_RTRCPTR /pvUser/,
834	"ioapicMMIOWrite", "ioapicMMIORead");
835	AssertRCReturn(rc, rc);
836
837	pThis->pIoApicHlpR0 = pThis->pIoApicHlpR3->pfnGetR0Helpers(pDevIns);
838	rc = PDMDevHlpMMIORegisterR0(pDevIns, UINT32_C(0xfec00000), 0x1000, NIL_RTR0PTR /pvUser/,
839	"ioapicMMIOWrite", "ioapicMMIORead");
840	AssertRCReturn(rc, rc);
841	}
842
843	rc = PDMDevHlpSSMRegister(pDevIns, IOAPIC_SAVED_STATE_VERSION_VBOX_50, sizeof(*pThis),
844	ioapicSaveExec, ioapicLoadExec);
845	if (RT_FAILURE(rc))
846	return rc;
847
848	/*
849	* Register debugger info callback.
850	*/
851	rc = PDMDevHlpDBGFInfoRegister(pDevIns, "ioapic", "Display I/O APIC state.", ioapicInfo); AssertRC(rc);
852	rc = PDMDevHlpDBGFRegRegister(pDevIns, g_aRegDesc); AssertRC(rc);
853
854	#ifdef VBOX_WITH_STATISTICS
855	/*
856	* Statistics.
857	*/
858	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMMIOReadGC, STAMTYPE_COUNTER, "/Devices/IOAPIC/MMIOReadGC", STAMUNIT_OCCURENCES, "Number of IOAPIC MMIO reads in GC.");
859	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMMIOReadHC, STAMTYPE_COUNTER, "/Devices/IOAPIC/MMIOReadHC", STAMUNIT_OCCURENCES, "Number of IOAPIC MMIO reads in HC.");
860	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMMIOWriteGC, STAMTYPE_COUNTER, "/Devices/IOAPIC/MMIOWriteGC", STAMUNIT_OCCURENCES, "Number of IOAPIC MMIO writes in GC.");
861	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMMIOWriteHC, STAMTYPE_COUNTER, "/Devices/IOAPIC/MMIOWriteHC", STAMUNIT_OCCURENCES, "Number of IOAPIC MMIO writes in HC.");
862	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatSetIrqGC, STAMTYPE_COUNTER, "/Devices/IOAPIC/SetIrqGC", STAMUNIT_OCCURENCES, "Number of IOAPIC SetIrq calls in GC.");
863	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatSetIrqHC, STAMTYPE_COUNTER, "/Devices/IOAPIC/SetIrqHC", STAMUNIT_OCCURENCES, "Number of IOAPIC SetIrq calls in HC.");
864	#endif
865
866	/*
867	* Reset the device state.
868	*/
869	ioapicReset(pDevIns);
870
871	return VINF_SUCCESS;
872	}
873
874	/**
875	* IO APIC device registration structure.
876	*/
877	const PDMDEVREG g_DeviceIOAPIC =
878	{
879	/* u32Version */
880	PDM_DEVREG_VERSION,
881	/* szName */
882	"ioapic",
883	/* szRCMod */
884	"VBoxDD2RC.rc",
885	/* szR0Mod */
886	"VBoxDD2R0.r0",
887	/* pszDescription */
888	"I/O Advanced Programmable Interrupt Controller (IO-APIC) Device",
889	/* fFlags */
890	PDM_DEVREG_FLAGS_HOST_BITS_DEFAULT \| PDM_DEVREG_FLAGS_GUEST_BITS_32_64 \| PDM_DEVREG_FLAGS_PAE36 \| PDM_DEVREG_FLAGS_RC \| PDM_DEVREG_FLAGS_R0,
891	/* fClass */
892	PDM_DEVREG_CLASS_PIC,
893	/* cMaxInstances */
894	1,
895	/* cbInstance */
896	sizeof(IOAPIC),
897	/* pfnConstruct */
898	ioapicConstruct,
899	/* pfnDestruct */
900	NULL,
901	/* pfnRelocate */
902	ioapicRelocate,
903	/* pfnMemSetup */
904	NULL,
905	/* pfnPowerOn */
906	NULL,
907	/* pfnReset */
908	ioapicReset,
909	/* pfnSuspend */
910	NULL,
911	/* pfnResume */
912	NULL,
913	/* pfnAttach */
914	NULL,
915	/* pfnDetach */
916	NULL,
917	/* pfnQueryInterface. */
918	NULL,
919	/* pfnInitComplete */
920	NULL,
921	/* pfnPowerOff */
922	NULL,
923	/* pfnSoftReset */
924	NULL,
925	/* u32VersionEnd */
926	PDM_DEVREG_VERSION
927	};
928
929	#endif /* IN_RING3 */
930	#endif /* !VBOX_DEVICE_STRUCT_TESTCASE */

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source: vbox/trunk/src/VBox/Devices/PC/DevIoApic_Old.cpp@ 62564

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