DevIoApic.cpp@ 63495

Last change on this file since 63495 was 63464, checked in by vboxsync, 8 years ago
DevIoApic: Revert r109657 (causing boot failures on SMP windows VMs)
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1	/* $Id: DevIoApic.cpp 63464 2016-08-15 09:40:52Z vboxsync $ */
2	/** @file
3	* IO APIC - Input/Output Advanced Programmable Interrupt Controller.
4	*/
5
6	/*
7	* Copyright (C) 2016 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18
19	/*********************************************************************************************************************************
20	* Header Files *
21	*********************************************************************************************************************************/
22	#define LOG_GROUP LOG_GROUP_DEV_IOAPIC
23	#include <VBox/log.h>
24	#include <VBox/vmm/hm.h>
25	#include <VBox/msi.h>
26	#include <VBox/vmm/pdmdev.h>
27
28	#include "VBoxDD.h"
29	#include <iprt/x86.h>
30
31
32	/*********************************************************************************************************************************
33	* Defined Constants And Macros *
34	*********************************************************************************************************************************/
35	/** The current IO APIC saved state version. */
36	#define IOAPIC_SAVED_STATE_VERSION 2
37	/** The saved state version used by VirtualBox 5.0 and
38	* earlier. */
39	#define IOAPIC_SAVED_STATE_VERSION_VBOX_50 1
40
41	/** Implementation specified by the "Intel I/O Controller Hub 9
42	* (ICH9) Family" */
43	#define IOAPIC_HARDWARE_VERSION_ICH9 1
44	/** Implementation specified by the "82093AA I/O Advanced Programmable Interrupt
45	Controller" */
46	#define IOAPIC_HARDWARE_VERSION_82093AA 2
47	/** The IO APIC implementation to use. */
48	#define IOAPIC_HARDWARE_VERSION IOAPIC_HARDWARE_VERSION_ICH9
49
50	#if IOAPIC_HARDWARE_VERSION == IOAPIC_HARDWARE_VERSION_82093AA
51	/** The version. */
52	# define IOAPIC_VERSION 0x11
53	/** The ID mask. */
54	# define IOAPIC_ID_MASK 0x0f
55	#elif IOAPIC_HARDWARE_VERSION == IOAPIC_HARDWARE_VERSION_ICH9
56	/** The version. */
57	# define IOAPIC_VERSION 0x20
58	/** The ID mask. */
59	# define IOAPIC_ID_MASK 0xff
60	#else
61	# error "Implement me"
62	#endif
63
64	/** The default MMIO base physical address. */
65	#define IOAPIC_MMIO_BASE_PHYSADDR UINT64_C(0xfec00000)
66	/** The size of the MMIO range. */
67	#define IOAPIC_MMIO_SIZE X86_PAGE_4K_SIZE
68	/** The mask for getting direct registers from physical address. */
69	#define IOAPIC_MMIO_REG_MASK 0xff
70
71	/** The number of interrupt input pins. */
72	#define IOAPIC_NUM_INTR_PINS 24
73	/** Maximum redirection entires. */
74	#define IOAPIC_MAX_REDIR_ENTRIES (IOAPIC_NUM_INTR_PINS - 1)
75
76	/** Version register - Gets the version. */
77	#define IOAPIC_VER_GET_VER(a_Reg) ((a_Reg) & 0xff)
78	/** Version register - Gets the maximum redirection entry. */
79	#define IOAPIC_VER_GET_MRE(a_Reg) (((a_Reg) >> 16) & 0xff)
80	/** Version register - Gets whether Pin Assertion Register (PRQ) is
81	* supported. */
82	#define IOAPIC_VER_HAS_PRQ(a_Reg) RT_BOOL((a_Reg) & RT_BIT_32(15))
83
84	/** Index register - Valid write mask. */
85	#define IOAPIC_INDEX_VALID_WRITE_MASK UINT32_C(0xff)
86
87	/** Arbitration register - Gets the ID. */
88	#define IOAPIC_ARB_GET_ID(a_Reg) ((a_Reg) >> 24 & 0xf)
89
90	/** ID register - Gets the ID. */
91	#define IOAPIC_ID_GET_ID(a_Reg) ((a_Reg) >> 24 & IOAPIC_ID_MASK)
92
93	/** Redirection table entry - Vector. */
94	#define IOAPIC_RTE_VECTOR UINT64_C(0xff)
95	/** Redirection table entry - Delivery mode. */
96	#define IOAPIC_RTE_DELIVERY_MODE (RT_BIT_64(8) \| RT_BIT_64(9) \| RT_BIT_64(10))
97	/** Redirection table entry - Destination mode. */
98	#define IOAPIC_RTE_DEST_MODE RT_BIT_64(11)
99	/** Redirection table entry - Delivery status. */
100	#define IOAPIC_RTE_DELIVERY_STATUS RT_BIT_64(12)
101	/** Redirection table entry - Interrupt input pin polarity. */
102	#define IOAPIC_RTE_POLARITY RT_BIT_64(13)
103	/** Redirection table entry - Remote IRR. */
104	#define IOAPIC_RTE_REMOTE_IRR RT_BIT_64(14)
105	/** Redirection table entry - Trigger Mode. */
106	#define IOAPIC_RTE_TRIGGER_MODE RT_BIT_64(15)
107	/** Redirection table entry - the mask bit number. */
108	#define IOAPIC_RTE_MASK_BIT 16
109	/** Redirection table entry - the mask. */
110	#define IOAPIC_RTE_MASK RT_BIT_64(IOAPIC_RTE_MASK_BIT)
111	/** Redirection table entry - Extended Destination ID. */
112	#define IOAPIC_RTE_EXT_DEST_ID UINT64_C(0x00ff000000000000)
113	/** Redirection table entry - Destination. */
114	#define IOAPIC_RTE_DEST UINT64_C(0xff00000000000000)
115
116	/** Redirection table entry - Gets the destination. */
117	#define IOAPIC_RTE_GET_DEST(a_Reg) ((a_Reg) >> 56 & 0xff)
118	/** Redirection table entry - Gets the mask flag. */
119	#define IOAPIC_RTE_GET_MASK(a_Reg) (((a_Reg) >> IOAPIC_RTE_MASK_BIT) & 0x1)
120	/** Redirection table entry - Checks whether it's masked. */
121	#define IOAPIC_RTE_IS_MASKED(a_Reg) ((a_Reg) & IOAPIC_RTE_MASK)
122	/** Redirection table entry - Gets the trigger mode. */
123	#define IOAPIC_RTE_GET_TRIGGER_MODE(a_Reg) (((a_Reg) >> 15) & 0x1)
124	/** Redirection table entry - Gets the remote IRR flag. */
125	#define IOAPIC_RTE_GET_REMOTE_IRR(a_Reg) (((a_Reg) >> 14) & 0x1)
126	/** Redirection table entry - Gets the interrupt pin polarity. */
127	#define IOAPIC_RTE_GET_POLARITY(a_Reg) (((a_Reg) >> 13) & 0x1)
128	/** Redirection table entry - Gets the delivery status. */
129	#define IOAPIC_RTE_GET_DELIVERY_STATUS(a_Reg) (((a_Reg) >> 12) & 0x1)
130	/** Redirection table entry - Gets the destination mode. */
131	#define IOAPIC_RTE_GET_DEST_MODE(a_Reg) (((a_Reg) >> 11) & 0x1)
132	/** Redirection table entry - Gets the delivery mode. */
133	#define IOAPIC_RTE_GET_DELIVERY_MODE(a_Reg) (((a_Reg) >> 8) & 0x7)
134	/** Redirection table entry - Gets the vector. */
135	#define IOAPIC_RTE_GET_VECTOR(a_Reg) ((a_Reg) & IOAPIC_RTE_VECTOR)
136
137	#if IOAPIC_HARDWARE_VERSION == IOAPIC_HARDWARE_VERSION_82093AA
138	/** Redirection table entry - Valid write mask. */
139	#define IOAPIC_RTE_VALID_WRITE_MASK ( IOAPIC_RTE_DEST \| IOAPIC_RTE_MASK \| IOAPIC_RTE_TRIGGER_MODE \
140	\| IOAPIC_RTE_POLARITY \| IOAPIC_RTE_DEST_MODE \| IOAPIC_RTE_DELIVERY_MODE \
141	\| IOAPIC_RTE_VECTOR)
142	/** Redirection table entry - Valid read mask. */
143	# define IOAPIC_RTE_VALID_READ_MASK ( IOAPIC_RTE_DEST \| IOAPIC_RTE_MASK \| IOAPIC_RTE_TRIGGER_MODE \
144	\| IOAPIC_RTE_REMOTE_IRR \| IOAPIC_RTE_POLARITY \| IOAPIC_RTE_DELIVERY_STATUS \
145	\| IOAPIC_RTE_DEST_MODE \| IOAPIC_RTE_DELIVERY_MODE \| IOAPIC_RTE_VECTOR)
146	#elif IOAPIC_HARDWARE_VERSION == IOAPIC_HARDWARE_VERSION_ICH9
147	/** Redirection table entry - Valid write mask (incl. remote IRR). */
148	#define IOAPIC_RTE_VALID_WRITE_MASK ( IOAPIC_RTE_DEST \| IOAPIC_RTE_MASK \| IOAPIC_RTE_TRIGGER_MODE \
149	/\| IOAPIC_RTE_REMOTE_IRR /\| IOAPIC_RTE_POLARITY \| IOAPIC_RTE_DEST_MODE \
150	\| IOAPIC_RTE_DELIVERY_MODE \| IOAPIC_RTE_VECTOR)
151	/** Redirection table entry - Valid read mask (incl. ExtDestID). */
152	# define IOAPIC_RTE_VALID_READ_MASK ( IOAPIC_RTE_DEST \| IOAPIC_RTE_EXT_DEST_ID \| IOAPIC_RTE_MASK \
153	\| IOAPIC_RTE_TRIGGER_MODE \| IOAPIC_RTE_REMOTE_IRR \| IOAPIC_RTE_POLARITY \
154	\| IOAPIC_RTE_DELIVERY_STATUS \| IOAPIC_RTE_DEST_MODE \| IOAPIC_RTE_DELIVERY_MODE \
155	\| IOAPIC_RTE_VECTOR)
156	#endif
157	/** Redirection table entry - Trigger mode edge. */
158	#define IOAPIC_RTE_TRIGGER_MODE_EDGE 0
159	/** Redirection table entry - Trigger mode level. */
160	#define IOAPIC_RTE_TRIGGER_MODE_LEVEL 1
161	/** Redirection table entry - Destination mode physical. */
162	#define IOAPIC_RTE_DEST_MODE_PHYSICAL 0
163	/** Redirection table entry - Destination mode logical. */
164	#define IOAPIC_RTE_DEST_MODE_LOGICAL 1
165
166
167	/** Index of indirect registers in the I/O APIC register table. */
168	#define IOAPIC_INDIRECT_INDEX_ID 0x0
169	#define IOAPIC_INDIRECT_INDEX_VERSION 0x1
170	#if IOAPIC_HARDWARE_VERSION == IOAPIC_HARDWARE_VERSION_82093AA
171	# define IOAPIC_INDIRECT_INDEX_ARB 0x2
172	#endif
173	#define IOAPIC_INDIRECT_INDEX_REDIR_TBL_START 0x10
174	#define IOAPIC_INDIRECT_INDEX_REDIR_TBL_END 0x3F
175
176	/** Offset of direct registers in the I/O APIC MMIO space. */
177	#define IOAPIC_DIRECT_OFF_INDEX 0x00
178	#define IOAPIC_DIRECT_OFF_DATA 0x10
179	#if IOAPIC_HARDWARE_VERSION == IOAPIC_HARDWARE_VERSION_ICH9
180	# define IOAPIC_DIRECT_OFF_EOI 0x40
181	#endif
182
183	/* Use PDM critsect for now for I/O APIC locking, see @bugref{8245#c121}. */
184	#define IOAPIC_WITH_PDM_CRITSECT
185	#ifdef IOAPIC_WITH_PDM_CRITSECT
186	# define IOAPIC_LOCK(pThis, rcBusy) (pThis)->CTX_SUFF(pIoApicHlp)->pfnLock((pThis)->CTX_SUFF(pDevIns), (rcBusy))
187	# define IOAPIC_UNLOCK(pThis) (pThis)->CTX_SUFF(pIoApicHlp)->pfnUnlock((pThis)->CTX_SUFF(pDevIns))
188	#else
189	# define IOAPIC_LOCK(pThis, rcBusy) PDMCritSectEnter(&(pThis)->CritSect, (rcBusy))
190	# define IOAPIC_UNLOCK(pThis) PDMCritSectLeave(&(pThis)->CritSect)
191	#endif
192
193
194	/*********************************************************************************************************************************
195	* Structures and Typedefs *
196	*********************************************************************************************************************************/
197	/**
198	* The per-VM I/O APIC device state.
199	*/
200	typedef struct IOAPIC
201	{
202	/** The device instance - R3 Ptr. */
203	PPDMDEVINSR3 pDevInsR3;
204	/** The IOAPIC helpers - R3 Ptr. */
205	PCPDMIOAPICHLPR3 pIoApicHlpR3;
206
207	/** The device instance - R0 Ptr. */
208	PPDMDEVINSR0 pDevInsR0;
209	/** The IOAPIC helpers - R0 Ptr. */
210	PCPDMIOAPICHLPR0 pIoApicHlpR0;
211
212	/** The device instance - RC Ptr. */
213	PPDMDEVINSRC pDevInsRC;
214	/** The IOAPIC helpers - RC Ptr. */
215	PCPDMIOAPICHLPRC pIoApicHlpRC;
216
217	/** The ID register. */
218	uint8_t volatile u8Id;
219	/** The index register. */
220	uint8_t volatile u8Index;
221	/** Number of CPUs. */
222	uint8_t cCpus;
223	/* Alignment padding. */
224	uint8_t u8Padding0[5];
225
226	/** The redirection table registers. */
227	uint64_t au64RedirTable[IOAPIC_NUM_INTR_PINS];
228	/** The IRQ tags and source IDs for each pin (tracing purposes). */
229	uint32_t au32TagSrc[IOAPIC_NUM_INTR_PINS];
230
231	/** Alignment padding. */
232	uint32_t u32Padding2;
233	/** The internal IRR reflecting state of the interrupt lines. */
234	uint32_t uIrr;
235
236	#ifndef IOAPIC_WITH_PDM_CRITSECT
237	/** The critsect for updating to the RTEs. */
238	PDMCRITSECT CritSect;
239	#endif
240
241	#ifdef VBOX_WITH_STATISTICS
242	/** Number of MMIO reads in RZ. */
243	STAMCOUNTER StatMmioReadRZ;
244	/** Number of MMIO reads in R3. */
245	STAMCOUNTER StatMmioReadR3;
246
247	/** Number of MMIO writes in RZ. */
248	STAMCOUNTER StatMmioWriteRZ;
249	/** Number of MMIO writes in R3. */
250	STAMCOUNTER StatMmioWriteR3;
251
252	/** Number of SetIrq calls in RZ. */
253	STAMCOUNTER StatSetIrqRZ;
254	/** Number of SetIrq calls in R3. */
255	STAMCOUNTER StatSetIrqR3;
256
257	/** Number of SetEoi calls in RZ. */
258	STAMCOUNTER StatSetEoiRZ;
259	/** Number of SetEoi calls in R3. */
260	STAMCOUNTER StatSetEoiR3;
261
262	/** Number of redundant edge-triggered interrupts. */
263	STAMCOUNTER StatRedundantEdgeIntr;
264	/** Number of redundant level-triggered interrupts. */
265	STAMCOUNTER StatRedundantLevelIntr;
266	/** Number of suppressed level-triggered interrupts (by remote IRR). */
267	STAMCOUNTER StatSuppressedLevelIntr;
268	/** Number of returns to ring-3 due to EOI broadcast lock contention. */
269	STAMCOUNTER StatEoiContention;
270	/** Number of returns to ring-3 due to Set RTE lock contention. */
271	STAMCOUNTER StatSetRteContention;
272	/** Number of level-triggered interrupts dispatched to the local APIC(s). */
273	STAMCOUNTER StatLevelIrqSent;
274	/** Number of EOIs received for level-triggered interrupts from the local
275	* APIC(s). */
276	STAMCOUNTER StatEoiReceived;
277	#endif
278	} IOAPIC;
279	/** Pointer to IOAPIC data. */
280	typedef IOAPIC *PIOAPIC;
281	/** Pointer to a const IOAPIC data. */
282	typedef IOAPIC const *PCIOAPIC;
283	AssertCompileMemberAlignment(IOAPIC, au64RedirTable, 8);
284
285	#ifndef VBOX_DEVICE_STRUCT_TESTCASE
286
287	#if IOAPIC_HARDWARE_VERSION == IOAPIC_HARDWARE_VERSION_82093AA
288	/**
289	* Gets the arbitration register.
290	*
291	* @returns The arbitration.
292	*/
293	DECLINLINE(uint32_t) ioapicGetArb(void)
294	{
295	Log2(("IOAPIC: ioapicGetArb: returns 0\n"));
296	return 0;
297	}
298	#endif
299
300
301	/**
302	* Gets the version register.
303	*
304	* @returns The version.
305	*/
306	DECLINLINE(uint32_t) ioapicGetVersion(void)
307	{
308	uint32_t uValue = RT_MAKE_U32(IOAPIC_VERSION, IOAPIC_MAX_REDIR_ENTRIES);
309	Log2(("IOAPIC: ioapicGetVersion: returns %#RX32\n", uValue));
310	return uValue;
311	}
312
313
314	/**
315	* Sets the ID register.
316	*
317	* @param pThis Pointer to the IOAPIC instance.
318	* @param uValue The value to set.
319	*/
320	DECLINLINE(void) ioapicSetId(PIOAPIC pThis, uint32_t uValue)
321	{
322	Log2(("IOAPIC: ioapicSetId: uValue=%#RX32\n", uValue));
323	ASMAtomicWriteU8(&pThis->u8Id, (uValue >> 24) & IOAPIC_ID_MASK);
324	}
325
326
327	/**
328	* Gets the ID register.
329	*
330	* @returns The ID.
331	* @param pThis Pointer to the IOAPIC instance.
332	*/
333	DECLINLINE(uint32_t) ioapicGetId(PCIOAPIC pThis)
334	{
335	uint32_t uValue = (uint32_t)(pThis->u8Id & IOAPIC_ID_MASK) << 24;
336	Log2(("IOAPIC: ioapicGetId: returns %#RX32\n", uValue));
337	return uValue;
338	}
339
340
341	/**
342	* Sets the index register.
343	*
344	* @param pThis Pointer to the IOAPIC instance.
345	* @param uValue The value to set.
346	*/
347	DECLINLINE(void) ioapicSetIndex(PIOAPIC pThis, uint32_t uValue)
348	{
349	LogFlow(("IOAPIC: ioapicSetIndex: uValue=%#RX32\n", uValue));
350	ASMAtomicWriteU8(&pThis->u8Index, uValue & IOAPIC_INDEX_VALID_WRITE_MASK);
351	}
352
353
354	/**
355	* Gets the index register.
356	*
357	* @returns The index value.
358	*/
359	DECLINLINE(uint32_t) ioapicGetIndex(PCIOAPIC pThis)
360	{
361	uint32_t const uValue = pThis->u8Index;
362	LogFlow(("IOAPIC: ioapicGetIndex: returns %#x\n", uValue));
363	return uValue;
364	}
365
366
367	/**
368	* Signals the next pending interrupt for the specified Redirection Table Entry
369	* (RTE).
370	*
371	* @param pThis The IOAPIC instance.
372	* @param idxRte The index of the RTE.
373	*
374	* @remarks It is the responsibility of the caller to verify that an interrupt is
375	* pending for the pin corresponding to the RTE before calling this
376	* function.
377	*/
378	static void ioapicSignalIntrForRte(PIOAPIC pThis, uint8_t idxRte)
379	{
380	#ifndef IOAPIC_WITH_PDM_CRITSECT
381	Assert(PDMCritSectIsOwner(&pThis->CritSect));
382	#endif
383
384	/* Ensure the RTE isn't masked. */
385	uint64_t const u64Rte = pThis->au64RedirTable[idxRte];
386	if (!IOAPIC_RTE_IS_MASKED(u64Rte))
387	{
388	/* We cannot accept another level-triggered interrupt until remote IRR has been cleared. */
389	uint8_t const u8TriggerMode = IOAPIC_RTE_GET_TRIGGER_MODE(u64Rte);
390	if (u8TriggerMode == IOAPIC_RTE_TRIGGER_MODE_LEVEL)
391	{
392	uint8_t const u8RemoteIrr = IOAPIC_RTE_GET_REMOTE_IRR(u64Rte);
393	if (u8RemoteIrr)
394	{
395	STAM_COUNTER_INC(&pThis->StatSuppressedLevelIntr);
396	return;
397	}
398	}
399
400	uint8_t const u8Vector = IOAPIC_RTE_GET_VECTOR(u64Rte);
401	uint8_t const u8DeliveryMode = IOAPIC_RTE_GET_DELIVERY_MODE(u64Rte);
402	uint8_t const u8DestMode = IOAPIC_RTE_GET_DEST_MODE(u64Rte);
403	uint8_t const u8Polarity = IOAPIC_RTE_GET_POLARITY(u64Rte);
404	uint8_t const u8Dest = IOAPIC_RTE_GET_DEST(u64Rte);
405	uint32_t const u32TagSrc = pThis->au32TagSrc[idxRte];
406
407	Log2(("IOAPIC: Signaling %s-triggered interrupt. Dest=%#x DestMode=%s Vector=%#x (%u)\n",
408	u8TriggerMode == IOAPIC_RTE_TRIGGER_MODE_EDGE ? "edge" : "level", u8Dest,
409	u8DestMode == IOAPIC_RTE_DEST_MODE_PHYSICAL ? "physical" : "logical", u8Vector, u8Vector));
410
411	/*
412	* Deliver to the local APIC via the system/3-wire-APIC bus.
413	*/
414	int rc = pThis->CTX_SUFF(pIoApicHlp)->pfnApicBusDeliver(pThis->CTX_SUFF(pDevIns),
415	u8Dest,
416	u8DestMode,
417	u8DeliveryMode,
418	u8Vector,
419	u8Polarity,
420	u8TriggerMode,
421	u32TagSrc);
422	/* Can't reschedule to R3. */
423	Assert(rc == VINF_SUCCESS \|\| rc == VERR_APIC_INTR_DISCARDED);
424	#ifdef DEBUG_ramshankar
425	if (rc == VERR_APIC_INTR_DISCARDED)
426	AssertMsgFailed(("APIC: Interrupt discarded u8Vector=%#x (%u) u64Rte=%#RX64\n", u8Vector, u8Vector, u64Rte));
427	#endif
428
429	/*
430	* For level-triggered interrupts, we set the remote IRR bit to indicate
431	* the local APIC has accepted the interrupt.
432	*
433	* For edge-triggered interrupts, we should not clear the IRR bit as it
434	* should remain intact to reflect the state of the interrupt line.
435	* The device will explicitly transition to inactive state via the
436	* ioapicSetIrq() callback.
437	*/
438	if ( u8TriggerMode == IOAPIC_RTE_TRIGGER_MODE_LEVEL
439	&& rc == VINF_SUCCESS)
440	{
441	Assert(u8TriggerMode == IOAPIC_RTE_TRIGGER_MODE_LEVEL);
442	pThis->au64RedirTable[idxRte] \|= IOAPIC_RTE_REMOTE_IRR;
443	STAM_COUNTER_INC(&pThis->StatLevelIrqSent);
444	}
445	}
446	}
447
448
449	/**
450	* Gets the redirection table entry.
451	*
452	* @returns The redirection table entry.
453	* @param pThis Pointer to the IOAPIC instance.
454	* @param uIndex The index value.
455	*/
456	DECLINLINE(uint32_t) ioapicGetRedirTableEntry(PCIOAPIC pThis, uint32_t uIndex)
457	{
458	uint8_t const idxRte = (uIndex - IOAPIC_INDIRECT_INDEX_REDIR_TBL_START) >> 1;
459	uint32_t uValue;
460	if (!(uIndex & 1))
461	uValue = RT_LO_U32(pThis->au64RedirTable[idxRte]) & RT_LO_U32(IOAPIC_RTE_VALID_READ_MASK);
462	else
463	uValue = RT_HI_U32(pThis->au64RedirTable[idxRte]) & RT_HI_U32(IOAPIC_RTE_VALID_READ_MASK);
464
465	LogFlow(("IOAPIC: ioapicGetRedirTableEntry: uIndex=%#RX32 idxRte=%u returns %#RX32\n", uIndex, idxRte, uValue));
466	return uValue;
467	}
468
469
470	/**
471	* Sets the redirection table entry.
472	*
473	* @param pThis Pointer to the IOAPIC instance.
474	* @param uIndex The index value.
475	* @param uValue The value to set.
476	*/
477	static int ioapicSetRedirTableEntry(PIOAPIC pThis, uint32_t uIndex, uint32_t uValue)
478	{
479	uint8_t const idxRte = (uIndex - IOAPIC_INDIRECT_INDEX_REDIR_TBL_START) >> 1;
480	AssertMsg(idxRte < RT_ELEMENTS(pThis->au64RedirTable), ("Invalid index %u, expected <= %u\n", idxRte,
481	RT_ELEMENTS(pThis->au64RedirTable)));
482
483	int rc = IOAPIC_LOCK(pThis, VINF_IOM_R3_MMIO_WRITE);
484	if (rc == VINF_SUCCESS)
485	{
486	/*
487	* Write the low or high 32-bit value into the specified 64-bit RTE register,
488	* update only the valid, writable bits.
489	*
490	* We need to preserve the read-only bits as it can have dire consequences
491	* otherwise, see @bugref{8386#c24}.
492	*/
493	uint64_t const u64Rte = pThis->au64RedirTable[idxRte];
494	if (!(uIndex & 1))
495	{
496	uint32_t const u32RtePreserveLo = RT_LO_U32(u64Rte) & ~RT_LO_U32(IOAPIC_RTE_VALID_WRITE_MASK);
497	uint32_t const u32RteNewLo = (uValue & RT_LO_U32(IOAPIC_RTE_VALID_WRITE_MASK)) \| u32RtePreserveLo;
498	uint64_t const u64RteHi = u64Rte & UINT64_C(0xffffffff00000000);
499	pThis->au64RedirTable[idxRte] = u64RteHi \| u32RteNewLo;
500	}
501	else
502	{
503	uint32_t const u32RtePreserveHi = RT_HI_U32(u64Rte) & ~RT_HI_U32(IOAPIC_RTE_VALID_WRITE_MASK);
504	uint32_t const u32RteLo = RT_LO_U32(u64Rte);
505	uint64_t const u64RteNewHi = ((uint64_t)((uValue & RT_HI_U32(IOAPIC_RTE_VALID_WRITE_MASK)) \| u32RtePreserveHi) << 32);
506	pThis->au64RedirTable[idxRte] = u64RteNewHi \| u32RteLo;
507	}
508
509	/*
510	* Signal the next pending interrupt for this RTE.
511	*/
512	uint32_t const uPinMask = UINT32_C(1) << idxRte;
513	if (pThis->uIrr & uPinMask)
514	ioapicSignalIntrForRte(pThis, idxRte);
515
516	IOAPIC_UNLOCK(pThis);
517	LogFlow(("IOAPIC: ioapicSetRedirTableEntry: uIndex=%#RX32 idxRte=%u uValue=%#RX32\n", uIndex, idxRte, uValue));
518	}
519	else
520	STAM_COUNTER_INC(&pThis->StatSetRteContention);
521
522	return rc;
523	}
524
525
526	/**
527	* Gets the data register.
528	*
529	* @returns The data value.
530	* @param pThis Pointer to the IOAPIC instance.
531	*/
532	static uint32_t ioapicGetData(PCIOAPIC pThis)
533	{
534	uint8_t const uIndex = pThis->u8Index;
535	if ( uIndex >= IOAPIC_INDIRECT_INDEX_REDIR_TBL_START
536	&& uIndex <= IOAPIC_INDIRECT_INDEX_REDIR_TBL_END)
537	return ioapicGetRedirTableEntry(pThis, uIndex);
538
539	uint32_t uValue;
540	switch (uIndex)
541	{
542	case IOAPIC_INDIRECT_INDEX_ID:
543	uValue = ioapicGetId(pThis);
544	break;
545
546	case IOAPIC_INDIRECT_INDEX_VERSION:
547	uValue = ioapicGetVersion();
548	break;
549
550	#if IOAPIC_HARDWARE_VERSION == IOAPIC_HARDWARE_VERSION_82093AA
551	case IOAPIC_INDIRECT_INDEX_ARB:
552	uValue = ioapicGetArb();
553	break;
554	#endif
555
556	default:
557	uValue = UINT32_C(0xffffffff);
558	Log2(("IOAPIC: Attempt to read register at invalid index %#x\n", uIndex));
559	break;
560	}
561	return uValue;
562	}
563
564
565	/**
566	* Sets the data register.
567	*
568	* @param pThis Pointer to the IOAPIC instance.
569	* @param uValue The value to set.
570	*/
571	static int ioapicSetData(PIOAPIC pThis, uint32_t uValue)
572	{
573	uint8_t const uIndex = pThis->u8Index;
574	LogFlow(("IOAPIC: ioapicSetData: uIndex=%#x uValue=%#RX32\n", uIndex, uValue));
575
576	if ( uIndex >= IOAPIC_INDIRECT_INDEX_REDIR_TBL_START
577	&& uIndex <= IOAPIC_INDIRECT_INDEX_REDIR_TBL_END)
578	return ioapicSetRedirTableEntry(pThis, uIndex, uValue);
579
580	if (uIndex == IOAPIC_INDIRECT_INDEX_ID)
581	ioapicSetId(pThis, uValue);
582	else
583	Log2(("IOAPIC: ioapicSetData: Invalid index %#RX32, ignoring write request with uValue=%#RX32\n", uIndex, uValue));
584
585	return VINF_SUCCESS;
586	}
587
588
589	/**
590	* @interface_method_impl{PDMIOAPICREG,pfnSetEoiR3}
591	*/
592	PDMBOTHCBDECL(int) ioapicSetEoi(PPDMDEVINS pDevIns, uint8_t u8Vector)
593	{
594	PIOAPIC pThis = PDMINS_2_DATA(pDevIns, PIOAPIC);
595	STAM_COUNTER_INC(&pThis->CTX_SUFF_Z(StatSetEoi));
596	LogFlow(("IOAPIC: ioapicSetEoi: u8Vector=%#x (%u)\n", u8Vector, u8Vector));
597
598	bool fRemoteIrrCleared = false;
599	int rc = IOAPIC_LOCK(pThis, VINF_IOM_R3_MMIO_WRITE);
600	if (rc == VINF_SUCCESS)
601	{
602	for (uint8_t idxRte = 0; idxRte < RT_ELEMENTS(pThis->au64RedirTable); idxRte++)
603	{
604	uint64_t const u64Rte = pThis->au64RedirTable[idxRte];
605	if (IOAPIC_RTE_GET_VECTOR(u64Rte) == u8Vector)
606	{
607	#ifdef DEBUG_ramshankar
608	/* This assertion may trigger when restoring saved-states created using the old, incorrect I/O APIC code. */
609	Assert(IOAPIC_RTE_GET_REMOTE_IRR(u64Rte));
610	#endif
611	pThis->au64RedirTable[idxRte] &= ~IOAPIC_RTE_REMOTE_IRR;
612	fRemoteIrrCleared = true;
613	STAM_COUNTER_INC(&pThis->StatEoiReceived);
614	Log2(("IOAPIC: ioapicSetEoi: Cleared remote IRR, idxRte=%u vector=%#x (%u)\n", idxRte, u8Vector, u8Vector));
615
616	/*
617	* Signal the next pending interrupt for this RTE.
618	*/
619	uint32_t const uPinMask = UINT32_C(1) << idxRte;
620	if (pThis->uIrr & uPinMask)
621	ioapicSignalIntrForRte(pThis, idxRte);
622	}
623	}
624
625	IOAPIC_UNLOCK(pThis);
626	AssertMsg(fRemoteIrrCleared, ("Failed to clear remote IRR for vector %#x (%u)\n", u8Vector, u8Vector));
627	}
628	else
629	STAM_COUNTER_INC(&pThis->StatEoiContention);
630
631	return rc;
632	}
633
634
635	/**
636	* @interface_method_impl{PDMIOAPICREG,pfnSetIrqR3}
637	*/
638	PDMBOTHCBDECL(void) ioapicSetIrq(PPDMDEVINS pDevIns, int iIrq, int iLevel, uint32_t uTagSrc)
639	{
640	#define IOAPIC_ASSERT_IRQ(a_idxRte, a_PinMask) do { \
641	pThis->au32TagSrc[(a_idxRte)] = !pThis->au32TagSrc[(a_idxRte)] ? uTagSrc : RT_BIT_32(31); \
642	pThis->uIrr \|= a_PinMask; \
643	ioapicSignalIntrForRte(pThis, (a_idxRte)); \
644	} while (0)
645
646	PIOAPIC pThis = PDMINS_2_DATA(pDevIns, PIOAPIC);
647	LogFlow(("IOAPIC: ioapicSetIrq: iIrq=%d iLevel=%d uTagSrc=%#x\n", iIrq, iLevel, uTagSrc));
648
649	STAM_COUNTER_INC(&pThis->CTX_SUFF_Z(StatSetIrq));
650
651	if (RT_LIKELY(iIrq >= 0 && iIrq < (int)RT_ELEMENTS(pThis->au64RedirTable)))
652	{
653	int rc = IOAPIC_LOCK(pThis, VINF_SUCCESS);
654	AssertRC(rc);
655
656	uint8_t const idxRte = iIrq;
657	uint32_t const uPinMask = UINT32_C(1) << idxRte;
658	uint32_t const u32RteLo = RT_LO_U32(pThis->au64RedirTable[idxRte]);
659	uint8_t const u8TriggerMode = IOAPIC_RTE_GET_TRIGGER_MODE(u32RteLo);
660
661	bool fActive = RT_BOOL(iLevel & 1);
662	/** @todo Polarity is busted elsewhere, we need to fix that
663	* first. See @bugref{8386#c7}. */
664	#if 0
665	uint8_t const u8Polarity = IOAPIC_RTE_GET_POLARITY(u32RteLo);
666	fActive ^= u8Polarity; */
667	#endif
668	if (!fActive)
669	{
670	pThis->uIrr &= ~uPinMask;
671	IOAPIC_UNLOCK(pThis);
672	return;
673	}
674
675	bool const fFlipFlop = ((iLevel & PDM_IRQ_LEVEL_FLIP_FLOP) == PDM_IRQ_LEVEL_FLIP_FLOP);
676	uint32_t const uPrevIrr = pThis->uIrr & uPinMask;
677	if (!fFlipFlop)
678	{
679	if (u8TriggerMode == IOAPIC_RTE_TRIGGER_MODE_EDGE)
680	{
681	/*
682	* For edge-triggered interrupts, we need to act only on a low to high edge transition.
683	* See ICH9 spec. 13.5.7 "REDIR_TBL: Redirection Table (LPC I/F-D31:F0)".
684	*/
685	if (!uPrevIrr)
686	IOAPIC_ASSERT_IRQ(idxRte, uPinMask);
687	else
688	{
689	STAM_COUNTER_INC(&pThis->StatRedundantEdgeIntr);
690	Log2(("IOAPIC: Redundant edge-triggered interrupt %#x (%u)\n", idxRte, idxRte));
691	}
692	}
693	else
694	{
695	Assert(u8TriggerMode == IOAPIC_RTE_TRIGGER_MODE_LEVEL);
696
697	/*
698	* For level-triggered interrupts, redundant interrupts are not a problem
699	* and will eventually be delivered anyway after an EOI, but our PDM devices
700	* should not typically call us with no change to the level.
701	*/
702	if (!uPrevIrr)
703	{ /* likely */ }
704	else
705	{
706	STAM_COUNTER_INC(&pThis->StatRedundantLevelIntr);
707	Log2(("IOAPIC: Redundant level-triggered interrupt %#x (%u)\n", idxRte, idxRte));
708	}
709
710	IOAPIC_ASSERT_IRQ(idxRte, uPinMask);
711	}
712	}
713	else
714	{
715	/*
716	* The device is flip-flopping the interrupt line, which implies we should de-assert
717	* and assert the interrupt line. The interrupt line is left in the asserted state
718	* after a flip-flop request. The de-assert is a NOP wrts to signaling an interrupt
719	* hence just the assert is done.
720	*/
721	IOAPIC_ASSERT_IRQ(idxRte, uPinMask);
722	}
723
724	IOAPIC_UNLOCK(pThis);
725	}
726	#undef IOAPIC_ASSERT_IRQ
727	}
728
729
730	/**
731	* @interface_method_impl{PDMIOAPICREG,pfnSendMsiR3}
732	*/
733	PDMBOTHCBDECL(void) ioapicSendMsi(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, uint32_t uValue, uint32_t uTagSrc)
734	{
735	PCIOAPIC pThis = PDMINS_2_DATA(pDevIns, PCIOAPIC);
736	LogFlow(("IOAPIC: ioapicSendMsi: GCPhys=%#RGp uValue=%#RX32\n", GCPhys, uValue));
737
738	/*
739	* Parse the message from the physical address.
740	* See Intel spec. 10.11.1 "Message Address Register Format".
741	*/
742	uint8_t const u8DestAddr = (GCPhys & VBOX_MSI_ADDR_DEST_ID_MASK) >> VBOX_MSI_ADDR_DEST_ID_SHIFT;
743	uint8_t const u8DestMode = (GCPhys >> VBOX_MSI_ADDR_DEST_MODE_SHIFT) & 0x1;
744	/** @todo Check if we need to implement Redirection Hint Indicator. */
745	/* uint8_t const uRedirectHint = (GCPhys >> VBOX_MSI_ADDR_REDIRECTION_SHIFT) & 0x1; */
746
747	/*
748	* Parse the message data.
749	* See Intel spec. 10.11.2 "Message Data Register Format".
750	*/
751	uint8_t const u8Vector = (uValue & VBOX_MSI_DATA_VECTOR_MASK) >> VBOX_MSI_DATA_VECTOR_SHIFT;
752	uint8_t const u8TriggerMode = (uValue >> VBOX_MSI_DATA_TRIGGER_SHIFT) & 0x1;
753	uint8_t const u8DeliveryMode = (uValue >> VBOX_MSI_DATA_DELIVERY_MODE_SHIFT) & 0x7;
754
755	/*
756	* Deliver to the local APIC via the system/3-wire-APIC bus.
757	*/
758	int rc = pThis->CTX_SUFF(pIoApicHlp)->pfnApicBusDeliver(pDevIns,
759	u8DestAddr,
760	u8DestMode,
761	u8DeliveryMode,
762	u8Vector,
763	0 /* u8Polarity - N/A */,
764	u8TriggerMode,
765	uTagSrc);
766	/* Can't reschedule to R3. */
767	Assert(rc == VINF_SUCCESS \|\| rc == VERR_APIC_INTR_DISCARDED); NOREF(rc);
768	}
769
770
771	/**
772	* @callback_method_impl{FNIOMMMIOREAD}
773	*/
774	PDMBOTHCBDECL(int) ioapicMmioRead(PPDMDEVINS pDevIns, void pvUser, RTGCPHYS GCPhysAddr, void pv, unsigned cb)
775	{
776	PIOAPIC pThis = PDMINS_2_DATA(pDevIns, PIOAPIC);
777	STAM_COUNTER_INC(&pThis->CTX_SUFF_Z(StatMmioRead));
778	Assert(cb == 4); RT_NOREF_PV(cb); /* registered for dwords only */
779	RT_NOREF_PV(pvUser);
780
781	int rc = VINF_SUCCESS;
782	uint32_t puValue = (uint32_t )pv;
783	uint32_t offReg = GCPhysAddr & IOAPIC_MMIO_REG_MASK;
784	switch (offReg)
785	{
786	case IOAPIC_DIRECT_OFF_INDEX:
787	*puValue = ioapicGetIndex(pThis);
788	break;
789
790	case IOAPIC_DIRECT_OFF_DATA:
791	*puValue = ioapicGetData(pThis);
792	break;
793
794	default:
795	Log2(("IOAPIC: ioapicMmioRead: Invalid offset. GCPhysAddr=%#RGp offReg=%#x\n", GCPhysAddr, offReg));
796	rc = VINF_IOM_MMIO_UNUSED_FF;
797	break;
798	}
799
800	LogFlow(("IOAPIC: ioapicMmioRead: offReg=%#x, returns %#RX32\n", offReg, *puValue));
801	return rc;
802	}
803
804
805	/**
806	* @callback_method_impl{FNIOMMMIOWRITE}
807	*/
808	PDMBOTHCBDECL(int) ioapicMmioWrite(PPDMDEVINS pDevIns, void pvUser, RTGCPHYS GCPhysAddr, void const pv, unsigned cb)
809	{
810	PIOAPIC pThis = PDMINS_2_DATA(pDevIns, PIOAPIC);
811	RT_NOREF_PV(pvUser);
812
813	STAM_COUNTER_INC(&pThis->CTX_SUFF_Z(StatMmioWrite));
814
815	Assert(!(GCPhysAddr & 3));
816	Assert(cb == 4); RT_NOREF_PV(cb); /* registered for dwords only */
817
818	uint32_t const uValue = (uint32_t const )pv;
819	uint32_t const offReg = GCPhysAddr & IOAPIC_MMIO_REG_MASK;
820
821	LogFlow(("IOAPIC: ioapicMmioWrite: pThis=%p GCPhysAddr=%#RGp cb=%u uValue=%#RX32\n", pThis, GCPhysAddr, cb, uValue));
822	int rc = VINF_SUCCESS;
823	switch (offReg)
824	{
825	case IOAPIC_DIRECT_OFF_INDEX:
826	ioapicSetIndex(pThis, uValue);
827	break;
828
829	case IOAPIC_DIRECT_OFF_DATA:
830	rc = ioapicSetData(pThis, uValue);
831	break;
832
833	#if IOAPIC_HARDWARE_VERSION == IOAPIC_HARDWARE_VERSION_ICH9
834	case IOAPIC_DIRECT_OFF_EOI:
835	rc = ioapicSetEoi(pDevIns, uValue);
836	break;
837	#endif
838
839	default:
840	Log2(("IOAPIC: ioapicMmioWrite: Invalid offset. GCPhysAddr=%#RGp offReg=%#x\n", GCPhysAddr, offReg));
841	break;
842	}
843
844	return rc;
845	}
846
847
848	#ifdef IN_RING3
849
850	/** @interface_method_impl{DBGFREGDESC,pfnGet} */
851	static DECLCALLBACK(int) ioapicDbgReg_GetIndex(void *pvUser, PCDBGFREGDESC pDesc, PDBGFREGVAL pValue)
852	{
853	RT_NOREF(pDesc);
854	pValue->u32 = ioapicGetIndex(PDMINS_2_DATA((PPDMDEVINS)pvUser, PCIOAPIC));
855	return VINF_SUCCESS;
856	}
857
858
859	/** @interface_method_impl{DBGFREGDESC,pfnSet} */
860	static DECLCALLBACK(int) ioapicDbgReg_SetIndex(void *pvUser, PCDBGFREGDESC pDesc, PCDBGFREGVAL pValue, PCDBGFREGVAL pfMask)
861	{
862	RT_NOREF(pDesc, pfMask);
863	ioapicSetIndex(PDMINS_2_DATA((PPDMDEVINS)pvUser, PIOAPIC), pValue->u8);
864	return VINF_SUCCESS;
865	}
866
867
868	/** @interface_method_impl{DBGFREGDESC,pfnGet} */
869	static DECLCALLBACK(int) ioapicDbgReg_GetData(void *pvUser, PCDBGFREGDESC pDesc, PDBGFREGVAL pValue)
870	{
871	RT_NOREF(pDesc);
872	pValue->u32 = ioapicGetData((PDMINS_2_DATA((PPDMDEVINS)pvUser, PCIOAPIC)));
873	return VINF_SUCCESS;
874	}
875
876
877	/** @interface_method_impl{DBGFREGDESC,pfnSet} */
878	static DECLCALLBACK(int) ioapicDbgReg_SetData(void *pvUser, PCDBGFREGDESC pDesc, PCDBGFREGVAL pValue, PCDBGFREGVAL pfMask)
879	{
880	RT_NOREF(pDesc, pfMask);
881	return ioapicSetData(PDMINS_2_DATA((PPDMDEVINS)pvUser, PIOAPIC), pValue->u32);
882	}
883
884
885	/** @interface_method_impl{DBGFREGDESC,pfnGet} */
886	static DECLCALLBACK(int) ioapicDbgReg_GetVersion(void *pvUser, PCDBGFREGDESC pDesc, PDBGFREGVAL pValue)
887	{
888	RT_NOREF(pvUser, pDesc);
889	pValue->u32 = ioapicGetVersion();
890	return VINF_SUCCESS;
891	}
892
893
894	# if IOAPIC_HARDWARE_VERSION == IOAPIC_HARDWARE_VERSION_82093AA
895	/** @interface_method_impl{DBGFREGDESC,pfnGetArb} */
896	static DECLCALLBACK(int) ioapicDbgReg_GetArb(void *pvUser, PCDBGFREGDESC pDesc, PDBGFREGVAL pValue)
897	{
898	RT_NOREF(pvUser, pDesc);
899	pValue->u32 = ioapicGetArb(PDMINS_2_DATA((PPDMDEVINS)pvUser, PCIOAPIC));
900	return VINF_SUCCESS;
901	}
902	#endif
903
904
905	/** @interface_method_impl{DBGFREGDESC,pfnGet} */
906	static DECLCALLBACK(int) ioapicDbgReg_GetRte(void *pvUser, PCDBGFREGDESC pDesc, PDBGFREGVAL pValue)
907	{
908	PCIOAPIC pThis = PDMINS_2_DATA((PPDMDEVINS)pvUser, PCIOAPIC);
909	Assert(pDesc->offRegister < RT_ELEMENTS(pThis->au64RedirTable));
910	pValue->u64 = pThis->au64RedirTable[pDesc->offRegister];
911	return VINF_SUCCESS;
912	}
913
914
915	/** @interface_method_impl{DBGFREGDESC,pfnSet} */
916	static DECLCALLBACK(int) ioapicDbgReg_SetRte(void *pvUser, PCDBGFREGDESC pDesc, PCDBGFREGVAL pValue, PCDBGFREGVAL pfMask)
917	{
918	RT_NOREF(pfMask);
919	PIOAPIC pThis = PDMINS_2_DATA((PPDMDEVINS)pvUser, PIOAPIC);
920	/* No locks, no checks, just do it. */
921	Assert(pDesc->offRegister < RT_ELEMENTS(pThis->au64RedirTable));
922	pThis->au64RedirTable[pDesc->offRegister] = pValue->u64;
923	return VINF_SUCCESS;
924	}
925
926
927	/** IOREDTBLn sub fields. */
928	static DBGFREGSUBFIELD const g_aRteSubs[] =
929	{
930	{ "vector", 0, 8, 0, 0, NULL, NULL },
931	{ "dlvr_mode", 8, 3, 0, 0, NULL, NULL },
932	{ "dest_mode", 11, 1, 0, 0, NULL, NULL },
933	{ "dlvr_status", 12, 1, 0, DBGFREGSUBFIELD_FLAGS_READ_ONLY, NULL, NULL },
934	{ "polarity", 13, 1, 0, 0, NULL, NULL },
935	{ "remote_irr", 14, 1, 0, DBGFREGSUBFIELD_FLAGS_READ_ONLY, NULL, NULL },
936	{ "trigger_mode", 15, 1, 0, 0, NULL, NULL },
937	{ "mask", 16, 1, 0, 0, NULL, NULL },
938	# if IOAPIC_HARDWARE_VERSION == IOAPIC_HARDWARE_VERSION_ICH9
939	{ "ext_dest_id", 48, 8, 0, DBGFREGSUBFIELD_FLAGS_READ_ONLY, NULL, NULL },
940	# endif
941	{ "dest", 56, 8, 0, 0, NULL, NULL },
942	DBGFREGSUBFIELD_TERMINATOR()
943	};
944
945
946	/** Register descriptors for DBGF. */
947	static DBGFREGDESC const g_aRegDesc[] =
948	{
949	{ "index", DBGFREG_END, DBGFREGVALTYPE_U8, 0, 0, ioapicDbgReg_GetIndex, ioapicDbgReg_SetIndex, NULL, NULL },
950	{ "data", DBGFREG_END, DBGFREGVALTYPE_U32, 0, 0, ioapicDbgReg_GetData, ioapicDbgReg_SetData, NULL, NULL },
951	{ "version", DBGFREG_END, DBGFREGVALTYPE_U32, DBGFREG_FLAGS_READ_ONLY, 0, ioapicDbgReg_GetVersion, NULL, NULL, NULL },
952	# if IOAPIC_HARDWARE_VERSION == IOAPIC_HARDWARE_VERSION_82093AA
953	{ "arb", DBGFREG_END, DBGFREGVALTYPE_U32, DBGFREG_FLAGS_READ_ONLY, 0, ioapicDbgReg_GetArb, NULL, NULL, NULL },
954	# endif
955	{ "rte0", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 0, ioapicDbgReg_GetRte, ioapicDbgReg_SetRte, NULL, &g_aRteSubs[0] },
956	{ "rte1", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 1, ioapicDbgReg_GetRte, ioapicDbgReg_SetRte, NULL, &g_aRteSubs[0] },
957	{ "rte2", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 2, ioapicDbgReg_GetRte, ioapicDbgReg_SetRte, NULL, &g_aRteSubs[0] },
958	{ "rte3", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 3, ioapicDbgReg_GetRte, ioapicDbgReg_SetRte, NULL, &g_aRteSubs[0] },
959	{ "rte4", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 4, ioapicDbgReg_GetRte, ioapicDbgReg_SetRte, NULL, &g_aRteSubs[0] },
960	{ "rte5", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 5, ioapicDbgReg_GetRte, ioapicDbgReg_SetRte, NULL, &g_aRteSubs[0] },
961	{ "rte6", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 6, ioapicDbgReg_GetRte, ioapicDbgReg_SetRte, NULL, &g_aRteSubs[0] },
962	{ "rte7", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 7, ioapicDbgReg_GetRte, ioapicDbgReg_SetRte, NULL, &g_aRteSubs[0] },
963	{ "rte8", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 8, ioapicDbgReg_GetRte, ioapicDbgReg_SetRte, NULL, &g_aRteSubs[0] },
964	{ "rte9", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 9, ioapicDbgReg_GetRte, ioapicDbgReg_SetRte, NULL, &g_aRteSubs[0] },
965	{ "rte10", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 10, ioapicDbgReg_GetRte, ioapicDbgReg_SetRte, NULL, &g_aRteSubs[0] },
966	{ "rte11", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 11, ioapicDbgReg_GetRte, ioapicDbgReg_SetRte, NULL, &g_aRteSubs[0] },
967	{ "rte12", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 12, ioapicDbgReg_GetRte, ioapicDbgReg_SetRte, NULL, &g_aRteSubs[0] },
968	{ "rte13", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 13, ioapicDbgReg_GetRte, ioapicDbgReg_SetRte, NULL, &g_aRteSubs[0] },
969	{ "rte14", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 14, ioapicDbgReg_GetRte, ioapicDbgReg_SetRte, NULL, &g_aRteSubs[0] },
970	{ "rte15", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 15, ioapicDbgReg_GetRte, ioapicDbgReg_SetRte, NULL, &g_aRteSubs[0] },
971	{ "rte16", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 16, ioapicDbgReg_GetRte, ioapicDbgReg_SetRte, NULL, &g_aRteSubs[0] },
972	{ "rte17", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 17, ioapicDbgReg_GetRte, ioapicDbgReg_SetRte, NULL, &g_aRteSubs[0] },
973	{ "rte18", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 18, ioapicDbgReg_GetRte, ioapicDbgReg_SetRte, NULL, &g_aRteSubs[0] },
974	{ "rte19", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 19, ioapicDbgReg_GetRte, ioapicDbgReg_SetRte, NULL, &g_aRteSubs[0] },
975	{ "rte20", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 20, ioapicDbgReg_GetRte, ioapicDbgReg_SetRte, NULL, &g_aRteSubs[0] },
976	{ "rte21", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 21, ioapicDbgReg_GetRte, ioapicDbgReg_SetRte, NULL, &g_aRteSubs[0] },
977	{ "rte22", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 22, ioapicDbgReg_GetRte, ioapicDbgReg_SetRte, NULL, &g_aRteSubs[0] },
978	{ "rte23", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 23, ioapicDbgReg_GetRte, ioapicDbgReg_SetRte, NULL, &g_aRteSubs[0] },
979	DBGFREGDESC_TERMINATOR()
980	};
981
982
983	/**
984	* @callback_method_impl{FNDBGFHANDLERDEV}
985	*/
986	static DECLCALLBACK(void) ioapicR3DbgInfo(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
987	{
988	RT_NOREF(pszArgs);
989	PCIOAPIC pThis = PDMINS_2_DATA(pDevIns, PIOAPIC);
990	LogFlow(("IOAPIC: ioapicR3DbgInfo: pThis=%p pszArgs=%s\n", pThis, pszArgs));
991
992	pHlp->pfnPrintf(pHlp, "I/O APIC at %#010x:\n", IOAPIC_MMIO_BASE_PHYSADDR);
993
994	uint32_t const uId = ioapicGetId(pThis);
995	pHlp->pfnPrintf(pHlp, " ID = %#RX32\n", uId);
996	pHlp->pfnPrintf(pHlp, " ID = %#x\n", IOAPIC_ID_GET_ID(uId));
997
998	uint32_t const uVer = ioapicGetVersion();
999	pHlp->pfnPrintf(pHlp, " Version = %#RX32\n", uVer);
1000	pHlp->pfnPrintf(pHlp, " Version = %#x\n", IOAPIC_VER_GET_VER(uVer));
1001	pHlp->pfnPrintf(pHlp, " Pin Assert Reg. Support = %RTbool\n", IOAPIC_VER_HAS_PRQ(uVer));
1002	pHlp->pfnPrintf(pHlp, " Max. Redirection Entry = %u\n", IOAPIC_VER_GET_MRE(uVer));
1003
1004	# if IOAPIC_HARDWARE_VERSION == IOAPIC_HARDWARE_VERSION_82093AA
1005	uint32_t const uArb = ioapicGetArb();
1006	pHlp->pfnPrintf(pHlp, " Arbitration = %#RX32\n", uArb);
1007	pHlp->pfnPrintf(pHlp, " Arbitration ID = %#x\n", IOAPIC_ARB_GET_ID(uArb));
1008	# endif
1009
1010	pHlp->pfnPrintf(pHlp, " Current index = %#x\n", ioapicGetIndex(pThis));
1011
1012	pHlp->pfnPrintf(pHlp, " I/O Redirection Table and IRR:\n");
1013	pHlp->pfnPrintf(pHlp, " idx dst_mode dst_addr mask irr trigger rirr polar dlvr_st dlvr_mode vector\n");
1014
1015	for (uint8_t idxRte = 0; idxRte < RT_ELEMENTS(pThis->au64RedirTable); idxRte++)
1016	{
1017	static const char * const s_apszDeliveryModes[] =
1018	{
1019	"Fixed ",
1020	"LowPri",
1021	"SMI ",
1022	"Rsvd ",
1023	"NMI ",
1024	"INIT ",
1025	"Rsvd ",
1026	"ExtINT"
1027	};
1028
1029	const uint64_t u64Rte = pThis->au64RedirTable[idxRte];
1030	const char *pszDestMode = IOAPIC_RTE_GET_DEST_MODE(u64Rte) == 0 ? "phys" : "log ";
1031	const uint8_t uDest = IOAPIC_RTE_GET_DEST(u64Rte);
1032	const uint8_t uMask = IOAPIC_RTE_GET_MASK(u64Rte);
1033	const char *pszTriggerMode = IOAPIC_RTE_GET_TRIGGER_MODE(u64Rte) == 0 ? "edge " : "level";
1034	const uint8_t uRemoteIrr = IOAPIC_RTE_GET_REMOTE_IRR(u64Rte);
1035	const char *pszPolarity = IOAPIC_RTE_GET_POLARITY(u64Rte) == 0 ? "acthi" : "actlo";
1036	const char *pszDeliveryStatus = IOAPIC_RTE_GET_DELIVERY_STATUS(u64Rte) == 0 ? "idle" : "pend";
1037	const uint8_t uDeliveryMode = IOAPIC_RTE_GET_DELIVERY_MODE(u64Rte);
1038	Assert(uDeliveryMode < RT_ELEMENTS(s_apszDeliveryModes));
1039	const char *pszDeliveryMode = s_apszDeliveryModes[uDeliveryMode];
1040	const uint8_t uVector = IOAPIC_RTE_GET_VECTOR(u64Rte);
1041
1042	pHlp->pfnPrintf(pHlp, " %02d %s %02x %u %u %s %u %s %s %s %3u (%016llx)\n",
1043	idxRte,
1044	pszDestMode,
1045	uDest,
1046	uMask,
1047	(pThis->uIrr >> idxRte) & 1,
1048	pszTriggerMode,
1049	uRemoteIrr,
1050	pszPolarity,
1051	pszDeliveryStatus,
1052	pszDeliveryMode,
1053	uVector,
1054	u64Rte);
1055	}
1056	}
1057
1058
1059	/**
1060	* @copydoc FNSSMDEVSAVEEXEC
1061	*/
1062	static DECLCALLBACK(int) ioapicR3SaveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
1063	{
1064	PCIOAPIC pThis = PDMINS_2_DATA(pDevIns, PCIOAPIC);
1065	LogFlow(("IOAPIC: ioapicR3SaveExec\n"));
1066
1067	SSMR3PutU32(pSSM, pThis->uIrr);
1068	SSMR3PutU8(pSSM, pThis->u8Id);
1069	SSMR3PutU8(pSSM, pThis->u8Index);
1070	for (uint8_t idxRte = 0; idxRte < RT_ELEMENTS(pThis->au64RedirTable); idxRte++)
1071	SSMR3PutU64(pSSM, pThis->au64RedirTable[idxRte]);
1072
1073	return VINF_SUCCESS;
1074	}
1075
1076
1077	/**
1078	* @copydoc FNSSMDEVLOADEXEC
1079	*/
1080	static DECLCALLBACK(int) ioapicR3LoadExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
1081	{
1082	PIOAPIC pThis = PDMINS_2_DATA(pDevIns, PIOAPIC);
1083	LogFlow(("APIC: apicR3LoadExec: uVersion=%u uPass=%#x\n", uVersion, uPass));
1084
1085	Assert(uPass == SSM_PASS_FINAL);
1086	NOREF(uPass);
1087
1088	/* Weed out invalid versions. */
1089	if ( uVersion != IOAPIC_SAVED_STATE_VERSION
1090	&& uVersion != IOAPIC_SAVED_STATE_VERSION_VBOX_50)
1091	{
1092	LogRel(("IOAPIC: ioapicR3LoadExec: Invalid/unrecognized saved-state version %u (%#x)\n", uVersion, uVersion));
1093	return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
1094	}
1095
1096	if (uVersion == IOAPIC_SAVED_STATE_VERSION)
1097	SSMR3GetU32(pSSM, (uint32_t *)&pThis->uIrr);
1098
1099	SSMR3GetU8(pSSM, (uint8_t *)&pThis->u8Id);
1100	SSMR3GetU8(pSSM, (uint8_t *)&pThis->u8Index);
1101	for (uint8_t idxRte = 0; idxRte < RT_ELEMENTS(pThis->au64RedirTable); idxRte++)
1102	SSMR3GetU64(pSSM, &pThis->au64RedirTable[idxRte]);
1103
1104	return VINF_SUCCESS;
1105	}
1106
1107
1108	/**
1109	* @interface_method_impl{PDMDEVREG,pfnReset}
1110	*/
1111	static DECLCALLBACK(void) ioapicR3Reset(PPDMDEVINS pDevIns)
1112	{
1113	PIOAPIC pThis = PDMINS_2_DATA(pDevIns, PIOAPIC);
1114	LogFlow(("IOAPIC: ioapicR3Reset: pThis=%p\n", pThis));
1115
1116	/* There might be devices threads calling ioapicSetIrq() in parallel, hence the lock. */
1117	IOAPIC_LOCK(pThis, VERR_IGNORED);
1118
1119	pThis->uIrr = 0;
1120	pThis->u8Index = 0;
1121	pThis->u8Id = 0;
1122
1123	for (uint8_t idxRte = 0; idxRte < RT_ELEMENTS(pThis->au64RedirTable); idxRte++)
1124	{
1125	pThis->au64RedirTable[idxRte] = IOAPIC_RTE_MASK;
1126	pThis->au32TagSrc[idxRte] = 0;
1127	}
1128
1129	IOAPIC_UNLOCK(pThis);
1130	}
1131
1132
1133	/**
1134	* @interface_method_impl{PDMDEVREG,pfnRelocate}
1135	*/
1136	static DECLCALLBACK(void) ioapicR3Relocate(PPDMDEVINS pDevIns, RTGCINTPTR offDelta)
1137	{
1138	RT_NOREF(offDelta);
1139	PIOAPIC pThis = PDMINS_2_DATA(pDevIns, PIOAPIC);
1140	LogFlow(("IOAPIC: ioapicR3Relocate: pThis=%p offDelta=%RGi\n", pThis, offDelta));
1141
1142	pThis->pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
1143	pThis->pIoApicHlpRC = pThis->pIoApicHlpR3->pfnGetRCHelpers(pDevIns);
1144	}
1145
1146
1147	/**
1148	* @interface_method_impl{PDMDEVREG,pfnDestruct}
1149	*/
1150	static DECLCALLBACK(int) ioapicR3Destruct(PPDMDEVINS pDevIns)
1151	{
1152	PIOAPIC pThis = PDMINS_2_DATA(pDevIns, PIOAPIC);
1153	LogFlow(("IOAPIC: ioapicR3Destruct: pThis=%p\n", pThis));
1154	PDMDEV_CHECK_VERSIONS_RETURN_QUIET(pDevIns);
1155
1156	# ifndef IOAPIC_WITH_PDM_CRITSECT
1157	/*
1158	* Destroy the RTE critical section.
1159	*/
1160	if (PDMCritSectIsInitialized(&pThis->CritSect))
1161	PDMR3CritSectDelete(&pThis->CritSect);
1162	# else
1163	RT_NOREF_PV(pThis);
1164	# endif
1165
1166	return VINF_SUCCESS;
1167	}
1168
1169
1170	/**
1171	* @interface_method_impl{PDMDEVREG,pfnConstruct}
1172	*/
1173	static DECLCALLBACK(int) ioapicR3Construct(PPDMDEVINS pDevIns, int iInstance, PCFGMNODE pCfg)
1174	{
1175	RT_NOREF(iInstance);
1176	PIOAPIC pThis = PDMINS_2_DATA(pDevIns, PIOAPIC);
1177	LogFlow(("IOAPIC: ioapicR3Construct: pThis=%p iInstance=%d\n", pThis, iInstance));
1178	Assert(iInstance == 0);
1179
1180	/*
1181	* Initialize the state data.
1182	*/
1183	pThis->pDevInsR3 = pDevIns;
1184	pThis->pDevInsR0 = PDMDEVINS_2_R0PTR(pDevIns);
1185	pThis->pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
1186
1187	/*
1188	* Validate and read the configuration.
1189	*/
1190	PDMDEV_VALIDATE_CONFIG_RETURN(pDevIns, "NumCPUs\|RZEnabled", "");
1191
1192	/* The number of CPUs is currently unused, but left in CFGM and saved-state in case an ID of 0 is
1193	upsets some guest which we haven't yet tested. */
1194	uint32_t cCpus;
1195	int rc = CFGMR3QueryU32Def(pCfg, "NumCPUs", &cCpus, 1);
1196	if (RT_FAILURE(rc))
1197	return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to query integer value \"NumCPUs\""));
1198	pThis->cCpus = (uint8_t)cCpus;
1199
1200	bool fRZEnabled;
1201	rc = CFGMR3QueryBoolDef(pCfg, "RZEnabled", &fRZEnabled, true);
1202	if (RT_FAILURE(rc))
1203	return PDMDEV_SET_ERROR(pDevIns, rc,
1204	N_("Configuration error: Failed to query boolean value \"RZEnabled\""));
1205
1206	Log2(("IOAPIC: cCpus=%u fRZEnabled=%RTbool\n", cCpus, fRZEnabled));
1207
1208	/*
1209	* We will use our own critical section for the IOAPIC device.
1210	*/
1211	rc = PDMDevHlpSetDeviceCritSect(pDevIns, PDMDevHlpCritSectGetNop(pDevIns));
1212	AssertRCReturn(rc, rc);
1213
1214	# ifndef IOAPIC_WITH_PDM_CRITSECT
1215	/*
1216	* Setup the critical section to protect concurrent writes to the RTEs.
1217	*/
1218	rc = PDMDevHlpCritSectInit(pDevIns, &pThis->CritSect, RT_SRC_POS, "IOAPIC");
1219	if (RT_FAILURE(rc))
1220	return PDMDevHlpVMSetError(pDevIns, rc, RT_SRC_POS, N_("IOAPIC: Failed to create critical section. rc=%Rrc"), rc);
1221	# endif
1222
1223	/*
1224	* Register the IOAPIC.
1225	*/
1226	PDMIOAPICREG IoApicReg;
1227	RT_ZERO(IoApicReg);
1228	IoApicReg.u32Version = PDM_IOAPICREG_VERSION;
1229	IoApicReg.pfnSetIrqR3 = ioapicSetIrq;
1230	IoApicReg.pfnSendMsiR3 = ioapicSendMsi;
1231	IoApicReg.pfnSetEoiR3 = ioapicSetEoi;
1232	if (fRZEnabled)
1233	{
1234	IoApicReg.pszSetIrqRC = "ioapicSetIrq";
1235	IoApicReg.pszSetIrqR0 = "ioapicSetIrq";
1236
1237	IoApicReg.pszSendMsiRC = "ioapicSendMsi";
1238	IoApicReg.pszSendMsiR0 = "ioapicSendMsi";
1239
1240	IoApicReg.pszSetEoiRC = "ioapicSetEoi";
1241	IoApicReg.pszSetEoiR0 = "ioapicSetEoi";
1242	}
1243	rc = PDMDevHlpIOAPICRegister(pDevIns, &IoApicReg, &pThis->pIoApicHlpR3);
1244	if (RT_FAILURE(rc))
1245	{
1246	AssertMsgFailed(("IOAPIC: PDMDevHlpIOAPICRegister failed! rc=%Rrc\n", rc));
1247	return rc;
1248	}
1249
1250	/*
1251	* Register MMIO callbacks.
1252	*/
1253	rc = PDMDevHlpMMIORegister(pDevIns, IOAPIC_MMIO_BASE_PHYSADDR, IOAPIC_MMIO_SIZE, pThis,
1254	IOMMMIO_FLAGS_READ_DWORD \| IOMMMIO_FLAGS_WRITE_DWORD_ZEROED, ioapicMmioWrite, ioapicMmioRead,
1255	"I/O APIC");
1256	if (RT_SUCCESS(rc))
1257	{
1258	if (fRZEnabled)
1259	{
1260	pThis->pIoApicHlpRC = pThis->pIoApicHlpR3->pfnGetRCHelpers(pDevIns);
1261	rc = PDMDevHlpMMIORegisterRC(pDevIns, IOAPIC_MMIO_BASE_PHYSADDR, IOAPIC_MMIO_SIZE, NIL_RTRCPTR /* pvUser */,
1262	"ioapicMmioWrite", "ioapicMmioRead");
1263	AssertRCReturn(rc, rc);
1264
1265	pThis->pIoApicHlpR0 = pThis->pIoApicHlpR3->pfnGetR0Helpers(pDevIns);
1266	rc = PDMDevHlpMMIORegisterR0(pDevIns, IOAPIC_MMIO_BASE_PHYSADDR, IOAPIC_MMIO_SIZE, NIL_RTR0PTR /* pvUser */,
1267	"ioapicMmioWrite", "ioapicMmioRead");
1268	AssertRCReturn(rc, rc);
1269	}
1270	}
1271	else
1272	{
1273	LogRel(("IOAPIC: PDMDevHlpMMIORegister failed! rc=%Rrc\n", rc));
1274	return rc;
1275	}
1276
1277	/*
1278	* Register saved-state callbacks.
1279	*/
1280	rc = PDMDevHlpSSMRegister(pDevIns, IOAPIC_SAVED_STATE_VERSION, sizeof(*pThis), ioapicR3SaveExec, ioapicR3LoadExec);
1281	if (RT_FAILURE(rc))
1282	{
1283	LogRel(("IOAPIC: PDMDevHlpSSMRegister failed! rc=%Rrc\n", rc));
1284	return rc;
1285	}
1286
1287	/*
1288	* Register debugger info callback.
1289	*/
1290	rc = PDMDevHlpDBGFInfoRegister(pDevIns, "ioapic", "Display IO APIC state.", ioapicR3DbgInfo);
1291	AssertRCReturn(rc, rc);
1292
1293	/*
1294	* Register debugger register access.
1295	*/
1296	rc = PDMDevHlpDBGFRegRegister(pDevIns, g_aRegDesc); AssertRC(rc);
1297	AssertRCReturn(rc, rc);
1298
1299	# ifdef VBOX_WITH_STATISTICS
1300	/*
1301	* Statistics.
1302	*/
1303	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMmioReadRZ, STAMTYPE_COUNTER, "/Devices/IOAPIC/RZ/MmioReadRZ", STAMUNIT_OCCURENCES, "Number of IOAPIC MMIO reads in RZ.");
1304	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMmioWriteRZ, STAMTYPE_COUNTER, "/Devices/IOAPIC/RZ/MmioWriteRZ", STAMUNIT_OCCURENCES, "Number of IOAPIC MMIO writes in RZ.");
1305	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatSetIrqRZ, STAMTYPE_COUNTER, "/Devices/IOAPIC/RZ/SetIrqRZ", STAMUNIT_OCCURENCES, "Number of IOAPIC SetIrq calls in RZ.");
1306	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatSetEoiRZ, STAMTYPE_COUNTER, "/Devices/IOAPIC/RZ/SetEoiRZ", STAMUNIT_OCCURENCES, "Number of IOAPIC SetEoi calls in RZ.");
1307
1308	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMmioReadR3, STAMTYPE_COUNTER, "/Devices/IOAPIC/R3/MmioReadR3", STAMUNIT_OCCURENCES, "Number of IOAPIC MMIO reads in R3");
1309	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMmioWriteR3, STAMTYPE_COUNTER, "/Devices/IOAPIC/R3/MmioWriteR3", STAMUNIT_OCCURENCES, "Number of IOAPIC MMIO writes in R3.");
1310	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatSetIrqR3, STAMTYPE_COUNTER, "/Devices/IOAPIC/R3/SetIrqR3", STAMUNIT_OCCURENCES, "Number of IOAPIC SetIrq calls in R3.");
1311	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatSetEoiR3, STAMTYPE_COUNTER, "/Devices/IOAPIC/R3/SetEoiR3", STAMUNIT_OCCURENCES, "Number of IOAPIC SetEoi calls in R3.");
1312
1313	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatRedundantEdgeIntr, STAMTYPE_COUNTER, "/Devices/IOAPIC/RedundantEdgeIntr", STAMUNIT_OCCURENCES, "Number of redundant edge-triggered interrupts (no IRR change).");
1314	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatRedundantLevelIntr, STAMTYPE_COUNTER, "/Devices/IOAPIC/RedundantLevelIntr", STAMUNIT_OCCURENCES, "Number of redundant level-triggered interrupts (no IRR change).");
1315	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatSuppressedLevelIntr, STAMTYPE_COUNTER, "/Devices/IOAPIC/SuppressedLevelIntr", STAMUNIT_OCCURENCES, "Number of suppressed level-triggered interrupts by remote IRR.");
1316
1317	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatEoiContention, STAMTYPE_COUNTER, "/Devices/IOAPIC/CritSect/ContentionSetEoi", STAMUNIT_OCCURENCES, "Number of times the critsect is busy during EOI writes causing trips to R3.");
1318	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatSetRteContention, STAMTYPE_COUNTER, "/Devices/IOAPIC/CritSect/ContentionSetRte", STAMUNIT_OCCURENCES, "Number of times the critsect is busy during RTE writes causing trips to R3.");
1319
1320	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatLevelIrqSent, STAMTYPE_COUNTER, "/Devices/IOAPIC/LevelIntr/Sent", STAMUNIT_OCCURENCES, "Number of level-triggered interrupts sent to the local APIC(s).");
1321	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatEoiReceived, STAMTYPE_COUNTER, "/Devices/IOAPIC/LevelIntr/Recv", STAMUNIT_OCCURENCES, "Number of EOIs received for level-triggered interrupts from the local APIC(s).");
1322	# endif
1323
1324	/*
1325	* Init. the device state.
1326	*/
1327	LogRel(("IOAPIC: Using implementation 2.0!\n"));
1328	ioapicR3Reset(pDevIns);
1329
1330	return VINF_SUCCESS;
1331	}
1332
1333
1334	/**
1335	* IO APIC device registration structure.
1336	*/
1337	const PDMDEVREG g_DeviceIOAPIC =
1338	{
1339	/* u32Version */
1340	PDM_DEVREG_VERSION,
1341	/* szName */
1342	"ioapic",
1343	/* szRCMod */
1344	"VBoxDDRC.rc",
1345	/* szR0Mod */
1346	"VBoxDDR0.r0",
1347	/* pszDescription */
1348	"I/O Advanced Programmable Interrupt Controller (IO-APIC) Device",
1349	/* fFlags */
1350	PDM_DEVREG_FLAGS_HOST_BITS_DEFAULT \| PDM_DEVREG_FLAGS_GUEST_BITS_32_64 \| PDM_DEVREG_FLAGS_PAE36
1351	\| PDM_DEVREG_FLAGS_RC \| PDM_DEVREG_FLAGS_R0,
1352	/* fClass */
1353	PDM_DEVREG_CLASS_PIC,
1354	/* cMaxInstances */
1355	1,
1356	/* cbInstance */
1357	sizeof(IOAPIC),
1358	/* pfnConstruct */
1359	ioapicR3Construct,
1360	/* pfnDestruct */
1361	ioapicR3Destruct,
1362	/* pfnRelocate */
1363	ioapicR3Relocate,
1364	/* pfnMemSetup */
1365	NULL,
1366	/* pfnPowerOn */
1367	NULL,
1368	/* pfnReset */
1369	ioapicR3Reset,
1370	/* pfnSuspend */
1371	NULL,
1372	/* pfnResume */
1373	NULL,
1374	/* pfnAttach */
1375	NULL,
1376	/* pfnDetach */
1377	NULL,
1378	/* pfnQueryInterface. */
1379	NULL,
1380	/* pfnInitComplete */
1381	NULL,
1382	/* pfnPowerOff */
1383	NULL,
1384	/* pfnSoftReset */
1385	NULL,
1386	/* u32VersionEnd */
1387	PDM_DEVREG_VERSION
1388	};
1389
1390	#endif /* IN_RING3 */
1391
1392	#endif /* !VBOX_DEVICE_STRUCT_TESTCASE */
1393

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source: vbox/trunk/src/VBox/Devices/PC/DevIoApic.cpp@ 63495

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