DevIoApic.cpp@ 62564

Last change on this file since 62564 was 62563, checked in by vboxsync, 8 years ago
Devices: Rename I/O APIC files.
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1	/* $Id: DevIoApic.cpp 62563 2016-07-26 14:12:44Z vboxsync $ */
2	/** @file
3	* IO APIC - Input/Output Advanced Programmable Interrupt Controller.
4	*/
5
6	/*
7	* Copyright (C) 2016 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18
19	/*********************************************************************************************************************************
20	* Header Files *
21	*********************************************************************************************************************************/
22	#define LOG_GROUP LOG_GROUP_DEV_IOAPIC
23	#include <VBox/log.h>
24	#include <VBox/vmm/hm.h>
25	#include <VBox/msi.h>
26	#include <VBox/vmm/pdmdev.h>
27
28	#include "VBoxDD.h"
29	#include <iprt/x86.h>
30
31
32	/*********************************************************************************************************************************
33	* Defined Constants And Macros *
34	*********************************************************************************************************************************/
35	/** The current IO APIC saved state version. */
36	#define IOAPIC_SAVED_STATE_VERSION 2
37	/** The saved state version used by VirtualBox 5.0 and
38	* earlier. */
39	#define IOAPIC_SAVED_STATE_VERSION_VBOX_50 1
40
41	/** Implementation specified by the "Intel I/O Controller Hub 9
42	* (ICH9) Family" */
43	#define IOAPIC_HARDWARE_VERSION_ICH9 1
44	/** Implementation specified by the "82093AA I/O Advanced Programmable Interrupt
45	Controller" */
46	#define IOAPIC_HARDWARE_VERSION_82093AA 2
47	/** The IO APIC implementation to use. */
48	#define IOAPIC_HARDWARE_VERSION IOAPIC_HARDWARE_VERSION_ICH9
49
50	#if IOAPIC_HARDWARE_VERSION == IOAPIC_HARDWARE_VERSION_82093AA
51	/** The version. */
52	# define IOAPIC_VERSION 0x11
53	/** The ID mask. */
54	# define IOAPIC_ID_MASK 0x0f
55	#elif IOAPIC_HARDWARE_VERSION == IOAPIC_HARDWARE_VERSION_ICH9
56	/** The version. */
57	# define IOAPIC_VERSION 0x20
58	/** The ID mask. */
59	# define IOAPIC_ID_MASK 0xff
60	#else
61	# error "Implement me"
62	#endif
63
64	/** The default MMIO base physical address. */
65	#define IOAPIC_MMIO_BASE_PHYSADDR UINT64_C(0xfec00000)
66	/** The size of the MMIO range. */
67	#define IOAPIC_MMIO_SIZE X86_PAGE_4K_SIZE
68	/** The mask for getting direct registers from physical address. */
69	#define IOAPIC_MMIO_REG_MASK 0xff
70
71	/** The number of interrupt input pins. */
72	#define IOAPIC_NUM_INTR_PINS 24
73	/** Maximum redirection entires. */
74	#define IOAPIC_MAX_REDIR_ENTRIES (IOAPIC_NUM_INTR_PINS - 1)
75
76	/** Version register - Gets the version. */
77	#define IOAPIC_VER_GET_VER(a_Reg) ((a_Reg) & 0xff)
78	/** Version register - Gets the maximum redirection entry. */
79	#define IOAPIC_VER_GET_MRE(a_Reg) (((a_Reg) >> 16) & 0xff)
80	/** Version register - Gets whether Pin Assertion Register (PRQ) is
81	* supported. */
82	#define IOAPIC_VER_HAS_PRQ(a_Reg) RT_BOOL((a_Reg) & RT_BIT_32(15))
83
84	/** Index register - Valid write mask. */
85	#define IOAPIC_INDEX_VALID_WRITE_MASK UINT32_C(0xff)
86
87	/** Arbitration register - Gets the ID. */
88	#define IOAPIC_ARB_GET_ID(a_Reg) ((a_Reg) >> 24 & 0xf)
89
90	/** ID register - Gets the ID. */
91	#define IOAPIC_ID_GET_ID(a_Reg) ((a_Reg) >> 24 & IOAPIC_ID_MASK)
92
93	/** Redirection table entry - Vector. */
94	#define IOAPIC_RTE_VECTOR UINT64_C(0xff)
95	/** Redirection table entry - Delivery mode. */
96	#define IOAPIC_RTE_DELIVERY_MODE (RT_BIT_64(8) \| RT_BIT_64(9) \| RT_BIT_64(10))
97	/** Redirection table entry - Destination mode. */
98	#define IOAPIC_RTE_DEST_MODE RT_BIT_64(11)
99	/** Redirection table entry - Delivery status. */
100	#define IOAPIC_RTE_DELIVERY_STATUS RT_BIT_64(12)
101	/** Redirection table entry - Interrupt input pin polarity. */
102	#define IOAPIC_RTE_POLARITY RT_BIT_64(13)
103	/** Redirection table entry - Remote IRR. */
104	#define IOAPIC_RTE_REMOTE_IRR RT_BIT_64(14)
105	/** Redirection table entry - Trigger Mode. */
106	#define IOAPIC_RTE_TRIGGER_MODE RT_BIT_64(15)
107	/** Redirection table entry - the mask bit number. */
108	#define IOAPIC_RTE_MASK_BIT 16
109	/** Redirection table entry - the mask. */
110	#define IOAPIC_RTE_MASK RT_BIT_64(IOAPIC_RTE_MASK_BIT)
111	/** Redirection table entry - Extended Destination ID. */
112	#define IOAPIC_RTE_EXT_DEST_ID UINT64_C(0x00ff000000000000)
113	/** Redirection table entry - Destination. */
114	#define IOAPIC_RTE_DEST UINT64_C(0xff00000000000000)
115
116	/** Redirection table entry - Gets the destination. */
117	#define IOAPIC_RTE_GET_DEST(a_Reg) ((a_Reg) >> 56 & 0xff)
118	/** Redirection table entry - Gets the mask flag. */
119	#define IOAPIC_RTE_GET_MASK(a_Reg) (((a_Reg) >> IOAPIC_RTE_MASK_BIT) & 0x1)
120	/** Redirection table entry - Checks whether it's masked. */
121	#define IOAPIC_RTE_IS_MASKED(a_Reg) ((a_Reg) & IOAPIC_RTE_MASK)
122	/** Redirection table entry - Gets the trigger mode. */
123	#define IOAPIC_RTE_GET_TRIGGER_MODE(a_Reg) (((a_Reg) >> 15) & 0x1)
124	/** Redirection table entry - Gets the remote IRR flag. */
125	#define IOAPIC_RTE_GET_REMOTE_IRR(a_Reg) (((a_Reg) >> 14) & 0x1)
126	/** Redirection table entry - Gets the interrupt pin polarity. */
127	#define IOAPIC_RTE_GET_POLARITY(a_Reg) (((a_Reg) >> 13) & 0x1)
128	/** Redirection table entry - Gets the delivery status. */
129	#define IOAPIC_RTE_GET_DELIVERY_STATUS(a_Reg) (((a_Reg) >> 12) & 0x1)
130	/** Redirection table entry - Gets the destination mode. */
131	#define IOAPIC_RTE_GET_DEST_MODE(a_Reg) (((a_Reg) >> 11) & 0x1)
132	/** Redirection table entry - Gets the delivery mode. */
133	#define IOAPIC_RTE_GET_DELIVERY_MODE(a_Reg) (((a_Reg) >> 8) & 0x7)
134	/** Redirection table entry - Gets the vector. */
135	#define IOAPIC_RTE_GET_VECTOR(a_Reg) ((a_Reg) & IOAPIC_RTE_VECTOR)
136	/** Redirection table entry - Valid write mask. */
137	#define IOAPIC_RTE_VALID_WRITE_MASK ( IOAPIC_RTE_DEST \| IOAPIC_RTE_MASK \| IOAPIC_RTE_TRIGGER_MODE \
138	\| IOAPIC_RTE_POLARITY \| IOAPIC_RTE_DEST_MODE \| IOAPIC_RTE_DELIVERY_MODE \
139	\| IOAPIC_RTE_VECTOR)
140
141	#if IOAPIC_HARDWARE_VERSION == IOAPIC_HARDWARE_VERSION_82093AA
142	/** Redirection table entry - Valid read mask. */
143	# define IOAPIC_RTE_VALID_READ_MASK ( IOAPIC_RTE_DEST \| IOAPIC_RTE_MASK \| IOAPIC_RTE_TRIGGER_MODE \
144	\| IOAPIC_RTE_REMOTE_IRR \| IOAPIC_RTE_POLARITY \| IOAPIC_RTE_DELIVERY_STATUS \
145	\| IOAPIC_RTE_DEST_MODE \| IOAPIC_RTE_DELIVERY_MODE \| IOAPIC_RTE_VECTOR)
146	#elif IOAPIC_HARDWARE_VERSION == IOAPIC_HARDWARE_VERSION_ICH9
147	/** Redirection table entry - Valid read mask. */
148	# define IOAPIC_RTE_VALID_READ_MASK ( IOAPIC_RTE_DEST \| IOAPIC_RTE_EXT_DEST_ID \| IOAPIC_RTE_MASK \
149	\| IOAPIC_RTE_TRIGGER_MODE \| IOAPIC_RTE_REMOTE_IRR \| IOAPIC_RTE_POLARITY \
150	\| IOAPIC_RTE_DELIVERY_STATUS \| IOAPIC_RTE_DEST_MODE \| IOAPIC_RTE_DELIVERY_MODE \
151	\| IOAPIC_RTE_VECTOR)
152	#endif
153	/** Redirection table entry - Trigger mode edge. */
154	#define IOAPIC_RTE_TRIGGER_MODE_EDGE 0
155	/** Redirection table entry - Trigger mode level. */
156	#define IOAPIC_RTE_TRIGGER_MODE_LEVEL 1
157	/** Redirection table entry - Destination mode physical. */
158	#define IOAPIC_RTE_DEST_MODE_PHYSICAL 0
159	/** Redirection table entry - Destination mode logical. */
160	#define IOAPIC_RTE_DEST_MODE_LOGICAL 1
161
162
163	/** Index of indirect registers in the I/O APIC register table. */
164	#define IOAPIC_INDIRECT_INDEX_ID 0x0
165	#define IOAPIC_INDIRECT_INDEX_VERSION 0x1
166	#if IOAPIC_HARDWARE_VERSION == IOAPIC_HARDWARE_VERSION_82093AA
167	# define IOAPIC_INDIRECT_INDEX_ARB 0x2
168	#endif
169	#define IOAPIC_INDIRECT_INDEX_REDIR_TBL_START 0x10
170	#define IOAPIC_INDIRECT_INDEX_REDIR_TBL_END 0x3F
171
172	/** Offset of direct registers in the I/O APIC MMIO space. */
173	#define IOAPIC_DIRECT_OFF_INDEX 0x00
174	#define IOAPIC_DIRECT_OFF_DATA 0x10
175	#if IOAPIC_HARDWARE_VERSION == IOAPIC_HARDWARE_VERSION_ICH9
176	# define IOAPIC_DIRECT_OFF_EOI 0x40
177	#endif
178
179	/* Use PDM critsect for now for I/O APIC locking, see @bugref{8245#c121}. */
180	#define IOAPIC_WITH_PDM_CRITSECT
181	#ifdef IOAPIC_WITH_PDM_CRITSECT
182	# define IOAPIC_LOCK(pThis, rcBusy) (pThis)->CTX_SUFF(pIoApicHlp)->pfnLock((pThis)->CTX_SUFF(pDevIns), (rcBusy))
183	# define IOAPIC_UNLOCK(pThis) (pThis)->CTX_SUFF(pIoApicHlp)->pfnUnlock((pThis)->CTX_SUFF(pDevIns))
184	#else
185	# define IOAPIC_LOCK(pThis, rcBusy) PDMCritSectEnter(&(pThis)->CritSect, (rcBusy))
186	# define IOAPIC_UNLOCK(pThis) PDMCritSectLeave(&(pThis)->CritSect)
187	#endif
188
189
190	/*********************************************************************************************************************************
191	* Structures and Typedefs *
192	*********************************************************************************************************************************/
193	/**
194	* The per-VM I/O APIC device state.
195	*/
196	typedef struct IOAPIC
197	{
198	/** The device instance - R3 Ptr. */
199	PPDMDEVINSR3 pDevInsR3;
200	/** The IOAPIC helpers - R3 Ptr. */
201	PCPDMIOAPICHLPR3 pIoApicHlpR3;
202
203	/** The device instance - R0 Ptr. */
204	PPDMDEVINSR0 pDevInsR0;
205	/** The IOAPIC helpers - R0 Ptr. */
206	PCPDMIOAPICHLPR0 pIoApicHlpR0;
207
208	/** The device instance - RC Ptr. */
209	PPDMDEVINSRC pDevInsRC;
210	/** The IOAPIC helpers - RC Ptr. */
211	PCPDMIOAPICHLPRC pIoApicHlpRC;
212
213	/** The ID register. */
214	uint8_t volatile u8Id;
215	/** The index register. */
216	uint8_t volatile u8Index;
217	/** Number of CPUs. */
218	uint8_t cCpus;
219	/* Alignment padding. */
220	uint8_t u8Padding0[5];
221
222	/** The redirection table registers. */
223	uint64_t au64RedirTable[IOAPIC_NUM_INTR_PINS];
224	/** The IRQ tags and source IDs for each pin (tracing purposes). */
225	uint32_t au32TagSrc[IOAPIC_NUM_INTR_PINS];
226
227	/** Alignment padding. */
228	uint32_t u32Padding2;
229	/** The internal IRR reflecting state of the interrupt lines. */
230	uint32_t uIrr;
231
232	#ifndef IOAPIC_WITH_PDM_CRITSECT
233	/** The critsect for updating to the RTEs. */
234	PDMCRITSECT CritSect;
235	#endif
236
237	#ifdef VBOX_WITH_STATISTICS
238	/** Number of MMIO reads in RZ. */
239	STAMCOUNTER StatMmioReadRZ;
240	/** Number of MMIO reads in R3. */
241	STAMCOUNTER StatMmioReadR3;
242
243	/** Number of MMIO writes in RZ. */
244	STAMCOUNTER StatMmioWriteRZ;
245	/** Number of MMIO writes in R3. */
246	STAMCOUNTER StatMmioWriteR3;
247
248	/** Number of SetIrq calls in RZ. */
249	STAMCOUNTER StatSetIrqRZ;
250	/** Number of SetIrq calls in R3. */
251	STAMCOUNTER StatSetIrqR3;
252
253	/** Number of SetEoi calls in RZ. */
254	STAMCOUNTER StatSetEoiRZ;
255	/** Number of SetEoi calls in R3. */
256	STAMCOUNTER StatSetEoiR3;
257
258	/** Number of redundant edge-triggered interrupts. */
259	STAMCOUNTER StatRedundantEdgeIntr;
260	/** Number of redundant level-triggered interrupts. */
261	STAMCOUNTER StatRedundantLevelIntr;
262	/** Number of suppressed level-triggered interrupts (by remote IRR). */
263	STAMCOUNTER StatSuppressedLevelIntr;
264	/** Number of returns to ring-3 due to EOI broadcast lock contention. */
265	STAMCOUNTER StatEoiContention;
266	/** Number of returns to ring-3 due to Set RTE lock contention. */
267	STAMCOUNTER StatSetRteContention;
268	/** Number of level-triggered interrupts dispatched to the local APIC(s). */
269	STAMCOUNTER StatLevelIrqSent;
270	/** Number of EOIs received for level-triggered interrupts from the local
271	* APIC(s). */
272	STAMCOUNTER StatEoiReceived;
273	#endif
274	} IOAPIC;
275	/** Pointer to IOAPIC data. */
276	typedef IOAPIC *PIOAPIC;
277	/** Pointer to a const IOAPIC data. */
278	typedef IOAPIC const *PCIOAPIC;
279	AssertCompileMemberAlignment(IOAPIC, au64RedirTable, 8);
280
281	#ifndef VBOX_DEVICE_STRUCT_TESTCASE
282
283	#if IOAPIC_HARDWARE_VERSION == IOAPIC_HARDWARE_VERSION_82093AA
284	/**
285	* Gets the arbitration register.
286	*
287	* @returns The arbitration.
288	*/
289	DECLINLINE(uint32_t) ioapicGetArb(void)
290	{
291	Log2(("IOAPIC: ioapicGetArb: returns 0\n"));
292	return 0;
293	}
294	#endif
295
296
297	/**
298	* Gets the version register.
299	*
300	* @returns The version.
301	*/
302	DECLINLINE(uint32_t) ioapicGetVersion(void)
303	{
304	uint32_t uValue = RT_MAKE_U32(IOAPIC_VERSION, IOAPIC_MAX_REDIR_ENTRIES);
305	Log2(("IOAPIC: ioapicGetVersion: returns %#RX32\n", uValue));
306	return uValue;
307	}
308
309
310	/**
311	* Sets the ID register.
312	*
313	* @param pThis Pointer to the IOAPIC instance.
314	* @param uValue The value to set.
315	*/
316	DECLINLINE(void) ioapicSetId(PIOAPIC pThis, uint32_t uValue)
317	{
318	Log2(("IOAPIC: ioapicSetId: uValue=%#RX32\n", uValue));
319	ASMAtomicWriteU8(&pThis->u8Id, (uValue >> 24) & IOAPIC_ID_MASK);
320	}
321
322
323	/**
324	* Gets the ID register.
325	*
326	* @returns The ID.
327	* @param pThis Pointer to the IOAPIC instance.
328	*/
329	DECLINLINE(uint32_t) ioapicGetId(PCIOAPIC pThis)
330	{
331	uint32_t uValue = (uint32_t)(pThis->u8Id & IOAPIC_ID_MASK) << 24;
332	Log2(("IOAPIC: ioapicGetId: returns %#RX32\n", uValue));
333	return uValue;
334	}
335
336
337	/**
338	* Sets the index register.
339	*
340	* @param pThis Pointer to the IOAPIC instance.
341	* @param uValue The value to set.
342	*/
343	DECLINLINE(void) ioapicSetIndex(PIOAPIC pThis, uint32_t uValue)
344	{
345	LogFlow(("IOAPIC: ioapicSetIndex: uValue=%#RX32\n", uValue));
346	ASMAtomicWriteU8(&pThis->u8Index, uValue & IOAPIC_INDEX_VALID_WRITE_MASK);
347	}
348
349
350	/**
351	* Gets the index register.
352	*
353	* @returns The index value.
354	*/
355	DECLINLINE(uint32_t) ioapicGetIndex(PCIOAPIC pThis)
356	{
357	uint32_t const uValue = pThis->u8Index;
358	LogFlow(("IOAPIC: ioapicGetIndex: returns %#x\n", uValue));
359	return uValue;
360	}
361
362
363	/**
364	* Signals the next pending interrupt for the specified Redirection Table Entry
365	* (RTE).
366	*
367	* @param pThis The IOAPIC instance.
368	* @param idxRte The index of the RTE.
369	*
370	* @remarks It is the responsibility of the caller to verify that an interrupt is
371	* pending for the pin corresponding to the RTE before calling this
372	* function.
373	*/
374	static void ioapicSignalIntrForRte(PIOAPIC pThis, uint8_t idxRte)
375	{
376	#ifndef IOAPIC_WITH_PDM_CRITSECT
377	Assert(PDMCritSectIsOwner(&pThis->CritSect));
378	#endif
379
380	/* Ensure the RTE isn't masked. */
381	uint64_t const u64Rte = pThis->au64RedirTable[idxRte];
382	if (!IOAPIC_RTE_IS_MASKED(u64Rte))
383	{
384	/* We cannot accept another level-triggered interrupt until remote IRR has been cleared. */
385	uint8_t const u8TriggerMode = IOAPIC_RTE_GET_TRIGGER_MODE(u64Rte);
386	if (u8TriggerMode == IOAPIC_RTE_TRIGGER_MODE_LEVEL)
387	{
388	uint8_t const u8RemoteIrr = IOAPIC_RTE_GET_REMOTE_IRR(u64Rte);
389	if (u8RemoteIrr)
390	{
391	STAM_COUNTER_INC(&pThis->StatSuppressedLevelIntr);
392	return;
393	}
394	}
395
396	uint8_t const u8Vector = IOAPIC_RTE_GET_VECTOR(u64Rte);
397	uint8_t const u8DeliveryMode = IOAPIC_RTE_GET_DELIVERY_MODE(u64Rte);
398	uint8_t const u8DestMode = IOAPIC_RTE_GET_DEST_MODE(u64Rte);
399	uint8_t const u8Polarity = IOAPIC_RTE_GET_POLARITY(u64Rte);
400	uint8_t const u8Dest = IOAPIC_RTE_GET_DEST(u64Rte);
401	uint32_t const u32TagSrc = pThis->au32TagSrc[idxRte];
402
403	Log2(("IOAPIC: Signaling %s-triggered interrupt. Dest=%#x DestMode=%s Vector=%#x (%u)",
404	u8TriggerMode == IOAPIC_RTE_TRIGGER_MODE_EDGE ? "edge" : "level", u8Dest,
405	u8DestMode == IOAPIC_RTE_DEST_MODE_PHYSICAL ? "physical" : "logical", u8Vector, u8Vector));
406
407	/*
408	* Deliver to the local APIC via the system/3-wire-APIC bus.
409	*/
410	int rc = pThis->CTX_SUFF(pIoApicHlp)->pfnApicBusDeliver(pThis->CTX_SUFF(pDevIns),
411	u8Dest,
412	u8DestMode,
413	u8DeliveryMode,
414	u8Vector,
415	u8Polarity,
416	u8TriggerMode,
417	u32TagSrc);
418	/* Can't reschedule to R3. */
419	Assert(rc == VINF_SUCCESS \|\| rc == VERR_APIC_INTR_DISCARDED);
420	#ifdef DEBUG_ramshankar
421	if (rc == VERR_APIC_INTR_DISCARDED)
422	AssertMsgFailed(("APIC: Interrupt discarded u8Vector=%#x (%u) u64Rte=%#RX64\n", u8Vector, u8Vector, u64Rte));
423	#endif
424
425	/*
426	* For level-triggered interrupts, we set the remote IRR bit to indicate
427	* the local APIC has accepted the interrupt.
428	*
429	* For edge-triggered interrupts, we should not clear the IRR bit as it
430	* should remain intact to reflect the state of the interrupt line.
431	* The device will explicitly transition to inactive state via the
432	* ioapicSetIrq() callback.
433	*/
434	if ( u8TriggerMode == IOAPIC_RTE_TRIGGER_MODE_LEVEL
435	&& rc == VINF_SUCCESS)
436	{
437	Assert(u8TriggerMode == IOAPIC_RTE_TRIGGER_MODE_LEVEL);
438	pThis->au64RedirTable[idxRte] \|= IOAPIC_RTE_REMOTE_IRR;
439	STAM_COUNTER_INC(&pThis->StatLevelIrqSent);
440	}
441	}
442	}
443
444
445	/**
446	* Gets the redirection table entry.
447	*
448	* @returns The redirection table entry.
449	* @param pThis Pointer to the IOAPIC instance.
450	* @param uIndex The index value.
451	*/
452	DECLINLINE(uint32_t) ioapicGetRedirTableEntry(PCIOAPIC pThis, uint32_t uIndex)
453	{
454	uint8_t const idxRte = (uIndex - IOAPIC_INDIRECT_INDEX_REDIR_TBL_START) >> 1;
455	uint32_t uValue;
456	if (!(uIndex & 1))
457	uValue = RT_LO_U32(pThis->au64RedirTable[idxRte]) & RT_LO_U32(IOAPIC_RTE_VALID_READ_MASK);
458	else
459	uValue = RT_HI_U32(pThis->au64RedirTable[idxRte]) & RT_HI_U32(IOAPIC_RTE_VALID_READ_MASK);
460
461	LogFlow(("IOAPIC: ioapicGetRedirTableEntry: uIndex=%#RX32 idxRte=%u returns %#RX32\n", uIndex, idxRte, uValue));
462	return uValue;
463	}
464
465
466	/**
467	* Sets the redirection table entry.
468	*
469	* @param pThis Pointer to the IOAPIC instance.
470	* @param uIndex The index value.
471	* @param uValue The value to set.
472	*/
473	static int ioapicSetRedirTableEntry(PIOAPIC pThis, uint32_t uIndex, uint32_t uValue)
474	{
475	uint8_t const idxRte = (uIndex - IOAPIC_INDIRECT_INDEX_REDIR_TBL_START) >> 1;
476	AssertMsg(idxRte < RT_ELEMENTS(pThis->au64RedirTable), ("Invalid index %u, expected <= %u\n", idxRte,
477	RT_ELEMENTS(pThis->au64RedirTable)));
478
479	int rc = IOAPIC_LOCK(pThis, VINF_IOM_R3_MMIO_WRITE);
480	if (rc == VINF_SUCCESS)
481	{
482	/*
483	* Write the low or high 32-bit value into the specified 64-bit RTE register,
484	* update only the valid, writable bits.
485	*
486	* We need to preserve the read-only bits as it can have dire consequences
487	* otherwise, see @bugref{8386#c24}.
488	*/
489	uint64_t const u64Rte = pThis->au64RedirTable[idxRte];
490	if (!(uIndex & 1))
491	{
492	uint32_t const u32RtePreserveLo = RT_LO_U32(u64Rte) & ~RT_LO_U32(IOAPIC_RTE_VALID_WRITE_MASK);
493	uint32_t const u32RteNewLo = (uValue & RT_LO_U32(IOAPIC_RTE_VALID_WRITE_MASK)) \| u32RtePreserveLo;
494	uint64_t const u64RteHi = u64Rte & UINT64_C(0xffffffff00000000);
495	pThis->au64RedirTable[idxRte] = u64RteHi \| u32RteNewLo;
496	}
497	else
498	{
499	uint32_t const u32RtePreserveHi = RT_HI_U32(u64Rte) & ~RT_HI_U32(IOAPIC_RTE_VALID_WRITE_MASK);
500	uint32_t const u32RteLo = RT_LO_U32(u64Rte);
501	uint64_t const u64RteNewHi = ((uint64_t)((uValue & RT_HI_U32(IOAPIC_RTE_VALID_WRITE_MASK)) \| u32RtePreserveHi) << 32);
502	pThis->au64RedirTable[idxRte] = u64RteNewHi \| u32RteLo;
503	}
504
505	/*
506	* Signal the next pending interrupt for this RTE.
507	*/
508	uint32_t const uPinMask = UINT32_C(1) << idxRte;
509	if (pThis->uIrr & uPinMask)
510	ioapicSignalIntrForRte(pThis, idxRte);
511
512	IOAPIC_UNLOCK(pThis);
513	LogFlow(("IOAPIC: ioapicSetRedirTableEntry: uIndex=%#RX32 idxRte=%u uValue=%#RX32\n", uIndex, idxRte, uValue));
514	}
515	else
516	STAM_COUNTER_INC(&pThis->StatSetRteContention);
517
518	return rc;
519	}
520
521
522	/**
523	* Gets the data register.
524	*
525	* @returns The data value.
526	* @param pThis Pointer to the IOAPIC instance.
527	*/
528	static uint32_t ioapicGetData(PCIOAPIC pThis)
529	{
530	uint8_t const uIndex = pThis->u8Index;
531	if ( uIndex >= IOAPIC_INDIRECT_INDEX_REDIR_TBL_START
532	&& uIndex <= IOAPIC_INDIRECT_INDEX_REDIR_TBL_END)
533	return ioapicGetRedirTableEntry(pThis, uIndex);
534
535	uint32_t uValue;
536	switch (uIndex)
537	{
538	case IOAPIC_INDIRECT_INDEX_ID:
539	uValue = ioapicGetId(pThis);
540	break;
541
542	case IOAPIC_INDIRECT_INDEX_VERSION:
543	uValue = ioapicGetVersion();
544	break;
545
546	#if IOAPIC_HARDWARE_VERSION == IOAPIC_HARDWARE_VERSION_82093AA
547	case IOAPIC_INDIRECT_INDEX_ARB:
548	uValue = ioapicGetArb();
549	break;
550	#endif
551
552	default:
553	uValue = UINT32_C(0xffffffff);
554	Log2(("IOAPIC: Attempt to read register at invalid index %#x\n", uIndex));
555	break;
556	}
557	return uValue;
558	}
559
560
561	/**
562	* Sets the data register.
563	*
564	* @param pThis Pointer to the IOAPIC instance.
565	* @param uValue The value to set.
566	*/
567	static int ioapicSetData(PIOAPIC pThis, uint32_t uValue)
568	{
569	uint8_t const uIndex = pThis->u8Index;
570	LogFlow(("IOAPIC: ioapicSetData: uIndex=%#x uValue=%#RX32\n", uIndex, uValue));
571
572	if ( uIndex >= IOAPIC_INDIRECT_INDEX_REDIR_TBL_START
573	&& uIndex <= IOAPIC_INDIRECT_INDEX_REDIR_TBL_END)
574	return ioapicSetRedirTableEntry(pThis, uIndex, uValue);
575
576	if (uIndex == IOAPIC_INDIRECT_INDEX_ID)
577	ioapicSetId(pThis, uValue);
578	else
579	Log2(("IOAPIC: ioapicSetData: Invalid index %#RX32, ignoring write request with uValue=%#RX32\n", uIndex, uValue));
580
581	return VINF_SUCCESS;
582	}
583
584
585	/**
586	* @interface_method_impl{PDMIOAPICREG,pfnSetEoiR3}
587	*/
588	PDMBOTHCBDECL(int) ioapicSetEoi(PPDMDEVINS pDevIns, uint8_t u8Vector)
589	{
590	PIOAPIC pThis = PDMINS_2_DATA(pDevIns, PIOAPIC);
591	STAM_COUNTER_INC(&pThis->CTX_SUFF_Z(StatSetEoi));
592	LogFlow(("IOAPIC: ioapicSetEoi: u8Vector=%#x (%u)\n", u8Vector, u8Vector));
593
594	bool fRemoteIrrCleared = false;
595	int rc = IOAPIC_LOCK(pThis, VINF_IOM_R3_MMIO_WRITE);
596	if (rc == VINF_SUCCESS)
597	{
598	for (uint8_t idxRte = 0; idxRte < RT_ELEMENTS(pThis->au64RedirTable); idxRte++)
599	{
600	uint64_t const u64Rte = pThis->au64RedirTable[idxRte];
601	if (IOAPIC_RTE_GET_VECTOR(u64Rte) == u8Vector)
602	{
603	#ifdef DEBUG_ramshankar
604	/* This assertion may trigger when restoring saved-states created using the old, incorrect I/O APIC code. */
605	Assert(IOAPIC_RTE_GET_REMOTE_IRR(u64Rte));
606	#endif
607	pThis->au64RedirTable[idxRte] &= ~IOAPIC_RTE_REMOTE_IRR;
608	fRemoteIrrCleared = true;
609	STAM_COUNTER_INC(&pThis->StatEoiReceived);
610	Log2(("IOAPIC: ioapicSetEoi: Cleared remote IRR, idxRte=%u vector=%#x (%u)\n", idxRte, u8Vector, u8Vector));
611
612	/*
613	* Signal the next pending interrupt for this RTE.
614	*/
615	uint32_t const uPinMask = UINT32_C(1) << idxRte;
616	if (pThis->uIrr & uPinMask)
617	ioapicSignalIntrForRte(pThis, idxRte);
618	}
619	}
620
621	IOAPIC_UNLOCK(pThis);
622	AssertMsg(fRemoteIrrCleared, ("Failed to clear remote IRR for vector %#x (%u)\n", u8Vector, u8Vector));
623	}
624	else
625	STAM_COUNTER_INC(&pThis->StatEoiContention);
626
627	return rc;
628	}
629
630
631	/**
632	* @interface_method_impl{PDMIOAPICREG,pfnSetIrqR3}
633	*/
634	PDMBOTHCBDECL(void) ioapicSetIrq(PPDMDEVINS pDevIns, int iIrq, int iLevel, uint32_t uTagSrc)
635	{
636	#define IOAPIC_ASSERT_IRQ(a_idxRte, a_PinMask) do { \
637	pThis->au32TagSrc[(a_idxRte)] = !pThis->au32TagSrc[(a_idxRte)] ? uTagSrc : RT_BIT_32(31); \
638	pThis->uIrr \|= a_PinMask; \
639	ioapicSignalIntrForRte(pThis, (a_idxRte)); \
640	} while (0)
641
642	PIOAPIC pThis = PDMINS_2_DATA(pDevIns, PIOAPIC);
643	LogFlow(("IOAPIC: ioapicSetIrq: iIrq=%d iLevel=%d uTagSrc=%#x\n", iIrq, iLevel, uTagSrc));
644
645	STAM_COUNTER_INC(&pThis->CTX_SUFF_Z(StatSetIrq));
646
647	if (RT_LIKELY(iIrq >= 0 && iIrq < (int)RT_ELEMENTS(pThis->au64RedirTable)))
648	{
649	int rc = IOAPIC_LOCK(pThis, VINF_SUCCESS);
650	AssertRC(rc);
651
652	uint8_t const idxRte = iIrq;
653	uint32_t const uPinMask = UINT32_C(1) << idxRte;
654	uint32_t const u32RteLo = RT_LO_U32(pThis->au64RedirTable[idxRte]);
655	uint8_t const u8TriggerMode = IOAPIC_RTE_GET_TRIGGER_MODE(u32RteLo);
656
657	bool fActive = RT_BOOL(iLevel & 1);
658	/** @todo Polarity is busted elsewhere, we need to fix that
659	* first. See @bugref{8386#c7}. */
660	#if 0
661	uint8_t const u8Polarity = IOAPIC_RTE_GET_POLARITY(u32RteLo);
662	fActive ^= u8Polarity; */
663	#endif
664	if (!fActive)
665	{
666	pThis->uIrr &= ~uPinMask;
667	IOAPIC_UNLOCK(pThis);
668	return;
669	}
670
671	bool const fFlipFlop = ((iLevel & PDM_IRQ_LEVEL_FLIP_FLOP) == PDM_IRQ_LEVEL_FLIP_FLOP);
672	uint32_t const uPrevIrr = pThis->uIrr & uPinMask;
673	if (!fFlipFlop)
674	{
675	if (u8TriggerMode == IOAPIC_RTE_TRIGGER_MODE_EDGE)
676	{
677	/*
678	* For edge-triggered interrupts, we need to act only on a low to high edge transition.
679	* See ICH9 spec. 13.5.7 "REDIR_TBL: Redirection Table (LPC I/F-D31:F0)".
680	*/
681	if (!uPrevIrr)
682	IOAPIC_ASSERT_IRQ(idxRte, uPinMask);
683	else
684	{
685	STAM_COUNTER_INC(&pThis->StatRedundantEdgeIntr);
686	Log2(("IOAPIC: Redundant edge-triggered interrupt %#x (%u)\n", idxRte, idxRte));
687	}
688	}
689	else
690	{
691	Assert(u8TriggerMode == IOAPIC_RTE_TRIGGER_MODE_LEVEL);
692
693	/*
694	* For level-triggered interrupts, redundant interrupts are not a problem
695	* and will eventually be delivered anyway after an EOI, but our PDM devices
696	* should not typically call us with no change to the level.
697	*/
698	if (!uPrevIrr)
699	{ /* likely */ }
700	else
701	{
702	STAM_COUNTER_INC(&pThis->StatRedundantLevelIntr);
703	Log2(("IOAPIC: Redundant level-triggered interrupt %#x (%u)\n", idxRte, idxRte));
704	}
705
706	IOAPIC_ASSERT_IRQ(idxRte, uPinMask);
707	}
708	}
709	else
710	{
711	/*
712	* The device is flip-flopping the interrupt line, which implies we should de-assert
713	* and assert the interrupt line. The interrupt line is left in the asserted state
714	* after a flip-flop request. The de-assert is a NOP wrts to signaling an interrupt
715	* hence just the assert is done.
716	*/
717	IOAPIC_ASSERT_IRQ(idxRte, uPinMask);
718	}
719
720	IOAPIC_UNLOCK(pThis);
721	}
722	#undef IOAPIC_ASSERT_IRQ
723	}
724
725
726	/**
727	* @interface_method_impl{PDMIOAPICREG,pfnSendMsiR3}
728	*/
729	PDMBOTHCBDECL(void) ioapicSendMsi(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, uint32_t uValue, uint32_t uTagSrc)
730	{
731	PCIOAPIC pThis = PDMINS_2_DATA(pDevIns, PCIOAPIC);
732	LogFlow(("IOAPIC: ioapicSendMsi: GCPhys=%#RGp uValue=%#RX32\n", GCPhys, uValue));
733
734	/*
735	* Parse the message from the physical address.
736	* See Intel spec. 10.11.1 "Message Address Register Format".
737	*/
738	uint8_t const u8DestAddr = (GCPhys & VBOX_MSI_ADDR_DEST_ID_MASK) >> VBOX_MSI_ADDR_DEST_ID_SHIFT;
739	uint8_t const u8DestMode = (GCPhys >> VBOX_MSI_ADDR_DEST_MODE_SHIFT) & 0x1;
740	/** @todo Check if we need to implement Redirection Hint Indicator. */
741	/* uint8_t const uRedirectHint = (GCPhys >> VBOX_MSI_ADDR_REDIRECTION_SHIFT) & 0x1; */
742
743	/*
744	* Parse the message data.
745	* See Intel spec. 10.11.2 "Message Data Register Format".
746	*/
747	uint8_t const u8Vector = (uValue & VBOX_MSI_DATA_VECTOR_MASK) >> VBOX_MSI_DATA_VECTOR_SHIFT;
748	uint8_t const u8TriggerMode = (uValue >> VBOX_MSI_DATA_TRIGGER_SHIFT) & 0x1;
749	uint8_t const u8DeliveryMode = (uValue >> VBOX_MSI_DATA_DELIVERY_MODE_SHIFT) & 0x7;
750
751	/*
752	* Deliver to the local APIC via the system/3-wire-APIC bus.
753	*/
754	int rc = pThis->CTX_SUFF(pIoApicHlp)->pfnApicBusDeliver(pDevIns,
755	u8DestAddr,
756	u8DestMode,
757	u8DeliveryMode,
758	u8Vector,
759	0 /* u8Polarity - N/A */,
760	u8TriggerMode,
761	uTagSrc);
762	/* Can't reschedule to R3. */
763	Assert(rc == VINF_SUCCESS \|\| rc == VERR_APIC_INTR_DISCARDED); NOREF(rc);
764	}
765
766
767	/**
768	* @callback_method_impl{FNIOMMMIOREAD}
769	*/
770	PDMBOTHCBDECL(int) ioapicMmioRead(PPDMDEVINS pDevIns, void pvUser, RTGCPHYS GCPhysAddr, void pv, unsigned cb)
771	{
772	PIOAPIC pThis = PDMINS_2_DATA(pDevIns, PIOAPIC);
773	STAM_COUNTER_INC(&pThis->CTX_SUFF_Z(StatMmioRead));
774
775	int rc = VINF_SUCCESS;
776	uint32_t puValue = (uint32_t )pv;
777	uint32_t offReg = GCPhysAddr & IOAPIC_MMIO_REG_MASK;
778	switch (offReg)
779	{
780	case IOAPIC_DIRECT_OFF_INDEX:
781	*puValue = ioapicGetIndex(pThis);
782	break;
783
784	case IOAPIC_DIRECT_OFF_DATA:
785	*puValue = ioapicGetData(pThis);
786	break;
787
788	default:
789	Log2(("IOAPIC: ioapicMmioRead: Invalid offset. GCPhysAddr=%#RGp offReg=%#x\n", GCPhysAddr, offReg));
790	rc = VINF_IOM_MMIO_UNUSED_FF;
791	break;
792	}
793
794	LogFlow(("IOAPIC: ioapicMmioRead: offReg=%#x, returns %#RX32\n", offReg, *puValue));
795	return rc;
796	}
797
798
799	/**
800	* @callback_method_impl{FNIOMMMIOWRITE}
801	*/
802	PDMBOTHCBDECL(int) ioapicMmioWrite(PPDMDEVINS pDevIns, void pvUser, RTGCPHYS GCPhysAddr, void const pv, unsigned cb)
803	{
804	PIOAPIC pThis = PDMINS_2_DATA(pDevIns, PIOAPIC);
805
806	STAM_COUNTER_INC(&pThis->CTX_SUFF_Z(StatMmioWrite));
807
808	Assert(!(GCPhysAddr & 3));
809	Assert(cb == 4);
810
811	uint32_t const uValue = (uint32_t const )pv;
812	uint32_t const offReg = GCPhysAddr & IOAPIC_MMIO_REG_MASK;
813
814	LogFlow(("IOAPIC: ioapicMmioWrite: pThis=%p GCPhysAddr=%#RGp cb=%u uValue=%#RX32\n", pThis, GCPhysAddr, cb, uValue));
815	int rc = VINF_SUCCESS;
816	switch (offReg)
817	{
818	case IOAPIC_DIRECT_OFF_INDEX:
819	ioapicSetIndex(pThis, uValue);
820	break;
821
822	case IOAPIC_DIRECT_OFF_DATA:
823	rc = ioapicSetData(pThis, uValue);
824	break;
825
826	#if IOAPIC_HARDWARE_VERSION == IOAPIC_HARDWARE_VERSION_ICH9
827	case IOAPIC_DIRECT_OFF_EOI:
828	rc = ioapicSetEoi(pDevIns, uValue);
829	break;
830	#endif
831
832	default:
833	Log2(("IOAPIC: ioapicMmioWrite: Invalid offset. GCPhysAddr=%#RGp offReg=%#x\n", GCPhysAddr, offReg));
834	break;
835	}
836
837	return rc;
838	}
839
840
841	#ifdef IN_RING3
842	/** @interface_method_impl{DBGFREGDESC,pfnGet} */
843	static DECLCALLBACK(int) ioapicDbgReg_GetIndex(void *pvUser, PCDBGFREGDESC pDesc, PDBGFREGVAL pValue)
844	{
845	pValue->u32 = ioapicGetIndex(PDMINS_2_DATA((PPDMDEVINS)pvUser, PCIOAPIC));
846	return VINF_SUCCESS;
847	}
848
849	/** @interface_method_impl{DBGFREGDESC,pfnSet} */
850	static DECLCALLBACK(int) ioapicDbgReg_SetIndex(void *pvUser, PCDBGFREGDESC pDesc, PCDBGFREGVAL pValue, PCDBGFREGVAL pfMask)
851	{
852	ioapicSetIndex(PDMINS_2_DATA((PPDMDEVINS)pvUser, PIOAPIC), pValue->u8);
853	return VINF_SUCCESS;
854	}
855
856	/** @interface_method_impl{DBGFREGDESC,pfnGet} */
857	static DECLCALLBACK(int) ioapicDbgReg_GetData(void *pvUser, PCDBGFREGDESC pDesc, PDBGFREGVAL pValue)
858	{
859	pValue->u32 = ioapicGetData((PDMINS_2_DATA((PPDMDEVINS)pvUser, PCIOAPIC)));
860	return VINF_SUCCESS;
861	}
862
863	/** @interface_method_impl{DBGFREGDESC,pfnSet} */
864	static DECLCALLBACK(int) ioapicDbgReg_SetData(void *pvUser, PCDBGFREGDESC pDesc, PCDBGFREGVAL pValue, PCDBGFREGVAL pfMask)
865	{
866	return ioapicSetData(PDMINS_2_DATA((PPDMDEVINS)pvUser, PIOAPIC), pValue->u32);
867	}
868
869	/** @interface_method_impl{DBGFREGDESC,pfnGet} */
870	static DECLCALLBACK(int) ioapicDbgReg_GetVersion(void *pvUser, PCDBGFREGDESC pDesc, PDBGFREGVAL pValue)
871	{
872	pValue->u32 = ioapicGetVersion();
873	return VINF_SUCCESS;
874	}
875
876	/** @interface_method_impl{DBGFREGDESC,pfnGet} */
877	static DECLCALLBACK(int) ioapicDbgReg_GetArb(void *pvUser, PCDBGFREGDESC pDesc, PDBGFREGVAL pValue)
878	{
879	#if IOAPIC_HARDWARE_VERSION == IOAPIC_HARDWARE_VERSION_82093AA
880	pValue->u32 = ioapicGetArb(PDMINS_2_DATA((PPDMDEVINS)pvUser, PCIOAPIC));
881	#else
882	pValue->u32 = UINT32_C(0xffffffff);
883	#endif
884	return VINF_SUCCESS;
885	}
886
887	/** @interface_method_impl{DBGFREGDESC,pfnGet} */
888	static DECLCALLBACK(int) ioapicDbgReg_GetRte(void *pvUser, PCDBGFREGDESC pDesc, PDBGFREGVAL pValue)
889	{
890	PCIOAPIC pThis = PDMINS_2_DATA((PPDMDEVINS)pvUser, PCIOAPIC);
891	Assert(pDesc->offRegister < RT_ELEMENTS(pThis->au64RedirTable));
892	pValue->u64 = pThis->au64RedirTable[pDesc->offRegister];
893	return VINF_SUCCESS;
894	}
895
896	/** @interface_method_impl{DBGFREGDESC,pfnSet} */
897	static DECLCALLBACK(int) ioapicDbgReg_SetRte(void *pvUser, PCDBGFREGDESC pDesc, PCDBGFREGVAL pValue, PCDBGFREGVAL pfMask)
898	{
899	PIOAPIC pThis = PDMINS_2_DATA((PPDMDEVINS)pvUser, PIOAPIC);
900	/* No locks, no checks, just do it. */
901	Assert(pDesc->offRegister < RT_ELEMENTS(pThis->au64RedirTable));
902	pThis->au64RedirTable[pDesc->offRegister] = pValue->u64;
903	return VINF_SUCCESS;
904	}
905
906	/** IOREDTBLn sub fields. */
907	static DBGFREGSUBFIELD const g_aRteSubs[] =
908	{
909	{ "vector", 0, 8, 0, 0, NULL, NULL },
910	{ "dlvr_mode", 8, 3, 0, 0, NULL, NULL },
911	{ "dest_mode", 11, 1, 0, 0, NULL, NULL },
912	{ "dlvr_status", 12, 1, 0, DBGFREGSUBFIELD_FLAGS_READ_ONLY, NULL, NULL },
913	{ "polarity", 13, 1, 0, 0, NULL, NULL },
914	{ "remote_irr", 14, 1, 0, DBGFREGSUBFIELD_FLAGS_READ_ONLY, NULL, NULL },
915	{ "trigger_mode", 15, 1, 0, 0, NULL, NULL },
916	{ "mask", 16, 1, 0, 0, NULL, NULL },
917	#if IOAPIC_HARDWARE_VERSION == IOAPIC_HARDWARE_VERSION_ICH9
918	{ "ext_dest_id", 48, 8, 0, DBGFREGSUBFIELD_FLAGS_READ_ONLY, NULL, NULL },
919	#endif
920	{ "dest", 56, 8, 0, 0, NULL, NULL },
921	DBGFREGSUBFIELD_TERMINATOR()
922	};
923
924	/** Register descriptors for DBGF. */
925	static DBGFREGDESC const g_aRegDesc[] =
926	{
927	{ "index", DBGFREG_END, DBGFREGVALTYPE_U8, 0, 0, ioapicDbgReg_GetIndex, ioapicDbgReg_SetIndex, NULL, NULL },
928	{ "data", DBGFREG_END, DBGFREGVALTYPE_U32, 0, 0, ioapicDbgReg_GetData, ioapicDbgReg_SetData, NULL, NULL },
929	{ "version", DBGFREG_END, DBGFREGVALTYPE_U32, DBGFREG_FLAGS_READ_ONLY, 0, ioapicDbgReg_GetVersion, NULL, NULL, NULL },
930	#if IOAPIC_HARDWARE_VERSION == IOAPIC_HARDWARE_VERSION_82093AA
931	{ "arb", DBGFREG_END, DBGFREGVALTYPE_U32, DBGFREG_FLAGS_READ_ONLY, 0, ioapicDbgReg_GetArb, NULL, NULL, NULL },
932	#endif
933	{ "rte0", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 0, ioapicDbgReg_GetRte, ioapicDbgReg_SetRte, NULL, &g_aRteSubs[0] },
934	{ "rte1", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 1, ioapicDbgReg_GetRte, ioapicDbgReg_SetRte, NULL, &g_aRteSubs[0] },
935	{ "rte2", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 2, ioapicDbgReg_GetRte, ioapicDbgReg_SetRte, NULL, &g_aRteSubs[0] },
936	{ "rte3", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 3, ioapicDbgReg_GetRte, ioapicDbgReg_SetRte, NULL, &g_aRteSubs[0] },
937	{ "rte4", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 4, ioapicDbgReg_GetRte, ioapicDbgReg_SetRte, NULL, &g_aRteSubs[0] },
938	{ "rte5", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 5, ioapicDbgReg_GetRte, ioapicDbgReg_SetRte, NULL, &g_aRteSubs[0] },
939	{ "rte6", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 6, ioapicDbgReg_GetRte, ioapicDbgReg_SetRte, NULL, &g_aRteSubs[0] },
940	{ "rte7", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 7, ioapicDbgReg_GetRte, ioapicDbgReg_SetRte, NULL, &g_aRteSubs[0] },
941	{ "rte8", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 8, ioapicDbgReg_GetRte, ioapicDbgReg_SetRte, NULL, &g_aRteSubs[0] },
942	{ "rte9", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 9, ioapicDbgReg_GetRte, ioapicDbgReg_SetRte, NULL, &g_aRteSubs[0] },
943	{ "rte10", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 10, ioapicDbgReg_GetRte, ioapicDbgReg_SetRte, NULL, &g_aRteSubs[0] },
944	{ "rte11", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 11, ioapicDbgReg_GetRte, ioapicDbgReg_SetRte, NULL, &g_aRteSubs[0] },
945	{ "rte12", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 12, ioapicDbgReg_GetRte, ioapicDbgReg_SetRte, NULL, &g_aRteSubs[0] },
946	{ "rte13", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 13, ioapicDbgReg_GetRte, ioapicDbgReg_SetRte, NULL, &g_aRteSubs[0] },
947	{ "rte14", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 14, ioapicDbgReg_GetRte, ioapicDbgReg_SetRte, NULL, &g_aRteSubs[0] },
948	{ "rte15", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 15, ioapicDbgReg_GetRte, ioapicDbgReg_SetRte, NULL, &g_aRteSubs[0] },
949	{ "rte16", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 16, ioapicDbgReg_GetRte, ioapicDbgReg_SetRte, NULL, &g_aRteSubs[0] },
950	{ "rte17", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 17, ioapicDbgReg_GetRte, ioapicDbgReg_SetRte, NULL, &g_aRteSubs[0] },
951	{ "rte18", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 18, ioapicDbgReg_GetRte, ioapicDbgReg_SetRte, NULL, &g_aRteSubs[0] },
952	{ "rte19", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 19, ioapicDbgReg_GetRte, ioapicDbgReg_SetRte, NULL, &g_aRteSubs[0] },
953	{ "rte20", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 20, ioapicDbgReg_GetRte, ioapicDbgReg_SetRte, NULL, &g_aRteSubs[0] },
954	{ "rte21", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 21, ioapicDbgReg_GetRte, ioapicDbgReg_SetRte, NULL, &g_aRteSubs[0] },
955	{ "rte22", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 22, ioapicDbgReg_GetRte, ioapicDbgReg_SetRte, NULL, &g_aRteSubs[0] },
956	{ "rte23", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 23, ioapicDbgReg_GetRte, ioapicDbgReg_SetRte, NULL, &g_aRteSubs[0] },
957	DBGFREGDESC_TERMINATOR()
958	};
959
960
961	/**
962	* @callback_method_impl{FNDBGFHANDLERDEV}
963	*/
964	static DECLCALLBACK(void) ioapicR3DbgInfo(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
965	{
966	PCIOAPIC pThis = PDMINS_2_DATA(pDevIns, PIOAPIC);
967	LogFlow(("IOAPIC: ioapicR3DbgInfo: pThis=%p pszArgs=%s\n", pThis, pszArgs));
968
969	pHlp->pfnPrintf(pHlp, "I/O APIC at %#010x:\n", IOAPIC_MMIO_BASE_PHYSADDR);
970
971	uint32_t const uId = ioapicGetId(pThis);
972	pHlp->pfnPrintf(pHlp, " ID = %#RX32\n", uId);
973	pHlp->pfnPrintf(pHlp, " ID = %#x\n", IOAPIC_ID_GET_ID(uId));
974
975	uint32_t const uVer = ioapicGetVersion();
976	pHlp->pfnPrintf(pHlp, " Version = %#RX32\n", uVer);
977	pHlp->pfnPrintf(pHlp, " Version = %#x\n", IOAPIC_VER_GET_VER(uVer));
978	pHlp->pfnPrintf(pHlp, " Pin Assert Reg. Support = %RTbool\n", IOAPIC_VER_HAS_PRQ(uVer));
979	pHlp->pfnPrintf(pHlp, " Max. Redirection Entry = %u\n", IOAPIC_VER_GET_MRE(uVer));
980
981	#if IOAPIC_HARDWARE_VERSION == IOAPIC_HARDWARE_VERSION_82093AA
982	uint32_t const uArb = ioapicGetArb();
983	pHlp->pfnPrintf(pHlp, " Arbitration = %#RX32\n", uArb);
984	pHlp->pfnPrintf(pHlp, " Arbitration ID = %#x\n", IOAPIC_ARB_GET_ID(uArb));
985	#endif
986
987	pHlp->pfnPrintf(pHlp, " Current index = %#x\n", ioapicGetIndex(pThis));
988
989	pHlp->pfnPrintf(pHlp, " I/O Redirection Table and IRR:\n");
990	pHlp->pfnPrintf(pHlp, " idx dst_mode dst_addr mask irr trigger rirr polar dlvr_st dlvr_mode vector\n");
991
992	for (uint8_t idxRte = 0; idxRte < RT_ELEMENTS(pThis->au64RedirTable); idxRte++)
993	{
994	static const char * const s_apszDeliveryModes[] =
995	{
996	"Fixed ",
997	"LowPri",
998	"SMI ",
999	"Rsvd ",
1000	"NMI ",
1001	"INIT ",
1002	"Rsvd ",
1003	"ExtINT"
1004	};
1005
1006	const uint64_t u64Rte = pThis->au64RedirTable[idxRte];
1007	const char *pszDestMode = IOAPIC_RTE_GET_DEST_MODE(u64Rte) == 0 ? "phys" : "log ";
1008	const uint8_t uDest = IOAPIC_RTE_GET_DEST(u64Rte);
1009	const uint8_t uMask = IOAPIC_RTE_GET_MASK(u64Rte);
1010	const char *pszTriggerMode = IOAPIC_RTE_GET_TRIGGER_MODE(u64Rte) == 0 ? "edge " : "level";
1011	const uint8_t uRemoteIrr = IOAPIC_RTE_GET_REMOTE_IRR(u64Rte);
1012	const char *pszPolarity = IOAPIC_RTE_GET_POLARITY(u64Rte) == 0 ? "acthi" : "actlo";
1013	const char *pszDeliveryStatus = IOAPIC_RTE_GET_DELIVERY_STATUS(u64Rte) == 0 ? "idle" : "pend";
1014	const uint8_t uDeliveryMode = IOAPIC_RTE_GET_DELIVERY_MODE(u64Rte);
1015	Assert(uDeliveryMode < RT_ELEMENTS(s_apszDeliveryModes));
1016	const char *pszDeliveryMode = s_apszDeliveryModes[uDeliveryMode];
1017	const uint8_t uVector = IOAPIC_RTE_GET_VECTOR(u64Rte);
1018
1019	pHlp->pfnPrintf(pHlp, " %02d %s %02x %u %u %s %u %s %s %s %3u (%016llx)\n",
1020	idxRte,
1021	pszDestMode,
1022	uDest,
1023	uMask,
1024	(pThis->uIrr >> idxRte) & 1,
1025	pszTriggerMode,
1026	uRemoteIrr,
1027	pszPolarity,
1028	pszDeliveryStatus,
1029	pszDeliveryMode,
1030	uVector,
1031	u64Rte);
1032	}
1033	}
1034
1035
1036	/**
1037	* @copydoc FNSSMDEVSAVEEXEC
1038	*/
1039	static DECLCALLBACK(int) ioapicR3SaveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
1040	{
1041	PCIOAPIC pThis = PDMINS_2_DATA(pDevIns, PCIOAPIC);
1042	LogFlow(("IOAPIC: ioapicR3SaveExec\n"));
1043
1044	SSMR3PutU32(pSSM, pThis->uIrr);
1045	SSMR3PutU8(pSSM, pThis->u8Id);
1046	SSMR3PutU8(pSSM, pThis->u8Index);
1047	for (uint8_t idxRte = 0; idxRte < RT_ELEMENTS(pThis->au64RedirTable); idxRte++)
1048	SSMR3PutU64(pSSM, pThis->au64RedirTable[idxRte]);
1049
1050	return VINF_SUCCESS;
1051	}
1052
1053
1054	/**
1055	* @copydoc FNSSMDEVLOADEXEC
1056	*/
1057	static DECLCALLBACK(int) ioapicR3LoadExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
1058	{
1059	PIOAPIC pThis = PDMINS_2_DATA(pDevIns, PIOAPIC);
1060	LogFlow(("APIC: apicR3LoadExec: uVersion=%u uPass=%#x\n", uVersion, uPass));
1061
1062	Assert(uPass == SSM_PASS_FINAL);
1063	NOREF(uPass);
1064
1065	/* Weed out invalid versions. */
1066	if ( uVersion != IOAPIC_SAVED_STATE_VERSION
1067	&& uVersion != IOAPIC_SAVED_STATE_VERSION_VBOX_50)
1068	{
1069	LogRel(("IOAPIC: ioapicR3LoadExec: Invalid/unrecognized saved-state version %u (%#x)\n", uVersion, uVersion));
1070	return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
1071	}
1072
1073	if (uVersion == IOAPIC_SAVED_STATE_VERSION)
1074	SSMR3GetU32(pSSM, (uint32_t *)&pThis->uIrr);
1075
1076	SSMR3GetU8(pSSM, (uint8_t *)&pThis->u8Id);
1077	SSMR3GetU8(pSSM, (uint8_t *)&pThis->u8Index);
1078	for (uint8_t idxRte = 0; idxRte < RT_ELEMENTS(pThis->au64RedirTable); idxRte++)
1079	SSMR3GetU64(pSSM, &pThis->au64RedirTable[idxRte]);
1080
1081	return VINF_SUCCESS;
1082	}
1083
1084
1085	/**
1086	* @interface_method_impl{PDMDEVREG,pfnReset}
1087	*/
1088	static DECLCALLBACK(void) ioapicR3Reset(PPDMDEVINS pDevIns)
1089	{
1090	PIOAPIC pThis = PDMINS_2_DATA(pDevIns, PIOAPIC);
1091	LogFlow(("IOAPIC: ioapicR3Reset: pThis=%p\n", pThis));
1092
1093	/* There might be devices threads calling ioapicSetIrq() in parallel, hence the lock. */
1094	IOAPIC_LOCK(pThis, VERR_IGNORED);
1095
1096	pThis->uIrr = 0;
1097	pThis->u8Index = 0;
1098	pThis->u8Id = 0;
1099
1100	for (uint8_t idxRte = 0; idxRte < RT_ELEMENTS(pThis->au64RedirTable); idxRte++)
1101	{
1102	pThis->au64RedirTable[idxRte] = IOAPIC_RTE_MASK;
1103	pThis->au32TagSrc[idxRte] = 0;
1104	}
1105
1106	IOAPIC_UNLOCK(pThis);
1107	}
1108
1109
1110	/**
1111	* @interface_method_impl{PDMDEVREG,pfnRelocate}
1112	*/
1113	static DECLCALLBACK(void) ioapicR3Relocate(PPDMDEVINS pDevIns, RTGCINTPTR offDelta)
1114	{
1115	PIOAPIC pThis = PDMINS_2_DATA(pDevIns, PIOAPIC);
1116	LogFlow(("IOAPIC: ioapicR3Relocate: pThis=%p offDelta=%RGi\n", pThis, offDelta));
1117
1118	pThis->pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
1119	pThis->pIoApicHlpRC = pThis->pIoApicHlpR3->pfnGetRCHelpers(pDevIns);
1120	}
1121
1122
1123	/**
1124	* @interface_method_impl{PDMDEVREG,pfnDestruct}
1125	*/
1126	static DECLCALLBACK(int) ioapicR3Destruct(PPDMDEVINS pDevIns)
1127	{
1128	PIOAPIC pThis = PDMINS_2_DATA(pDevIns, PIOAPIC);
1129	LogFlow(("IOAPIC: ioapicR3Destruct: pThis=%p\n", pThis));
1130	PDMDEV_CHECK_VERSIONS_RETURN_QUIET(pDevIns);
1131
1132	#ifndef IOAPIC_WITH_PDM_CRITSECT
1133	/*
1134	* Destroy the RTE critical section.
1135	*/
1136	if (PDMCritSectIsInitialized(&pThis->CritSect))
1137	PDMR3CritSectDelete(&pThis->CritSect);
1138	#endif
1139
1140	return VINF_SUCCESS;
1141	}
1142
1143
1144	/**
1145	* @interface_method_impl{PDMDEVREG,pfnConstruct}
1146	*/
1147	static DECLCALLBACK(int) ioapicR3Construct(PPDMDEVINS pDevIns, int iInstance, PCFGMNODE pCfg)
1148	{
1149	PIOAPIC pThis = PDMINS_2_DATA(pDevIns, PIOAPIC);
1150	LogFlow(("IOAPIC: ioapicR3Construct: pThis=%p iInstance=%d\n", pThis, iInstance));
1151	Assert(iInstance == 0);
1152
1153	/*
1154	* Initialize the state data.
1155	*/
1156	pThis->pDevInsR3 = pDevIns;
1157	pThis->pDevInsR0 = PDMDEVINS_2_R0PTR(pDevIns);
1158	pThis->pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
1159
1160	/*
1161	* Validate and read the configuration.
1162	*/
1163	PDMDEV_VALIDATE_CONFIG_RETURN(pDevIns, "NumCPUs\|RZEnabled", "");
1164
1165	/* The number of CPUs is currently unused, but left in CFGM and saved-state in case an ID of 0 is
1166	upsets some guest which we haven't yet tested. */
1167	uint32_t cCpus;
1168	int rc = CFGMR3QueryU32Def(pCfg, "NumCPUs", &cCpus, 1);
1169	if (RT_FAILURE(rc))
1170	return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to query integer value \"NumCPUs\""));
1171	pThis->cCpus = (uint8_t)cCpus;
1172
1173	bool fRZEnabled;
1174	rc = CFGMR3QueryBoolDef(pCfg, "RZEnabled", &fRZEnabled, true);
1175	if (RT_FAILURE(rc))
1176	return PDMDEV_SET_ERROR(pDevIns, rc,
1177	N_("Configuration error: Failed to query boolean value \"RZEnabled\""));
1178
1179	Log2(("IOAPIC: cCpus=%u fRZEnabled=%RTbool\n", cCpus, fRZEnabled));
1180
1181	/*
1182	* We will use our own critical section for the IOAPIC device.
1183	*/
1184	rc = PDMDevHlpSetDeviceCritSect(pDevIns, PDMDevHlpCritSectGetNop(pDevIns));
1185	AssertRCReturn(rc, rc);
1186
1187	#ifndef IOAPIC_WITH_PDM_CRITSECT
1188	/*
1189	* Setup the critical section to protect concurrent writes to the RTEs.
1190	*/
1191	rc = PDMDevHlpCritSectInit(pDevIns, &pThis->CritSect, RT_SRC_POS, "IOAPIC");
1192	if (RT_FAILURE(rc))
1193	return PDMDevHlpVMSetError(pDevIns, rc, RT_SRC_POS, N_("IOAPIC: Failed to create critical section. rc=%Rrc"), rc);
1194	#endif
1195
1196	/*
1197	* Register the IOAPIC.
1198	*/
1199	PDMIOAPICREG IoApicReg;
1200	RT_ZERO(IoApicReg);
1201	IoApicReg.u32Version = PDM_IOAPICREG_VERSION;
1202	IoApicReg.pfnSetIrqR3 = ioapicSetIrq;
1203	IoApicReg.pfnSendMsiR3 = ioapicSendMsi;
1204	IoApicReg.pfnSetEoiR3 = ioapicSetEoi;
1205	if (fRZEnabled)
1206	{
1207	IoApicReg.pszSetIrqRC = "ioapicSetIrq";
1208	IoApicReg.pszSetIrqR0 = "ioapicSetIrq";
1209
1210	IoApicReg.pszSendMsiRC = "ioapicSendMsi";
1211	IoApicReg.pszSendMsiR0 = "ioapicSendMsi";
1212
1213	IoApicReg.pszSetEoiRC = "ioapicSetEoi";
1214	IoApicReg.pszSetEoiR0 = "ioapicSetEoi";
1215	}
1216	rc = PDMDevHlpIOAPICRegister(pDevIns, &IoApicReg, &pThis->pIoApicHlpR3);
1217	if (RT_FAILURE(rc))
1218	{
1219	AssertMsgFailed(("IOAPIC: PDMDevHlpIOAPICRegister failed! rc=%Rrc\n", rc));
1220	return rc;
1221	}
1222
1223	/*
1224	* Register MMIO callbacks.
1225	*/
1226	rc = PDMDevHlpMMIORegister(pDevIns, IOAPIC_MMIO_BASE_PHYSADDR, IOAPIC_MMIO_SIZE, pThis,
1227	IOMMMIO_FLAGS_READ_DWORD \| IOMMMIO_FLAGS_WRITE_DWORD_ZEROED, ioapicMmioWrite, ioapicMmioRead,
1228	"I/O APIC");
1229	if (RT_SUCCESS(rc))
1230	{
1231	if (fRZEnabled)
1232	{
1233	pThis->pIoApicHlpRC = pThis->pIoApicHlpR3->pfnGetRCHelpers(pDevIns);
1234	rc = PDMDevHlpMMIORegisterRC(pDevIns, IOAPIC_MMIO_BASE_PHYSADDR, IOAPIC_MMIO_SIZE, NIL_RTRCPTR /* pvUser */,
1235	"ioapicMmioWrite", "ioapicMmioRead");
1236	AssertRCReturn(rc, rc);
1237
1238	pThis->pIoApicHlpR0 = pThis->pIoApicHlpR3->pfnGetR0Helpers(pDevIns);
1239	rc = PDMDevHlpMMIORegisterR0(pDevIns, IOAPIC_MMIO_BASE_PHYSADDR, IOAPIC_MMIO_SIZE, NIL_RTR0PTR /* pvUser */,
1240	"ioapicMmioWrite", "ioapicMmioRead");
1241	AssertRCReturn(rc, rc);
1242	}
1243	}
1244	else
1245	{
1246	LogRel(("IOAPIC: PDMDevHlpMMIORegister failed! rc=%Rrc\n", rc));
1247	return rc;
1248	}
1249
1250	/*
1251	* Register saved-state callbacks.
1252	*/
1253	rc = PDMDevHlpSSMRegister(pDevIns, IOAPIC_SAVED_STATE_VERSION, sizeof(*pThis), ioapicR3SaveExec, ioapicR3LoadExec);
1254	if (RT_FAILURE(rc))
1255	{
1256	LogRel(("IOAPIC: PDMDevHlpSSMRegister failed! rc=%Rrc\n", rc));
1257	return rc;
1258	}
1259
1260	/*
1261	* Register debugger info callback.
1262	*/
1263	rc = PDMDevHlpDBGFInfoRegister(pDevIns, "ioapic", "Display IO APIC state.", ioapicR3DbgInfo);
1264	AssertRCReturn(rc, rc);
1265
1266	/*
1267	* Register debugger register access.
1268	*/
1269	rc = PDMDevHlpDBGFRegRegister(pDevIns, g_aRegDesc); AssertRC(rc);
1270	AssertRCReturn(rc, rc);
1271
1272	#ifdef VBOX_WITH_STATISTICS
1273	/*
1274	* Statistics.
1275	*/
1276	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMmioReadRZ, STAMTYPE_COUNTER, "/Devices/IOAPIC/RZ/MmioReadRZ", STAMUNIT_OCCURENCES, "Number of IOAPIC MMIO reads in RZ.");
1277	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMmioWriteRZ, STAMTYPE_COUNTER, "/Devices/IOAPIC/RZ/MmioWriteRZ", STAMUNIT_OCCURENCES, "Number of IOAPIC MMIO writes in RZ.");
1278	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatSetIrqRZ, STAMTYPE_COUNTER, "/Devices/IOAPIC/RZ/SetIrqRZ", STAMUNIT_OCCURENCES, "Number of IOAPIC SetIrq calls in RZ.");
1279	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatSetEoiRZ, STAMTYPE_COUNTER, "/Devices/IOAPIC/RZ/SetEoiRZ", STAMUNIT_OCCURENCES, "Number of IOAPIC SetEoi calls in RZ.");
1280
1281	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMmioReadR3, STAMTYPE_COUNTER, "/Devices/IOAPIC/R3/MmioReadR3", STAMUNIT_OCCURENCES, "Number of IOAPIC MMIO reads in R3");
1282	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMmioWriteR3, STAMTYPE_COUNTER, "/Devices/IOAPIC/R3/MmioWriteR3", STAMUNIT_OCCURENCES, "Number of IOAPIC MMIO writes in R3.");
1283	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatSetIrqR3, STAMTYPE_COUNTER, "/Devices/IOAPIC/R3/SetIrqR3", STAMUNIT_OCCURENCES, "Number of IOAPIC SetIrq calls in R3.");
1284	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatSetEoiR3, STAMTYPE_COUNTER, "/Devices/IOAPIC/R3/SetEoiR3", STAMUNIT_OCCURENCES, "Number of IOAPIC SetEoi calls in R3.");
1285
1286	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatRedundantEdgeIntr, STAMTYPE_COUNTER, "/Devices/IOAPIC/RedundantEdgeIntr", STAMUNIT_OCCURENCES, "Number of redundant edge-triggered interrupts (no IRR change).");
1287	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatRedundantLevelIntr, STAMTYPE_COUNTER, "/Devices/IOAPIC/RedundantLevelIntr", STAMUNIT_OCCURENCES, "Number of redundant level-triggered interrupts (no IRR change).");
1288	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatSuppressedLevelIntr, STAMTYPE_COUNTER, "/Devices/IOAPIC/SuppressedLevelIntr", STAMUNIT_OCCURENCES, "Number of suppressed level-triggered interrupts by remote IRR.");
1289
1290	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatEoiContention, STAMTYPE_COUNTER, "/Devices/IOAPIC/CritSect/ContentionSetEoi", STAMUNIT_OCCURENCES, "Number of times the critsect is busy during EOI writes causing trips to R3.");
1291	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatSetRteContention, STAMTYPE_COUNTER, "/Devices/IOAPIC/CritSect/ContentionSetRte", STAMUNIT_OCCURENCES, "Number of times the critsect is busy during RTE writes causing trips to R3.");
1292
1293	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatLevelIrqSent, STAMTYPE_COUNTER, "/Devices/IOAPIC/LevelIntr/Sent", STAMUNIT_OCCURENCES, "Number of level-triggered interrupts sent to the local APIC(s).");
1294	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatEoiReceived, STAMTYPE_COUNTER, "/Devices/IOAPIC/LevelIntr/Recv", STAMUNIT_OCCURENCES, "Number of EOIs received for level-triggered interrupts from the local APIC(s).");
1295	#endif
1296
1297	/*
1298	* Init. the device state.
1299	*/
1300	LogRel(("IOAPIC: Using implementation 2.0!\n"));
1301	ioapicR3Reset(pDevIns);
1302
1303	return VINF_SUCCESS;
1304	}
1305
1306
1307	/**
1308	* IO APIC device registration structure.
1309	*/
1310	const PDMDEVREG g_DeviceIOAPIC =
1311	{
1312	/* u32Version */
1313	PDM_DEVREG_VERSION,
1314	/* szName */
1315	"ioapic",
1316	/* szRCMod */
1317	"VBoxDDRC.rc",
1318	/* szR0Mod */
1319	"VBoxDDR0.r0",
1320	/* pszDescription */
1321	"I/O Advanced Programmable Interrupt Controller (IO-APIC) Device",
1322	/* fFlags */
1323	PDM_DEVREG_FLAGS_HOST_BITS_DEFAULT \| PDM_DEVREG_FLAGS_GUEST_BITS_32_64 \| PDM_DEVREG_FLAGS_PAE36
1324	\| PDM_DEVREG_FLAGS_RC \| PDM_DEVREG_FLAGS_R0,
1325	/* fClass */
1326	PDM_DEVREG_CLASS_PIC,
1327	/* cMaxInstances */
1328	1,
1329	/* cbInstance */
1330	sizeof(IOAPIC),
1331	/* pfnConstruct */
1332	ioapicR3Construct,
1333	/* pfnDestruct */
1334	ioapicR3Destruct,
1335	/* pfnRelocate */
1336	ioapicR3Relocate,
1337	/* pfnMemSetup */
1338	NULL,
1339	/* pfnPowerOn */
1340	NULL,
1341	/* pfnReset */
1342	ioapicR3Reset,
1343	/* pfnSuspend */
1344	NULL,
1345	/* pfnResume */
1346	NULL,
1347	/* pfnAttach */
1348	NULL,
1349	/* pfnDetach */
1350	NULL,
1351	/* pfnQueryInterface. */
1352	NULL,
1353	/* pfnInitComplete */
1354	NULL,
1355	/* pfnPowerOff */
1356	NULL,
1357	/* pfnSoftReset */
1358	NULL,
1359	/* u32VersionEnd */
1360	PDM_DEVREG_VERSION
1361	};
1362
1363	#endif /* IN_RING3 */
1364
1365	#endif /* !VBOX_DEVICE_STRUCT_TESTCASE */
1366

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source: vbox/trunk/src/VBox/Devices/PC/DevIoApic.cpp@ 62564

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