VirtualBox

source: vbox/trunk/src/VBox/Devices/PC/DevHPET.cpp@ 62477

Last change on this file since 62477 was 60041, checked in by vboxsync, 9 years ago

DevHPET: harmless missing typecast (thanks PVS)
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1/* $Id: DevHPET.cpp 60041 2016-03-15 13:49:51Z vboxsync $ */
2/** @file
3 * HPET virtual device - High Precision Event Timer emulation.
4 */
5
6/*
7 * Copyright (C) 2009-2015 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18/* This implementation is based on the (generic) Intel IA-PC HPET specification
19 * and the Intel ICH9 datasheet.
20 */
21
22
23/*********************************************************************************************************************************
24* Header Files *
25*********************************************************************************************************************************/
26#define LOG_GROUP LOG_GROUP_DEV_HPET
27#include <VBox/vmm/pdmdev.h>
28#include <VBox/vmm/stam.h>
29#include <VBox/log.h>
30#include <iprt/assert.h>
31#include <iprt/asm-math.h>
32#include <iprt/string.h>
33
34#include "VBoxDD.h"
35
36
37/*********************************************************************************************************************************
38* Defined Constants And Macros *
39*********************************************************************************************************************************/
40/*
41 * Current limitations:
42 * - not entirely correct time of interrupt, i.e. never
43 * schedule interrupt earlier than in 1ms
44 * - statistics not implemented
45 * - level-triggered mode not implemented
46 */
47
48/** Base address for MMIO.
49 * On ICH9, it is 0xFED0x000 where 'x' is 0-3, default 0. We do not support
50 * relocation as the platform firmware is responsible for configuring the
51 * HPET base address and the OS isn't expected to move it.
52 * WARNING: This has to match the ACPI tables! */
53#define HPET_BASE 0xfed00000
54
55/** HPET reserves a 1K range. */
56#define HPET_BAR_SIZE 0x1000
57
58/** The number of timers for PIIX4 / PIIX3. */
59#define HPET_NUM_TIMERS_PIIX 3 /* Minimal implementation. */
60/** The number of timers for ICH9. */
61#define HPET_NUM_TIMERS_ICH9 4
62
63/** HPET clock period for PIIX4 / PIIX3.
64 * 10000000 femtoseconds == 10ns.
65 */
66#define HPET_CLK_PERIOD_PIIX UINT32_C(10000000)
67
68/** HPET clock period for ICH9.
69 * 69841279 femtoseconds == 69.84 ns (1 / 14.31818MHz).
70 */
71#define HPET_CLK_PERIOD_ICH9 UINT32_C(69841279)
72
73/**
74 * Femtosecods in a nanosecond
75 */
76#define FS_PER_NS 1000000
77
78/** @name Interrupt type
79 * @{ */
80#define HPET_TIMER_TYPE_LEVEL (1 << 1)
81#define HPET_TIMER_TYPE_EDGE (0 << 1)
82/** @} */
83
84/** @name Delivery mode
85 * @{ */
86#define HPET_TIMER_DELIVERY_APIC 0 /**< Delivery through APIC. */
87#define HPET_TIMER_DELIVERY_FSB 1 /**< Delivery through FSB. */
88/** @} */
89
90#define HPET_TIMER_CAP_FSB_INT_DEL (1 << 15)
91#define HPET_TIMER_CAP_PER_INT (1 << 4)
92
93#define HPET_CFG_ENABLE 0x001 /**< ENABLE_CNF */
94#define HPET_CFG_LEGACY 0x002 /**< LEG_RT_CNF */
95
96/** @name Register offsets in HPET space.
97 * @{ */
98#define HPET_ID 0x000 /**< Device ID. */
99#define HPET_PERIOD 0x004 /**< Clock period in femtoseconds. */
100#define HPET_CFG 0x010 /**< Configuration register. */
101#define HPET_STATUS 0x020 /**< Status register. */
102#define HPET_COUNTER 0x0f0 /**< Main HPET counter. */
103/** @} */
104
105/** @name Timer N offsets (within each timer's space).
106 * @{ */
107#define HPET_TN_CFG 0x000 /**< Timer N configuration. */
108#define HPET_TN_CMP 0x008 /**< Timer N comparator. */
109#define HPET_TN_ROUTE 0x010 /**< Timer N interrupt route. */
110/** @} */
111
112#define HPET_CFG_WRITE_MASK 0x3
113
114#define HPET_TN_INT_TYPE RT_BIT_64(1)
115#define HPET_TN_ENABLE RT_BIT_64(2)
116#define HPET_TN_PERIODIC RT_BIT_64(3)
117#define HPET_TN_PERIODIC_CAP RT_BIT_64(4)
118#define HPET_TN_SIZE_CAP RT_BIT_64(5)
119#define HPET_TN_SETVAL RT_BIT_64(6)
120#define HPET_TN_32BIT RT_BIT_64(8)
121#define HPET_TN_INT_ROUTE_MASK UINT64_C(0x3e00)
122#define HPET_TN_CFG_WRITE_MASK UINT64_C(0x3e46)
123#define HPET_TN_INT_ROUTE_SHIFT 9
124#define HPET_TN_INT_ROUTE_CAP_SHIFT 32
125
126#define HPET_TN_CFG_BITS_READONLY_OR_RESERVED 0xffff80b1U
127
128/** Extract the timer count from the capabilities. */
129#define HPET_CAP_GET_TIMERS(a_u32) ( ((a_u32) >> 8) & 0x1f )
130
131/** The version of the saved state. */
132#define HPET_SAVED_STATE_VERSION 2
133/** Empty saved state */
134#define HPET_SAVED_STATE_VERSION_EMPTY 1
135
136
137/**
138 * Acquires the HPET lock or returns.
139 */
140#define DEVHPET_LOCK_RETURN(a_pThis, a_rcBusy) \
141 do { \
142 int rcLock = PDMCritSectEnter(&(a_pThis)->CritSect, (a_rcBusy)); \
143 if (rcLock != VINF_SUCCESS) \
144 return rcLock; \
145 } while (0)
146
147/**
148 * Releases the HPET lock.
149 */
150#define DEVHPET_UNLOCK(a_pThis) \
151 do { PDMCritSectLeave(&(a_pThis)->CritSect); } while (0)
152
153
154/**
155 * Acquires the TM lock and HPET lock, returns on failure.
156 */
157#define DEVHPET_LOCK_BOTH_RETURN(a_pThis, a_rcBusy) \
158 do { \
159 int rcLock = TMTimerLock((a_pThis)->aTimers[0].CTX_SUFF(pTimer), (a_rcBusy)); \
160 if (rcLock != VINF_SUCCESS) \
161 return rcLock; \
162 rcLock = PDMCritSectEnter(&(a_pThis)->CritSect, (a_rcBusy)); \
163 if (rcLock != VINF_SUCCESS) \
164 { \
165 TMTimerUnlock((a_pThis)->aTimers[0].CTX_SUFF(pTimer)); \
166 return rcLock; \
167 } \
168 } while (0)
169
170
171/**
172 * Releases the HPET lock and TM lock.
173 */
174#define DEVHPET_UNLOCK_BOTH(a_pThis) \
175 do { \
176 PDMCritSectLeave(&(a_pThis)->CritSect); \
177 TMTimerUnlock((a_pThis)->aTimers[0].CTX_SUFF(pTimer)); \
178 } while (0)
179
180
181/*********************************************************************************************************************************
182* Structures and Typedefs *
183*********************************************************************************************************************************/
184/**
185 * A HPET timer.
186 */
187typedef struct HPETTIMER
188{
189 /** The HPET timer - R3 Ptr. */
190 PTMTIMERR3 pTimerR3;
191 /** Pointer to the instance data - R3 Ptr. */
192 R3PTRTYPE(struct HPET *) pHpetR3;
193
194 /** The HPET timer - R0 Ptr. */
195 PTMTIMERR0 pTimerR0;
196 /** Pointer to the instance data - R0 Ptr. */
197 R0PTRTYPE(struct HPET *) pHpetR0;
198
199 /** The HPET timer - RC Ptr. */
200 PTMTIMERRC pTimerRC;
201 /** Pointer to the instance data - RC Ptr. */
202 RCPTRTYPE(struct HPET *) pHpetRC;
203
204 /** Timer index. */
205 uint8_t idxTimer;
206 /** Wrap. */
207 uint8_t u8Wrap;
208 /** Alignment. */
209 uint32_t alignment0;
210
211 /** @name Memory-mapped, software visible timer registers.
212 * @{ */
213 /** Configuration/capabilities. */
214 uint64_t u64Config;
215 /** Comparator. */
216 uint64_t u64Cmp;
217 /** FSB route, not supported now. */
218 uint64_t u64Fsb;
219 /** @} */
220
221 /** @name Hidden register state.
222 * @{ */
223 /** Last value written to comparator. */
224 uint64_t u64Period;
225 /** @} */
226} HPETTIMER;
227AssertCompileMemberAlignment(HPETTIMER, u64Config, sizeof(uint64_t));
228
229/**
230 * The HPET state.
231 */
232typedef struct HPET
233{
234 /** Pointer to the device instance. - R3 ptr. */
235 PPDMDEVINSR3 pDevInsR3;
236 /** The HPET helpers - R3 Ptr. */
237 PCPDMHPETHLPR3 pHpetHlpR3;
238
239 /** Pointer to the device instance. - R0 ptr. */
240 PPDMDEVINSR0 pDevInsR0;
241 /** The HPET helpers - R0 Ptr. */
242 PCPDMHPETHLPR0 pHpetHlpR0;
243
244 /** Pointer to the device instance. - RC ptr. */
245 PPDMDEVINSRC pDevInsRC;
246 /** The HPET helpers - RC Ptr. */
247 PCPDMHPETHLPRC pHpetHlpRC;
248
249 /** Timer structures. */
250 HPETTIMER aTimers[RT_MAX(HPET_NUM_TIMERS_PIIX, HPET_NUM_TIMERS_ICH9)];
251
252 /** Offset realtive to the virtual sync clock. */
253 uint64_t u64HpetOffset;
254
255 /** @name Memory-mapped, software visible registers
256 * @{ */
257 /** Capabilities. */
258 uint32_t u32Capabilities;
259 /** HPET_PERIOD - . */
260 uint32_t u32Period;
261 /** Configuration. */
262 uint64_t u64HpetConfig;
263 /** Interrupt status register. */
264 uint64_t u64Isr;
265 /** Main counter. */
266 uint64_t u64HpetCounter;
267 /** @} */
268
269 /** Global device lock. */
270 PDMCRITSECT CritSect;
271
272 /** Whether we emulate ICH9 HPET (different frequency & timer count). */
273 bool fIch9;
274 /** Size alignment padding. */
275 uint8_t abPadding0[7];
276} HPET;
277
278
279#ifndef VBOX_DEVICE_STRUCT_TESTCASE
280
281
282DECLINLINE(bool) hpet32bitTimer(HPETTIMER *pHpetTimer)
283{
284 uint64_t u64Cfg = pHpetTimer->u64Config;
285
286 return ((u64Cfg & HPET_TN_SIZE_CAP) == 0) || ((u64Cfg & HPET_TN_32BIT) != 0);
287}
288
289DECLINLINE(uint64_t) hpetInvalidValue(HPETTIMER *pHpetTimer)
290{
291 return hpet32bitTimer(pHpetTimer) ? UINT32_MAX : UINT64_MAX;
292}
293
294DECLINLINE(uint64_t) hpetTicksToNs(HPET *pThis, uint64_t value)
295{
296 return ASMMultU64ByU32DivByU32(value, pThis->u32Period, FS_PER_NS);
297}
298
299DECLINLINE(uint64_t) nsToHpetTicks(HPET const *pThis, uint64_t u64Value)
300{
301 return ASMMultU64ByU32DivByU32(u64Value, FS_PER_NS, pThis->u32Period);
302}
303
304DECLINLINE(uint64_t) hpetGetTicks(HPET const *pThis)
305{
306 /*
307 * We can use any timer to get current time, they all go
308 * with the same speed.
309 */
310 return nsToHpetTicks(pThis,
311 TMTimerGet(pThis->aTimers[0].CTX_SUFF(pTimer))
312 + pThis->u64HpetOffset);
313}
314
315DECLINLINE(uint64_t) hpetUpdateMasked(uint64_t u64NewValue, uint64_t u64OldValue, uint64_t u64Mask)
316{
317 u64NewValue &= u64Mask;
318 u64NewValue |= (u64OldValue & ~u64Mask);
319 return u64NewValue;
320}
321
322DECLINLINE(bool) hpetBitJustSet(uint64_t u64OldValue, uint64_t u64NewValue, uint64_t u64Mask)
323{
324 return !(u64OldValue & u64Mask)
325 && !!(u64NewValue & u64Mask);
326}
327
328DECLINLINE(bool) hpetBitJustCleared(uint64_t u64OldValue, uint64_t u64NewValue, uint64_t u64Mask)
329{
330 return !!(u64OldValue & u64Mask)
331 && !(u64NewValue & u64Mask);
332}
333
334DECLINLINE(uint64_t) hpetComputeDiff(HPETTIMER *pHpetTimer, uint64_t u64Now)
335{
336
337 if (hpet32bitTimer(pHpetTimer))
338 {
339 uint32_t u32Diff;
340
341 u32Diff = (uint32_t)pHpetTimer->u64Cmp - (uint32_t)u64Now;
342 u32Diff = ((int32_t)u32Diff > 0) ? u32Diff : (uint32_t)0;
343 return (uint64_t)u32Diff;
344 }
345 else
346 {
347 uint64_t u64Diff;
348
349 u64Diff = pHpetTimer->u64Cmp - u64Now;
350 u64Diff = ((int64_t)u64Diff > 0) ? u64Diff : (uint64_t)0;
351 return u64Diff;
352 }
353}
354
355
356static void hpetAdjustComparator(HPETTIMER *pHpetTimer, uint64_t u64Now)
357{
358 uint64_t u64Period = pHpetTimer->u64Period;
359
360 if ((pHpetTimer->u64Config & HPET_TN_PERIODIC) && u64Period)
361 {
362 uint64_t cPeriods = (u64Now - pHpetTimer->u64Cmp) / u64Period;
363
364 pHpetTimer->u64Cmp += (cPeriods + 1) * u64Period;
365 }
366}
367
368
369/**
370 * Sets the frequency hint if it's a periodic timer.
371 *
372 * @param pThis The HPET state.
373 * @param pHpetTimer The timer.
374 */
375DECLINLINE(void) hpetTimerSetFrequencyHint(HPET *pThis, HPETTIMER *pHpetTimer)
376{
377 if (pHpetTimer->u64Config & HPET_TN_PERIODIC)
378 {
379 uint64_t const u64Period = pHpetTimer->u64Period;
380 uint32_t const u32Freq = pThis->u32Period;
381 if (u64Period > 0 && u64Period < u32Freq)
382 TMTimerSetFrequencyHint(pHpetTimer->CTX_SUFF(pTimer), u32Freq / (uint32_t)u64Period);
383 }
384}
385
386
387static void hpetProgramTimer(HPETTIMER *pHpetTimer)
388{
389 /* no wrapping on new timers */
390 pHpetTimer->u8Wrap = 0;
391
392 uint64_t u64Ticks = hpetGetTicks(pHpetTimer->CTX_SUFF(pHpet));
393 hpetAdjustComparator(pHpetTimer, u64Ticks);
394
395 uint64_t u64Diff = hpetComputeDiff(pHpetTimer, u64Ticks);
396
397 /*
398 * HPET spec says in one-shot 32-bit mode, generate an interrupt when
399 * counter wraps in addition to an interrupt with comparator match.
400 */
401 if ( hpet32bitTimer(pHpetTimer)
402 && !(pHpetTimer->u64Config & HPET_TN_PERIODIC))
403 {
404 uint32_t u32TillWrap = 0xffffffff - (uint32_t)u64Ticks + 1;
405 if (u32TillWrap < (uint32_t)u64Diff)
406 {
407 Log(("wrap on timer %d: till=%u ticks=%lld diff64=%lld\n",
408 pHpetTimer->idxTimer, u32TillWrap, u64Ticks, u64Diff));
409 u64Diff = u32TillWrap;
410 pHpetTimer->u8Wrap = 1;
411 }
412 }
413
414 /*
415 * HACK ALERT! Avoid killing VM with interrupts.
416 */
417#if 1 /** @todo: HACK, rethink, may have negative impact on the guest */
418 if (u64Diff == 0)
419 u64Diff = 100000; /* 1 millisecond */
420#endif
421
422 Log4(("HPET: next IRQ in %lld ticks (%lld ns)\n", u64Diff, hpetTicksToNs(pHpetTimer->CTX_SUFF(pHpet), u64Diff)));
423 TMTimerSetNano(pHpetTimer->CTX_SUFF(pTimer), hpetTicksToNs(pHpetTimer->CTX_SUFF(pHpet), u64Diff));
424 hpetTimerSetFrequencyHint(pHpetTimer->CTX_SUFF(pHpet), pHpetTimer);
425}
426
427
428/* -=-=-=-=-=- Timer register accesses -=-=-=-=-=- */
429
430
431/**
432 * Reads a HPET timer register.
433 *
434 * @returns VBox strict status code.
435 * @param pThis The HPET instance.
436 * @param iTimerNo The timer index.
437 * @param iTimerReg The index of the timer register to read.
438 * @param pu32Value Where to return the register value.
439 *
440 * @remarks ASSUMES the caller holds the HPET lock.
441 */
442static int hpetTimerRegRead32(HPET const *pThis, uint32_t iTimerNo, uint32_t iTimerReg, uint32_t *pu32Value)
443{
444 Assert(PDMCritSectIsOwner(&pThis->CritSect));
445
446 if ( iTimerNo >= HPET_CAP_GET_TIMERS(pThis->u32Capabilities) /* The second check is only to satisfy Parfait; */
447 || iTimerNo >= RT_ELEMENTS(pThis->aTimers) ) /* in practice, the number of configured timers */
448 { /* will always be <= aTimers elements. */
449 LogRelMax(10, ("HPET: Using timer above configured range: %d\n", iTimerNo));
450 *pu32Value = 0;
451 return VINF_SUCCESS;
452 }
453
454 HPETTIMER const *pHpetTimer = &pThis->aTimers[iTimerNo];
455 uint32_t u32Value;
456 switch (iTimerReg)
457 {
458 case HPET_TN_CFG:
459 u32Value = (uint32_t)pHpetTimer->u64Config;
460 Log(("read HPET_TN_CFG on %d: %#x\n", iTimerNo, u32Value));
461 break;
462
463 case HPET_TN_CFG + 4:
464 u32Value = (uint32_t)(pHpetTimer->u64Config >> 32);
465 Log(("read HPET_TN_CFG+4 on %d: %#x\n", iTimerNo, u32Value));
466 break;
467
468 case HPET_TN_CMP:
469 u32Value = (uint32_t)pHpetTimer->u64Cmp;
470 Log(("read HPET_TN_CMP on %d: %#x (%#llx)\n", pHpetTimer->idxTimer, u32Value, pHpetTimer->u64Cmp));
471 break;
472
473 case HPET_TN_CMP + 4:
474 u32Value = (uint32_t)(pHpetTimer->u64Cmp >> 32);
475 Log(("read HPET_TN_CMP+4 on %d: %#x (%#llx)\n", pHpetTimer->idxTimer, u32Value, pHpetTimer->u64Cmp));
476 break;
477
478 case HPET_TN_ROUTE:
479 u32Value = (uint32_t)(pHpetTimer->u64Fsb >> 32); /** @todo Looks wrong, but since it's not supported, who cares. */
480 Log(("read HPET_TN_ROUTE on %d: %#x\n", iTimerNo, u32Value));
481 break;
482
483 default:
484 {
485 LogRelMax(10, ("HPET: Invalid HPET register read %d on %d\n", iTimerReg, pHpetTimer->idxTimer));
486 u32Value = 0;
487 break;
488 }
489 }
490 *pu32Value = u32Value;
491 return VINF_SUCCESS;
492}
493
494
495/**
496 * 32-bit write to a HPET timer register.
497 *
498 * @returns Strict VBox status code.
499 *
500 * @param pThis The HPET state.
501 * @param idxReg The register being written to.
502 * @param u32NewValue The value being written.
503 *
504 * @remarks The caller should not hold the device lock, unless it also holds
505 * the TM lock.
506 */
507static int hpetTimerRegWrite32(HPET *pThis, uint32_t iTimerNo, uint32_t iTimerReg, uint32_t u32NewValue)
508{
509 Assert(!PDMCritSectIsOwner(&pThis->CritSect) || TMTimerIsLockOwner(pThis->aTimers[0].CTX_SUFF(pTimer)));
510
511 if ( iTimerNo >= HPET_CAP_GET_TIMERS(pThis->u32Capabilities)
512 || iTimerNo >= RT_ELEMENTS(pThis->aTimers) ) /* Parfait - see above. */
513 {
514 LogRelMax(10, ("HPET: Using timer above configured range: %d\n", iTimerNo));
515 return VINF_SUCCESS;
516 }
517 HPETTIMER *pHpetTimer = &pThis->aTimers[iTimerNo];
518
519 switch (iTimerReg)
520 {
521 case HPET_TN_CFG:
522 {
523 DEVHPET_LOCK_RETURN(pThis, VINF_IOM_R3_MMIO_WRITE);
524 uint64_t u64Mask = HPET_TN_CFG_WRITE_MASK;
525
526 Log(("write HPET_TN_CFG: %d: %x\n", iTimerNo, u32NewValue));
527 if (pHpetTimer->u64Config & HPET_TN_PERIODIC_CAP)
528 u64Mask |= HPET_TN_PERIODIC;
529
530 if (pHpetTimer->u64Config & HPET_TN_SIZE_CAP)
531 u64Mask |= HPET_TN_32BIT;
532 else
533 u32NewValue &= ~HPET_TN_32BIT;
534
535 if (u32NewValue & HPET_TN_32BIT)
536 {
537 Log(("setting timer %d to 32-bit mode\n", iTimerNo));
538 pHpetTimer->u64Cmp = (uint32_t)pHpetTimer->u64Cmp;
539 pHpetTimer->u64Period = (uint32_t)pHpetTimer->u64Period;
540 }
541 if ((u32NewValue & HPET_TN_INT_TYPE) == HPET_TIMER_TYPE_LEVEL)
542 {
543 LogRelMax(10, ("HPET: Level-triggered config not yet supported\n"));
544 AssertFailed();
545 }
546
547 /* We only care about lower 32-bits so far */
548 pHpetTimer->u64Config = hpetUpdateMasked(u32NewValue, pHpetTimer->u64Config, u64Mask);
549 DEVHPET_UNLOCK(pThis);
550 break;
551 }
552
553 case HPET_TN_CFG + 4: /* Interrupt capabilities - read only. */
554 Log(("write HPET_TN_CFG + 4, useless\n"));
555 break;
556
557 case HPET_TN_CMP: /* lower bits of comparator register */
558 {
559 DEVHPET_LOCK_BOTH_RETURN(pThis, VINF_IOM_R3_MMIO_WRITE);
560 Log(("write HPET_TN_CMP on %d: %#x\n", iTimerNo, u32NewValue));
561
562 if (pHpetTimer->u64Config & HPET_TN_PERIODIC)
563 pHpetTimer->u64Period = RT_MAKE_U64(u32NewValue, RT_HI_U32(pHpetTimer->u64Period));
564 pHpetTimer->u64Cmp = RT_MAKE_U64(u32NewValue, RT_HI_U32(pHpetTimer->u64Cmp));
565 pHpetTimer->u64Config &= ~HPET_TN_SETVAL;
566 Log2(("after HPET_TN_CMP cmp=%#llx per=%#llx\n", pHpetTimer->u64Cmp, pHpetTimer->u64Period));
567
568 if (pThis->u64HpetConfig & HPET_CFG_ENABLE)
569 hpetProgramTimer(pHpetTimer);
570 DEVHPET_UNLOCK_BOTH(pThis);
571 break;
572 }
573
574 case HPET_TN_CMP + 4: /* upper bits of comparator register */
575 {
576 DEVHPET_LOCK_BOTH_RETURN(pThis, VINF_IOM_R3_MMIO_WRITE);
577 Log(("write HPET_TN_CMP + 4 on %d: %#x\n", iTimerNo, u32NewValue));
578 if (!hpet32bitTimer(pHpetTimer))
579 {
580 if (pHpetTimer->u64Config & HPET_TN_PERIODIC)
581 pHpetTimer->u64Period = RT_MAKE_U64(RT_LO_U32(pHpetTimer->u64Period), u32NewValue);
582 pHpetTimer->u64Cmp = RT_MAKE_U64(RT_LO_U32(pHpetTimer->u64Cmp), u32NewValue);
583
584 Log2(("after HPET_TN_CMP+4 cmp=%llx per=%llx tmr=%d\n", pHpetTimer->u64Cmp, pHpetTimer->u64Period, iTimerNo));
585
586 pHpetTimer->u64Config &= ~HPET_TN_SETVAL;
587
588 if (pThis->u64HpetConfig & HPET_CFG_ENABLE)
589 hpetProgramTimer(pHpetTimer);
590 }
591 DEVHPET_UNLOCK_BOTH(pThis);
592 break;
593 }
594
595 case HPET_TN_ROUTE:
596 Log(("write HPET_TN_ROUTE\n"));
597 break;
598
599 case HPET_TN_ROUTE + 4:
600 Log(("write HPET_TN_ROUTE + 4\n"));
601 break;
602
603 default:
604 LogRelMax(10, ("HPET: Invalid timer register write: %d\n", iTimerReg));
605 break;
606 }
607
608 return VINF_SUCCESS;
609}
610
611
612/* -=-=-=-=-=- Non-timer register accesses -=-=-=-=-=- */
613
614
615/**
616 * Read a 32-bit HPET register.
617 *
618 * @returns Strict VBox status code.
619 * @param pThis The HPET state.
620 * @param idxReg The register to read.
621 * @param pu32Value Where to return the register value.
622 *
623 * @remarks The caller must not own the device lock if HPET_COUNTER is read.
624 */
625static int hpetConfigRegRead32(HPET *pThis, uint32_t idxReg, uint32_t *pu32Value)
626{
627 Assert(!PDMCritSectIsOwner(&pThis->CritSect) || (idxReg != HPET_COUNTER && idxReg != HPET_COUNTER + 4));
628
629 uint32_t u32Value;
630 switch (idxReg)
631 {
632 case HPET_ID:
633 DEVHPET_LOCK_RETURN(pThis, VINF_IOM_R3_MMIO_READ);
634 u32Value = pThis->u32Capabilities;
635 DEVHPET_UNLOCK(pThis);
636 Log(("read HPET_ID: %#x\n", u32Value));
637 break;
638
639 case HPET_PERIOD:
640 DEVHPET_LOCK_RETURN(pThis, VINF_IOM_R3_MMIO_READ);
641 u32Value = pThis->u32Period;
642 DEVHPET_UNLOCK(pThis);
643 Log(("read HPET_PERIOD: %#x\n", u32Value));
644 break;
645
646 case HPET_CFG:
647 DEVHPET_LOCK_RETURN(pThis, VINF_IOM_R3_MMIO_READ);
648 u32Value = (uint32_t)pThis->u64HpetConfig;
649 DEVHPET_UNLOCK(pThis);
650 Log(("read HPET_CFG: %#x\n", u32Value));
651 break;
652
653 case HPET_CFG + 4:
654 DEVHPET_LOCK_RETURN(pThis, VINF_IOM_R3_MMIO_READ);
655 u32Value = (uint32_t)(pThis->u64HpetConfig >> 32);
656 DEVHPET_UNLOCK(pThis);
657 Log(("read of HPET_CFG + 4: %#x\n", u32Value));
658 break;
659
660 case HPET_COUNTER:
661 case HPET_COUNTER + 4:
662 {
663 DEVHPET_LOCK_BOTH_RETURN(pThis, VINF_IOM_R3_MMIO_READ);
664
665 uint64_t u64Ticks;
666 if (pThis->u64HpetConfig & HPET_CFG_ENABLE)
667 u64Ticks = hpetGetTicks(pThis);
668 else
669 u64Ticks = pThis->u64HpetCounter;
670
671 DEVHPET_UNLOCK_BOTH(pThis);
672
673 /** @todo is it correct? */
674 u32Value = (idxReg == HPET_COUNTER) ? (uint32_t)u64Ticks : (uint32_t)(u64Ticks >> 32);
675 Log(("read HPET_COUNTER: %s part value %x (%#llx)\n",
676 (idxReg == HPET_COUNTER) ? "low" : "high", u32Value, u64Ticks));
677 break;
678 }
679
680 case HPET_STATUS:
681 DEVHPET_LOCK_RETURN(pThis, VINF_IOM_R3_MMIO_READ);
682 u32Value = (uint32_t)pThis->u64Isr;
683 DEVHPET_UNLOCK(pThis);
684 Log(("read HPET_STATUS: %#x\n", u32Value));
685 break;
686
687 default:
688 Log(("invalid HPET register read: %x\n", idxReg));
689 u32Value = 0;
690 break;
691 }
692
693 *pu32Value = u32Value;
694 return VINF_SUCCESS;
695}
696
697
698/**
699 * 32-bit write to a config register.
700 *
701 * @returns Strict VBox status code.
702 *
703 * @param pThis The HPET state.
704 * @param idxReg The register being written to.
705 * @param u32NewValue The value being written.
706 *
707 * @remarks The caller should not hold the device lock, unless it also holds
708 * the TM lock.
709 */
710static int hpetConfigRegWrite32(HPET *pThis, uint32_t idxReg, uint32_t u32NewValue)
711{
712 Assert(!PDMCritSectIsOwner(&pThis->CritSect) || TMTimerIsLockOwner(pThis->aTimers[0].CTX_SUFF(pTimer)));
713
714 int rc = VINF_SUCCESS;
715 switch (idxReg)
716 {
717 case HPET_ID:
718 case HPET_ID + 4:
719 {
720 Log(("write HPET_ID, useless\n"));
721 break;
722 }
723
724 case HPET_CFG:
725 {
726 DEVHPET_LOCK_BOTH_RETURN(pThis, VINF_IOM_R3_MMIO_WRITE);
727 uint32_t const iOldValue = (uint32_t)(pThis->u64HpetConfig);
728 Log(("write HPET_CFG: %x (old %x)\n", u32NewValue, iOldValue));
729
730 /*
731 * This check must be here, before actual update, as hpetLegacyMode
732 * may request retry in R3 - so we must keep state intact.
733 */
734 if ( ((iOldValue ^ u32NewValue) & HPET_CFG_LEGACY)
735 && pThis->pHpetHlpR3 != NIL_RTR3PTR)
736 {
737#ifdef IN_RING3
738 rc = pThis->pHpetHlpR3->pfnSetLegacyMode(pThis->pDevInsR3, RT_BOOL(u32NewValue & HPET_CFG_LEGACY));
739 if (rc != VINF_SUCCESS)
740#else
741 rc = VINF_IOM_R3_MMIO_WRITE;
742#endif
743 {
744 DEVHPET_UNLOCK_BOTH(pThis);
745 break;
746 }
747 }
748
749 pThis->u64HpetConfig = hpetUpdateMasked(u32NewValue, iOldValue, HPET_CFG_WRITE_MASK);
750
751 uint32_t const cTimers = HPET_CAP_GET_TIMERS(pThis->u32Capabilities);
752 if (hpetBitJustSet(iOldValue, u32NewValue, HPET_CFG_ENABLE))
753 {
754/** @todo Only get the time stamp once when reprogramming? */
755 /* Enable main counter and interrupt generation. */
756 pThis->u64HpetOffset = hpetTicksToNs(pThis, pThis->u64HpetCounter)
757 - TMTimerGet(pThis->aTimers[0].CTX_SUFF(pTimer));
758 for (uint32_t i = 0; i < cTimers; i++)
759 if (pThis->aTimers[i].u64Cmp != hpetInvalidValue(&pThis->aTimers[i]))
760 hpetProgramTimer(&pThis->aTimers[i]);
761 }
762 else if (hpetBitJustCleared(iOldValue, u32NewValue, HPET_CFG_ENABLE))
763 {
764 /* Halt main counter and disable interrupt generation. */
765 pThis->u64HpetCounter = hpetGetTicks(pThis);
766 for (uint32_t i = 0; i < cTimers; i++)
767 TMTimerStop(pThis->aTimers[i].CTX_SUFF(pTimer));
768 }
769
770 DEVHPET_UNLOCK_BOTH(pThis);
771 break;
772 }
773
774 case HPET_CFG + 4:
775 {
776 DEVHPET_LOCK_RETURN(pThis, VINF_IOM_R3_MMIO_WRITE);
777 pThis->u64HpetConfig = hpetUpdateMasked((uint64_t)u32NewValue << 32,
778 pThis->u64HpetConfig,
779 UINT64_C(0xffffffff00000000));
780 Log(("write HPET_CFG + 4: %x -> %#llx\n", u32NewValue, pThis->u64HpetConfig));
781 DEVHPET_UNLOCK(pThis);
782 break;
783 }
784
785 case HPET_STATUS:
786 {
787 DEVHPET_LOCK_RETURN(pThis, VINF_IOM_R3_MMIO_WRITE);
788 /* Clear ISR for all set bits in u32NewValue, see p. 14 of the HPET spec. */
789 pThis->u64Isr &= ~((uint64_t)u32NewValue);
790 Log(("write HPET_STATUS: %x -> ISR=%#llx\n", u32NewValue, pThis->u64Isr));
791 DEVHPET_UNLOCK(pThis);
792 break;
793 }
794
795 case HPET_STATUS + 4:
796 {
797 Log(("write HPET_STATUS + 4: %x\n", u32NewValue));
798 if (u32NewValue != 0)
799 LogRelMax(10, ("HPET: Writing HPET_STATUS + 4 with non-zero, ignored\n"));
800 break;
801 }
802
803 case HPET_COUNTER:
804 {
805 DEVHPET_LOCK_RETURN(pThis, VINF_IOM_R3_MMIO_WRITE);
806 pThis->u64HpetCounter = RT_MAKE_U64(u32NewValue, RT_HI_U32(pThis->u64HpetCounter));
807 Log(("write HPET_COUNTER: %#x -> %llx\n", u32NewValue, pThis->u64HpetCounter));
808 DEVHPET_UNLOCK(pThis);
809 break;
810 }
811
812 case HPET_COUNTER + 4:
813 {
814 DEVHPET_LOCK_RETURN(pThis, VINF_IOM_R3_MMIO_WRITE);
815 pThis->u64HpetCounter = RT_MAKE_U64(RT_LO_U32(pThis->u64HpetCounter), u32NewValue);
816 Log(("write HPET_COUNTER + 4: %#x -> %llx\n", u32NewValue, pThis->u64HpetCounter));
817 DEVHPET_UNLOCK(pThis);
818 break;
819 }
820
821 default:
822 LogRelMax(10, ("HPET: Invalid HPET config write: %x\n", idxReg));
823 break;
824 }
825
826 return rc;
827}
828
829
830/* -=-=-=-=-=- MMIO callbacks -=-=-=-=-=- */
831
832
833/**
834 * @callback_method_impl{FNIOMMMIOREAD}
835 */
836PDMBOTHCBDECL(int) hpetMMIORead(PPDMDEVINS pDevIns, void *pvUser, RTGCPHYS GCPhysAddr, void *pv, unsigned cb)
837{
838 HPET *pThis = PDMINS_2_DATA(pDevIns, HPET*);
839 uint32_t const idxReg = (uint32_t)(GCPhysAddr - HPET_BASE);
840 NOREF(pvUser);
841 Assert(cb == 4 || cb == 8);
842
843 LogFlow(("hpetMMIORead (%d): %llx (%x)\n", cb, (uint64_t)GCPhysAddr, idxReg));
844
845 int rc;
846 if (cb == 4)
847 {
848 /*
849 * 4-byte access.
850 */
851 if (idxReg >= 0x100 && idxReg < 0x400)
852 {
853 DEVHPET_LOCK_RETURN(pThis, VINF_IOM_R3_MMIO_READ);
854 rc = hpetTimerRegRead32(pThis,
855 (idxReg - 0x100) / 0x20,
856 (idxReg - 0x100) % 0x20,
857 (uint32_t *)pv);
858 DEVHPET_UNLOCK(pThis);
859 }
860 else
861 rc = hpetConfigRegRead32(pThis, idxReg, (uint32_t *)pv);
862 }
863 else
864 {
865 /*
866 * 8-byte access - Split the access except for timing sensitive registers.
867 * The others assume the protection of the lock.
868 */
869 PRTUINT64U pValue = (PRTUINT64U)pv;
870 if (idxReg == HPET_COUNTER)
871 {
872 /* When reading HPET counter we must read it in a single read,
873 to avoid unexpected time jumps on 32-bit overflow. */
874 DEVHPET_LOCK_BOTH_RETURN(pThis, VINF_IOM_R3_MMIO_READ);
875 if (pThis->u64HpetConfig & HPET_CFG_ENABLE)
876 pValue->u = hpetGetTicks(pThis);
877 else
878 pValue->u = pThis->u64HpetCounter;
879 DEVHPET_UNLOCK_BOTH(pThis);
880 rc = VINF_SUCCESS;
881 }
882 else
883 {
884 DEVHPET_LOCK_RETURN(pThis, VINF_IOM_R3_MMIO_READ);
885 if (idxReg >= 0x100 && idxReg < 0x400)
886 {
887 uint32_t iTimer = (idxReg - 0x100) / 0x20;
888 uint32_t iTimerReg = (idxReg - 0x100) % 0x20;
889 rc = hpetTimerRegRead32(pThis, iTimer, iTimerReg, &pValue->s.Lo);
890 if (rc == VINF_SUCCESS)
891 rc = hpetTimerRegRead32(pThis, iTimer, iTimerReg + 4, &pValue->s.Hi);
892 }
893 else
894 {
895 /* for most 8-byte accesses we just split them, happens under lock anyway. */
896 rc = hpetConfigRegRead32(pThis, idxReg, &pValue->s.Lo);
897 if (rc == VINF_SUCCESS)
898 rc = hpetConfigRegRead32(pThis, idxReg + 4, &pValue->s.Hi);
899 }
900 DEVHPET_UNLOCK(pThis);
901 }
902 }
903 return rc;
904}
905
906
907/**
908 * @callback_method_impl{FNIOMMMIOWRITE}
909 */
910PDMBOTHCBDECL(int) hpetMMIOWrite(PPDMDEVINS pDevIns, void *pvUser, RTGCPHYS GCPhysAddr, void const *pv, unsigned cb)
911{
912 HPET *pThis = PDMINS_2_DATA(pDevIns, HPET*);
913 uint32_t idxReg = (uint32_t)(GCPhysAddr - HPET_BASE);
914 LogFlow(("hpetMMIOWrite: cb=%u reg=%03x (%RGp) val=%llx\n",
915 cb, idxReg, GCPhysAddr, cb == 4 ? *(uint32_t *)pv : cb == 8 ? *(uint64_t *)pv : 0xdeadbeef));
916 NOREF(pvUser);
917 Assert(cb == 4 || cb == 8);
918
919 int rc;
920 if (cb == 4)
921 {
922 if (idxReg >= 0x100 && idxReg < 0x400)
923 rc = hpetTimerRegWrite32(pThis,
924 (idxReg - 0x100) / 0x20,
925 (idxReg - 0x100) % 0x20,
926 *(uint32_t const *)pv);
927 else
928 rc = hpetConfigRegWrite32(pThis, idxReg, *(uint32_t const *)pv);
929 }
930 else
931 {
932 /*
933 * 8-byte access.
934 */
935 /* Split the access and rely on the locking to prevent trouble. */
936 DEVHPET_LOCK_BOTH_RETURN(pThis, VINF_IOM_R3_MMIO_WRITE);
937 RTUINT64U uValue;
938 uValue.u = *(uint64_t const *)pv;
939 if (idxReg >= 0x100 && idxReg < 0x400)
940 {
941 uint32_t iTimer = (idxReg - 0x100) / 0x20;
942 uint32_t iTimerReg = (idxReg - 0x100) % 0x20;
943 /** @todo Consider handling iTimerReg == HPET_TN_CMP specially here */
944 rc = hpetTimerRegWrite32(pThis, iTimer, iTimerReg, uValue.s.Lo);
945 if (RT_LIKELY(rc == VINF_SUCCESS))
946 rc = hpetTimerRegWrite32(pThis, iTimer, iTimerReg + 4, uValue.s.Hi);
947 }
948 else
949 {
950 rc = hpetConfigRegWrite32(pThis, idxReg, uValue.s.Lo);
951 if (RT_LIKELY(rc == VINF_SUCCESS))
952 rc = hpetConfigRegWrite32(pThis, idxReg + 4, uValue.s.Hi);
953 }
954 DEVHPET_UNLOCK_BOTH(pThis);
955 }
956
957 return rc;
958}
959
960#ifdef IN_RING3
961
962/* -=-=-=-=-=- Timer Callback Processing -=-=-=-=-=- */
963
964/**
965 * Gets the IRQ of an HPET timer.
966 *
967 * @returns IRQ number.
968 * @param pHpetTimer The HPET timer.
969 */
970static uint32_t hpetR3TimerGetIrq(struct HPETTIMER const *pHpetTimer)
971{
972 /*
973 * Per spec, in legacy mode the HPET timers are wired as follows:
974 * timer 0: IRQ0 for PIC and IRQ2 for APIC
975 * timer 1: IRQ8 for both PIC and APIC
976 *
977 * ISA IRQ delivery logic will take care of correct delivery
978 * to the different ICs.
979 */
980 if ( (pHpetTimer->idxTimer <= 1)
981 && (pHpetTimer->CTX_SUFF(pHpet)->u64HpetConfig & HPET_CFG_LEGACY))
982 return (pHpetTimer->idxTimer == 0) ? 0 : 8;
983
984 return (pHpetTimer->u64Config & HPET_TN_INT_ROUTE_MASK) >> HPET_TN_INT_ROUTE_SHIFT;
985}
986
987
988/**
989 * Used by hpetR3Timer to update the IRQ status.
990 *
991 * @param pThis The HPET device state.
992 * @param pHpetTimer The HPET timer.
993 */
994static void hpetR3TimerUpdateIrq(HPET *pThis, struct HPETTIMER *pHpetTimer)
995{
996 /** @todo: is it correct? */
997 if ( !!(pHpetTimer->u64Config & HPET_TN_ENABLE)
998 && !!(pThis->u64HpetConfig & HPET_CFG_ENABLE))
999 {
1000 uint32_t irq = hpetR3TimerGetIrq(pHpetTimer);
1001 Log4(("HPET: raising IRQ %d\n", irq));
1002
1003 /* ISR bits are only set in level-triggered mode. */
1004 if ((pHpetTimer->u64Config & HPET_TN_INT_TYPE) == HPET_TIMER_TYPE_LEVEL)
1005 pThis->u64Isr |= UINT64_C(1) << pHpetTimer->idxTimer;
1006
1007 /* We trigger flip/flop in edge-triggered mode and do nothing in
1008 level-triggered mode yet. */
1009 if ((pHpetTimer->u64Config & HPET_TN_INT_TYPE) == HPET_TIMER_TYPE_EDGE)
1010 pThis->pHpetHlpR3->pfnSetIrq(pThis->CTX_SUFF(pDevIns), irq, PDM_IRQ_LEVEL_FLIP_FLOP);
1011 else
1012 AssertFailed();
1013 /** @todo: implement IRQs in level-triggered mode */
1014 }
1015}
1016
1017/**
1018 * Device timer callback function.
1019 *
1020 * @param pDevIns Device instance of the device which registered the timer.
1021 * @param pTimer The timer handle.
1022 * @param pvUser Pointer to the HPET timer state.
1023 */
1024static DECLCALLBACK(void) hpetR3Timer(PPDMDEVINS pDevIns, PTMTIMER pTimer, void *pvUser)
1025{
1026 HPET *pThis = PDMINS_2_DATA(pDevIns, HPET *);
1027 HPETTIMER *pHpetTimer = (HPETTIMER *)pvUser;
1028 uint64_t u64Period = pHpetTimer->u64Period;
1029 uint64_t u64CurTick = hpetGetTicks(pThis);
1030 uint64_t u64Diff;
1031
1032 if (pHpetTimer->u64Config & HPET_TN_PERIODIC)
1033 {
1034 if (u64Period) {
1035 hpetAdjustComparator(pHpetTimer, u64CurTick);
1036
1037 u64Diff = hpetComputeDiff(pHpetTimer, u64CurTick);
1038
1039 Log4(("HPET: periodic: next in %llu\n", hpetTicksToNs(pThis, u64Diff)));
1040 TMTimerSetNano(pTimer, hpetTicksToNs(pThis, u64Diff));
1041 }
1042 }
1043 else if (hpet32bitTimer(pHpetTimer))
1044 {
1045 /* For 32-bit non-periodic timers, generate wrap-around interrupts. */
1046 if (pHpetTimer->u8Wrap)
1047 {
1048 u64Diff = hpetComputeDiff(pHpetTimer, u64CurTick);
1049 TMTimerSetNano(pTimer, hpetTicksToNs(pThis, u64Diff));
1050 pHpetTimer->u8Wrap = 0;
1051 }
1052 }
1053
1054 /* Should it really be under lock, does it really matter? */
1055 hpetR3TimerUpdateIrq(pThis, pHpetTimer);
1056}
1057
1058
1059/* -=-=-=-=-=- DBGF Info Handlers -=-=-=-=-=- */
1060
1061
1062/**
1063 * @callback_method_impl{FNDBGFHANDLERDEV}
1064 */
1065static DECLCALLBACK(void) hpetR3Info(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
1066{
1067 HPET *pThis = PDMINS_2_DATA(pDevIns, HPET *);
1068 NOREF(pszArgs);
1069
1070 pHlp->pfnPrintf(pHlp,
1071 "HPET status:\n"
1072 " config=%016RX64 isr=%016RX64\n"
1073 " offset=%016RX64 counter=%016RX64 frequency=%08x\n"
1074 " legacy-mode=%s timer-count=%u\n",
1075 pThis->u64HpetConfig, pThis->u64Isr,
1076 pThis->u64HpetOffset, pThis->u64HpetCounter, pThis->u32Period,
1077 !!(pThis->u64HpetConfig & HPET_CFG_LEGACY) ? "on " : "off",
1078 HPET_CAP_GET_TIMERS(pThis->u32Capabilities));
1079 pHlp->pfnPrintf(pHlp,
1080 "Timers:\n");
1081 for (unsigned i = 0; i < RT_ELEMENTS(pThis->aTimers); i++)
1082 {
1083 pHlp->pfnPrintf(pHlp, " %d: comparator=%016RX64 period(hidden)=%016RX64 cfg=%016RX64\n",
1084 pThis->aTimers[i].idxTimer,
1085 pThis->aTimers[i].u64Cmp,
1086 pThis->aTimers[i].u64Period,
1087 pThis->aTimers[i].u64Config);
1088 }
1089}
1090
1091
1092/* -=-=-=-=-=- Saved State -=-=-=-=-=- */
1093
1094
1095/**
1096 * @callback_method_impl{FNSSMDEVLIVEEXEC}
1097 */
1098static DECLCALLBACK(int) hpetR3LiveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t uPass)
1099{
1100 HPET *pThis = PDMINS_2_DATA(pDevIns, HPET *);
1101 NOREF(uPass);
1102
1103 SSMR3PutU8(pSSM, HPET_CAP_GET_TIMERS(pThis->u32Capabilities));
1104
1105 return VINF_SSM_DONT_CALL_AGAIN;
1106}
1107
1108
1109/**
1110 * @callback_method_impl{FNSSMDEVSAVEEXEC}
1111 */
1112static DECLCALLBACK(int) hpetR3SaveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
1113{
1114 HPET *pThis = PDMINS_2_DATA(pDevIns, HPET *);
1115
1116 /*
1117 * The config.
1118 */
1119 hpetR3LiveExec(pDevIns, pSSM, SSM_PASS_FINAL);
1120
1121 /*
1122 * The state.
1123 */
1124 uint32_t const cTimers = HPET_CAP_GET_TIMERS(pThis->u32Capabilities);
1125 for (uint32_t iTimer = 0; iTimer < cTimers; iTimer++)
1126 {
1127 HPETTIMER *pHpetTimer = &pThis->aTimers[iTimer];
1128 TMR3TimerSave(pHpetTimer->pTimerR3, pSSM);
1129 SSMR3PutU8(pSSM, pHpetTimer->u8Wrap);
1130 SSMR3PutU64(pSSM, pHpetTimer->u64Config);
1131 SSMR3PutU64(pSSM, pHpetTimer->u64Cmp);
1132 SSMR3PutU64(pSSM, pHpetTimer->u64Fsb);
1133 SSMR3PutU64(pSSM, pHpetTimer->u64Period);
1134 }
1135
1136 SSMR3PutU64(pSSM, pThis->u64HpetOffset);
1137 uint64_t u64CapPer = RT_MAKE_U64(pThis->u32Capabilities, pThis->u32Period);
1138 SSMR3PutU64(pSSM, u64CapPer);
1139 SSMR3PutU64(pSSM, pThis->u64HpetConfig);
1140 SSMR3PutU64(pSSM, pThis->u64Isr);
1141 return SSMR3PutU64(pSSM, pThis->u64HpetCounter);
1142}
1143
1144
1145/**
1146 * @callback_method_impl{FNSSMDEVLOADEXEC}
1147 */
1148static DECLCALLBACK(int) hpetR3LoadExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
1149{
1150 HPET *pThis = PDMINS_2_DATA(pDevIns, HPET *);
1151
1152 /*
1153 * Version checks.
1154 */
1155 if (uVersion == HPET_SAVED_STATE_VERSION_EMPTY)
1156 return VINF_SUCCESS;
1157 if (uVersion != HPET_SAVED_STATE_VERSION)
1158 return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
1159
1160 /*
1161 * The config.
1162 */
1163 uint8_t cTimers;
1164 int rc = SSMR3GetU8(pSSM, &cTimers);
1165 AssertRCReturn(rc, rc);
1166 if (cTimers > RT_ELEMENTS(pThis->aTimers))
1167 return SSMR3SetCfgError(pSSM, RT_SRC_POS, N_("Config mismatch - too many timers: saved=%#x config=%#x"),
1168 cTimers, RT_ELEMENTS(pThis->aTimers));
1169
1170 if (uPass != SSM_PASS_FINAL)
1171 return VINF_SUCCESS;
1172
1173 /*
1174 * The state.
1175 */
1176 for (uint32_t iTimer = 0; iTimer < cTimers; iTimer++)
1177 {
1178 HPETTIMER *pHpetTimer = &pThis->aTimers[iTimer];
1179 TMR3TimerLoad(pHpetTimer->pTimerR3, pSSM);
1180 SSMR3GetU8(pSSM, &pHpetTimer->u8Wrap);
1181 SSMR3GetU64(pSSM, &pHpetTimer->u64Config);
1182 SSMR3GetU64(pSSM, &pHpetTimer->u64Cmp);
1183 SSMR3GetU64(pSSM, &pHpetTimer->u64Fsb);
1184 SSMR3GetU64(pSSM, &pHpetTimer->u64Period);
1185 }
1186
1187 SSMR3GetU64(pSSM, &pThis->u64HpetOffset);
1188 uint64_t u64CapPer;
1189 SSMR3GetU64(pSSM, &u64CapPer);
1190 SSMR3GetU64(pSSM, &pThis->u64HpetConfig);
1191 SSMR3GetU64(pSSM, &pThis->u64Isr);
1192 rc = SSMR3GetU64(pSSM, &pThis->u64HpetCounter);
1193 if (RT_FAILURE(rc))
1194 return rc;
1195 if (HPET_CAP_GET_TIMERS(RT_LO_U32(u64CapPer)) != cTimers)
1196 return SSMR3SetCfgError(pSSM, RT_SRC_POS, N_("Capabilities does not match timer count: cTimers=%#x caps=%#x"),
1197 cTimers, (unsigned)HPET_CAP_GET_TIMERS(u64CapPer));
1198 pThis->u32Capabilities = RT_LO_U32(u64CapPer);
1199 pThis->u32Period = RT_HI_U32(u64CapPer);
1200
1201 /*
1202 * Set the timer frequency hints.
1203 */
1204 PDMCritSectEnter(&pThis->CritSect, VERR_IGNORED);
1205 for (uint32_t iTimer = 0; iTimer < cTimers; iTimer++)
1206 {
1207 HPETTIMER *pHpetTimer = &pThis->aTimers[iTimer];
1208 if (TMTimerIsActive(pHpetTimer->CTX_SUFF(pTimer)))
1209 hpetTimerSetFrequencyHint(pThis, pHpetTimer);
1210 }
1211 PDMCritSectLeave(&pThis->CritSect);
1212 return VINF_SUCCESS;
1213}
1214
1215
1216/* -=-=-=-=-=- PDMDEVREG -=-=-=-=-=- */
1217
1218
1219/**
1220 * @interface_method_impl{PDMDEVREG,pfnRelocate}
1221 */
1222static DECLCALLBACK(void) hpetR3Relocate(PPDMDEVINS pDevIns, RTGCINTPTR offDelta)
1223{
1224 HPET *pThis = PDMINS_2_DATA(pDevIns, HPET *);
1225 LogFlow(("hpetR3Relocate:\n"));
1226 NOREF(offDelta);
1227
1228 pThis->pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
1229 pThis->pHpetHlpRC = pThis->pHpetHlpR3->pfnGetRCHelpers(pDevIns);
1230
1231 for (unsigned i = 0; i < RT_ELEMENTS(pThis->aTimers); i++)
1232 {
1233 HPETTIMER *pTm = &pThis->aTimers[i];
1234 if (pTm->pTimerR3)
1235 pTm->pTimerRC = TMTimerRCPtr(pTm->pTimerR3);
1236 pTm->pHpetRC = PDMINS_2_DATA_RCPTR(pDevIns);
1237 }
1238}
1239
1240
1241/**
1242 * @interface_method_impl{PDMDEVREG,pfnReset}
1243 */
1244static DECLCALLBACK(void) hpetR3Reset(PPDMDEVINS pDevIns)
1245{
1246 HPET *pThis = PDMINS_2_DATA(pDevIns, HPET *);
1247 LogFlow(("hpetR3Reset:\n"));
1248
1249 /*
1250 * The timers first.
1251 */
1252 TMTimerLock(pThis->aTimers[0].pTimerR3, VERR_IGNORED);
1253 for (unsigned i = 0; i < RT_ELEMENTS(pThis->aTimers); i++)
1254 {
1255 HPETTIMER *pHpetTimer = &pThis->aTimers[i];
1256 Assert(pHpetTimer->idxTimer == i);
1257 TMTimerStop(pHpetTimer->pTimerR3);
1258
1259 /* capable of periodic operations and 64-bits */
1260 if (pThis->fIch9)
1261 pHpetTimer->u64Config = (i == 0)
1262 ? (HPET_TN_PERIODIC_CAP | HPET_TN_SIZE_CAP)
1263 : 0;
1264 else
1265 pHpetTimer->u64Config = HPET_TN_PERIODIC_CAP | HPET_TN_SIZE_CAP;
1266
1267 /* We can do all IRQs */
1268 uint32_t u32RoutingCap = 0xffffffff;
1269 pHpetTimer->u64Config |= ((uint64_t)u32RoutingCap) << 32;
1270 pHpetTimer->u64Period = 0;
1271 pHpetTimer->u8Wrap = 0;
1272 pHpetTimer->u64Cmp = hpetInvalidValue(pHpetTimer);
1273 }
1274 TMTimerUnlock(pThis->aTimers[0].pTimerR3);
1275
1276 /*
1277 * The HPET state.
1278 */
1279 pThis->u64HpetConfig = 0;
1280 pThis->u64HpetCounter = 0;
1281 pThis->u64HpetOffset = 0;
1282
1283 /* 64-bit main counter; 3 timers supported; LegacyReplacementRoute. */
1284 pThis->u32Capabilities = (1 << 15) /* LEG_RT_CAP - LegacyReplacementRoute capable. */
1285 | (1 << 13) /* COUNTER_SIZE_CAP - Main counter is 64-bit capable. */
1286 | 1; /* REV_ID - Revision, must not be 0 */
1287 if (pThis->fIch9) /* NUM_TIM_CAP - Number of timers -1. */
1288 pThis->u32Capabilities |= (HPET_NUM_TIMERS_ICH9 - 1) << 8;
1289 else
1290 pThis->u32Capabilities |= (HPET_NUM_TIMERS_PIIX - 1) << 8;
1291 pThis->u32Capabilities |= UINT32_C(0x80860000); /* VENDOR */
1292 AssertCompile(HPET_NUM_TIMERS_ICH9 <= RT_ELEMENTS(pThis->aTimers));
1293 AssertCompile(HPET_NUM_TIMERS_PIIX <= RT_ELEMENTS(pThis->aTimers));
1294
1295 pThis->u32Period = pThis->fIch9 ? HPET_CLK_PERIOD_ICH9 : HPET_CLK_PERIOD_PIIX;
1296
1297 /*
1298 * Notify the PIT/RTC devices.
1299 */
1300 if (pThis->pHpetHlpR3)
1301 pThis->pHpetHlpR3->pfnSetLegacyMode(pDevIns, false /*fActive*/);
1302}
1303
1304
1305/**
1306 * @interface_method_impl{PDMDEVREG,pfnConstruct}
1307 */
1308static DECLCALLBACK(int) hpetR3Construct(PPDMDEVINS pDevIns, int iInstance, PCFGMNODE pCfg)
1309{
1310 PDMDEV_CHECK_VERSIONS_RETURN(pDevIns);
1311 HPET *pThis = PDMINS_2_DATA(pDevIns, HPET *);
1312
1313 /* Only one HPET device now, as we use fixed MMIO region. */
1314 Assert(iInstance == 0);
1315
1316 /*
1317 * Initialize the device state.
1318 */
1319 pThis->pDevInsR3 = pDevIns;
1320 pThis->pDevInsR0 = PDMDEVINS_2_R0PTR(pDevIns);
1321 pThis->pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
1322
1323 /* Init the HPET timers (init all regardless of how many we expose). */
1324 for (unsigned i = 0; i < RT_ELEMENTS(pThis->aTimers); i++)
1325 {
1326 HPETTIMER *pHpetTimer = &pThis->aTimers[i];
1327
1328 pHpetTimer->idxTimer = i;
1329 pHpetTimer->pHpetR3 = pThis;
1330 pHpetTimer->pHpetR0 = PDMINS_2_DATA_R0PTR(pDevIns);
1331 pHpetTimer->pHpetRC = PDMINS_2_DATA_RCPTR(pDevIns);
1332 }
1333
1334 /*
1335 * Validate and read the configuration.
1336 */
1337 PDMDEV_VALIDATE_CONFIG_RETURN(pDevIns, "GCEnabled|R0Enabled|ICH9", "");
1338
1339 bool fRCEnabled;
1340 int rc = CFGMR3QueryBoolDef(pCfg, "GCEnabled", &fRCEnabled, true);
1341 if (RT_FAILURE(rc))
1342 return PDMDEV_SET_ERROR(pDevIns, rc,
1343 N_("Configuration error: Querying \"GCEnabled\" as a bool failed"));
1344
1345 bool fR0Enabled;
1346 rc = CFGMR3QueryBoolDef(pCfg, "R0Enabled", &fR0Enabled, true);
1347 if (RT_FAILURE(rc))
1348 return PDMDEV_SET_ERROR(pDevIns, rc,
1349 N_("Configuration error: failed to read R0Enabled as boolean"));
1350
1351 rc = CFGMR3QueryBoolDef(pCfg, "ICH9", &pThis->fIch9, false);
1352 if (RT_FAILURE(rc))
1353 return PDMDEV_SET_ERROR(pDevIns, rc,
1354 N_("Configuration error: failed to read ICH9 as boolean"));
1355
1356
1357 /*
1358 * Create critsect and timers.
1359 * Note! We don't use the default critical section of the device, but our own.
1360 */
1361 rc = PDMDevHlpCritSectInit(pDevIns, &pThis->CritSect, RT_SRC_POS, "HPET");
1362 AssertRCReturn(rc, rc);
1363
1364 rc = PDMDevHlpSetDeviceCritSect(pDevIns, PDMDevHlpCritSectGetNop(pDevIns));
1365 AssertRCReturn(rc, rc);
1366
1367 /* Init the HPET timers (init all regardless of how many we expose). */
1368 for (unsigned i = 0; i < RT_ELEMENTS(pThis->aTimers); i++)
1369 {
1370 HPETTIMER *pHpetTimer = &pThis->aTimers[i];
1371
1372 rc = PDMDevHlpTMTimerCreate(pDevIns, TMCLOCK_VIRTUAL_SYNC, hpetR3Timer, pHpetTimer,
1373 TMTIMER_FLAGS_NO_CRIT_SECT, "HPET Timer",
1374 &pThis->aTimers[i].pTimerR3);
1375 AssertRCReturn(rc, rc);
1376 pThis->aTimers[i].pTimerRC = TMTimerRCPtr(pThis->aTimers[i].pTimerR3);
1377 pThis->aTimers[i].pTimerR0 = TMTimerR0Ptr(pThis->aTimers[i].pTimerR3);
1378 rc = TMR3TimerSetCritSect(pThis->aTimers[i].pTimerR3, &pThis->CritSect);
1379 AssertRCReturn(rc, rc);
1380 }
1381
1382 /*
1383 * This must be done prior to registering the HPET, right?
1384 */
1385 hpetR3Reset(pDevIns);
1386
1387 /*
1388 * Register the HPET and get helpers.
1389 */
1390 PDMHPETREG HpetReg;
1391 HpetReg.u32Version = PDM_HPETREG_VERSION;
1392 rc = PDMDevHlpHPETRegister(pDevIns, &HpetReg, &pThis->pHpetHlpR3);
1393 AssertRCReturn(rc, rc);
1394
1395 /*
1396 * Register the MMIO range, PDM API requests page aligned
1397 * addresses and sizes.
1398 */
1399 rc = PDMDevHlpMMIORegister(pDevIns, HPET_BASE, HPET_BAR_SIZE, pThis,
1400 IOMMMIO_FLAGS_READ_DWORD_QWORD | IOMMMIO_FLAGS_WRITE_ONLY_DWORD_QWORD,
1401 hpetMMIOWrite, hpetMMIORead, "HPET Memory");
1402 AssertRCReturn(rc, rc);
1403
1404 if (fRCEnabled)
1405 {
1406 rc = PDMDevHlpMMIORegisterRC(pDevIns, HPET_BASE, HPET_BAR_SIZE, NIL_RTRCPTR /*pvUser*/, "hpetMMIOWrite", "hpetMMIORead");
1407 AssertRCReturn(rc, rc);
1408
1409 pThis->pHpetHlpRC = pThis->pHpetHlpR3->pfnGetRCHelpers(pDevIns);
1410 }
1411
1412 if (fR0Enabled)
1413 {
1414 rc = PDMDevHlpMMIORegisterR0(pDevIns, HPET_BASE, HPET_BAR_SIZE, NIL_RTR0PTR /*pvUser*/,
1415 "hpetMMIOWrite", "hpetMMIORead");
1416 AssertRCReturn(rc, rc);
1417
1418 pThis->pHpetHlpR0 = pThis->pHpetHlpR3->pfnGetR0Helpers(pDevIns);
1419 AssertReturn(pThis->pHpetHlpR0 != NIL_RTR0PTR, VERR_INTERNAL_ERROR);
1420 }
1421
1422 /* Register SSM callbacks */
1423 rc = PDMDevHlpSSMRegister3(pDevIns, HPET_SAVED_STATE_VERSION, sizeof(*pThis), hpetR3LiveExec, hpetR3SaveExec, hpetR3LoadExec);
1424 AssertRCReturn(rc, rc);
1425
1426 /* Register an info callback. */
1427 PDMDevHlpDBGFInfoRegister(pDevIns, "hpet", "Display HPET status. (no arguments)", hpetR3Info);
1428
1429 return VINF_SUCCESS;
1430}
1431
1432
1433/**
1434 * The device registration structure.
1435 */
1436const PDMDEVREG g_DeviceHPET =
1437{
1438 /* u32Version */
1439 PDM_DEVREG_VERSION,
1440 /* szName */
1441 "hpet",
1442 /* szRCMod */
1443 "VBoxDDRC.rc",
1444 /* szR0Mod */
1445 "VBoxDDR0.r0",
1446 /* pszDescription */
1447 " High Precision Event Timer (HPET) Device",
1448 /* fFlags */
1449 PDM_DEVREG_FLAGS_HOST_BITS_DEFAULT | PDM_DEVREG_FLAGS_GUEST_BITS_32_64 | PDM_DEVREG_FLAGS_PAE36
1450 | PDM_DEVREG_FLAGS_RC | PDM_DEVREG_FLAGS_R0,
1451 /* fClass */
1452 PDM_DEVREG_CLASS_PIT,
1453 /* cMaxInstances */
1454 1,
1455 /* cbInstance */
1456 sizeof(HPET),
1457 /* pfnConstruct */
1458 hpetR3Construct,
1459 /* pfnDestruct */
1460 NULL,
1461 /* pfnRelocate */
1462 hpetR3Relocate,
1463 /* pfnMemSetup */
1464 NULL,
1465 /* pfnPowerOn */
1466 NULL,
1467 /* pfnReset */
1468 hpetR3Reset,
1469 /* pfnSuspend */
1470 NULL,
1471 /* pfnResume */
1472 NULL,
1473 /* pfnAttach */
1474 NULL,
1475 /* pfnDetach */
1476 NULL,
1477 /* pfnQueryInterface. */
1478 NULL,
1479 /* pfnInitComplete */
1480 NULL,
1481 /* pfnPowerOff */
1482 NULL,
1483 /* pfnSoftReset */
1484 NULL,
1485 /* u32VersionEnd */
1486 PDM_DEVREG_VERSION
1487};
1488
1489#endif /* IN_RING3 */
1490#endif /* !VBOX_DEVICE_STRUCT_TESTCASE */
1491
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