DevHPET.cpp@ 42202

Last change on this file since 42202 was 41983, checked in by vboxsync, 12 years ago
DevHPET: parfait hint
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1	/* $Id: DevHPET.cpp 41983 2012-07-02 12:23:44Z vboxsync $ */
2	/** @file
3	* HPET virtual device - high precision event timer emulation
4	*/
5
6	/*
7	* Copyright (C) 2009-2011 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18	/*******************************************************************************
19	* Header Files *
20	*******************************************************************************/
21	#define LOG_GROUP LOG_GROUP_DEV_HPET
22	#include <VBox/vmm/pdmdev.h>
23	#include <VBox/vmm/stam.h>
24	#include <VBox/log.h>
25	#include <iprt/assert.h>
26	#include <iprt/asm-math.h>
27	#include <iprt/string.h>
28
29	#include "VBoxDD.h"
30
31
32	/*******************************************************************************
33	* Defined Constants And Macros *
34	*******************************************************************************/
35	/*
36	* Current limitations:
37	* - not entirely correct time of interrupt, i.e. never
38	* schedule interrupt earlier than in 1ms
39	* - statistics not implemented
40	* - level-triggered mode not implemented
41	*/
42
43	/** Base address for MMIO. */
44	#define HPET_BASE 0xfed00000
45
46	/** The number of timers for PIIX4 / PIIX3. */
47	#define HPET_NUM_TIMERS_PIIX 3
48	/** The number of timers for ICH9. */
49	#define HPET_NUM_TIMERS_ICH9 4
50
51	/** HPET clock period for PIIX4 / PIIX3.
52	* 10000000 femtoseconds == 10ns.
53	*/
54	#define HPET_CLK_PERIOD_PIIX UINT32_C(10000000)
55
56	/** HPET clock period for ICH9.
57	* 69841279 femtoseconds == 69.84 ns (1 / 14.31818MHz).
58	*/
59	#define HPET_CLK_PERIOD_ICH9 UINT32_C(69841279)
60
61	/*
62	* Femptosecods in nanosecond
63	*/
64	#define FS_PER_NS 1000000
65
66	/*
67	* Interrupt type
68	*/
69	#define HPET_TIMER_TYPE_LEVEL 1
70	#define HPET_TIMER_TYPE_EDGE 0
71
72	/* Delivery mode */
73	/* Via APIC */
74	#define HPET_TIMER_DELIVERY_APIC 0
75	/* Via FSB */
76	#define HPET_TIMER_DELIVERY_FSB 1
77
78	#define HPET_TIMER_CAP_FSB_INT_DEL (1 << 15)
79	#define HPET_TIMER_CAP_PER_INT (1 << 4)
80
81	#define HPET_CFG_ENABLE 0x001 /* ENABLE_CNF */
82	#define HPET_CFG_LEGACY 0x002 /* LEG_RT_CNF */
83
84	#define HPET_ID 0x000
85	#define HPET_PERIOD 0x004
86	#define HPET_CFG 0x010
87	#define HPET_STATUS 0x020
88	#define HPET_COUNTER 0x0f0
89	#define HPET_TN_CFG 0x000
90	#define HPET_TN_CMP 0x008
91	#define HPET_TN_ROUTE 0x010
92	#define HPET_CFG_WRITE_MASK 0x3
93
94	#define HPET_TN_INT_TYPE RT_BIT_64(1)
95	#define HPET_TN_ENABLE RT_BIT_64(2)
96	#define HPET_TN_PERIODIC RT_BIT_64(3)
97	#define HPET_TN_PERIODIC_CAP RT_BIT_64(4)
98	#define HPET_TN_SIZE_CAP RT_BIT_64(5)
99	#define HPET_TN_SETVAL RT_BIT_64(6)
100	#define HPET_TN_32BIT RT_BIT_64(8)
101	#define HPET_TN_INT_ROUTE_MASK UINT64_C(0x3e00)
102	#define HPET_TN_CFG_WRITE_MASK UINT64_C(0x3e46)
103	#define HPET_TN_INT_ROUTE_SHIFT 9
104	#define HPET_TN_INT_ROUTE_CAP_SHIFT 32
105	#define HPET_TN_CFG_BITS_READONLY_OR_RESERVED 0xffff80b1U
106
107	/** Extract the timer count from the capabilities.
108	* @todo Check if the mask is correct. */
109	#define HPET_CAP_GET_TIMERS(a_u32) ( ((a_u32) >> 8) & 0xf )
110
111	/** The version of the saved state. */
112	#define HPET_SAVED_STATE_VERSION 2
113	/** Empty saved state */
114	#define HPET_SAVED_STATE_VERSION_EMPTY 1
115
116
117	/**
118	* Acquires the HPET lock or returns.
119	*/
120	#define DEVHPET_LOCK_RETURN(a_pThis, a_rcBusy) \
121	do { \
122	int rcLock = PDMCritSectEnter(&(a_pThis)->csLock, (a_rcBusy)); \
123	if (rcLock != VINF_SUCCESS) \
124	return rcLock; \
125	} while (0)
126
127	/**
128	* Releases the HPET lock.
129	*/
130	#define DEVHPET_UNLOCK(a_pThis) \
131	do { PDMCritSectLeave(&(a_pThis)->csLock); } while (0)
132
133
134	/**
135	* Acquires the TM lock and HPET lock, returns on failure.
136	*/
137	#define DEVHPET_LOCK_BOTH_RETURN(a_pThis, a_rcBusy) \
138	do { \
139	int rcLock = TMTimerLock((a_pThis)->aTimers[0].CTX_SUFF(pTimer), (a_rcBusy)); \
140	if (rcLock != VINF_SUCCESS) \
141	return rcLock; \
142	rcLock = PDMCritSectEnter(&(a_pThis)->csLock, (a_rcBusy)); \
143	if (rcLock != VINF_SUCCESS) \
144	{ \
145	TMTimerUnlock((a_pThis)->aTimers[0].CTX_SUFF(pTimer)); \
146	return rcLock; \
147	} \
148	} while (0)
149
150
151	/**
152	* Releases the HPET lock and TM lock.
153	*/
154	#define DEVHPET_UNLOCK_BOTH(a_pThis) \
155	do { \
156	PDMCritSectLeave(&(a_pThis)->csLock); \
157	TMTimerUnlock((a_pThis)->aTimers[0].CTX_SUFF(pTimer)); \
158	} while (0)
159
160
161	/*******************************************************************************
162	* Structures and Typedefs *
163	*******************************************************************************/
164	struct HpetState;
165	typedef struct HpetTimer
166	{
167	/** The HPET timer - R3 Ptr. */
168	PTMTIMERR3 pTimerR3;
169	/** Pointer to the instance data - R3 Ptr. */
170	R3PTRTYPE(struct HpetState *) pHpetR3;
171
172	/** The HPET timer - R0 Ptr. */
173	PTMTIMERR0 pTimerR0;
174	/** Pointer to the instance data - R0 Ptr. */
175	R0PTRTYPE(struct HpetState *) pHpetR0;
176
177	/** The HPET timer - RC Ptr. */
178	PTMTIMERRC pTimerRC;
179	/** Pointer to the instance data - RC Ptr. */
180	RCPTRTYPE(struct HpetState *) pHpetRC;
181
182	/** Timer index. */
183	uint8_t idxTimer;
184	/** Wrap. */
185	uint8_t u8Wrap;
186	/** Alignment. */
187	uint32_t alignment0;
188
189	/** @name Memory-mapped, software visible timer registers.
190	* @{ */
191	/** Configuration/capabilities. */
192	uint64_t u64Config;
193	/** Comparator. */
194	uint64_t u64Cmp;
195	/** FSB route, not supported now. */
196	uint64_t u64Fsb;
197	/** @} */
198
199	/** @name Hidden register state.
200	* @{ */
201	/** Last value written to comparator. */
202	uint64_t u64Period;
203	/** @} */
204	} HpetTimer;
205	AssertCompileMemberAlignment(HpetTimer, u64Config, sizeof(uint64_t));
206
207	typedef struct HpetState
208	{
209	/** Pointer to the device instance. - R3 ptr. */
210	PPDMDEVINSR3 pDevInsR3;
211	/** The HPET helpers - R3 Ptr. */
212	PCPDMHPETHLPR3 pHpetHlpR3;
213
214	/** Pointer to the device instance. - R0 ptr. */
215	PPDMDEVINSR0 pDevInsR0;
216	/** The HPET helpers - R0 Ptr. */
217	PCPDMHPETHLPR0 pHpetHlpR0;
218
219	/** Pointer to the device instance. - RC ptr. */
220	PPDMDEVINSRC pDevInsRC;
221	/** The HPET helpers - RC Ptr. */
222	PCPDMHPETHLPRC pHpetHlpRC;
223
224	/** Timer structures. */
225	HpetTimer aTimers[RT_MAX(HPET_NUM_TIMERS_PIIX, HPET_NUM_TIMERS_ICH9)];
226
227	/** Offset realtive to the virtual sync clock. */
228	uint64_t u64HpetOffset;
229
230	/** @name Memory-mapped, software visible registers
231	* @{ */
232	/** Capabilities. */
233	uint32_t u32Capabilities;
234	/** HPET_PERIOD - . */
235	uint32_t u32Period;
236	/** Configuration. */
237	uint64_t u64HpetConfig;
238	/** Interrupt status register. */
239	uint64_t u64Isr;
240	/** Main counter. */
241	uint64_t u64HpetCounter;
242	/** @} */
243
244	/** Global device lock. */
245	PDMCRITSECT csLock;
246
247	/** If we emulate ICH9 HPET (different frequency & timer count). */
248	bool fIch9;
249	uint8_t padding0[7];
250	} HpetState;
251
252
253	#ifndef VBOX_DEVICE_STRUCT_TESTCASE
254
255
256	DECLINLINE(bool) hpet32bitTimer(HpetTimer *pHpetTimer)
257	{
258	uint64_t u64Cfg = pHpetTimer->u64Config;
259
260	return ((u64Cfg & HPET_TN_SIZE_CAP) == 0) \|\| ((u64Cfg & HPET_TN_32BIT) != 0);
261	}
262
263	DECLINLINE(uint64_t) hpetInvalidValue(HpetTimer *pHpetTimer)
264	{
265	return hpet32bitTimer(pHpetTimer) ? UINT32_MAX : UINT64_MAX;
266	}
267
268	DECLINLINE(uint32_t) hpetTimeAfter32(uint64_t a, uint64_t b)
269	{
270	return ((int32_t)(b) - (int32_t)(a) <= 0);
271	}
272
273	DECLINLINE(uint32_t) hpetTimeAfter64(uint64_t a, uint64_t b)
274	{
275	return ((int64_t)(b) - (int64_t)(a) <= 0);
276	}
277
278	DECLINLINE(uint64_t) hpetTicksToNs(HpetState *pThis, uint64_t value)
279	{
280	return ASMMultU64ByU32DivByU32(value, pThis->u32Period, FS_PER_NS);
281	}
282
283	DECLINLINE(uint64_t) nsToHpetTicks(HpetState const *pThis, uint64_t u64Value)
284	{
285	return ASMMultU64ByU32DivByU32(u64Value, FS_PER_NS, pThis->u32Period);
286	}
287
288	DECLINLINE(uint64_t) hpetGetTicks(HpetState const *pThis)
289	{
290	/*
291	* We can use any timer to get current time, they all go
292	* with the same speed.
293	*/
294	return nsToHpetTicks(pThis,
295	TMTimerGet(pThis->aTimers[0].CTX_SUFF(pTimer))
296	+ pThis->u64HpetOffset);
297	}
298
299	DECLINLINE(uint64_t) hpetUpdateMasked(uint64_t u64NewValue,
300	uint64_t u64OldValue,
301	uint64_t u64Mask)
302	{
303	u64NewValue &= u64Mask;
304	u64NewValue \|= (u64OldValue & ~u64Mask);
305	return u64NewValue;
306	}
307
308	DECLINLINE(bool) hpetBitJustSet(uint64_t u64OldValue,
309	uint64_t u64NewValue,
310	uint64_t u64Mask)
311	{
312	return !(u64OldValue & u64Mask)
313	&& !!(u64NewValue & u64Mask);
314	}
315
316	DECLINLINE(bool) hpetBitJustCleared(uint64_t u64OldValue,
317	uint64_t u64NewValue,
318	uint64_t u64Mask)
319	{
320	return !!(u64OldValue & u64Mask)
321	&& !(u64NewValue & u64Mask);
322	}
323
324	DECLINLINE(uint64_t) hpetComputeDiff(HpetTimer *pHpetTimer,
325	uint64_t u64Now)
326	{
327
328	if (hpet32bitTimer(pHpetTimer))
329	{
330	uint32_t u32Diff;
331
332	u32Diff = (uint32_t)pHpetTimer->u64Cmp - (uint32_t)u64Now;
333	u32Diff = ((int32_t)u32Diff > 0) ? u32Diff : (uint32_t)0;
334	return (uint64_t)u32Diff;
335	}
336	else
337	{
338	uint64_t u64Diff;
339
340	u64Diff = pHpetTimer->u64Cmp - u64Now;
341	u64Diff = ((int64_t)u64Diff > 0) ? u64Diff : (uint64_t)0;
342	return u64Diff;
343	}
344	}
345
346
347	static void hpetAdjustComparator(HpetTimer *pHpetTimer, uint64_t u64Now)
348	{
349	uint64_t u64Period = pHpetTimer->u64Period;
350	if ( (pHpetTimer->u64Config & HPET_TN_PERIODIC)
351	&& u64Period != 0)
352	{
353	/* While loop is suboptimal */
354	if (hpet32bitTimer(pHpetTimer))
355	{
356	while (hpetTimeAfter32(u64Now, pHpetTimer->u64Cmp))
357	pHpetTimer->u64Cmp = (uint32_t)(pHpetTimer->u64Cmp + u64Period);
358	}
359	else
360	{
361	while (hpetTimeAfter64(u64Now, pHpetTimer->u64Cmp))
362	pHpetTimer->u64Cmp += u64Period;
363	}
364	}
365	}
366
367
368	/**
369	* Sets the frequency hint if it's a periodic timer.
370	*
371	* @param pThis The HPET state.
372	* @param pHpetTimer The timer.
373	*/
374	DECLINLINE(void) hpetTimerSetFrequencyHint(HpetState pThis, HpetTimer pHpetTimer)
375	{
376	if (pHpetTimer->u64Config & HPET_TN_PERIODIC)
377	{
378	uint64_t const u64Period = pHpetTimer->u64Period;
379	uint32_t const u32Freq = pThis->u32Period;
380	if (u64Period > 0 && u64Period < u32Freq)
381	TMTimerSetFrequencyHint(pHpetTimer->CTX_SUFF(pTimer), u32Freq / (uint32_t)u64Period);
382	}
383	}
384
385
386	static void hpetProgramTimer(HpetTimer *pHpetTimer)
387	{
388	/* no wrapping on new timers */
389	pHpetTimer->u8Wrap = 0;
390
391	uint64_t u64Ticks = hpetGetTicks(pHpetTimer->CTX_SUFF(pHpet));
392	hpetAdjustComparator(pHpetTimer, u64Ticks);
393
394	uint64_t u64Diff = hpetComputeDiff(pHpetTimer, u64Ticks);
395
396	/*
397	* HPET spec says in one-shot 32-bit mode, generate an interrupt when
398	* counter wraps in addition to an interrupt with comparator match.
399	*/
400	if ( hpet32bitTimer(pHpetTimer)
401	&& !(pHpetTimer->u64Config & HPET_TN_PERIODIC))
402	{
403	uint32_t u32TillWrap = 0xffffffff - (uint32_t)u64Ticks + 1;
404	if (u32TillWrap < (uint32_t)u64Diff)
405	{
406	Log(("wrap on timer %d: till=%u ticks=%lld diff64=%lld\n",
407	pHpetTimer->idxTimer, u32TillWrap, u64Ticks, u64Diff));
408	u64Diff = u32TillWrap;
409	pHpetTimer->u8Wrap = 1;
410	}
411	}
412
413	/*
414	* HACK ALERT! Avoid killing VM with interrupts.
415	*/
416	#if 1 /** @todo: HACK, rethink, may have negative impact on the guest */
417	if (u64Diff == 0)
418	u64Diff = 100000; /* 1 millisecond */
419	#endif
420
421	Log4(("HPET: next IRQ in %lld ticks (%lld ns)\n", u64Diff, hpetTicksToNs(pHpetTimer->CTX_SUFF(pHpet), u64Diff)));
422	TMTimerSetNano(pHpetTimer->CTX_SUFF(pTimer), hpetTicksToNs(pHpetTimer->CTX_SUFF(pHpet), u64Diff));
423	hpetTimerSetFrequencyHint(pHpetTimer->CTX_SUFF(pHpet), pHpetTimer);
424	}
425
426
427	/* -=-=-=-=-=- Timer register accesses -=-=-=-=-=- */
428
429
430	/**
431	* Reads a HPET timer register.
432	*
433	* @returns VBox strict status code.
434	* @param pThis The HPET instance.
435	* @param iTimerNo The timer index.
436	* @param iTimerReg The index of the timer register to read.
437	* @param pu32Value Where to return the register value.
438	*
439	* @remarks ASSUMES the caller does holds the HPET lock.
440	*/
441	static int hpetTimerRegRead32(HpetState const pThis, uint32_t iTimerNo, uint32_t iTimerReg, uint32_t pu32Value)
442	{
443	Assert(PDMCritSectIsOwner(&pThis->csLock));
444
445	if ( iTimerNo >= RT_ELEMENTS(pThis->aTimers) /* parfait */
446	\|\| iTimerNo >= HPET_CAP_GET_TIMERS(pThis->u32Capabilities))
447	{
448	static unsigned s_cOccurences = 0;
449	if (s_cOccurences++ < 10)
450	LogRel(("HPET: using timer above configured range: %d\n", iTimerNo));
451	*pu32Value = 0;
452	return VINF_SUCCESS;
453	}
454
455	HpetTimer const *pHpetTimer = &pThis->aTimers[iTimerNo];
456	uint32_t u32Value;
457	switch (iTimerReg)
458	{
459	case HPET_TN_CFG:
460	u32Value = (uint32_t)pHpetTimer->u64Config;
461	Log(("read HPET_TN_CFG on %d: %#x\n", iTimerNo, u32Value));
462	break;
463
464	case HPET_TN_CFG + 4:
465	u32Value = (uint32_t)(pHpetTimer->u64Config >> 32);
466	Log(("read HPET_TN_CFG+4 on %d: %#x\n", iTimerNo, u32Value));
467	break;
468
469	case HPET_TN_CMP:
470	u32Value = (uint32_t)pHpetTimer->u64Cmp;
471	Log(("read HPET_TN_CMP on %d: %#x (%#llx)\n", pHpetTimer->idxTimer, u32Value, pHpetTimer->u64Cmp));
472	break;
473
474	case HPET_TN_CMP + 4:
475	u32Value = (uint32_t)(pHpetTimer->u64Cmp >> 32);
476	Log(("read HPET_TN_CMP+4 on %d: %#x (%#llx)\n", pHpetTimer->idxTimer, u32Value, pHpetTimer->u64Cmp));
477	break;
478
479	case HPET_TN_ROUTE:
480	u32Value = (uint32_t)(pHpetTimer->u64Fsb >> 32); /** @todo Looks wrong, but since it's not supported, who cares. */
481	Log(("read HPET_TN_ROUTE on %d: %#x\n", iTimerNo, u32Value));
482	break;
483
484	default:
485	{
486	static unsigned s_cOccurences = 0;
487	if (s_cOccurences++ < 10)
488	LogRel(("invalid HPET register read %d on %d\n", iTimerReg, pHpetTimer->idxTimer));
489	u32Value = 0;
490	break;
491	}
492	}
493	*pu32Value = u32Value;
494	return VINF_SUCCESS;
495	}
496
497
498	/**
499	* 32-bit write to a HPET timer register.
500	*
501	* @returns Strict VBox status code.
502	*
503	* @param pThis The HPET state.
504	* @param idxReg The register being written to.
505	* @param u32NewValue The value being written.
506	*
507	* @remarks The caller should not hold the device lock, unless it also holds
508	* the TM lock.
509	*/
510	static int hpetTimerRegWrite32(HpetState *pThis, uint32_t iTimerNo, uint32_t iTimerReg, uint32_t u32NewValue)
511	{
512	Assert(!PDMCritSectIsOwner(&pThis->csLock) \|\| TMTimerIsLockOwner(pThis->aTimers[0].CTX_SUFF(pTimer)));
513
514	if ( iTimerNo >= RT_ELEMENTS(pThis->aTimers) /* parfait */
515	\|\| iTimerNo >= HPET_CAP_GET_TIMERS(pThis->u32Capabilities))
516	{
517	static unsigned s_cOccurences = 0;
518	if (s_cOccurences++ < 10)
519	LogRel(("HPET: using timer above configured range: %d\n", iTimerNo));
520	return VINF_SUCCESS;
521	}
522	HpetTimer *pHpetTimer = &pThis->aTimers[iTimerNo];
523
524	switch (iTimerReg)
525	{
526	case HPET_TN_CFG:
527	{
528	DEVHPET_LOCK_RETURN(pThis, VINF_IOM_R3_MMIO_WRITE);
529	Log(("write HPET_TN_CFG: %d: %x\n", iTimerNo, u32NewValue));
530	uint64_t const iOldValue = (uint32_t)pHpetTimer->u64Config;
531
532	uint64_t u64Mask = HPET_TN_CFG_WRITE_MASK;
533	if (pHpetTimer->u64Config & HPET_TN_PERIODIC_CAP)
534	u64Mask \|= HPET_TN_PERIODIC;
535
536	if (pHpetTimer->u64Config & HPET_TN_SIZE_CAP)
537	u64Mask \|= HPET_TN_32BIT;
538	else
539	u32NewValue &= ~HPET_TN_32BIT;
540
541	if (u32NewValue & HPET_TN_32BIT)
542	{
543	Log(("setting timer %d to 32-bit mode\n", iTimerNo));
544	pHpetTimer->u64Cmp = (uint32_t)pHpetTimer->u64Cmp;
545	pHpetTimer->u64Period = (uint32_t)pHpetTimer->u64Period;
546	}
547	if ((u32NewValue & HPET_TN_INT_TYPE) == HPET_TIMER_TYPE_LEVEL)
548	{
549	static unsigned s_cOccurences = 0;
550	if (s_cOccurences++ < 10)
551	LogRel(("level-triggered config not yet supported\n"));
552	AssertFailed();
553	}
554
555	/* We only care about lower 32-bits so far */
556	pHpetTimer->u64Config = hpetUpdateMasked(u32NewValue, iOldValue, u64Mask);
557	DEVHPET_UNLOCK(pThis);
558	break;
559	}
560
561	case HPET_TN_CFG + 4: /* Interrupt capabilities */
562	{
563	Log(("write HPET_TN_CFG + 4, useless\n"));
564	break;
565	}
566
567	case HPET_TN_CMP: /* lower bits of comparator register */
568	{
569	DEVHPET_LOCK_BOTH_RETURN(pThis, VINF_IOM_R3_MMIO_WRITE);
570	Log(("write HPET_TN_CMP on %d: %#x\n", iTimerNo, u32NewValue));
571
572	if (pHpetTimer->u64Config & HPET_TN_PERIODIC)
573	{
574	u32NewValue &= hpetInvalidValue(pHpetTimer) >> 1; /** @todo check this in the docs and add a not why? */
575	pHpetTimer->u64Period = RT_MAKE_U64(u32NewValue, pHpetTimer->u64Period);
576	}
577	pHpetTimer->u64Cmp = RT_MAKE_U64(u32NewValue, pHpetTimer->u64Cmp);
578	pHpetTimer->u64Config &= ~HPET_TN_SETVAL;
579	Log2(("after HPET_TN_CMP cmp=%#llx per=%#llx\n", pHpetTimer->u64Cmp, pHpetTimer->u64Period));
580
581	if (pThis->u64HpetConfig & HPET_CFG_ENABLE)
582	hpetProgramTimer(pHpetTimer);
583	DEVHPET_UNLOCK_BOTH(pThis);
584	break;
585	}
586
587	case HPET_TN_CMP + 4: /* upper bits of comparator register */
588	{
589	DEVHPET_LOCK_BOTH_RETURN(pThis, VINF_IOM_R3_MMIO_WRITE);
590	Log(("write HPET_TN_CMP + 4 on %d: %#x\n", iTimerNo, u32NewValue));
591	if (!hpet32bitTimer(pHpetTimer))
592	{
593	if (pHpetTimer->u64Config & HPET_TN_PERIODIC)
594	pHpetTimer->u64Period = RT_MAKE_U64(pHpetTimer->u64Period, u32NewValue);
595	pHpetTimer->u64Cmp = RT_MAKE_U64(pHpetTimer->u64Cmp, u32NewValue);
596
597	Log2(("after HPET_TN_CMP+4 cmp=%llx per=%llx tmr=%d\n", pHpetTimer->u64Cmp, pHpetTimer->u64Period, iTimerNo));
598
599	pHpetTimer->u64Config &= ~HPET_TN_SETVAL;
600
601	if (pThis->u64HpetConfig & HPET_CFG_ENABLE)
602	hpetProgramTimer(pHpetTimer);
603	}
604	DEVHPET_UNLOCK_BOTH(pThis);
605	break;
606	}
607
608	case HPET_TN_ROUTE:
609	{
610	Log(("write HPET_TN_ROUTE\n"));
611	break;
612	}
613
614	case HPET_TN_ROUTE + 4:
615	{
616	Log(("write HPET_TN_ROUTE + 4\n"));
617	break;
618	}
619
620	default:
621	{
622	static unsigned s_cOccurences = 0;
623	if (s_cOccurences++ < 10)
624	LogRel(("invalid timer register write: %d\n", iTimerReg));
625	break;
626	}
627	}
628
629	return VINF_SUCCESS;
630	}
631
632
633	/* -=-=-=-=-=- Non-timer register accesses -=-=-=-=-=- */
634
635
636	/**
637	* Read a 32-bit HPET register.
638	*
639	* @returns Strict VBox status code.
640	* @param pThis The HPET state.
641	* @param idxReg The register to read.
642	* @param pu32Value Where to return the register value.
643	*
644	* @remarks The caller must not own the device lock if HPET_COUNTER is read.
645	*/
646	static int hpetConfigRegRead32(HpetState pThis, uint32_t idxReg, uint32_t pu32Value)
647	{
648	Assert(!PDMCritSectIsOwner(&pThis->csLock) \|\| (idxReg != HPET_COUNTER && idxReg != HPET_COUNTER + 4));
649
650	uint32_t u32Value;
651	switch (idxReg)
652	{
653	case HPET_ID:
654	DEVHPET_LOCK_RETURN(pThis, VINF_IOM_R3_MMIO_READ);
655	u32Value = pThis->u32Capabilities;
656	DEVHPET_UNLOCK(pThis);
657	Log(("read HPET_ID: %#x\n", u32Value));
658	break;
659
660	case HPET_PERIOD:
661	DEVHPET_LOCK_RETURN(pThis, VINF_IOM_R3_MMIO_READ);
662	u32Value = pThis->u32Period;
663	DEVHPET_UNLOCK(pThis);
664	Log(("read HPET_PERIOD: %#x\n", u32Value));
665	break;
666
667	case HPET_CFG:
668	DEVHPET_LOCK_RETURN(pThis, VINF_IOM_R3_MMIO_READ);
669	u32Value = (uint32_t)pThis->u64HpetConfig;
670	DEVHPET_UNLOCK(pThis);
671	Log(("read HPET_CFG: %#x\n", u32Value));
672	break;
673
674	case HPET_CFG + 4:
675	DEVHPET_LOCK_RETURN(pThis, VINF_IOM_R3_MMIO_READ);
676	u32Value = (uint32_t)(pThis->u64HpetConfig >> 32);
677	DEVHPET_UNLOCK(pThis);
678	Log(("read of HPET_CFG + 4: %#x\n", u32Value));
679	break;
680
681	case HPET_COUNTER:
682	case HPET_COUNTER + 4:
683	{
684	DEVHPET_LOCK_BOTH_RETURN(pThis, VINF_IOM_R3_MMIO_READ);
685
686	uint64_t u64Ticks;
687	if (pThis->u64HpetConfig & HPET_CFG_ENABLE)
688	u64Ticks = hpetGetTicks(pThis);
689	else
690	u64Ticks = pThis->u64HpetCounter;
691
692	DEVHPET_UNLOCK_BOTH(pThis);
693
694	/** @todo is it correct? */
695	u32Value = (idxReg == HPET_COUNTER) ? (uint32_t)u64Ticks : (uint32_t)(u64Ticks >> 32);
696	Log(("read HPET_COUNTER: %s part value %x (%#llx)\n",
697	(idxReg == HPET_COUNTER) ? "low" : "high", u32Value, u64Ticks));
698	break;
699	}
700
701	case HPET_STATUS:
702	DEVHPET_LOCK_RETURN(pThis, VINF_IOM_R3_MMIO_READ);
703	u32Value = (uint32_t)pThis->u64Isr;
704	DEVHPET_UNLOCK(pThis);
705	Log(("read HPET_STATUS: %#x\n", u32Value));
706	break;
707
708	default:
709	Log(("invalid HPET register read: %x\n", idxReg));
710	u32Value = 0;
711	break;
712	}
713
714	*pu32Value = u32Value;
715	return VINF_SUCCESS;
716	}
717
718
719	/**
720	* 32-bit write to a config register.
721	*
722	* @returns Strict VBox status code.
723	*
724	* @param pThis The HPET state.
725	* @param idxReg The register being written to.
726	* @param u32NewValue The value being written.
727	*
728	* @remarks The caller should not hold the device lock, unless it also holds
729	* the TM lock.
730	*/
731	static int hpetConfigRegWrite32(HpetState *pThis, uint32_t idxReg, uint32_t u32NewValue)
732	{
733	Assert(!PDMCritSectIsOwner(&pThis->csLock) \|\| TMTimerIsLockOwner(pThis->aTimers[0].CTX_SUFF(pTimer)));
734
735	int rc = VINF_SUCCESS;
736	switch (idxReg)
737	{
738	case HPET_ID:
739	case HPET_ID + 4:
740	{
741	Log(("write HPET_ID, useless\n"));
742	break;
743	}
744
745	case HPET_CFG:
746	{
747	DEVHPET_LOCK_BOTH_RETURN(pThis, VINF_IOM_R3_MMIO_WRITE);
748	uint32_t const iOldValue = (uint32_t)(pThis->u64HpetConfig);
749	Log(("write HPET_CFG: %x (old %x)\n", u32NewValue, iOldValue));
750
751	/*
752	* This check must be here, before actual update, as hpetLegacyMode
753	* may request retry in R3 - so we must keep state intact.
754	*/
755	if ( ((iOldValue ^ u32NewValue) & HPET_CFG_LEGACY)
756	&& pThis->pHpetHlpR3 != NIL_RTR3PTR)
757	{
758	#ifdef IN_RING3
759	rc = pThis->pHpetHlpR3->pfnSetLegacyMode(pThis->pDevInsR3, RT_BOOL(u32NewValue & HPET_CFG_LEGACY));
760	if (rc != VINF_SUCCESS)
761	#else
762	rc = VINF_IOM_R3_MMIO_WRITE;
763	#endif
764	{
765	DEVHPET_UNLOCK_BOTH(pThis);
766	break;
767	}
768	}
769
770	pThis->u64HpetConfig = hpetUpdateMasked(u32NewValue, iOldValue, HPET_CFG_WRITE_MASK);
771
772	uint32_t const cTimers = HPET_CAP_GET_TIMERS(pThis->u32Capabilities);
773	if (hpetBitJustSet(iOldValue, u32NewValue, HPET_CFG_ENABLE))
774	{
775	/** @todo Only get the time stamp once when reprogramming? */
776	/* Enable main counter and interrupt generation. */
777	pThis->u64HpetOffset = hpetTicksToNs(pThis, pThis->u64HpetCounter)
778	- TMTimerGet(pThis->aTimers[0].CTX_SUFF(pTimer));
779	for (uint32_t i = 0; i < cTimers; i++)
780	if (pThis->aTimers[i].u64Cmp != hpetInvalidValue(&pThis->aTimers[i]))
781	hpetProgramTimer(&pThis->aTimers[i]);
782	}
783	else if (hpetBitJustCleared(iOldValue, u32NewValue, HPET_CFG_ENABLE))
784	{
785	/* Halt main counter and disable interrupt generation. */
786	pThis->u64HpetCounter = hpetGetTicks(pThis);
787	for (uint32_t i = 0; i < cTimers; i++)
788	TMTimerStop(pThis->aTimers[i].CTX_SUFF(pTimer));
789	}
790
791	DEVHPET_UNLOCK_BOTH(pThis);
792	break;
793	}
794
795	case HPET_CFG + 4:
796	{
797	DEVHPET_LOCK_RETURN(pThis, VINF_IOM_R3_MMIO_WRITE);
798	pThis->u64HpetConfig = hpetUpdateMasked((uint64_t)u32NewValue << 32,
799	pThis->u64HpetConfig,
800	UINT64_C(0xffffffff00000000));
801	Log(("write HPET_CFG + 4: %x -> %#llx\n", u32NewValue, pThis->u64HpetConfig));
802	DEVHPET_UNLOCK(pThis);
803	break;
804	}
805
806	case HPET_STATUS:
807	{
808	DEVHPET_LOCK_RETURN(pThis, VINF_IOM_R3_MMIO_WRITE);
809	/* Clear ISR for all set bits in u32NewValue, see p. 14 of the HPET spec. */
810	pThis->u64Isr &= ~((uint64_t)u32NewValue);
811	Log(("write HPET_STATUS: %x -> ISR=%#llx\n", u32NewValue, pThis->u64Isr));
812	DEVHPET_UNLOCK(pThis);
813	break;
814	}
815
816	case HPET_STATUS + 4:
817	{
818	Log(("write HPET_STATUS + 4: %x\n", u32NewValue));
819	if (u32NewValue != 0)
820	{
821	static unsigned s_cOccurrences = 0;
822	if (s_cOccurrences++ < 10)
823	LogRel(("Writing HPET_STATUS + 4 with non-zero, ignored\n"));
824	}
825	break;
826	}
827
828	case HPET_COUNTER:
829	{
830	DEVHPET_LOCK_RETURN(pThis, VINF_IOM_R3_MMIO_WRITE);
831	pThis->u64HpetCounter = RT_MAKE_U64(u32NewValue, pThis->u64HpetCounter);
832	Log(("write HPET_COUNTER: %#x -> %llx\n", u32NewValue, pThis->u64HpetCounter));
833	DEVHPET_UNLOCK(pThis);
834	break;
835	}
836
837	case HPET_COUNTER + 4:
838	{
839	DEVHPET_LOCK_RETURN(pThis, VINF_IOM_R3_MMIO_WRITE);
840	pThis->u64HpetCounter = RT_MAKE_U64(pThis->u64HpetCounter, u32NewValue);
841	Log(("write HPET_COUNTER + 4: %#x -> %llx\n", u32NewValue, pThis->u64HpetCounter));
842	DEVHPET_UNLOCK(pThis);
843	break;
844	}
845
846	default:
847	{
848	static unsigned s_cOccurences = 0;
849	if (s_cOccurences++ < 10)
850	LogRel(("invalid HPET config write: %x\n", idxReg));
851	break;
852	}
853	}
854
855	return rc;
856	}
857
858
859	/* -=-=-=-=-=- MMIO callbacks -=-=-=-=-=- */
860
861
862	/**
863	* @callback_method_impl{FNIOMMMIOREAD}
864	*/
865	PDMBOTHCBDECL(int) hpetMMIORead(PPDMDEVINS pDevIns, void pvUser, RTGCPHYS GCPhysAddr, void pv, unsigned cb)
866	{
867	HpetState pThis = PDMINS_2_DATA(pDevIns, HpetState);
868	uint32_t const idxReg = (uint32_t)(GCPhysAddr - HPET_BASE);
869	NOREF(pvUser);
870
871	LogFlow(("hpetMMIORead (%d): %llx (%x)\n", cb, (uint64_t)GCPhysAddr, idxReg));
872
873	int rc = VINF_SUCCESS;
874	switch (cb)
875	{
876	case 4:
877	if (idxReg >= 0x100 && idxReg < 0x400)
878	{
879	DEVHPET_LOCK_RETURN(pThis, VINF_IOM_R3_MMIO_READ);
880	rc = hpetTimerRegRead32(pThis,
881	(idxReg - 0x100) / 0x20,
882	(idxReg - 0x100) % 0x20,
883	(uint32_t *)pv);
884	DEVHPET_UNLOCK(pThis);
885	}
886	else
887	rc = hpetConfigRegRead32(pThis, idxReg, (uint32_t *)pv);
888	break;
889
890	case 8:
891	{
892	/* Unaligned accesses not allowed */
893	if (RT_UNLIKELY(idxReg % 8 != 0))
894	{
895	rc = PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "idxReg=%#x cb=8\n", idxReg);
896	break;
897	}
898
899	/* Split the access except for timing sensitive registers. The
900	others assume the protection of the lock. */
901	PRTUINT64U pValue = (PRTUINT64U)pv;
902	if (idxReg == HPET_COUNTER)
903	{
904	/* When reading HPET counter we must read it in a single read,
905	to avoid unexpected time jumps on 32-bit overflow. */
906	DEVHPET_LOCK_BOTH_RETURN(pThis, VINF_IOM_R3_MMIO_READ);
907	if (pThis->u64HpetConfig & HPET_CFG_ENABLE)
908	pValue->u = hpetGetTicks(pThis);
909	else
910	pValue->u = pThis->u64HpetCounter;
911	DEVHPET_UNLOCK_BOTH(pThis);
912	}
913	else
914	{
915	DEVHPET_LOCK_RETURN(pThis, VINF_IOM_R3_MMIO_READ);
916	if (idxReg >= 0x100 && idxReg < 0x400)
917	{
918	uint32_t iTimer = (idxReg - 0x100) / 0x20;
919	uint32_t iTimerReg = (idxReg - 0x100) % 0x20;
920	rc = hpetTimerRegRead32(pThis, iTimer, iTimerReg, &pValue->s.Lo);
921	if (rc == VINF_SUCCESS)
922	rc = hpetTimerRegRead32(pThis, iTimer, iTimerReg + 4, &pValue->s.Hi);
923	}
924	else
925	{
926	/* for most 8-byte accesses we just split them, happens under lock anyway. */
927	rc = hpetConfigRegRead32(pThis, idxReg, &pValue->s.Lo);
928	if (rc == VINF_SUCCESS)
929	rc = hpetConfigRegRead32(pThis, idxReg + 4, &pValue->s.Hi);
930	}
931	DEVHPET_UNLOCK(pThis);
932	}
933	break;
934	}
935
936	case 1:
937	case 2:
938	Log(("Narrow read: %d\n", cb));
939	rc = VINF_SUCCESS;
940	break;
941
942	default:
943	AssertReleaseMsgFailed(("cb=%d\n", cb)); /* for now we assume simple accesses. */
944	rc = VINF_SUCCESS;
945	}
946
947	return rc;
948	}
949
950
951	/**
952	* @callback_method_impl{FNIOMMMIOWRITE}
953	*/
954	PDMBOTHCBDECL(int) hpetMMIOWrite(PPDMDEVINS pDevIns, void pvUser, RTGCPHYS GCPhysAddr, void const pv, unsigned cb)
955	{
956	HpetState pThis = PDMINS_2_DATA(pDevIns, HpetState);
957	uint32_t idxReg = (uint32_t)(GCPhysAddr - HPET_BASE);
958	LogFlow(("hpetMMIOWrite: cb=%u reg=%03x (%RGp) val=%llx\n",
959	cb, idxReg, GCPhysAddr, cb == 4 ? (uint32_t )pv : cb == 8 ? (uint64_t )pv : 0xdeadbeef));
960	NOREF(pvUser);
961
962	int rc;
963	switch (cb)
964	{
965	case 4:
966	if (idxReg >= 0x100 && idxReg < 0x400)
967	rc = hpetTimerRegWrite32(pThis,
968	(idxReg - 0x100) / 0x20,
969	(idxReg - 0x100) % 0x20,
970	(uint32_t const )pv);
971	else
972	rc = hpetConfigRegWrite32(pThis, idxReg, (uint32_t const )pv);
973	break;
974
975	case 8:
976	{
977	/* Unaligned accesses are not allowed. */
978	if (RT_UNLIKELY(idxReg % 8 != 0))
979	{
980	rc = PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "idxReg=%#x cb=8\n", idxReg);
981	break;
982	}
983
984	/* Split the access and rely on the locking to prevent trouble. */
985	DEVHPET_LOCK_BOTH_RETURN(pThis, VINF_IOM_R3_MMIO_WRITE);
986	RTUINT64U uValue;
987	uValue.u = (uint64_t const )pv;
988	if (idxReg >= 0x100 && idxReg < 0x400)
989	{
990	uint32_t iTimer = (idxReg - 0x100) / 0x20;
991	uint32_t iTimerReg = (idxReg - 0x100) % 0x20;
992	/** @todo Consider handling iTimerReg == HPET_TN_CMP specially here */
993	rc = hpetTimerRegWrite32(pThis, iTimer, iTimerReg, uValue.s.Lo);
994	if (RT_LIKELY(rc == VINF_SUCCESS))
995	rc = hpetTimerRegWrite32(pThis, iTimer, iTimerReg + 4, uValue.s.Hi);
996	}
997	else
998	{
999	rc = hpetConfigRegWrite32(pThis, idxReg, uValue.s.Lo);
1000	if (RT_LIKELY(rc == VINF_SUCCESS))
1001	rc = hpetConfigRegWrite32(pThis, idxReg + 4, uValue.s.Hi);
1002	}
1003	DEVHPET_UNLOCK_BOTH(pThis);
1004	break;
1005	}
1006
1007	case 1:
1008	case 2:
1009	Log(("Narrow write: %d\n", cb));
1010	rc = VINF_SUCCESS;
1011	break;
1012
1013	default:
1014	AssertReleaseMsgFailed(("cb=%d\n", cb)); /* for now we assume simple accesses. */
1015	rc = VERR_INTERNAL_ERROR;
1016	break;
1017	}
1018
1019	return rc;
1020	}
1021
1022	#ifdef IN_RING3
1023
1024	/* -=-=-=-=-=- Timer Callback Processing -=-=-=-=-=- */
1025
1026	/**
1027	* Gets the IRQ of an HPET timer.
1028	*
1029	* @returns IRQ number.
1030	* @param pHpetTimer The HPET timer.
1031	*/
1032	static uint32_t hpetTimerCbGetIrq(struct HpetTimer const *pHpetTimer)
1033	{
1034	/*
1035	* Per spec, in legacy mode HPET timers wired as:
1036	* timer 0: IRQ0 for PIC and IRQ2 for APIC
1037	* timer 1: IRQ8 for both PIC and APIC
1038	*
1039	* ISA IRQ delivery logic will take care of correct delivery
1040	* to the different ICs.
1041	*/
1042	if ( (pHpetTimer->idxTimer <= 1)
1043	&& (pHpetTimer->CTX_SUFF(pHpet)->u64HpetConfig & HPET_CFG_LEGACY))
1044	return (pHpetTimer->idxTimer == 0) ? 0 : 8;
1045
1046	return (pHpetTimer->u64Config & HPET_TN_INT_ROUTE_MASK) >> HPET_TN_INT_ROUTE_SHIFT;
1047	}
1048
1049
1050	/**
1051	* Used by hpetTimerCb to update the IRQ status.
1052	*
1053	* @param pThis The HPET device state.
1054	* @param pHpetTimer The HPET timer.
1055	*/
1056	static void hpetTimerCbUpdateIrq(HpetState pThis, struct HpetTimer pHpetTimer)
1057	{
1058	/** @todo: is it correct? */
1059	if ( !!(pHpetTimer->u64Config & HPET_TN_ENABLE)
1060	&& !!(pThis->u64HpetConfig & HPET_CFG_ENABLE))
1061	{
1062	uint32_t irq = hpetTimerCbGetIrq(pHpetTimer);
1063	Log4(("HPET: raising IRQ %d\n", irq));
1064
1065	/* ISR bits are only set in level-triggered mode. */
1066	if ((pHpetTimer->u64Config & HPET_TN_INT_TYPE) == HPET_TIMER_TYPE_LEVEL)
1067	pThis->u64Isr \|= (uint64_t)(1 << pHpetTimer->idxTimer);
1068
1069	/* We trigger flip/flop in edge-triggered mode and do nothing in
1070	level-triggered mode yet. */
1071	if ((pHpetTimer->u64Config & HPET_TN_INT_TYPE) == HPET_TIMER_TYPE_EDGE)
1072	pThis->pHpetHlpR3->pfnSetIrq(pThis->CTX_SUFF(pDevIns), irq, PDM_IRQ_LEVEL_FLIP_FLOP);
1073	else
1074	AssertFailed();
1075	/** @todo: implement IRQs in level-triggered mode */
1076	}
1077	}
1078
1079	/**
1080	* Device timer callback function.
1081	*
1082	* @param pDevIns Device instance of the device which registered the timer.
1083	* @param pTimer The timer handle.
1084	* @param pvUser Pointer to the HPET timer state.
1085	*/
1086	static DECLCALLBACK(void) hpetTimerCb(PPDMDEVINS pDevIns, PTMTIMER pTimer, void *pvUser)
1087	{
1088	HpetState pThis = PDMINS_2_DATA(pDevIns, HpetState );
1089	HpetTimer pHpetTimer = (HpetTimer )pvUser;
1090	uint64_t u64Period = pHpetTimer->u64Period;
1091	uint64_t u64CurTick = hpetGetTicks(pThis);
1092	uint64_t u64Diff;
1093
1094	if ((pHpetTimer->u64Config & HPET_TN_PERIODIC) && (u64Period != 0))
1095	{
1096	hpetAdjustComparator(pHpetTimer, u64CurTick);
1097
1098	u64Diff = hpetComputeDiff(pHpetTimer, u64CurTick);
1099
1100	Log4(("HPET: periodical: next in %llu\n", hpetTicksToNs(pThis, u64Diff)));
1101	TMTimerSetNano(pTimer, hpetTicksToNs(pThis, u64Diff));
1102	}
1103	else if ( hpet32bitTimer(pHpetTimer)
1104	&& !(pHpetTimer->u64Config & HPET_TN_PERIODIC))
1105	{
1106	if (pHpetTimer->u8Wrap)
1107	{
1108	u64Diff = hpetComputeDiff(pHpetTimer, u64CurTick);
1109	TMTimerSetNano(pTimer, hpetTicksToNs(pThis, u64Diff));
1110	pHpetTimer->u8Wrap = 0;
1111	}
1112	}
1113
1114	/* Should it really be under lock, does it really matter? */
1115	hpetTimerCbUpdateIrq(pThis, pHpetTimer);
1116	}
1117
1118
1119	/* -=-=-=-=-=- DBGF Info Handlers -=-=-=-=-=- */
1120
1121
1122	/**
1123	* @callback_method_impl{FNDBGFHANDLERDEV}
1124	*/
1125	static DECLCALLBACK(void) hpetInfo(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
1126	{
1127	HpetState pThis = PDMINS_2_DATA(pDevIns, HpetState );
1128	NOREF(pszArgs);
1129
1130	pHlp->pfnPrintf(pHlp,
1131	"HPET status:\n"
1132	" config=%016RX64 isr=%016RX64\n"
1133	" offset=%016RX64 counter=%016RX64 frequency=%08x\n"
1134	" legacy-mode=%s timer-count=%u\n",
1135	pThis->u64HpetConfig, pThis->u64Isr,
1136	pThis->u64HpetOffset, pThis->u64HpetCounter, pThis->u32Period,
1137	!!(pThis->u64HpetConfig & HPET_CFG_LEGACY) ? "on " : "off",
1138	HPET_CAP_GET_TIMERS(pThis->u32Capabilities));
1139	pHlp->pfnPrintf(pHlp,
1140	"Timers:\n");
1141	for (unsigned i = 0; i < RT_ELEMENTS(pThis->aTimers); i++)
1142	{
1143	pHlp->pfnPrintf(pHlp, " %d: comparator=%016RX64 period(hidden)=%016RX64 cfg=%016RX64\n",
1144	pThis->aTimers[i].idxTimer,
1145	pThis->aTimers[i].u64Cmp,
1146	pThis->aTimers[i].u64Period,
1147	pThis->aTimers[i].u64Config);
1148	}
1149	}
1150
1151
1152	/* -=-=-=-=-=- Saved State -=-=-=-=-=- */
1153
1154
1155	/**
1156	* @callback_method_impl{FNSSMDEVLIVEEXEC}
1157	*/
1158	static DECLCALLBACK(int) hpetLiveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t uPass)
1159	{
1160	HpetState pThis = PDMINS_2_DATA(pDevIns, HpetState );
1161	NOREF(uPass);
1162
1163	SSMR3PutU8(pSSM, HPET_CAP_GET_TIMERS(pThis->u32Capabilities));
1164
1165	return VINF_SSM_DONT_CALL_AGAIN;
1166	}
1167
1168
1169	/**
1170	* @callback_method_impl{FNSSMDEVSAVEEXEC}
1171	*/
1172	static DECLCALLBACK(int) hpetSaveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
1173	{
1174	HpetState pThis = PDMINS_2_DATA(pDevIns, HpetState );
1175
1176	/*
1177	* The config.
1178	*/
1179	hpetLiveExec(pDevIns, pSSM, SSM_PASS_FINAL);
1180
1181	/*
1182	* The state.
1183	*/
1184	uint32_t const cTimers = HPET_CAP_GET_TIMERS(pThis->u32Capabilities);
1185	for (uint32_t iTimer = 0; iTimer < cTimers; iTimer++)
1186	{
1187	HpetTimer *pHpetTimer = &pThis->aTimers[iTimer];
1188	TMR3TimerSave(pHpetTimer->pTimerR3, pSSM);
1189	SSMR3PutU8(pSSM, pHpetTimer->u8Wrap);
1190	SSMR3PutU64(pSSM, pHpetTimer->u64Config);
1191	SSMR3PutU64(pSSM, pHpetTimer->u64Cmp);
1192	SSMR3PutU64(pSSM, pHpetTimer->u64Fsb);
1193	SSMR3PutU64(pSSM, pHpetTimer->u64Period);
1194	}
1195
1196	SSMR3PutU64(pSSM, pThis->u64HpetOffset);
1197	uint64_t u64CapPer = RT_MAKE_U64(pThis->u32Capabilities, pThis->u32Period);
1198	SSMR3PutU64(pSSM, u64CapPer);
1199	SSMR3PutU64(pSSM, pThis->u64HpetConfig);
1200	SSMR3PutU64(pSSM, pThis->u64Isr);
1201	return SSMR3PutU64(pSSM, pThis->u64HpetCounter);
1202	}
1203
1204
1205	/**
1206	* @callback_method_impl{FNSSMDEVLOADEXEC}
1207	*/
1208	static DECLCALLBACK(int) hpetLoadExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
1209	{
1210	HpetState pThis = PDMINS_2_DATA(pDevIns, HpetState );
1211
1212	/*
1213	* Version checks.
1214	*/
1215	if (uVersion == HPET_SAVED_STATE_VERSION_EMPTY)
1216	return VINF_SUCCESS;
1217	if (uVersion != HPET_SAVED_STATE_VERSION)
1218	return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
1219
1220	/*
1221	* The config.
1222	*/
1223	uint8_t cTimers;
1224	int rc = SSMR3GetU8(pSSM, &cTimers);
1225	AssertRCReturn(rc, rc);
1226	if (cTimers > RT_ELEMENTS(pThis->aTimers))
1227	return SSMR3SetCfgError(pSSM, RT_SRC_POS, N_("Config mismatch - too many timers: saved=%#x config=%#x"),
1228	cTimers, RT_ELEMENTS(pThis->aTimers));
1229
1230	if (uPass != SSM_PASS_FINAL)
1231	return VINF_SUCCESS;
1232
1233	/*
1234	* The state.
1235	*/
1236	for (uint32_t iTimer = 0; iTimer < cTimers; iTimer++)
1237	{
1238	HpetTimer *pHpetTimer = &pThis->aTimers[iTimer];
1239	TMR3TimerLoad(pHpetTimer->pTimerR3, pSSM);
1240	SSMR3GetU8(pSSM, &pHpetTimer->u8Wrap);
1241	SSMR3GetU64(pSSM, &pHpetTimer->u64Config);
1242	SSMR3GetU64(pSSM, &pHpetTimer->u64Cmp);
1243	SSMR3GetU64(pSSM, &pHpetTimer->u64Fsb);
1244	SSMR3GetU64(pSSM, &pHpetTimer->u64Period);
1245	}
1246
1247	SSMR3GetU64(pSSM, &pThis->u64HpetOffset);
1248	uint64_t u64CapPer;
1249	SSMR3GetU64(pSSM, &u64CapPer);
1250	SSMR3GetU64(pSSM, &pThis->u64HpetConfig);
1251	SSMR3GetU64(pSSM, &pThis->u64Isr);
1252	rc = SSMR3GetU64(pSSM, &pThis->u64HpetCounter);
1253	if (RT_FAILURE(rc))
1254	return rc;
1255	if (HPET_CAP_GET_TIMERS(RT_LO_U32(u64CapPer)) != cTimers)
1256	return SSMR3SetCfgError(pSSM, RT_SRC_POS, N_("Capabilities does not match timer count: cTimers=%#x caps=%#x"),
1257	cTimers, (unsigned)HPET_CAP_GET_TIMERS(u64CapPer));
1258	pThis->u32Capabilities = RT_LO_U32(u64CapPer);
1259	pThis->u32Period = RT_HI_U32(u64CapPer);
1260
1261	/*
1262	* Set the timer frequency hints.
1263	*/
1264	PDMCritSectEnter(&pThis->csLock, VERR_IGNORED);
1265	for (uint32_t iTimer = 0; iTimer < cTimers; iTimer++)
1266	{
1267	HpetTimer *pHpetTimer = &pThis->aTimers[iTimer];
1268	if (TMTimerIsActive(pHpetTimer->CTX_SUFF(pTimer)))
1269	hpetTimerSetFrequencyHint(pThis, pHpetTimer);
1270	}
1271	PDMCritSectLeave(&pThis->csLock);
1272	return VINF_SUCCESS;
1273	}
1274
1275
1276	/* -=-=-=-=-=- PDMDEVREG -=-=-=-=-=- */
1277
1278
1279	/**
1280	* @interface_method_impl{PDMDEVREG,pfnRelocate}
1281	*/
1282	static DECLCALLBACK(void) hpetRelocate(PPDMDEVINS pDevIns, RTGCINTPTR offDelta)
1283	{
1284	HpetState pThis = PDMINS_2_DATA(pDevIns, HpetState );
1285	LogFlow(("hpetRelocate:\n"));
1286	NOREF(offDelta);
1287
1288	pThis->pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
1289	pThis->pHpetHlpRC = pThis->pHpetHlpR3->pfnGetRCHelpers(pDevIns);
1290
1291	for (unsigned i = 0; i < RT_ELEMENTS(pThis->aTimers); i++)
1292	{
1293	HpetTimer *pTm = &pThis->aTimers[i];
1294	if (pTm->pTimerR3)
1295	pTm->pTimerRC = TMTimerRCPtr(pTm->pTimerR3);
1296	pTm->pHpetRC = PDMINS_2_DATA_RCPTR(pDevIns);
1297	}
1298	}
1299
1300
1301	/**
1302	* @interface_method_impl{PDMDEVREG,pfnReset}
1303	*/
1304	static DECLCALLBACK(void) hpetReset(PPDMDEVINS pDevIns)
1305	{
1306	HpetState pThis = PDMINS_2_DATA(pDevIns, HpetState );
1307	LogFlow(("hpetReset:\n"));
1308
1309	/*
1310	* The timers first.
1311	*/
1312	TMTimerLock(pThis->aTimers[0].pTimerR3, VERR_IGNORED);
1313	for (unsigned i = 0; i < RT_ELEMENTS(pThis->aTimers); i++)
1314	{
1315	HpetTimer *pHpetTimer = &pThis->aTimers[i];
1316	Assert(pHpetTimer->idxTimer == i);
1317	TMTimerStop(pHpetTimer->pTimerR3);
1318
1319	/* capable of periodic operations and 64-bits */
1320	if (pThis->fIch9)
1321	pHpetTimer->u64Config = (i == 0)
1322	? (HPET_TN_PERIODIC_CAP \| HPET_TN_SIZE_CAP)
1323	: 0;
1324	else
1325	pHpetTimer->u64Config = HPET_TN_PERIODIC_CAP \| HPET_TN_SIZE_CAP;
1326
1327	/* We can do all IRQs */
1328	uint32_t u32RoutingCap = 0xffffffff;
1329	pHpetTimer->u64Config \|= ((uint64_t)u32RoutingCap) << 32;
1330	pHpetTimer->u64Period = 0;
1331	pHpetTimer->u8Wrap = 0;
1332	pHpetTimer->u64Cmp = hpetInvalidValue(pHpetTimer);
1333	}
1334	TMTimerUnlock(pThis->aTimers[0].pTimerR3);
1335
1336	/*
1337	* The HPET state.
1338	*/
1339	pThis->u64HpetConfig = 0;
1340	pThis->u64HpetCounter = 0;
1341	pThis->u64HpetOffset = 0;
1342
1343	/* 64-bit main counter; 3 timers supported; LegacyReplacementRoute. */
1344	pThis->u32Capabilities = (1 << 15) /* LEG_RT_CAP - LegacyReplacementRoute capable. */
1345	\| (1 << 13) /* COUNTER_SIZE_CAP - Main counter is 64-bit capable. */
1346	\| 1; /* REV_ID - Revision, must not be 0 */
1347	if (pThis->fIch9) /* NUM_TIM_CAP - Number of timers -1. */
1348	pThis->u32Capabilities \|= (HPET_NUM_TIMERS_ICH9 - 1) << 8;
1349	else
1350	pThis->u32Capabilities \|= (HPET_NUM_TIMERS_PIIX - 1) << 8;
1351	pThis->u32Capabilities \|= UINT32_C(0x80860000); /* VENDOR */
1352	AssertCompile(HPET_NUM_TIMERS_ICH9 <= RT_ELEMENTS(pThis->aTimers));
1353	AssertCompile(HPET_NUM_TIMERS_PIIX <= RT_ELEMENTS(pThis->aTimers));
1354
1355	pThis->u32Period = pThis->fIch9 ? HPET_CLK_PERIOD_ICH9 : HPET_CLK_PERIOD_PIIX;
1356
1357	/*
1358	* Notify the PIT/RTC devices.
1359	*/
1360	if (pThis->pHpetHlpR3)
1361	pThis->pHpetHlpR3->pfnSetLegacyMode(pDevIns, false /fActive/);
1362	}
1363
1364
1365	/**
1366	* @interface_method_impl{PDMDEVREG,pfnConstruct}
1367	*/
1368	static DECLCALLBACK(int) hpetConstruct(PPDMDEVINS pDevIns, int iInstance, PCFGMNODE pCfg)
1369	{
1370	PDMDEV_CHECK_VERSIONS_RETURN(pDevIns);
1371	HpetState pThis = PDMINS_2_DATA(pDevIns, HpetState );
1372
1373	/* Only one HPET device now, as we use fixed MMIO region. */
1374	Assert(iInstance == 0);
1375
1376	/*
1377	* Validate and read the configuration.
1378	*/
1379	PDMDEV_VALIDATE_CONFIG_RETURN(pDevIns, "GCEnabled\|R0Enabled\|ICH9", "");
1380
1381	bool fRCEnabled;
1382	int rc = CFGMR3QueryBoolDef(pCfg, "GCEnabled", &fRCEnabled, true);
1383	if (RT_FAILURE(rc))
1384	return PDMDEV_SET_ERROR(pDevIns, rc,
1385	N_("Configuration error: Querying \"GCEnabled\" as a bool failed"));
1386
1387	bool fR0Enabled;
1388	rc = CFGMR3QueryBoolDef(pCfg, "R0Enabled", &fR0Enabled, true);
1389	if (RT_FAILURE(rc))
1390	return PDMDEV_SET_ERROR(pDevIns, rc,
1391	N_("Configuration error: failed to read R0Enabled as boolean"));
1392
1393	rc = CFGMR3QueryBoolDef(pCfg, "ICH9", &pThis->fIch9, false);
1394	if (RT_FAILURE(rc))
1395	return PDMDEV_SET_ERROR(pDevIns, rc,
1396	N_("Configuration error: failed to read ICH9 as boolean"));
1397
1398	/*
1399	* Initialize the device state.
1400	*/
1401	pThis->pDevInsR3 = pDevIns;
1402	pThis->pDevInsR0 = PDMDEVINS_2_R0PTR(pDevIns);
1403	pThis->pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
1404
1405	rc = PDMDevHlpCritSectInit(pDevIns, &pThis->csLock, RT_SRC_POS, "HPET#%u", pDevIns->iInstance);
1406	AssertRCReturn(rc, rc);
1407
1408	/* No automatic locking. */
1409	rc = PDMDevHlpSetDeviceCritSect(pDevIns, PDMDevHlpCritSectGetNop(pDevIns));
1410	AssertRCReturn(rc, rc);
1411
1412	/* Init the HPET timers (init all regardless of how many we expose). */
1413	for (unsigned i = 0; i < RT_ELEMENTS(pThis->aTimers); i++)
1414	{
1415	HpetTimer *pHpetTimer = &pThis->aTimers[i];
1416
1417	pHpetTimer->idxTimer = i;
1418	pHpetTimer->pHpetR3 = pThis;
1419	pHpetTimer->pHpetR0 = PDMINS_2_DATA_R0PTR(pDevIns);
1420	pHpetTimer->pHpetRC = PDMINS_2_DATA_RCPTR(pDevIns);
1421
1422	rc = PDMDevHlpTMTimerCreate(pDevIns, TMCLOCK_VIRTUAL_SYNC, hpetTimerCb, pHpetTimer,
1423	TMTIMER_FLAGS_NO_CRIT_SECT, "HPET Timer",
1424	&pThis->aTimers[i].pTimerR3);
1425	AssertRCReturn(rc, rc);
1426	pThis->aTimers[i].pTimerRC = TMTimerRCPtr(pThis->aTimers[i].pTimerR3);
1427	pThis->aTimers[i].pTimerR0 = TMTimerR0Ptr(pThis->aTimers[i].pTimerR3);
1428	rc = TMR3TimerSetCritSect(pThis->aTimers[i].pTimerR3, &pThis->csLock);
1429	AssertRCReturn(rc, rc);
1430	}
1431
1432	/* This must be done prior to registering the HPET, right? */
1433	hpetReset(pDevIns);
1434
1435	/*
1436	* Register the HPET and get helpers.
1437	*/
1438	PDMHPETREG HpetReg;
1439	HpetReg.u32Version = PDM_HPETREG_VERSION;
1440	rc = PDMDevHlpHPETRegister(pDevIns, &HpetReg, &pThis->pHpetHlpR3);
1441	AssertRCReturn(rc, rc);
1442
1443	/*
1444	* Register the MMIO range, PDM API requests page aligned
1445	* addresses and sizes.
1446	*/
1447	rc = PDMDevHlpMMIORegister(pDevIns, HPET_BASE, 0x1000, pThis,
1448	IOMMMIO_FLAGS_READ_PASSTHRU \| IOMMMIO_FLAGS_WRITE_PASSTHRU,
1449	hpetMMIOWrite, hpetMMIORead, "HPET Memory");
1450	AssertRCReturn(rc, rc);
1451
1452	if (fRCEnabled)
1453	{
1454	rc = PDMDevHlpMMIORegisterRC(pDevIns, HPET_BASE, 0x1000, NIL_RTRCPTR /pvUser/, "hpetMMIOWrite", "hpetMMIORead");
1455	AssertRCReturn(rc, rc);
1456
1457	pThis->pHpetHlpRC = pThis->pHpetHlpR3->pfnGetRCHelpers(pDevIns);
1458	AssertReturn(pThis->pHpetHlpRC != NIL_RTRCPTR, VERR_INTERNAL_ERROR);
1459	}
1460
1461	if (fR0Enabled)
1462	{
1463	rc = PDMDevHlpMMIORegisterR0(pDevIns, HPET_BASE, 0x1000, NIL_RTR0PTR /pvUser/,
1464	"hpetMMIOWrite", "hpetMMIORead");
1465	AssertRCReturn(rc, rc);
1466
1467	pThis->pHpetHlpR0 = pThis->pHpetHlpR3->pfnGetR0Helpers(pDevIns);
1468	AssertReturn(pThis->pHpetHlpR0 != NIL_RTR0PTR, VERR_INTERNAL_ERROR);
1469	}
1470
1471	/* Register SSM callbacks */
1472	rc = PDMDevHlpSSMRegister3(pDevIns, HPET_SAVED_STATE_VERSION, sizeof(*pThis), hpetLiveExec, hpetSaveExec, hpetLoadExec);
1473	AssertRCReturn(rc, rc);
1474
1475	/* Register an info callback. */
1476	PDMDevHlpDBGFInfoRegister(pDevIns, "hpet", "Display HPET status. (no arguments)", hpetInfo);
1477
1478	return VINF_SUCCESS;
1479	}
1480
1481
1482	/**
1483	* The device registration structure.
1484	*/
1485	const PDMDEVREG g_DeviceHPET =
1486	{
1487	/* u32Version */
1488	PDM_DEVREG_VERSION,
1489	/* szName */
1490	"hpet",
1491	/* szRCMod */
1492	"VBoxDDGC.gc",
1493	/* szR0Mod */
1494	"VBoxDDR0.r0",
1495	/* pszDescription */
1496	" High Precision Event Timer (HPET) Device",
1497	/* fFlags */
1498	PDM_DEVREG_FLAGS_HOST_BITS_DEFAULT \| PDM_DEVREG_FLAGS_GUEST_BITS_32_64 \| PDM_DEVREG_FLAGS_PAE36 \| PDM_DEVREG_FLAGS_RC \| PDM_DEVREG_FLAGS_R0,
1499	/* fClass */
1500	PDM_DEVREG_CLASS_PIT,
1501	/* cMaxInstances */
1502	1,
1503	/* cbInstance */
1504	sizeof(HpetState),
1505	/* pfnConstruct */
1506	hpetConstruct,
1507	/* pfnDestruct */
1508	NULL,
1509	/* pfnRelocate */
1510	hpetRelocate,
1511	/* pfnIOCtl */
1512	NULL,
1513	/* pfnPowerOn */
1514	NULL,
1515	/* pfnReset */
1516	hpetReset,
1517	/* pfnSuspend */
1518	NULL,
1519	/* pfnResume */
1520	NULL,
1521	/* pfnAttach */
1522	NULL,
1523	/* pfnDetach */
1524	NULL,
1525	/* pfnQueryInterface. */
1526	NULL,
1527	/* pfnInitComplete */
1528	NULL,
1529	/* pfnPowerOff */
1530	NULL,
1531	/* pfnSoftReset */
1532	NULL,
1533	/* u32VersionEnd */
1534	PDM_DEVREG_VERSION
1535	};
1536
1537	#endif /* IN_RING3 */
1538	#endif /* !VBOX_DEVICE_STRUCT_TESTCASE */
1539

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source: vbox/trunk/src/VBox/Devices/PC/DevHPET.cpp@ 42202

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