VirtualBox

source: vbox/trunk/src/VBox/Devices/PC/DevHPET.cpp@ 40280

Last change on this file since 40280 was 40280, checked in by vboxsync, 13 years ago

Corrected a bunch of HC and GC uses in status codes.
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File size: 49.8 KB
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1/* $Id: DevHPET.cpp 40280 2012-02-28 19:47:00Z vboxsync $ */
2/** @file
3 * HPET virtual device - high precision event timer emulation
4 */
5
6/*
7 * Copyright (C) 2009-2011 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18/*******************************************************************************
19* Header Files *
20*******************************************************************************/
21#define LOG_GROUP LOG_GROUP_DEV_HPET
22#include <VBox/vmm/pdmdev.h>
23#include <VBox/vmm/stam.h>
24#include <VBox/log.h>
25#include <iprt/assert.h>
26#include <iprt/asm-math.h>
27#include <iprt/string.h>
28
29#include "VBoxDD.h"
30
31
32/*******************************************************************************
33* Defined Constants And Macros *
34*******************************************************************************/
35/*
36 * Current limitations:
37 * - not entirely correct time of interrupt, i.e. never
38 * schedule interrupt earlier than in 1ms
39 * - statistics not implemented
40 * - level-triggered mode not implemented
41 */
42
43/** Base address for MMIO. */
44#define HPET_BASE 0xfed00000
45
46/** The number of timers for PIIX4 / PIIX3. */
47#define HPET_NUM_TIMERS_PIIX 3
48/** The number of timers for ICH9. */
49#define HPET_NUM_TIMERS_ICH9 4
50
51/** HPET clock period for PIIX4 / PIIX3.
52 * 10000000 femtoseconds == 10ns.
53 */
54#define HPET_CLK_PERIOD_PIIX UINT32_C(10000000)
55
56/** HPET clock period for ICH9.
57 * 69841279 femtoseconds == 69.84 ns (1 / 14.31818MHz).
58 */
59#define HPET_CLK_PERIOD_ICH9 UINT32_C(69841279)
60
61/*
62 * Femptosecods in nanosecond
63 */
64#define FS_PER_NS 1000000
65
66/*
67 * Interrupt type
68 */
69#define HPET_TIMER_TYPE_LEVEL 1
70#define HPET_TIMER_TYPE_EDGE 0
71
72/* Delivery mode */
73/* Via APIC */
74#define HPET_TIMER_DELIVERY_APIC 0
75/* Via FSB */
76#define HPET_TIMER_DELIVERY_FSB 1
77
78#define HPET_TIMER_CAP_FSB_INT_DEL (1 << 15)
79#define HPET_TIMER_CAP_PER_INT (1 << 4)
80
81#define HPET_CFG_ENABLE 0x001 /* ENABLE_CNF */
82#define HPET_CFG_LEGACY 0x002 /* LEG_RT_CNF */
83
84#define HPET_ID 0x000
85#define HPET_PERIOD 0x004
86#define HPET_CFG 0x010
87#define HPET_STATUS 0x020
88#define HPET_COUNTER 0x0f0
89#define HPET_TN_CFG 0x000
90#define HPET_TN_CMP 0x008
91#define HPET_TN_ROUTE 0x010
92#define HPET_CFG_WRITE_MASK 0x3
93
94#define HPET_TN_INT_TYPE RT_BIT_64(1)
95#define HPET_TN_ENABLE RT_BIT_64(2)
96#define HPET_TN_PERIODIC RT_BIT_64(3)
97#define HPET_TN_PERIODIC_CAP RT_BIT_64(4)
98#define HPET_TN_SIZE_CAP RT_BIT_64(5)
99#define HPET_TN_SETVAL RT_BIT_64(6)
100#define HPET_TN_32BIT RT_BIT_64(8)
101#define HPET_TN_INT_ROUTE_MASK UINT64_C(0x3e00)
102#define HPET_TN_CFG_WRITE_MASK UINT64_C(0x3e46)
103#define HPET_TN_INT_ROUTE_SHIFT 9
104#define HPET_TN_INT_ROUTE_CAP_SHIFT 32
105#define HPET_TN_CFG_BITS_READONLY_OR_RESERVED 0xffff80b1U
106
107/** Extract the timer count from the capabilities.
108 * @todo Check if the mask is correct. */
109#define HPET_CAP_GET_TIMERS(a_u32) ( ((a_u32) >> 8) & 0xf )
110
111/** The version of the saved state. */
112#define HPET_SAVED_STATE_VERSION 2
113/** Empty saved state */
114#define HPET_SAVED_STATE_VERSION_EMPTY 1
115
116
117/**
118 * Acquires the HPET lock or returns.
119 */
120#define DEVHPET_LOCK_RETURN(a_pThis, a_rcBusy) \
121 do { \
122 int rcLock = PDMCritSectEnter(&(a_pThis)->csLock, (a_rcBusy)); \
123 if (rcLock != VINF_SUCCESS) \
124 return rcLock; \
125 } while (0)
126
127/**
128 * Releases the HPET lock.
129 */
130#define DEVHPET_UNLOCK(a_pThis) \
131 do { PDMCritSectLeave(&(a_pThis)->csLock); } while (0)
132
133
134/**
135 * Acquires the TM lock and HPET lock, returns on failure.
136 */
137#define DEVHPET_LOCK_BOTH_RETURN(a_pThis, a_rcBusy) \
138 do { \
139 int rcLock = TMTimerLock((a_pThis)->aTimers[0].CTX_SUFF(pTimer), (a_rcBusy)); \
140 if (rcLock != VINF_SUCCESS) \
141 return rcLock; \
142 rcLock = PDMCritSectEnter(&(a_pThis)->csLock, (a_rcBusy)); \
143 if (rcLock != VINF_SUCCESS) \
144 { \
145 TMTimerUnlock((a_pThis)->aTimers[0].CTX_SUFF(pTimer)); \
146 return rcLock; \
147 } \
148 } while (0)
149
150
151/**
152 * Releases the HPET lock and TM lock.
153 */
154#define DEVHPET_UNLOCK_BOTH(a_pThis) \
155 do { \
156 PDMCritSectLeave(&(a_pThis)->csLock); \
157 TMTimerUnlock((a_pThis)->aTimers[0].CTX_SUFF(pTimer)); \
158 } while (0)
159
160
161/*******************************************************************************
162* Structures and Typedefs *
163*******************************************************************************/
164struct HpetState;
165typedef struct HpetTimer
166{
167 /** The HPET timer - R3 Ptr. */
168 PTMTIMERR3 pTimerR3;
169 /** Pointer to the instance data - R3 Ptr. */
170 R3PTRTYPE(struct HpetState *) pHpetR3;
171
172 /** The HPET timer - R0 Ptr. */
173 PTMTIMERR0 pTimerR0;
174 /** Pointer to the instance data - R0 Ptr. */
175 R0PTRTYPE(struct HpetState *) pHpetR0;
176
177 /** The HPET timer - RC Ptr. */
178 PTMTIMERRC pTimerRC;
179 /** Pointer to the instance data - RC Ptr. */
180 RCPTRTYPE(struct HpetState *) pHpetRC;
181
182 /** Timer index. */
183 uint8_t idxTimer;
184 /** Wrap. */
185 uint8_t u8Wrap;
186 /** Alignment. */
187 uint32_t alignment0;
188
189 /** @name Memory-mapped, software visible timer registers.
190 * @{ */
191 /** Configuration/capabilities. */
192 uint64_t u64Config;
193 /** Comparator. */
194 uint64_t u64Cmp;
195 /** FSB route, not supported now. */
196 uint64_t u64Fsb;
197 /** @} */
198
199 /** @name Hidden register state.
200 * @{ */
201 /** Last value written to comparator. */
202 uint64_t u64Period;
203 /** @} */
204} HpetTimer;
205AssertCompileMemberAlignment(HpetTimer, u64Config, sizeof(uint64_t));
206
207typedef struct HpetState
208{
209 /** Pointer to the device instance. - R3 ptr. */
210 PPDMDEVINSR3 pDevInsR3;
211 /** The HPET helpers - R3 Ptr. */
212 PCPDMHPETHLPR3 pHpetHlpR3;
213
214 /** Pointer to the device instance. - R0 ptr. */
215 PPDMDEVINSR0 pDevInsR0;
216 /** The HPET helpers - R0 Ptr. */
217 PCPDMHPETHLPR0 pHpetHlpR0;
218
219 /** Pointer to the device instance. - RC ptr. */
220 PPDMDEVINSRC pDevInsRC;
221 /** The HPET helpers - RC Ptr. */
222 PCPDMHPETHLPRC pHpetHlpRC;
223
224 /** Timer structures. */
225 HpetTimer aTimers[RT_MAX(HPET_NUM_TIMERS_PIIX, HPET_NUM_TIMERS_ICH9)];
226
227 /** Offset realtive to the virtual sync clock. */
228 uint64_t u64HpetOffset;
229
230 /** @name Memory-mapped, software visible registers
231 * @{ */
232 /** Capabilities. */
233 uint32_t u32Capabilities;
234 /** HPET_PERIOD - . */
235 uint32_t u32Period;
236 /** Configuration. */
237 uint64_t u64HpetConfig;
238 /** Interrupt status register. */
239 uint64_t u64Isr;
240 /** Main counter. */
241 uint64_t u64HpetCounter;
242 /** @} */
243
244 /** Global device lock. */
245 PDMCRITSECT csLock;
246
247 /** If we emulate ICH9 HPET (different frequency & timer count). */
248 bool fIch9;
249 uint8_t padding0[7];
250} HpetState;
251
252
253#ifndef VBOX_DEVICE_STRUCT_TESTCASE
254
255
256DECLINLINE(bool) hpet32bitTimer(HpetTimer *pHpetTimer)
257{
258 uint64_t u64Cfg = pHpetTimer->u64Config;
259
260 return ((u64Cfg & HPET_TN_SIZE_CAP) == 0) || ((u64Cfg & HPET_TN_32BIT) != 0);
261}
262
263DECLINLINE(uint64_t) hpetInvalidValue(HpetTimer *pHpetTimer)
264{
265 return hpet32bitTimer(pHpetTimer) ? UINT32_MAX : UINT64_MAX;
266}
267
268DECLINLINE(uint32_t) hpetTimeAfter32(uint64_t a, uint64_t b)
269{
270 return ((int32_t)(b) - (int32_t)(a) <= 0);
271}
272
273DECLINLINE(uint32_t) hpetTimeAfter64(uint64_t a, uint64_t b)
274{
275 return ((int64_t)(b) - (int64_t)(a) <= 0);
276}
277
278DECLINLINE(uint64_t) hpetTicksToNs(HpetState *pThis, uint64_t value)
279{
280 return ASMMultU64ByU32DivByU32(value, pThis->u32Period, FS_PER_NS);
281}
282
283DECLINLINE(uint64_t) nsToHpetTicks(HpetState const *pThis, uint64_t u64Value)
284{
285 return ASMMultU64ByU32DivByU32(u64Value, FS_PER_NS, pThis->u32Period);
286}
287
288DECLINLINE(uint64_t) hpetGetTicks(HpetState const *pThis)
289{
290 /*
291 * We can use any timer to get current time, they all go
292 * with the same speed.
293 */
294 return nsToHpetTicks(pThis,
295 TMTimerGet(pThis->aTimers[0].CTX_SUFF(pTimer))
296 + pThis->u64HpetOffset);
297}
298
299DECLINLINE(uint64_t) hpetUpdateMasked(uint64_t u64NewValue,
300 uint64_t u64OldValue,
301 uint64_t u64Mask)
302{
303 u64NewValue &= u64Mask;
304 u64NewValue |= (u64OldValue & ~u64Mask);
305 return u64NewValue;
306}
307
308DECLINLINE(bool) hpetBitJustSet(uint64_t u64OldValue,
309 uint64_t u64NewValue,
310 uint64_t u64Mask)
311{
312 return !(u64OldValue & u64Mask)
313 && !!(u64NewValue & u64Mask);
314}
315
316DECLINLINE(bool) hpetBitJustCleared(uint64_t u64OldValue,
317 uint64_t u64NewValue,
318 uint64_t u64Mask)
319{
320 return !!(u64OldValue & u64Mask)
321 && !(u64NewValue & u64Mask);
322}
323
324DECLINLINE(uint64_t) hpetComputeDiff(HpetTimer *pHpetTimer,
325 uint64_t u64Now)
326{
327
328 if (hpet32bitTimer(pHpetTimer))
329 {
330 uint32_t u32Diff;
331
332 u32Diff = (uint32_t)pHpetTimer->u64Cmp - (uint32_t)u64Now;
333 u32Diff = ((int32_t)u32Diff > 0) ? u32Diff : (uint32_t)0;
334 return (uint64_t)u32Diff;
335 }
336 else
337 {
338 uint64_t u64Diff;
339
340 u64Diff = pHpetTimer->u64Cmp - u64Now;
341 u64Diff = ((int64_t)u64Diff > 0) ? u64Diff : (uint64_t)0;
342 return u64Diff;
343 }
344}
345
346
347static void hpetAdjustComparator(HpetTimer *pHpetTimer, uint64_t u64Now)
348{
349 uint64_t u64Period = pHpetTimer->u64Period;
350 if ( (pHpetTimer->u64Config & HPET_TN_PERIODIC)
351 && u64Period != 0)
352 {
353 /* While loop is suboptimal */
354 if (hpet32bitTimer(pHpetTimer))
355 {
356 while (hpetTimeAfter32(u64Now, pHpetTimer->u64Cmp))
357 pHpetTimer->u64Cmp = (uint32_t)(pHpetTimer->u64Cmp + u64Period);
358 }
359 else
360 {
361 while (hpetTimeAfter64(u64Now, pHpetTimer->u64Cmp))
362 pHpetTimer->u64Cmp += u64Period;
363 }
364 }
365}
366
367
368/**
369 * Sets the frequency hint if it's a periodic timer.
370 *
371 * @param pThis The HPET state.
372 * @param pHpetTimer The timer.
373 */
374DECLINLINE(void) hpetTimerSetFrequencyHint(HpetState *pThis, HpetTimer *pHpetTimer)
375{
376 if (pHpetTimer->u64Config & HPET_TN_PERIODIC)
377 {
378 uint64_t const u64Period = pHpetTimer->u64Period;
379 uint32_t const u32Freq = pThis->u32Period;
380 if (u64Period > 0 && u64Period < u32Freq)
381 TMTimerSetFrequencyHint(pHpetTimer->CTX_SUFF(pTimer), u32Freq / (uint32_t)u64Period);
382 }
383}
384
385
386static void hpetProgramTimer(HpetTimer *pHpetTimer)
387{
388 /* no wrapping on new timers */
389 pHpetTimer->u8Wrap = 0;
390
391 uint64_t u64Ticks = hpetGetTicks(pHpetTimer->CTX_SUFF(pHpet));
392 hpetAdjustComparator(pHpetTimer, u64Ticks);
393
394 uint64_t u64Diff = hpetComputeDiff(pHpetTimer, u64Ticks);
395
396 /*
397 * HPET spec says in one-shot 32-bit mode, generate an interrupt when
398 * counter wraps in addition to an interrupt with comparator match.
399 */
400 if ( hpet32bitTimer(pHpetTimer)
401 && !(pHpetTimer->u64Config & HPET_TN_PERIODIC))
402 {
403 uint32_t u32TillWrap = 0xffffffff - (uint32_t)u64Ticks + 1;
404 if (u32TillWrap < (uint32_t)u64Diff)
405 {
406 Log(("wrap on timer %d: till=%u ticks=%lld diff64=%lld\n",
407 pHpetTimer->idxTimer, u32TillWrap, u64Ticks, u64Diff));
408 u64Diff = u32TillWrap;
409 pHpetTimer->u8Wrap = 1;
410 }
411 }
412
413 /*
414 * HACK ALERT! Avoid killing VM with interrupts.
415 */
416#if 1 /** @todo: HACK, rethink, may have negative impact on the guest */
417 if (u64Diff == 0)
418 u64Diff = 100000; /* 1 millisecond */
419#endif
420
421 Log4(("HPET: next IRQ in %lld ticks (%lld ns)\n", u64Diff, hpetTicksToNs(pHpetTimer->CTX_SUFF(pHpet), u64Diff)));
422 TMTimerSetNano(pHpetTimer->CTX_SUFF(pTimer), hpetTicksToNs(pHpetTimer->CTX_SUFF(pHpet), u64Diff));
423 hpetTimerSetFrequencyHint(pHpetTimer->CTX_SUFF(pHpet), pHpetTimer);
424}
425
426
427/* -=-=-=-=-=- Timer register accesses -=-=-=-=-=- */
428
429
430/**
431 * Reads a HPET timer register.
432 *
433 * @returns VBox strict status code.
434 * @param pThis The HPET instance.
435 * @param iTimerNo The timer index.
436 * @param iTimerReg The index of the timer register to read.
437 * @param pu32Value Where to return the register value.
438 *
439 * @remarks ASSUMES the caller does holds the HPET lock.
440 */
441static int hpetTimerRegRead32(HpetState const *pThis, uint32_t iTimerNo, uint32_t iTimerReg, uint32_t *pu32Value)
442{
443 Assert(PDMCritSectIsOwner(&pThis->csLock));
444
445 if (iTimerNo >= HPET_CAP_GET_TIMERS(pThis->u32Capabilities))
446 {
447 static unsigned s_cOccurences = 0;
448 if (s_cOccurences++ < 10)
449 LogRel(("HPET: using timer above configured range: %d\n", iTimerNo));
450 *pu32Value = 0;
451 return VINF_SUCCESS;
452 }
453
454 HpetTimer const *pHpetTimer = &pThis->aTimers[iTimerNo];
455 uint32_t u32Value;
456 switch (iTimerReg)
457 {
458 case HPET_TN_CFG:
459 u32Value = (uint32_t)pHpetTimer->u64Config;
460 Log(("read HPET_TN_CFG on %d: %#x\n", iTimerNo, u32Value));
461 break;
462
463 case HPET_TN_CFG + 4:
464 u32Value = (uint32_t)(pHpetTimer->u64Config >> 32);
465 Log(("read HPET_TN_CFG+4 on %d: %#x\n", iTimerNo, u32Value));
466 break;
467
468 case HPET_TN_CMP:
469 u32Value = (uint32_t)pHpetTimer->u64Cmp;
470 Log(("read HPET_TN_CMP on %d: %#x (%#llx)\n", pHpetTimer->idxTimer, u32Value, pHpetTimer->u64Cmp));
471 break;
472
473 case HPET_TN_CMP + 4:
474 u32Value = (uint32_t)(pHpetTimer->u64Cmp >> 32);
475 Log(("read HPET_TN_CMP+4 on %d: %#x (%#llx)\n", pHpetTimer->idxTimer, u32Value, pHpetTimer->u64Cmp));
476 break;
477
478 case HPET_TN_ROUTE:
479 u32Value = (uint32_t)(pHpetTimer->u64Fsb >> 32); /** @todo Looks wrong, but since it's not supported, who cares. */
480 Log(("read HPET_TN_ROUTE on %d: %#x\n", iTimerNo, u32Value));
481 break;
482
483 default:
484 {
485 static unsigned s_cOccurences = 0;
486 if (s_cOccurences++ < 10)
487 LogRel(("invalid HPET register read %d on %d\n", iTimerReg, pHpetTimer->idxTimer));
488 u32Value = 0;
489 break;
490 }
491 }
492 *pu32Value = u32Value;
493 return VINF_SUCCESS;
494}
495
496
497/**
498 * 32-bit write to a HPET timer register.
499 *
500 * @returns Strict VBox status code.
501 *
502 * @param pThis The HPET state.
503 * @param idxReg The register being written to.
504 * @param u32NewValue The value being written.
505 *
506 * @remarks The caller should not hold the device lock, unless it also holds
507 * the TM lock.
508 */
509static int hpetTimerRegWrite32(HpetState *pThis, uint32_t iTimerNo, uint32_t iTimerReg, uint32_t u32NewValue)
510{
511 Assert(!PDMCritSectIsOwner(&pThis->csLock) || TMTimerIsLockOwner(pThis->aTimers[0].CTX_SUFF(pTimer)));
512
513 if (iTimerNo >= HPET_CAP_GET_TIMERS(pThis->u32Capabilities))
514 {
515 static unsigned s_cOccurences = 0;
516 if (s_cOccurences++ < 10)
517 LogRel(("HPET: using timer above configured range: %d\n", iTimerNo));
518 return VINF_SUCCESS;
519 }
520 HpetTimer *pHpetTimer = &pThis->aTimers[iTimerNo];
521
522 switch (iTimerReg)
523 {
524 case HPET_TN_CFG:
525 {
526 DEVHPET_LOCK_RETURN(pThis, VINF_IOM_R3_MMIO_WRITE);
527 Log(("write HPET_TN_CFG: %d: %x\n", iTimerNo, u32NewValue));
528 uint64_t const iOldValue = (uint32_t)pHpetTimer->u64Config;
529
530 uint64_t u64Mask = HPET_TN_CFG_WRITE_MASK;
531 if (pHpetTimer->u64Config & HPET_TN_PERIODIC_CAP)
532 u64Mask |= HPET_TN_PERIODIC;
533
534 if (pHpetTimer->u64Config & HPET_TN_SIZE_CAP)
535 u64Mask |= HPET_TN_32BIT;
536 else
537 u32NewValue &= ~HPET_TN_32BIT;
538
539 if (u32NewValue & HPET_TN_32BIT)
540 {
541 Log(("setting timer %d to 32-bit mode\n", iTimerNo));
542 pHpetTimer->u64Cmp = (uint32_t)pHpetTimer->u64Cmp;
543 pHpetTimer->u64Period = (uint32_t)pHpetTimer->u64Period;
544 }
545 if ((u32NewValue & HPET_TN_INT_TYPE) == HPET_TIMER_TYPE_LEVEL)
546 {
547 static unsigned s_cOccurences = 0;
548 if (s_cOccurences++ < 10)
549 LogRel(("level-triggered config not yet supported\n"));
550 AssertFailed();
551 }
552
553 /* We only care about lower 32-bits so far */
554 pHpetTimer->u64Config = hpetUpdateMasked(u32NewValue, iOldValue, u64Mask);
555 DEVHPET_UNLOCK(pThis);
556 break;
557 }
558
559 case HPET_TN_CFG + 4: /* Interrupt capabilities */
560 {
561 Log(("write HPET_TN_CFG + 4, useless\n"));
562 break;
563 }
564
565 case HPET_TN_CMP: /* lower bits of comparator register */
566 {
567 DEVHPET_LOCK_BOTH_RETURN(pThis, VINF_IOM_R3_MMIO_WRITE);
568 Log(("write HPET_TN_CMP on %d: %#x\n", iTimerNo, u32NewValue));
569
570 if (pHpetTimer->u64Config & HPET_TN_PERIODIC)
571 {
572 u32NewValue &= hpetInvalidValue(pHpetTimer) >> 1; /** @todo check this in the docs and add a not why? */
573 pHpetTimer->u64Period = RT_MAKE_U64(u32NewValue, pHpetTimer->u64Period);
574 }
575 pHpetTimer->u64Cmp = RT_MAKE_U64(u32NewValue, pHpetTimer->u64Cmp);
576 pHpetTimer->u64Config &= ~HPET_TN_SETVAL;
577 Log2(("after HPET_TN_CMP cmp=%#llx per=%#llx\n", pHpetTimer->u64Cmp, pHpetTimer->u64Period));
578
579 if (pThis->u64HpetConfig & HPET_CFG_ENABLE)
580 hpetProgramTimer(pHpetTimer);
581 DEVHPET_UNLOCK_BOTH(pThis);
582 break;
583 }
584
585 case HPET_TN_CMP + 4: /* upper bits of comparator register */
586 {
587 DEVHPET_LOCK_BOTH_RETURN(pThis, VINF_IOM_R3_MMIO_WRITE);
588 Log(("write HPET_TN_CMP + 4 on %d: %#x\n", iTimerNo, u32NewValue));
589 if (!hpet32bitTimer(pHpetTimer))
590 {
591 if (pHpetTimer->u64Config & HPET_TN_PERIODIC)
592 pHpetTimer->u64Period = RT_MAKE_U64(pHpetTimer->u64Period, u32NewValue);
593 pHpetTimer->u64Cmp = RT_MAKE_U64(pHpetTimer->u64Cmp, u32NewValue);
594
595 Log2(("after HPET_TN_CMP+4 cmp=%llx per=%llx tmr=%d\n", pHpetTimer->u64Cmp, pHpetTimer->u64Period, iTimerNo));
596
597 pHpetTimer->u64Config &= ~HPET_TN_SETVAL;
598
599 if (pThis->u64HpetConfig & HPET_CFG_ENABLE)
600 hpetProgramTimer(pHpetTimer);
601 }
602 DEVHPET_UNLOCK_BOTH(pThis);
603 break;
604 }
605
606 case HPET_TN_ROUTE:
607 {
608 Log(("write HPET_TN_ROUTE\n"));
609 break;
610 }
611
612 case HPET_TN_ROUTE + 4:
613 {
614 Log(("write HPET_TN_ROUTE + 4\n"));
615 break;
616 }
617
618 default:
619 {
620 static unsigned s_cOccurences = 0;
621 if (s_cOccurences++ < 10)
622 LogRel(("invalid timer register write: %d\n", iTimerReg));
623 break;
624 }
625 }
626
627 return VINF_SUCCESS;
628}
629
630
631/* -=-=-=-=-=- Non-timer register accesses -=-=-=-=-=- */
632
633
634/**
635 * Read a 32-bit HPET register.
636 *
637 * @returns Strict VBox status code.
638 * @param pThis The HPET state.
639 * @param idxReg The register to read.
640 * @param pu32Value Where to return the register value.
641 *
642 * @remarks The caller must not own the device lock if HPET_COUNTER is read.
643 */
644static int hpetConfigRegRead32(HpetState *pThis, uint32_t idxReg, uint32_t *pu32Value)
645{
646 Assert(!PDMCritSectIsOwner(&pThis->csLock) || (idxReg != HPET_COUNTER && idxReg != HPET_COUNTER + 4));
647
648 uint32_t u32Value;
649 switch (idxReg)
650 {
651 case HPET_ID:
652 DEVHPET_LOCK_RETURN(pThis, VINF_IOM_R3_MMIO_READ);
653 u32Value = pThis->u32Capabilities;
654 DEVHPET_UNLOCK(pThis);
655 Log(("read HPET_ID: %#x\n", u32Value));
656 break;
657
658 case HPET_PERIOD:
659 DEVHPET_LOCK_RETURN(pThis, VINF_IOM_R3_MMIO_READ);
660 u32Value = pThis->u32Period;
661 DEVHPET_UNLOCK(pThis);
662 Log(("read HPET_PERIOD: %#x\n", u32Value));
663 break;
664
665 case HPET_CFG:
666 DEVHPET_LOCK_RETURN(pThis, VINF_IOM_R3_MMIO_READ);
667 u32Value = (uint32_t)pThis->u64HpetConfig;
668 DEVHPET_UNLOCK(pThis);
669 Log(("read HPET_CFG: %#x\n", u32Value));
670 break;
671
672 case HPET_CFG + 4:
673 DEVHPET_LOCK_RETURN(pThis, VINF_IOM_R3_MMIO_READ);
674 u32Value = (uint32_t)(pThis->u64HpetConfig >> 32);
675 DEVHPET_UNLOCK(pThis);
676 Log(("read of HPET_CFG + 4: %#x\n", u32Value));
677 break;
678
679 case HPET_COUNTER:
680 case HPET_COUNTER + 4:
681 {
682 DEVHPET_LOCK_BOTH_RETURN(pThis, VINF_IOM_R3_MMIO_READ);
683
684 uint64_t u64Ticks;
685 if (pThis->u64HpetConfig & HPET_CFG_ENABLE)
686 u64Ticks = hpetGetTicks(pThis);
687 else
688 u64Ticks = pThis->u64HpetCounter;
689
690 DEVHPET_UNLOCK_BOTH(pThis);
691
692 /** @todo is it correct? */
693 u32Value = (idxReg == HPET_COUNTER) ? (uint32_t)u64Ticks : (uint32_t)(u64Ticks >> 32);
694 Log(("read HPET_COUNTER: %s part value %x (%#llx)\n",
695 (idxReg == HPET_COUNTER) ? "low" : "high", u32Value, u64Ticks));
696 break;
697 }
698
699 case HPET_STATUS:
700 DEVHPET_LOCK_RETURN(pThis, VINF_IOM_R3_MMIO_READ);
701 u32Value = (uint32_t)pThis->u64Isr;
702 DEVHPET_UNLOCK(pThis);
703 Log(("read HPET_STATUS: %#x\n", u32Value));
704 break;
705
706 default:
707 Log(("invalid HPET register read: %x\n", idxReg));
708 u32Value = 0;
709 break;
710 }
711
712 *pu32Value = u32Value;
713 return VINF_SUCCESS;
714}
715
716
717/**
718 * 32-bit write to a config register.
719 *
720 * @returns Strict VBox status code.
721 *
722 * @param pThis The HPET state.
723 * @param idxReg The register being written to.
724 * @param u32NewValue The value being written.
725 *
726 * @remarks The caller should not hold the device lock, unless it also holds
727 * the TM lock.
728 */
729static int hpetConfigRegWrite32(HpetState *pThis, uint32_t idxReg, uint32_t u32NewValue)
730{
731 Assert(!PDMCritSectIsOwner(&pThis->csLock) || TMTimerIsLockOwner(pThis->aTimers[0].CTX_SUFF(pTimer)));
732
733 int rc = VINF_SUCCESS;
734 switch (idxReg)
735 {
736 case HPET_ID:
737 case HPET_ID + 4:
738 {
739 Log(("write HPET_ID, useless\n"));
740 break;
741 }
742
743 case HPET_CFG:
744 {
745 DEVHPET_LOCK_BOTH_RETURN(pThis, VINF_IOM_R3_MMIO_WRITE);
746 uint32_t const iOldValue = (uint32_t)(pThis->u64HpetConfig);
747 Log(("write HPET_CFG: %x (old %x)\n", u32NewValue, iOldValue));
748
749 /*
750 * This check must be here, before actual update, as hpetLegacyMode
751 * may request retry in R3 - so we must keep state intact.
752 */
753 if ( ((iOldValue ^ u32NewValue) & HPET_CFG_LEGACY)
754 && pThis->pHpetHlpR3 != NIL_RTR3PTR)
755 {
756#ifdef IN_RING3
757 rc = pThis->pHpetHlpR3->pfnSetLegacyMode(pThis->pDevInsR3, RT_BOOL(u32NewValue & HPET_CFG_LEGACY));
758 if (rc != VINF_SUCCESS)
759#else
760 rc = VINF_IOM_R3_MMIO_WRITE;
761#endif
762 {
763 DEVHPET_UNLOCK_BOTH(pThis);
764 break;
765 }
766 }
767
768 pThis->u64HpetConfig = hpetUpdateMasked(u32NewValue, iOldValue, HPET_CFG_WRITE_MASK);
769
770 uint32_t const cTimers = HPET_CAP_GET_TIMERS(pThis->u32Capabilities);
771 if (hpetBitJustSet(iOldValue, u32NewValue, HPET_CFG_ENABLE))
772 {
773/** @todo Only get the time stamp once when reprogramming? */
774 /* Enable main counter and interrupt generation. */
775 pThis->u64HpetOffset = hpetTicksToNs(pThis, pThis->u64HpetCounter)
776 - TMTimerGet(pThis->aTimers[0].CTX_SUFF(pTimer));
777 for (uint32_t i = 0; i < cTimers; i++)
778 if (pThis->aTimers[i].u64Cmp != hpetInvalidValue(&pThis->aTimers[i]))
779 hpetProgramTimer(&pThis->aTimers[i]);
780 }
781 else if (hpetBitJustCleared(iOldValue, u32NewValue, HPET_CFG_ENABLE))
782 {
783 /* Halt main counter and disable interrupt generation. */
784 pThis->u64HpetCounter = hpetGetTicks(pThis);
785 for (uint32_t i = 0; i < cTimers; i++)
786 TMTimerStop(pThis->aTimers[i].CTX_SUFF(pTimer));
787 }
788
789 DEVHPET_UNLOCK_BOTH(pThis);
790 break;
791 }
792
793 case HPET_CFG + 4:
794 {
795 DEVHPET_LOCK_RETURN(pThis, VINF_IOM_R3_MMIO_WRITE);
796 pThis->u64HpetConfig = hpetUpdateMasked((uint64_t)u32NewValue << 32,
797 pThis->u64HpetConfig,
798 UINT64_C(0xffffffff00000000));
799 Log(("write HPET_CFG + 4: %x -> %#llx\n", u32NewValue, pThis->u64HpetConfig));
800 DEVHPET_UNLOCK(pThis);
801 break;
802 }
803
804 case HPET_STATUS:
805 {
806 DEVHPET_LOCK_RETURN(pThis, VINF_IOM_R3_MMIO_WRITE);
807 /* Clear ISR for all set bits in u32NewValue, see p. 14 of the HPET spec. */
808 pThis->u64Isr &= ~((uint64_t)u32NewValue);
809 Log(("write HPET_STATUS: %x -> ISR=%#llx\n", u32NewValue, pThis->u64Isr));
810 DEVHPET_UNLOCK(pThis);
811 break;
812 }
813
814 case HPET_STATUS + 4:
815 {
816 Log(("write HPET_STATUS + 4: %x\n", u32NewValue));
817 if (u32NewValue != 0)
818 {
819 static unsigned s_cOccurrences = 0;
820 if (s_cOccurrences++ < 10)
821 LogRel(("Writing HPET_STATUS + 4 with non-zero, ignored\n"));
822 }
823 break;
824 }
825
826 case HPET_COUNTER:
827 {
828 DEVHPET_LOCK_RETURN(pThis, VINF_IOM_R3_MMIO_WRITE);
829 pThis->u64HpetCounter = RT_MAKE_U64(u32NewValue, pThis->u64HpetCounter);
830 Log(("write HPET_COUNTER: %#x -> %llx\n", u32NewValue, pThis->u64HpetCounter));
831 DEVHPET_UNLOCK(pThis);
832 break;
833 }
834
835 case HPET_COUNTER + 4:
836 {
837 DEVHPET_LOCK_RETURN(pThis, VINF_IOM_R3_MMIO_WRITE);
838 pThis->u64HpetCounter = RT_MAKE_U64(pThis->u64HpetCounter, u32NewValue);
839 Log(("write HPET_COUNTER + 4: %#x -> %llx\n", u32NewValue, pThis->u64HpetCounter));
840 DEVHPET_UNLOCK(pThis);
841 break;
842 }
843
844 default:
845 {
846 static unsigned s_cOccurences = 0;
847 if (s_cOccurences++ < 10)
848 LogRel(("invalid HPET config write: %x\n", idxReg));
849 break;
850 }
851 }
852
853 return rc;
854}
855
856
857/* -=-=-=-=-=- MMIO callbacks -=-=-=-=-=- */
858
859
860/**
861 * @callback_method_impl{FNIOMMMIOREAD}
862 */
863PDMBOTHCBDECL(int) hpetMMIORead(PPDMDEVINS pDevIns, void *pvUser, RTGCPHYS GCPhysAddr, void *pv, unsigned cb)
864{
865 HpetState *pThis = PDMINS_2_DATA(pDevIns, HpetState*);
866 uint32_t const idxReg = (uint32_t)(GCPhysAddr - HPET_BASE);
867 NOREF(pvUser);
868
869 LogFlow(("hpetMMIORead (%d): %llx (%x)\n", cb, (uint64_t)GCPhysAddr, idxReg));
870
871 int rc = VINF_SUCCESS;
872 switch (cb)
873 {
874 case 4:
875 if (idxReg >= 0x100 && idxReg < 0x400)
876 {
877 DEVHPET_LOCK_RETURN(pThis, VINF_IOM_R3_MMIO_READ);
878 rc = hpetTimerRegRead32(pThis,
879 (idxReg - 0x100) / 0x20,
880 (idxReg - 0x100) % 0x20,
881 (uint32_t *)pv);
882 DEVHPET_UNLOCK(pThis);
883 }
884 else
885 rc = hpetConfigRegRead32(pThis, idxReg, (uint32_t *)pv);
886 break;
887
888 case 8:
889 {
890 /* Unaligned accesses not allowed */
891 if (RT_UNLIKELY(idxReg % 8 != 0))
892 {
893 rc = PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "idxReg=%#x cb=8\n", idxReg);
894 break;
895 }
896
897 /* Split the access except for timing sensitive registers. The
898 others assume the protection of the lock. */
899 PRTUINT64U pValue = (PRTUINT64U)pv;
900 if (idxReg == HPET_COUNTER)
901 {
902 /* When reading HPET counter we must read it in a single read,
903 to avoid unexpected time jumps on 32-bit overflow. */
904 DEVHPET_LOCK_BOTH_RETURN(pThis, VINF_IOM_R3_MMIO_READ);
905 if (pThis->u64HpetConfig & HPET_CFG_ENABLE)
906 pValue->u = hpetGetTicks(pThis);
907 else
908 pValue->u = pThis->u64HpetCounter;
909 DEVHPET_UNLOCK_BOTH(pThis);
910 }
911 else
912 {
913 DEVHPET_LOCK_RETURN(pThis, VINF_IOM_R3_MMIO_READ);
914 if (idxReg >= 0x100 && idxReg < 0x400)
915 {
916 uint32_t iTimer = (idxReg - 0x100) / 0x20;
917 uint32_t iTimerReg = (idxReg - 0x100) % 0x20;
918 rc = hpetTimerRegRead32(pThis, iTimer, iTimerReg, &pValue->s.Lo);
919 if (rc == VINF_SUCCESS)
920 rc = hpetTimerRegRead32(pThis, iTimer, iTimerReg + 4, &pValue->s.Hi);
921 }
922 else
923 {
924 /* for most 8-byte accesses we just split them, happens under lock anyway. */
925 rc = hpetConfigRegRead32(pThis, idxReg, &pValue->s.Lo);
926 if (rc == VINF_SUCCESS)
927 rc = hpetConfigRegRead32(pThis, idxReg + 4, &pValue->s.Hi);
928 }
929 DEVHPET_UNLOCK(pThis);
930 }
931 break;
932 }
933
934 case 1:
935 case 2:
936 Log(("Narrow read: %d\n", cb));
937 rc = VINF_SUCCESS;
938 break;
939
940 default:
941 AssertReleaseMsgFailed(("cb=%d\n", cb)); /* for now we assume simple accesses. */
942 rc = VINF_SUCCESS;
943 }
944
945 return rc;
946}
947
948
949/**
950 * @callback_method_impl{FNIOMMMIOWRITE}
951 */
952PDMBOTHCBDECL(int) hpetMMIOWrite(PPDMDEVINS pDevIns, void *pvUser, RTGCPHYS GCPhysAddr, void const *pv, unsigned cb)
953{
954 HpetState *pThis = PDMINS_2_DATA(pDevIns, HpetState*);
955 uint32_t idxReg = (uint32_t)(GCPhysAddr - HPET_BASE);
956 LogFlow(("hpetMMIOWrite: cb=%u reg=%03x (%RGp) val=%llx\n",
957 cb, idxReg, GCPhysAddr, cb == 4 ? *(uint32_t *)pv : cb == 8 ? *(uint64_t *)pv : 0xdeadbeef));
958 NOREF(pvUser);
959
960 int rc;
961 switch (cb)
962 {
963 case 4:
964 if (idxReg >= 0x100 && idxReg < 0x400)
965 rc = hpetTimerRegWrite32(pThis,
966 (idxReg - 0x100) / 0x20,
967 (idxReg - 0x100) % 0x20,
968 *(uint32_t const *)pv);
969 else
970 rc = hpetConfigRegWrite32(pThis, idxReg, *(uint32_t const *)pv);
971 break;
972
973 case 8:
974 {
975 /* Unaligned accesses are not allowed. */
976 if (RT_UNLIKELY(idxReg % 8 != 0))
977 {
978 rc = PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "idxReg=%#x cb=8\n", idxReg);
979 break;
980 }
981
982 /* Split the access and rely on the locking to prevent trouble. */
983 DEVHPET_LOCK_BOTH_RETURN(pThis, VINF_IOM_R3_MMIO_WRITE);
984 RTUINT64U uValue;
985 uValue.u = *(uint64_t const *)pv;
986 if (idxReg >= 0x100 && idxReg < 0x400)
987 {
988 uint32_t iTimer = (idxReg - 0x100) / 0x20;
989 uint32_t iTimerReg = (idxReg - 0x100) % 0x20;
990/** @todo Consider handling iTimerReg == HPET_TN_CMP specially here */
991 rc = hpetTimerRegWrite32(pThis, iTimer, iTimerReg, uValue.s.Lo);
992 if (RT_LIKELY(rc == VINF_SUCCESS))
993 rc = hpetTimerRegWrite32(pThis, iTimer, iTimerReg + 4, uValue.s.Hi);
994 }
995 else
996 {
997 rc = hpetConfigRegWrite32(pThis, idxReg, uValue.s.Lo);
998 if (RT_LIKELY(rc == VINF_SUCCESS))
999 rc = hpetConfigRegWrite32(pThis, idxReg + 4, uValue.s.Hi);
1000 }
1001 DEVHPET_UNLOCK_BOTH(pThis);
1002 break;
1003 }
1004
1005 case 1:
1006 case 2:
1007 Log(("Narrow write: %d\n", cb));
1008 rc = VINF_SUCCESS;
1009 break;
1010
1011 default:
1012 AssertReleaseMsgFailed(("cb=%d\n", cb)); /* for now we assume simple accesses. */
1013 rc = VERR_INTERNAL_ERROR;
1014 break;
1015 }
1016
1017 return rc;
1018}
1019
1020#ifdef IN_RING3
1021
1022/* -=-=-=-=-=- Timer Callback Processing -=-=-=-=-=- */
1023
1024/**
1025 * Gets the IRQ of an HPET timer.
1026 *
1027 * @returns IRQ number.
1028 * @param pHpetTimer The HPET timer.
1029 */
1030static uint32_t hpetTimerCbGetIrq(struct HpetTimer const *pHpetTimer)
1031{
1032 /*
1033 * Per spec, in legacy mode HPET timers wired as:
1034 * timer 0: IRQ0 for PIC and IRQ2 for APIC
1035 * timer 1: IRQ8 for both PIC and APIC
1036 *
1037 * ISA IRQ delivery logic will take care of correct delivery
1038 * to the different ICs.
1039 */
1040 if ( (pHpetTimer->idxTimer <= 1)
1041 && (pHpetTimer->CTX_SUFF(pHpet)->u64HpetConfig & HPET_CFG_LEGACY))
1042 return (pHpetTimer->idxTimer == 0) ? 0 : 8;
1043
1044 return (pHpetTimer->u64Config & HPET_TN_INT_ROUTE_MASK) >> HPET_TN_INT_ROUTE_SHIFT;
1045}
1046
1047
1048/**
1049 * Used by hpetTimerCb to update the IRQ status.
1050 *
1051 * @param pThis The HPET device state.
1052 * @param pHpetTimer The HPET timer.
1053 */
1054static void hpetTimerCbUpdateIrq(HpetState *pThis, struct HpetTimer *pHpetTimer)
1055{
1056 /** @todo: is it correct? */
1057 if ( !!(pHpetTimer->u64Config & HPET_TN_ENABLE)
1058 && !!(pThis->u64HpetConfig & HPET_CFG_ENABLE))
1059 {
1060 uint32_t irq = hpetTimerCbGetIrq(pHpetTimer);
1061 Log4(("HPET: raising IRQ %d\n", irq));
1062
1063 /* ISR bits are only set in level-triggered mode. */
1064 if ((pHpetTimer->u64Config & HPET_TN_INT_TYPE) == HPET_TIMER_TYPE_LEVEL)
1065 pThis->u64Isr |= (uint64_t)(1 << pHpetTimer->idxTimer);
1066
1067 /* We trigger flip/flop in edge-triggered mode and do nothing in
1068 level-triggered mode yet. */
1069 if ((pHpetTimer->u64Config & HPET_TN_INT_TYPE) == HPET_TIMER_TYPE_EDGE)
1070 pThis->pHpetHlpR3->pfnSetIrq(pThis->CTX_SUFF(pDevIns), irq, PDM_IRQ_LEVEL_FLIP_FLOP);
1071 else
1072 AssertFailed();
1073 /** @todo: implement IRQs in level-triggered mode */
1074 }
1075}
1076
1077/**
1078 * Device timer callback function.
1079 *
1080 * @param pDevIns Device instance of the device which registered the timer.
1081 * @param pTimer The timer handle.
1082 * @param pvUser Pointer to the HPET timer state.
1083 */
1084static DECLCALLBACK(void) hpetTimerCb(PPDMDEVINS pDevIns, PTMTIMER pTimer, void *pvUser)
1085{
1086 HpetState *pThis = PDMINS_2_DATA(pDevIns, HpetState *);
1087 HpetTimer *pHpetTimer = (HpetTimer *)pvUser;
1088 uint64_t u64Period = pHpetTimer->u64Period;
1089 uint64_t u64CurTick = hpetGetTicks(pThis);
1090 uint64_t u64Diff;
1091
1092 if ((pHpetTimer->u64Config & HPET_TN_PERIODIC) && (u64Period != 0))
1093 {
1094 hpetAdjustComparator(pHpetTimer, u64CurTick);
1095
1096 u64Diff = hpetComputeDiff(pHpetTimer, u64CurTick);
1097
1098 Log4(("HPET: periodical: next in %llu\n", hpetTicksToNs(pThis, u64Diff)));
1099 TMTimerSetNano(pTimer, hpetTicksToNs(pThis, u64Diff));
1100 }
1101 else if ( hpet32bitTimer(pHpetTimer)
1102 && !(pHpetTimer->u64Config & HPET_TN_PERIODIC))
1103 {
1104 if (pHpetTimer->u8Wrap)
1105 {
1106 u64Diff = hpetComputeDiff(pHpetTimer, u64CurTick);
1107 TMTimerSetNano(pTimer, hpetTicksToNs(pThis, u64Diff));
1108 pHpetTimer->u8Wrap = 0;
1109 }
1110 }
1111
1112 /* Should it really be under lock, does it really matter? */
1113 hpetTimerCbUpdateIrq(pThis, pHpetTimer);
1114}
1115
1116
1117/* -=-=-=-=-=- DBGF Info Handlers -=-=-=-=-=- */
1118
1119
1120/**
1121 * @callback_method_impl{FNDBGFHANDLERDEV}
1122 */
1123static DECLCALLBACK(void) hpetInfo(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
1124{
1125 HpetState *pThis = PDMINS_2_DATA(pDevIns, HpetState *);
1126 NOREF(pszArgs);
1127
1128 pHlp->pfnPrintf(pHlp,
1129 "HPET status:\n"
1130 " config=%016RX64 isr=%016RX64\n"
1131 " offset=%016RX64 counter=%016RX64 frequency=%08x\n"
1132 " legacy-mode=%s timer-count=%u\n",
1133 pThis->u64HpetConfig, pThis->u64Isr,
1134 pThis->u64HpetOffset, pThis->u64HpetCounter, pThis->u32Period,
1135 !!(pThis->u64HpetConfig & HPET_CFG_LEGACY) ? "on " : "off",
1136 HPET_CAP_GET_TIMERS(pThis->u32Capabilities));
1137 pHlp->pfnPrintf(pHlp,
1138 "Timers:\n");
1139 for (unsigned i = 0; i < RT_ELEMENTS(pThis->aTimers); i++)
1140 {
1141 pHlp->pfnPrintf(pHlp, " %d: comparator=%016RX64 period(hidden)=%016RX64 cfg=%016RX64\n",
1142 pThis->aTimers[i].idxTimer,
1143 pThis->aTimers[i].u64Cmp,
1144 pThis->aTimers[i].u64Period,
1145 pThis->aTimers[i].u64Config);
1146 }
1147}
1148
1149
1150/* -=-=-=-=-=- Saved State -=-=-=-=-=- */
1151
1152
1153/**
1154 * @callback_method_impl{FNSSMDEVLIVEEXEC}
1155 */
1156static DECLCALLBACK(int) hpetLiveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t uPass)
1157{
1158 HpetState *pThis = PDMINS_2_DATA(pDevIns, HpetState *);
1159 NOREF(uPass);
1160
1161 SSMR3PutU8(pSSM, HPET_CAP_GET_TIMERS(pThis->u32Capabilities));
1162
1163 return VINF_SSM_DONT_CALL_AGAIN;
1164}
1165
1166
1167/**
1168 * @callback_method_impl{FNSSMDEVSAVEEXEC}
1169 */
1170static DECLCALLBACK(int) hpetSaveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
1171{
1172 HpetState *pThis = PDMINS_2_DATA(pDevIns, HpetState *);
1173
1174 /*
1175 * The config.
1176 */
1177 hpetLiveExec(pDevIns, pSSM, SSM_PASS_FINAL);
1178
1179 /*
1180 * The state.
1181 */
1182 uint32_t const cTimers = HPET_CAP_GET_TIMERS(pThis->u32Capabilities);
1183 for (uint32_t iTimer = 0; iTimer < cTimers; iTimer++)
1184 {
1185 HpetTimer *pHpetTimer = &pThis->aTimers[iTimer];
1186 TMR3TimerSave(pHpetTimer->pTimerR3, pSSM);
1187 SSMR3PutU8(pSSM, pHpetTimer->u8Wrap);
1188 SSMR3PutU64(pSSM, pHpetTimer->u64Config);
1189 SSMR3PutU64(pSSM, pHpetTimer->u64Cmp);
1190 SSMR3PutU64(pSSM, pHpetTimer->u64Fsb);
1191 SSMR3PutU64(pSSM, pHpetTimer->u64Period);
1192 }
1193
1194 SSMR3PutU64(pSSM, pThis->u64HpetOffset);
1195 uint64_t u64CapPer = RT_MAKE_U64(pThis->u32Capabilities, pThis->u32Period);
1196 SSMR3PutU64(pSSM, u64CapPer);
1197 SSMR3PutU64(pSSM, pThis->u64HpetConfig);
1198 SSMR3PutU64(pSSM, pThis->u64Isr);
1199 return SSMR3PutU64(pSSM, pThis->u64HpetCounter);
1200}
1201
1202
1203/**
1204 * @callback_method_impl{FNSSMDEVLOADEXEC}
1205 */
1206static DECLCALLBACK(int) hpetLoadExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
1207{
1208 HpetState *pThis = PDMINS_2_DATA(pDevIns, HpetState *);
1209
1210 /*
1211 * Version checks.
1212 */
1213 if (uVersion == HPET_SAVED_STATE_VERSION_EMPTY)
1214 return VINF_SUCCESS;
1215 if (uVersion != HPET_SAVED_STATE_VERSION)
1216 return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
1217
1218 /*
1219 * The config.
1220 */
1221 uint8_t cTimers;
1222 int rc = SSMR3GetU8(pSSM, &cTimers);
1223 AssertRCReturn(rc, rc);
1224 if (cTimers > RT_ELEMENTS(pThis->aTimers))
1225 return SSMR3SetCfgError(pSSM, RT_SRC_POS, N_("Config mismatch - too many timers: saved=%#x config=%#x"),
1226 cTimers, RT_ELEMENTS(pThis->aTimers));
1227
1228 if (uPass != SSM_PASS_FINAL)
1229 return VINF_SUCCESS;
1230
1231 /*
1232 * The state.
1233 */
1234 for (uint32_t iTimer = 0; iTimer < cTimers; iTimer++)
1235 {
1236 HpetTimer *pHpetTimer = &pThis->aTimers[iTimer];
1237 TMR3TimerLoad(pHpetTimer->pTimerR3, pSSM);
1238 SSMR3GetU8(pSSM, &pHpetTimer->u8Wrap);
1239 SSMR3GetU64(pSSM, &pHpetTimer->u64Config);
1240 SSMR3GetU64(pSSM, &pHpetTimer->u64Cmp);
1241 SSMR3GetU64(pSSM, &pHpetTimer->u64Fsb);
1242 SSMR3GetU64(pSSM, &pHpetTimer->u64Period);
1243 }
1244
1245 SSMR3GetU64(pSSM, &pThis->u64HpetOffset);
1246 uint64_t u64CapPer;
1247 SSMR3GetU64(pSSM, &u64CapPer);
1248 SSMR3GetU64(pSSM, &pThis->u64HpetConfig);
1249 SSMR3GetU64(pSSM, &pThis->u64Isr);
1250 rc = SSMR3GetU64(pSSM, &pThis->u64HpetCounter);
1251 if (RT_FAILURE(rc))
1252 return rc;
1253 if (HPET_CAP_GET_TIMERS(RT_LO_U32(u64CapPer)) != cTimers)
1254 return SSMR3SetCfgError(pSSM, RT_SRC_POS, N_("Capabilities does not match timer count: cTimers=%#x caps=%#x"),
1255 cTimers, (unsigned)HPET_CAP_GET_TIMERS(u64CapPer));
1256 pThis->u32Capabilities = RT_LO_U32(u64CapPer);
1257 pThis->u32Period = RT_HI_U32(u64CapPer);
1258
1259 /*
1260 * Set the timer frequency hints.
1261 */
1262 PDMCritSectEnter(&pThis->csLock, VERR_IGNORED);
1263 for (uint32_t iTimer = 0; iTimer < cTimers; iTimer++)
1264 {
1265 HpetTimer *pHpetTimer = &pThis->aTimers[iTimer];
1266 if (TMTimerIsActive(pHpetTimer->CTX_SUFF(pTimer)))
1267 hpetTimerSetFrequencyHint(pThis, pHpetTimer);
1268 }
1269 PDMCritSectLeave(&pThis->csLock);
1270 return VINF_SUCCESS;
1271}
1272
1273
1274/* -=-=-=-=-=- PDMDEVREG -=-=-=-=-=- */
1275
1276
1277/**
1278 * @interface_method_impl{PDMDEVREG,pfnRelocate}
1279 */
1280static DECLCALLBACK(void) hpetRelocate(PPDMDEVINS pDevIns, RTGCINTPTR offDelta)
1281{
1282 HpetState *pThis = PDMINS_2_DATA(pDevIns, HpetState *);
1283 LogFlow(("hpetRelocate:\n"));
1284 NOREF(offDelta);
1285
1286 pThis->pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
1287 pThis->pHpetHlpRC = pThis->pHpetHlpR3->pfnGetRCHelpers(pDevIns);
1288
1289 for (unsigned i = 0; i < RT_ELEMENTS(pThis->aTimers); i++)
1290 {
1291 HpetTimer *pTm = &pThis->aTimers[i];
1292 if (pTm->pTimerR3)
1293 pTm->pTimerRC = TMTimerRCPtr(pTm->pTimerR3);
1294 pTm->pHpetRC = PDMINS_2_DATA_RCPTR(pDevIns);
1295 }
1296}
1297
1298
1299/**
1300 * @interface_method_impl{PDMDEVREG,pfnReset}
1301 */
1302static DECLCALLBACK(void) hpetReset(PPDMDEVINS pDevIns)
1303{
1304 HpetState *pThis = PDMINS_2_DATA(pDevIns, HpetState *);
1305 LogFlow(("hpetReset:\n"));
1306
1307 /*
1308 * The timers first.
1309 */
1310 TMTimerLock(pThis->aTimers[0].pTimerR3, VERR_IGNORED);
1311 for (unsigned i = 0; i < RT_ELEMENTS(pThis->aTimers); i++)
1312 {
1313 HpetTimer *pHpetTimer = &pThis->aTimers[i];
1314 Assert(pHpetTimer->idxTimer == i);
1315 TMTimerStop(pHpetTimer->pTimerR3);
1316
1317 /* capable of periodic operations and 64-bits */
1318 if (pThis->fIch9)
1319 pHpetTimer->u64Config = (i == 0)
1320 ? (HPET_TN_PERIODIC_CAP | HPET_TN_SIZE_CAP)
1321 : 0;
1322 else
1323 pHpetTimer->u64Config = HPET_TN_PERIODIC_CAP | HPET_TN_SIZE_CAP;
1324
1325 /* We can do all IRQs */
1326 uint32_t u32RoutingCap = 0xffffffff;
1327 pHpetTimer->u64Config |= ((uint64_t)u32RoutingCap) << 32;
1328 pHpetTimer->u64Period = 0;
1329 pHpetTimer->u8Wrap = 0;
1330 pHpetTimer->u64Cmp = hpetInvalidValue(pHpetTimer);
1331 }
1332 TMTimerUnlock(pThis->aTimers[0].pTimerR3);
1333
1334 /*
1335 * The HPET state.
1336 */
1337 pThis->u64HpetConfig = 0;
1338 pThis->u64HpetCounter = 0;
1339 pThis->u64HpetOffset = 0;
1340
1341 /* 64-bit main counter; 3 timers supported; LegacyReplacementRoute. */
1342 pThis->u32Capabilities = (1 << 15) /* LEG_RT_CAP - LegacyReplacementRoute capable. */
1343 | (1 << 13) /* COUNTER_SIZE_CAP - Main counter is 64-bit capable. */
1344 | 1; /* REV_ID - Revision, must not be 0 */
1345 if (pThis->fIch9) /* NUM_TIM_CAP - Number of timers -1. */
1346 pThis->u32Capabilities |= (HPET_NUM_TIMERS_ICH9 - 1) << 8;
1347 else
1348 pThis->u32Capabilities |= (HPET_NUM_TIMERS_PIIX - 1) << 8;
1349 pThis->u32Capabilities |= UINT32_C(0x80860000); /* VENDOR */
1350 AssertCompile(HPET_NUM_TIMERS_ICH9 <= RT_ELEMENTS(pThis->aTimers));
1351 AssertCompile(HPET_NUM_TIMERS_PIIX <= RT_ELEMENTS(pThis->aTimers));
1352
1353 pThis->u32Period = pThis->fIch9 ? HPET_CLK_PERIOD_ICH9 : HPET_CLK_PERIOD_PIIX;
1354
1355 /*
1356 * Notify the PIT/RTC devices.
1357 */
1358 if (pThis->pHpetHlpR3)
1359 pThis->pHpetHlpR3->pfnSetLegacyMode(pDevIns, false /*fActive*/);
1360}
1361
1362
1363/**
1364 * @interface_method_impl{PDMDEVREG,pfnConstruct}
1365 */
1366static DECLCALLBACK(int) hpetConstruct(PPDMDEVINS pDevIns, int iInstance, PCFGMNODE pCfg)
1367{
1368 PDMDEV_CHECK_VERSIONS_RETURN(pDevIns);
1369 HpetState *pThis = PDMINS_2_DATA(pDevIns, HpetState *);
1370
1371 /* Only one HPET device now, as we use fixed MMIO region. */
1372 Assert(iInstance == 0);
1373
1374 /*
1375 * Validate and read the configuration.
1376 */
1377 PDMDEV_VALIDATE_CONFIG_RETURN(pDevIns, "GCEnabled|R0Enabled|ICH9", "");
1378
1379 bool fRCEnabled;
1380 int rc = CFGMR3QueryBoolDef(pCfg, "GCEnabled", &fRCEnabled, true);
1381 if (RT_FAILURE(rc))
1382 return PDMDEV_SET_ERROR(pDevIns, rc,
1383 N_("Configuration error: Querying \"GCEnabled\" as a bool failed"));
1384
1385 bool fR0Enabled;
1386 rc = CFGMR3QueryBoolDef(pCfg, "R0Enabled", &fR0Enabled, true);
1387 if (RT_FAILURE(rc))
1388 return PDMDEV_SET_ERROR(pDevIns, rc,
1389 N_("Configuration error: failed to read R0Enabled as boolean"));
1390
1391 rc = CFGMR3QueryBoolDef(pCfg, "ICH9", &pThis->fIch9, false);
1392 if (RT_FAILURE(rc))
1393 return PDMDEV_SET_ERROR(pDevIns, rc,
1394 N_("Configuration error: failed to read ICH9 as boolean"));
1395
1396 /*
1397 * Initialize the device state.
1398 */
1399 pThis->pDevInsR3 = pDevIns;
1400 pThis->pDevInsR0 = PDMDEVINS_2_R0PTR(pDevIns);
1401 pThis->pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
1402
1403 rc = PDMDevHlpCritSectInit(pDevIns, &pThis->csLock, RT_SRC_POS, "HPET#%u", pDevIns->iInstance);
1404 AssertRCReturn(rc, rc);
1405
1406 /* No automatic locking. */
1407 rc = PDMDevHlpSetDeviceCritSect(pDevIns, PDMDevHlpCritSectGetNop(pDevIns));
1408 AssertRCReturn(rc, rc);
1409
1410 /* Init the HPET timers (init all regardless of how many we expose). */
1411 for (unsigned i = 0; i < RT_ELEMENTS(pThis->aTimers); i++)
1412 {
1413 HpetTimer *pHpetTimer = &pThis->aTimers[i];
1414
1415 pHpetTimer->idxTimer = i;
1416 pHpetTimer->pHpetR3 = pThis;
1417 pHpetTimer->pHpetR0 = PDMINS_2_DATA_R0PTR(pDevIns);
1418 pHpetTimer->pHpetRC = PDMINS_2_DATA_RCPTR(pDevIns);
1419
1420 rc = PDMDevHlpTMTimerCreate(pDevIns, TMCLOCK_VIRTUAL_SYNC, hpetTimerCb, pHpetTimer,
1421 TMTIMER_FLAGS_NO_CRIT_SECT, "HPET Timer",
1422 &pThis->aTimers[i].pTimerR3);
1423 AssertRCReturn(rc, rc);
1424 pThis->aTimers[i].pTimerRC = TMTimerRCPtr(pThis->aTimers[i].pTimerR3);
1425 pThis->aTimers[i].pTimerR0 = TMTimerR0Ptr(pThis->aTimers[i].pTimerR3);
1426 rc = TMR3TimerSetCritSect(pThis->aTimers[i].pTimerR3, &pThis->csLock);
1427 AssertRCReturn(rc, rc);
1428 }
1429
1430 /* This must be done prior to registering the HPET, right? */
1431 hpetReset(pDevIns);
1432
1433 /*
1434 * Register the HPET and get helpers.
1435 */
1436 PDMHPETREG HpetReg;
1437 HpetReg.u32Version = PDM_HPETREG_VERSION;
1438 rc = PDMDevHlpHPETRegister(pDevIns, &HpetReg, &pThis->pHpetHlpR3);
1439 AssertRCReturn(rc, rc);
1440
1441 /*
1442 * Register the MMIO range, PDM API requests page aligned
1443 * addresses and sizes.
1444 */
1445 rc = PDMDevHlpMMIORegister(pDevIns, HPET_BASE, 0x1000, pThis,
1446 IOMMMIO_FLAGS_READ_PASSTHRU | IOMMMIO_FLAGS_WRITE_PASSTHRU,
1447 hpetMMIOWrite, hpetMMIORead, "HPET Memory");
1448 AssertRCReturn(rc, rc);
1449
1450 if (fRCEnabled)
1451 {
1452 rc = PDMDevHlpMMIORegisterRC(pDevIns, HPET_BASE, 0x1000, NIL_RTRCPTR /*pvUser*/, "hpetMMIOWrite", "hpetMMIORead");
1453 AssertRCReturn(rc, rc);
1454
1455 pThis->pHpetHlpRC = pThis->pHpetHlpR3->pfnGetRCHelpers(pDevIns);
1456 AssertReturn(pThis->pHpetHlpRC != NIL_RTRCPTR, VERR_INTERNAL_ERROR);
1457 }
1458
1459 if (fR0Enabled)
1460 {
1461 rc = PDMDevHlpMMIORegisterR0(pDevIns, HPET_BASE, 0x1000, NIL_RTR0PTR /*pvUser*/,
1462 "hpetMMIOWrite", "hpetMMIORead");
1463 AssertRCReturn(rc, rc);
1464
1465 pThis->pHpetHlpR0 = pThis->pHpetHlpR3->pfnGetR0Helpers(pDevIns);
1466 AssertReturn(pThis->pHpetHlpR0 != NIL_RTR0PTR, VERR_INTERNAL_ERROR);
1467 }
1468
1469 /* Register SSM callbacks */
1470 rc = PDMDevHlpSSMRegister3(pDevIns, HPET_SAVED_STATE_VERSION, sizeof(*pThis), hpetLiveExec, hpetSaveExec, hpetLoadExec);
1471 AssertRCReturn(rc, rc);
1472
1473 /* Register an info callback. */
1474 PDMDevHlpDBGFInfoRegister(pDevIns, "hpet", "Display HPET status. (no arguments)", hpetInfo);
1475
1476 return VINF_SUCCESS;
1477}
1478
1479
1480/**
1481 * The device registration structure.
1482 */
1483const PDMDEVREG g_DeviceHPET =
1484{
1485 /* u32Version */
1486 PDM_DEVREG_VERSION,
1487 /* szName */
1488 "hpet",
1489 /* szRCMod */
1490 "VBoxDDGC.gc",
1491 /* szR0Mod */
1492 "VBoxDDR0.r0",
1493 /* pszDescription */
1494 " High Precision Event Timer (HPET) Device",
1495 /* fFlags */
1496 PDM_DEVREG_FLAGS_HOST_BITS_DEFAULT | PDM_DEVREG_FLAGS_GUEST_BITS_32_64 | PDM_DEVREG_FLAGS_PAE36 | PDM_DEVREG_FLAGS_RC | PDM_DEVREG_FLAGS_R0,
1497 /* fClass */
1498 PDM_DEVREG_CLASS_PIT,
1499 /* cMaxInstances */
1500 1,
1501 /* cbInstance */
1502 sizeof(HpetState),
1503 /* pfnConstruct */
1504 hpetConstruct,
1505 /* pfnDestruct */
1506 NULL,
1507 /* pfnRelocate */
1508 hpetRelocate,
1509 /* pfnIOCtl */
1510 NULL,
1511 /* pfnPowerOn */
1512 NULL,
1513 /* pfnReset */
1514 hpetReset,
1515 /* pfnSuspend */
1516 NULL,
1517 /* pfnResume */
1518 NULL,
1519 /* pfnAttach */
1520 NULL,
1521 /* pfnDetach */
1522 NULL,
1523 /* pfnQueryInterface. */
1524 NULL,
1525 /* pfnInitComplete */
1526 NULL,
1527 /* pfnPowerOff */
1528 NULL,
1529 /* pfnSoftReset */
1530 NULL,
1531 /* u32VersionEnd */
1532 PDM_DEVREG_VERSION
1533};
1534
1535#endif /* IN_RING3 */
1536#endif /* !VBOX_DEVICE_STRUCT_TESTCASE */
1537
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