1 | /* $Id: DevFwCommon.cpp 46355 2013-06-03 10:01:49Z vboxsync $ */
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2 | /** @file
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3 | * FwCommon - Shared firmware code (used by DevPcBios & DevEFI).
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4 | */
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5 |
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6 | /*
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7 | * Copyright (C) 2009-2012 Oracle Corporation
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8 | *
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9 | * This file is part of VirtualBox Open Source Edition (OSE), as
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10 | * available from http://www.virtualbox.org. This file is free software;
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11 | * you can redistribute it and/or modify it under the terms of the GNU
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12 | * General Public License (GPL) as published by the Free Software
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13 | * Foundation, in version 2 as it comes in the "COPYING" file of the
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14 | * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
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15 | * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
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16 | */
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17 |
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18 | /*******************************************************************************
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19 | * Header Files *
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20 | *******************************************************************************/
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21 | #define LOG_GROUP LOG_GROUP_DEV
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22 | #include <VBox/vmm/pdmdev.h>
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23 |
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24 | #include <VBox/log.h>
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25 | #include <VBox/err.h>
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26 | #include <VBox/param.h>
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27 |
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28 | #include <iprt/asm.h>
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29 | #include <iprt/assert.h>
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30 | #include <iprt/buildconfig.h>
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31 | #include <iprt/file.h>
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32 | #include <iprt/mem.h>
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33 | #include <iprt/string.h>
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34 | #include <iprt/uuid.h>
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35 | #include <iprt/system.h>
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36 | #include <iprt/cdefs.h>
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37 |
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38 | #include "VBoxDD.h"
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39 | #include "VBoxDD2.h"
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40 | #include "DevFwCommon.h"
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41 |
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42 |
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43 | /*******************************************************************************
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44 | * Defined Constants And Macros *
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45 | *******************************************************************************/
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46 |
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47 | /*
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48 | * Default DMI data (legacy).
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49 | * Don't change this information otherwise Windows guests might demand re-activation!
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50 | */
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51 |
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52 | /* type 0 -- DMI BIOS information */
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53 | static const int32_t s_iDefDmiBIOSReleaseMajor = 0;
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54 | static const int32_t s_iDefDmiBIOSReleaseMinor = 0;
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55 | static const int32_t s_iDefDmiBIOSFirmwareMajor = 0;
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56 | static const int32_t s_iDefDmiBIOSFirmwareMinor = 0;
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57 | static const char *s_szDefDmiBIOSVendor = "innotek GmbH";
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58 | static const char *s_szDefDmiBIOSVersion = "VirtualBox";
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59 | static const char *s_szDefDmiBIOSReleaseDate = "12/01/2006";
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60 | /* type 1 -- DMI system information */
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61 | static const char *s_szDefDmiSystemVendor = "innotek GmbH";
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62 | static const char *s_szDefDmiSystemProduct = "VirtualBox";
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63 | static const char *s_szDefDmiSystemVersion = "1.2";
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64 | static const char *s_szDefDmiSystemSerial = "0";
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65 | static const char *s_szDefDmiSystemSKU = "";
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66 | static const char *s_szDefDmiSystemFamily = "Virtual Machine";
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67 | /* type 2 -- DMI board information */
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68 | static const char *s_szDefDmiBoardVendor = "Oracle Corporation";
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69 | static const char *s_szDefDmiBoardProduct = "VirtualBox";
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70 | static const char *s_szDefDmiBoardVersion = "1.2";
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71 | static const char *s_szDefDmiBoardSerial = "0";
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72 | static const char *s_szDefDmiBoardAssetTag = "";
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73 | static const char *s_szDefDmiBoardLocInChass = "";
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74 | static const int32_t s_iDefDmiBoardBoardType = 0x0A; /* Motherboard */
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75 | /* type 3 -- DMI chassis information */
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76 | static const char *s_szDefDmiChassisVendor = "Oracle Corporation";
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77 | static const int32_t s_iDefDmiChassisType = 0x01; /* ''other'', no chassis lock present */
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78 | static const char *s_szDefDmiChassisVersion = "";
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79 | static const char *s_szDefDmiChassisSerial = "";
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80 | static const char *s_szDefDmiChassisAssetTag = "";
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81 | /* type 4 -- DMI processor information */
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82 | static const char *s_szDefDmiProcManufacturer = "GenuineIntel";
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83 | static const char *s_szDefDmiProcVersion = "Pentium(R) III";
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84 |
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85 | static char g_szHostDmiSystemProduct[64];
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86 | static char g_szHostDmiSystemVersion[64];
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87 |
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88 |
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89 | /*******************************************************************************
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90 | * Structures and Typedefs *
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91 | *******************************************************************************/
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92 | #pragma pack(1)
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93 |
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94 | typedef struct SMBIOSHDR
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95 | {
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96 | uint8_t au8Signature[4];
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97 | uint8_t u8Checksum;
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98 | uint8_t u8Eps;
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99 | uint8_t u8VersionMajor;
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100 | uint8_t u8VersionMinor;
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101 | uint16_t u16MaxStructureSize;
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102 | uint8_t u8EntryPointRevision;
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103 | uint8_t u8Pad[5];
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104 | } *SMBIOSHDRPTR;
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105 | AssertCompileSize(SMBIOSHDR, 16);
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106 |
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107 | typedef struct DMIMAINHDR
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108 | {
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109 | uint8_t au8Signature[5];
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110 | uint8_t u8Checksum;
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111 | uint16_t u16TablesLength;
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112 | uint32_t u32TableBase;
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113 | uint16_t u16TableEntries;
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114 | uint8_t u8TableVersion;
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115 | } *DMIMAINHDRPTR;
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116 | AssertCompileSize(DMIMAINHDR, 15);
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117 |
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118 | /** DMI header */
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119 | typedef struct DMIHDR
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120 | {
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121 | uint8_t u8Type;
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122 | uint8_t u8Length;
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123 | uint16_t u16Handle;
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124 | } *PDMIHDR;
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125 | AssertCompileSize(DMIHDR, 4);
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126 |
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127 | /** DMI BIOS information (Type 0) */
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128 | typedef struct DMIBIOSINF
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129 | {
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130 | DMIHDR header;
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131 | uint8_t u8Vendor;
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132 | uint8_t u8Version;
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133 | uint16_t u16Start;
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134 | uint8_t u8Release;
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135 | uint8_t u8ROMSize;
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136 | uint64_t u64Characteristics;
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137 | uint8_t u8CharacteristicsByte1;
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138 | uint8_t u8CharacteristicsByte2;
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139 | uint8_t u8ReleaseMajor;
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140 | uint8_t u8ReleaseMinor;
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141 | uint8_t u8FirmwareMajor;
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142 | uint8_t u8FirmwareMinor;
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143 | } *PDMIBIOSINF;
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144 | AssertCompileSize(DMIBIOSINF, 0x18);
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145 |
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146 | /** DMI system information (Type 1) */
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147 | typedef struct DMISYSTEMINF
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148 | {
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149 | DMIHDR header;
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150 | uint8_t u8Manufacturer;
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151 | uint8_t u8ProductName;
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152 | uint8_t u8Version;
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153 | uint8_t u8SerialNumber;
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154 | uint8_t au8Uuid[16];
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155 | uint8_t u8WakeupType;
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156 | uint8_t u8SKUNumber;
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157 | uint8_t u8Family;
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158 | } *PDMISYSTEMINF;
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159 | AssertCompileSize(DMISYSTEMINF, 0x1b);
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160 |
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161 | /** DMI board (or module) information (Type 2) */
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162 | typedef struct DMIBOARDINF
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163 | {
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164 | DMIHDR header;
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165 | uint8_t u8Manufacturer;
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166 | uint8_t u8Product;
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167 | uint8_t u8Version;
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168 | uint8_t u8SerialNumber;
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169 | uint8_t u8AssetTag;
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170 | uint8_t u8FeatureFlags;
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171 | uint8_t u8LocationInChass;
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172 | uint16_t u16ChassisHandle;
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173 | uint8_t u8BoardType;
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174 | uint8_t u8cObjectHandles;
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175 | } *PDMIBOARDINF;
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176 | AssertCompileSize(DMIBOARDINF, 0x0f);
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177 |
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178 | /** DMI system enclosure or chassis type (Type 3) */
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179 | typedef struct DMICHASSIS
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180 | {
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181 | DMIHDR header;
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182 | uint8_t u8Manufacturer;
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183 | uint8_t u8Type;
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184 | uint8_t u8Version;
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185 | uint8_t u8SerialNumber;
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186 | uint8_t u8AssetTag;
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187 | uint8_t u8BootupState;
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188 | uint8_t u8PowerSupplyState;
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189 | uint8_t u8ThermalState;
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190 | uint8_t u8SecurityStatus;
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191 | /* v2.3+, currently not supported */
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192 | uint32_t u32OEMdefined;
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193 | uint8_t u8Height;
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194 | uint8_t u8NumPowerChords;
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195 | uint8_t u8ContElems;
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196 | uint8_t u8ContElemRecLen;
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197 | } *PDMICHASSIS;
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198 | AssertCompileSize(DMICHASSIS, 0x15);
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199 |
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200 | /** DMI processor information (Type 4) */
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201 | typedef struct DMIPROCESSORINF
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202 | {
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203 | DMIHDR header;
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204 | uint8_t u8SocketDesignation;
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205 | uint8_t u8ProcessorType;
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206 | uint8_t u8ProcessorFamily;
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207 | uint8_t u8ProcessorManufacturer;
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208 | uint64_t u64ProcessorID;
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209 | uint8_t u8ProcessorVersion;
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210 | uint8_t u8Voltage;
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211 | uint16_t u16ExternalClock;
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212 | uint16_t u16MaxSpeed;
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213 | uint16_t u16CurrentSpeed;
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214 | uint8_t u8Status;
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215 | uint8_t u8ProcessorUpgrade;
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216 | /* v2.1+ */
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217 | uint16_t u16L1CacheHandle;
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218 | uint16_t u16L2CacheHandle;
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219 | uint16_t u16L3CacheHandle;
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220 | /* v2.3+ */
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221 | uint8_t u8SerialNumber;
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222 | uint8_t u8AssetTag;
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223 | uint8_t u8PartNumber;
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224 | /* v2.5+ */
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225 | uint8_t u8CoreCount;
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226 | uint8_t u8CoreEnabled;
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227 | uint8_t u8ThreadCount;
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228 | uint16_t u16ProcessorCharacteristics;
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229 | /* v2.6+ */
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230 | uint16_t u16ProcessorFamily2;
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231 | } *PDMIPROCESSORINF;
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232 | AssertCompileSize(DMIPROCESSORINF, 0x2a);
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233 |
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234 | /** DMI OEM strings (Type 11) */
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235 | typedef struct DMIOEMSTRINGS
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236 | {
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237 | DMIHDR header;
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238 | uint8_t u8Count;
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239 | uint8_t u8VBoxVersion;
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240 | uint8_t u8VBoxRevision;
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241 | } *PDMIOEMSTRINGS;
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242 | AssertCompileSize(DMIOEMSTRINGS, 0x7);
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243 |
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244 | /** DMI OEM-specific table (Type 128) */
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245 | typedef struct DMIOEMSPECIFIC
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246 | {
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247 | DMIHDR header;
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248 | uint32_t u32CpuFreqKHz;
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249 | } *PDMIOEMSPECIFIC;
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250 | AssertCompileSize(DMIOEMSPECIFIC, 0x8);
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251 |
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252 | /** Physical memory array (Type 16) */
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253 | typedef struct DMIRAMARRAY
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254 | {
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255 | DMIHDR header;
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256 | uint8_t u8Location;
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257 | uint8_t u8Use;
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258 | uint8_t u8MemErrorCorrection;
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259 | uint32_t u32MaxCapacity;
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260 | uint16_t u16MemErrorHandle;
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261 | uint16_t u16NumberOfMemDevices;
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262 | } *PDMIRAMARRAY;
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263 | AssertCompileSize(DMIRAMARRAY, 15);
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264 |
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265 | /** DMI Memory Device (Type 17) */
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266 | typedef struct DMIMEMORYDEV
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267 | {
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268 | DMIHDR header;
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269 | uint16_t u16PhysMemArrayHandle;
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270 | uint16_t u16MemErrHandle;
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271 | uint16_t u16TotalWidth;
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272 | uint16_t u16DataWidth;
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273 | uint16_t u16Size;
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274 | uint8_t u8FormFactor;
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275 | uint8_t u8DeviceSet;
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276 | uint8_t u8DeviceLocator;
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277 | uint8_t u8BankLocator;
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278 | uint8_t u8MemoryType;
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279 | uint16_t u16TypeDetail;
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280 | uint16_t u16Speed;
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281 | uint8_t u8Manufacturer;
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282 | uint8_t u8SerialNumber;
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283 | uint8_t u8AssetTag;
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284 | uint8_t u8PartNumber;
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285 | /* v2.6+ */
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286 | uint8_t u8Attributes;
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287 | } *PDMIMEMORYDEV;
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288 | AssertCompileSize(DMIMEMORYDEV, 28);
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289 |
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290 | /** MPS floating pointer structure */
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291 | typedef struct MPSFLOATPTR
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292 | {
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293 | uint8_t au8Signature[4];
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294 | uint32_t u32MPSAddr;
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295 | uint8_t u8Length;
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296 | uint8_t u8SpecRev;
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297 | uint8_t u8Checksum;
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298 | uint8_t au8Feature[5];
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299 | } *PMPSFLOATPTR;
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300 | AssertCompileSize(MPSFLOATPTR, 16);
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301 |
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302 | /** MPS config table header */
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303 | typedef struct MPSCFGTBLHEADER
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304 | {
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305 | uint8_t au8Signature[4];
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306 | uint16_t u16Length;
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307 | uint8_t u8SpecRev;
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308 | uint8_t u8Checksum;
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309 | uint8_t au8OemId[8];
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310 | uint8_t au8ProductId[12];
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311 | uint32_t u32OemTablePtr;
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312 | uint16_t u16OemTableSize;
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313 | uint16_t u16EntryCount;
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314 | uint32_t u32AddrLocalApic;
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315 | uint16_t u16ExtTableLength;
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316 | uint8_t u8ExtTableChecksum;
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317 | uint8_t u8Reserved;
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318 | } *PMPSCFGTBLHEADER;
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319 | AssertCompileSize(MPSCFGTBLHEADER, 0x2c);
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320 |
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321 | /** MPS processor entry */
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322 | typedef struct MPSPROCENTRY
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323 | {
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324 | uint8_t u8EntryType;
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325 | uint8_t u8LocalApicId;
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326 | uint8_t u8LocalApicVersion;
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327 | uint8_t u8CPUFlags;
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328 | uint32_t u32CPUSignature;
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329 | uint32_t u32CPUFeatureFlags;
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330 | uint32_t u32Reserved[2];
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331 | } *PMPSPROCENTRY;
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332 | AssertCompileSize(MPSPROCENTRY, 20);
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333 |
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334 | /** MPS bus entry */
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335 | typedef struct MPSBUSENTRY
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336 | {
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337 | uint8_t u8EntryType;
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338 | uint8_t u8BusId;
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339 | uint8_t au8BusTypeStr[6];
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340 | } *PMPSBUSENTRY;
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341 | AssertCompileSize(MPSBUSENTRY, 8);
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342 |
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343 | /** MPS I/O-APIC entry */
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344 | typedef struct MPSIOAPICENTRY
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345 | {
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346 | uint8_t u8EntryType;
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347 | uint8_t u8Id;
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348 | uint8_t u8Version;
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349 | uint8_t u8Flags;
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350 | uint32_t u32Addr;
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351 | } *PMPSIOAPICENTRY;
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352 | AssertCompileSize(MPSIOAPICENTRY, 8);
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353 |
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354 | /** MPS I/O-Interrupt entry */
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355 | typedef struct MPSIOINTERRUPTENTRY
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356 | {
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357 | uint8_t u8EntryType;
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358 | uint8_t u8Type;
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359 | uint16_t u16Flags;
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360 | uint8_t u8SrcBusId;
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361 | uint8_t u8SrcBusIrq;
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362 | uint8_t u8DstIOAPICId;
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363 | uint8_t u8DstIOAPICInt;
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364 | } *PMPSIOIRQENTRY;
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365 | AssertCompileSize(MPSIOINTERRUPTENTRY, 8);
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366 |
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367 | #pragma pack()
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368 |
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369 |
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370 | /**
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371 | * Calculate a simple checksum for the MPS table.
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372 | *
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373 | * @param data data
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374 | * @param len size of data
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375 | */
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376 | static uint8_t fwCommonChecksum(const uint8_t * const au8Data, uint32_t u32Length)
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377 | {
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378 | uint8_t u8Sum = 0;
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379 | for (size_t i = 0; i < u32Length; ++i)
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380 | u8Sum += au8Data[i];
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381 | return -u8Sum;
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382 | }
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383 |
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384 | #if 0 /* unused */
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385 | static bool fwCommonChecksumOk(const uint8_t * const au8Data, uint32_t u32Length)
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386 | {
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387 | uint8_t u8Sum = 0;
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388 | for (size_t i = 0; i < u32Length; i++)
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389 | u8Sum += au8Data[i];
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390 | return (u8Sum == 0);
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391 | }
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392 | #endif
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393 |
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394 | /**
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395 | * Try fetch the DMI strings from the system.
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396 | */
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397 | static void fwCommonUseHostDMIStrings(void)
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398 | {
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399 | int rc;
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400 |
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401 | rc = RTSystemQueryDmiString(RTSYSDMISTR_PRODUCT_NAME,
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402 | g_szHostDmiSystemProduct, sizeof(g_szHostDmiSystemProduct));
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403 | if (RT_SUCCESS(rc))
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404 | {
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405 | s_szDefDmiSystemProduct = g_szHostDmiSystemProduct;
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406 | LogRel(("DMI: Using DmiSystemProduct from host: %s\n", g_szHostDmiSystemProduct));
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407 | }
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408 |
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409 | rc = RTSystemQueryDmiString(RTSYSDMISTR_PRODUCT_VERSION,
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410 | g_szHostDmiSystemVersion, sizeof(g_szHostDmiSystemVersion));
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411 | if (RT_SUCCESS(rc))
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412 | {
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413 | s_szDefDmiSystemVersion = g_szHostDmiSystemVersion;
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414 | LogRel(("DMI: Using DmiSystemVersion from host: %s\n", g_szHostDmiSystemVersion));
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415 | }
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416 | }
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417 |
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418 | /**
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419 | * Construct the DMI table.
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420 | *
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421 | * @returns VBox status code.
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422 | * @param pDevIns The device instance.
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423 | * @param pTable Where to create the DMI table.
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424 | * @param cbMax The maximum size of the DMI table.
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425 | * @param pUuid Pointer to the UUID to use if the DmiUuid
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426 | * configuration string isn't present.
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427 | * @param pCfg The handle to our config node.
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428 | * @param cCpus Number of VCPUs.
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429 | * @param pcbDmiTables Size of DMI data in bytes.
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430 | * @param pcNumDmiTables Number of DMI tables.
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431 | */
|
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432 | int FwCommonPlantDMITable(PPDMDEVINS pDevIns, uint8_t *pTable, unsigned cbMax, PCRTUUID pUuid, PCFGMNODE pCfg, uint16_t cCpus, uint16_t *pcbDmiTables, uint16_t *pcNumDmiTables)
|
---|
433 | {
|
---|
434 | #define CHECKSIZE(cbWant) \
|
---|
435 | { \
|
---|
436 | size_t cbNeed = (size_t)(pszStr + cbWant - (char *)pTable) + 5; /* +1 for strtab terminator +4 for end-of-table entry */ \
|
---|
437 | if (cbNeed > cbMax) \
|
---|
438 | { \
|
---|
439 | if (fHideErrors) \
|
---|
440 | { \
|
---|
441 | LogRel(("One of the DMI strings is too long -- using default DMI data!\n")); \
|
---|
442 | continue; \
|
---|
443 | } \
|
---|
444 | return PDMDevHlpVMSetError(pDevIns, VERR_TOO_MUCH_DATA, RT_SRC_POS, \
|
---|
445 | N_("One of the DMI strings is too long. Check all bios/Dmi* configuration entries. At least %zu bytes are needed but there is no space for more than %d bytes"), cbNeed, cbMax); \
|
---|
446 | } \
|
---|
447 | }
|
---|
448 |
|
---|
449 | #define READCFGSTRDEF(variable, name, default_value) \
|
---|
450 | { \
|
---|
451 | if (fForceDefault) \
|
---|
452 | pszTmp = default_value; \
|
---|
453 | else \
|
---|
454 | { \
|
---|
455 | rc = CFGMR3QueryStringDef(pCfg, name, szBuf, sizeof(szBuf), default_value); \
|
---|
456 | if (RT_FAILURE(rc)) \
|
---|
457 | { \
|
---|
458 | if (fHideErrors) \
|
---|
459 | { \
|
---|
460 | LogRel(("Configuration error: Querying \"" name "\" as a string failed -- using default DMI data!\n")); \
|
---|
461 | continue; \
|
---|
462 | } \
|
---|
463 | return PDMDevHlpVMSetError(pDevIns, rc, RT_SRC_POS, \
|
---|
464 | N_("Configuration error: Querying \"" name "\" as a string failed")); \
|
---|
465 | } \
|
---|
466 | else if (!strcmp(szBuf, "<EMPTY>")) \
|
---|
467 | pszTmp = ""; \
|
---|
468 | else \
|
---|
469 | pszTmp = szBuf; \
|
---|
470 | } \
|
---|
471 | if (!pszTmp[0]) \
|
---|
472 | variable = 0; /* empty string */ \
|
---|
473 | else \
|
---|
474 | { \
|
---|
475 | variable = iStrNr++; \
|
---|
476 | size_t cStr = strlen(pszTmp) + 1; \
|
---|
477 | CHECKSIZE(cStr); \
|
---|
478 | memcpy(pszStr, pszTmp, cStr); \
|
---|
479 | pszStr += cStr ; \
|
---|
480 | } \
|
---|
481 | }
|
---|
482 |
|
---|
483 | #define READCFGSTR(variable, name) \
|
---|
484 | READCFGSTRDEF(variable, # name, s_szDef ## name)
|
---|
485 |
|
---|
486 | #define READCFGINT(variable, name) \
|
---|
487 | { \
|
---|
488 | if (fForceDefault) \
|
---|
489 | variable = s_iDef ## name; \
|
---|
490 | else \
|
---|
491 | { \
|
---|
492 | rc = CFGMR3QueryS32Def(pCfg, # name, & variable, s_iDef ## name); \
|
---|
493 | if (RT_FAILURE(rc)) \
|
---|
494 | { \
|
---|
495 | if (fHideErrors) \
|
---|
496 | { \
|
---|
497 | LogRel(("Configuration error: Querying \"" # name "\" as an int failed -- using default DMI data!\n")); \
|
---|
498 | continue; \
|
---|
499 | } \
|
---|
500 | return PDMDevHlpVMSetError(pDevIns, rc, RT_SRC_POS, \
|
---|
501 | N_("Configuration error: Querying \"" # name "\" as an int failed")); \
|
---|
502 | } \
|
---|
503 | } \
|
---|
504 | }
|
---|
505 |
|
---|
506 | #define START_STRUCT(tbl) \
|
---|
507 | pszStr = (char *)(tbl + 1); \
|
---|
508 | iStrNr = 1;
|
---|
509 |
|
---|
510 | #define TERM_STRUCT \
|
---|
511 | { \
|
---|
512 | *pszStr++ = '\0'; /* terminate set of text strings */ \
|
---|
513 | if (iStrNr == 1) \
|
---|
514 | *pszStr++ = '\0'; /* terminate a structure without strings */ \
|
---|
515 | }
|
---|
516 |
|
---|
517 | bool fForceDefault = false;
|
---|
518 | #ifdef VBOX_BIOS_DMI_FALLBACK
|
---|
519 | /*
|
---|
520 | * There will be two passes. If an error occurs during the first pass, a
|
---|
521 | * message will be written to the release log and we fall back to default
|
---|
522 | * DMI data and start a second pass.
|
---|
523 | */
|
---|
524 | bool fHideErrors = true;
|
---|
525 | #else
|
---|
526 | /*
|
---|
527 | * There will be one pass, every error is fatal and will prevent the VM
|
---|
528 | * from starting.
|
---|
529 | */
|
---|
530 | bool fHideErrors = false;
|
---|
531 | #endif
|
---|
532 |
|
---|
533 | uint8_t fDmiUseHostInfo;
|
---|
534 | int rc = CFGMR3QueryU8Def(pCfg, "DmiUseHostInfo", &fDmiUseHostInfo, 0);
|
---|
535 | if (RT_FAILURE (rc))
|
---|
536 | return PDMDEV_SET_ERROR(pDevIns, rc,
|
---|
537 | N_("Configuration error: Failed to read \"DmiUseHostInfo\""));
|
---|
538 |
|
---|
539 | /* Sync up with host default DMI values */
|
---|
540 | if (fDmiUseHostInfo)
|
---|
541 | fwCommonUseHostDMIStrings();
|
---|
542 |
|
---|
543 | uint8_t fDmiExposeMemoryTable;
|
---|
544 | rc = CFGMR3QueryU8Def(pCfg, "DmiExposeMemoryTable", &fDmiExposeMemoryTable, 0);
|
---|
545 | if (RT_FAILURE (rc))
|
---|
546 | return PDMDEV_SET_ERROR(pDevIns, rc,
|
---|
547 | N_("Configuration error: Failed to read \"DmiExposeMemoryTable\""));
|
---|
548 | uint8_t fDmiExposeProcessorInf;
|
---|
549 | rc = CFGMR3QueryU8Def(pCfg, "DmiExposeProcInf", &fDmiExposeProcessorInf, 0);
|
---|
550 | if (RT_FAILURE (rc))
|
---|
551 | return PDMDEV_SET_ERROR(pDevIns, rc,
|
---|
552 | N_("Configuration error: Failed to read \"DmiExposeProcInf\""));
|
---|
553 |
|
---|
554 | for (;; fForceDefault = true, fHideErrors = false)
|
---|
555 | {
|
---|
556 | int iStrNr;
|
---|
557 | char szBuf[256];
|
---|
558 | char *pszStr = (char *)pTable;
|
---|
559 | char szDmiSystemUuid[64];
|
---|
560 | char *pszDmiSystemUuid;
|
---|
561 | const char *pszTmp;
|
---|
562 |
|
---|
563 | if (fForceDefault)
|
---|
564 | pszDmiSystemUuid = NULL;
|
---|
565 | else
|
---|
566 | {
|
---|
567 | rc = CFGMR3QueryString(pCfg, "DmiSystemUuid", szDmiSystemUuid, sizeof(szDmiSystemUuid));
|
---|
568 | if (rc == VERR_CFGM_VALUE_NOT_FOUND)
|
---|
569 | pszDmiSystemUuid = NULL;
|
---|
570 | else if (RT_FAILURE(rc))
|
---|
571 | {
|
---|
572 | if (fHideErrors)
|
---|
573 | {
|
---|
574 | LogRel(("Configuration error: Querying \"DmiSystemUuid\" as a string failed, using default DMI data\n"));
|
---|
575 | continue;
|
---|
576 | }
|
---|
577 | return PDMDevHlpVMSetError(pDevIns, rc, RT_SRC_POS,
|
---|
578 | N_("Configuration error: Querying \"DmiSystemUuid\" as a string failed"));
|
---|
579 | }
|
---|
580 | else
|
---|
581 | pszDmiSystemUuid = szDmiSystemUuid;
|
---|
582 | }
|
---|
583 |
|
---|
584 | /*********************************
|
---|
585 | * DMI BIOS information (Type 0) *
|
---|
586 | *********************************/
|
---|
587 | PDMIBIOSINF pBIOSInf = (PDMIBIOSINF)pszStr;
|
---|
588 | CHECKSIZE(sizeof(*pBIOSInf));
|
---|
589 |
|
---|
590 | pszStr = (char *)&pBIOSInf->u8ReleaseMajor;
|
---|
591 | pBIOSInf->header.u8Length = RT_OFFSETOF(DMIBIOSINF, u8ReleaseMajor);
|
---|
592 |
|
---|
593 | /* don't set these fields by default for legacy compatibility */
|
---|
594 | int iDmiBIOSReleaseMajor, iDmiBIOSReleaseMinor;
|
---|
595 | READCFGINT(iDmiBIOSReleaseMajor, DmiBIOSReleaseMajor);
|
---|
596 | READCFGINT(iDmiBIOSReleaseMinor, DmiBIOSReleaseMinor);
|
---|
597 | if (iDmiBIOSReleaseMajor != 0 || iDmiBIOSReleaseMinor != 0)
|
---|
598 | {
|
---|
599 | pszStr = (char *)&pBIOSInf->u8FirmwareMajor;
|
---|
600 | pBIOSInf->header.u8Length = RT_OFFSETOF(DMIBIOSINF, u8FirmwareMajor);
|
---|
601 | pBIOSInf->u8ReleaseMajor = iDmiBIOSReleaseMajor;
|
---|
602 | pBIOSInf->u8ReleaseMinor = iDmiBIOSReleaseMinor;
|
---|
603 |
|
---|
604 | int iDmiBIOSFirmwareMajor, iDmiBIOSFirmwareMinor;
|
---|
605 | READCFGINT(iDmiBIOSFirmwareMajor, DmiBIOSFirmwareMajor);
|
---|
606 | READCFGINT(iDmiBIOSFirmwareMinor, DmiBIOSFirmwareMinor);
|
---|
607 | if (iDmiBIOSFirmwareMajor != 0 || iDmiBIOSFirmwareMinor != 0)
|
---|
608 | {
|
---|
609 | pszStr = (char *)(pBIOSInf + 1);
|
---|
610 | pBIOSInf->header.u8Length = sizeof(DMIBIOSINF);
|
---|
611 | pBIOSInf->u8FirmwareMajor = iDmiBIOSFirmwareMajor;
|
---|
612 | pBIOSInf->u8FirmwareMinor = iDmiBIOSFirmwareMinor;
|
---|
613 | }
|
---|
614 | }
|
---|
615 |
|
---|
616 | iStrNr = 1;
|
---|
617 | pBIOSInf->header.u8Type = 0; /* BIOS Information */
|
---|
618 | pBIOSInf->header.u16Handle = 0x0000;
|
---|
619 | READCFGSTR(pBIOSInf->u8Vendor, DmiBIOSVendor);
|
---|
620 | READCFGSTR(pBIOSInf->u8Version, DmiBIOSVersion);
|
---|
621 | pBIOSInf->u16Start = 0xE000;
|
---|
622 | READCFGSTR(pBIOSInf->u8Release, DmiBIOSReleaseDate);
|
---|
623 | pBIOSInf->u8ROMSize = 1; /* 128K */
|
---|
624 | pBIOSInf->u64Characteristics = RT_BIT(4) /* ISA is supported */
|
---|
625 | | RT_BIT(7) /* PCI is supported */
|
---|
626 | | RT_BIT(15) /* Boot from CD is supported */
|
---|
627 | | RT_BIT(16) /* Selectable Boot is supported */
|
---|
628 | | RT_BIT(27) /* Int 9h, 8042 Keyboard services supported */
|
---|
629 | | RT_BIT(30) /* Int 10h, CGA/Mono Video Services supported */
|
---|
630 | /* any more?? */
|
---|
631 | ;
|
---|
632 | pBIOSInf->u8CharacteristicsByte1 = RT_BIT(0) /* ACPI is supported */
|
---|
633 | /* any more?? */
|
---|
634 | ;
|
---|
635 | pBIOSInf->u8CharacteristicsByte2 = 0
|
---|
636 | /* any more?? */
|
---|
637 | ;
|
---|
638 | TERM_STRUCT;
|
---|
639 |
|
---|
640 | /***********************************
|
---|
641 | * DMI system information (Type 1) *
|
---|
642 | ***********************************/
|
---|
643 | PDMISYSTEMINF pSystemInf = (PDMISYSTEMINF)pszStr;
|
---|
644 | CHECKSIZE(sizeof(*pSystemInf));
|
---|
645 | START_STRUCT(pSystemInf);
|
---|
646 | pSystemInf->header.u8Type = 1; /* System Information */
|
---|
647 | pSystemInf->header.u8Length = sizeof(*pSystemInf);
|
---|
648 | pSystemInf->header.u16Handle = 0x0001;
|
---|
649 | READCFGSTR(pSystemInf->u8Manufacturer, DmiSystemVendor);
|
---|
650 | READCFGSTR(pSystemInf->u8ProductName, DmiSystemProduct);
|
---|
651 | READCFGSTR(pSystemInf->u8Version, DmiSystemVersion);
|
---|
652 | READCFGSTR(pSystemInf->u8SerialNumber, DmiSystemSerial);
|
---|
653 |
|
---|
654 | RTUUID uuid;
|
---|
655 | if (pszDmiSystemUuid)
|
---|
656 | {
|
---|
657 | rc = RTUuidFromStr(&uuid, pszDmiSystemUuid);
|
---|
658 | if (RT_FAILURE(rc))
|
---|
659 | {
|
---|
660 | if (fHideErrors)
|
---|
661 | {
|
---|
662 | LogRel(("Configuration error: Invalid UUID for DMI tables specified, using default DMI data\n"));
|
---|
663 | continue;
|
---|
664 | }
|
---|
665 | return PDMDevHlpVMSetError(pDevIns, rc, RT_SRC_POS,
|
---|
666 | N_("Configuration error: Invalid UUID for DMI tables specified"));
|
---|
667 | }
|
---|
668 | uuid.Gen.u32TimeLow = RT_H2BE_U32(uuid.Gen.u32TimeLow);
|
---|
669 | uuid.Gen.u16TimeMid = RT_H2BE_U16(uuid.Gen.u16TimeMid);
|
---|
670 | uuid.Gen.u16TimeHiAndVersion = RT_H2BE_U16(uuid.Gen.u16TimeHiAndVersion);
|
---|
671 | pUuid = &uuid;
|
---|
672 | }
|
---|
673 | memcpy(pSystemInf->au8Uuid, pUuid, sizeof(RTUUID));
|
---|
674 |
|
---|
675 | pSystemInf->u8WakeupType = 6; /* Power Switch */
|
---|
676 | READCFGSTR(pSystemInf->u8SKUNumber, DmiSystemSKU);
|
---|
677 | READCFGSTR(pSystemInf->u8Family, DmiSystemFamily);
|
---|
678 | TERM_STRUCT;
|
---|
679 |
|
---|
680 | /**********************************
|
---|
681 | * DMI board information (Type 2) *
|
---|
682 | **********************************/
|
---|
683 | PDMIBOARDINF pBoardInf = (PDMIBOARDINF)pszStr;
|
---|
684 | CHECKSIZE(sizeof(*pBoardInf));
|
---|
685 | START_STRUCT(pBoardInf);
|
---|
686 | int iDmiBoardBoardType;
|
---|
687 | pBoardInf->header.u8Type = 2; /* Board Information */
|
---|
688 | pBoardInf->header.u8Length = sizeof(*pBoardInf);
|
---|
689 | pBoardInf->header.u16Handle = 0x0008;
|
---|
690 | READCFGSTR(pBoardInf->u8Manufacturer, DmiBoardVendor);
|
---|
691 | READCFGSTR(pBoardInf->u8Product, DmiBoardProduct);
|
---|
692 | READCFGSTR(pBoardInf->u8Version, DmiBoardVersion);
|
---|
693 | READCFGSTR(pBoardInf->u8SerialNumber, DmiBoardSerial);
|
---|
694 | READCFGSTR(pBoardInf->u8AssetTag, DmiBoardAssetTag);
|
---|
695 | pBoardInf->u8FeatureFlags = RT_BIT(0) /* hosting board, e.g. motherboard */
|
---|
696 | ;
|
---|
697 | READCFGSTR(pBoardInf->u8LocationInChass, DmiBoardLocInChass);
|
---|
698 | pBoardInf->u16ChassisHandle = 0x0003; /* see type 3 */
|
---|
699 | READCFGINT(iDmiBoardBoardType, DmiBoardBoardType);
|
---|
700 | pBoardInf->u8BoardType = iDmiBoardBoardType;
|
---|
701 | pBoardInf->u8cObjectHandles = 0;
|
---|
702 |
|
---|
703 | TERM_STRUCT;
|
---|
704 |
|
---|
705 | /********************************************
|
---|
706 | * DMI System Enclosure or Chassis (Type 3) *
|
---|
707 | ********************************************/
|
---|
708 | PDMICHASSIS pChassis = (PDMICHASSIS)pszStr;
|
---|
709 | CHECKSIZE(sizeof(*pChassis));
|
---|
710 | pszStr = (char*)&pChassis->u32OEMdefined;
|
---|
711 | iStrNr = 1;
|
---|
712 | #ifdef VBOX_WITH_DMI_CHASSIS
|
---|
713 | pChassis->header.u8Type = 3; /* System Enclosure or Chassis */
|
---|
714 | #else
|
---|
715 | pChassis->header.u8Type = 0x7e; /* inactive */
|
---|
716 | #endif
|
---|
717 | pChassis->header.u8Length = RT_OFFSETOF(DMICHASSIS, u32OEMdefined);
|
---|
718 | pChassis->header.u16Handle = 0x0003;
|
---|
719 | READCFGSTR(pChassis->u8Manufacturer, DmiChassisVendor);
|
---|
720 | int iDmiChassisType;
|
---|
721 | READCFGINT(iDmiChassisType, DmiChassisType);
|
---|
722 | pChassis->u8Type = iDmiChassisType;
|
---|
723 | READCFGSTR(pChassis->u8Version, DmiChassisVersion);
|
---|
724 | READCFGSTR(pChassis->u8SerialNumber, DmiChassisSerial);
|
---|
725 | READCFGSTR(pChassis->u8AssetTag, DmiChassisAssetTag);
|
---|
726 | pChassis->u8BootupState = 0x03; /* safe */
|
---|
727 | pChassis->u8PowerSupplyState = 0x03; /* safe */
|
---|
728 | pChassis->u8ThermalState = 0x03; /* safe */
|
---|
729 | pChassis->u8SecurityStatus = 0x03; /* none XXX */
|
---|
730 | # if 0
|
---|
731 | /* v2.3+, currently not supported */
|
---|
732 | pChassis->u32OEMdefined = 0;
|
---|
733 | pChassis->u8Height = 0; /* unspecified */
|
---|
734 | pChassis->u8NumPowerChords = 0; /* unspecified */
|
---|
735 | pChassis->u8ContElems = 0; /* no contained elements */
|
---|
736 | pChassis->u8ContElemRecLen = 0; /* no contained elements */
|
---|
737 | # endif
|
---|
738 | TERM_STRUCT;
|
---|
739 |
|
---|
740 | /**************************************
|
---|
741 | * DMI Processor Information (Type 4) *
|
---|
742 | **************************************/
|
---|
743 |
|
---|
744 | /*
|
---|
745 | * This is just a dummy processor. Should we expose the real guest CPU features
|
---|
746 | * here? Accessing this information at this point is difficult.
|
---|
747 | */
|
---|
748 | char szSocket[32];
|
---|
749 | PDMIPROCESSORINF pProcessorInf = (PDMIPROCESSORINF)pszStr;
|
---|
750 | CHECKSIZE(sizeof(*pProcessorInf));
|
---|
751 | START_STRUCT(pProcessorInf);
|
---|
752 | if (fDmiExposeProcessorInf)
|
---|
753 | pProcessorInf->header.u8Type = 4; /* Processor Information */
|
---|
754 | else
|
---|
755 | pProcessorInf->header.u8Type = 126; /* inactive structure */
|
---|
756 | pProcessorInf->header.u8Length = sizeof(*pProcessorInf);
|
---|
757 | pProcessorInf->header.u16Handle = 0x0007;
|
---|
758 | RTStrPrintf(szSocket, sizeof(szSocket), "Socket #%u", 0);
|
---|
759 | pProcessorInf->u8SocketDesignation = iStrNr++;
|
---|
760 | {
|
---|
761 | size_t cStr = strlen(szSocket) + 1;
|
---|
762 | CHECKSIZE(cStr);
|
---|
763 | memcpy(pszStr, szSocket, cStr);
|
---|
764 | pszStr += cStr;
|
---|
765 | }
|
---|
766 | pProcessorInf->u8ProcessorType = 0x03; /* Central Processor */
|
---|
767 | pProcessorInf->u8ProcessorFamily = 0xB1; /* Pentium III with Intel SpeedStep(TM) */
|
---|
768 | READCFGSTR(pProcessorInf->u8ProcessorManufacturer, DmiProcManufacturer);
|
---|
769 |
|
---|
770 | pProcessorInf->u64ProcessorID = UINT64_C(0x0FEBFBFF00010676);
|
---|
771 | /* Ext Family ID = 0
|
---|
772 | * Ext Model ID = 2
|
---|
773 | * Processor Type = 0
|
---|
774 | * Family ID = 6
|
---|
775 | * Model = 7
|
---|
776 | * Stepping = 6
|
---|
777 | * Features: FPU, VME, DE, PSE, TSC, MSR, PAE, MCE, CX8,
|
---|
778 | * APIC, SEP, MTRR, PGE, MCA, CMOV, PAT, PSE-36,
|
---|
779 | * CFLSH, DS, ACPI, MMX, FXSR, SSE, SSE2, SS */
|
---|
780 | READCFGSTR(pProcessorInf->u8ProcessorVersion, DmiProcVersion);
|
---|
781 | pProcessorInf->u8Voltage = 0x02; /* 3.3V */
|
---|
782 | pProcessorInf->u16ExternalClock = 0x00; /* unknown */
|
---|
783 | pProcessorInf->u16MaxSpeed = 3000; /* 3GHz */
|
---|
784 | pProcessorInf->u16CurrentSpeed = 3000; /* 3GHz */
|
---|
785 | pProcessorInf->u8Status = RT_BIT(6) /* CPU socket populated */
|
---|
786 | | RT_BIT(0) /* CPU enabled */
|
---|
787 | ;
|
---|
788 | pProcessorInf->u8ProcessorUpgrade = 0x04; /* ZIF Socket */
|
---|
789 | pProcessorInf->u16L1CacheHandle = 0xFFFF; /* not specified */
|
---|
790 | pProcessorInf->u16L2CacheHandle = 0xFFFF; /* not specified */
|
---|
791 | pProcessorInf->u16L3CacheHandle = 0xFFFF; /* not specified */
|
---|
792 | pProcessorInf->u8SerialNumber = 0; /* not specified */
|
---|
793 | pProcessorInf->u8AssetTag = 0; /* not specified */
|
---|
794 | pProcessorInf->u8PartNumber = 0; /* not specified */
|
---|
795 | pProcessorInf->u8CoreCount = cCpus; /* */
|
---|
796 | pProcessorInf->u8CoreEnabled = cCpus;
|
---|
797 | pProcessorInf->u8ThreadCount = 1;
|
---|
798 | pProcessorInf->u16ProcessorCharacteristics
|
---|
799 | = RT_BIT(2); /* 64-bit capable */
|
---|
800 | pProcessorInf->u16ProcessorFamily2 = 0;
|
---|
801 | TERM_STRUCT;
|
---|
802 |
|
---|
803 | /***************************************
|
---|
804 | * DMI Physical Memory Array (Type 16) *
|
---|
805 | ***************************************/
|
---|
806 | uint64_t u64RamSize;
|
---|
807 | rc = CFGMR3QueryU64(pCfg, "RamSize", &u64RamSize);
|
---|
808 | if (RT_FAILURE (rc))
|
---|
809 | return PDMDEV_SET_ERROR(pDevIns, rc,
|
---|
810 | N_("Configuration error: Failed to read \"RamSize\""));
|
---|
811 |
|
---|
812 | PDMIRAMARRAY pMemArray = (PDMIRAMARRAY)pszStr;
|
---|
813 | CHECKSIZE(sizeof(*pMemArray));
|
---|
814 | START_STRUCT(pMemArray);
|
---|
815 | if (fDmiExposeMemoryTable)
|
---|
816 | pMemArray->header.u8Type = 16; /* Physical Memory Array */
|
---|
817 | else
|
---|
818 | pMemArray->header.u8Type = 126; /* inactive structure */
|
---|
819 | pMemArray->header.u8Length = sizeof(*pMemArray);
|
---|
820 | pMemArray->header.u16Handle = 0x0005;
|
---|
821 | pMemArray->u8Location = 0x03; /* Motherboard */
|
---|
822 | pMemArray->u8Use = 0x03; /* System memory */
|
---|
823 | pMemArray->u8MemErrorCorrection = 0x01; /* Other */
|
---|
824 | pMemArray->u32MaxCapacity = (uint32_t)(u64RamSize / _1K); /* RAM size in K */
|
---|
825 | pMemArray->u16MemErrorHandle = 0xfffe; /* No error info structure */
|
---|
826 | pMemArray->u16NumberOfMemDevices = 1;
|
---|
827 | TERM_STRUCT;
|
---|
828 |
|
---|
829 | /***************************************
|
---|
830 | * DMI Memory Device (Type 17) *
|
---|
831 | ***************************************/
|
---|
832 | PDMIMEMORYDEV pMemDev = (PDMIMEMORYDEV)pszStr;
|
---|
833 | CHECKSIZE(sizeof(*pMemDev));
|
---|
834 | START_STRUCT(pMemDev);
|
---|
835 | if (fDmiExposeMemoryTable)
|
---|
836 | pMemDev->header.u8Type = 17; /* Memory Device */
|
---|
837 | else
|
---|
838 | pMemDev->header.u8Type = 126; /* inactive structure */
|
---|
839 | pMemDev->header.u8Length = sizeof(*pMemDev);
|
---|
840 | pMemDev->header.u16Handle = 0x0006;
|
---|
841 | pMemDev->u16PhysMemArrayHandle = 0x0005; /* handle of array we belong to */
|
---|
842 | pMemDev->u16MemErrHandle = 0xfffe; /* system doesn't provide this information */
|
---|
843 | pMemDev->u16TotalWidth = 0xffff; /* Unknown */
|
---|
844 | pMemDev->u16DataWidth = 0xffff; /* Unknown */
|
---|
845 | int16_t u16RamSizeM = (uint16_t)(u64RamSize / _1M);
|
---|
846 | if (u16RamSizeM == 0)
|
---|
847 | u16RamSizeM = 0x400; /* 1G */
|
---|
848 | pMemDev->u16Size = u16RamSizeM; /* RAM size */
|
---|
849 | pMemDev->u8FormFactor = 0x09; /* DIMM */
|
---|
850 | pMemDev->u8DeviceSet = 0x00; /* Not part of a device set */
|
---|
851 | READCFGSTRDEF(pMemDev->u8DeviceLocator, " ", "DIMM 0");
|
---|
852 | READCFGSTRDEF(pMemDev->u8BankLocator, " ", "Bank 0");
|
---|
853 | pMemDev->u8MemoryType = 0x03; /* DRAM */
|
---|
854 | pMemDev->u16TypeDetail = 0; /* Nothing special */
|
---|
855 | pMemDev->u16Speed = 1600; /* Unknown, shall be speed in MHz */
|
---|
856 | READCFGSTR(pMemDev->u8Manufacturer, DmiSystemVendor);
|
---|
857 | READCFGSTRDEF(pMemDev->u8SerialNumber, " ", "00000000");
|
---|
858 | READCFGSTRDEF(pMemDev->u8AssetTag, " ", "00000000");
|
---|
859 | READCFGSTRDEF(pMemDev->u8PartNumber, " ", "00000000");
|
---|
860 | pMemDev->u8Attributes = 0; /* Unknown */
|
---|
861 | TERM_STRUCT;
|
---|
862 |
|
---|
863 | /*****************************
|
---|
864 | * DMI OEM strings (Type 11) *
|
---|
865 | *****************************/
|
---|
866 | PDMIOEMSTRINGS pOEMStrings = (PDMIOEMSTRINGS)pszStr;
|
---|
867 | CHECKSIZE(sizeof(*pOEMStrings));
|
---|
868 | START_STRUCT(pOEMStrings);
|
---|
869 | #ifdef VBOX_WITH_DMI_OEMSTRINGS
|
---|
870 | pOEMStrings->header.u8Type = 0xb; /* OEM Strings */
|
---|
871 | #else
|
---|
872 | pOEMStrings->header.u8Type = 126; /* inactive structure */
|
---|
873 | #endif
|
---|
874 | pOEMStrings->header.u8Length = sizeof(*pOEMStrings);
|
---|
875 | pOEMStrings->header.u16Handle = 0x0002;
|
---|
876 | pOEMStrings->u8Count = 2;
|
---|
877 |
|
---|
878 | char szTmp[64];
|
---|
879 | RTStrPrintf(szTmp, sizeof(szTmp), "vboxVer_%u.%u.%u",
|
---|
880 | RTBldCfgVersionMajor(), RTBldCfgVersionMinor(), RTBldCfgVersionBuild());
|
---|
881 | READCFGSTRDEF(pOEMStrings->u8VBoxVersion, "DmiOEMVBoxVer", szTmp);
|
---|
882 | RTStrPrintf(szTmp, sizeof(szTmp), "vboxRev_%u", RTBldCfgRevision());
|
---|
883 | READCFGSTRDEF(pOEMStrings->u8VBoxRevision, "DmiOEMVBoxRev", szTmp);
|
---|
884 | TERM_STRUCT;
|
---|
885 |
|
---|
886 | /*************************************
|
---|
887 | * DMI OEM specific table (Type 128) *
|
---|
888 | ************************************/
|
---|
889 | PDMIOEMSPECIFIC pOEMSpecific = (PDMIOEMSPECIFIC)pszStr;
|
---|
890 | CHECKSIZE(sizeof(*pOEMSpecific));
|
---|
891 | START_STRUCT(pOEMSpecific);
|
---|
892 | pOEMSpecific->header.u8Type = 0x80; /* OEM specific */
|
---|
893 | pOEMSpecific->header.u8Length = sizeof(*pOEMSpecific);
|
---|
894 | pOEMSpecific->header.u16Handle = 0x0008; /* Just next free handle */
|
---|
895 | pOEMSpecific->u32CpuFreqKHz = RT_H2LE_U32((uint32_t)((uint64_t)TMCpuTicksPerSecond(PDMDevHlpGetVM(pDevIns)) / 1000));
|
---|
896 | TERM_STRUCT;
|
---|
897 |
|
---|
898 | /* End-of-table marker - includes padding to account for fixed table size. */
|
---|
899 | PDMIHDR pEndOfTable = (PDMIHDR)pszStr;
|
---|
900 | pszStr = (char *)(pEndOfTable + 1);
|
---|
901 | pEndOfTable->u8Type = 0x7f;
|
---|
902 |
|
---|
903 | pEndOfTable->u8Length = sizeof(*pEndOfTable);
|
---|
904 | pEndOfTable->u16Handle = 0xFEFF;
|
---|
905 | *pcbDmiTables = ((uintptr_t)pszStr - (uintptr_t)pTable) + 2;
|
---|
906 |
|
---|
907 | /* We currently plant 10 DMI tables. Update this if tables number changed. */
|
---|
908 | *pcNumDmiTables = 10;
|
---|
909 |
|
---|
910 | /* If more fields are added here, fix the size check in READCFGSTR */
|
---|
911 |
|
---|
912 | /* Success! */
|
---|
913 | break;
|
---|
914 | }
|
---|
915 |
|
---|
916 | #undef READCFGSTR
|
---|
917 | #undef READCFGINT
|
---|
918 | #undef CHECKSIZE
|
---|
919 | return VINF_SUCCESS;
|
---|
920 | }
|
---|
921 |
|
---|
922 | /**
|
---|
923 | * Construct the SMBIOS and DMI headers table pointer at VM construction and
|
---|
924 | * reset.
|
---|
925 | *
|
---|
926 | * @param pDevIns The device instance data.
|
---|
927 | */
|
---|
928 | void FwCommonPlantSmbiosAndDmiHdrs(PPDMDEVINS pDevIns, uint16_t cbDmiTables, uint16_t cNumDmiTables)
|
---|
929 | {
|
---|
930 | struct
|
---|
931 | {
|
---|
932 | struct SMBIOSHDR smbios;
|
---|
933 | struct DMIMAINHDR dmi;
|
---|
934 | }
|
---|
935 | aBiosHeaders =
|
---|
936 | {
|
---|
937 | // The SMBIOS header
|
---|
938 | {
|
---|
939 | { 0x5f, 0x53, 0x4d, 0x5f}, // "_SM_" signature
|
---|
940 | 0x00, // checksum
|
---|
941 | 0x1f, // EPS length, defined by standard
|
---|
942 | VBOX_SMBIOS_MAJOR_VER, // SMBIOS major version
|
---|
943 | VBOX_SMBIOS_MINOR_VER, // SMBIOS minor version
|
---|
944 | VBOX_SMBIOS_MAXSS, // Maximum structure size
|
---|
945 | 0x00, // Entry point revision
|
---|
946 | { 0x00, 0x00, 0x00, 0x00, 0x00 } // padding
|
---|
947 | },
|
---|
948 | // The DMI header
|
---|
949 | {
|
---|
950 | { 0x5f, 0x44, 0x4d, 0x49, 0x5f }, // "_DMI_" signature
|
---|
951 | 0x00, // checksum
|
---|
952 | 0, // DMI tables length
|
---|
953 | VBOX_DMI_TABLE_BASE, // DMI tables base
|
---|
954 | 0, // DMI tables entries
|
---|
955 | VBOX_DMI_TABLE_VER, // DMI version
|
---|
956 | }
|
---|
957 | };
|
---|
958 |
|
---|
959 | aBiosHeaders.dmi.u16TablesLength = cbDmiTables;
|
---|
960 | aBiosHeaders.dmi.u16TableEntries = cNumDmiTables;
|
---|
961 | aBiosHeaders.smbios.u8Checksum = fwCommonChecksum((uint8_t*)&aBiosHeaders.smbios, sizeof(aBiosHeaders.smbios));
|
---|
962 | aBiosHeaders.dmi.u8Checksum = fwCommonChecksum((uint8_t*)&aBiosHeaders.dmi, sizeof(aBiosHeaders.dmi));
|
---|
963 |
|
---|
964 | PDMDevHlpPhysWrite(pDevIns, 0xfe300, &aBiosHeaders, sizeof(aBiosHeaders));
|
---|
965 | }
|
---|
966 |
|
---|
967 | /**
|
---|
968 | * Construct the MPS table for implanting as a ROM page.
|
---|
969 | *
|
---|
970 | * Only applicable if IOAPIC is active!
|
---|
971 | *
|
---|
972 | * See ``MultiProcessor Specification Version 1.4 (May 1997)'':
|
---|
973 | * ``1.3 Scope
|
---|
974 | * ...
|
---|
975 | * The hardware required to implement the MP specification is kept to a
|
---|
976 | * minimum, as follows:
|
---|
977 | * * One or more processors that are Intel architecture instruction set
|
---|
978 | * compatible, such as the CPUs in the Intel486 or Pentium processor
|
---|
979 | * family.
|
---|
980 | * * One or more APICs, such as the Intel 82489DX Advanced Programmable
|
---|
981 | * Interrupt Controller or the integrated APIC, such as that on the
|
---|
982 | * Intel Pentium 735\\90 and 815\\100 processors, together with a discrete
|
---|
983 | * I/O APIC unit.''
|
---|
984 | * and later:
|
---|
985 | * ``4.3.3 I/O APIC Entries
|
---|
986 | * The configuration table contains one or more entries for I/O APICs.
|
---|
987 | * ...
|
---|
988 | * I/O APIC FLAGS: EN 3:0 1 If zero, this I/O APIC is unusable, and the
|
---|
989 | * operating system should not attempt to access
|
---|
990 | * this I/O APIC.
|
---|
991 | * At least one I/O APIC must be enabled.''
|
---|
992 | *
|
---|
993 | * @param pDevIns The device instance data.
|
---|
994 | * @param pTable Where to write the table.
|
---|
995 | * @param cbMax The maximum size of the MPS table.
|
---|
996 | * @param cCpus The number of guest CPUs.
|
---|
997 | */
|
---|
998 | void FwCommonPlantMpsTable(PPDMDEVINS pDevIns, uint8_t *pTable, unsigned cbMax, uint16_t cCpus)
|
---|
999 | {
|
---|
1000 | /* configuration table */
|
---|
1001 | PMPSCFGTBLHEADER pCfgTab = (MPSCFGTBLHEADER*)pTable;
|
---|
1002 | memcpy(pCfgTab->au8Signature, "PCMP", 4);
|
---|
1003 | pCfgTab->u8SpecRev = 4; /* 1.4 */
|
---|
1004 | memcpy(pCfgTab->au8OemId, "VBOXCPU ", 8);
|
---|
1005 | memcpy(pCfgTab->au8ProductId, "VirtualBox ", 12);
|
---|
1006 | pCfgTab->u32OemTablePtr = 0;
|
---|
1007 | pCfgTab->u16OemTableSize = 0;
|
---|
1008 | pCfgTab->u16EntryCount = 0; /* Incremented as we go. */
|
---|
1009 | pCfgTab->u32AddrLocalApic = 0xfee00000;
|
---|
1010 | pCfgTab->u16ExtTableLength = 0;
|
---|
1011 | pCfgTab->u8ExtTableChecksum = 0;
|
---|
1012 | pCfgTab->u8Reserved = 0;
|
---|
1013 |
|
---|
1014 | uint32_t u32Eax, u32Ebx, u32Ecx, u32Edx;
|
---|
1015 | uint32_t u32CPUSignature = 0x0520; /* default: Pentium 100 */
|
---|
1016 | uint32_t u32FeatureFlags = 0x0001; /* default: FPU */
|
---|
1017 | PDMDevHlpGetCpuId(pDevIns, 0, &u32Eax, &u32Ebx, &u32Ecx, &u32Edx);
|
---|
1018 | if (u32Eax >= 1)
|
---|
1019 | {
|
---|
1020 | PDMDevHlpGetCpuId(pDevIns, 1, &u32Eax, &u32Ebx, &u32Ecx, &u32Edx);
|
---|
1021 | u32CPUSignature = u32Eax & 0xfff;
|
---|
1022 | /* Local APIC will be enabled later so override it here. Since we provide
|
---|
1023 | * an MP table we have an IOAPIC and therefore a Local APIC. */
|
---|
1024 | u32FeatureFlags = u32Edx | X86_CPUID_FEATURE_EDX_APIC;
|
---|
1025 | }
|
---|
1026 | /* Construct MPS table for each VCPU. */
|
---|
1027 | PMPSPROCENTRY pProcEntry = (PMPSPROCENTRY)(pCfgTab+1);
|
---|
1028 | for (int i = 0; i < cCpus; i++)
|
---|
1029 | {
|
---|
1030 | pProcEntry->u8EntryType = 0; /* processor entry */
|
---|
1031 | pProcEntry->u8LocalApicId = i;
|
---|
1032 | pProcEntry->u8LocalApicVersion = 0x14;
|
---|
1033 | pProcEntry->u8CPUFlags = (i == 0 ? 2 /* bootstrap processor */ : 0 /* application processor */) | 1 /* enabled */;
|
---|
1034 | pProcEntry->u32CPUSignature = u32CPUSignature;
|
---|
1035 | pProcEntry->u32CPUFeatureFlags = u32FeatureFlags;
|
---|
1036 | pProcEntry->u32Reserved[0] =
|
---|
1037 | pProcEntry->u32Reserved[1] = 0;
|
---|
1038 | pProcEntry++;
|
---|
1039 | pCfgTab->u16EntryCount++;
|
---|
1040 | }
|
---|
1041 |
|
---|
1042 | uint32_t iBusIdIsa = 0;
|
---|
1043 | uint32_t iBusIdPci0 = 1;
|
---|
1044 |
|
---|
1045 | /* ISA bus */
|
---|
1046 | PMPSBUSENTRY pBusEntry = (PMPSBUSENTRY)pProcEntry;
|
---|
1047 | pBusEntry->u8EntryType = 1; /* bus entry */
|
---|
1048 | pBusEntry->u8BusId = iBusIdIsa; /* this ID is referenced by the interrupt entries */
|
---|
1049 | memcpy(pBusEntry->au8BusTypeStr, "ISA ", 6);
|
---|
1050 | pBusEntry++;
|
---|
1051 | pCfgTab->u16EntryCount++;
|
---|
1052 |
|
---|
1053 | /* PCI bus */
|
---|
1054 | pBusEntry->u8EntryType = 1; /* bus entry */
|
---|
1055 | pBusEntry->u8BusId = iBusIdPci0; /* this ID can be referenced by the interrupt entries */
|
---|
1056 | memcpy(pBusEntry->au8BusTypeStr, "PCI ", 6);
|
---|
1057 | pCfgTab->u16EntryCount++;
|
---|
1058 |
|
---|
1059 |
|
---|
1060 | /* I/O-APIC.
|
---|
1061 | * MP spec: "The configuration table contains one or more entries for I/O APICs.
|
---|
1062 | * ... At least one I/O APIC must be enabled." */
|
---|
1063 | PMPSIOAPICENTRY pIOAPICEntry = (PMPSIOAPICENTRY)(pBusEntry+1);
|
---|
1064 | uint16_t iApicId = 0;
|
---|
1065 | pIOAPICEntry->u8EntryType = 2; /* I/O-APIC entry */
|
---|
1066 | pIOAPICEntry->u8Id = iApicId; /* this ID is referenced by the interrupt entries */
|
---|
1067 | pIOAPICEntry->u8Version = 0x11;
|
---|
1068 | pIOAPICEntry->u8Flags = 1 /* enable */;
|
---|
1069 | pIOAPICEntry->u32Addr = 0xfec00000;
|
---|
1070 | pCfgTab->u16EntryCount++;
|
---|
1071 |
|
---|
1072 | /* Interrupt tables */
|
---|
1073 | /* Bus vectors */
|
---|
1074 | /* Note: The PIC is currently not routed to the I/O APIC. Therefore we skip
|
---|
1075 | * pin 0 on the I/O APIC.
|
---|
1076 | */
|
---|
1077 | PMPSIOIRQENTRY pIrqEntry = (PMPSIOIRQENTRY)(pIOAPICEntry+1);
|
---|
1078 | for (int iPin = 1; iPin < 16; iPin++, pIrqEntry++)
|
---|
1079 | {
|
---|
1080 | pIrqEntry->u8EntryType = 3; /* I/O interrupt entry */
|
---|
1081 | /*
|
---|
1082 | * 0 - INT, vectored interrupt,
|
---|
1083 | * 3 - ExtINT, vectored interrupt provided by PIC
|
---|
1084 | * As we emulate system with both APIC and PIC, it's needed for their coexistence.
|
---|
1085 | */
|
---|
1086 | pIrqEntry->u8Type = (iPin == 0) ? 3 : 0;
|
---|
1087 | pIrqEntry->u16Flags = 0; /* polarity of APIC I/O input signal = conforms to bus,
|
---|
1088 | trigger mode = conforms to bus */
|
---|
1089 | pIrqEntry->u8SrcBusId = iBusIdIsa; /* ISA bus */
|
---|
1090 | /* IRQ0 mapped to pin 2, other are identity mapped */
|
---|
1091 | /* If changing, also update PDMIsaSetIrq() and MADT */
|
---|
1092 | pIrqEntry->u8SrcBusIrq = (iPin == 2) ? 0 : iPin; /* IRQ on the bus */
|
---|
1093 | pIrqEntry->u8DstIOAPICId = iApicId; /* destination IO-APIC */
|
---|
1094 | pIrqEntry->u8DstIOAPICInt = iPin; /* pin on destination IO-APIC */
|
---|
1095 | pCfgTab->u16EntryCount++;
|
---|
1096 | }
|
---|
1097 | /* Local delivery */
|
---|
1098 | pIrqEntry->u8EntryType = 4; /* Local interrupt entry */
|
---|
1099 | pIrqEntry->u8Type = 3; /* ExtINT */
|
---|
1100 | pIrqEntry->u16Flags = (1 << 2) | 1; /* active-high, edge-triggered */
|
---|
1101 | pIrqEntry->u8SrcBusId = iBusIdIsa;
|
---|
1102 | pIrqEntry->u8SrcBusIrq = 0;
|
---|
1103 | pIrqEntry->u8DstIOAPICId = 0xff;
|
---|
1104 | pIrqEntry->u8DstIOAPICInt = 0;
|
---|
1105 | pIrqEntry++;
|
---|
1106 | pCfgTab->u16EntryCount++;
|
---|
1107 | pIrqEntry->u8EntryType = 4; /* Local interrupt entry */
|
---|
1108 | pIrqEntry->u8Type = 1; /* NMI */
|
---|
1109 | pIrqEntry->u16Flags = (1 << 2) | 1; /* active-high, edge-triggered */
|
---|
1110 | pIrqEntry->u8SrcBusId = iBusIdIsa;
|
---|
1111 | pIrqEntry->u8SrcBusIrq = 0;
|
---|
1112 | pIrqEntry->u8DstIOAPICId = 0xff;
|
---|
1113 | pIrqEntry->u8DstIOAPICInt = 1;
|
---|
1114 | pIrqEntry++;
|
---|
1115 | pCfgTab->u16EntryCount++;
|
---|
1116 |
|
---|
1117 | pCfgTab->u16Length = (uint8_t*)pIrqEntry - pTable;
|
---|
1118 | pCfgTab->u8Checksum = fwCommonChecksum(pTable, pCfgTab->u16Length);
|
---|
1119 |
|
---|
1120 | AssertMsg(pCfgTab->u16Length < cbMax,
|
---|
1121 | ("VBOX_MPS_TABLE_SIZE=%d, maximum allowed size is %d",
|
---|
1122 | pCfgTab->u16Length, cbMax));
|
---|
1123 | }
|
---|
1124 |
|
---|
1125 | /**
|
---|
1126 | * Construct the MPS table pointer at VM construction and reset.
|
---|
1127 | *
|
---|
1128 | * Only applicable if IOAPIC is active!
|
---|
1129 | *
|
---|
1130 | * @param pDevIns The device instance data.
|
---|
1131 | */
|
---|
1132 | void FwCommonPlantMpsFloatPtr(PPDMDEVINS pDevIns)
|
---|
1133 | {
|
---|
1134 | MPSFLOATPTR floatPtr;
|
---|
1135 | floatPtr.au8Signature[0] = '_';
|
---|
1136 | floatPtr.au8Signature[1] = 'M';
|
---|
1137 | floatPtr.au8Signature[2] = 'P';
|
---|
1138 | floatPtr.au8Signature[3] = '_';
|
---|
1139 | floatPtr.u32MPSAddr = VBOX_MPS_TABLE_BASE;
|
---|
1140 | floatPtr.u8Length = 1; /* structure size in paragraphs */
|
---|
1141 | floatPtr.u8SpecRev = 4; /* MPS revision 1.4 */
|
---|
1142 | floatPtr.u8Checksum = 0;
|
---|
1143 | floatPtr.au8Feature[0] = 0;
|
---|
1144 | floatPtr.au8Feature[1] = 0;
|
---|
1145 | floatPtr.au8Feature[2] = 0;
|
---|
1146 | floatPtr.au8Feature[3] = 0;
|
---|
1147 | floatPtr.au8Feature[4] = 0;
|
---|
1148 | floatPtr.u8Checksum = fwCommonChecksum((uint8_t*)&floatPtr, 16);
|
---|
1149 | PDMDevHlpPhysWrite(pDevIns, 0x9fff0, &floatPtr, 16);
|
---|
1150 | }
|
---|