DevFwCommon.cpp@ 93435

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1	/* $Id: DevFwCommon.cpp 93115 2022-01-01 11:31:46Z vboxsync $ */
2	/** @file
3	* FwCommon - Shared firmware code (used by DevPcBios & DevEFI).
4	*/
5
6	/*
7	* Copyright (C) 2009-2022 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18
19	/*********************************************************************************************************************************
20	* Header Files *
21	*********************************************************************************************************************************/
22	#define LOG_GROUP LOG_GROUP_DEV
23	#include <VBox/vmm/pdmdev.h>
24
25	#include <VBox/log.h>
26	#include <VBox/err.h>
27	#include <VBox/param.h>
28
29	#include <iprt/asm.h>
30	#include <iprt/assert.h>
31	#include <iprt/buildconfig.h>
32	#include <iprt/file.h>
33	#include <iprt/mem.h>
34	#include <iprt/string.h>
35	#include <iprt/uuid.h>
36	#include <iprt/system.h>
37	#include <iprt/cdefs.h>
38
39	#include "VBoxDD.h"
40	#include "VBoxDD2.h"
41	#include "DevFwCommon.h"
42
43
44	/*********************************************************************************************************************************
45	* Defined Constants And Macros *
46	*********************************************************************************************************************************/
47
48	/*
49	* Default DMI data (legacy).
50	* Don't change this information otherwise Windows guests might demand re-activation!
51	*/
52
53	/* type 0 -- DMI BIOS information */
54	static const int32_t g_iDefDmiBIOSReleaseMajor = 0;
55	static const int32_t g_iDefDmiBIOSReleaseMinor = 0;
56	static const int32_t g_iDefDmiBIOSFirmwareMajor = 0;
57	static const int32_t g_iDefDmiBIOSFirmwareMinor = 0;
58	static const char *g_pszDefDmiBIOSVendor = "innotek GmbH";
59	static const char *g_pszDefDmiBIOSVersion = "VirtualBox";
60	static const char *g_pszDefDmiBIOSReleaseDate = "12/01/2006";
61	/* type 1 -- DMI system information */
62	static const char *g_pszDefDmiSystemVendor = "innotek GmbH";
63	static const char *g_pszDefDmiSystemProduct = "VirtualBox";
64	static const char *g_pszDefDmiSystemVersion = "1.2";
65	static const char *g_pszDefDmiSystemSerial = "0";
66	static const char *g_pszDefDmiSystemSKU = "";
67	static const char *g_pszDefDmiSystemFamily = "Virtual Machine";
68	/* type 2 -- DMI board information */
69	static const char *g_pszDefDmiBoardVendor = "Oracle Corporation";
70	static const char *g_pszDefDmiBoardProduct = "VirtualBox";
71	static const char *g_pszDefDmiBoardVersion = "1.2";
72	static const char *g_pszDefDmiBoardSerial = "0";
73	static const char *g_pszDefDmiBoardAssetTag = "";
74	static const char *g_pszDefDmiBoardLocInChass = "";
75	static const int32_t g_iDefDmiBoardBoardType = 0x0A; /* Motherboard */
76	/* type 3 -- DMI chassis information */
77	static const char *g_pszDefDmiChassisVendor = "Oracle Corporation";
78	static const int32_t g_iDefDmiChassisType = 0x01; /* ''other'', no chassis lock present */
79	static const char *g_pszDefDmiChassisVersion = "";
80	static const char *g_pszDefDmiChassisSerial = "";
81	static const char *g_pszDefDmiChassisAssetTag = "";
82	/* type 4 -- DMI processor information */
83	static const char *g_pszDefDmiProcManufacturer= "GenuineIntel";
84	static const char *g_pszDefDmiProcVersion = "Pentium(R) III";
85
86	/** The host DMI system product value, for DmiUseHostInfo=1. */
87	static char g_szHostDmiSystemProduct[64];
88	/** The host DMI system version value, for DmiUseHostInfo=1. */
89	static char g_szHostDmiSystemVersion[64];
90
91
92	/*********************************************************************************************************************************
93	* Structures and Typedefs *
94	*********************************************************************************************************************************/
95	#pragma pack(1)
96
97	typedef struct SMBIOSHDR
98	{
99	uint8_t au8Signature[4];
100	uint8_t u8Checksum;
101	uint8_t u8Eps;
102	uint8_t u8VersionMajor;
103	uint8_t u8VersionMinor;
104	uint16_t u16MaxStructureSize;
105	uint8_t u8EntryPointRevision;
106	uint8_t u8Pad[5];
107	} *SMBIOSHDRPTR;
108	AssertCompileSize(SMBIOSHDR, 16);
109
110	typedef struct DMIMAINHDR
111	{
112	uint8_t au8Signature[5];
113	uint8_t u8Checksum;
114	uint16_t u16TablesLength;
115	uint32_t u32TableBase;
116	uint16_t u16TableEntries;
117	uint8_t u8TableVersion;
118	} *DMIMAINHDRPTR;
119	AssertCompileSize(DMIMAINHDR, 15);
120
121	AssertCompile(sizeof(SMBIOSHDR) + sizeof(DMIMAINHDR) <= VBOX_DMI_HDR_SIZE);
122
123	/** DMI header */
124	typedef struct DMIHDR
125	{
126	uint8_t u8Type;
127	uint8_t u8Length;
128	uint16_t u16Handle;
129	} *PDMIHDR;
130	AssertCompileSize(DMIHDR, 4);
131
132	/** DMI BIOS information (Type 0) */
133	typedef struct DMIBIOSINF
134	{
135	DMIHDR header;
136	uint8_t u8Vendor;
137	uint8_t u8Version;
138	uint16_t u16Start;
139	uint8_t u8Release;
140	uint8_t u8ROMSize;
141	uint64_t u64Characteristics;
142	uint8_t u8CharacteristicsByte1;
143	uint8_t u8CharacteristicsByte2;
144	uint8_t u8ReleaseMajor;
145	uint8_t u8ReleaseMinor;
146	uint8_t u8FirmwareMajor;
147	uint8_t u8FirmwareMinor;
148	} *PDMIBIOSINF;
149	AssertCompileSize(DMIBIOSINF, 0x18);
150
151	/** DMI system information (Type 1) */
152	typedef struct DMISYSTEMINF
153	{
154	DMIHDR header;
155	uint8_t u8Manufacturer;
156	uint8_t u8ProductName;
157	uint8_t u8Version;
158	uint8_t u8SerialNumber;
159	uint8_t au8Uuid[16];
160	uint8_t u8WakeupType;
161	uint8_t u8SKUNumber;
162	uint8_t u8Family;
163	} *PDMISYSTEMINF;
164	AssertCompileSize(DMISYSTEMINF, 0x1b);
165
166	/** DMI board (or module) information (Type 2) */
167	typedef struct DMIBOARDINF
168	{
169	DMIHDR header;
170	uint8_t u8Manufacturer;
171	uint8_t u8Product;
172	uint8_t u8Version;
173	uint8_t u8SerialNumber;
174	uint8_t u8AssetTag;
175	uint8_t u8FeatureFlags;
176	uint8_t u8LocationInChass;
177	uint16_t u16ChassisHandle;
178	uint8_t u8BoardType;
179	uint8_t u8cObjectHandles;
180	} *PDMIBOARDINF;
181	AssertCompileSize(DMIBOARDINF, 0x0f);
182
183	/** DMI system enclosure or chassis type (Type 3) */
184	typedef struct DMICHASSIS
185	{
186	DMIHDR header;
187	uint8_t u8Manufacturer;
188	uint8_t u8Type;
189	uint8_t u8Version;
190	uint8_t u8SerialNumber;
191	uint8_t u8AssetTag;
192	uint8_t u8BootupState;
193	uint8_t u8PowerSupplyState;
194	uint8_t u8ThermalState;
195	uint8_t u8SecurityStatus;
196	/* v2.3+, currently not supported */
197	uint32_t u32OEMdefined;
198	uint8_t u8Height;
199	uint8_t u8NumPowerChords;
200	uint8_t u8ContElems;
201	uint8_t u8ContElemRecLen;
202	} *PDMICHASSIS;
203	AssertCompileSize(DMICHASSIS, 0x15);
204
205	/** DMI processor information (Type 4) */
206	typedef struct DMIPROCESSORINF
207	{
208	DMIHDR header;
209	uint8_t u8SocketDesignation;
210	uint8_t u8ProcessorType;
211	uint8_t u8ProcessorFamily;
212	uint8_t u8ProcessorManufacturer;
213	uint64_t u64ProcessorID;
214	uint8_t u8ProcessorVersion;
215	uint8_t u8Voltage;
216	uint16_t u16ExternalClock;
217	uint16_t u16MaxSpeed;
218	uint16_t u16CurrentSpeed;
219	uint8_t u8Status;
220	uint8_t u8ProcessorUpgrade;
221	/* v2.1+ */
222	uint16_t u16L1CacheHandle;
223	uint16_t u16L2CacheHandle;
224	uint16_t u16L3CacheHandle;
225	/* v2.3+ */
226	uint8_t u8SerialNumber;
227	uint8_t u8AssetTag;
228	uint8_t u8PartNumber;
229	/* v2.5+ */
230	uint8_t u8CoreCount;
231	uint8_t u8CoreEnabled;
232	uint8_t u8ThreadCount;
233	uint16_t u16ProcessorCharacteristics;
234	/* v2.6+ */
235	uint16_t u16ProcessorFamily2;
236	} *PDMIPROCESSORINF;
237	AssertCompileSize(DMIPROCESSORINF, 0x2a);
238
239	/** DMI OEM strings (Type 11) */
240	typedef struct DMIOEMSTRINGS
241	{
242	DMIHDR header;
243	uint8_t u8Count;
244	uint8_t u8VBoxVersion;
245	uint8_t u8VBoxRevision;
246	} *PDMIOEMSTRINGS;
247	AssertCompileSize(DMIOEMSTRINGS, 0x7);
248
249	/** DMI OEM-specific table (Type 128) */
250	typedef struct DMIOEMSPECIFIC
251	{
252	DMIHDR header;
253	uint32_t u32CpuFreqKHz;
254	} *PDMIOEMSPECIFIC;
255	AssertCompileSize(DMIOEMSPECIFIC, 0x8);
256
257	/** Physical memory array (Type 16) */
258	typedef struct DMIRAMARRAY
259	{
260	DMIHDR header;
261	uint8_t u8Location;
262	uint8_t u8Use;
263	uint8_t u8MemErrorCorrection;
264	uint32_t u32MaxCapacity;
265	uint16_t u16MemErrorHandle;
266	uint16_t u16NumberOfMemDevices;
267	} *PDMIRAMARRAY;
268	AssertCompileSize(DMIRAMARRAY, 15);
269
270	/** DMI Memory Device (Type 17) */
271	typedef struct DMIMEMORYDEV
272	{
273	DMIHDR header;
274	uint16_t u16PhysMemArrayHandle;
275	uint16_t u16MemErrHandle;
276	uint16_t u16TotalWidth;
277	uint16_t u16DataWidth;
278	uint16_t u16Size;
279	uint8_t u8FormFactor;
280	uint8_t u8DeviceSet;
281	uint8_t u8DeviceLocator;
282	uint8_t u8BankLocator;
283	uint8_t u8MemoryType;
284	uint16_t u16TypeDetail;
285	uint16_t u16Speed;
286	uint8_t u8Manufacturer;
287	uint8_t u8SerialNumber;
288	uint8_t u8AssetTag;
289	uint8_t u8PartNumber;
290	/* v2.6+ */
291	uint8_t u8Attributes;
292	/* v2.7+ */
293	uint32_t u32ExtendedSize;
294	uint16_t u16CfgSpeed; /* Configured speed in MT/sec. */
295	} *PDMIMEMORYDEV;
296	AssertCompileSize(DMIMEMORYDEV, 34);
297
298	/** MPS floating pointer structure */
299	typedef struct MPSFLOATPTR
300	{
301	uint8_t au8Signature[4];
302	uint32_t u32MPSAddr;
303	uint8_t u8Length;
304	uint8_t u8SpecRev;
305	uint8_t u8Checksum;
306	uint8_t au8Feature[5];
307	} *PMPSFLOATPTR;
308	AssertCompileSize(MPSFLOATPTR, 16);
309
310	/** MPS config table header */
311	typedef struct MPSCFGTBLHEADER
312	{
313	uint8_t au8Signature[4];
314	uint16_t u16Length;
315	uint8_t u8SpecRev;
316	uint8_t u8Checksum;
317	uint8_t au8OemId[8];
318	uint8_t au8ProductId[12];
319	uint32_t u32OemTablePtr;
320	uint16_t u16OemTableSize;
321	uint16_t u16EntryCount;
322	uint32_t u32AddrLocalApic;
323	uint16_t u16ExtTableLength;
324	uint8_t u8ExtTableChecksum;
325	uint8_t u8Reserved;
326	} *PMPSCFGTBLHEADER;
327	AssertCompileSize(MPSCFGTBLHEADER, 0x2c);
328
329	/** MPS processor entry */
330	typedef struct MPSPROCENTRY
331	{
332	uint8_t u8EntryType;
333	uint8_t u8LocalApicId;
334	uint8_t u8LocalApicVersion;
335	uint8_t u8CPUFlags;
336	uint32_t u32CPUSignature;
337	uint32_t u32CPUFeatureFlags;
338	uint32_t u32Reserved[2];
339	} *PMPSPROCENTRY;
340	AssertCompileSize(MPSPROCENTRY, 20);
341
342	/** MPS bus entry */
343	typedef struct MPSBUSENTRY
344	{
345	uint8_t u8EntryType;
346	uint8_t u8BusId;
347	uint8_t au8BusTypeStr[6];
348	} *PMPSBUSENTRY;
349	AssertCompileSize(MPSBUSENTRY, 8);
350
351	/** MPS I/O-APIC entry */
352	typedef struct MPSIOAPICENTRY
353	{
354	uint8_t u8EntryType;
355	uint8_t u8Id;
356	uint8_t u8Version;
357	uint8_t u8Flags;
358	uint32_t u32Addr;
359	} *PMPSIOAPICENTRY;
360	AssertCompileSize(MPSIOAPICENTRY, 8);
361
362	/** MPS I/O-Interrupt entry */
363	typedef struct MPSIOINTERRUPTENTRY
364	{
365	uint8_t u8EntryType;
366	uint8_t u8Type;
367	uint16_t u16Flags;
368	uint8_t u8SrcBusId;
369	uint8_t u8SrcBusIrq;
370	uint8_t u8DstIOAPICId;
371	uint8_t u8DstIOAPICInt;
372	} *PMPSIOIRQENTRY;
373	AssertCompileSize(MPSIOINTERRUPTENTRY, 8);
374
375	#pragma pack()
376
377
378	/**
379	* Calculate a simple checksum for the MPS table.
380	*
381	* @param au8Data data
382	* @param u32Length size of data
383	*/
384	static uint8_t fwCommonChecksum(const uint8_t * const au8Data, uint32_t u32Length)
385	{
386	uint8_t u8Sum = 0;
387	for (size_t i = 0; i < u32Length; ++i)
388	u8Sum += au8Data[i];
389	return -u8Sum;
390	}
391
392	#if 0 /* unused */
393	static bool fwCommonChecksumOk(const uint8_t * const au8Data, uint32_t u32Length)
394	{
395	uint8_t u8Sum = 0;
396	for (size_t i = 0; i < u32Length; i++)
397	u8Sum += au8Data[i];
398	return (u8Sum == 0);
399	}
400	#endif
401
402	/**
403	* Try fetch the DMI strings from the system.
404	*/
405	static void fwCommonUseHostDMIStrings(void)
406	{
407	int rc;
408
409	rc = RTSystemQueryDmiString(RTSYSDMISTR_PRODUCT_NAME,
410	g_szHostDmiSystemProduct, sizeof(g_szHostDmiSystemProduct));
411	if (RT_SUCCESS(rc))
412	{
413	g_pszDefDmiSystemProduct = g_szHostDmiSystemProduct;
414	LogRel(("DMI: Using DmiSystemProduct from host: %s\n", g_szHostDmiSystemProduct));
415	}
416
417	rc = RTSystemQueryDmiString(RTSYSDMISTR_PRODUCT_VERSION,
418	g_szHostDmiSystemVersion, sizeof(g_szHostDmiSystemVersion));
419	if (RT_SUCCESS(rc))
420	{
421	g_pszDefDmiSystemVersion = g_szHostDmiSystemVersion;
422	LogRel(("DMI: Using DmiSystemVersion from host: %s\n", g_szHostDmiSystemVersion));
423	}
424	}
425
426	/**
427	* Construct the DMI table.
428	*
429	* @returns VBox status code.
430	* @param pDevIns The device instance.
431	* @param pTable Where to create the DMI table.
432	* @param cbMax The maximum size of the DMI table.
433	* @param pUuid Pointer to the UUID to use if the DmiUuid
434	* configuration string isn't present.
435	* @param pCfg The handle to our config node.
436	* @param cCpus Number of VCPUs.
437	* @param pcbDmiTables Size of DMI data in bytes.
438	* @param pcDmiTables Number of DMI tables.
439	* @param fUefi Flag whether the UEFI specification is supported.
440	*/
441	int FwCommonPlantDMITable(PPDMDEVINS pDevIns, uint8_t *pTable, unsigned cbMax, PCRTUUID pUuid, PCFGMNODE pCfg, uint16_t cCpus,
442	uint16_t pcbDmiTables, uint16_t pcDmiTables, bool fUefi)
443	{
444	PCPDMDEVHLPR3 pHlp = pDevIns->pHlpR3;
445
446	/*
447	* CFGM Hint!
448	*
449	* The macros below makes it a bit hard to figure out the config options
450	* available here. To get a quick hint, take a look a the CFGM
451	* validation in the calling code (DevEFI.cpp and DevPcBios.cpp).
452	*
453	* 32-bit signed integer CFGM options are read by DMI_READ_CFG_S32, the 2nd
454	* parameter is the CFGM value name.
455	*
456	* Strings are read by DMI_READ_CFG_STR and DMI_READ_CFG_STR_DEF, the 2nd parameter is
457	* the CFGM value name.
458	*/
459	#define DMI_CHECK_SIZE(cbWant) \
460	{ \
461	size_t cbNeed = (size_t)(pszStr + cbWant - (char )pTable) + 5; / +1 for strtab terminator +4 for end-of-table entry */ \
462	if (cbNeed > cbMax) \
463	{ \
464	if (fHideErrors) \
465	{ \
466	LogRel(("One of the DMI strings is too long -- using default DMI data!\n")); \
467	continue; \
468	} \
469	return PDMDevHlpVMSetError(pDevIns, VERR_TOO_MUCH_DATA, RT_SRC_POS, \
470	N_("One of the DMI strings is too long. Check all bios/Dmi* configuration entries. At least %zu bytes are needed but there is no space for more than %d bytes"), cbNeed, cbMax); \
471	} \
472	}
473
474	#define DMI_READ_CFG_STR_DEF(variable, name, default_value) \
475	{ \
476	if (fForceDefault) \
477	pszTmp = default_value; \
478	else \
479	{ \
480	rc = pHlp->pfnCFGMQueryStringDef(pCfg, name, szBuf, sizeof(szBuf), default_value); \
481	if (RT_FAILURE(rc)) \
482	{ \
483	if (fHideErrors) \
484	{ \
485	LogRel(("Configuration error: Querying \"" name "\" as a string failed -- using default DMI data!\n")); \
486	continue; \
487	} \
488	return PDMDevHlpVMSetError(pDevIns, rc, RT_SRC_POS, \
489	N_("Configuration error: Querying \"" name "\" as a string failed")); \
490	} \
491	else if (!strcmp(szBuf, "<EMPTY>")) \
492	pszTmp = ""; \
493	else \
494	pszTmp = szBuf; \
495	} \
496	if (!pszTmp[0]) \
497	variable = 0; /* empty string */ \
498	else \
499	{ \
500	variable = iStrNr++; \
501	size_t cStr = strlen(pszTmp) + 1; \
502	DMI_CHECK_SIZE(cStr); \
503	memcpy(pszStr, pszTmp, cStr); \
504	pszStr += cStr ; \
505	} \
506	}
507
508	#define DMI_READ_CFG_STR(variable, name) \
509	DMI_READ_CFG_STR_DEF(variable, # name, g_pszDef ## name)
510
511	#define DMI_READ_CFG_S32(variable, name) \
512	{ \
513	if (fForceDefault) \
514	variable = g_iDef ## name; \
515	else \
516	{ \
517	rc = pHlp->pfnCFGMQueryS32Def(pCfg, # name, & variable, g_iDef ## name); \
518	if (RT_FAILURE(rc)) \
519	{ \
520	if (fHideErrors) \
521	{ \
522	LogRel(("Configuration error: Querying \"" # name "\" as an int failed -- using default DMI data!\n")); \
523	continue; \
524	} \
525	return PDMDevHlpVMSetError(pDevIns, rc, RT_SRC_POS, \
526	N_("Configuration error: Querying \"" # name "\" as an int failed")); \
527	} \
528	} \
529	}
530
531	#define DMI_START_STRUCT(tbl) \
532	pszStr = (char *)(tbl + 1); \
533	iStrNr = 1;
534
535	#define DMI_TERM_STRUCT \
536	{ \
537	pszStr++ = '\0'; / terminate set of text strings */ \
538	if (iStrNr == 1) \
539	pszStr++ = '\0'; / terminate a structure without strings */ \
540	}
541
542	bool fForceDefault = false;
543	#ifdef VBOX_BIOS_DMI_FALLBACK
544	/*
545	* There will be two passes. If an error occurs during the first pass, a
546	* message will be written to the release log and we fall back to default
547	* DMI data and start a second pass.
548	*/
549	bool fHideErrors = true;
550	#else
551	/*
552	* There will be one pass, every error is fatal and will prevent the VM
553	* from starting.
554	*/
555	bool fHideErrors = false;
556	#endif
557
558	uint8_t fDmiUseHostInfo;
559	int rc = pHlp->pfnCFGMQueryU8Def(pCfg, "DmiUseHostInfo", &fDmiUseHostInfo, 0);
560	if (RT_FAILURE (rc))
561	return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to read \"DmiUseHostInfo\""));
562
563	/* Sync up with host default DMI values */
564	if (fDmiUseHostInfo)
565	fwCommonUseHostDMIStrings();
566
567	uint8_t fDmiExposeMemoryTable;
568	rc = pHlp->pfnCFGMQueryU8Def(pCfg, "DmiExposeMemoryTable", &fDmiExposeMemoryTable, 0);
569	if (RT_FAILURE (rc))
570	return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to read \"DmiExposeMemoryTable\""));
571	uint8_t fDmiExposeProcessorInf;
572	rc = pHlp->pfnCFGMQueryU8Def(pCfg, "DmiExposeProcInf", &fDmiExposeProcessorInf, 0);
573	if (RT_FAILURE (rc))
574	return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to read \"DmiExposeProcInf\""));
575
576	for (;; fForceDefault = true, fHideErrors = false)
577	{
578	int iStrNr;
579	char szBuf[256];
580	char pszStr = (char )pTable;
581	char szDmiSystemUuid[64];
582	char *pszDmiSystemUuid;
583	const char *pszTmp;
584
585	if (fForceDefault)
586	pszDmiSystemUuid = NULL;
587	else
588	{
589	rc = pHlp->pfnCFGMQueryString(pCfg, "DmiSystemUuid", szDmiSystemUuid, sizeof(szDmiSystemUuid));
590	if (rc == VERR_CFGM_VALUE_NOT_FOUND)
591	pszDmiSystemUuid = NULL;
592	else if (RT_FAILURE(rc))
593	{
594	if (fHideErrors)
595	{
596	LogRel(("Configuration error: Querying \"DmiSystemUuid\" as a string failed, using default DMI data\n"));
597	continue;
598	}
599	return PDMDevHlpVMSetError(pDevIns, rc, RT_SRC_POS,
600	N_("Configuration error: Querying \"DmiSystemUuid\" as a string failed"));
601	}
602	else
603	pszDmiSystemUuid = szDmiSystemUuid;
604	}
605
606	/*********************************
607	* DMI BIOS information (Type 0) *
608	*********************************/
609	PDMIBIOSINF pBIOSInf = (PDMIBIOSINF)pszStr;
610	DMI_CHECK_SIZE(sizeof(*pBIOSInf));
611
612	pszStr = (char *)&pBIOSInf->u8ReleaseMajor;
613	pBIOSInf->header.u8Length = RT_OFFSETOF(DMIBIOSINF, u8ReleaseMajor);
614
615	/* don't set these fields by default for legacy compatibility */
616	int iDmiBIOSReleaseMajor, iDmiBIOSReleaseMinor;
617	DMI_READ_CFG_S32(iDmiBIOSReleaseMajor, DmiBIOSReleaseMajor);
618	DMI_READ_CFG_S32(iDmiBIOSReleaseMinor, DmiBIOSReleaseMinor);
619	if (iDmiBIOSReleaseMajor != 0 \|\| iDmiBIOSReleaseMinor != 0)
620	{
621	pszStr = (char *)&pBIOSInf->u8FirmwareMajor;
622	pBIOSInf->header.u8Length = RT_OFFSETOF(DMIBIOSINF, u8FirmwareMajor);
623	pBIOSInf->u8ReleaseMajor = iDmiBIOSReleaseMajor;
624	pBIOSInf->u8ReleaseMinor = iDmiBIOSReleaseMinor;
625
626	int iDmiBIOSFirmwareMajor, iDmiBIOSFirmwareMinor;
627	DMI_READ_CFG_S32(iDmiBIOSFirmwareMajor, DmiBIOSFirmwareMajor);
628	DMI_READ_CFG_S32(iDmiBIOSFirmwareMinor, DmiBIOSFirmwareMinor);
629	if (iDmiBIOSFirmwareMajor != 0 \|\| iDmiBIOSFirmwareMinor != 0)
630	{
631	pszStr = (char *)(pBIOSInf + 1);
632	pBIOSInf->header.u8Length = sizeof(DMIBIOSINF);
633	pBIOSInf->u8FirmwareMajor = iDmiBIOSFirmwareMajor;
634	pBIOSInf->u8FirmwareMinor = iDmiBIOSFirmwareMinor;
635	}
636	}
637
638	iStrNr = 1;
639	pBIOSInf->header.u8Type = 0; /* BIOS Information */
640	pBIOSInf->header.u16Handle = 0x0000;
641	DMI_READ_CFG_STR(pBIOSInf->u8Vendor, DmiBIOSVendor);
642	DMI_READ_CFG_STR(pBIOSInf->u8Version, DmiBIOSVersion);
643	pBIOSInf->u16Start = 0xE000;
644	DMI_READ_CFG_STR(pBIOSInf->u8Release, DmiBIOSReleaseDate);
645	pBIOSInf->u8ROMSize = 1; /* 128K */
646	pBIOSInf->u64Characteristics = RT_BIT(4) /* ISA is supported */
647	\| RT_BIT(7) /* PCI is supported */
648	\| RT_BIT(15) /* Boot from CD is supported */
649	\| RT_BIT(16) /* Selectable Boot is supported */
650	\| RT_BIT(27) /* Int 9h, 8042 Keyboard services supported */
651	\| RT_BIT(30) /* Int 10h, CGA/Mono Video Services supported */
652	/* any more?? */
653	;
654	pBIOSInf->u8CharacteristicsByte1 = RT_BIT(0) /* ACPI is supported */
655	/* any more?? */
656	;
657	pBIOSInf->u8CharacteristicsByte2 = fUefi ? RT_BIT(3) : 0
658	/* any more?? */
659	;
660	DMI_TERM_STRUCT;
661
662	/***********************************
663	* DMI system information (Type 1) *
664	***********************************/
665	PDMISYSTEMINF pSystemInf = (PDMISYSTEMINF)pszStr;
666	DMI_CHECK_SIZE(sizeof(*pSystemInf));
667	DMI_START_STRUCT(pSystemInf);
668	pSystemInf->header.u8Type = 1; /* System Information */
669	pSystemInf->header.u8Length = sizeof(*pSystemInf);
670	pSystemInf->header.u16Handle = 0x0001;
671	DMI_READ_CFG_STR(pSystemInf->u8Manufacturer, DmiSystemVendor);
672	DMI_READ_CFG_STR(pSystemInf->u8ProductName, DmiSystemProduct);
673	DMI_READ_CFG_STR(pSystemInf->u8Version, DmiSystemVersion);
674	DMI_READ_CFG_STR(pSystemInf->u8SerialNumber, DmiSystemSerial);
675
676	RTUUID uuid;
677	if (pszDmiSystemUuid)
678	{
679	rc = RTUuidFromStr(&uuid, pszDmiSystemUuid);
680	if (RT_FAILURE(rc))
681	{
682	if (fHideErrors)
683	{
684	LogRel(("Configuration error: Invalid UUID for DMI tables specified, using default DMI data\n"));
685	continue;
686	}
687	return PDMDevHlpVMSetError(pDevIns, rc, RT_SRC_POS,
688	N_("Configuration error: Invalid UUID for DMI tables specified"));
689	}
690	uuid.Gen.u32TimeLow = RT_H2BE_U32(uuid.Gen.u32TimeLow);
691	uuid.Gen.u16TimeMid = RT_H2BE_U16(uuid.Gen.u16TimeMid);
692	uuid.Gen.u16TimeHiAndVersion = RT_H2BE_U16(uuid.Gen.u16TimeHiAndVersion);
693	pUuid = &uuid;
694	}
695	memcpy(pSystemInf->au8Uuid, pUuid, sizeof(RTUUID));
696
697	pSystemInf->u8WakeupType = 6; /* Power Switch */
698	DMI_READ_CFG_STR(pSystemInf->u8SKUNumber, DmiSystemSKU);
699	DMI_READ_CFG_STR(pSystemInf->u8Family, DmiSystemFamily);
700	DMI_TERM_STRUCT;
701
702	/**********************************
703	* DMI board information (Type 2) *
704	**********************************/
705	PDMIBOARDINF pBoardInf = (PDMIBOARDINF)pszStr;
706	DMI_CHECK_SIZE(sizeof(*pBoardInf));
707	DMI_START_STRUCT(pBoardInf);
708	int iDmiBoardBoardType;
709	pBoardInf->header.u8Type = 2; /* Board Information */
710	pBoardInf->header.u8Length = sizeof(*pBoardInf);
711	pBoardInf->header.u16Handle = 0x0008;
712	DMI_READ_CFG_STR(pBoardInf->u8Manufacturer, DmiBoardVendor);
713	DMI_READ_CFG_STR(pBoardInf->u8Product, DmiBoardProduct);
714	DMI_READ_CFG_STR(pBoardInf->u8Version, DmiBoardVersion);
715	DMI_READ_CFG_STR(pBoardInf->u8SerialNumber, DmiBoardSerial);
716	DMI_READ_CFG_STR(pBoardInf->u8AssetTag, DmiBoardAssetTag);
717	pBoardInf->u8FeatureFlags = RT_BIT(0) /* hosting board, e.g. motherboard */
718	;
719	DMI_READ_CFG_STR(pBoardInf->u8LocationInChass, DmiBoardLocInChass);
720	pBoardInf->u16ChassisHandle = 0x0003; /* see type 3 */
721	DMI_READ_CFG_S32(iDmiBoardBoardType, DmiBoardBoardType);
722	pBoardInf->u8BoardType = iDmiBoardBoardType;
723	pBoardInf->u8cObjectHandles = 0;
724
725	DMI_TERM_STRUCT;
726
727	/********************************************
728	* DMI System Enclosure or Chassis (Type 3) *
729	********************************************/
730	PDMICHASSIS pChassis = (PDMICHASSIS)pszStr;
731	DMI_CHECK_SIZE(sizeof(*pChassis));
732	pszStr = (char*)&pChassis->u32OEMdefined;
733	iStrNr = 1;
734	#ifdef VBOX_WITH_DMI_CHASSIS
735	pChassis->header.u8Type = 3; /* System Enclosure or Chassis */
736	#else
737	pChassis->header.u8Type = 0x7e; /* inactive */
738	#endif
739	pChassis->header.u8Length = RT_OFFSETOF(DMICHASSIS, u32OEMdefined);
740	pChassis->header.u16Handle = 0x0003;
741	DMI_READ_CFG_STR(pChassis->u8Manufacturer, DmiChassisVendor);
742	int iDmiChassisType;
743	DMI_READ_CFG_S32(iDmiChassisType, DmiChassisType);
744	pChassis->u8Type = iDmiChassisType;
745	DMI_READ_CFG_STR(pChassis->u8Version, DmiChassisVersion);
746	DMI_READ_CFG_STR(pChassis->u8SerialNumber, DmiChassisSerial);
747	DMI_READ_CFG_STR(pChassis->u8AssetTag, DmiChassisAssetTag);
748	pChassis->u8BootupState = 0x03; /* safe */
749	pChassis->u8PowerSupplyState = 0x03; /* safe */
750	pChassis->u8ThermalState = 0x03; /* safe */
751	pChassis->u8SecurityStatus = 0x03; /* none XXX */
752	# if 0
753	/* v2.3+, currently not supported */
754	pChassis->u32OEMdefined = 0;
755	pChassis->u8Height = 0; /* unspecified */
756	pChassis->u8NumPowerChords = 0; /* unspecified */
757	pChassis->u8ContElems = 0; /* no contained elements */
758	pChassis->u8ContElemRecLen = 0; /* no contained elements */
759	# endif
760	DMI_TERM_STRUCT;
761
762	/**************************************
763	* DMI Processor Information (Type 4) *
764	**************************************/
765
766	/*
767	* This is just a dummy processor. Should we expose the real guest CPU features
768	* here? Accessing this information at this point is difficult.
769	*/
770	char szSocket[32];
771	PDMIPROCESSORINF pProcessorInf = (PDMIPROCESSORINF)pszStr;
772	DMI_CHECK_SIZE(sizeof(*pProcessorInf));
773	DMI_START_STRUCT(pProcessorInf);
774	if (fDmiExposeProcessorInf)
775	pProcessorInf->header.u8Type = 4; /* Processor Information */
776	else
777	pProcessorInf->header.u8Type = 126; /* inactive structure */
778	pProcessorInf->header.u8Length = sizeof(*pProcessorInf);
779	pProcessorInf->header.u16Handle = 0x0007;
780	RTStrPrintf(szSocket, sizeof(szSocket), "Socket #%u", 0);
781	pProcessorInf->u8SocketDesignation = iStrNr++;
782	{
783	size_t cStr = strlen(szSocket) + 1;
784	DMI_CHECK_SIZE(cStr);
785	memcpy(pszStr, szSocket, cStr);
786	pszStr += cStr;
787	}
788	pProcessorInf->u8ProcessorType = 0x03; /* Central Processor */
789	pProcessorInf->u8ProcessorFamily = 0xB1; /* Pentium III with Intel SpeedStep(TM) */
790	DMI_READ_CFG_STR(pProcessorInf->u8ProcessorManufacturer, DmiProcManufacturer);
791
792	pProcessorInf->u64ProcessorID = UINT64_C(0x0FEBFBFF00010676);
793	/* Ext Family ID = 0
794	* Ext Model ID = 2
795	* Processor Type = 0
796	* Family ID = 6
797	* Model = 7
798	* Stepping = 6
799	* Features: FPU, VME, DE, PSE, TSC, MSR, PAE, MCE, CX8,
800	* APIC, SEP, MTRR, PGE, MCA, CMOV, PAT, PSE-36,
801	* CFLSH, DS, ACPI, MMX, FXSR, SSE, SSE2, SS */
802	DMI_READ_CFG_STR(pProcessorInf->u8ProcessorVersion, DmiProcVersion);
803	pProcessorInf->u8Voltage = 0x02; /* 3.3V */
804	pProcessorInf->u16ExternalClock = 0x00; /* unknown */
805	pProcessorInf->u16MaxSpeed = 3000; /* 3GHz */
806	pProcessorInf->u16CurrentSpeed = 3000; /* 3GHz */
807	pProcessorInf->u8Status = RT_BIT(6) /* CPU socket populated */
808	\| RT_BIT(0) /* CPU enabled */
809	;
810	pProcessorInf->u8ProcessorUpgrade = 0x04; /* ZIF Socket */
811	pProcessorInf->u16L1CacheHandle = 0xFFFF; /* not specified */
812	pProcessorInf->u16L2CacheHandle = 0xFFFF; /* not specified */
813	pProcessorInf->u16L3CacheHandle = 0xFFFF; /* not specified */
814	pProcessorInf->u8SerialNumber = 0; /* not specified */
815	pProcessorInf->u8AssetTag = 0; /* not specified */
816	pProcessorInf->u8PartNumber = 0; /* not specified */
817	pProcessorInf->u8CoreCount = cCpus; /* */
818	pProcessorInf->u8CoreEnabled = cCpus;
819	pProcessorInf->u8ThreadCount = 1;
820	pProcessorInf->u16ProcessorCharacteristics
821	= RT_BIT(2); /* 64-bit capable */
822	pProcessorInf->u16ProcessorFamily2 = 0;
823	DMI_TERM_STRUCT;
824
825	/***************************************
826	* DMI Physical Memory Array (Type 16) *
827	***************************************/
828	uint64_t const cbRamSize = PDMDevHlpMMPhysGetRamSize(pDevIns);
829
830	PDMIRAMARRAY pMemArray = (PDMIRAMARRAY)pszStr;
831	DMI_CHECK_SIZE(sizeof(*pMemArray));
832	DMI_START_STRUCT(pMemArray);
833	if (fDmiExposeMemoryTable)
834	pMemArray->header.u8Type = 16; /* Physical Memory Array */
835	else
836	pMemArray->header.u8Type = 126; /* inactive structure */
837	pMemArray->header.u8Length = sizeof(*pMemArray);
838	pMemArray->header.u16Handle = 0x0005;
839	pMemArray->u8Location = 0x03; /* Motherboard */
840	pMemArray->u8Use = 0x03; /* System memory */
841	pMemArray->u8MemErrorCorrection = 0x01; /* Other */
842	if (cbRamSize / _1K > INT32_MAX)
843	{
844	/** @todo 2TB-1K limit. In such cases we probably need to provide multiple type-16 descriptors.
845	* Or use 0x8000'0000 = 'capacity unknown'? */
846	AssertLogRelMsgFailed(("DMI: RAM size %#RX64 does not fit into type-16 descriptor, clipping to %#RX64\n",
847	cbRamSize, (uint64_t)INT32_MAX * _1K));
848	pMemArray->u32MaxCapacity = INT32_MAX;
849	}
850	else
851	pMemArray->u32MaxCapacity = (int32_t)(cbRamSize / _1K); /* RAM size in K */
852	pMemArray->u16MemErrorHandle = 0xfffe; /* No error info structure */
853	pMemArray->u16NumberOfMemDevices = 1;
854	DMI_TERM_STRUCT;
855
856	/***************************************
857	* DMI Memory Device (Type 17) *
858	***************************************/
859	PDMIMEMORYDEV pMemDev = (PDMIMEMORYDEV)pszStr;
860	DMI_CHECK_SIZE(sizeof(*pMemDev));
861	DMI_START_STRUCT(pMemDev);
862	if (fDmiExposeMemoryTable)
863	pMemDev->header.u8Type = 17; /* Memory Device */
864	else
865	pMemDev->header.u8Type = 126; /* inactive structure */
866	pMemDev->header.u8Length = sizeof(*pMemDev);
867	pMemDev->header.u16Handle = 0x0006;
868	pMemDev->u16PhysMemArrayHandle = 0x0005; /* handle of array we belong to */
869	pMemDev->u16MemErrHandle = 0xfffe; /* system doesn't provide this information */
870	pMemDev->u16TotalWidth = 0xffff; /* Unknown */
871	pMemDev->u16DataWidth = 0xffff; /* Unknown */
872	int16_t u16RamSizeM;
873	int32_t u32ExtRamSizeM = 0;
874	if (cbRamSize / _1M > INT16_MAX)
875	{
876	/* The highest bit of u16Size must be 0 to specify 'MB' units / 1 would be 'KB'.
877	* SMBIOS 2.7 intruduced a 32-bit extended size. If module size is 32GB or greater,
878	* the old u16Size is set to 7FFFh; old parsers will see 32GB-1MB, new parsers will
879	* look at new u32ExtendedSize which can represent at least 128TB. OS X 10.14+ looks
880	* at the extended size.
881	*/
882	LogRel(("DMI: RAM size %#RX64 too big for one type-17 descriptor, clipping to %#RX64\n",
883	cbRamSize, (uint64_t)INT16_MAX * _1M));
884	u16RamSizeM = INT16_MAX;
885	if (cbRamSize / _1M >= 0x8000000) {
886	AssertLogRelMsgFailed(("DMI: RAM size %#RX64 too big for one type-17 descriptor, clipping to %#RX64\n",
887	cbRamSize, (uint64_t)INT32_MAX * _1M));
888	u32ExtRamSizeM = 0x8000000; /* 128TB */
889	}
890	else
891	u32ExtRamSizeM = cbRamSize / _1M;
892	}
893	else
894	u16RamSizeM = (uint16_t)(cbRamSize / _1M);
895	if (u16RamSizeM == 0)
896	u16RamSizeM = 0x400; /* 1G */
897	pMemDev->u16Size = u16RamSizeM; /* RAM size */
898	pMemDev->u32ExtendedSize = u32ExtRamSizeM;
899	pMemDev->u8FormFactor = 0x09; /* DIMM */
900	pMemDev->u8DeviceSet = 0x00; /* Not part of a device set */
901	DMI_READ_CFG_STR_DEF(pMemDev->u8DeviceLocator, " ", "DIMM 0");
902	DMI_READ_CFG_STR_DEF(pMemDev->u8BankLocator, " ", "Bank 0");
903	pMemDev->u8MemoryType = 0x03; /* DRAM */
904	pMemDev->u16TypeDetail = 0; /* Nothing special */
905	pMemDev->u16Speed = 1600; /* Unknown, shall be speed in MHz */
906	DMI_READ_CFG_STR(pMemDev->u8Manufacturer, DmiSystemVendor);
907	DMI_READ_CFG_STR_DEF(pMemDev->u8SerialNumber, " ", "00000000");
908	DMI_READ_CFG_STR_DEF(pMemDev->u8AssetTag, " ", "00000000");
909	DMI_READ_CFG_STR_DEF(pMemDev->u8PartNumber, " ", "00000000");
910	pMemDev->u8Attributes = 0; /* Unknown */
911	DMI_TERM_STRUCT;
912
913	/*****************************
914	* DMI OEM strings (Type 11) *
915	*****************************/
916	PDMIOEMSTRINGS pOEMStrings = (PDMIOEMSTRINGS)pszStr;
917	DMI_CHECK_SIZE(sizeof(*pOEMStrings));
918	DMI_START_STRUCT(pOEMStrings);
919	#ifdef VBOX_WITH_DMI_OEMSTRINGS
920	pOEMStrings->header.u8Type = 0xb; /* OEM Strings */
921	#else
922	pOEMStrings->header.u8Type = 126; /* inactive structure */
923	#endif
924	pOEMStrings->header.u8Length = sizeof(*pOEMStrings);
925	pOEMStrings->header.u16Handle = 0x0002;
926	pOEMStrings->u8Count = 2;
927
928	char szTmp[64];
929	RTStrPrintf(szTmp, sizeof(szTmp), "vboxVer_%u.%u.%u",
930	RTBldCfgVersionMajor(), RTBldCfgVersionMinor(), RTBldCfgVersionBuild());
931	DMI_READ_CFG_STR_DEF(pOEMStrings->u8VBoxVersion, "DmiOEMVBoxVer", szTmp);
932	RTStrPrintf(szTmp, sizeof(szTmp), "vboxRev_%u", RTBldCfgRevision());
933	DMI_READ_CFG_STR_DEF(pOEMStrings->u8VBoxRevision, "DmiOEMVBoxRev", szTmp);
934	DMI_TERM_STRUCT;
935
936	/*************************************
937	* DMI OEM specific table (Type 128) *
938	************************************/
939	PDMIOEMSPECIFIC pOEMSpecific = (PDMIOEMSPECIFIC)pszStr;
940	DMI_CHECK_SIZE(sizeof(*pOEMSpecific));
941	DMI_START_STRUCT(pOEMSpecific);
942	pOEMSpecific->header.u8Type = 0x80; /* OEM specific */
943	pOEMSpecific->header.u8Length = sizeof(*pOEMSpecific);
944	pOEMSpecific->header.u16Handle = 0x0008; /* Just next free handle */
945	pOEMSpecific->u32CpuFreqKHz = RT_H2LE_U32((uint32_t)((uint64_t)PDMDevHlpTMCpuTicksPerSecond(pDevIns) / 1000));
946	DMI_TERM_STRUCT;
947
948	/* End-of-table marker - includes padding to account for fixed table size. */
949	PDMIHDR pEndOfTable = (PDMIHDR)pszStr;
950	pszStr = (char *)(pEndOfTable + 1);
951	pEndOfTable->u8Type = 0x7f;
952
953	pEndOfTable->u8Length = sizeof(*pEndOfTable);
954	pEndOfTable->u16Handle = 0xFEFF;
955	*pcbDmiTables = ((uintptr_t)pszStr - (uintptr_t)pTable) + 2;
956
957	/* We currently plant 10 DMI tables. Update this if tables number changed. */
958	*pcDmiTables = 10;
959
960	/* If more fields are added here, fix the size check in DMI_READ_CFG_STR */
961
962	/* Success! */
963	break;
964	}
965
966	#undef DMI_READ_CFG_STR
967	#undef DMI_READ_CFG_S32
968	#undef DMI_CHECK_SIZE
969	return VINF_SUCCESS;
970	}
971
972	/**
973	* Construct the SMBIOS and DMI headers table pointer at VM construction and
974	* reset.
975	*
976	* @param pDevIns The device instance data.
977	* @param pHdr Pointer to the header destination.
978	* @param cbDmiTables Size of all DMI tables planted in bytes.
979	* @param cNumDmiTables Number of DMI tables planted.
980	*/
981	void FwCommonPlantSmbiosAndDmiHdrs(PPDMDEVINS pDevIns, uint8_t *pHdr, uint16_t cbDmiTables, uint16_t cNumDmiTables)
982	{
983	RT_NOREF(pDevIns);
984
985	struct
986	{
987	struct SMBIOSHDR smbios;
988	struct DMIMAINHDR dmi;
989	}
990	aBiosHeaders =
991	{
992	// The SMBIOS header
993	{
994	{ 0x5f, 0x53, 0x4d, 0x5f}, // "_SM_" signature
995	0x00, // checksum
996	0x1f, // EPS length, defined by standard
997	VBOX_SMBIOS_MAJOR_VER, // SMBIOS major version
998	VBOX_SMBIOS_MINOR_VER, // SMBIOS minor version
999	VBOX_SMBIOS_MAXSS, // Maximum structure size
1000	0x00, // Entry point revision
1001	{ 0x00, 0x00, 0x00, 0x00, 0x00 } // padding
1002	},
1003	// The DMI header
1004	{
1005	{ 0x5f, 0x44, 0x4d, 0x49, 0x5f }, // "_DMI_" signature
1006	0x00, // checksum
1007	0, // DMI tables length
1008	VBOX_DMI_TABLE_BASE, // DMI tables base
1009	0, // DMI tables entries
1010	VBOX_DMI_TABLE_VER, // DMI version
1011	}
1012	};
1013
1014	aBiosHeaders.dmi.u16TablesLength = cbDmiTables;
1015	aBiosHeaders.dmi.u16TableEntries = cNumDmiTables;
1016	/* NB: The _SM_ table checksum technically covers both the _SM_ part (16 bytes) and the _DMI_ part
1017	* (further 15 bytes). However, because the _DMI_ checksum must be zero, the _SM_ checksum can
1018	* be calculated independently.
1019	*/
1020	aBiosHeaders.smbios.u8Checksum = fwCommonChecksum((uint8_t*)&aBiosHeaders.smbios, sizeof(aBiosHeaders.smbios));
1021	aBiosHeaders.dmi.u8Checksum = fwCommonChecksum((uint8_t*)&aBiosHeaders.dmi, sizeof(aBiosHeaders.dmi));
1022
1023	memcpy(pHdr, &aBiosHeaders, sizeof(aBiosHeaders));
1024	}
1025
1026	/**
1027	* Construct the MPS table for implanting as a ROM page.
1028	*
1029	* Only applicable if IOAPIC is active!
1030	*
1031	* See ``MultiProcessor Specification Version 1.4 (May 1997)'':
1032	* ``1.3 Scope
1033	* ...
1034	* The hardware required to implement the MP specification is kept to a
1035	* minimum, as follows:
1036	* * One or more processors that are Intel architecture instruction set
1037	* compatible, such as the CPUs in the Intel486 or Pentium processor
1038	* family.
1039	* * One or more APICs, such as the Intel 82489DX Advanced Programmable
1040	* Interrupt Controller or the integrated APIC, such as that on the
1041	* Intel Pentium 735\\90 and 815\\100 processors, together with a discrete
1042	* I/O APIC unit.''
1043	* and later:
1044	* ``4.3.3 I/O APIC Entries
1045	* The configuration table contains one or more entries for I/O APICs.
1046	* ...
1047	* I/O APIC FLAGS: EN 3:0 1 If zero, this I/O APIC is unusable, and the
1048	* operating system should not attempt to access
1049	* this I/O APIC.
1050	* At least one I/O APIC must be enabled.''
1051	*
1052	* @param pDevIns The device instance data.
1053	* @param pTable Where to write the table.
1054	* @param cbMax The maximum size of the MPS table.
1055	* @param cCpus The number of guest CPUs.
1056	*/
1057	void FwCommonPlantMpsTable(PPDMDEVINS pDevIns, uint8_t *pTable, unsigned cbMax, uint16_t cCpus)
1058	{
1059	RT_NOREF1(cbMax);
1060
1061	/* configuration table */
1062	PMPSCFGTBLHEADER pCfgTab = (MPSCFGTBLHEADER*)pTable;
1063	memcpy(pCfgTab->au8Signature, "PCMP", 4);
1064	pCfgTab->u8SpecRev = 4; /* 1.4 */
1065	memcpy(pCfgTab->au8OemId, "VBOXCPU ", 8);
1066	memcpy(pCfgTab->au8ProductId, "VirtualBox ", 12);
1067	pCfgTab->u32OemTablePtr = 0;
1068	pCfgTab->u16OemTableSize = 0;
1069	pCfgTab->u16EntryCount = 0; /* Incremented as we go. */
1070	pCfgTab->u32AddrLocalApic = 0xfee00000;
1071	pCfgTab->u16ExtTableLength = 0;
1072	pCfgTab->u8ExtTableChecksum = 0;
1073	pCfgTab->u8Reserved = 0;
1074
1075	uint32_t u32Eax, u32Ebx, u32Ecx, u32Edx;
1076	uint32_t u32CPUSignature = 0x0520; /* default: Pentium 100 */
1077	uint32_t u32FeatureFlags = 0x0001; /* default: FPU */
1078	PDMDevHlpGetCpuId(pDevIns, 0, &u32Eax, &u32Ebx, &u32Ecx, &u32Edx);
1079	if (u32Eax >= 1)
1080	{
1081	PDMDevHlpGetCpuId(pDevIns, 1, &u32Eax, &u32Ebx, &u32Ecx, &u32Edx);
1082	u32CPUSignature = u32Eax & 0xfff;
1083	/* Local APIC will be enabled later so override it here. Since we provide
1084	* an MP table we have an IOAPIC and therefore a Local APIC. */
1085	u32FeatureFlags = u32Edx \| X86_CPUID_FEATURE_EDX_APIC;
1086	}
1087	/* Construct MPS table for each VCPU. */
1088	PMPSPROCENTRY pProcEntry = (PMPSPROCENTRY)(pCfgTab+1);
1089	for (int i = 0; i < cCpus; i++)
1090	{
1091	pProcEntry->u8EntryType = 0; /* processor entry */
1092	pProcEntry->u8LocalApicId = i;
1093	pProcEntry->u8LocalApicVersion = 0x14;
1094	pProcEntry->u8CPUFlags = (i == 0 ? 2 /* bootstrap processor / : 0 / application processor /) \| 1 / enabled */;
1095	pProcEntry->u32CPUSignature = u32CPUSignature;
1096	pProcEntry->u32CPUFeatureFlags = u32FeatureFlags;
1097	pProcEntry->u32Reserved[0] =
1098	pProcEntry->u32Reserved[1] = 0;
1099	pProcEntry++;
1100	pCfgTab->u16EntryCount++;
1101	}
1102
1103	uint32_t iBusIdIsa = 0;
1104	uint32_t iBusIdPci0 = 1;
1105
1106	/* ISA bus */
1107	PMPSBUSENTRY pBusEntry = (PMPSBUSENTRY)pProcEntry;
1108	pBusEntry->u8EntryType = 1; /* bus entry */
1109	pBusEntry->u8BusId = iBusIdIsa; /* this ID is referenced by the interrupt entries */
1110	memcpy(pBusEntry->au8BusTypeStr, "ISA ", 6);
1111	pBusEntry++;
1112	pCfgTab->u16EntryCount++;
1113
1114	/* PCI bus */
1115	pBusEntry->u8EntryType = 1; /* bus entry */
1116	pBusEntry->u8BusId = iBusIdPci0; /* this ID can be referenced by the interrupt entries */
1117	memcpy(pBusEntry->au8BusTypeStr, "PCI ", 6);
1118	pBusEntry++;
1119	pCfgTab->u16EntryCount++;
1120
1121
1122	/* I/O-APIC.
1123	* MP spec: "The configuration table contains one or more entries for I/O APICs.
1124	* ... At least one I/O APIC must be enabled." */
1125	PMPSIOAPICENTRY pIOAPICEntry = (PMPSIOAPICENTRY)(pBusEntry);
1126	uint16_t iApicId = 0;
1127	pIOAPICEntry->u8EntryType = 2; /* I/O-APIC entry */
1128	pIOAPICEntry->u8Id = iApicId; /* this ID is referenced by the interrupt entries */
1129	pIOAPICEntry->u8Version = 0x11;
1130	pIOAPICEntry->u8Flags = 1 /* enable */;
1131	pIOAPICEntry->u32Addr = 0xfec00000;
1132	pCfgTab->u16EntryCount++;
1133
1134	/* Interrupt tables */
1135	/* Bus vectors */
1136	/* Note: The PIC is currently not routed to the I/O APIC. Therefore we skip
1137	* pin 0 on the I/O APIC.
1138	*/
1139	PMPSIOIRQENTRY pIrqEntry = (PMPSIOIRQENTRY)(pIOAPICEntry+1);
1140	for (int iPin = 1; iPin < 16; iPin++, pIrqEntry++)
1141	{
1142	pIrqEntry->u8EntryType = 3; /* I/O interrupt entry */
1143	/*
1144	* 0 - INT, vectored interrupt,
1145	* 3 - ExtINT, vectored interrupt provided by PIC
1146	* As we emulate system with both APIC and PIC, it's needed for their coexistence.
1147	*/
1148	pIrqEntry->u8Type = (iPin == 0) ? 3 : 0;
1149	pIrqEntry->u16Flags = 0; /* polarity of APIC I/O input signal = conforms to bus,
1150	trigger mode = conforms to bus */
1151	pIrqEntry->u8SrcBusId = iBusIdIsa; /* ISA bus */
1152	/* IRQ0 mapped to pin 2, other are identity mapped */
1153	/* If changing, also update PDMIsaSetIrq() and MADT */
1154	pIrqEntry->u8SrcBusIrq = (iPin == 2) ? 0 : iPin; /* IRQ on the bus */
1155	pIrqEntry->u8DstIOAPICId = iApicId; /* destination IO-APIC */
1156	pIrqEntry->u8DstIOAPICInt = iPin; /* pin on destination IO-APIC */
1157	pCfgTab->u16EntryCount++;
1158	}
1159	/* Local delivery */
1160	pIrqEntry->u8EntryType = 4; /* Local interrupt entry */
1161	pIrqEntry->u8Type = 3; /* ExtINT */
1162	pIrqEntry->u16Flags = (1 << 2) \| 1; /* active-high, edge-triggered */
1163	pIrqEntry->u8SrcBusId = iBusIdIsa;
1164	pIrqEntry->u8SrcBusIrq = 0;
1165	pIrqEntry->u8DstIOAPICId = 0xff;
1166	pIrqEntry->u8DstIOAPICInt = 0;
1167	pIrqEntry++;
1168	pCfgTab->u16EntryCount++;
1169	pIrqEntry->u8EntryType = 4; /* Local interrupt entry */
1170	pIrqEntry->u8Type = 1; /* NMI */
1171	pIrqEntry->u16Flags = (1 << 2) \| 1; /* active-high, edge-triggered */
1172	pIrqEntry->u8SrcBusId = iBusIdIsa;
1173	pIrqEntry->u8SrcBusIrq = 0;
1174	pIrqEntry->u8DstIOAPICId = 0xff;
1175	pIrqEntry->u8DstIOAPICInt = 1;
1176	pIrqEntry++;
1177	pCfgTab->u16EntryCount++;
1178
1179	pCfgTab->u16Length = (uint8_t*)pIrqEntry - pTable;
1180	pCfgTab->u8Checksum = fwCommonChecksum(pTable, pCfgTab->u16Length);
1181
1182	AssertMsg(pCfgTab->u16Length < cbMax,
1183	("VBOX_MPS_TABLE_SIZE=%d, maximum allowed size is %d",
1184	pCfgTab->u16Length, cbMax));
1185	}
1186
1187	/**
1188	* Construct the MPS table pointer at VM construction and reset.
1189	*
1190	* Only applicable if IOAPIC is active!
1191	*
1192	* @param pDevIns The device instance data.
1193	* @param u32MpTableAddr The MP table physical address.
1194	*/
1195	void FwCommonPlantMpsFloatPtr(PPDMDEVINS pDevIns, uint32_t u32MpTableAddr)
1196	{
1197	MPSFLOATPTR floatPtr;
1198	floatPtr.au8Signature[0] = '_';
1199	floatPtr.au8Signature[1] = 'M';
1200	floatPtr.au8Signature[2] = 'P';
1201	floatPtr.au8Signature[3] = '_';
1202	floatPtr.u32MPSAddr = u32MpTableAddr;
1203	floatPtr.u8Length = 1; /* structure size in paragraphs */
1204	floatPtr.u8SpecRev = 4; /* MPS revision 1.4 */
1205	floatPtr.u8Checksum = 0;
1206	floatPtr.au8Feature[0] = 0;
1207	floatPtr.au8Feature[1] = 0;
1208	floatPtr.au8Feature[2] = 0;
1209	floatPtr.au8Feature[3] = 0;
1210	floatPtr.au8Feature[4] = 0;
1211	floatPtr.u8Checksum = fwCommonChecksum((uint8_t*)&floatPtr, 16);
1212	PDMDevHlpPhysWrite(pDevIns, 0x9fff0, &floatPtr, 16);
1213	}
1214

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source: vbox/trunk/src/VBox/Devices/PC/DevFwCommon.cpp@ 93435

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