DevDMA.cpp@ 71214

Last change on this file since 71214 was 71214, checked in by vboxsync, 7 years ago
DevDMA: Handle I/O port access from ring-0 and raw-mode since we handle port 0x80 here. Port 0x80 is used both the our BIOS and the linux kernel for I/O delay / debugging, there is no need to go to ring-3 each time it is accessed. [build fix]
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1	/* $Id: DevDMA.cpp 71214 2018-03-05 20:31:03Z vboxsync $ */
2	/** @file
3	* DevDMA - DMA Controller Device.
4	*/
5
6	/*
7	* Copyright (C) 2006-2017 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	* --------------------------------------------------------------------
17	*
18	* This code is loosely based on:
19	*
20	* QEMU DMA emulation
21	*
22	* Copyright (c) 2003 Vassili Karpov (malc)
23	*
24	* Permission is hereby granted, free of charge, to any person obtaining a copy
25	* of this software and associated documentation files (the "Software"), to deal
26	* in the Software without restriction, including without limitation the rights
27	* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
28	* copies of the Software, and to permit persons to whom the Software is
29	* furnished to do so, subject to the following conditions:
30	*
31	* The above copyright notice and this permission notice shall be included in
32	* all copies or substantial portions of the Software.
33	*
34	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
35	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
36	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
37	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
38	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
39	* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
40	* THE SOFTWARE.
41	*/
42
43
44	/*********************************************************************************************************************************
45	* Header Files *
46	*********************************************************************************************************************************/
47	#define LOG_GROUP LOG_GROUP_DEV_DMA
48	#include <VBox/vmm/pdmdev.h>
49	#include <VBox/err.h>
50
51	#include <VBox/log.h>
52	#include <iprt/assert.h>
53	#include <iprt/string.h>
54
55	#include "VBoxDD.h"
56
57
58	/** @page pg_dev_dma DMA Overview and notes
59	*
60	* Modern PCs typically emulate AT-compatible DMA. The IBM PC/AT used dual
61	* cascaded 8237A DMA controllers, augmented with a 74LS612 memory mapper.
62	* The 8237As are 8-bit parts, only capable of addressing up to 64KB; the
63	* 74LS612 extends addressing to 24 bits. That leads to well known and
64	* inconvenient DMA limitations:
65	* - DMA can only access physical memory under the 16MB line
66	* - DMA transfers must occur within a 64KB/128KB 'page'
67	*
68	* The 16-bit DMA controller added in the PC/AT shifts all 8237A addresses
69	* left by one, including the control registers addresses. The DMA register
70	* offsets (except for the page registers) are therefore "double spaced".
71	*
72	* Due to the address shifting, the DMA controller decodes more addresses
73	* than are usually documented, with aliasing. See the ICH8 datasheet.
74	*
75	* In the IBM PC and PC/XT, DMA channel 0 was used for memory refresh, thus
76	* preventing the use of memory-to-memory DMA transfers (which use channels
77	* 0 and 1). In the PC/AT, memory-to-memory DMA was theoretically possible.
78	* However, it would transfer a single byte at a time, while the CPU can
79	* transfer two (on a 286) or four (on a 386+) bytes at a time. On many
80	* compatibles, memory-to-memory DMA is not even implemented at all, and
81	* therefore has no practical use.
82	*
83	* Auto-init mode is handled implicitly; a device's transfer handler may
84	* return an end count lower than the start count.
85	*
86	* Naming convention: 'channel' refers to a system-wide DMA channel (0-7)
87	* while 'chidx' refers to a DMA channel index within a controller (0-3).
88	*
89	* References:
90	* - IBM Personal Computer AT Technical Reference, 1984
91	* - Intel 8237A-5 Datasheet, 1993
92	* - Frank van Gilluwe, The Undocumented PC, 1994
93	* - OPTi 82C206 Data Book, 1996 (or Chips & Tech 82C206)
94	* - Intel ICH8 Datasheet, 2007
95	*/
96
97
98	/* Saved state versions. */
99	#define DMA_SAVESTATE_OLD 1 /* The original saved state. */
100	#define DMA_SAVESTATE_CURRENT 2 /* The new and improved saved state. */
101
102	/* State information for a single DMA channel. */
103	typedef struct {
104	RTR3PTR pvUser; /* User specific context. */
105	R3PTRTYPE(PFNDMATRANSFERHANDLER) pfnXferHandler; /* Transfer handler for channel. */
106	uint16_t u16BaseAddr; /* Base address for transfers. */
107	uint16_t u16BaseCount; /* Base count for transfers. */
108	uint16_t u16CurAddr; /* Current address. */
109	uint16_t u16CurCount; /* Current count. */
110	uint8_t u8Mode; /* Channel mode. */
111	} DMAChannel;
112
113	/* State information for a DMA controller (DMA8 or DMA16). */
114	typedef struct {
115	DMAChannel ChState[4]; /* Per-channel state. */
116	uint8_t au8Page[8]; /* Page registers (A16-A23). */
117	uint8_t au8PageHi[8]; /* High page registers (A24-A31). */
118	uint8_t u8Command; /* Command register. */
119	uint8_t u8Status; /* Status register. */
120	uint8_t u8Mask; /* Mask register. */
121	uint8_t u8Temp; /* Temporary (mem/mem) register. */
122	uint8_t u8ModeCtr; /* Mode register counter for reads. */
123	bool fHiByte; /* Byte pointer (T/F -> high/low). */
124	uint32_t is16bit; /* True for 16-bit DMA. */
125	} DMAControl;
126
127	/* Complete DMA state information. */
128	typedef struct {
129	PPDMDEVINSR3 pDevIns; /* Device instance. */
130	R3PTRTYPE(PCPDMDMACHLP) pHlp; /* PDM DMA helpers. */
131	DMAControl DMAC[2]; /* Two DMA controllers. */
132	bool fRZEnabled;
133	} DMAState;
134
135	/* DMA command register bits. */
136	enum {
137	CMD_MEMTOMEM = 0x01, /* Enable mem-to-mem trasfers. */
138	CMD_ADRHOLD = 0x02, /* Address hold for mem-to-mem. */
139	CMD_DISABLE = 0x04, /* Disable controller. */
140	CMD_COMPRTIME = 0x08, /* Compressed timing. */
141	CMD_ROTPRIO = 0x10, /* Rotating priority. */
142	CMD_EXTWR = 0x20, /* Extended write. */
143	CMD_DREQHI = 0x40, /* DREQ is active high if set. */
144	CMD_DACKHI = 0x80, /* DACK is active high if set. */
145	CMD_UNSUPPORTED = CMD_MEMTOMEM \| CMD_ADRHOLD \| CMD_COMPRTIME
146	\| CMD_EXTWR \| CMD_DREQHI \| CMD_DACKHI
147	};
148
149	/* DMA control register offsets for read accesses. */
150	enum {
151	CTL_R_STAT, /* Read status registers. */
152	CTL_R_DMAREQ, /* Read DRQ register. */
153	CTL_R_CMD, /* Read command register. */
154	CTL_R_MODE, /* Read mode register. */
155	CTL_R_SETBPTR, /* Set byte pointer flip-flop. */
156	CTL_R_TEMP, /* Read temporary register. */
157	CTL_R_CLRMODE, /* Clear mode register counter. */
158	CTL_R_MASK /* Read all DRQ mask bits. */
159	};
160
161	/* DMA control register offsets for read accesses. */
162	enum {
163	CTL_W_CMD, /* Write command register. */
164	CTL_W_DMAREQ, /* Write DRQ register. */
165	CTL_W_MASKONE, /* Write single DRQ mask bit. */
166	CTL_W_MODE, /* Write mode register. */
167	CTL_W_CLRBPTR, /* Clear byte pointer flip-flop. */
168	CTL_W_MASTRCLR, /* Master clear. */
169	CTL_W_CLRMASK, /* Clear all DRQ mask bits. */
170	CTL_W_MASK /* Write all DRQ mask bits. */
171	};
172
173	/* DMA transfer modes. */
174	enum {
175	DMODE_DEMAND, /* Demand transfer mode. */
176	DMODE_SINGLE, /* Single transfer mode. */
177	DMODE_BLOCK, /* Block transfer mode. */
178	DMODE_CASCADE /* Cascade mode. */
179	};
180
181	/* DMA transfer types. */
182	enum {
183	DTYPE_VERIFY, /* Verify transfer type. */
184	DTYPE_WRITE, /* Write transfer type. */
185	DTYPE_READ, /* Read transfer type. */
186	DTYPE_ILLEGAL /* Undefined. */
187	};
188
189	#ifndef VBOX_DEVICE_STRUCT_TESTCASE
190
191
192	/* Convert DMA channel number (0-7) to controller number (0-1). */
193	#define DMACH2C(c) (c < 4 ? 0 : 1)
194
195	#ifdef LOG_ENABLED
196	static int const g_aiDmaChannelMap[8] = {-1, 2, 3, 1, -1, -1, -1, 0};
197	/* Map a DMA page register offset (0-7) to channel index (0-3). */
198	# define DMAPG2CX(c) (g_aiDmaChannelMap[c])
199	#endif
200
201	#ifdef IN_RING3
202	static int const g_aiDmaMapChannel[4] = {7, 3, 1, 2};
203	/* Map a channel index (0-3) to DMA page register offset (0-7). */
204	# define DMACX2PG(c) (g_aiDmaMapChannel[c])
205	/* Map a channel number (0-7) to DMA page register offset (0-7). */
206	# define DMACH2PG(c) (g_aiDmaMapChannel[c & 3])
207	#endif
208
209	/* Test the decrement bit of mode register. */
210	#define IS_MODE_DEC(c) ((c) & 0x20)
211	/* Test the auto-init bit of mode register. */
212	#define IS_MODE_AI(c) ((c) & 0x10)
213	/* Extract the transfer type bits of mode register. */
214	#define GET_MODE_XTYP(c) (((c) & 0x0c) >> 2)
215
216
217	/* Perform a master clear (reset) on a DMA controller. */
218	static void dmaClear(DMAControl *dc)
219	{
220	dc->u8Command = 0;
221	dc->u8Status = 0;
222	dc->u8Temp = 0;
223	dc->u8ModeCtr = 0;
224	dc->fHiByte = false;
225	dc->u8Mask = UINT8_MAX;
226	}
227
228
229	/** Read the byte pointer and flip it. */
230	DECLINLINE(bool) dmaReadBytePtr(DMAControl *dc)
231	{
232	bool fHighByte = !!dc->fHiByte;
233	dc->fHiByte ^= 1;
234	return fHighByte;
235	}
236
237
238	/* DMA address registers writes and reads. */
239
240	/**
241	* @callback_method_impl{FNIOMIOPORTOUT, Ports 0-7 & 0xc0-0xcf}
242	*/
243	PDMBOTHCBDECL(int) dmaWriteAddr(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT port, uint32_t u32, unsigned cb)
244	{
245	RT_NOREF(pDevIns);
246	if (cb == 1)
247	{
248	DMAControl dc = (DMAControl )pvUser;
249	DMAChannel *ch;
250	int chidx, reg, is_count;
251
252	Assert(!(u32 & ~0xff)); /* Check for garbage in high bits. */
253	reg = (port >> dc->is16bit) & 0x0f;
254	chidx = reg >> 1;
255	is_count = reg & 1;
256	ch = &dc->ChState[chidx];
257	if (dmaReadBytePtr(dc))
258	{
259	/* Write the high byte. */
260	if (is_count)
261	ch->u16BaseCount = RT_MAKE_U16(ch->u16BaseCount, u32);
262	else
263	ch->u16BaseAddr = RT_MAKE_U16(ch->u16BaseAddr, u32);
264
265	ch->u16CurCount = 0;
266	ch->u16CurAddr = ch->u16BaseAddr;
267	}
268	else
269	{
270	/* Write the low byte. */
271	if (is_count)
272	ch->u16BaseCount = RT_MAKE_U16(u32, RT_HIBYTE(ch->u16BaseCount));
273	else
274	ch->u16BaseAddr = RT_MAKE_U16(u32, RT_HIBYTE(ch->u16BaseAddr));
275	}
276	Log2(("dmaWriteAddr: port %#06x, chidx %d, data %#02x\n",
277	port, chidx, u32));
278	}
279	else
280	{
281	/* Likely a guest bug. */
282	Log(("Bad size write to count register %#x (size %d, data %#x)\n",
283	port, cb, u32));
284	}
285	return VINF_SUCCESS;
286	}
287
288
289	/**
290	* @callback_method_impl{FNIOMIOPORTIN, Ports 0-7 & 0xc0-0xcf}
291	*/
292	PDMBOTHCBDECL(int) dmaReadAddr(PPDMDEVINS pDevIns, void pvUser, RTIOPORT port, uint32_t pu32, unsigned cb)
293	{
294	RT_NOREF(pDevIns);
295	if (cb == 1)
296	{
297	DMAControl dc = (DMAControl )pvUser;
298	DMAChannel *ch;
299	int chidx, reg, val, dir;
300	int bptr;
301
302	reg = (port >> dc->is16bit) & 0x0f;
303	chidx = reg >> 1;
304	ch = &dc->ChState[chidx];
305
306	dir = IS_MODE_DEC(ch->u8Mode) ? -1 : 1;
307	if (reg & 1)
308	val = ch->u16BaseCount - ch->u16CurCount;
309	else
310	val = ch->u16CurAddr + ch->u16CurCount * dir;
311
312	bptr = dmaReadBytePtr(dc);
313	pu32 = RT_LOBYTE(val >> (bptr 8));
314
315	Log(("Count read: port %#06x, reg %#04x, data %#x\n", port, reg, val));
316	return VINF_SUCCESS;
317	}
318	return VERR_IOM_IOPORT_UNUSED;
319	}
320
321	/* DMA control registers writes and reads. */
322
323	/**
324	* @callback_method_impl{FNIOMIOPORTOUT, Ports 0x8-0xf & 0xd0-0xdf}
325	*/
326	PDMBOTHCBDECL(int) dmaWriteCtl(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT port, uint32_t u32, unsigned cb)
327	{
328	RT_NOREF(pDevIns);
329	if (cb == 1)
330	{
331	DMAControl dc = (DMAControl )pvUser;
332	int chidx = 0;
333	int reg;
334
335	reg = ((port >> dc->is16bit) & 0x0f) - 8;
336	Assert((reg >= CTL_W_CMD && reg <= CTL_W_MASK));
337	Assert(!(u32 & ~0xff)); /* Check for garbage in high bits. */
338
339	switch (reg) {
340	case CTL_W_CMD:
341	/* Unsupported commands are entirely ignored. */
342	if (u32 & CMD_UNSUPPORTED)
343	{
344	Log(("DMA command %#x is not supported, ignoring!\n", u32));
345	break;
346	}
347	dc->u8Command = u32;
348	break;
349	case CTL_W_DMAREQ:
350	chidx = u32 & 3;
351	if (u32 & 4)
352	dc->u8Status \|= 1 << (chidx + 4);
353	else
354	dc->u8Status &= ~(1 << (chidx + 4));
355	dc->u8Status &= ~(1 << chidx); /* Clear TC for channel. */
356	break;
357	case CTL_W_MASKONE:
358	chidx = u32 & 3;
359	if (u32 & 4)
360	dc->u8Mask \|= 1 << chidx;
361	else
362	dc->u8Mask &= ~(1 << chidx);
363	break;
364	case CTL_W_MODE:
365	{
366	int op, opmode;
367
368	chidx = u32 & 3;
369	op = (u32 >> 2) & 3;
370	opmode = (u32 >> 6) & 3;
371	Log2(("chidx %d, op %d, %sauto-init, %screment, opmode %d\n",
372	chidx, op, IS_MODE_AI(u32) ? "" : "no ",
373	IS_MODE_DEC(u32) ? "de" : "in", opmode));
374
375	dc->ChState[chidx].u8Mode = u32;
376	break;
377	}
378	case CTL_W_CLRBPTR:
379	dc->fHiByte = false;
380	break;
381	case CTL_W_MASTRCLR:
382	dmaClear(dc);
383	break;
384	case CTL_W_CLRMASK:
385	dc->u8Mask = 0;
386	break;
387	case CTL_W_MASK:
388	dc->u8Mask = u32;
389	break;
390	default:
391	Assert(0);
392	break;
393	}
394	Log(("dmaWriteCtl: port %#06x, chidx %d, data %#02x\n",
395	port, chidx, u32));
396	}
397	else
398	{
399	/* Likely a guest bug. */
400	Log(("Bad size write to controller register %#x (size %d, data %#x)\n",
401	port, cb, u32));
402	}
403	return VINF_SUCCESS;
404	}
405
406
407	/**
408	* @callback_method_impl{FNIOMIOPORTIN, Ports 0x8-0xf & 0xd0-0xdf}
409	*/
410	PDMBOTHCBDECL(int) dmaReadCtl(PPDMDEVINS pDevIns, void pvUser, RTIOPORT port, uint32_t pu32, unsigned cb)
411	{
412	RT_NOREF(pDevIns);
413	if (cb == 1)
414	{
415	DMAControl dc = (DMAControl )pvUser;
416	uint8_t val = 0;
417	int reg;
418
419	reg = ((port >> dc->is16bit) & 0x0f) - 8;
420	Assert((reg >= CTL_R_STAT && reg <= CTL_R_MASK));
421
422	switch (reg)
423	{
424	case CTL_R_STAT:
425	val = dc->u8Status;
426	dc->u8Status &= 0xf0; /* A read clears all TCs. */
427	break;
428	case CTL_R_DMAREQ:
429	val = (dc->u8Status >> 4) \| 0xf0;
430	break;
431	case CTL_R_CMD:
432	val = dc->u8Command;
433	break;
434	case CTL_R_MODE:
435	val = dc->ChState[dc->u8ModeCtr].u8Mode \| 3;
436	dc->u8ModeCtr = (dc->u8ModeCtr + 1) & 3;
437	break;
438	case CTL_R_SETBPTR:
439	dc->fHiByte = true;
440	break;
441	case CTL_R_TEMP:
442	val = dc->u8Temp;
443	break;
444	case CTL_R_CLRMODE:
445	dc->u8ModeCtr = 0;
446	break;
447	case CTL_R_MASK:
448	val = dc->u8Mask;
449	break;
450	default:
451	Assert(0);
452	break;
453	}
454
455	Log(("Ctrl read: port %#06x, reg %#04x, data %#x\n", port, reg, val));
456	*pu32 = val;
457
458	return VINF_SUCCESS;
459	}
460	return VERR_IOM_IOPORT_UNUSED;
461	}
462
463
464
465	/**
466	* @callback_method_impl{FNIOMIOPORTIN,
467	* DMA page registers - Ports 0x80-0x87 & 0x88-0x8f}
468	*
469	* There are 16 R/W page registers for compatibility with the IBM PC/AT; only
470	* some of those registers are used for DMA. The page register accessible via
471	* port 80h may be read to insert small delays or used as a scratch register by
472	* a BIOS.
473	*/
474	PDMBOTHCBDECL(int) dmaReadPage(PPDMDEVINS pDevIns, void pvUser, RTIOPORT port, uint32_t pu32, unsigned cb)
475	{
476	RT_NOREF(pDevIns);
477	DMAControl dc = (DMAControl )pvUser;
478	int reg;
479
480	if (cb == 1)
481	{
482	reg = port & 7;
483	*pu32 = dc->au8Page[reg];
484	Log2(("Read %#x (byte) from page register %#x (channel %d)\n",
485	*pu32, port, DMAPG2CX(reg)));
486	return VINF_SUCCESS;
487	}
488
489	if (cb == 2)
490	{
491	reg = port & 7;
492	*pu32 = dc->au8Page[reg] \| (dc->au8Page[(reg + 1) & 7] << 8);
493	Log2(("Read %#x (word) from page register %#x (channel %d)\n",
494	*pu32, port, DMAPG2CX(reg)));
495	return VINF_SUCCESS;
496	}
497
498	return VERR_IOM_IOPORT_UNUSED;
499	}
500
501
502	/**
503	* @callback_method_impl{FNIOMIOPORTOUT,
504	* DMA page registers - Ports 0x80-0x87 & 0x88-0x8f}
505	*/
506	PDMBOTHCBDECL(int) dmaWritePage(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT port, uint32_t u32, unsigned cb)
507	{
508	RT_NOREF(pDevIns);
509	DMAControl dc = (DMAControl )pvUser;
510	int reg;
511
512	if (cb == 1)
513	{
514	Assert(!(u32 & ~0xff)); /* Check for garbage in high bits. */
515	reg = port & 7;
516	dc->au8Page[reg] = u32;
517	dc->au8PageHi[reg] = 0; /* Corresponding high page cleared. */
518	Log2(("Wrote %#x to page register %#x (channel %d)\n",
519	u32, port, DMAPG2CX(reg)));
520	}
521	else if (cb == 2)
522	{
523	Assert(!(u32 & ~0xffff)); /* Check for garbage in high bits. */
524	reg = port & 7;
525	dc->au8Page[reg] = u32;
526	dc->au8PageHi[reg] = 0; /* Corresponding high page cleared. */
527	reg = (port + 1) & 7;
528	dc->au8Page[reg] = u32 >> 8;
529	dc->au8PageHi[reg] = 0; /* Corresponding high page cleared. */
530	}
531	else
532	{
533	/* Likely a guest bug. */
534	Log(("Bad size write to page register %#x (size %d, data %#x)\n",
535	port, cb, u32));
536	}
537	return VINF_SUCCESS;
538	}
539
540
541	/**
542	* @callback_method_impl{FNIOMIOPORTIN,
543	* EISA style high page registers for extending the DMA addresses to cover
544	* the entire 32-bit address space. Ports 0x480-0x487 & 0x488-0x48f}
545	*/
546	PDMBOTHCBDECL(int) dmaReadHiPage(PPDMDEVINS pDevIns, void pvUser, RTIOPORT port, uint32_t pu32, unsigned cb)
547	{
548	RT_NOREF(pDevIns);
549	if (cb == 1)
550	{
551	DMAControl dc = (DMAControl )pvUser;
552	int reg;
553
554	reg = port & 7;
555	*pu32 = dc->au8PageHi[reg];
556	Log2(("Read %#x to from high page register %#x (channel %d)\n",
557	*pu32, port, DMAPG2CX(reg)));
558	return VINF_SUCCESS;
559	}
560	return VERR_IOM_IOPORT_UNUSED;
561	}
562
563
564	/**
565	* @callback_method_impl{FNIOMIOPORTOUT, Ports 0x480-0x487 & 0x488-0x48f}
566	*/
567	PDMBOTHCBDECL(int) dmaWriteHiPage(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT port, uint32_t u32, unsigned cb)
568	{
569	RT_NOREF(pDevIns);
570	if (cb == 1)
571	{
572	DMAControl dc = (DMAControl )pvUser;
573	int reg;
574
575	Assert(!(u32 & ~0xff)); /* Check for garbage in high bits. */
576	reg = port & 7;
577	dc->au8PageHi[reg] = u32;
578	Log2(("Wrote %#x to high page register %#x (channel %d)\n",
579	u32, port, DMAPG2CX(reg)));
580	}
581	else
582	{
583	/* Likely a guest bug. */
584	Log(("Bad size write to high page register %#x (size %d, data %#x)\n",
585	port, cb, u32));
586	}
587	return VINF_SUCCESS;
588	}
589
590
591	#ifdef IN_RING3
592
593	/** Perform any pending transfers on a single DMA channel. */
594	static void dmaRunChannel(DMAState *pThis, int ctlidx, int chidx)
595	{
596	DMAControl *dc = &pThis->DMAC[ctlidx];
597	DMAChannel *ch = &dc->ChState[chidx];
598	uint32_t start_cnt, end_cnt;
599	int opmode;
600
601	opmode = (ch->u8Mode >> 6) & 3;
602
603	Log3(("DMA address %screment, mode %d\n",
604	IS_MODE_DEC(ch->u8Mode) ? "de" : "in",
605	ch->u8Mode >> 6));
606
607	/* Addresses and counts are shifted for 16-bit channels. */
608	start_cnt = ch->u16CurCount << dc->is16bit;
609	/* NB: The device is responsible for examining the DMA mode and not
610	* transferring more than it should if auto-init is not in use.
611	*/
612	end_cnt = ch->pfnXferHandler(pThis->pDevIns, ch->pvUser, (ctlidx * 4) + chidx,
613	start_cnt, (ch->u16BaseCount + 1) << dc->is16bit);
614	ch->u16CurCount = end_cnt >> dc->is16bit;
615	/* Set the TC (Terminal Count) bit if transfer was completed. */
616	if (ch->u16CurCount == ch->u16BaseCount + 1)
617	switch (opmode)
618	{
619	case DMODE_DEMAND:
620	case DMODE_SINGLE:
621	case DMODE_BLOCK:
622	dc->u8Status \|= RT_BIT(chidx);
623	Log3(("TC set for DMA channel %d\n", (ctlidx * 4) + chidx));
624	break;
625	default:
626	break;
627	}
628	Log3(("DMA position %d, size %d\n", end_cnt, (ch->u16BaseCount + 1) << dc->is16bit));
629	}
630
631	/**
632	* @interface_method_impl{PDMDMAREG,pfnRun}
633	*/
634	static DECLCALLBACK(bool) dmaRun(PPDMDEVINS pDevIns)
635	{
636	DMAState pThis = PDMINS_2_DATA(pDevIns, DMAState );
637	DMAControl *dc;
638	int ctlidx, chidx, mask;
639	PDMCritSectEnter(pDevIns->pCritSectRoR3, VERR_IGNORED);
640
641	/* Run all controllers and channels. */
642	for (ctlidx = 0; ctlidx < 2; ++ctlidx)
643	{
644	dc = &pThis->DMAC[ctlidx];
645
646	/* If controller is disabled, don't even bother. */
647	if (dc->u8Command & CMD_DISABLE)
648	continue;
649
650	for (chidx = 0; chidx < 4; ++chidx)
651	{
652	mask = 1 << chidx;
653	if (!(dc->u8Mask & mask) && (dc->u8Status & (mask << 4)))
654	dmaRunChannel(pThis, ctlidx, chidx);
655	}
656	}
657
658	PDMCritSectLeave(pDevIns->pCritSectRoR3);
659	return 0;
660	}
661
662	/**
663	* @interface_method_impl{PDMDMAREG,pfnRegister}
664	*/
665	static DECLCALLBACK(void) dmaRegister(PPDMDEVINS pDevIns, unsigned uChannel,
666	PFNDMATRANSFERHANDLER pfnTransferHandler, void *pvUser)
667	{
668	DMAState pThis = PDMINS_2_DATA(pDevIns, DMAState );
669	DMAChannel *ch = &pThis->DMAC[DMACH2C(uChannel)].ChState[uChannel & 3];
670
671	LogFlow(("dmaRegister: pThis=%p uChannel=%u pfnTransferHandler=%p pvUser=%p\n", pThis, uChannel, pfnTransferHandler, pvUser));
672
673	PDMCritSectEnter(pDevIns->pCritSectRoR3, VERR_IGNORED);
674	ch->pfnXferHandler = pfnTransferHandler;
675	ch->pvUser = pvUser;
676	PDMCritSectLeave(pDevIns->pCritSectRoR3);
677	}
678
679	/** Reverse the order of bytes in a memory buffer. */
680	static void dmaReverseBuf8(void *buf, unsigned len)
681	{
682	uint8_t pBeg, pEnd;
683	uint8_t temp;
684
685	pBeg = (uint8_t *)buf;
686	pEnd = pBeg + len - 1;
687	for (len = len / 2; len; --len)
688	{
689	temp = *pBeg;
690	pBeg++ = pEnd;
691	*pEnd-- = temp;
692	}
693	}
694
695	/** Reverse the order of words in a memory buffer. */
696	static void dmaReverseBuf16(void *buf, unsigned len)
697	{
698	uint16_t pBeg, pEnd;
699	uint16_t temp;
700
701	Assert(!(len & 1));
702	len /= 2; /* Convert to word count. */
703	pBeg = (uint16_t *)buf;
704	pEnd = pBeg + len - 1;
705	for (len = len / 2; len; --len)
706	{
707	temp = *pBeg;
708	pBeg++ = pEnd;
709	*pEnd-- = temp;
710	}
711	}
712
713	/**
714	* @interface_method_impl{PDMDMAREG,pfnReadMemory}
715	*/
716	static DECLCALLBACK(uint32_t) dmaReadMemory(PPDMDEVINS pDevIns, unsigned uChannel,
717	void *pvBuffer, uint32_t off, uint32_t cbBlock)
718	{
719	DMAState pThis = PDMINS_2_DATA(pDevIns, DMAState );
720	DMAControl *dc = &pThis->DMAC[DMACH2C(uChannel)];
721	DMAChannel *ch = &dc->ChState[uChannel & 3];
722	uint32_t page, pagehi;
723	uint32_t addr;
724
725	LogFlow(("dmaReadMemory: pThis=%p uChannel=%u pvBuffer=%p off=%u cbBlock=%u\n", pThis, uChannel, pvBuffer, off, cbBlock));
726
727	PDMCritSectEnter(pDevIns->pCritSectRoR3, VERR_IGNORED);
728
729	/* Build the address for this transfer. */
730	page = dc->au8Page[DMACH2PG(uChannel)] & ~dc->is16bit;
731	pagehi = dc->au8PageHi[DMACH2PG(uChannel)];
732	addr = (pagehi << 24) \| (page << 16) \| (ch->u16CurAddr << dc->is16bit);
733
734	if (IS_MODE_DEC(ch->u8Mode))
735	{
736	PDMDevHlpPhysRead(pThis->pDevIns, addr - off - cbBlock, pvBuffer, cbBlock);
737	if (dc->is16bit)
738	dmaReverseBuf16(pvBuffer, cbBlock);
739	else
740	dmaReverseBuf8(pvBuffer, cbBlock);
741	}
742	else
743	PDMDevHlpPhysRead(pThis->pDevIns, addr + off, pvBuffer, cbBlock);
744
745	PDMCritSectLeave(pDevIns->pCritSectRoR3);
746	return cbBlock;
747	}
748
749	/**
750	* @interface_method_impl{PDMDMAREG,pfnWriteMemory}
751	*/
752	static DECLCALLBACK(uint32_t) dmaWriteMemory(PPDMDEVINS pDevIns, unsigned uChannel,
753	const void *pvBuffer, uint32_t off, uint32_t cbBlock)
754	{
755	DMAState pThis = PDMINS_2_DATA(pDevIns, DMAState );
756	DMAControl *dc = &pThis->DMAC[DMACH2C(uChannel)];
757	DMAChannel *ch = &dc->ChState[uChannel & 3];
758	uint32_t page, pagehi;
759	uint32_t addr;
760
761	LogFlow(("dmaWriteMemory: pThis=%p uChannel=%u pvBuffer=%p off=%u cbBlock=%u\n", pThis, uChannel, pvBuffer, off, cbBlock));
762	if (GET_MODE_XTYP(ch->u8Mode) == DTYPE_VERIFY)
763	{
764	Log(("DMA verify transfer, ignoring write.\n"));
765	return cbBlock;
766	}
767
768	PDMCritSectEnter(pDevIns->pCritSectRoR3, VERR_IGNORED);
769
770	/* Build the address for this transfer. */
771	page = dc->au8Page[DMACH2PG(uChannel)] & ~dc->is16bit;
772	pagehi = dc->au8PageHi[DMACH2PG(uChannel)];
773	addr = (pagehi << 24) \| (page << 16) \| (ch->u16CurAddr << dc->is16bit);
774
775	if (IS_MODE_DEC(ch->u8Mode))
776	{
777	/// @todo This would need a temporary buffer.
778	Assert(0);
779	#if 0
780	if (dc->is16bit)
781	dmaReverseBuf16(pvBuffer, cbBlock);
782	else
783	dmaReverseBuf8(pvBuffer, cbBlock);
784	#endif
785	PDMDevHlpPhysWrite(pThis->pDevIns, addr - off - cbBlock, pvBuffer, cbBlock);
786	}
787	else
788	PDMDevHlpPhysWrite(pThis->pDevIns, addr + off, pvBuffer, cbBlock);
789
790	PDMCritSectLeave(pDevIns->pCritSectRoR3);
791	return cbBlock;
792	}
793
794	/**
795	* @interface_method_impl{PDMDMAREG,pfnSetDREQ}
796	*/
797	static DECLCALLBACK(void) dmaSetDREQ(PPDMDEVINS pDevIns, unsigned uChannel, unsigned uLevel)
798	{
799	DMAState pThis = PDMINS_2_DATA(pDevIns, DMAState );
800	DMAControl *dc = &pThis->DMAC[DMACH2C(uChannel)];
801	int chidx;
802
803	LogFlow(("dmaSetDREQ: pThis=%p uChannel=%u uLevel=%u\n", pThis, uChannel, uLevel));
804
805	PDMCritSectEnter(pDevIns->pCritSectRoR3, VERR_IGNORED);
806	chidx = uChannel & 3;
807	if (uLevel)
808	dc->u8Status \|= 1 << (chidx + 4);
809	else
810	dc->u8Status &= ~(1 << (chidx + 4));
811	PDMCritSectLeave(pDevIns->pCritSectRoR3);
812	}
813
814	/**
815	* @interface_method_impl{PDMDMAREG,pfnGetChannelMode}
816	*/
817	static DECLCALLBACK(uint8_t) dmaGetChannelMode(PPDMDEVINS pDevIns, unsigned uChannel)
818	{
819	DMAState pThis = PDMINS_2_DATA(pDevIns, DMAState );
820
821	LogFlow(("dmaGetChannelMode: pThis=%p uChannel=%u\n", pThis, uChannel));
822
823	PDMCritSectEnter(pDevIns->pCritSectRoR3, VERR_IGNORED);
824	uint8_t u8Mode = pThis->DMAC[DMACH2C(uChannel)].ChState[uChannel & 3].u8Mode;
825	PDMCritSectLeave(pDevIns->pCritSectRoR3);
826	return u8Mode;
827	}
828
829
830	/**
831	* @interface_method_impl{PDMDEVREG,pfnReset}
832	*/
833	static DECLCALLBACK(void) dmaReset(PPDMDEVINS pDevIns)
834	{
835	DMAState pThis = PDMINS_2_DATA(pDevIns, DMAState );
836
837	LogFlow(("dmaReset: pThis=%p\n", pThis));
838
839	/* NB: The page and address registers are unaffected by a reset
840	* and in an undefined state after power-up.
841	*/
842	dmaClear(&pThis->DMAC[0]);
843	dmaClear(&pThis->DMAC[1]);
844	}
845
846	/** Register DMA I/O port handlers. */
847	static int dmaIORegister(PPDMDEVINS pDevIns, bool fHighPage)
848	{
849	DMAState pThis = PDMINS_2_DATA(pDevIns, DMAState );
850	DMAControl *dc8 = &pThis->DMAC[0];
851	DMAControl *dc16 = &pThis->DMAC[1];
852	int rc;
853
854	dc8->is16bit = false;
855	dc16->is16bit = true;
856
857	/* Base and current address for each channel. */
858	rc = PDMDevHlpIOPortRegister(pThis->pDevIns, 0x00, 8, dc8, dmaWriteAddr, dmaReadAddr, NULL, NULL, "DMA8 Address");
859	AssertLogRelRCReturn(rc, rc);
860	rc = PDMDevHlpIOPortRegister(pThis->pDevIns, 0xC0, 16, dc16, dmaWriteAddr, dmaReadAddr, NULL, NULL, "DMA16 Address");
861	AssertLogRelRCReturn(rc, rc);
862
863	/* Control registers for both DMA controllers. */
864	rc = PDMDevHlpIOPortRegister(pThis->pDevIns, 0x08, 8, dc8, dmaWriteCtl, dmaReadCtl, NULL, NULL, "DMA8 Control");
865	AssertLogRelRCReturn(rc, rc);
866	rc = PDMDevHlpIOPortRegister(pThis->pDevIns, 0xD0, 16, dc16, dmaWriteCtl, dmaReadCtl, NULL, NULL, "DMA16 Control");
867	AssertLogRelRCReturn(rc, rc);
868
869	/* Page registers for each channel (plus a few unused ones). */
870	rc = PDMDevHlpIOPortRegister(pThis->pDevIns, 0x80, 8, dc8, dmaWritePage, dmaReadPage, NULL, NULL, "DMA8 Page");
871	AssertLogRelRCReturn(rc, rc);
872	rc = PDMDevHlpIOPortRegister(pThis->pDevIns, 0x88, 8, dc16, dmaWritePage, dmaReadPage, NULL, NULL, "DMA16 Page");
873	AssertLogRelRCReturn(rc, rc);
874
875	/* Optional EISA style high page registers (address bits 24-31). */
876	if (fHighPage)
877	{
878	rc = PDMDevHlpIOPortRegister(pThis->pDevIns, 0x480, 8, dc8, dmaWriteHiPage, dmaReadHiPage, NULL, NULL, "DMA8 Page High");
879	AssertLogRelRCReturn(rc, rc);
880	rc = PDMDevHlpIOPortRegister(pThis->pDevIns, 0x488, 8, dc16, dmaWriteHiPage, dmaReadHiPage, NULL, NULL, "DMA16 Page High");
881	AssertLogRelRCReturn(rc, rc);
882	}
883
884	if (pThis->fRZEnabled)
885	{
886	/*
887	* Ditto for raw-mode.
888	*/
889	RTRCPTR RCPtrDc8 = PDMINS_2_DATA_RCPTR(pDevIns) + RT_OFFSETOF(DMAState, DMAC[0]);
890	RTRCPTR RCPtrDc16 = PDMINS_2_DATA_RCPTR(pDevIns) + RT_OFFSETOF(DMAState, DMAC[1]);
891
892	/* Base and current address for each channel. */
893	rc = PDMDevHlpIOPortRegisterRC(pThis->pDevIns, 0x00, 8, RCPtrDc8, "dmaWriteAddr", "dmaReadAddr", NULL, NULL, "DMA8 Address");
894	AssertLogRelRCReturn(rc, rc);
895	rc = PDMDevHlpIOPortRegisterRC(pThis->pDevIns, 0xC0, 16, RCPtrDc16, "dmaWriteAddr", "dmaReadAddr", NULL, NULL, "DMA16 Address");
896	AssertLogRelRCReturn(rc, rc);
897
898	/* Control registers for both DMA controllers. */
899	rc = PDMDevHlpIOPortRegisterRC(pThis->pDevIns, 0x08, 8, RCPtrDc8, "dmaWriteCtl", "dmaReadCtl", NULL, NULL, "DMA8 Control");
900	AssertLogRelRCReturn(rc, rc);
901	rc = PDMDevHlpIOPortRegisterRC(pThis->pDevIns, 0xD0, 16, RCPtrDc16, "dmaWriteCtl", "dmaReadCtl", NULL, NULL, "DMA16 Control");
902	AssertLogRelRCReturn(rc, rc);
903
904	/* Page registers for each channel (plus a few unused ones). */
905	rc = PDMDevHlpIOPortRegisterRC(pThis->pDevIns, 0x80, 8, RCPtrDc8, "dmaWritePage", "dmaReadPage", NULL, NULL, "DMA8 Page");
906	AssertLogRelRCReturn(rc, rc);
907	rc = PDMDevHlpIOPortRegisterRC(pThis->pDevIns, 0x88, 8, RCPtrDc16, "dmaWritePage", "dmaReadPage", NULL, NULL, "DMA16 Page");
908	AssertLogRelRCReturn(rc, rc);
909
910	/* Optional EISA style high page registers (address bits 24-31). */
911	if (fHighPage)
912	{
913	rc = PDMDevHlpIOPortRegisterRC(pThis->pDevIns, 0x480, 8, RCPtrDc8, "dmaWriteHiPage", "dmaReadHiPage", NULL, NULL, "DMA8 Page High");
914	AssertLogRelRCReturn(rc, rc);
915	rc = PDMDevHlpIOPortRegisterRC(pThis->pDevIns, 0x488, 8, RCPtrDc16, "dmaWriteHiPage", "dmaReadHiPage", NULL, NULL, "DMA16 Page High");
916	AssertLogRelRCReturn(rc, rc);
917	}
918
919	/*
920	* Ditto for ring-0.
921	*/
922	RTR0PTR R0PtrDc8 = PDMINS_2_DATA_R0PTR(pDevIns) + RT_OFFSETOF(DMAState, DMAC[0]);
923	RTR0PTR R0PtrDc16 = PDMINS_2_DATA_R0PTR(pDevIns) + RT_OFFSETOF(DMAState, DMAC[1]);
924
925	/* Base and current address for each channel. */
926	rc = PDMDevHlpIOPortRegisterR0(pThis->pDevIns, 0x00, 8, R0PtrDc8, "dmaWriteAddr", "dmaReadAddr", NULL, NULL, "DMA8 Address");
927	AssertLogRelRCReturn(rc, rc);
928	rc = PDMDevHlpIOPortRegisterR0(pThis->pDevIns, 0xC0, 16, R0PtrDc16, "dmaWriteAddr", "dmaReadAddr", NULL, NULL, "DMA16 Address");
929	AssertLogRelRCReturn(rc, rc);
930
931	/* Control registers for both DMA controllers. */
932	rc = PDMDevHlpIOPortRegisterR0(pThis->pDevIns, 0x08, 8, R0PtrDc8, "dmaWriteCtl", "dmaReadCtl", NULL, NULL, "DMA8 Control");
933	AssertLogRelRCReturn(rc, rc);
934	rc = PDMDevHlpIOPortRegisterR0(pThis->pDevIns, 0xD0, 16, R0PtrDc16, "dmaWriteCtl", "dmaReadCtl", NULL, NULL, "DMA16 Control");
935	AssertLogRelRCReturn(rc, rc);
936
937	/* Page registers for each channel (plus a few unused ones). */
938	rc = PDMDevHlpIOPortRegisterR0(pThis->pDevIns, 0x80, 8, R0PtrDc8, "dmaWritePage", "dmaReadPage", NULL, NULL, "DMA8 Page");
939	AssertLogRelRCReturn(rc, rc);
940	rc = PDMDevHlpIOPortRegisterR0(pThis->pDevIns, 0x88, 8, R0PtrDc16, "dmaWritePage", "dmaReadPage", NULL, NULL, "DMA16 Page");
941	AssertLogRelRCReturn(rc, rc);
942
943	/* Optional EISA style high page registers (address bits 24-31). */
944	if (fHighPage)
945	{
946	rc = PDMDevHlpIOPortRegisterR0(pThis->pDevIns, 0x480, 8, R0PtrDc8, "dmaWriteHiPage", "dmaReadHiPage", NULL, NULL, "DMA8 Page High");
947	AssertLogRelRCReturn(rc, rc);
948	rc = PDMDevHlpIOPortRegisterR0(pThis->pDevIns, 0x488, 8, R0PtrDc16, "dmaWriteHiPage", "dmaReadHiPage", NULL, NULL, "DMA16 Page High");
949	AssertLogRelRCReturn(rc, rc);
950	}
951	}
952
953	return VINF_SUCCESS;
954	}
955
956	static void dmaSaveController(PSSMHANDLE pSSM, DMAControl *dc)
957	{
958	int chidx;
959
960	/* Save controller state... */
961	SSMR3PutU8(pSSM, dc->u8Command);
962	SSMR3PutU8(pSSM, dc->u8Mask);
963	SSMR3PutU8(pSSM, dc->fHiByte);
964	SSMR3PutU32(pSSM, dc->is16bit);
965	SSMR3PutU8(pSSM, dc->u8Status);
966	SSMR3PutU8(pSSM, dc->u8Temp);
967	SSMR3PutU8(pSSM, dc->u8ModeCtr);
968	SSMR3PutMem(pSSM, &dc->au8Page, sizeof(dc->au8Page));
969	SSMR3PutMem(pSSM, &dc->au8PageHi, sizeof(dc->au8PageHi));
970
971	/* ...and all four of its channels. */
972	for (chidx = 0; chidx < 4; ++chidx)
973	{
974	DMAChannel *ch = &dc->ChState[chidx];
975
976	SSMR3PutU16(pSSM, ch->u16CurAddr);
977	SSMR3PutU16(pSSM, ch->u16CurCount);
978	SSMR3PutU16(pSSM, ch->u16BaseAddr);
979	SSMR3PutU16(pSSM, ch->u16BaseCount);
980	SSMR3PutU8(pSSM, ch->u8Mode);
981	}
982	}
983
984	static int dmaLoadController(PSSMHANDLE pSSM, DMAControl *dc, int version)
985	{
986	uint8_t u8val;
987	uint32_t u32val;
988	int chidx;
989
990	SSMR3GetU8(pSSM, &dc->u8Command);
991	SSMR3GetU8(pSSM, &dc->u8Mask);
992	SSMR3GetU8(pSSM, &u8val);
993	dc->fHiByte = !!u8val;
994	SSMR3GetU32(pSSM, &dc->is16bit);
995	if (version > DMA_SAVESTATE_OLD)
996	{
997	SSMR3GetU8(pSSM, &dc->u8Status);
998	SSMR3GetU8(pSSM, &dc->u8Temp);
999	SSMR3GetU8(pSSM, &dc->u8ModeCtr);
1000	SSMR3GetMem(pSSM, &dc->au8Page, sizeof(dc->au8Page));
1001	SSMR3GetMem(pSSM, &dc->au8PageHi, sizeof(dc->au8PageHi));
1002	}
1003
1004	for (chidx = 0; chidx < 4; ++chidx)
1005	{
1006	DMAChannel *ch = &dc->ChState[chidx];
1007
1008	if (version == DMA_SAVESTATE_OLD)
1009	{
1010	/* Convert from 17-bit to 16-bit format. */
1011	SSMR3GetU32(pSSM, &u32val);
1012	ch->u16CurAddr = u32val >> dc->is16bit;
1013	SSMR3GetU32(pSSM, &u32val);
1014	ch->u16CurCount = u32val >> dc->is16bit;
1015	}
1016	else
1017	{
1018	SSMR3GetU16(pSSM, &ch->u16CurAddr);
1019	SSMR3GetU16(pSSM, &ch->u16CurCount);
1020	}
1021	SSMR3GetU16(pSSM, &ch->u16BaseAddr);
1022	SSMR3GetU16(pSSM, &ch->u16BaseCount);
1023	SSMR3GetU8(pSSM, &ch->u8Mode);
1024	/* Convert from old save state. */
1025	if (version == DMA_SAVESTATE_OLD)
1026	{
1027	/* Remap page register contents. */
1028	SSMR3GetU8(pSSM, &u8val);
1029	dc->au8Page[DMACX2PG(chidx)] = u8val;
1030	SSMR3GetU8(pSSM, &u8val);
1031	dc->au8PageHi[DMACX2PG(chidx)] = u8val;
1032	/* Throw away dack, eop. */
1033	SSMR3GetU8(pSSM, &u8val);
1034	SSMR3GetU8(pSSM, &u8val);
1035	}
1036	}
1037	return 0;
1038	}
1039
1040	/** @callback_method_impl{FNSSMDEVSAVEEXEC} */
1041	static DECLCALLBACK(int) dmaSaveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
1042	{
1043	DMAState pThis = PDMINS_2_DATA(pDevIns, DMAState );
1044
1045	dmaSaveController(pSSM, &pThis->DMAC[0]);
1046	dmaSaveController(pSSM, &pThis->DMAC[1]);
1047	return VINF_SUCCESS;
1048	}
1049
1050	/** @callback_method_impl{FNSSMDEVLOADEXEC} */
1051	static DECLCALLBACK(int) dmaLoadExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
1052	{
1053	DMAState pThis = PDMINS_2_DATA(pDevIns, DMAState );
1054
1055	AssertMsgReturn(uVersion <= DMA_SAVESTATE_CURRENT, ("%d\n", uVersion), VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION);
1056	Assert(uPass == SSM_PASS_FINAL); NOREF(uPass);
1057
1058	dmaLoadController(pSSM, &pThis->DMAC[0], uVersion);
1059	return dmaLoadController(pSSM, &pThis->DMAC[1], uVersion);
1060	}
1061
1062	/**
1063	* @interface_method_impl{PDMDEVREG,pfnConstruct}
1064	*/
1065	static DECLCALLBACK(int) dmaConstruct(PPDMDEVINS pDevIns, int iInstance, PCFGMNODE pCfg)
1066	{
1067	RT_NOREF(iInstance);
1068	DMAState pThis = PDMINS_2_DATA(pDevIns, DMAState );
1069
1070	/*
1071	* Initialize data.
1072	*/
1073	pThis->pDevIns = pDevIns;
1074
1075	/*
1076	* Validate configuration.
1077	*/
1078	if (!CFGMR3AreValuesValid(pCfg, "RZEnabled\0"
1079	"\0")) /* "HighPageEnable\0")) */
1080	return VERR_PDM_DEVINS_UNKNOWN_CFG_VALUES;
1081
1082	bool bHighPage = false;
1083	#if 0
1084	rc = CFGMR3QueryBool(pCfg, "HighPageEnable", &bHighPage);
1085	if (RT_FAILURE (rc))
1086	return rc;
1087	#endif
1088
1089	int rc = CFGMR3QueryBoolDef(pCfg, "RZEnabled", &pThis->fRZEnabled, true);
1090	AssertLogRelRCReturn(rc, rc);
1091
1092	rc = dmaIORegister(pDevIns, bHighPage);
1093	AssertLogRelRCReturn(rc, rc);
1094
1095	dmaReset(pDevIns);
1096
1097	PDMDMACREG Reg;
1098	Reg.u32Version = PDM_DMACREG_VERSION;
1099	Reg.pfnRun = dmaRun;
1100	Reg.pfnRegister = dmaRegister;
1101	Reg.pfnReadMemory = dmaReadMemory;
1102	Reg.pfnWriteMemory = dmaWriteMemory;
1103	Reg.pfnSetDREQ = dmaSetDREQ;
1104	Reg.pfnGetChannelMode = dmaGetChannelMode;
1105
1106	rc = PDMDevHlpDMACRegister(pDevIns, &Reg, &pThis->pHlp);
1107	if (RT_FAILURE (rc))
1108	return rc;
1109
1110	rc = PDMDevHlpSSMRegister(pDevIns, DMA_SAVESTATE_CURRENT, sizeof(*pThis), dmaSaveExec, dmaLoadExec);
1111	if (RT_FAILURE(rc))
1112	return rc;
1113
1114	return VINF_SUCCESS;
1115	}
1116
1117	/**
1118	* The device registration structure.
1119	*/
1120	const PDMDEVREG g_DeviceDMA =
1121	{
1122	/* u32Version */
1123	PDM_DEVREG_VERSION,
1124	/* szName */
1125	"8237A",
1126	/* szRCMod */
1127	"VBoxDDRC.rc",
1128	/* szR0Mod */
1129	"VBoxDDR0.r0",
1130	/* pszDescription */
1131	"DMA Controller Device",
1132	/* fFlags */
1133	PDM_DEVREG_FLAGS_DEFAULT_BITS \| PDM_DEVREG_FLAGS_R0 \| PDM_DEVREG_FLAGS_RC,
1134	/* fClass */
1135	PDM_DEVREG_CLASS_DMA,
1136	/* cMaxInstances */
1137	1,
1138	/* cbInstance */
1139	sizeof(DMAState),
1140	/* pfnConstruct */
1141	dmaConstruct,
1142	/* pfnDestruct */
1143	NULL,
1144	/* pfnRelocate */
1145	NULL,
1146	/* pfnMemSetup */
1147	NULL,
1148	/* pfnPowerOn */
1149	NULL,
1150	/* pfnReset */
1151	dmaReset,
1152	/* pfnSuspend */
1153	NULL,
1154	/* pfnResume */
1155	NULL,
1156	/* pfnAttach */
1157	NULL,
1158	/* pfnDetach */
1159	NULL,
1160	/* pfnQueryInterface. */
1161	NULL,
1162	/* pfnInitComplete */
1163	NULL,
1164	/* pfnPowerOff */
1165	NULL,
1166	/* pfnSoftReset */
1167	NULL,
1168	/* u32VersionEnd */
1169	PDM_DEVREG_VERSION
1170	};
1171	#endif /* IN_RING3 */
1172	#endif /* !VBOX_DEVICE_STRUCT_TESTCASE */
1173

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source: vbox/trunk/src/VBox/Devices/PC/DevDMA.cpp@ 71214

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