DevDMA.cpp@ 71210

Last change on this file since 71210 was 71210, checked in by vboxsync, 7 years ago
DevDMA: Handle I/O port access from ring-0 and raw-mode since we handle port 0x80 here. Port 0x80 is used both the our BIOS and the linux kernel for I/O delay / debugging, there is no need to go to ring-3 each time it is accessed.
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1	/* $Id: DevDMA.cpp 71210 2018-03-05 20:24:50Z vboxsync $ */
2	/** @file
3	* DevDMA - DMA Controller Device.
4	*/
5
6	/*
7	* Copyright (C) 2006-2017 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	* --------------------------------------------------------------------
17	*
18	* This code is loosely based on:
19	*
20	* QEMU DMA emulation
21	*
22	* Copyright (c) 2003 Vassili Karpov (malc)
23	*
24	* Permission is hereby granted, free of charge, to any person obtaining a copy
25	* of this software and associated documentation files (the "Software"), to deal
26	* in the Software without restriction, including without limitation the rights
27	* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
28	* copies of the Software, and to permit persons to whom the Software is
29	* furnished to do so, subject to the following conditions:
30	*
31	* The above copyright notice and this permission notice shall be included in
32	* all copies or substantial portions of the Software.
33	*
34	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
35	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
36	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
37	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
38	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
39	* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
40	* THE SOFTWARE.
41	*/
42
43
44	/*********************************************************************************************************************************
45	* Header Files *
46	*********************************************************************************************************************************/
47	#define LOG_GROUP LOG_GROUP_DEV_DMA
48	#include <VBox/vmm/pdmdev.h>
49	#include <VBox/err.h>
50
51	#include <VBox/log.h>
52	#include <iprt/assert.h>
53	#include <iprt/string.h>
54
55	#include <stdio.h>
56	#include <stdlib.h>
57
58	#include "VBoxDD.h"
59
60
61	/** @page pg_dev_dma DMA Overview and notes
62	*
63	* Modern PCs typically emulate AT-compatible DMA. The IBM PC/AT used dual
64	* cascaded 8237A DMA controllers, augmented with a 74LS612 memory mapper.
65	* The 8237As are 8-bit parts, only capable of addressing up to 64KB; the
66	* 74LS612 extends addressing to 24 bits. That leads to well known and
67	* inconvenient DMA limitations:
68	* - DMA can only access physical memory under the 16MB line
69	* - DMA transfers must occur within a 64KB/128KB 'page'
70	*
71	* The 16-bit DMA controller added in the PC/AT shifts all 8237A addresses
72	* left by one, including the control registers addresses. The DMA register
73	* offsets (except for the page registers) are therefore "double spaced".
74	*
75	* Due to the address shifting, the DMA controller decodes more addresses
76	* than are usually documented, with aliasing. See the ICH8 datasheet.
77	*
78	* In the IBM PC and PC/XT, DMA channel 0 was used for memory refresh, thus
79	* preventing the use of memory-to-memory DMA transfers (which use channels
80	* 0 and 1). In the PC/AT, memory-to-memory DMA was theoretically possible.
81	* However, it would transfer a single byte at a time, while the CPU can
82	* transfer two (on a 286) or four (on a 386+) bytes at a time. On many
83	* compatibles, memory-to-memory DMA is not even implemented at all, and
84	* therefore has no practical use.
85	*
86	* Auto-init mode is handled implicitly; a device's transfer handler may
87	* return an end count lower than the start count.
88	*
89	* Naming convention: 'channel' refers to a system-wide DMA channel (0-7)
90	* while 'chidx' refers to a DMA channel index within a controller (0-3).
91	*
92	* References:
93	* - IBM Personal Computer AT Technical Reference, 1984
94	* - Intel 8237A-5 Datasheet, 1993
95	* - Frank van Gilluwe, The Undocumented PC, 1994
96	* - OPTi 82C206 Data Book, 1996 (or Chips & Tech 82C206)
97	* - Intel ICH8 Datasheet, 2007
98	*/
99
100
101	/* Saved state versions. */
102	#define DMA_SAVESTATE_OLD 1 /* The original saved state. */
103	#define DMA_SAVESTATE_CURRENT 2 /* The new and improved saved state. */
104
105	/* State information for a single DMA channel. */
106	typedef struct {
107	RTR3PTR pvUser; /* User specific context. */
108	R3PTRTYPE(PFNDMATRANSFERHANDLER) pfnXferHandler; /* Transfer handler for channel. */
109	uint16_t u16BaseAddr; /* Base address for transfers. */
110	uint16_t u16BaseCount; /* Base count for transfers. */
111	uint16_t u16CurAddr; /* Current address. */
112	uint16_t u16CurCount; /* Current count. */
113	uint8_t u8Mode; /* Channel mode. */
114	} DMAChannel;
115
116	/* State information for a DMA controller (DMA8 or DMA16). */
117	typedef struct {
118	DMAChannel ChState[4]; /* Per-channel state. */
119	uint8_t au8Page[8]; /* Page registers (A16-A23). */
120	uint8_t au8PageHi[8]; /* High page registers (A24-A31). */
121	uint8_t u8Command; /* Command register. */
122	uint8_t u8Status; /* Status register. */
123	uint8_t u8Mask; /* Mask register. */
124	uint8_t u8Temp; /* Temporary (mem/mem) register. */
125	uint8_t u8ModeCtr; /* Mode register counter for reads. */
126	bool fHiByte; /* Byte pointer (T/F -> high/low). */
127	uint32_t is16bit; /* True for 16-bit DMA. */
128	} DMAControl;
129
130	/* Complete DMA state information. */
131	typedef struct {
132	PPDMDEVINSR3 pDevIns; /* Device instance. */
133	R3PTRTYPE(PCPDMDMACHLP) pHlp; /* PDM DMA helpers. */
134	DMAControl DMAC[2]; /* Two DMA controllers. */
135	bool fRZEnabled;
136	} DMAState;
137
138	/* DMA command register bits. */
139	enum {
140	CMD_MEMTOMEM = 0x01, /* Enable mem-to-mem trasfers. */
141	CMD_ADRHOLD = 0x02, /* Address hold for mem-to-mem. */
142	CMD_DISABLE = 0x04, /* Disable controller. */
143	CMD_COMPRTIME = 0x08, /* Compressed timing. */
144	CMD_ROTPRIO = 0x10, /* Rotating priority. */
145	CMD_EXTWR = 0x20, /* Extended write. */
146	CMD_DREQHI = 0x40, /* DREQ is active high if set. */
147	CMD_DACKHI = 0x80, /* DACK is active high if set. */
148	CMD_UNSUPPORTED = CMD_MEMTOMEM \| CMD_ADRHOLD \| CMD_COMPRTIME
149	\| CMD_EXTWR \| CMD_DREQHI \| CMD_DACKHI
150	};
151
152	/* DMA control register offsets for read accesses. */
153	enum {
154	CTL_R_STAT, /* Read status registers. */
155	CTL_R_DMAREQ, /* Read DRQ register. */
156	CTL_R_CMD, /* Read command register. */
157	CTL_R_MODE, /* Read mode register. */
158	CTL_R_SETBPTR, /* Set byte pointer flip-flop. */
159	CTL_R_TEMP, /* Read temporary register. */
160	CTL_R_CLRMODE, /* Clear mode register counter. */
161	CTL_R_MASK /* Read all DRQ mask bits. */
162	};
163
164	/* DMA control register offsets for read accesses. */
165	enum {
166	CTL_W_CMD, /* Write command register. */
167	CTL_W_DMAREQ, /* Write DRQ register. */
168	CTL_W_MASKONE, /* Write single DRQ mask bit. */
169	CTL_W_MODE, /* Write mode register. */
170	CTL_W_CLRBPTR, /* Clear byte pointer flip-flop. */
171	CTL_W_MASTRCLR, /* Master clear. */
172	CTL_W_CLRMASK, /* Clear all DRQ mask bits. */
173	CTL_W_MASK /* Write all DRQ mask bits. */
174	};
175
176	/* DMA transfer modes. */
177	enum {
178	DMODE_DEMAND, /* Demand transfer mode. */
179	DMODE_SINGLE, /* Single transfer mode. */
180	DMODE_BLOCK, /* Block transfer mode. */
181	DMODE_CASCADE /* Cascade mode. */
182	};
183
184	/* DMA transfer types. */
185	enum {
186	DTYPE_VERIFY, /* Verify transfer type. */
187	DTYPE_WRITE, /* Write transfer type. */
188	DTYPE_READ, /* Read transfer type. */
189	DTYPE_ILLEGAL /* Undefined. */
190	};
191
192	#ifndef VBOX_DEVICE_STRUCT_TESTCASE
193
194
195	/* Convert DMA channel number (0-7) to controller number (0-1). */
196	#define DMACH2C(c) (c < 4 ? 0 : 1)
197
198	#ifdef LOG_ENABLED
199	static int const dmaChannelMap[8] = {-1, 2, 3, 1, -1, -1, -1, 0};
200	/* Map a DMA page register offset (0-7) to channel index (0-3). */
201	#define DMAPG2CX(c) (dmaChannelMap[c])
202	#endif
203
204	static int const dmaMapChannel[4] = {7, 3, 1, 2};
205	/* Map a channel index (0-3) to DMA page register offset (0-7). */
206	#define DMACX2PG(c) (dmaMapChannel[c])
207	/* Map a channel number (0-7) to DMA page register offset (0-7). */
208	#define DMACH2PG(c) (dmaMapChannel[c & 3])
209
210	/* Test the decrement bit of mode register. */
211	#define IS_MODE_DEC(c) ((c) & 0x20)
212	/* Test the auto-init bit of mode register. */
213	#define IS_MODE_AI(c) ((c) & 0x10)
214	/* Extract the transfer type bits of mode register. */
215	#define GET_MODE_XTYP(c)(((c) & 0x0c) >> 2)
216
217
218	/* Perform a master clear (reset) on a DMA controller. */
219	static void dmaClear(DMAControl *dc)
220	{
221	dc->u8Command = 0;
222	dc->u8Status = 0;
223	dc->u8Temp = 0;
224	dc->u8ModeCtr = 0;
225	dc->fHiByte = false;
226	dc->u8Mask = UINT8_MAX;
227	}
228
229
230	/** Read the byte pointer and flip it. */
231	DECLINLINE(bool) dmaReadBytePtr(DMAControl *dc)
232	{
233	bool fHighByte = !!dc->fHiByte;
234	dc->fHiByte ^= 1;
235	return fHighByte;
236	}
237
238
239	/* DMA address registers writes and reads. */
240
241	/**
242	* @callback_method_impl{FNIOMIOPORTOUT, Ports 0-7 & 0xc0-0xcf}
243	*/
244	PDMBOTHCBDECL(int) dmaWriteAddr(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT port, uint32_t u32, unsigned cb)
245	{
246	RT_NOREF(pDevIns);
247	if (cb == 1)
248	{
249	DMAControl dc = (DMAControl )pvUser;
250	DMAChannel *ch;
251	int chidx, reg, is_count;
252
253	Assert(!(u32 & ~0xff)); /* Check for garbage in high bits. */
254	reg = (port >> dc->is16bit) & 0x0f;
255	chidx = reg >> 1;
256	is_count = reg & 1;
257	ch = &dc->ChState[chidx];
258	if (dmaReadBytePtr(dc))
259	{
260	/* Write the high byte. */
261	if (is_count)
262	ch->u16BaseCount = RT_MAKE_U16(ch->u16BaseCount, u32);
263	else
264	ch->u16BaseAddr = RT_MAKE_U16(ch->u16BaseAddr, u32);
265
266	ch->u16CurCount = 0;
267	ch->u16CurAddr = ch->u16BaseAddr;
268	}
269	else
270	{
271	/* Write the low byte. */
272	if (is_count)
273	ch->u16BaseCount = RT_MAKE_U16(u32, RT_HIBYTE(ch->u16BaseCount));
274	else
275	ch->u16BaseAddr = RT_MAKE_U16(u32, RT_HIBYTE(ch->u16BaseAddr));
276	}
277	Log2(("dmaWriteAddr: port %#06x, chidx %d, data %#02x\n",
278	port, chidx, u32));
279	}
280	else
281	{
282	/* Likely a guest bug. */
283	Log(("Bad size write to count register %#x (size %d, data %#x)\n",
284	port, cb, u32));
285	}
286	return VINF_SUCCESS;
287	}
288
289
290	/**
291	* @callback_method_impl{FNIOMIOPORTIN, Ports 0-7 & 0xc0-0xcf}
292	*/
293	PDMBOTHCBDECL(int) dmaReadAddr(PPDMDEVINS pDevIns, void pvUser, RTIOPORT port, uint32_t pu32, unsigned cb)
294	{
295	RT_NOREF(pDevIns);
296	if (cb == 1)
297	{
298	DMAControl dc = (DMAControl )pvUser;
299	DMAChannel *ch;
300	int chidx, reg, val, dir;
301	int bptr;
302
303	reg = (port >> dc->is16bit) & 0x0f;
304	chidx = reg >> 1;
305	ch = &dc->ChState[chidx];
306
307	dir = IS_MODE_DEC(ch->u8Mode) ? -1 : 1;
308	if (reg & 1)
309	val = ch->u16BaseCount - ch->u16CurCount;
310	else
311	val = ch->u16CurAddr + ch->u16CurCount * dir;
312
313	bptr = dmaReadBytePtr(dc);
314	pu32 = RT_LOBYTE(val >> (bptr 8));
315
316	Log(("Count read: port %#06x, reg %#04x, data %#x\n", port, reg, val));
317	return VINF_SUCCESS;
318	}
319	return VERR_IOM_IOPORT_UNUSED;
320	}
321
322	/* DMA control registers writes and reads. */
323
324	/**
325	* @callback_method_impl{FNIOMIOPORTOUT, Ports 0x8-0xf & 0xd0-0xdf}
326	*/
327	PDMBOTHCBDECL(int) dmaWriteCtl(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT port, uint32_t u32, unsigned cb)
328	{
329	RT_NOREF(pDevIns);
330	if (cb == 1)
331	{
332	DMAControl dc = (DMAControl )pvUser;
333	int chidx = 0;
334	int reg;
335
336	reg = ((port >> dc->is16bit) & 0x0f) - 8;
337	Assert((reg >= CTL_W_CMD && reg <= CTL_W_MASK));
338	Assert(!(u32 & ~0xff)); /* Check for garbage in high bits. */
339
340	switch (reg) {
341	case CTL_W_CMD:
342	/* Unsupported commands are entirely ignored. */
343	if (u32 & CMD_UNSUPPORTED)
344	{
345	Log(("DMA command %#x is not supported, ignoring!\n", u32));
346	break;
347	}
348	dc->u8Command = u32;
349	break;
350	case CTL_W_DMAREQ:
351	chidx = u32 & 3;
352	if (u32 & 4)
353	dc->u8Status \|= 1 << (chidx + 4);
354	else
355	dc->u8Status &= ~(1 << (chidx + 4));
356	dc->u8Status &= ~(1 << chidx); /* Clear TC for channel. */
357	break;
358	case CTL_W_MASKONE:
359	chidx = u32 & 3;
360	if (u32 & 4)
361	dc->u8Mask \|= 1 << chidx;
362	else
363	dc->u8Mask &= ~(1 << chidx);
364	break;
365	case CTL_W_MODE:
366	{
367	int op, opmode;
368
369	chidx = u32 & 3;
370	op = (u32 >> 2) & 3;
371	opmode = (u32 >> 6) & 3;
372	Log2(("chidx %d, op %d, %sauto-init, %screment, opmode %d\n",
373	chidx, op, IS_MODE_AI(u32) ? "" : "no ",
374	IS_MODE_DEC(u32) ? "de" : "in", opmode));
375
376	dc->ChState[chidx].u8Mode = u32;
377	break;
378	}
379	case CTL_W_CLRBPTR:
380	dc->fHiByte = false;
381	break;
382	case CTL_W_MASTRCLR:
383	dmaClear(dc);
384	break;
385	case CTL_W_CLRMASK:
386	dc->u8Mask = 0;
387	break;
388	case CTL_W_MASK:
389	dc->u8Mask = u32;
390	break;
391	default:
392	Assert(0);
393	break;
394	}
395	Log(("dmaWriteCtl: port %#06x, chidx %d, data %#02x\n",
396	port, chidx, u32));
397	}
398	else
399	{
400	/* Likely a guest bug. */
401	Log(("Bad size write to controller register %#x (size %d, data %#x)\n",
402	port, cb, u32));
403	}
404	return VINF_SUCCESS;
405	}
406
407
408	/**
409	* @callback_method_impl{FNIOMIOPORTIN, Ports 0x8-0xf & 0xd0-0xdf}
410	*/
411	PDMBOTHCBDECL(int) dmaReadCtl(PPDMDEVINS pDevIns, void pvUser, RTIOPORT port, uint32_t pu32, unsigned cb)
412	{
413	RT_NOREF(pDevIns);
414	if (cb == 1)
415	{
416	DMAControl dc = (DMAControl )pvUser;
417	uint8_t val = 0;
418	int reg;
419
420	reg = ((port >> dc->is16bit) & 0x0f) - 8;
421	Assert((reg >= CTL_R_STAT && reg <= CTL_R_MASK));
422
423	switch (reg)
424	{
425	case CTL_R_STAT:
426	val = dc->u8Status;
427	dc->u8Status &= 0xf0; /* A read clears all TCs. */
428	break;
429	case CTL_R_DMAREQ:
430	val = (dc->u8Status >> 4) \| 0xf0;
431	break;
432	case CTL_R_CMD:
433	val = dc->u8Command;
434	break;
435	case CTL_R_MODE:
436	val = dc->ChState[dc->u8ModeCtr].u8Mode \| 3;
437	dc->u8ModeCtr = (dc->u8ModeCtr + 1) & 3;
438	break;
439	case CTL_R_SETBPTR:
440	dc->fHiByte = true;
441	break;
442	case CTL_R_TEMP:
443	val = dc->u8Temp;
444	break;
445	case CTL_R_CLRMODE:
446	dc->u8ModeCtr = 0;
447	break;
448	case CTL_R_MASK:
449	val = dc->u8Mask;
450	break;
451	default:
452	Assert(0);
453	break;
454	}
455
456	Log(("Ctrl read: port %#06x, reg %#04x, data %#x\n", port, reg, val));
457	*pu32 = val;
458
459	return VINF_SUCCESS;
460	}
461	return VERR_IOM_IOPORT_UNUSED;
462	}
463
464
465
466	/**
467	* @callback_method_impl{FNIOMIOPORTIN,
468	* DMA page registers - Ports 0x80-0x87 & 0x88-0x8f}
469	*
470	* There are 16 R/W page registers for compatibility with the IBM PC/AT; only
471	* some of those registers are used for DMA. The page register accessible via
472	* port 80h may be read to insert small delays or used as a scratch register by
473	* a BIOS.
474	*/
475	PDMBOTHCBDECL(int) dmaReadPage(PPDMDEVINS pDevIns, void pvUser, RTIOPORT port, uint32_t pu32, unsigned cb)
476	{
477	RT_NOREF(pDevIns);
478	DMAControl dc = (DMAControl )pvUser;
479	int reg;
480
481	if (cb == 1)
482	{
483	reg = port & 7;
484	*pu32 = dc->au8Page[reg];
485	Log2(("Read %#x (byte) from page register %#x (channel %d)\n",
486	*pu32, port, DMAPG2CX(reg)));
487	return VINF_SUCCESS;
488	}
489
490	if (cb == 2)
491	{
492	reg = port & 7;
493	*pu32 = dc->au8Page[reg] \| (dc->au8Page[(reg + 1) & 7] << 8);
494	Log2(("Read %#x (word) from page register %#x (channel %d)\n",
495	*pu32, port, DMAPG2CX(reg)));
496	return VINF_SUCCESS;
497	}
498
499	return VERR_IOM_IOPORT_UNUSED;
500	}
501
502
503	/**
504	* @callback_method_impl{FNIOMIOPORTOUT,
505	* DMA page registers - Ports 0x80-0x87 & 0x88-0x8f}
506	*/
507	PDMBOTHCBDECL(int) dmaWritePage(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT port, uint32_t u32, unsigned cb)
508	{
509	RT_NOREF(pDevIns);
510	DMAControl dc = (DMAControl )pvUser;
511	int reg;
512
513	if (cb == 1)
514	{
515	Assert(!(u32 & ~0xff)); /* Check for garbage in high bits. */
516	reg = port & 7;
517	dc->au8Page[reg] = u32;
518	dc->au8PageHi[reg] = 0; /* Corresponding high page cleared. */
519	Log2(("Wrote %#x to page register %#x (channel %d)\n",
520	u32, port, DMAPG2CX(reg)));
521	}
522	else if (cb == 2)
523	{
524	Assert(!(u32 & ~0xffff)); /* Check for garbage in high bits. */
525	reg = port & 7;
526	dc->au8Page[reg] = u32;
527	dc->au8PageHi[reg] = 0; /* Corresponding high page cleared. */
528	reg = (port + 1) & 7;
529	dc->au8Page[reg] = u32 >> 8;
530	dc->au8PageHi[reg] = 0; /* Corresponding high page cleared. */
531	}
532	else
533	{
534	/* Likely a guest bug. */
535	Log(("Bad size write to page register %#x (size %d, data %#x)\n",
536	port, cb, u32));
537	}
538	return VINF_SUCCESS;
539	}
540
541
542	/**
543	* @callback_method_impl{FNIOMIOPORTIN,
544	* EISA style high page registers for extending the DMA addresses to cover
545	* the entire 32-bit address space. Ports 0x480-0x487 & 0x488-0x48f}
546	*/
547	PDMBOTHCBDECL(int) dmaReadHiPage(PPDMDEVINS pDevIns, void pvUser, RTIOPORT port, uint32_t pu32, unsigned cb)
548	{
549	RT_NOREF(pDevIns);
550	if (cb == 1)
551	{
552	DMAControl dc = (DMAControl )pvUser;
553	int reg;
554
555	reg = port & 7;
556	*pu32 = dc->au8PageHi[reg];
557	Log2(("Read %#x to from high page register %#x (channel %d)\n",
558	*pu32, port, DMAPG2CX(reg)));
559	return VINF_SUCCESS;
560	}
561	return VERR_IOM_IOPORT_UNUSED;
562	}
563
564
565	/**
566	* @callback_method_impl{FNIOMIOPORTOUT, Ports 0x480-0x487 & 0x488-0x48f}
567	*/
568	PDMBOTHCBDECL(int) dmaWriteHiPage(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT port, uint32_t u32, unsigned cb)
569	{
570	RT_NOREF(pDevIns);
571	if (cb == 1)
572	{
573	DMAControl dc = (DMAControl )pvUser;
574	int reg;
575
576	Assert(!(u32 & ~0xff)); /* Check for garbage in high bits. */
577	reg = port & 7;
578	dc->au8PageHi[reg] = u32;
579	Log2(("Wrote %#x to high page register %#x (channel %d)\n",
580	u32, port, DMAPG2CX(reg)));
581	}
582	else
583	{
584	/* Likely a guest bug. */
585	Log(("Bad size write to high page register %#x (size %d, data %#x)\n",
586	port, cb, u32));
587	}
588	return VINF_SUCCESS;
589	}
590
591
592	#ifdef IN_RING3
593
594	/** Perform any pending transfers on a single DMA channel. */
595	static void dmaRunChannel(DMAState *pThis, int ctlidx, int chidx)
596	{
597	DMAControl *dc = &pThis->DMAC[ctlidx];
598	DMAChannel *ch = &dc->ChState[chidx];
599	uint32_t start_cnt, end_cnt;
600	int opmode;
601
602	opmode = (ch->u8Mode >> 6) & 3;
603
604	Log3(("DMA address %screment, mode %d\n",
605	IS_MODE_DEC(ch->u8Mode) ? "de" : "in",
606	ch->u8Mode >> 6));
607
608	/* Addresses and counts are shifted for 16-bit channels. */
609	start_cnt = ch->u16CurCount << dc->is16bit;
610	/* NB: The device is responsible for examining the DMA mode and not
611	* transferring more than it should if auto-init is not in use.
612	*/
613	end_cnt = ch->pfnXferHandler(pThis->pDevIns, ch->pvUser, (ctlidx * 4) + chidx,
614	start_cnt, (ch->u16BaseCount + 1) << dc->is16bit);
615	ch->u16CurCount = end_cnt >> dc->is16bit;
616	/* Set the TC (Terminal Count) bit if transfer was completed. */
617	if (ch->u16CurCount == ch->u16BaseCount + 1)
618	switch (opmode)
619	{
620	case DMODE_DEMAND:
621	case DMODE_SINGLE:
622	case DMODE_BLOCK:
623	dc->u8Status \|= RT_BIT(chidx);
624	Log3(("TC set for DMA channel %d\n", (ctlidx * 4) + chidx));
625	break;
626	default:
627	break;
628	}
629	Log3(("DMA position %d, size %d\n", end_cnt, (ch->u16BaseCount + 1) << dc->is16bit));
630	}
631
632	/**
633	* @interface_method_impl{PDMDMAREG,pfnRun}
634	*/
635	static DECLCALLBACK(bool) dmaRun(PPDMDEVINS pDevIns)
636	{
637	DMAState pThis = PDMINS_2_DATA(pDevIns, DMAState );
638	DMAControl *dc;
639	int ctlidx, chidx, mask;
640	PDMCritSectEnter(pDevIns->pCritSectRoR3, VERR_IGNORED);
641
642	/* Run all controllers and channels. */
643	for (ctlidx = 0; ctlidx < 2; ++ctlidx)
644	{
645	dc = &pThis->DMAC[ctlidx];
646
647	/* If controller is disabled, don't even bother. */
648	if (dc->u8Command & CMD_DISABLE)
649	continue;
650
651	for (chidx = 0; chidx < 4; ++chidx)
652	{
653	mask = 1 << chidx;
654	if (!(dc->u8Mask & mask) && (dc->u8Status & (mask << 4)))
655	dmaRunChannel(pThis, ctlidx, chidx);
656	}
657	}
658
659	PDMCritSectLeave(pDevIns->pCritSectRoR3);
660	return 0;
661	}
662
663	/**
664	* @interface_method_impl{PDMDMAREG,pfnRegister}
665	*/
666	static DECLCALLBACK(void) dmaRegister(PPDMDEVINS pDevIns, unsigned uChannel,
667	PFNDMATRANSFERHANDLER pfnTransferHandler, void *pvUser)
668	{
669	DMAState pThis = PDMINS_2_DATA(pDevIns, DMAState );
670	DMAChannel *ch = &pThis->DMAC[DMACH2C(uChannel)].ChState[uChannel & 3];
671
672	LogFlow(("dmaRegister: pThis=%p uChannel=%u pfnTransferHandler=%p pvUser=%p\n", pThis, uChannel, pfnTransferHandler, pvUser));
673
674	PDMCritSectEnter(pDevIns->pCritSectRoR3, VERR_IGNORED);
675	ch->pfnXferHandler = pfnTransferHandler;
676	ch->pvUser = pvUser;
677	PDMCritSectLeave(pDevIns->pCritSectRoR3);
678	}
679
680	/** Reverse the order of bytes in a memory buffer. */
681	static void dmaReverseBuf8(void *buf, unsigned len)
682	{
683	uint8_t pBeg, pEnd;
684	uint8_t temp;
685
686	pBeg = (uint8_t *)buf;
687	pEnd = pBeg + len - 1;
688	for (len = len / 2; len; --len)
689	{
690	temp = *pBeg;
691	pBeg++ = pEnd;
692	*pEnd-- = temp;
693	}
694	}
695
696	/** Reverse the order of words in a memory buffer. */
697	static void dmaReverseBuf16(void *buf, unsigned len)
698	{
699	uint16_t pBeg, pEnd;
700	uint16_t temp;
701
702	Assert(!(len & 1));
703	len /= 2; /* Convert to word count. */
704	pBeg = (uint16_t *)buf;
705	pEnd = pBeg + len - 1;
706	for (len = len / 2; len; --len)
707	{
708	temp = *pBeg;
709	pBeg++ = pEnd;
710	*pEnd-- = temp;
711	}
712	}
713
714	/**
715	* @interface_method_impl{PDMDMAREG,pfnReadMemory}
716	*/
717	static DECLCALLBACK(uint32_t) dmaReadMemory(PPDMDEVINS pDevIns, unsigned uChannel,
718	void *pvBuffer, uint32_t off, uint32_t cbBlock)
719	{
720	DMAState pThis = PDMINS_2_DATA(pDevIns, DMAState );
721	DMAControl *dc = &pThis->DMAC[DMACH2C(uChannel)];
722	DMAChannel *ch = &dc->ChState[uChannel & 3];
723	uint32_t page, pagehi;
724	uint32_t addr;
725
726	LogFlow(("dmaReadMemory: pThis=%p uChannel=%u pvBuffer=%p off=%u cbBlock=%u\n", pThis, uChannel, pvBuffer, off, cbBlock));
727
728	PDMCritSectEnter(pDevIns->pCritSectRoR3, VERR_IGNORED);
729
730	/* Build the address for this transfer. */
731	page = dc->au8Page[DMACH2PG(uChannel)] & ~dc->is16bit;
732	pagehi = dc->au8PageHi[DMACH2PG(uChannel)];
733	addr = (pagehi << 24) \| (page << 16) \| (ch->u16CurAddr << dc->is16bit);
734
735	if (IS_MODE_DEC(ch->u8Mode))
736	{
737	PDMDevHlpPhysRead(pThis->pDevIns, addr - off - cbBlock, pvBuffer, cbBlock);
738	if (dc->is16bit)
739	dmaReverseBuf16(pvBuffer, cbBlock);
740	else
741	dmaReverseBuf8(pvBuffer, cbBlock);
742	}
743	else
744	PDMDevHlpPhysRead(pThis->pDevIns, addr + off, pvBuffer, cbBlock);
745
746	PDMCritSectLeave(pDevIns->pCritSectRoR3);
747	return cbBlock;
748	}
749
750	/**
751	* @interface_method_impl{PDMDMAREG,pfnWriteMemory}
752	*/
753	static DECLCALLBACK(uint32_t) dmaWriteMemory(PPDMDEVINS pDevIns, unsigned uChannel,
754	const void *pvBuffer, uint32_t off, uint32_t cbBlock)
755	{
756	DMAState pThis = PDMINS_2_DATA(pDevIns, DMAState );
757	DMAControl *dc = &pThis->DMAC[DMACH2C(uChannel)];
758	DMAChannel *ch = &dc->ChState[uChannel & 3];
759	uint32_t page, pagehi;
760	uint32_t addr;
761
762	LogFlow(("dmaWriteMemory: pThis=%p uChannel=%u pvBuffer=%p off=%u cbBlock=%u\n", pThis, uChannel, pvBuffer, off, cbBlock));
763	if (GET_MODE_XTYP(ch->u8Mode) == DTYPE_VERIFY)
764	{
765	Log(("DMA verify transfer, ignoring write.\n"));
766	return cbBlock;
767	}
768
769	PDMCritSectEnter(pDevIns->pCritSectRoR3, VERR_IGNORED);
770
771	/* Build the address for this transfer. */
772	page = dc->au8Page[DMACH2PG(uChannel)] & ~dc->is16bit;
773	pagehi = dc->au8PageHi[DMACH2PG(uChannel)];
774	addr = (pagehi << 24) \| (page << 16) \| (ch->u16CurAddr << dc->is16bit);
775
776	if (IS_MODE_DEC(ch->u8Mode))
777	{
778	/// @todo This would need a temporary buffer.
779	Assert(0);
780	#if 0
781	if (dc->is16bit)
782	dmaReverseBuf16(pvBuffer, cbBlock);
783	else
784	dmaReverseBuf8(pvBuffer, cbBlock);
785	#endif
786	PDMDevHlpPhysWrite(pThis->pDevIns, addr - off - cbBlock, pvBuffer, cbBlock);
787	}
788	else
789	PDMDevHlpPhysWrite(pThis->pDevIns, addr + off, pvBuffer, cbBlock);
790
791	PDMCritSectLeave(pDevIns->pCritSectRoR3);
792	return cbBlock;
793	}
794
795	/**
796	* @interface_method_impl{PDMDMAREG,pfnSetDREQ}
797	*/
798	static DECLCALLBACK(void) dmaSetDREQ(PPDMDEVINS pDevIns, unsigned uChannel, unsigned uLevel)
799	{
800	DMAState pThis = PDMINS_2_DATA(pDevIns, DMAState );
801	DMAControl *dc = &pThis->DMAC[DMACH2C(uChannel)];
802	int chidx;
803
804	LogFlow(("dmaSetDREQ: pThis=%p uChannel=%u uLevel=%u\n", pThis, uChannel, uLevel));
805
806	PDMCritSectEnter(pDevIns->pCritSectRoR3, VERR_IGNORED);
807	chidx = uChannel & 3;
808	if (uLevel)
809	dc->u8Status \|= 1 << (chidx + 4);
810	else
811	dc->u8Status &= ~(1 << (chidx + 4));
812	PDMCritSectLeave(pDevIns->pCritSectRoR3);
813	}
814
815	/**
816	* @interface_method_impl{PDMDMAREG,pfnGetChannelMode}
817	*/
818	static DECLCALLBACK(uint8_t) dmaGetChannelMode(PPDMDEVINS pDevIns, unsigned uChannel)
819	{
820	DMAState pThis = PDMINS_2_DATA(pDevIns, DMAState );
821
822	LogFlow(("dmaGetChannelMode: pThis=%p uChannel=%u\n", pThis, uChannel));
823
824	PDMCritSectEnter(pDevIns->pCritSectRoR3, VERR_IGNORED);
825	uint8_t u8Mode = pThis->DMAC[DMACH2C(uChannel)].ChState[uChannel & 3].u8Mode;
826	PDMCritSectLeave(pDevIns->pCritSectRoR3);
827	return u8Mode;
828	}
829
830
831	/**
832	* @interface_method_impl{PDMDEVREG,pfnReset}
833	*/
834	static DECLCALLBACK(void) dmaReset(PPDMDEVINS pDevIns)
835	{
836	DMAState pThis = PDMINS_2_DATA(pDevIns, DMAState );
837
838	LogFlow(("dmaReset: pThis=%p\n", pThis));
839
840	/* NB: The page and address registers are unaffected by a reset
841	* and in an undefined state after power-up.
842	*/
843	dmaClear(&pThis->DMAC[0]);
844	dmaClear(&pThis->DMAC[1]);
845	}
846
847	/** Register DMA I/O port handlers. */
848	static int dmaIORegister(PPDMDEVINS pDevIns, bool fHighPage)
849	{
850	DMAState pThis = PDMINS_2_DATA(pDevIns, DMAState );
851	DMAControl *dc8 = &pThis->DMAC[0];
852	DMAControl *dc16 = &pThis->DMAC[1];
853	int rc;
854
855	dc8->is16bit = false;
856	dc16->is16bit = true;
857
858	/* Base and current address for each channel. */
859	rc = PDMDevHlpIOPortRegister(pThis->pDevIns, 0x00, 8, dc8, dmaWriteAddr, dmaReadAddr, NULL, NULL, "DMA8 Address");
860	AssertLogRelRCReturn(rc, rc);
861	rc = PDMDevHlpIOPortRegister(pThis->pDevIns, 0xC0, 16, dc16, dmaWriteAddr, dmaReadAddr, NULL, NULL, "DMA16 Address");
862	AssertLogRelRCReturn(rc, rc);
863
864	/* Control registers for both DMA controllers. */
865	rc = PDMDevHlpIOPortRegister(pThis->pDevIns, 0x08, 8, dc8, dmaWriteCtl, dmaReadCtl, NULL, NULL, "DMA8 Control");
866	AssertLogRelRCReturn(rc, rc);
867	rc = PDMDevHlpIOPortRegister(pThis->pDevIns, 0xD0, 16, dc16, dmaWriteCtl, dmaReadCtl, NULL, NULL, "DMA16 Control");
868	AssertLogRelRCReturn(rc, rc);
869
870	/* Page registers for each channel (plus a few unused ones). */
871	rc = PDMDevHlpIOPortRegister(pThis->pDevIns, 0x80, 8, dc8, dmaWritePage, dmaReadPage, NULL, NULL, "DMA8 Page");
872	AssertLogRelRCReturn(rc, rc);
873	rc = PDMDevHlpIOPortRegister(pThis->pDevIns, 0x88, 8, dc16, dmaWritePage, dmaReadPage, NULL, NULL, "DMA16 Page");
874	AssertLogRelRCReturn(rc, rc);
875
876	/* Optional EISA style high page registers (address bits 24-31). */
877	if (fHighPage)
878	{
879	rc = PDMDevHlpIOPortRegister(pThis->pDevIns, 0x480, 8, dc8, dmaWriteHiPage, dmaReadHiPage, NULL, NULL, "DMA8 Page High");
880	AssertLogRelRCReturn(rc, rc);
881	rc = PDMDevHlpIOPortRegister(pThis->pDevIns, 0x488, 8, dc16, dmaWriteHiPage, dmaReadHiPage, NULL, NULL, "DMA16 Page High");
882	AssertLogRelRCReturn(rc, rc);
883	}
884
885	if (pThis->fRZEnabled)
886	{
887	/*
888	* Ditto for raw-mode.
889	*/
890	RTRCPTR RCPtrDc8 = PDMINS_2_DATA_RCPTR(pDevIns) + RT_OFFSETOF(DMAState, DMAC[0]);
891	RTRCPTR RCPtrDc16 = PDMINS_2_DATA_RCPTR(pDevIns) + RT_OFFSETOF(DMAState, DMAC[1]);
892
893	/* Base and current address for each channel. */
894	rc = PDMDevHlpIOPortRegisterRC(pThis->pDevIns, 0x00, 8, RCPtrDc8, "dmaWriteAddr", "dmaReadAddr", NULL, NULL, "DMA8 Address");
895	AssertLogRelRCReturn(rc, rc);
896	rc = PDMDevHlpIOPortRegisterRC(pThis->pDevIns, 0xC0, 16, RCPtrDc16, "dmaWriteAddr", "dmaReadAddr", NULL, NULL, "DMA16 Address");
897	AssertLogRelRCReturn(rc, rc);
898
899	/* Control registers for both DMA controllers. */
900	rc = PDMDevHlpIOPortRegisterRC(pThis->pDevIns, 0x08, 8, RCPtrDc8, "dmaWriteCtl", "dmaReadCtl", NULL, NULL, "DMA8 Control");
901	AssertLogRelRCReturn(rc, rc);
902	rc = PDMDevHlpIOPortRegisterRC(pThis->pDevIns, 0xD0, 16, RCPtrDc16, "dmaWriteCtl", "dmaReadCtl", NULL, NULL, "DMA16 Control");
903	AssertLogRelRCReturn(rc, rc);
904
905	/* Page registers for each channel (plus a few unused ones). */
906	rc = PDMDevHlpIOPortRegisterRC(pThis->pDevIns, 0x80, 8, RCPtrDc8, "dmaWritePage", "dmaReadPage", NULL, NULL, "DMA8 Page");
907	AssertLogRelRCReturn(rc, rc);
908	rc = PDMDevHlpIOPortRegisterRC(pThis->pDevIns, 0x88, 8, RCPtrDc16, "dmaWritePage", "dmaReadPage", NULL, NULL, "DMA16 Page");
909	AssertLogRelRCReturn(rc, rc);
910
911	/* Optional EISA style high page registers (address bits 24-31). */
912	if (fHighPage)
913	{
914	rc = PDMDevHlpIOPortRegisterRC(pThis->pDevIns, 0x480, 8, RCPtrDc8, "dmaWriteHiPage", "dmaReadHiPage", NULL, NULL, "DMA8 Page High");
915	AssertLogRelRCReturn(rc, rc);
916	rc = PDMDevHlpIOPortRegisterRC(pThis->pDevIns, 0x488, 8, RCPtrDc16, "dmaWriteHiPage", "dmaReadHiPage", NULL, NULL, "DMA16 Page High");
917	AssertLogRelRCReturn(rc, rc);
918	}
919
920	/*
921	* Ditto for ring-0.
922	*/
923	RTR0PTR R0PtrDc8 = PDMINS_2_DATA_R0PTR(pDevIns) + RT_OFFSETOF(DMAState, DMAC[0]);
924	RTR0PTR R0PtrDc16 = PDMINS_2_DATA_R0PTR(pDevIns) + RT_OFFSETOF(DMAState, DMAC[1]);
925
926	/* Base and current address for each channel. */
927	rc = PDMDevHlpIOPortRegisterR0(pThis->pDevIns, 0x00, 8, R0PtrDc8, "dmaWriteAddr", "dmaReadAddr", NULL, NULL, "DMA8 Address");
928	AssertLogRelRCReturn(rc, rc);
929	rc = PDMDevHlpIOPortRegisterR0(pThis->pDevIns, 0xC0, 16, R0PtrDc16, "dmaWriteAddr", "dmaReadAddr", NULL, NULL, "DMA16 Address");
930	AssertLogRelRCReturn(rc, rc);
931
932	/* Control registers for both DMA controllers. */
933	rc = PDMDevHlpIOPortRegisterR0(pThis->pDevIns, 0x08, 8, R0PtrDc8, "dmaWriteCtl", "dmaReadCtl", NULL, NULL, "DMA8 Control");
934	AssertLogRelRCReturn(rc, rc);
935	rc = PDMDevHlpIOPortRegisterR0(pThis->pDevIns, 0xD0, 16, R0PtrDc16, "dmaWriteCtl", "dmaReadCtl", NULL, NULL, "DMA16 Control");
936	AssertLogRelRCReturn(rc, rc);
937
938	/* Page registers for each channel (plus a few unused ones). */
939	rc = PDMDevHlpIOPortRegisterR0(pThis->pDevIns, 0x80, 8, R0PtrDc8, "dmaWritePage", "dmaReadPage", NULL, NULL, "DMA8 Page");
940	AssertLogRelRCReturn(rc, rc);
941	rc = PDMDevHlpIOPortRegisterR0(pThis->pDevIns, 0x88, 8, R0PtrDc16, "dmaWritePage", "dmaReadPage", NULL, NULL, "DMA16 Page");
942	AssertLogRelRCReturn(rc, rc);
943
944	/* Optional EISA style high page registers (address bits 24-31). */
945	if (fHighPage)
946	{
947	rc = PDMDevHlpIOPortRegisterR0(pThis->pDevIns, 0x480, 8, R0PtrDc8, "dmaWriteHiPage", "dmaReadHiPage", NULL, NULL, "DMA8 Page High");
948	AssertLogRelRCReturn(rc, rc);
949	rc = PDMDevHlpIOPortRegisterR0(pThis->pDevIns, 0x488, 8, R0PtrDc16, "dmaWriteHiPage", "dmaReadHiPage", NULL, NULL, "DMA16 Page High");
950	AssertLogRelRCReturn(rc, rc);
951	}
952	}
953
954	return VINF_SUCCESS;
955	}
956
957	static void dmaSaveController(PSSMHANDLE pSSM, DMAControl *dc)
958	{
959	int chidx;
960
961	/* Save controller state... */
962	SSMR3PutU8(pSSM, dc->u8Command);
963	SSMR3PutU8(pSSM, dc->u8Mask);
964	SSMR3PutU8(pSSM, dc->fHiByte);
965	SSMR3PutU32(pSSM, dc->is16bit);
966	SSMR3PutU8(pSSM, dc->u8Status);
967	SSMR3PutU8(pSSM, dc->u8Temp);
968	SSMR3PutU8(pSSM, dc->u8ModeCtr);
969	SSMR3PutMem(pSSM, &dc->au8Page, sizeof(dc->au8Page));
970	SSMR3PutMem(pSSM, &dc->au8PageHi, sizeof(dc->au8PageHi));
971
972	/* ...and all four of its channels. */
973	for (chidx = 0; chidx < 4; ++chidx)
974	{
975	DMAChannel *ch = &dc->ChState[chidx];
976
977	SSMR3PutU16(pSSM, ch->u16CurAddr);
978	SSMR3PutU16(pSSM, ch->u16CurCount);
979	SSMR3PutU16(pSSM, ch->u16BaseAddr);
980	SSMR3PutU16(pSSM, ch->u16BaseCount);
981	SSMR3PutU8(pSSM, ch->u8Mode);
982	}
983	}
984
985	static int dmaLoadController(PSSMHANDLE pSSM, DMAControl *dc, int version)
986	{
987	uint8_t u8val;
988	uint32_t u32val;
989	int chidx;
990
991	SSMR3GetU8(pSSM, &dc->u8Command);
992	SSMR3GetU8(pSSM, &dc->u8Mask);
993	SSMR3GetU8(pSSM, &u8val);
994	dc->fHiByte = !!u8val;
995	SSMR3GetU32(pSSM, &dc->is16bit);
996	if (version > DMA_SAVESTATE_OLD)
997	{
998	SSMR3GetU8(pSSM, &dc->u8Status);
999	SSMR3GetU8(pSSM, &dc->u8Temp);
1000	SSMR3GetU8(pSSM, &dc->u8ModeCtr);
1001	SSMR3GetMem(pSSM, &dc->au8Page, sizeof(dc->au8Page));
1002	SSMR3GetMem(pSSM, &dc->au8PageHi, sizeof(dc->au8PageHi));
1003	}
1004
1005	for (chidx = 0; chidx < 4; ++chidx)
1006	{
1007	DMAChannel *ch = &dc->ChState[chidx];
1008
1009	if (version == DMA_SAVESTATE_OLD)
1010	{
1011	/* Convert from 17-bit to 16-bit format. */
1012	SSMR3GetU32(pSSM, &u32val);
1013	ch->u16CurAddr = u32val >> dc->is16bit;
1014	SSMR3GetU32(pSSM, &u32val);
1015	ch->u16CurCount = u32val >> dc->is16bit;
1016	}
1017	else
1018	{
1019	SSMR3GetU16(pSSM, &ch->u16CurAddr);
1020	SSMR3GetU16(pSSM, &ch->u16CurCount);
1021	}
1022	SSMR3GetU16(pSSM, &ch->u16BaseAddr);
1023	SSMR3GetU16(pSSM, &ch->u16BaseCount);
1024	SSMR3GetU8(pSSM, &ch->u8Mode);
1025	/* Convert from old save state. */
1026	if (version == DMA_SAVESTATE_OLD)
1027	{
1028	/* Remap page register contents. */
1029	SSMR3GetU8(pSSM, &u8val);
1030	dc->au8Page[DMACX2PG(chidx)] = u8val;
1031	SSMR3GetU8(pSSM, &u8val);
1032	dc->au8PageHi[DMACX2PG(chidx)] = u8val;
1033	/* Throw away dack, eop. */
1034	SSMR3GetU8(pSSM, &u8val);
1035	SSMR3GetU8(pSSM, &u8val);
1036	}
1037	}
1038	return 0;
1039	}
1040
1041	/** @callback_method_impl{FNSSMDEVSAVEEXEC} */
1042	static DECLCALLBACK(int) dmaSaveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
1043	{
1044	DMAState pThis = PDMINS_2_DATA(pDevIns, DMAState );
1045
1046	dmaSaveController(pSSM, &pThis->DMAC[0]);
1047	dmaSaveController(pSSM, &pThis->DMAC[1]);
1048	return VINF_SUCCESS;
1049	}
1050
1051	/** @callback_method_impl{FNSSMDEVLOADEXEC} */
1052	static DECLCALLBACK(int) dmaLoadExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
1053	{
1054	DMAState pThis = PDMINS_2_DATA(pDevIns, DMAState );
1055
1056	AssertMsgReturn(uVersion <= DMA_SAVESTATE_CURRENT, ("%d\n", uVersion), VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION);
1057	Assert(uPass == SSM_PASS_FINAL); NOREF(uPass);
1058
1059	dmaLoadController(pSSM, &pThis->DMAC[0], uVersion);
1060	return dmaLoadController(pSSM, &pThis->DMAC[1], uVersion);
1061	}
1062
1063	/**
1064	* @interface_method_impl{PDMDEVREG,pfnConstruct}
1065	*/
1066	static DECLCALLBACK(int) dmaConstruct(PPDMDEVINS pDevIns, int iInstance, PCFGMNODE pCfg)
1067	{
1068	RT_NOREF(iInstance);
1069	DMAState pThis = PDMINS_2_DATA(pDevIns, DMAState );
1070
1071	/*
1072	* Initialize data.
1073	*/
1074	pThis->pDevIns = pDevIns;
1075
1076	/*
1077	* Validate configuration.
1078	*/
1079	if (!CFGMR3AreValuesValid(pCfg, "RZEnabled\0"
1080	"\0")) /* "HighPageEnable\0")) */
1081	return VERR_PDM_DEVINS_UNKNOWN_CFG_VALUES;
1082
1083	bool bHighPage = false;
1084	#if 0
1085	rc = CFGMR3QueryBool(pCfg, "HighPageEnable", &bHighPage);
1086	if (RT_FAILURE (rc))
1087	return rc;
1088	#endif
1089
1090	int rc = CFGMR3QueryBoolDef(pCfg, "RZEnabled", &pThis->fRZEnabled, true);
1091	AssertLogRelRCReturn(rc, rc);
1092
1093	rc = dmaIORegister(pDevIns, bHighPage);
1094	AssertLogRelRCReturn(rc, rc);
1095
1096	dmaReset(pDevIns);
1097
1098	PDMDMACREG Reg;
1099	Reg.u32Version = PDM_DMACREG_VERSION;
1100	Reg.pfnRun = dmaRun;
1101	Reg.pfnRegister = dmaRegister;
1102	Reg.pfnReadMemory = dmaReadMemory;
1103	Reg.pfnWriteMemory = dmaWriteMemory;
1104	Reg.pfnSetDREQ = dmaSetDREQ;
1105	Reg.pfnGetChannelMode = dmaGetChannelMode;
1106
1107	rc = PDMDevHlpDMACRegister(pDevIns, &Reg, &pThis->pHlp);
1108	if (RT_FAILURE (rc))
1109	return rc;
1110
1111	rc = PDMDevHlpSSMRegister(pDevIns, DMA_SAVESTATE_CURRENT, sizeof(*pThis), dmaSaveExec, dmaLoadExec);
1112	if (RT_FAILURE(rc))
1113	return rc;
1114
1115	return VINF_SUCCESS;
1116	}
1117
1118	/**
1119	* The device registration structure.
1120	*/
1121	const PDMDEVREG g_DeviceDMA =
1122	{
1123	/* u32Version */
1124	PDM_DEVREG_VERSION,
1125	/* szName */
1126	"8237A",
1127	/* szRCMod */
1128	"VBoxDDRC.rc",
1129	/* szR0Mod */
1130	"VBoxDDR0.r0",
1131	/* pszDescription */
1132	"DMA Controller Device",
1133	/* fFlags */
1134	PDM_DEVREG_FLAGS_DEFAULT_BITS \| PDM_DEVREG_FLAGS_R0 \| PDM_DEVREG_FLAGS_RC,
1135	/* fClass */
1136	PDM_DEVREG_CLASS_DMA,
1137	/* cMaxInstances */
1138	1,
1139	/* cbInstance */
1140	sizeof(DMAState),
1141	/* pfnConstruct */
1142	dmaConstruct,
1143	/* pfnDestruct */
1144	NULL,
1145	/* pfnRelocate */
1146	NULL,
1147	/* pfnMemSetup */
1148	NULL,
1149	/* pfnPowerOn */
1150	NULL,
1151	/* pfnReset */
1152	dmaReset,
1153	/* pfnSuspend */
1154	NULL,
1155	/* pfnResume */
1156	NULL,
1157	/* pfnAttach */
1158	NULL,
1159	/* pfnDetach */
1160	NULL,
1161	/* pfnQueryInterface. */
1162	NULL,
1163	/* pfnInitComplete */
1164	NULL,
1165	/* pfnPowerOff */
1166	NULL,
1167	/* pfnSoftReset */
1168	NULL,
1169	/* u32VersionEnd */
1170	PDM_DEVREG_VERSION
1171	};
1172	#endif /* IN_RING3 */
1173	#endif /* !VBOX_DEVICE_STRUCT_TESTCASE */
1174

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source: vbox/trunk/src/VBox/Devices/PC/DevDMA.cpp@ 71210

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