[2781] | 1 | /* $Id: DevDMA.cpp 106061 2024-09-16 14:03:52Z vboxsync $ */
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[1] | 2 | /** @file
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[11248] | 3 | * DevDMA - DMA Controller Device.
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[1] | 4 | */
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| 5 |
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| 6 | /*
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[106061] | 7 | * Copyright (C) 2006-2024 Oracle and/or its affiliates.
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[1] | 8 | *
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[96407] | 9 | * This file is part of VirtualBox base platform packages, as
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| 10 | * available from https://www.virtualbox.org.
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| 11 | *
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| 12 | * This program is free software; you can redistribute it and/or
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| 13 | * modify it under the terms of the GNU General Public License
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| 14 | * as published by the Free Software Foundation, in version 3 of the
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| 15 | * License.
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| 16 | *
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| 17 | * This program is distributed in the hope that it will be useful, but
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| 18 | * WITHOUT ANY WARRANTY; without even the implied warranty of
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| 19 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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| 20 | * General Public License for more details.
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| 21 | *
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| 22 | * You should have received a copy of the GNU General Public License
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| 23 | * along with this program; if not, see <https://www.gnu.org/licenses>.
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| 24 | *
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| 25 | * SPDX-License-Identifier: GPL-3.0-only
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[69498] | 26 | * --------------------------------------------------------------------
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[1] | 27 | *
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[36204] | 28 | * This code is loosely based on:
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[1] | 29 | *
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| 30 | * QEMU DMA emulation
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| 31 | *
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| 32 | * Copyright (c) 2003 Vassili Karpov (malc)
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| 33 | *
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| 34 | * Permission is hereby granted, free of charge, to any person obtaining a copy
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| 35 | * of this software and associated documentation files (the "Software"), to deal
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| 36 | * in the Software without restriction, including without limitation the rights
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| 37 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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| 38 | * copies of the Software, and to permit persons to whom the Software is
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| 39 | * furnished to do so, subject to the following conditions:
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| 40 | *
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| 41 | * The above copyright notice and this permission notice shall be included in
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| 42 | * all copies or substantial portions of the Software.
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| 43 | *
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| 44 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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| 45 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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| 46 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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| 47 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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| 48 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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| 49 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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| 50 | * THE SOFTWARE.
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| 51 | */
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| 52 |
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[57358] | 53 |
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| 54 | /*********************************************************************************************************************************
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| 55 | * Header Files *
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| 56 | *********************************************************************************************************************************/
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[36204] | 57 | #define LOG_GROUP LOG_GROUP_DEV_DMA
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[35346] | 58 | #include <VBox/vmm/pdmdev.h>
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[1] | 59 | #include <VBox/err.h>
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| 60 |
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[81985] | 61 | #include <VBox/AssertGuest.h>
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[1] | 62 | #include <VBox/log.h>
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| 63 | #include <iprt/assert.h>
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| 64 | #include <iprt/string.h>
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| 65 |
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[35353] | 66 | #include "VBoxDD.h"
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[1] | 67 |
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| 68 |
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[44534] | 69 | /** @page pg_dev_dma DMA Overview and notes
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[36204] | 70 | *
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| 71 | * Modern PCs typically emulate AT-compatible DMA. The IBM PC/AT used dual
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| 72 | * cascaded 8237A DMA controllers, augmented with a 74LS612 memory mapper.
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| 73 | * The 8237As are 8-bit parts, only capable of addressing up to 64KB; the
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| 74 | * 74LS612 extends addressing to 24 bits. That leads to well known and
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| 75 | * inconvenient DMA limitations:
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| 76 | * - DMA can only access physical memory under the 16MB line
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| 77 | * - DMA transfers must occur within a 64KB/128KB 'page'
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| 78 | *
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| 79 | * The 16-bit DMA controller added in the PC/AT shifts all 8237A addresses
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| 80 | * left by one, including the control registers addresses. The DMA register
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| 81 | * offsets (except for the page registers) are therefore "double spaced".
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[37423] | 82 | *
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[36204] | 83 | * Due to the address shifting, the DMA controller decodes more addresses
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| 84 | * than are usually documented, with aliasing. See the ICH8 datasheet.
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| 85 | *
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| 86 | * In the IBM PC and PC/XT, DMA channel 0 was used for memory refresh, thus
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| 87 | * preventing the use of memory-to-memory DMA transfers (which use channels
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| 88 | * 0 and 1). In the PC/AT, memory-to-memory DMA was theoretically possible.
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| 89 | * However, it would transfer a single byte at a time, while the CPU can
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| 90 | * transfer two (on a 286) or four (on a 386+) bytes at a time. On many
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| 91 | * compatibles, memory-to-memory DMA is not even implemented at all, and
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| 92 | * therefore has no practical use.
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| 93 | *
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| 94 | * Auto-init mode is handled implicitly; a device's transfer handler may
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| 95 | * return an end count lower than the start count.
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| 96 | *
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| 97 | * Naming convention: 'channel' refers to a system-wide DMA channel (0-7)
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| 98 | * while 'chidx' refers to a DMA channel index within a controller (0-3).
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| 99 | *
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| 100 | * References:
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| 101 | * - IBM Personal Computer AT Technical Reference, 1984
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| 102 | * - Intel 8237A-5 Datasheet, 1993
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| 103 | * - Frank van Gilluwe, The Undocumented PC, 1994
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| 104 | * - OPTi 82C206 Data Book, 1996 (or Chips & Tech 82C206)
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| 105 | * - Intel ICH8 Datasheet, 2007
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| 106 | */
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[1] | 107 |
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| 108 |
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[36204] | 109 | /* Saved state versions. */
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| 110 | #define DMA_SAVESTATE_OLD 1 /* The original saved state. */
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| 111 | #define DMA_SAVESTATE_CURRENT 2 /* The new and improved saved state. */
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[1] | 112 |
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[36204] | 113 | /* State information for a single DMA channel. */
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| 114 | typedef struct {
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[87127] | 115 | PPDMDEVINS pDevInsHandler; /**< The device instance the channel is associated with. */
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[71210] | 116 | RTR3PTR pvUser; /* User specific context. */
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| 117 | R3PTRTYPE(PFNDMATRANSFERHANDLER) pfnXferHandler; /* Transfer handler for channel. */
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| 118 | uint16_t u16BaseAddr; /* Base address for transfers. */
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| 119 | uint16_t u16BaseCount; /* Base count for transfers. */
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| 120 | uint16_t u16CurAddr; /* Current address. */
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| 121 | uint16_t u16CurCount; /* Current count. */
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| 122 | uint8_t u8Mode; /* Channel mode. */
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[71216] | 123 | uint8_t abPadding[7];
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[81985] | 124 | } DMAChannel, DMACHANNEL;
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| 125 | typedef DMACHANNEL *PDMACHANNEL;
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[1] | 126 |
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[36204] | 127 | /* State information for a DMA controller (DMA8 or DMA16). */
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| 128 | typedef struct {
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| 129 | DMAChannel ChState[4]; /* Per-channel state. */
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| 130 | uint8_t au8Page[8]; /* Page registers (A16-A23). */
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| 131 | uint8_t au8PageHi[8]; /* High page registers (A24-A31). */
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| 132 | uint8_t u8Command; /* Command register. */
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| 133 | uint8_t u8Status; /* Status register. */
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| 134 | uint8_t u8Mask; /* Mask register. */
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| 135 | uint8_t u8Temp; /* Temporary (mem/mem) register. */
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| 136 | uint8_t u8ModeCtr; /* Mode register counter for reads. */
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[44534] | 137 | bool fHiByte; /* Byte pointer (T/F -> high/low). */
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[71218] | 138 | uint8_t abPadding0[2];
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[36204] | 139 | uint32_t is16bit; /* True for 16-bit DMA. */
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[71218] | 140 | uint8_t abPadding1[4];
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[81984] | 141 | /** The base abd current address I/O port registration. */
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| 142 | IOMIOPORTHANDLE hIoPortBase;
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| 143 | /** The control register I/O port registration. */
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| 144 | IOMIOPORTHANDLE hIoPortCtl;
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| 145 | /** The page registers I/O port registration. */
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| 146 | IOMIOPORTHANDLE hIoPortPage;
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| 147 | /** The EISA style high page registers I/O port registration. */
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| 148 | IOMIOPORTHANDLE hIoPortHi;
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| 149 | } DMAControl, DMACONTROLLER;
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| 150 | /** Pointer to the shared DMA controller state. */
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| 151 | typedef DMACONTROLLER *PDMACONTROLLER;
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[1] | 152 |
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[36204] | 153 | /* Complete DMA state information. */
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| 154 | typedef struct {
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[81979] | 155 | DMAControl DMAC[2]; /* Two DMA controllers. */
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[71210] | 156 | PPDMDEVINSR3 pDevIns; /* Device instance. */
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| 157 | R3PTRTYPE(PCPDMDMACHLP) pHlp; /* PDM DMA helpers. */
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[81985] | 158 | STAMPROFILE StatRun;
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[81979] | 159 | } DMAState, DMASTATE;
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| 160 | /** Pointer to the shared DMA state information. */
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| 161 | typedef DMASTATE *PDMASTATE;
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[1] | 162 |
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[36204] | 163 | /* DMA command register bits. */
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| 164 | enum {
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| 165 | CMD_MEMTOMEM = 0x01, /* Enable mem-to-mem trasfers. */
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| 166 | CMD_ADRHOLD = 0x02, /* Address hold for mem-to-mem. */
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| 167 | CMD_DISABLE = 0x04, /* Disable controller. */
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| 168 | CMD_COMPRTIME = 0x08, /* Compressed timing. */
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| 169 | CMD_ROTPRIO = 0x10, /* Rotating priority. */
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| 170 | CMD_EXTWR = 0x20, /* Extended write. */
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| 171 | CMD_DREQHI = 0x40, /* DREQ is active high if set. */
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| 172 | CMD_DACKHI = 0x80, /* DACK is active high if set. */
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| 173 | CMD_UNSUPPORTED = CMD_MEMTOMEM | CMD_ADRHOLD | CMD_COMPRTIME
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| 174 | | CMD_EXTWR | CMD_DREQHI | CMD_DACKHI
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[1] | 175 | };
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| 176 |
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[36204] | 177 | /* DMA control register offsets for read accesses. */
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| 178 | enum {
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| 179 | CTL_R_STAT, /* Read status registers. */
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| 180 | CTL_R_DMAREQ, /* Read DRQ register. */
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| 181 | CTL_R_CMD, /* Read command register. */
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| 182 | CTL_R_MODE, /* Read mode register. */
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| 183 | CTL_R_SETBPTR, /* Set byte pointer flip-flop. */
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| 184 | CTL_R_TEMP, /* Read temporary register. */
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| 185 | CTL_R_CLRMODE, /* Clear mode register counter. */
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| 186 | CTL_R_MASK /* Read all DRQ mask bits. */
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| 187 | };
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[1] | 188 |
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[36204] | 189 | /* DMA control register offsets for read accesses. */
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| 190 | enum {
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| 191 | CTL_W_CMD, /* Write command register. */
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| 192 | CTL_W_DMAREQ, /* Write DRQ register. */
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| 193 | CTL_W_MASKONE, /* Write single DRQ mask bit. */
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| 194 | CTL_W_MODE, /* Write mode register. */
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| 195 | CTL_W_CLRBPTR, /* Clear byte pointer flip-flop. */
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| 196 | CTL_W_MASTRCLR, /* Master clear. */
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| 197 | CTL_W_CLRMASK, /* Clear all DRQ mask bits. */
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| 198 | CTL_W_MASK /* Write all DRQ mask bits. */
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[1] | 199 | };
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| 200 |
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[46499] | 201 | /* DMA transfer modes. */
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| 202 | enum {
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| 203 | DMODE_DEMAND, /* Demand transfer mode. */
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| 204 | DMODE_SINGLE, /* Single transfer mode. */
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| 205 | DMODE_BLOCK, /* Block transfer mode. */
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| 206 | DMODE_CASCADE /* Cascade mode. */
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| 207 | };
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| 208 |
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[48046] | 209 | /* DMA transfer types. */
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| 210 | enum {
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| 211 | DTYPE_VERIFY, /* Verify transfer type. */
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| 212 | DTYPE_WRITE, /* Write transfer type. */
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| 213 | DTYPE_READ, /* Read transfer type. */
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| 214 | DTYPE_ILLEGAL /* Undefined. */
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| 215 | };
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| 216 |
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[71210] | 217 | #ifndef VBOX_DEVICE_STRUCT_TESTCASE
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| 218 |
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| 219 |
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[36204] | 220 | /* Convert DMA channel number (0-7) to controller number (0-1). */
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[71214] | 221 | #define DMACH2C(c) (c < 4 ? 0 : 1)
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[1] | 222 |
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[63369] | 223 | #ifdef LOG_ENABLED
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[71214] | 224 | static int const g_aiDmaChannelMap[8] = {-1, 2, 3, 1, -1, -1, -1, 0};
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[36204] | 225 | /* Map a DMA page register offset (0-7) to channel index (0-3). */
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[71214] | 226 | # define DMAPG2CX(c) (g_aiDmaChannelMap[c])
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[63369] | 227 | #endif
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[1] | 228 |
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[71214] | 229 | #ifdef IN_RING3
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| 230 | static int const g_aiDmaMapChannel[4] = {7, 3, 1, 2};
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[36204] | 231 | /* Map a channel index (0-3) to DMA page register offset (0-7). */
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[71214] | 232 | # define DMACX2PG(c) (g_aiDmaMapChannel[c])
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[36204] | 233 | /* Map a channel number (0-7) to DMA page register offset (0-7). */
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[71214] | 234 | # define DMACH2PG(c) (g_aiDmaMapChannel[c & 3])
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| 235 | #endif
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[1] | 236 |
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[36204] | 237 | /* Test the decrement bit of mode register. */
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[71214] | 238 | #define IS_MODE_DEC(c) ((c) & 0x20)
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[36204] | 239 | /* Test the auto-init bit of mode register. */
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[71214] | 240 | #define IS_MODE_AI(c) ((c) & 0x10)
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[48046] | 241 | /* Extract the transfer type bits of mode register. */
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[71214] | 242 | #define GET_MODE_XTYP(c) (((c) & 0x0c) >> 2)
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[1] | 243 |
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[62903] | 244 |
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[36204] | 245 | /* Perform a master clear (reset) on a DMA controller. */
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| 246 | static void dmaClear(DMAControl *dc)
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[1] | 247 | {
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[36204] | 248 | dc->u8Command = 0;
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| 249 | dc->u8Status = 0;
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| 250 | dc->u8Temp = 0;
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| 251 | dc->u8ModeCtr = 0;
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[44534] | 252 | dc->fHiByte = false;
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[62903] | 253 | dc->u8Mask = UINT8_MAX;
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[1] | 254 | }
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| 255 |
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[62903] | 256 |
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| 257 | /** Read the byte pointer and flip it. */
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| 258 | DECLINLINE(bool) dmaReadBytePtr(DMAControl *dc)
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[1] | 259 | {
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[71210] | 260 | bool fHighByte = !!dc->fHiByte;
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[44534] | 261 | dc->fHiByte ^= 1;
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[71210] | 262 | return fHighByte;
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[1] | 263 | }
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| 264 |
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[62903] | 265 |
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[36204] | 266 | /* DMA address registers writes and reads. */
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| 267 |
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[62903] | 268 | /**
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| 269 | * @callback_method_impl{FNIOMIOPORTOUT, Ports 0-7 & 0xc0-0xcf}
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| 270 | */
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[81984] | 271 | static DECLCALLBACK(VBOXSTRICTRC) dmaWriteAddr(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT offPort, uint32_t u32, unsigned cb)
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[1] | 272 | {
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[81986] | 273 | PDMACONTROLLER dc = (PDMACONTROLLER)pvUser;
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[62903] | 274 | RT_NOREF(pDevIns);
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[36204] | 275 | if (cb == 1)
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| 276 | {
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[81985] | 277 | unsigned const reg = (offPort >> dc->is16bit) & 0x0f;
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| 278 | unsigned const chidx = reg >> 1;
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| 279 | unsigned const is_count = reg & 1;
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| 280 | PDMACHANNEL ch = &RT_SAFE_SUBSCRIPT(dc->ChState, chidx);
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| 281 | Assert(!(u32 & ~0xff)); /* Check for garbage in high bits. */
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[1] | 282 |
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[36204] | 283 | if (dmaReadBytePtr(dc))
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| 284 | {
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| 285 | /* Write the high byte. */
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| 286 | if (is_count)
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| 287 | ch->u16BaseCount = RT_MAKE_U16(ch->u16BaseCount, u32);
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| 288 | else
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| 289 | ch->u16BaseAddr = RT_MAKE_U16(ch->u16BaseAddr, u32);
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[78572] | 290 |
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| 291 | ch->u16CurCount = 0;
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| 292 | ch->u16CurAddr = ch->u16BaseAddr;
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[36204] | 293 | }
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| 294 | else
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| 295 | {
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| 296 | /* Write the low byte. */
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| 297 | if (is_count)
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| 298 | ch->u16BaseCount = RT_MAKE_U16(u32, RT_HIBYTE(ch->u16BaseCount));
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| 299 | else
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| 300 | ch->u16BaseAddr = RT_MAKE_U16(u32, RT_HIBYTE(ch->u16BaseAddr));
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| 301 | }
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[81986] | 302 | Log2(("dmaWriteAddr/%u: offPort %#06x, chidx %d, data %#02x\n", dc->is16bit, offPort, chidx, u32));
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[1] | 303 | }
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[36204] | 304 | else
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| 305 | {
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| 306 | /* Likely a guest bug. */
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[81986] | 307 | Log(("dmaWriteAddr/%u: Bad size write to count register %#x (size %d, data %#x)\n", dc->is16bit, offPort, cb, u32));
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[36204] | 308 | }
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| 309 | return VINF_SUCCESS;
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[1] | 310 | }
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| 311 |
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[62903] | 312 |
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| 313 | /**
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| 314 | * @callback_method_impl{FNIOMIOPORTIN, Ports 0-7 & 0xc0-0xcf}
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| 315 | */
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[81984] | 316 | static DECLCALLBACK(VBOXSTRICTRC) dmaReadAddr(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT offPort, uint32_t *pu32, unsigned cb)
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[1] | 317 | {
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[62903] | 318 | RT_NOREF(pDevIns);
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[36204] | 319 | if (cb == 1)
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| 320 | {
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[81985] | 321 | PDMACONTROLLER dc = (PDMACONTROLLER)pvUser;
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| 322 | unsigned const reg = (offPort >> dc->is16bit) & 0x0f;
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| 323 | unsigned const chidx = reg >> 1;
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| 324 | PDMACHANNEL ch = &RT_SAFE_SUBSCRIPT(dc->ChState, chidx);
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| 325 | int const dir = IS_MODE_DEC(ch->u8Mode) ? -1 : 1;
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| 326 | int val;
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| 327 | int bptr;
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[1] | 328 |
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[36204] | 329 | if (reg & 1)
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| 330 | val = ch->u16BaseCount - ch->u16CurCount;
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| 331 | else
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| 332 | val = ch->u16CurAddr + ch->u16CurCount * dir;
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[1] | 333 |
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[36204] | 334 | bptr = dmaReadBytePtr(dc);
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| 335 | *pu32 = RT_LOBYTE(val >> (bptr * 8));
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[1] | 336 |
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[81986] | 337 | Log(("dmaReadAddr/%u: Count read: offPort %#06x, reg %#04x, data %#x\n", dc->is16bit, offPort, reg, val));
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[36204] | 338 | return VINF_SUCCESS;
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| 339 | }
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[62903] | 340 | return VERR_IOM_IOPORT_UNUSED;
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[1] | 341 | }
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| 342 |
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[36204] | 343 | /* DMA control registers writes and reads. */
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[1] | 344 |
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[62903] | 345 | /**
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| 346 | * @callback_method_impl{FNIOMIOPORTOUT, Ports 0x8-0xf & 0xd0-0xdf}
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| 347 | */
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[81984] | 348 | static DECLCALLBACK(VBOXSTRICTRC) dmaWriteCtl(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT offPort, uint32_t u32, unsigned cb)
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[1] | 349 | {
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[81986] | 350 | PDMACONTROLLER dc = (PDMACONTROLLER)pvUser;
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[62903] | 351 | RT_NOREF(pDevIns);
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[36204] | 352 | if (cb == 1)
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| 353 | {
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[81985] | 354 | unsigned chidx = 0;
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[81984] | 355 | unsigned const reg = (offPort >> dc->is16bit) & 0x0f;
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| 356 | Assert((int)reg >= CTL_W_CMD && reg <= CTL_W_MASK);
|
---|
[36204] | 357 | Assert(!(u32 & ~0xff)); /* Check for garbage in high bits. */
|
---|
[1] | 358 |
|
---|
[36204] | 359 | switch (reg) {
|
---|
| 360 | case CTL_W_CMD:
|
---|
| 361 | /* Unsupported commands are entirely ignored. */
|
---|
| 362 | if (u32 & CMD_UNSUPPORTED)
|
---|
| 363 | {
|
---|
[81986] | 364 | Log(("dmaWriteCtl/%u: DMA command %#x is not supported, ignoring!\n", dc->is16bit, u32));
|
---|
[36204] | 365 | break;
|
---|
| 366 | }
|
---|
| 367 | dc->u8Command = u32;
|
---|
| 368 | break;
|
---|
| 369 | case CTL_W_DMAREQ:
|
---|
| 370 | chidx = u32 & 3;
|
---|
| 371 | if (u32 & 4)
|
---|
| 372 | dc->u8Status |= 1 << (chidx + 4);
|
---|
| 373 | else
|
---|
| 374 | dc->u8Status &= ~(1 << (chidx + 4));
|
---|
| 375 | dc->u8Status &= ~(1 << chidx); /* Clear TC for channel. */
|
---|
| 376 | break;
|
---|
| 377 | case CTL_W_MASKONE:
|
---|
| 378 | chidx = u32 & 3;
|
---|
| 379 | if (u32 & 4)
|
---|
| 380 | dc->u8Mask |= 1 << chidx;
|
---|
| 381 | else
|
---|
| 382 | dc->u8Mask &= ~(1 << chidx);
|
---|
| 383 | break;
|
---|
| 384 | case CTL_W_MODE:
|
---|
[81985] | 385 | chidx = u32 & 3;
|
---|
| 386 | dc->ChState[chidx].u8Mode = u32;
|
---|
[81986] | 387 | Log2(("dmaWriteCtl/%u: chidx %d, op %d, %sauto-init, %screment, opmode %d\n", dc->is16bit,
|
---|
[81985] | 388 | chidx, (u32 >> 2) & 3, IS_MODE_AI(u32) ? "" : "no ", IS_MODE_DEC(u32) ? "de" : "in", (u32 >> 6) & 3));
|
---|
| 389 | break;
|
---|
[36204] | 390 | case CTL_W_CLRBPTR:
|
---|
[44534] | 391 | dc->fHiByte = false;
|
---|
[1] | 392 | break;
|
---|
[36204] | 393 | case CTL_W_MASTRCLR:
|
---|
| 394 | dmaClear(dc);
|
---|
| 395 | break;
|
---|
| 396 | case CTL_W_CLRMASK:
|
---|
| 397 | dc->u8Mask = 0;
|
---|
| 398 | break;
|
---|
| 399 | case CTL_W_MASK:
|
---|
| 400 | dc->u8Mask = u32;
|
---|
| 401 | break;
|
---|
| 402 | default:
|
---|
[81985] | 403 | ASSERT_GUEST_MSG_FAILED(("reg=%u\n", reg));
|
---|
[36204] | 404 | break;
|
---|
[1] | 405 | }
|
---|
[81986] | 406 | Log(("dmaWriteCtl/%u: offPort %#06x, chidx %d, data %#02x\n", dc->is16bit, offPort, chidx, u32));
|
---|
[36204] | 407 | }
|
---|
| 408 | else
|
---|
| 409 | {
|
---|
| 410 | /* Likely a guest bug. */
|
---|
[81986] | 411 | Log(("dmaWriteCtl/%u: Bad size write to controller register %#x (size %d, data %#x)\n", dc->is16bit, offPort, cb, u32));
|
---|
[36204] | 412 | }
|
---|
| 413 | return VINF_SUCCESS;
|
---|
| 414 | }
|
---|
[1] | 415 |
|
---|
[62903] | 416 |
|
---|
| 417 | /**
|
---|
| 418 | * @callback_method_impl{FNIOMIOPORTIN, Ports 0x8-0xf & 0xd0-0xdf}
|
---|
| 419 | */
|
---|
[81984] | 420 | static DECLCALLBACK(VBOXSTRICTRC) dmaReadCtl(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT offPort, uint32_t *pu32, unsigned cb)
|
---|
[36204] | 421 | {
|
---|
[62903] | 422 | RT_NOREF(pDevIns);
|
---|
[36204] | 423 | if (cb == 1)
|
---|
| 424 | {
|
---|
[81985] | 425 | PDMACONTROLLER dc = (PDMACONTROLLER)pvUser;
|
---|
| 426 | uint8_t val = 0;
|
---|
[1] | 427 |
|
---|
[81984] | 428 | unsigned const reg = (offPort >> dc->is16bit) & 0x0f;
|
---|
| 429 | Assert((int)reg >= CTL_R_STAT && reg <= CTL_R_MASK);
|
---|
[1] | 430 |
|
---|
[44534] | 431 | switch (reg)
|
---|
| 432 | {
|
---|
| 433 | case CTL_R_STAT:
|
---|
| 434 | val = dc->u8Status;
|
---|
| 435 | dc->u8Status &= 0xf0; /* A read clears all TCs. */
|
---|
| 436 | break;
|
---|
| 437 | case CTL_R_DMAREQ:
|
---|
| 438 | val = (dc->u8Status >> 4) | 0xf0;
|
---|
| 439 | break;
|
---|
| 440 | case CTL_R_CMD:
|
---|
| 441 | val = dc->u8Command;
|
---|
| 442 | break;
|
---|
| 443 | case CTL_R_MODE:
|
---|
[81985] | 444 | val = RT_SAFE_SUBSCRIPT(dc->ChState, dc->u8ModeCtr).u8Mode | 3;
|
---|
[44534] | 445 | dc->u8ModeCtr = (dc->u8ModeCtr + 1) & 3;
|
---|
[65916] | 446 | break;
|
---|
[44534] | 447 | case CTL_R_SETBPTR:
|
---|
| 448 | dc->fHiByte = true;
|
---|
| 449 | break;
|
---|
| 450 | case CTL_R_TEMP:
|
---|
| 451 | val = dc->u8Temp;
|
---|
| 452 | break;
|
---|
| 453 | case CTL_R_CLRMODE:
|
---|
| 454 | dc->u8ModeCtr = 0;
|
---|
| 455 | break;
|
---|
| 456 | case CTL_R_MASK:
|
---|
| 457 | val = dc->u8Mask;
|
---|
| 458 | break;
|
---|
| 459 | default:
|
---|
| 460 | Assert(0);
|
---|
| 461 | break;
|
---|
[36204] | 462 | }
|
---|
[1] | 463 |
|
---|
[81986] | 464 | Log(("dmaReadCtl/%u: Ctrl read: offPort %#06x, reg %#04x, data %#x\n", dc->is16bit, offPort, reg, val));
|
---|
[36204] | 465 | *pu32 = val;
|
---|
[1] | 466 |
|
---|
[36204] | 467 | return VINF_SUCCESS;
|
---|
[1] | 468 | }
|
---|
[44534] | 469 | return VERR_IOM_IOPORT_UNUSED;
|
---|
[1] | 470 | }
|
---|
| 471 |
|
---|
[62903] | 472 |
|
---|
[71210] | 473 |
|
---|
[62903] | 474 | /**
|
---|
| 475 | * @callback_method_impl{FNIOMIOPORTIN,
|
---|
| 476 | * DMA page registers - Ports 0x80-0x87 & 0x88-0x8f}
|
---|
| 477 | *
|
---|
| 478 | * There are 16 R/W page registers for compatibility with the IBM PC/AT; only
|
---|
| 479 | * some of those registers are used for DMA. The page register accessible via
|
---|
| 480 | * port 80h may be read to insert small delays or used as a scratch register by
|
---|
| 481 | * a BIOS.
|
---|
| 482 | */
|
---|
[81984] | 483 | static DECLCALLBACK(VBOXSTRICTRC) dmaReadPage(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT offPort, uint32_t *pu32, unsigned cb)
|
---|
[1] | 484 | {
|
---|
[62903] | 485 | RT_NOREF(pDevIns);
|
---|
[81985] | 486 | PDMACONTROLLER dc = (PDMACONTROLLER)pvUser;
|
---|
| 487 | int reg;
|
---|
[38188] | 488 |
|
---|
[37423] | 489 | if (cb == 1)
|
---|
[36204] | 490 | {
|
---|
[81984] | 491 | reg = offPort & 7;
|
---|
[36204] | 492 | *pu32 = dc->au8Page[reg];
|
---|
[81986] | 493 | Log2(("dmaReadPage/%u: Read %#x (byte) from page register %#x (channel %d)\n", dc->is16bit, *pu32, offPort, DMAPG2CX(reg)));
|
---|
[36204] | 494 | return VINF_SUCCESS;
|
---|
[48947] | 495 | }
|
---|
[44534] | 496 |
|
---|
| 497 | if (cb == 2)
|
---|
[38188] | 498 | {
|
---|
[81984] | 499 | reg = offPort & 7;
|
---|
[38188] | 500 | *pu32 = dc->au8Page[reg] | (dc->au8Page[(reg + 1) & 7] << 8);
|
---|
[81986] | 501 | Log2(("dmaReadPage/%u: Read %#x (word) from page register %#x (channel %d)\n", dc->is16bit, *pu32, offPort, DMAPG2CX(reg)));
|
---|
[38188] | 502 | return VINF_SUCCESS;
|
---|
[1] | 503 | }
|
---|
[44534] | 504 |
|
---|
| 505 | return VERR_IOM_IOPORT_UNUSED;
|
---|
[1] | 506 | }
|
---|
| 507 |
|
---|
[62903] | 508 |
|
---|
| 509 | /**
|
---|
| 510 | * @callback_method_impl{FNIOMIOPORTOUT,
|
---|
| 511 | * DMA page registers - Ports 0x80-0x87 & 0x88-0x8f}
|
---|
| 512 | */
|
---|
[81984] | 513 | static DECLCALLBACK(VBOXSTRICTRC) dmaWritePage(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT offPort, uint32_t u32, unsigned cb)
|
---|
[1] | 514 | {
|
---|
[62903] | 515 | RT_NOREF(pDevIns);
|
---|
[81985] | 516 | PDMACONTROLLER dc = (PDMACONTROLLER)pvUser;
|
---|
| 517 | unsigned reg;
|
---|
[38188] | 518 |
|
---|
[36204] | 519 | if (cb == 1)
|
---|
| 520 | {
|
---|
[38221] | 521 | Assert(!(u32 & ~0xff)); /* Check for garbage in high bits. */
|
---|
[81984] | 522 | reg = offPort & 7;
|
---|
[36204] | 523 | dc->au8Page[reg] = u32;
|
---|
| 524 | dc->au8PageHi[reg] = 0; /* Corresponding high page cleared. */
|
---|
[81986] | 525 | Log2(("dmaWritePage/%u: Wrote %#x to page register %#x (channel %d)\n", dc->is16bit, u32, offPort, DMAPG2CX(reg)));
|
---|
[36204] | 526 | }
|
---|
[48947] | 527 | else if (cb == 2)
|
---|
[38188] | 528 | {
|
---|
[38221] | 529 | Assert(!(u32 & ~0xffff)); /* Check for garbage in high bits. */
|
---|
[81984] | 530 | reg = offPort & 7;
|
---|
[38188] | 531 | dc->au8Page[reg] = u32;
|
---|
| 532 | dc->au8PageHi[reg] = 0; /* Corresponding high page cleared. */
|
---|
[81984] | 533 | reg = (offPort + 1) & 7;
|
---|
[38188] | 534 | dc->au8Page[reg] = u32 >> 8;
|
---|
| 535 | dc->au8PageHi[reg] = 0; /* Corresponding high page cleared. */
|
---|
| 536 | }
|
---|
[36204] | 537 | else
|
---|
| 538 | {
|
---|
| 539 | /* Likely a guest bug. */
|
---|
[81986] | 540 | Log(("dmaWritePage/%u: Bad size write to page register %#x (size %d, data %#x)\n", dc->is16bit, offPort, cb, u32));
|
---|
[36204] | 541 | }
|
---|
| 542 | return VINF_SUCCESS;
|
---|
[1] | 543 | }
|
---|
| 544 |
|
---|
[62903] | 545 |
|
---|
[44534] | 546 | /**
|
---|
[62903] | 547 | * @callback_method_impl{FNIOMIOPORTIN,
|
---|
[64369] | 548 | * EISA style high page registers for extending the DMA addresses to cover
|
---|
[62903] | 549 | * the entire 32-bit address space. Ports 0x480-0x487 & 0x488-0x48f}
|
---|
[36204] | 550 | */
|
---|
[81984] | 551 | static DECLCALLBACK(VBOXSTRICTRC) dmaReadHiPage(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT offPort, uint32_t *pu32, unsigned cb)
|
---|
[1] | 552 | {
|
---|
[62903] | 553 | RT_NOREF(pDevIns);
|
---|
[37423] | 554 | if (cb == 1)
|
---|
[36204] | 555 | {
|
---|
[81985] | 556 | PDMACONTROLLER dc = (PDMACONTROLLER)pvUser;
|
---|
| 557 | unsigned const reg = offPort & 7;
|
---|
[1] | 558 |
|
---|
[36204] | 559 | *pu32 = dc->au8PageHi[reg];
|
---|
[81986] | 560 | Log2(("dmaReadHiPage/%u: Read %#x to from high page register %#x (channel %d)\n", dc->is16bit, *pu32, offPort, DMAPG2CX(reg)));
|
---|
[36204] | 561 | return VINF_SUCCESS;
|
---|
| 562 | }
|
---|
[44534] | 563 | return VERR_IOM_IOPORT_UNUSED;
|
---|
[1] | 564 | }
|
---|
| 565 |
|
---|
[62903] | 566 |
|
---|
| 567 | /**
|
---|
| 568 | * @callback_method_impl{FNIOMIOPORTOUT, Ports 0x480-0x487 & 0x488-0x48f}
|
---|
| 569 | */
|
---|
[81984] | 570 | static DECLCALLBACK(VBOXSTRICTRC) dmaWriteHiPage(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT offPort, uint32_t u32, unsigned cb)
|
---|
[1] | 571 | {
|
---|
[62903] | 572 | RT_NOREF(pDevIns);
|
---|
[81986] | 573 | PDMACONTROLLER dc = (PDMACONTROLLER)pvUser;
|
---|
[36204] | 574 | if (cb == 1)
|
---|
| 575 | {
|
---|
[81985] | 576 | unsigned const reg = offPort & 7;
|
---|
[1] | 577 |
|
---|
[36204] | 578 | Assert(!(u32 & ~0xff)); /* Check for garbage in high bits. */
|
---|
| 579 | dc->au8PageHi[reg] = u32;
|
---|
[81986] | 580 | Log2(("dmaWriteHiPage/%u: Wrote %#x to high page register %#x (channel %d)\n", dc->is16bit, u32, offPort, DMAPG2CX(reg)));
|
---|
[36204] | 581 | }
|
---|
| 582 | else
|
---|
| 583 | {
|
---|
| 584 | /* Likely a guest bug. */
|
---|
[81989] | 585 | Log(("dmaWriteHiPage/%u: Bad size write to high page register %#x (size %d, data %#x)\n", dc->is16bit, offPort, cb, u32));
|
---|
[36204] | 586 | }
|
---|
| 587 | return VINF_SUCCESS;
|
---|
[1] | 588 | }
|
---|
| 589 |
|
---|
[71210] | 590 |
|
---|
| 591 | #ifdef IN_RING3
|
---|
| 592 |
|
---|
[44534] | 593 | /** Perform any pending transfers on a single DMA channel. */
|
---|
[81990] | 594 | static void dmaR3RunChannel(DMAState *pThis, int ctlidx, int chidx)
|
---|
[1] | 595 | {
|
---|
[44534] | 596 | DMAControl *dc = &pThis->DMAC[ctlidx];
|
---|
[36204] | 597 | DMAChannel *ch = &dc->ChState[chidx];
|
---|
| 598 | uint32_t start_cnt, end_cnt;
|
---|
| 599 | int opmode;
|
---|
[1] | 600 |
|
---|
[36204] | 601 | opmode = (ch->u8Mode >> 6) & 3;
|
---|
[1] | 602 |
|
---|
[81985] | 603 | Log3(("DMA address %screment, mode %d\n", IS_MODE_DEC(ch->u8Mode) ? "de" : "in", ch->u8Mode >> 6));
|
---|
[87127] | 604 | AssertReturnVoid(ch->pfnXferHandler);
|
---|
[1] | 605 |
|
---|
[36204] | 606 | /* Addresses and counts are shifted for 16-bit channels. */
|
---|
| 607 | start_cnt = ch->u16CurCount << dc->is16bit;
|
---|
[46499] | 608 | /* NB: The device is responsible for examining the DMA mode and not
|
---|
| 609 | * transferring more than it should if auto-init is not in use.
|
---|
| 610 | */
|
---|
[87127] | 611 | end_cnt = ch->pfnXferHandler(ch->pDevInsHandler, ch->pvUser, (ctlidx * 4) + chidx,
|
---|
[36204] | 612 | start_cnt, (ch->u16BaseCount + 1) << dc->is16bit);
|
---|
| 613 | ch->u16CurCount = end_cnt >> dc->is16bit;
|
---|
[46499] | 614 | /* Set the TC (Terminal Count) bit if transfer was completed. */
|
---|
| 615 | if (ch->u16CurCount == ch->u16BaseCount + 1)
|
---|
[48947] | 616 | switch (opmode)
|
---|
[46499] | 617 | {
|
---|
| 618 | case DMODE_DEMAND:
|
---|
| 619 | case DMODE_SINGLE:
|
---|
| 620 | case DMODE_BLOCK:
|
---|
[78572] | 621 | dc->u8Status |= RT_BIT(chidx);
|
---|
| 622 | Log3(("TC set for DMA channel %d\n", (ctlidx * 4) + chidx));
|
---|
[46499] | 623 | break;
|
---|
| 624 | default:
|
---|
| 625 | break;
|
---|
| 626 | }
|
---|
[36204] | 627 | Log3(("DMA position %d, size %d\n", end_cnt, (ch->u16BaseCount + 1) << dc->is16bit));
|
---|
[1] | 628 | }
|
---|
| 629 |
|
---|
[44534] | 630 | /**
|
---|
| 631 | * @interface_method_impl{PDMDMAREG,pfnRun}
|
---|
| 632 | */
|
---|
[81986] | 633 | static DECLCALLBACK(bool) dmaR3Run(PPDMDEVINS pDevIns)
|
---|
[1] | 634 | {
|
---|
[81979] | 635 | DMAState *pThis = PDMDEVINS_2_DATA(pDevIns, PDMASTATE);
|
---|
[36204] | 636 | DMAControl *dc;
|
---|
[81988] | 637 | int chidx, mask;
|
---|
[87127] | 638 |
|
---|
[81985] | 639 | STAM_PROFILE_START(&pThis->StatRun, a);
|
---|
[87127] | 640 |
|
---|
| 641 | /* We must first lock all the devices then the DMAC or we end up with a
|
---|
| 642 | lock order validation when the callback helpers (PDMDMACREG) are being
|
---|
| 643 | invoked from I/O port and MMIO callbacks in channel devices. While this
|
---|
| 644 | may sound a little brutish, it's actually in line with the bus locking
|
---|
| 645 | the original DMAC did back in the days. Besides, we've only got the FDC
|
---|
| 646 | and SB16 as potential customers here at present, so hardly a problem. */
|
---|
| 647 | for (unsigned idxCtl = 0; idxCtl < RT_ELEMENTS(pThis->DMAC); idxCtl++)
|
---|
| 648 | for (unsigned idxCh = 0; idxCh < RT_ELEMENTS(pThis->DMAC[idxCtl].ChState); idxCh++)
|
---|
| 649 | if (pThis->DMAC[idxCtl].ChState[idxCh].pDevInsHandler)
|
---|
[90447] | 650 | {
|
---|
| 651 | int const rc = PDMDevHlpCritSectEnter(pDevIns, pThis->DMAC[idxCtl].ChState[idxCh].pDevInsHandler->pCritSectRoR3,
|
---|
| 652 | VERR_IGNORED);
|
---|
| 653 | PDM_CRITSECT_RELEASE_ASSERT_RC_DEV(pDevIns, pThis->DMAC[idxCtl].ChState[idxCh].pDevInsHandler->pCritSectRoR3, rc);
|
---|
| 654 | }
|
---|
| 655 | int const rc = PDMDevHlpCritSectEnter(pDevIns, pDevIns->pCritSectRoR3, VERR_IGNORED);
|
---|
| 656 | PDM_CRITSECT_RELEASE_ASSERT_RC_DEV(pDevIns, pDevIns->pCritSectRoR3, rc);
|
---|
[1] | 657 |
|
---|
[36204] | 658 | /* Run all controllers and channels. */
|
---|
[81988] | 659 | for (unsigned ctlidx = 0; ctlidx < RT_ELEMENTS(pThis->DMAC); ++ctlidx)
|
---|
[36204] | 660 | {
|
---|
[44534] | 661 | dc = &pThis->DMAC[ctlidx];
|
---|
[1] | 662 |
|
---|
[36204] | 663 | /* If controller is disabled, don't even bother. */
|
---|
| 664 | if (dc->u8Command & CMD_DISABLE)
|
---|
| 665 | continue;
|
---|
[1] | 666 |
|
---|
[36204] | 667 | for (chidx = 0; chidx < 4; ++chidx)
|
---|
| 668 | {
|
---|
| 669 | mask = 1 << chidx;
|
---|
| 670 | if (!(dc->u8Mask & mask) && (dc->u8Status & (mask << 4)))
|
---|
[81990] | 671 | dmaR3RunChannel(pThis, ctlidx, chidx);
|
---|
[1] | 672 | }
|
---|
| 673 | }
|
---|
[44534] | 674 |
|
---|
[87127] | 675 | /* Unlock everything (order is mostly irrelevant). */
|
---|
| 676 | for (unsigned idxCtl = 0; idxCtl < RT_ELEMENTS(pThis->DMAC); idxCtl++)
|
---|
| 677 | for (unsigned idxCh = 0; idxCh < RT_ELEMENTS(pThis->DMAC[idxCtl].ChState); idxCh++)
|
---|
| 678 | if (pThis->DMAC[idxCtl].ChState[idxCh].pDevInsHandler)
|
---|
| 679 | PDMDevHlpCritSectLeave(pDevIns, pThis->DMAC[idxCtl].ChState[idxCh].pDevInsHandler->pCritSectRoR3);
|
---|
[81988] | 680 | PDMDevHlpCritSectLeave(pDevIns, pDevIns->pCritSectRoR3);
|
---|
[87127] | 681 |
|
---|
[81985] | 682 | STAM_PROFILE_STOP(&pThis->StatRun, a);
|
---|
[36204] | 683 | return 0;
|
---|
[1] | 684 | }
|
---|
| 685 |
|
---|
[44534] | 686 | /**
|
---|
| 687 | * @interface_method_impl{PDMDMAREG,pfnRegister}
|
---|
| 688 | */
|
---|
[87127] | 689 | static DECLCALLBACK(void) dmaR3Register(PPDMDEVINS pDevIns, unsigned uChannel, PPDMDEVINS pDevInsHandler,
|
---|
[81986] | 690 | PFNDMATRANSFERHANDLER pfnTransferHandler, void *pvUser)
|
---|
[1] | 691 | {
|
---|
[81979] | 692 | DMAState *pThis = PDMDEVINS_2_DATA(pDevIns, PDMASTATE);
|
---|
[44534] | 693 | DMAChannel *ch = &pThis->DMAC[DMACH2C(uChannel)].ChState[uChannel & 3];
|
---|
[1] | 694 |
|
---|
[81986] | 695 | LogFlow(("dmaR3Register: pThis=%p uChannel=%u pfnTransferHandler=%p pvUser=%p\n", pThis, uChannel, pfnTransferHandler, pvUser));
|
---|
[1] | 696 |
|
---|
[90447] | 697 | int const rcLock = PDMDevHlpCritSectEnter(pDevIns, pDevIns->pCritSectRoR3, VERR_IGNORED);
|
---|
| 698 | PDM_CRITSECT_RELEASE_ASSERT_RC_DEV(pDevIns, pDevIns->pCritSectRoR3, rcLock);
|
---|
| 699 |
|
---|
[87127] | 700 | ch->pDevInsHandler = pDevInsHandler;
|
---|
[44534] | 701 | ch->pfnXferHandler = pfnTransferHandler;
|
---|
[36204] | 702 | ch->pvUser = pvUser;
|
---|
[90447] | 703 |
|
---|
[81988] | 704 | PDMDevHlpCritSectLeave(pDevIns, pDevIns->pCritSectRoR3);
|
---|
[1] | 705 | }
|
---|
| 706 |
|
---|
[44534] | 707 | /** Reverse the order of bytes in a memory buffer. */
|
---|
[36204] | 708 | static void dmaReverseBuf8(void *buf, unsigned len)
|
---|
[1] | 709 | {
|
---|
[36204] | 710 | uint8_t *pBeg, *pEnd;
|
---|
| 711 | uint8_t temp;
|
---|
[1] | 712 |
|
---|
[36204] | 713 | pBeg = (uint8_t *)buf;
|
---|
| 714 | pEnd = pBeg + len - 1;
|
---|
| 715 | for (len = len / 2; len; --len)
|
---|
| 716 | {
|
---|
| 717 | temp = *pBeg;
|
---|
| 718 | *pBeg++ = *pEnd;
|
---|
| 719 | *pEnd-- = temp;
|
---|
| 720 | }
|
---|
| 721 | }
|
---|
[1] | 722 |
|
---|
[44534] | 723 | /** Reverse the order of words in a memory buffer. */
|
---|
[36204] | 724 | static void dmaReverseBuf16(void *buf, unsigned len)
|
---|
| 725 | {
|
---|
| 726 | uint16_t *pBeg, *pEnd;
|
---|
| 727 | uint16_t temp;
|
---|
| 728 |
|
---|
| 729 | Assert(!(len & 1));
|
---|
| 730 | len /= 2; /* Convert to word count. */
|
---|
| 731 | pBeg = (uint16_t *)buf;
|
---|
| 732 | pEnd = pBeg + len - 1;
|
---|
| 733 | for (len = len / 2; len; --len)
|
---|
| 734 | {
|
---|
| 735 | temp = *pBeg;
|
---|
| 736 | *pBeg++ = *pEnd;
|
---|
| 737 | *pEnd-- = temp;
|
---|
[1] | 738 | }
|
---|
| 739 | }
|
---|
| 740 |
|
---|
[44534] | 741 | /**
|
---|
| 742 | * @interface_method_impl{PDMDMAREG,pfnReadMemory}
|
---|
| 743 | */
|
---|
[81986] | 744 | static DECLCALLBACK(uint32_t) dmaR3ReadMemory(PPDMDEVINS pDevIns, unsigned uChannel,
|
---|
| 745 | void *pvBuffer, uint32_t off, uint32_t cbBlock)
|
---|
[1] | 746 | {
|
---|
[81979] | 747 | DMAState *pThis = PDMDEVINS_2_DATA(pDevIns, PDMASTATE);
|
---|
[44534] | 748 | DMAControl *dc = &pThis->DMAC[DMACH2C(uChannel)];
|
---|
| 749 | DMAChannel *ch = &dc->ChState[uChannel & 3];
|
---|
[36204] | 750 | uint32_t page, pagehi;
|
---|
| 751 | uint32_t addr;
|
---|
[1] | 752 |
|
---|
[81986] | 753 | LogFlow(("dmaR3ReadMemory: pThis=%p uChannel=%u pvBuffer=%p off=%u cbBlock=%u\n", pThis, uChannel, pvBuffer, off, cbBlock));
|
---|
[1] | 754 |
|
---|
[90447] | 755 | int const rcLock = PDMDevHlpCritSectEnter(pDevIns, pDevIns->pCritSectRoR3, VERR_IGNORED);
|
---|
| 756 | PDM_CRITSECT_RELEASE_ASSERT_RC_DEV(pDevIns, pDevIns->pCritSectRoR3, rcLock);
|
---|
[44534] | 757 |
|
---|
[36204] | 758 | /* Build the address for this transfer. */
|
---|
[44534] | 759 | page = dc->au8Page[DMACH2PG(uChannel)] & ~dc->is16bit;
|
---|
| 760 | pagehi = dc->au8PageHi[DMACH2PG(uChannel)];
|
---|
[36204] | 761 | addr = (pagehi << 24) | (page << 16) | (ch->u16CurAddr << dc->is16bit);
|
---|
| 762 |
|
---|
| 763 | if (IS_MODE_DEC(ch->u8Mode))
|
---|
| 764 | {
|
---|
[44534] | 765 | PDMDevHlpPhysRead(pThis->pDevIns, addr - off - cbBlock, pvBuffer, cbBlock);
|
---|
[36204] | 766 | if (dc->is16bit)
|
---|
[44534] | 767 | dmaReverseBuf16(pvBuffer, cbBlock);
|
---|
[36204] | 768 | else
|
---|
[44534] | 769 | dmaReverseBuf8(pvBuffer, cbBlock);
|
---|
[1] | 770 | }
|
---|
| 771 | else
|
---|
[44534] | 772 | PDMDevHlpPhysRead(pThis->pDevIns, addr + off, pvBuffer, cbBlock);
|
---|
[1] | 773 |
|
---|
[81988] | 774 | PDMDevHlpCritSectLeave(pDevIns, pDevIns->pCritSectRoR3);
|
---|
[44534] | 775 | return cbBlock;
|
---|
[1] | 776 | }
|
---|
| 777 |
|
---|
[44534] | 778 | /**
|
---|
| 779 | * @interface_method_impl{PDMDMAREG,pfnWriteMemory}
|
---|
| 780 | */
|
---|
[81986] | 781 | static DECLCALLBACK(uint32_t) dmaR3WriteMemory(PPDMDEVINS pDevIns, unsigned uChannel,
|
---|
| 782 | const void *pvBuffer, uint32_t off, uint32_t cbBlock)
|
---|
[1] | 783 | {
|
---|
[81979] | 784 | DMAState *pThis = PDMDEVINS_2_DATA(pDevIns, PDMASTATE);
|
---|
[44534] | 785 | DMAControl *dc = &pThis->DMAC[DMACH2C(uChannel)];
|
---|
| 786 | DMAChannel *ch = &dc->ChState[uChannel & 3];
|
---|
[36204] | 787 | uint32_t page, pagehi;
|
---|
| 788 | uint32_t addr;
|
---|
[1] | 789 |
|
---|
[81986] | 790 | LogFlow(("dmaR3WriteMemory: pThis=%p uChannel=%u pvBuffer=%p off=%u cbBlock=%u\n", pThis, uChannel, pvBuffer, off, cbBlock));
|
---|
[48046] | 791 | if (GET_MODE_XTYP(ch->u8Mode) == DTYPE_VERIFY)
|
---|
| 792 | {
|
---|
| 793 | Log(("DMA verify transfer, ignoring write.\n"));
|
---|
| 794 | return cbBlock;
|
---|
| 795 | }
|
---|
| 796 |
|
---|
[90447] | 797 | int const rcLock = PDMDevHlpCritSectEnter(pDevIns, pDevIns->pCritSectRoR3, VERR_IGNORED);
|
---|
| 798 | PDM_CRITSECT_RELEASE_ASSERT_RC_DEV(pDevIns, pDevIns->pCritSectRoR3, rcLock);
|
---|
[1] | 799 |
|
---|
[36204] | 800 | /* Build the address for this transfer. */
|
---|
[44534] | 801 | page = dc->au8Page[DMACH2PG(uChannel)] & ~dc->is16bit;
|
---|
| 802 | pagehi = dc->au8PageHi[DMACH2PG(uChannel)];
|
---|
[36204] | 803 | addr = (pagehi << 24) | (page << 16) | (ch->u16CurAddr << dc->is16bit);
|
---|
[1] | 804 |
|
---|
[36204] | 805 | if (IS_MODE_DEC(ch->u8Mode))
|
---|
| 806 | {
|
---|
[63562] | 807 | /// @todo This would need a temporary buffer.
|
---|
[36204] | 808 | Assert(0);
|
---|
| 809 | #if 0
|
---|
| 810 | if (dc->is16bit)
|
---|
[44534] | 811 | dmaReverseBuf16(pvBuffer, cbBlock);
|
---|
[36204] | 812 | else
|
---|
[44534] | 813 | dmaReverseBuf8(pvBuffer, cbBlock);
|
---|
[1] | 814 | #endif
|
---|
[44534] | 815 | PDMDevHlpPhysWrite(pThis->pDevIns, addr - off - cbBlock, pvBuffer, cbBlock);
|
---|
[1] | 816 | }
|
---|
[36204] | 817 | else
|
---|
[44534] | 818 | PDMDevHlpPhysWrite(pThis->pDevIns, addr + off, pvBuffer, cbBlock);
|
---|
[1] | 819 |
|
---|
[81988] | 820 | PDMDevHlpCritSectLeave(pDevIns, pDevIns->pCritSectRoR3);
|
---|
[44534] | 821 | return cbBlock;
|
---|
[1] | 822 | }
|
---|
| 823 |
|
---|
[44534] | 824 | /**
|
---|
| 825 | * @interface_method_impl{PDMDMAREG,pfnSetDREQ}
|
---|
| 826 | */
|
---|
[81986] | 827 | static DECLCALLBACK(void) dmaR3SetDREQ(PPDMDEVINS pDevIns, unsigned uChannel, unsigned uLevel)
|
---|
[1] | 828 | {
|
---|
[81979] | 829 | DMAState *pThis = PDMDEVINS_2_DATA(pDevIns, PDMASTATE);
|
---|
[44534] | 830 | DMAControl *dc = &pThis->DMAC[DMACH2C(uChannel)];
|
---|
[36204] | 831 | int chidx;
|
---|
[1] | 832 |
|
---|
[81986] | 833 | LogFlow(("dmaR3SetDREQ: pThis=%p uChannel=%u uLevel=%u\n", pThis, uChannel, uLevel));
|
---|
[1] | 834 |
|
---|
[90447] | 835 | int const rcLock = PDMDevHlpCritSectEnter(pDevIns, pDevIns->pCritSectRoR3, VERR_IGNORED);
|
---|
| 836 | PDM_CRITSECT_RELEASE_ASSERT_RC_DEV(pDevIns, pDevIns->pCritSectRoR3, rcLock);
|
---|
| 837 |
|
---|
[44534] | 838 | chidx = uChannel & 3;
|
---|
| 839 | if (uLevel)
|
---|
[36204] | 840 | dc->u8Status |= 1 << (chidx + 4);
|
---|
| 841 | else
|
---|
| 842 | dc->u8Status &= ~(1 << (chidx + 4));
|
---|
[90447] | 843 |
|
---|
[81988] | 844 | PDMDevHlpCritSectLeave(pDevIns, pDevIns->pCritSectRoR3);
|
---|
[1] | 845 | }
|
---|
| 846 |
|
---|
[44534] | 847 | /**
|
---|
| 848 | * @interface_method_impl{PDMDMAREG,pfnGetChannelMode}
|
---|
| 849 | */
|
---|
[81986] | 850 | static DECLCALLBACK(uint8_t) dmaR3GetChannelMode(PPDMDEVINS pDevIns, unsigned uChannel)
|
---|
[1] | 851 | {
|
---|
[81979] | 852 | PDMASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PDMASTATE);
|
---|
[1] | 853 |
|
---|
[81986] | 854 | LogFlow(("dmaR3GetChannelMode: pThis=%p uChannel=%u\n", pThis, uChannel));
|
---|
[1] | 855 |
|
---|
[90447] | 856 | int const rcLock = PDMDevHlpCritSectEnter(pDevIns, pDevIns->pCritSectRoR3, VERR_IGNORED);
|
---|
| 857 | PDM_CRITSECT_RELEASE_ASSERT_RC_DEV(pDevIns, pDevIns->pCritSectRoR3, rcLock);
|
---|
| 858 |
|
---|
[44534] | 859 | uint8_t u8Mode = pThis->DMAC[DMACH2C(uChannel)].ChState[uChannel & 3].u8Mode;
|
---|
[90447] | 860 |
|
---|
[81988] | 861 | PDMDevHlpCritSectLeave(pDevIns, pDevIns->pCritSectRoR3);
|
---|
[44534] | 862 | return u8Mode;
|
---|
[1] | 863 | }
|
---|
| 864 |
|
---|
[44534] | 865 |
|
---|
[81986] | 866 | static void dmaR3SaveController(PCPDMDEVHLPR3 pHlp, PSSMHANDLE pSSM, DMAControl *dc)
|
---|
[1] | 867 | {
|
---|
[36204] | 868 | /* Save controller state... */
|
---|
[81979] | 869 | pHlp->pfnSSMPutU8(pSSM, dc->u8Command);
|
---|
| 870 | pHlp->pfnSSMPutU8(pSSM, dc->u8Mask);
|
---|
| 871 | pHlp->pfnSSMPutU8(pSSM, dc->fHiByte);
|
---|
| 872 | pHlp->pfnSSMPutU32(pSSM, dc->is16bit);
|
---|
| 873 | pHlp->pfnSSMPutU8(pSSM, dc->u8Status);
|
---|
| 874 | pHlp->pfnSSMPutU8(pSSM, dc->u8Temp);
|
---|
| 875 | pHlp->pfnSSMPutU8(pSSM, dc->u8ModeCtr);
|
---|
| 876 | pHlp->pfnSSMPutMem(pSSM, &dc->au8Page, sizeof(dc->au8Page));
|
---|
| 877 | pHlp->pfnSSMPutMem(pSSM, &dc->au8PageHi, sizeof(dc->au8PageHi));
|
---|
[1] | 878 |
|
---|
[36204] | 879 | /* ...and all four of its channels. */
|
---|
[81986] | 880 | for (unsigned chidx = 0; chidx < RT_ELEMENTS(dc->ChState); ++chidx)
|
---|
[36204] | 881 | {
|
---|
| 882 | DMAChannel *ch = &dc->ChState[chidx];
|
---|
[1] | 883 |
|
---|
[81979] | 884 | pHlp->pfnSSMPutU16(pSSM, ch->u16CurAddr);
|
---|
| 885 | pHlp->pfnSSMPutU16(pSSM, ch->u16CurCount);
|
---|
| 886 | pHlp->pfnSSMPutU16(pSSM, ch->u16BaseAddr);
|
---|
| 887 | pHlp->pfnSSMPutU16(pSSM, ch->u16BaseCount);
|
---|
| 888 | pHlp->pfnSSMPutU8(pSSM, ch->u8Mode);
|
---|
[36204] | 889 | }
|
---|
[1] | 890 | }
|
---|
| 891 |
|
---|
[81986] | 892 | static int dmaR3LoadController(PCPDMDEVHLPR3 pHlp, PSSMHANDLE pSSM, DMAControl *dc, int version)
|
---|
[1] | 893 | {
|
---|
[36204] | 894 | uint8_t u8val;
|
---|
| 895 | uint32_t u32val;
|
---|
[1] | 896 |
|
---|
[81979] | 897 | pHlp->pfnSSMGetU8(pSSM, &dc->u8Command);
|
---|
| 898 | pHlp->pfnSSMGetU8(pSSM, &dc->u8Mask);
|
---|
| 899 | pHlp->pfnSSMGetU8(pSSM, &u8val);
|
---|
[44534] | 900 | dc->fHiByte = !!u8val;
|
---|
[81979] | 901 | pHlp->pfnSSMGetU32(pSSM, &dc->is16bit);
|
---|
[36204] | 902 | if (version > DMA_SAVESTATE_OLD)
|
---|
| 903 | {
|
---|
[81979] | 904 | pHlp->pfnSSMGetU8(pSSM, &dc->u8Status);
|
---|
| 905 | pHlp->pfnSSMGetU8(pSSM, &dc->u8Temp);
|
---|
| 906 | pHlp->pfnSSMGetU8(pSSM, &dc->u8ModeCtr);
|
---|
| 907 | pHlp->pfnSSMGetMem(pSSM, &dc->au8Page, sizeof(dc->au8Page));
|
---|
| 908 | pHlp->pfnSSMGetMem(pSSM, &dc->au8PageHi, sizeof(dc->au8PageHi));
|
---|
[1] | 909 | }
|
---|
| 910 |
|
---|
[81986] | 911 | for (unsigned chidx = 0; chidx < RT_ELEMENTS(dc->ChState); ++chidx)
|
---|
[36204] | 912 | {
|
---|
| 913 | DMAChannel *ch = &dc->ChState[chidx];
|
---|
[1] | 914 |
|
---|
[36204] | 915 | if (version == DMA_SAVESTATE_OLD)
|
---|
| 916 | {
|
---|
| 917 | /* Convert from 17-bit to 16-bit format. */
|
---|
[81979] | 918 | pHlp->pfnSSMGetU32(pSSM, &u32val);
|
---|
[36204] | 919 | ch->u16CurAddr = u32val >> dc->is16bit;
|
---|
[81979] | 920 | pHlp->pfnSSMGetU32(pSSM, &u32val);
|
---|
[36204] | 921 | ch->u16CurCount = u32val >> dc->is16bit;
|
---|
| 922 | }
|
---|
| 923 | else
|
---|
| 924 | {
|
---|
[81979] | 925 | pHlp->pfnSSMGetU16(pSSM, &ch->u16CurAddr);
|
---|
| 926 | pHlp->pfnSSMGetU16(pSSM, &ch->u16CurCount);
|
---|
[36204] | 927 | }
|
---|
[81979] | 928 | pHlp->pfnSSMGetU16(pSSM, &ch->u16BaseAddr);
|
---|
| 929 | pHlp->pfnSSMGetU16(pSSM, &ch->u16BaseCount);
|
---|
| 930 | pHlp->pfnSSMGetU8(pSSM, &ch->u8Mode);
|
---|
[36204] | 931 | /* Convert from old save state. */
|
---|
| 932 | if (version == DMA_SAVESTATE_OLD)
|
---|
| 933 | {
|
---|
| 934 | /* Remap page register contents. */
|
---|
[81979] | 935 | pHlp->pfnSSMGetU8(pSSM, &u8val);
|
---|
[36204] | 936 | dc->au8Page[DMACX2PG(chidx)] = u8val;
|
---|
[81979] | 937 | pHlp->pfnSSMGetU8(pSSM, &u8val);
|
---|
[36204] | 938 | dc->au8PageHi[DMACX2PG(chidx)] = u8val;
|
---|
| 939 | /* Throw away dack, eop. */
|
---|
[81979] | 940 | pHlp->pfnSSMGetU8(pSSM, &u8val);
|
---|
| 941 | pHlp->pfnSSMGetU8(pSSM, &u8val);
|
---|
[36204] | 942 | }
|
---|
| 943 | }
|
---|
| 944 | return 0;
|
---|
[1] | 945 | }
|
---|
| 946 |
|
---|
[44534] | 947 | /** @callback_method_impl{FNSSMDEVSAVEEXEC} */
|
---|
[81986] | 948 | static DECLCALLBACK(int) dmaR3SaveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
|
---|
[1] | 949 | {
|
---|
[81979] | 950 | PDMASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PDMASTATE);
|
---|
| 951 | PCPDMDEVHLPR3 pHlp = pDevIns->pHlpR3;
|
---|
[36204] | 952 |
|
---|
[81986] | 953 | dmaR3SaveController(pHlp, pSSM, &pThis->DMAC[0]);
|
---|
| 954 | dmaR3SaveController(pHlp, pSSM, &pThis->DMAC[1]);
|
---|
[1] | 955 | return VINF_SUCCESS;
|
---|
| 956 | }
|
---|
| 957 |
|
---|
[44534] | 958 | /** @callback_method_impl{FNSSMDEVLOADEXEC} */
|
---|
[81986] | 959 | static DECLCALLBACK(int) dmaR3LoadExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
|
---|
[1] | 960 | {
|
---|
[81979] | 961 | PDMASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PDMASTATE);
|
---|
| 962 | PCPDMDEVHLPR3 pHlp = pDevIns->pHlpR3;
|
---|
[1] | 963 |
|
---|
[36204] | 964 | AssertMsgReturn(uVersion <= DMA_SAVESTATE_CURRENT, ("%d\n", uVersion), VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION);
|
---|
| 965 | Assert(uPass == SSM_PASS_FINAL); NOREF(uPass);
|
---|
[1] | 966 |
|
---|
[81986] | 967 | dmaR3LoadController(pHlp, pSSM, &pThis->DMAC[0], uVersion);
|
---|
| 968 | return dmaR3LoadController(pHlp, pSSM, &pThis->DMAC[1], uVersion);
|
---|
[1] | 969 | }
|
---|
| 970 |
|
---|
[82657] | 971 | /** @callback_method_impl{FNDBGFHANDLERDEV} */
|
---|
| 972 | static DECLCALLBACK(void) dmaR3Info(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
|
---|
| 973 | {
|
---|
| 974 | PDMASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PDMASTATE);
|
---|
| 975 | NOREF(pszArgs);
|
---|
| 976 |
|
---|
| 977 | /*
|
---|
| 978 | * Show info.
|
---|
| 979 | */
|
---|
| 980 | for (unsigned i = 0; i < RT_ELEMENTS(pThis->DMAC); i++)
|
---|
| 981 | {
|
---|
| 982 | PDMACONTROLLER pDmac = &pThis->DMAC[i];
|
---|
| 983 |
|
---|
| 984 | pHlp->pfnPrintf(pHlp, "\nDMAC%d:\n", i);
|
---|
| 985 | pHlp->pfnPrintf(pHlp, " Status : %02X - DRQ 3210 TC 3210\n", pDmac->u8Status);
|
---|
| 986 | pHlp->pfnPrintf(pHlp, " %u%u%u%u %u%u%u%u\n",
|
---|
| 987 | !!(pDmac->u8Status & RT_BIT(7)), !!(pDmac->u8Status & RT_BIT(6)),
|
---|
| 988 | !!(pDmac->u8Status & RT_BIT(5)), !!(pDmac->u8Status & RT_BIT(4)),
|
---|
| 989 | !!(pDmac->u8Status & RT_BIT(3)), !!(pDmac->u8Status & RT_BIT(2)),
|
---|
| 990 | !!(pDmac->u8Status & RT_BIT(1)), !!(pDmac->u8Status & RT_BIT(0)));
|
---|
| 991 | pHlp->pfnPrintf(pHlp, " Mask : %02X - Chn 3210\n", pDmac->u8Mask);
|
---|
| 992 | pHlp->pfnPrintf(pHlp, " %u%u%u%u\n",
|
---|
| 993 | !!(pDmac->u8Mask & RT_BIT(3)), !!(pDmac->u8Mask & RT_BIT(2)),
|
---|
| 994 | !!(pDmac->u8Mask & RT_BIT(1)), !!(pDmac->u8Mask & RT_BIT(0)));
|
---|
| 995 | pHlp->pfnPrintf(pHlp, " Temp : %02x\n", pDmac->u8Temp);
|
---|
| 996 | pHlp->pfnPrintf(pHlp, " Command: %02X\n", pDmac->u8Command);
|
---|
| 997 | pHlp->pfnPrintf(pHlp, " DACK: active %s DREQ: active %s\n",
|
---|
| 998 | pDmac->u8Command & RT_BIT(7) ? "high" : "low ",
|
---|
| 999 | pDmac->u8Command & RT_BIT(6) ? "high" : "low ");
|
---|
| 1000 | pHlp->pfnPrintf(pHlp, " Extended write: %s Priority: %s\n",
|
---|
| 1001 | pDmac->u8Command & RT_BIT(5) ? "enabled " : "disabled",
|
---|
| 1002 | pDmac->u8Command & RT_BIT(4) ? "rotating" : "fixed ");
|
---|
| 1003 | pHlp->pfnPrintf(pHlp, " Timing: %s Controller: %s\n",
|
---|
| 1004 | pDmac->u8Command & RT_BIT(3) ? "normal " : "compressed",
|
---|
| 1005 | pDmac->u8Command & RT_BIT(2) ? "enabled " : "disabled");
|
---|
| 1006 | pHlp->pfnPrintf(pHlp, " Adress Hold: %s Mem-to-Mem Ch 0/1: %s\n",
|
---|
| 1007 | pDmac->u8Command & RT_BIT(1) ? "enabled " : "disabled",
|
---|
| 1008 | pDmac->u8Command & RT_BIT(0) ? "enabled " : "disabled");
|
---|
| 1009 |
|
---|
| 1010 | for (unsigned ch = 0; ch < RT_ELEMENTS(pDmac->ChState); ch++)
|
---|
| 1011 | {
|
---|
| 1012 | PDMACHANNEL pChan = &pDmac->ChState[ch];
|
---|
| 1013 | const char *apszChanMode[] = { "demand ", "single ", "block ", "cascade" };
|
---|
| 1014 | const char *apszChanType[] = { "verify ", "write ", "read ", "illegal" };
|
---|
| 1015 |
|
---|
| 1016 | pHlp->pfnPrintf(pHlp, "\n DMA Channel %d: Page:%02X\n",
|
---|
| 1017 | ch, pDmac->au8Page[DMACX2PG(ch)]);
|
---|
| 1018 | pHlp->pfnPrintf(pHlp, " Mode : %02X Auto-init: %s %screment\n",
|
---|
| 1019 | pChan->u8Mode, pChan->u8Mode & RT_BIT(4) ? "yes" : "no",
|
---|
| 1020 | pChan->u8Mode & RT_BIT(5) ? "De" : "In" );
|
---|
| 1021 | pHlp->pfnPrintf(pHlp, " Xfer Type: %s Mode: %s\n",
|
---|
| 1022 | apszChanType[((pChan->u8Mode >> 2) & 3)],
|
---|
| 1023 | apszChanMode[((pChan->u8Mode >> 6) & 3)]);
|
---|
| 1024 | pHlp->pfnPrintf(pHlp, " Base address:%04X count:%04X\n",
|
---|
| 1025 | pChan->u16BaseAddr, pChan->u16BaseCount);
|
---|
| 1026 | pHlp->pfnPrintf(pHlp, " Current address:%04X count:%04X\n",
|
---|
| 1027 | pChan->u16CurAddr, pChan->u16CurCount);
|
---|
| 1028 | }
|
---|
| 1029 | }
|
---|
| 1030 | }
|
---|
| 1031 |
|
---|
[84913] | 1032 | /** @callback_method_impl{FNDBGFHANDLERDEV} */
|
---|
| 1033 | static DECLCALLBACK(void) dmaR3InfoPageReg(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
|
---|
| 1034 | {
|
---|
| 1035 | PDMASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PDMASTATE);
|
---|
| 1036 | NOREF(pszArgs);
|
---|
| 1037 |
|
---|
| 1038 | /*
|
---|
| 1039 | * Show page register contents.
|
---|
| 1040 | */
|
---|
| 1041 | for (unsigned i = 0; i < RT_ELEMENTS(pThis->DMAC); i++)
|
---|
| 1042 | {
|
---|
| 1043 | PDMACONTROLLER pDmac = &pThis->DMAC[i];
|
---|
| 1044 |
|
---|
| 1045 | pHlp->pfnPrintf(pHlp, "DMA page registers at %02X:", i == 0 ? 0x80 : 0x88);
|
---|
| 1046 | for (unsigned pg = 0; pg < RT_ELEMENTS(pDmac->au8Page); pg++)
|
---|
| 1047 | pHlp->pfnPrintf(pHlp, " %02X", pDmac->au8Page[pg]);
|
---|
| 1048 |
|
---|
| 1049 | pHlp->pfnPrintf(pHlp, "\n");
|
---|
| 1050 | }
|
---|
| 1051 | }
|
---|
| 1052 |
|
---|
[1] | 1053 | /**
|
---|
[81986] | 1054 | * @interface_method_impl{PDMDEVREG,pfnReset}
|
---|
| 1055 | */
|
---|
| 1056 | static DECLCALLBACK(void) dmaR3Reset(PPDMDEVINS pDevIns)
|
---|
| 1057 | {
|
---|
| 1058 | PDMASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PDMASTATE);
|
---|
| 1059 |
|
---|
| 1060 | LogFlow(("dmaR3Reset: pThis=%p\n", pThis));
|
---|
| 1061 |
|
---|
| 1062 | /* NB: The page and address registers are unaffected by a reset
|
---|
| 1063 | * and in an undefined state after power-up.
|
---|
| 1064 | */
|
---|
| 1065 | dmaClear(&pThis->DMAC[0]);
|
---|
| 1066 | dmaClear(&pThis->DMAC[1]);
|
---|
| 1067 | }
|
---|
| 1068 |
|
---|
| 1069 | /**
|
---|
[26160] | 1070 | * @interface_method_impl{PDMDEVREG,pfnConstruct}
|
---|
[1] | 1071 | */
|
---|
[81986] | 1072 | static DECLCALLBACK(int) dmaR3Construct(PPDMDEVINS pDevIns, int iInstance, PCFGMNODE pCfg)
|
---|
[1] | 1073 | {
|
---|
[71809] | 1074 | PDMDEV_CHECK_VERSIONS_RETURN(pDevIns);
|
---|
[81979] | 1075 | PDMASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PDMASTATE);
|
---|
| 1076 | PCPDMDEVHLPR3 pHlp = pDevIns->pHlpR3;
|
---|
[62903] | 1077 | RT_NOREF(iInstance);
|
---|
[1] | 1078 |
|
---|
[62903] | 1079 | /*
|
---|
| 1080 | * Initialize data.
|
---|
| 1081 | */
|
---|
[44534] | 1082 | pThis->pDevIns = pDevIns;
|
---|
[1] | 1083 |
|
---|
[81984] | 1084 | DMAControl *pDC8 = &pThis->DMAC[0];
|
---|
| 1085 | DMAControl *pDC16 = &pThis->DMAC[1];
|
---|
| 1086 | pDC8->is16bit = false;
|
---|
| 1087 | pDC16->is16bit = true;
|
---|
| 1088 |
|
---|
[1] | 1089 | /*
|
---|
[81979] | 1090 | * Validate and read the configuration.
|
---|
[1] | 1091 | */
|
---|
[81979] | 1092 | PDMDEV_VALIDATE_CONFIG_RETURN(pDevIns, "HighPageEnable", "");
|
---|
[1] | 1093 |
|
---|
[81979] | 1094 | bool fHighPage = false;
|
---|
| 1095 | int rc = pHlp->pfnCFGMQueryBoolDef(pCfg, "HighPageEnable", &fHighPage, false);
|
---|
[81984] | 1096 | AssertRCReturn(rc, rc);
|
---|
[1] | 1097 |
|
---|
[81979] | 1098 | /*
|
---|
| 1099 | * Register I/O callbacks.
|
---|
| 1100 | */
|
---|
[81984] | 1101 | /* Base and current address for each channel. */
|
---|
| 1102 | rc = PDMDevHlpIoPortCreateUAndMap(pDevIns, 0x00, 8, dmaWriteAddr, dmaReadAddr, pDC8, "DMA8 Address", NULL, &pDC8->hIoPortBase);
|
---|
[71210] | 1103 | AssertLogRelRCReturn(rc, rc);
|
---|
[81984] | 1104 | rc = PDMDevHlpIoPortCreateUAndMap(pDevIns, 0xc0, 16, dmaWriteAddr, dmaReadAddr, pDC16, "DMA16 Address", NULL, &pDC16->hIoPortBase);
|
---|
| 1105 | AssertLogRelRCReturn(rc, rc);
|
---|
[71210] | 1106 |
|
---|
[81984] | 1107 | /* Control registers for both DMA controllers. */
|
---|
| 1108 | rc = PDMDevHlpIoPortCreateUAndMap(pDevIns, 0x08, 8, dmaWriteCtl, dmaReadCtl, pDC8, "DMA8 Control", NULL, &pDC8->hIoPortCtl);
|
---|
| 1109 | AssertLogRelRCReturn(rc, rc);
|
---|
| 1110 | rc = PDMDevHlpIoPortCreateUAndMap(pDevIns, 0xd0, 16, dmaWriteCtl, dmaReadCtl, pDC16, "DMA16 Control", NULL, &pDC16->hIoPortCtl);
|
---|
| 1111 | AssertLogRelRCReturn(rc, rc);
|
---|
| 1112 |
|
---|
| 1113 | /* Page registers for each channel (plus a few unused ones). */
|
---|
| 1114 | rc = PDMDevHlpIoPortCreateUAndMap(pDevIns, 0x80, 8, dmaWritePage, dmaReadPage, pDC8, "DMA8 Page", NULL, &pDC8->hIoPortPage);
|
---|
| 1115 | AssertLogRelRCReturn(rc, rc);
|
---|
| 1116 | rc = PDMDevHlpIoPortCreateUAndMap(pDevIns, 0x88, 8, dmaWritePage, dmaReadPage, pDC16, "DMA16 Page", NULL, &pDC16->hIoPortPage);
|
---|
| 1117 | AssertLogRelRCReturn(rc, rc);
|
---|
| 1118 |
|
---|
| 1119 | /* Optional EISA style high page registers (address bits 24-31). */
|
---|
| 1120 | if (fHighPage)
|
---|
| 1121 | {
|
---|
| 1122 | rc = PDMDevHlpIoPortCreateUAndMap(pDevIns, 0x480, 8, dmaWriteHiPage, dmaReadHiPage, pDC8, "DMA8 Page High", NULL, &pDC8->hIoPortHi);
|
---|
| 1123 | AssertLogRelRCReturn(rc, rc);
|
---|
| 1124 | rc = PDMDevHlpIoPortCreateUAndMap(pDevIns, 0x488, 8, dmaWriteHiPage, dmaReadHiPage, pDC16, "DMA16 Page High", NULL, &pDC16->hIoPortHi);
|
---|
| 1125 | AssertLogRelRCReturn(rc, rc);
|
---|
| 1126 | }
|
---|
| 1127 | else
|
---|
| 1128 | {
|
---|
| 1129 | pDC8->hIoPortHi = NIL_IOMIOPORTHANDLE;
|
---|
| 1130 | pDC16->hIoPortHi = NIL_IOMIOPORTHANDLE;
|
---|
| 1131 | }
|
---|
| 1132 |
|
---|
[81979] | 1133 | /*
|
---|
| 1134 | * Reset controller state.
|
---|
| 1135 | */
|
---|
[81986] | 1136 | dmaR3Reset(pDevIns);
|
---|
[1] | 1137 |
|
---|
[81979] | 1138 | /*
|
---|
| 1139 | * Register ourselves with PDM as the DMA controller.
|
---|
| 1140 | */
|
---|
[62903] | 1141 | PDMDMACREG Reg;
|
---|
| 1142 | Reg.u32Version = PDM_DMACREG_VERSION;
|
---|
[81986] | 1143 | Reg.pfnRun = dmaR3Run;
|
---|
| 1144 | Reg.pfnRegister = dmaR3Register;
|
---|
| 1145 | Reg.pfnReadMemory = dmaR3ReadMemory;
|
---|
| 1146 | Reg.pfnWriteMemory = dmaR3WriteMemory;
|
---|
| 1147 | Reg.pfnSetDREQ = dmaR3SetDREQ;
|
---|
| 1148 | Reg.pfnGetChannelMode = dmaR3GetChannelMode;
|
---|
[1] | 1149 |
|
---|
[71210] | 1150 | rc = PDMDevHlpDMACRegister(pDevIns, &Reg, &pThis->pHlp);
|
---|
[81984] | 1151 | AssertRCReturn(rc, rc);
|
---|
[1] | 1152 |
|
---|
[81979] | 1153 | /*
|
---|
| 1154 | * Register the saved state.
|
---|
| 1155 | */
|
---|
[81986] | 1156 | rc = PDMDevHlpSSMRegister(pDevIns, DMA_SAVESTATE_CURRENT, sizeof(*pThis), dmaR3SaveExec, dmaR3LoadExec);
|
---|
[81984] | 1157 | AssertRCReturn(rc, rc);
|
---|
[1] | 1158 |
|
---|
[81985] | 1159 | /*
|
---|
| 1160 | * Statistics.
|
---|
| 1161 | */
|
---|
[81986] | 1162 | PDMDevHlpSTAMRegister(pDevIns, &pThis->StatRun, STAMTYPE_PROFILE, "DmaRun", STAMUNIT_TICKS_PER_CALL, "Profiling dmaR3Run().");
|
---|
[81985] | 1163 |
|
---|
[82657] | 1164 | /*
|
---|
| 1165 | * Register the info item.
|
---|
| 1166 | */
|
---|
| 1167 | PDMDevHlpDBGFInfoRegister(pDevIns, "dmac", "DMA controller info.", dmaR3Info);
|
---|
[84913] | 1168 | PDMDevHlpDBGFInfoRegister(pDevIns, "dmapage", "DMA page register info.", dmaR3InfoPageReg);
|
---|
[82657] | 1169 |
|
---|
[1] | 1170 | return VINF_SUCCESS;
|
---|
| 1171 | }
|
---|
| 1172 |
|
---|
[81984] | 1173 | #else /* !IN_RING3 */
|
---|
[80531] | 1174 |
|
---|
[1] | 1175 | /**
|
---|
[81984] | 1176 | * @callback_method_impl{PDMDEVREGR0,pfnConstruct}
|
---|
| 1177 | */
|
---|
| 1178 | static DECLCALLBACK(int) dmaRZConstruct(PPDMDEVINS pDevIns)
|
---|
| 1179 | {
|
---|
| 1180 | PDMDEV_CHECK_VERSIONS_RETURN(pDevIns);
|
---|
| 1181 | PDMASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PDMASTATE);
|
---|
| 1182 | int rc;
|
---|
| 1183 |
|
---|
| 1184 | for (unsigned i = 0; i < RT_ELEMENTS(pThis->DMAC); i++)
|
---|
| 1185 | {
|
---|
| 1186 | PDMACONTROLLER pCtl = &pThis->DMAC[i];
|
---|
| 1187 |
|
---|
| 1188 | rc = PDMDevHlpIoPortSetUpContext(pDevIns, pCtl->hIoPortBase, dmaWriteAddr, dmaReadAddr, pCtl);
|
---|
| 1189 | AssertLogRelRCReturn(rc, rc);
|
---|
| 1190 |
|
---|
| 1191 | rc = PDMDevHlpIoPortSetUpContext(pDevIns, pCtl->hIoPortCtl, dmaWriteCtl, dmaReadCtl, pCtl);
|
---|
| 1192 | AssertLogRelRCReturn(rc, rc);
|
---|
| 1193 |
|
---|
| 1194 | rc = PDMDevHlpIoPortSetUpContext(pDevIns, pCtl->hIoPortPage, dmaWritePage, dmaReadPage, pCtl);
|
---|
| 1195 | AssertLogRelRCReturn(rc, rc);
|
---|
| 1196 |
|
---|
| 1197 | if (pCtl->hIoPortHi != NIL_IOMIOPORTHANDLE)
|
---|
| 1198 | {
|
---|
| 1199 | rc = PDMDevHlpIoPortSetUpContext(pDevIns, pCtl->hIoPortHi, dmaWriteHiPage, dmaReadHiPage, pCtl);
|
---|
| 1200 | AssertLogRelRCReturn(rc, rc);
|
---|
| 1201 | }
|
---|
| 1202 | }
|
---|
| 1203 |
|
---|
| 1204 | return VINF_SUCCESS;
|
---|
| 1205 | }
|
---|
| 1206 |
|
---|
| 1207 | #endif /* !IN_RING3 */
|
---|
| 1208 |
|
---|
| 1209 | /**
|
---|
[1] | 1210 | * The device registration structure.
|
---|
| 1211 | */
|
---|
| 1212 | const PDMDEVREG g_DeviceDMA =
|
---|
| 1213 | {
|
---|
[80531] | 1214 | /* .u32Version = */ PDM_DEVREG_VERSION,
|
---|
| 1215 | /* .uReserved0 = */ 0,
|
---|
| 1216 | /* .szName = */ "8237A",
|
---|
[81985] | 1217 | /* .fFlags = */ PDM_DEVREG_FLAGS_DEFAULT_BITS | PDM_DEVREG_FLAGS_RZ | PDM_DEVREG_FLAGS_NEW_STYLE,
|
---|
[80531] | 1218 | /* .fClass = */ PDM_DEVREG_CLASS_DMA,
|
---|
| 1219 | /* .cMaxInstances = */ 1,
|
---|
| 1220 | /* .uSharedVersion = */ 42,
|
---|
| 1221 | /* .cbInstanceShared = */ sizeof(DMAState),
|
---|
| 1222 | /* .cbInstanceCC = */ 0,
|
---|
| 1223 | /* .cbInstanceRC = */ 0,
|
---|
[80703] | 1224 | /* .cMaxPciDevices = */ 0,
|
---|
[80704] | 1225 | /* .cMaxMsixVectors = */ 0,
|
---|
[80531] | 1226 | /* .pszDescription = */ "DMA Controller Device",
|
---|
| 1227 | #if defined(IN_RING3)
|
---|
| 1228 | /* .pszRCMod = */ "VBoxDDRC.rc",
|
---|
| 1229 | /* .pszR0Mod = */ "VBoxDDR0.r0",
|
---|
[81986] | 1230 | /* .pfnConstruct = */ dmaR3Construct,
|
---|
[80531] | 1231 | /* .pfnDestruct = */ NULL,
|
---|
| 1232 | /* .pfnRelocate = */ NULL,
|
---|
| 1233 | /* .pfnMemSetup = */ NULL,
|
---|
| 1234 | /* .pfnPowerOn = */ NULL,
|
---|
[81986] | 1235 | /* .pfnReset = */ dmaR3Reset,
|
---|
[80531] | 1236 | /* .pfnSuspend = */ NULL,
|
---|
| 1237 | /* .pfnResume = */ NULL,
|
---|
| 1238 | /* .pfnAttach = */ NULL,
|
---|
| 1239 | /* .pfnDetach = */ NULL,
|
---|
| 1240 | /* .pfnQueryInterface = */ NULL,
|
---|
| 1241 | /* .pfnInitComplete = */ NULL,
|
---|
| 1242 | /* .pfnPowerOff = */ NULL,
|
---|
| 1243 | /* .pfnSoftReset = */ NULL,
|
---|
| 1244 | /* .pfnReserved0 = */ NULL,
|
---|
| 1245 | /* .pfnReserved1 = */ NULL,
|
---|
| 1246 | /* .pfnReserved2 = */ NULL,
|
---|
| 1247 | /* .pfnReserved3 = */ NULL,
|
---|
| 1248 | /* .pfnReserved4 = */ NULL,
|
---|
| 1249 | /* .pfnReserved5 = */ NULL,
|
---|
| 1250 | /* .pfnReserved6 = */ NULL,
|
---|
| 1251 | /* .pfnReserved7 = */ NULL,
|
---|
| 1252 | #elif defined(IN_RING0)
|
---|
| 1253 | /* .pfnEarlyConstruct = */ NULL,
|
---|
[81984] | 1254 | /* .pfnConstruct = */ dmaRZConstruct,
|
---|
[80531] | 1255 | /* .pfnDestruct = */ NULL,
|
---|
| 1256 | /* .pfnFinalDestruct = */ NULL,
|
---|
| 1257 | /* .pfnRequest = */ NULL,
|
---|
| 1258 | /* .pfnReserved0 = */ NULL,
|
---|
| 1259 | /* .pfnReserved1 = */ NULL,
|
---|
| 1260 | /* .pfnReserved2 = */ NULL,
|
---|
| 1261 | /* .pfnReserved3 = */ NULL,
|
---|
| 1262 | /* .pfnReserved4 = */ NULL,
|
---|
| 1263 | /* .pfnReserved5 = */ NULL,
|
---|
| 1264 | /* .pfnReserved6 = */ NULL,
|
---|
| 1265 | /* .pfnReserved7 = */ NULL,
|
---|
| 1266 | #elif defined(IN_RC)
|
---|
[81984] | 1267 | /* .pfnConstruct = */ dmaRZConstruct,
|
---|
[80531] | 1268 | /* .pfnReserved0 = */ NULL,
|
---|
| 1269 | /* .pfnReserved1 = */ NULL,
|
---|
| 1270 | /* .pfnReserved2 = */ NULL,
|
---|
| 1271 | /* .pfnReserved3 = */ NULL,
|
---|
| 1272 | /* .pfnReserved4 = */ NULL,
|
---|
| 1273 | /* .pfnReserved5 = */ NULL,
|
---|
| 1274 | /* .pfnReserved6 = */ NULL,
|
---|
| 1275 | /* .pfnReserved7 = */ NULL,
|
---|
| 1276 | #else
|
---|
| 1277 | # error "Not in IN_RING3, IN_RING0 or IN_RC!"
|
---|
| 1278 | #endif
|
---|
| 1279 | /* .u32VersionEnd = */ PDM_DEVREG_VERSION
|
---|
[1] | 1280 | };
|
---|
[80531] | 1281 |
|
---|
[71210] | 1282 | #endif /* !VBOX_DEVICE_STRUCT_TESTCASE */
|
---|
| 1283 |
|
---|