VirtualBox

source: vbox/trunk/src/VBox/Devices/PC/DevAPIC.cpp@ 44004

Last change on this file since 44004 was 43974, checked in by vboxsync, 12 years ago

VMM: Fix MSR range values for X2APIC, add in the X2APIC TPR MSR.
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1/* $Id: DevAPIC.cpp 43974 2012-11-27 14:52:12Z vboxsync $ */
2/** @file
3 * Advanced Programmable Interrupt Controller (APIC) Device.
4 */
5
6/*
7 * Copyright (C) 2006-2011 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 * --------------------------------------------------------------------
17 *
18 * This code is based on:
19 *
20 * apic.c revision 1.5 @@OSETODO
21 *
22 * APIC support
23 *
24 * Copyright (c) 2004-2005 Fabrice Bellard
25 *
26 * This library is free software; you can redistribute it and/or
27 * modify it under the terms of the GNU Lesser General Public
28 * License as published by the Free Software Foundation; either
29 * version 2 of the License, or (at your option) any later version.
30 *
31 * This library is distributed in the hope that it will be useful,
32 * but WITHOUT ANY WARRANTY; without even the implied warranty of
33 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
34 * Lesser General Public License for more details.
35 *
36 * You should have received a copy of the GNU Lesser General Public
37 * License along with this library; if not, write to the Free Software
38 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
39 */
40
41/*******************************************************************************
42* Header Files *
43*******************************************************************************/
44#define LOG_GROUP LOG_GROUP_DEV_APIC
45#include <VBox/vmm/pdmdev.h>
46
47#include <VBox/log.h>
48#include <VBox/vmm/stam.h>
49#include <VBox/vmm/vmcpuset.h>
50#include <iprt/asm.h>
51#include <iprt/assert.h>
52
53#include <VBox/msi.h>
54
55#include "VBoxDD2.h"
56#include "DevApic.h"
57
58
59/*******************************************************************************
60* Defined Constants And Macros *
61*******************************************************************************/
62#define MSR_IA32_APICBASE 0x1b
63#define MSR_IA32_APICBASE_BSP (1<<8)
64#define MSR_IA32_APICBASE_ENABLE (1<<11)
65#define MSR_IA32_APICBASE_X2ENABLE (1<<10)
66#define MSR_IA32_APICBASE_BASE (0xfffff<<12)
67
68#ifdef _MSC_VER
69# pragma warning(disable:4244)
70#endif
71
72/** The current saved state version.*/
73#define APIC_SAVED_STATE_VERSION 3
74/** The saved state version used by VirtualBox v3 and earlier.
75 * This does not include the config. */
76#define APIC_SAVED_STATE_VERSION_VBOX_30 2
77/** Some ancient version... */
78#define APIC_SAVED_STATE_VERSION_ANCIENT 1
79
80/* version 0x14: Pentium 4, Xeon; LVT count depends on that */
81#define APIC_HW_VERSION 0x14
82
83/** @def APIC_LOCK
84 * Acquires the PDM lock. */
85#define APIC_LOCK(a_pDev, rcBusy) \
86 do { \
87 int rc2 = PDMCritSectEnter((a_pDev)->CTX_SUFF(pCritSect), (rcBusy)); \
88 if (rc2 != VINF_SUCCESS) \
89 return rc2; \
90 } while (0)
91
92/** @def APIC_LOCK_VOID
93 * Acquires the PDM lock and does not expect failure (i.e. ring-3 only!). */
94#define APIC_LOCK_VOID(a_pDev, rcBusy) \
95 do { \
96 int rc2 = PDMCritSectEnter((a_pDev)->CTX_SUFF(pCritSect), (rcBusy)); \
97 AssertLogRelRCReturnVoid(rc2); \
98 } while (0)
99
100/** @def APIC_UNLOCK
101 * Releases the PDM lock. */
102#define APIC_UNLOCK(a_pDev) \
103 PDMCritSectLeave((a_pDev)->CTX_SUFF(pCritSect))
104
105/** @def APIC_AND_TM_LOCK
106 * Acquires the virtual sync clock lock as well as the PDM lock. */
107#define APIC_AND_TM_LOCK(a_pDev, a_pAcpi, rcBusy) \
108 do { \
109 int rc2 = TMTimerLock((a_pAcpi)->CTX_SUFF(pTimer), (rcBusy)); \
110 if (rc2 != VINF_SUCCESS) \
111 return rc2; \
112 rc2 = PDMCritSectEnter((a_pDev)->CTX_SUFF(pCritSect), (rcBusy)); \
113 if (rc2 != VINF_SUCCESS) \
114 { \
115 TMTimerUnlock((a_pAcpi)->CTX_SUFF(pTimer)); \
116 return rc2; \
117 } \
118 } while (0)
119
120/** @def APIC_AND_TM_UNLOCK
121 * Releases the PDM lock as well as the TM virtual sync clock lock. */
122#define APIC_AND_TM_UNLOCK(a_pDev, a_pAcpi) \
123 do { \
124 TMTimerUnlock((a_pAcpi)->CTX_SUFF(pTimer)); \
125 PDMCritSectLeave((a_pDev)->CTX_SUFF(pCritSect)); \
126 } while (0)
127
128/**
129 * Begins an APIC enumeration block.
130 *
131 * Code placed between this and the APIC_FOREACH_END macro will be executed for
132 * each APIC instance present in the system.
133 *
134 * @param a_pDev The APIC device.
135 */
136#define APIC_FOREACH_BEGIN(a_pDev) \
137 do { \
138 VMCPUID const cApics = (a_pDev)->cCpus; \
139 APICState *pCurApic = (a_pDev)->CTX_SUFF(paLapics); \
140 for (VMCPUID iCurApic = 0; iCurApic < cApics; iCurApic++, pCurApic++) \
141 { \
142 do { } while (0)
143
144/**
145 * Begins an APIC enumeration block, given a destination set.
146 *
147 * Code placed between this and the APIC_FOREACH_END macro will be executed for
148 * each APIC instance present in @a a_pDstSet.
149 *
150 * @param a_pDev The APIC device.
151 * @param a_pDstSet The destination set.
152 */
153#define APIC_FOREACH_IN_SET_BEGIN(a_pDev, a_pDstSet) \
154 APIC_FOREACH_BEGIN(a_pDev); \
155 if (!VMCPUSET_IS_PRESENT((a_pDstSet), iCurApic)) \
156 continue; \
157 do { } while (0)
158
159
160/** Counterpart to APIC_FOREACH_IN_SET_BEGIN and APIC_FOREACH_BEGIN. */
161#define APIC_FOREACH_END() \
162 } \
163 } while (0)
164
165#define DEBUG_APIC
166
167/* APIC Local Vector Table */
168#define APIC_LVT_TIMER 0
169#define APIC_LVT_THERMAL 1
170#define APIC_LVT_PERFORM 2
171#define APIC_LVT_LINT0 3
172#define APIC_LVT_LINT1 4
173#define APIC_LVT_ERROR 5
174#define APIC_LVT_NB 6
175
176/* APIC delivery modes */
177#define APIC_DM_FIXED 0
178#define APIC_DM_LOWPRI 1
179#define APIC_DM_SMI 2
180#define APIC_DM_NMI 4
181#define APIC_DM_INIT 5
182#define APIC_DM_SIPI 6
183#define APIC_DM_EXTINT 7
184
185/* APIC destination mode */
186#define APIC_DESTMODE_FLAT 0xf
187#define APIC_DESTMODE_CLUSTER 0x0
188
189#define APIC_TRIGGER_EDGE 0
190#define APIC_TRIGGER_LEVEL 1
191
192#define APIC_LVT_TIMER_PERIODIC (1<<17)
193#define APIC_LVT_MASKED (1<<16)
194#define APIC_LVT_LEVEL_TRIGGER (1<<15)
195#define APIC_LVT_REMOTE_IRR (1<<14)
196#define APIC_INPUT_POLARITY (1<<13)
197#define APIC_SEND_PENDING (1<<12)
198
199#define ESR_ILLEGAL_ADDRESS (1 << 7)
200
201#define APIC_SV_ENABLE (1 << 8)
202
203#define APIC_MAX_PATCH_ATTEMPTS 100
204
205typedef uint32_t PhysApicId;
206typedef uint32_t LogApicId;
207
208
209/*******************************************************************************
210* Structures and Typedefs *
211*******************************************************************************/
212typedef struct APIC256BITREG
213{
214 /** The bitmap data. */
215 uint32_t au32Bitmap[8 /*256/32*/];
216} APIC256BITREG;
217typedef APIC256BITREG *PAPIC256BITREG;
218typedef APIC256BITREG const *PCAPIC256BITREG;
219
220/**
221 * Tests if a bit in the 256-bit APIC register is set.
222 *
223 * @returns true if set, false if clear.
224 *
225 * @param pReg The register.
226 * @param iBit The bit to test for.
227 */
228DECLINLINE(bool) Apic256BitReg_IsBitSet(PCAPIC256BITREG pReg, unsigned iBit)
229{
230 Assert(iBit < 256);
231 return ASMBitTest(&pReg->au32Bitmap[0], iBit);
232}
233
234
235/**
236 * Sets a bit in the 256-bit APIC register is set.
237 *
238 * @param pReg The register.
239 * @param iBit The bit to set.
240 */
241DECLINLINE(void) Apic256BitReg_SetBit(PAPIC256BITREG pReg, unsigned iBit)
242{
243 Assert(iBit < 256);
244 return ASMBitSet(&pReg->au32Bitmap[0], iBit);
245}
246
247
248/**
249 * Clears a bit in the 256-bit APIC register is set.
250 *
251 * @param pReg The register.
252 * @param iBit The bit to clear.
253 */
254DECLINLINE(void) Apic256BitReg_ClearBit(PAPIC256BITREG pReg, unsigned iBit)
255{
256 Assert(iBit < 256);
257 return ASMBitClear(&pReg->au32Bitmap[0], iBit);
258}
259
260/**
261 * Clears all bits in the 256-bit APIC register set.
262 *
263 * @param pReg The register.
264 */
265DECLINLINE(void) Apic256BitReg_Empty(PAPIC256BITREG pReg)
266{
267 memset(&pReg->au32Bitmap[0], 0, sizeof(pReg->au32Bitmap));
268}
269
270/**
271 * Finds the last bit set in the register, i.e. the highest priority interrupt.
272 *
273 * @returns The index of the found bit, @a iRetAllClear if none was found.
274 *
275 * @param pReg The register.
276 * @param iRetAllClear What to return if all bits are clear.
277 */
278static int Apic256BitReg_FindLastSetBit(PCAPIC256BITREG pReg, int iRetAllClear)
279{
280 uint32_t i = RT_ELEMENTS(pReg->au32Bitmap);
281 while (i-- > 0)
282 {
283 uint32_t u = pReg->au32Bitmap[i];
284 if (u)
285 {
286 u = ASMBitLastSetU32(u);
287 u--;
288 u |= i << 5;
289 return (int)u;
290 }
291 }
292 return iRetAllClear;
293}
294
295
296typedef struct APICState
297{
298 uint32_t apicbase;
299 /* Task priority register (interrupt level) */
300 uint32_t tpr;
301 /* Logical APIC id - user programmable */
302 LogApicId id;
303 /* Physical APIC id - not visible to user, constant */
304 PhysApicId phys_id;
305 /** @todo: is it logical or physical? Not really used anyway now. */
306 PhysApicId arb_id;
307 uint32_t spurious_vec;
308 uint8_t log_dest;
309 uint8_t dest_mode;
310 APIC256BITREG isr; /**< in service register */
311 APIC256BITREG tmr; /**< trigger mode register */
312 APIC256BITREG irr; /**< interrupt request register */
313 uint32_t lvt[APIC_LVT_NB];
314 uint32_t esr; /* error register */
315 uint32_t icr[2];
316 uint32_t divide_conf;
317 int count_shift;
318 uint32_t initial_count;
319 uint32_t Alignment0;
320
321 /** The time stamp of the initial_count load, i.e. when it was started. */
322 uint64_t initial_count_load_time;
323 /** The time stamp of the next timer callback. */
324 uint64_t next_time;
325 /** The APIC timer - R3 Ptr. */
326 PTMTIMERR3 pTimerR3;
327 /** The APIC timer - R0 Ptr. */
328 PTMTIMERR0 pTimerR0;
329 /** The APIC timer - RC Ptr. */
330 PTMTIMERRC pTimerRC;
331 /** Whether the timer is armed or not */
332 bool fTimerArmed;
333 /** Alignment */
334 bool afAlignment[3];
335 /** The initial_count value used for the current frequency hint. */
336 uint32_t uHintedInitialCount;
337 /** The count_shift value used for the current frequency hint. */
338 uint32_t uHintedCountShift;
339 /** Timer description timer. */
340 R3PTRTYPE(char *) pszDesc;
341
342 /** The IRQ tags and source IDs for each (tracing purposes). */
343 uint32_t auTags[256];
344
345# ifdef VBOX_WITH_STATISTICS
346# if HC_ARCH_BITS == 32
347 uint32_t u32Alignment0;
348# endif
349 STAMCOUNTER StatTimerSetInitialCount;
350 STAMCOUNTER StatTimerSetInitialCountArm;
351 STAMCOUNTER StatTimerSetInitialCountDisarm;
352 STAMCOUNTER StatTimerSetLvt;
353 STAMCOUNTER StatTimerSetLvtClearPeriodic;
354 STAMCOUNTER StatTimerSetLvtPostponed;
355 STAMCOUNTER StatTimerSetLvtArmed;
356 STAMCOUNTER StatTimerSetLvtArm;
357 STAMCOUNTER StatTimerSetLvtArmRetries;
358 STAMCOUNTER StatTimerSetLvtNoRelevantChange;
359# endif
360
361} APICState;
362
363AssertCompileMemberAlignment(APICState, initial_count_load_time, 8);
364# ifdef VBOX_WITH_STATISTICS
365AssertCompileMemberAlignment(APICState, StatTimerSetInitialCount, 8);
366# endif
367
368typedef struct
369{
370 /** The device instance - R3 Ptr. */
371 PPDMDEVINSR3 pDevInsR3;
372 /** The APIC helpers - R3 Ptr. */
373 PCPDMAPICHLPR3 pApicHlpR3;
374 /** LAPICs states - R3 Ptr */
375 R3PTRTYPE(APICState *) paLapicsR3;
376 /** The critical section - R3 Ptr. */
377 R3PTRTYPE(PPDMCRITSECT) pCritSectR3;
378
379 /** The device instance - R0 Ptr. */
380 PPDMDEVINSR0 pDevInsR0;
381 /** The APIC helpers - R0 Ptr. */
382 PCPDMAPICHLPR0 pApicHlpR0;
383 /** LAPICs states - R0 Ptr */
384 R0PTRTYPE(APICState *) paLapicsR0;
385 /** The critical section - R3 Ptr. */
386 R0PTRTYPE(PPDMCRITSECT) pCritSectR0;
387
388 /** The device instance - RC Ptr. */
389 PPDMDEVINSRC pDevInsRC;
390 /** The APIC helpers - RC Ptr. */
391 PCPDMAPICHLPRC pApicHlpRC;
392 /** LAPICs states - RC Ptr */
393 RCPTRTYPE(APICState *) paLapicsRC;
394 /** The critical section - R3 Ptr. */
395 RCPTRTYPE(PPDMCRITSECT) pCritSectRC;
396
397 /** APIC specification version in this virtual hardware configuration. */
398 PDMAPICVERSION enmVersion;
399
400 /** Number of attempts made to optimize TPR accesses. */
401 uint32_t cTPRPatchAttempts;
402
403 /** Number of CPUs on the system (same as LAPIC count). */
404 uint32_t cCpus;
405 /** Whether we've got an IO APIC or not. */
406 bool fIoApic;
407 /** Alignment padding. */
408 bool afPadding[3];
409
410# ifdef VBOX_WITH_STATISTICS
411 STAMCOUNTER StatMMIOReadGC;
412 STAMCOUNTER StatMMIOReadHC;
413 STAMCOUNTER StatMMIOWriteGC;
414 STAMCOUNTER StatMMIOWriteHC;
415 STAMCOUNTER StatClearedActiveIrq;
416# endif
417} APICDeviceInfo;
418# ifdef VBOX_WITH_STATISTICS
419AssertCompileMemberAlignment(APICDeviceInfo, StatMMIOReadGC, 8);
420# endif
421
422#ifndef VBOX_DEVICE_STRUCT_TESTCASE
423
424/*******************************************************************************
425* Internal Functions *
426*******************************************************************************/
427static void apic_update_tpr(APICDeviceInfo *pDev, APICState* s, uint32_t val);
428
429static void apic_eoi(APICDeviceInfo *pDev, APICState* s); /* */
430static PVMCPUSET apic_get_delivery_bitmask(APICDeviceInfo* pDev, uint8_t dest, uint8_t dest_mode, PVMCPUSET pDstSet);
431static int apic_deliver(APICDeviceInfo* pDev, APICState *s,
432 uint8_t dest, uint8_t dest_mode,
433 uint8_t delivery_mode, uint8_t vector_num,
434 uint8_t polarity, uint8_t trigger_mode);
435static int apic_get_arb_pri(APICState const *s);
436static int apic_get_ppr(APICState const *s);
437static uint32_t apic_get_current_count(APICDeviceInfo const *pDev, APICState const *s);
438static void apicTimerSetInitialCount(APICDeviceInfo *pDev, APICState *s, uint32_t initial_count);
439static void apicTimerSetLvt(APICDeviceInfo *pDev, APICState *pApic, uint32_t fNew);
440static void apicSendInitIpi(APICDeviceInfo* pDev, APICState *s);
441
442static void apic_init_ipi(APICDeviceInfo* pDev, APICState *s);
443static void apic_set_irq(APICDeviceInfo* pDev, APICState *s, int vector_num, int trigger_mode, uint32_t uTagSrc);
444static bool apic_update_irq(APICDeviceInfo* pDev, APICState *s);
445
446
447DECLINLINE(APICState*) getLapicById(APICDeviceInfo *pDev, VMCPUID id)
448{
449 AssertFatalMsg(id < pDev->cCpus, ("CPU id %d out of range\n", id));
450 return &pDev->CTX_SUFF(paLapics)[id];
451}
452
453DECLINLINE(APICState*) getLapic(APICDeviceInfo* pDev)
454{
455 /* LAPIC's array is indexed by CPU id */
456 VMCPUID id = pDev->CTX_SUFF(pApicHlp)->pfnGetCpuId(pDev->CTX_SUFF(pDevIns));
457 return getLapicById(pDev, id);
458}
459
460DECLINLINE(VMCPUID) getCpuFromLapic(APICDeviceInfo* pDev, APICState *s)
461{
462 /* for now we assume LAPIC physical id == CPU id */
463 return (VMCPUID)s->phys_id;
464}
465
466DECLINLINE(void) cpuSetInterrupt(APICDeviceInfo* pDev, APICState *s, PDMAPICIRQ enmType = PDMAPICIRQ_HARDWARE)
467{
468 LogFlow(("apic: setting interrupt flag for cpu %d\n", getCpuFromLapic(pDev, s)));
469 pDev->CTX_SUFF(pApicHlp)->pfnSetInterruptFF(pDev->CTX_SUFF(pDevIns), enmType,
470 getCpuFromLapic(pDev, s));
471}
472
473DECLINLINE(void) cpuClearInterrupt(APICDeviceInfo* pDev, APICState *s, PDMAPICIRQ enmType = PDMAPICIRQ_HARDWARE)
474{
475 LogFlow(("apic: clear interrupt flag\n"));
476 pDev->CTX_SUFF(pApicHlp)->pfnClearInterruptFF(pDev->CTX_SUFF(pDevIns), enmType,
477 getCpuFromLapic(pDev, s));
478}
479
480# ifdef IN_RING3
481
482DECLINLINE(void) cpuSendSipi(APICDeviceInfo* pDev, APICState *s, int vector)
483{
484 Log2(("apic: send SIPI vector=%d\n", vector));
485
486 pDev->pApicHlpR3->pfnSendSipi(pDev->pDevInsR3,
487 getCpuFromLapic(pDev, s),
488 vector);
489}
490
491DECLINLINE(void) cpuSendInitIpi(APICDeviceInfo* pDev, APICState *s)
492{
493 Log2(("apic: send init IPI\n"));
494
495 pDev->pApicHlpR3->pfnSendInitIpi(pDev->pDevInsR3,
496 getCpuFromLapic(pDev, s));
497}
498
499# endif /* IN_RING3 */
500
501DECLINLINE(uint32_t) getApicEnableBits(APICDeviceInfo* pDev)
502{
503 switch (pDev->enmVersion)
504 {
505 case PDMAPICVERSION_NONE:
506 return 0;
507 case PDMAPICVERSION_APIC:
508 return MSR_IA32_APICBASE_ENABLE;
509 case PDMAPICVERSION_X2APIC:
510 return MSR_IA32_APICBASE_ENABLE | MSR_IA32_APICBASE_X2ENABLE ;
511 default:
512 AssertMsgFailed(("Unsupported APIC version %d\n", pDev->enmVersion));
513 return 0;
514 }
515}
516
517DECLINLINE(PDMAPICVERSION) getApicMode(APICState *apic)
518{
519 switch (((apic->apicbase) >> 10) & 0x3)
520 {
521 case 0:
522 return PDMAPICVERSION_NONE;
523 case 1:
524 default:
525 /* Invalid */
526 return PDMAPICVERSION_NONE;
527 case 2:
528 return PDMAPICVERSION_APIC;
529 case 3:
530 return PDMAPICVERSION_X2APIC;
531 }
532}
533
534static int apic_bus_deliver(APICDeviceInfo* pDev,
535 PCVMCPUSET pDstSet, uint8_t delivery_mode,
536 uint8_t vector_num, uint8_t polarity,
537 uint8_t trigger_mode, uint32_t uTagSrc)
538{
539 LogFlow(("apic_bus_deliver mask=%R[vmcpuset] mode=%x vector=%x polarity=%x trigger_mode=%x uTagSrc=%#x\n",
540 pDstSet, delivery_mode, vector_num, polarity, trigger_mode, uTagSrc));
541
542 switch (delivery_mode)
543 {
544 case APIC_DM_LOWPRI:
545 {
546 VMCPUID idDstCpu = VMCPUSET_FIND_FIRST_PRESENT(pDstSet);
547 if (idDstCpu != NIL_VMCPUID)
548 {
549 APICState *pApic = getLapicById(pDev, idDstCpu);
550 apic_set_irq(pDev, pApic, vector_num, trigger_mode, uTagSrc);
551 }
552 return VINF_SUCCESS;
553 }
554
555 case APIC_DM_FIXED:
556 /** @todo XXX: arbitration */
557 break;
558
559 case APIC_DM_SMI:
560 APIC_FOREACH_IN_SET_BEGIN(pDev, pDstSet);
561 cpuSetInterrupt(pDev, pCurApic, PDMAPICIRQ_SMI);
562 APIC_FOREACH_END();
563 return VINF_SUCCESS;
564
565 case APIC_DM_NMI:
566 APIC_FOREACH_IN_SET_BEGIN(pDev, pDstSet);
567 cpuSetInterrupt(pDev, pCurApic, PDMAPICIRQ_NMI);
568 APIC_FOREACH_END();
569 return VINF_SUCCESS;
570
571 case APIC_DM_INIT:
572 /* normal INIT IPI sent to processors */
573#ifdef IN_RING3
574 APIC_FOREACH_IN_SET_BEGIN(pDev, pDstSet);
575 apicSendInitIpi(pDev, pCurApic);
576 APIC_FOREACH_END();
577 return VINF_SUCCESS;
578#else
579 /* We shall send init IPI only in R3. */
580 return VINF_IOM_R3_MMIO_READ_WRITE;
581#endif /* IN_RING3 */
582
583 case APIC_DM_EXTINT:
584 /* handled in I/O APIC code */
585 break;
586
587 default:
588 return VINF_SUCCESS;
589 }
590
591 APIC_FOREACH_IN_SET_BEGIN(pDev, pDstSet);
592 apic_set_irq(pDev, pCurApic, vector_num, trigger_mode, uTagSrc);
593 APIC_FOREACH_END();
594 return VINF_SUCCESS;
595}
596
597
598PDMBOTHCBDECL(void) apicSetBase(PPDMDEVINS pDevIns, VMCPUID idCpu, uint64_t val)
599{
600 APICDeviceInfo *pDev = PDMINS_2_DATA(pDevIns, APICDeviceInfo *);
601 Assert(PDMCritSectIsOwner(pDev->CTX_SUFF(pCritSect)));
602 APICState *s = getLapicById(pDev, idCpu);
603 Log(("apicSetBase: %016RX64\n", val));
604
605 /** @todo: do we need to lock here ? */
606 /* APIC_LOCK_VOID(pDev, VERR_INTERNAL_ERROR); */
607 /** @todo If this change is valid immediately, then we should change the MMIO registration! */
608 /* We cannot change if this CPU is BSP or not by writing to MSR - it's hardwired */
609 PDMAPICVERSION oldMode = getApicMode(s);
610 s->apicbase =
611 (val & 0xfffff000) | /* base */
612 (val & getApicEnableBits(pDev)) | /* mode */
613 (s->apicbase & MSR_IA32_APICBASE_BSP) /* keep BSP bit */;
614 PDMAPICVERSION newMode = getApicMode(s);
615
616 if (oldMode != newMode)
617 {
618 switch (newMode)
619 {
620 case PDMAPICVERSION_NONE:
621 {
622 s->spurious_vec &= ~APIC_SV_ENABLE;
623 /* Clear any pending APIC interrupt action flag. */
624 cpuClearInterrupt(pDev, s);
625 /** @todo: why do we do that? */
626 pDev->CTX_SUFF(pApicHlp)->pfnChangeFeature(pDevIns, PDMAPICVERSION_NONE);
627 break;
628 }
629 case PDMAPICVERSION_APIC:
630 /** @todo: map MMIO ranges, if needed */
631 break;
632 case PDMAPICVERSION_X2APIC:
633 /** @todo: unmap MMIO ranges of this APIC, according to the spec */
634 break;
635 default:
636 break;
637 }
638 }
639 /* APIC_UNLOCK(pDev); */
640}
641
642PDMBOTHCBDECL(uint64_t) apicGetBase(PPDMDEVINS pDevIns, VMCPUID idCpu)
643{
644 APICDeviceInfo *pDev = PDMINS_2_DATA(pDevIns, APICDeviceInfo *);
645 Assert(PDMCritSectIsOwner(pDev->CTX_SUFF(pCritSect)));
646 APICState *s = getLapicById(pDev, idCpu);
647 LogFlow(("apicGetBase: %016llx\n", (uint64_t)s->apicbase));
648 return s->apicbase;
649}
650
651PDMBOTHCBDECL(void) apicSetTPR(PPDMDEVINS pDevIns, VMCPUID idCpu, uint8_t val)
652{
653 APICDeviceInfo *pDev = PDMINS_2_DATA(pDevIns, APICDeviceInfo *);
654 Assert(PDMCritSectIsOwner(pDev->CTX_SUFF(pCritSect)));
655 APICState *s = getLapicById(pDev, idCpu);
656 LogFlow(("apicSetTPR: val=%#x (trp %#x -> %#x)\n", val, s->tpr, val));
657 apic_update_tpr(pDev, s, val);
658}
659
660PDMBOTHCBDECL(uint8_t) apicGetTPR(PPDMDEVINS pDevIns, VMCPUID idCpu)
661{
662 /* We don't perform any locking here as that would cause a lot of contention for VT-x/AMD-V. */
663 APICDeviceInfo *pDev = PDMINS_2_DATA(pDevIns, APICDeviceInfo *);
664 APICState *s = getLapicById(pDev, idCpu);
665 Log2(("apicGetTPR: returns %#x\n", s->tpr));
666 return s->tpr;
667}
668
669
670/**
671 * apicWriteRegister helper for dealing with invalid register access.
672 *
673 * @returns Strict VBox status code.
674 * @param pDev The PDM device instance.
675 * @param pApic The APIC being written to.
676 * @param iReg The APIC register index.
677 * @param u64Value The value being written.
678 * @param rcBusy The busy return code to employ. See
679 * PDMCritSectEnter for a description.
680 * @param fMsr Set if called via MSR, clear if MMIO.
681 */
682static int apicWriteRegisterInvalid(APICDeviceInfo *pDev, APICState *pApic, uint32_t iReg, uint64_t u64Value,
683 int rcBusy, bool fMsr)
684{
685 Log(("apicWriteRegisterInvalid/%u: iReg=%#x fMsr=%RTbool u64Value=%#llx\n", pApic->phys_id, iReg, fMsr, u64Value));
686 int rc = PDMDevHlpDBGFStop(pDev->CTX_SUFF(pDevIns), RT_SRC_POS,
687 "iReg=%#x fMsr=%RTbool u64Value=%#llx id=%u\n", iReg, fMsr, u64Value, pApic->phys_id);
688 APIC_LOCK(pDev, rcBusy);
689 pApic->esr |= ESR_ILLEGAL_ADDRESS;
690 APIC_UNLOCK(pDev);
691 return rc;
692}
693
694
695
696/**
697 * Writes to an APIC register via MMIO or MSR.
698 *
699 * @returns Strict VBox status code.
700 * @param pDev The PDM device instance.
701 * @param pApic The APIC being written to.
702 * @param iReg The APIC register index.
703 * @param u64Value The value being written.
704 * @param rcBusy The busy return code to employ. See
705 * PDMCritSectEnter for a description.
706 * @param fMsr Set if called via MSR, clear if MMIO.
707 */
708static int apicWriteRegister(APICDeviceInfo *pDev, APICState *pApic, uint32_t iReg, uint64_t u64Value,
709 int rcBusy, bool fMsr)
710{
711 Assert(!PDMCritSectIsOwner(pDev->CTX_SUFF(pCritSect)));
712
713 int rc = VINF_SUCCESS;
714 switch (iReg)
715 {
716 case 0x02:
717 APIC_LOCK(pDev, rcBusy);
718 pApic->id = (u64Value >> 24); /** @todo r=bird: Is the range supposed to be 40 bits??? */
719 APIC_UNLOCK(pDev);
720 break;
721
722 case 0x03:
723 /* read only, ignore write. */
724 break;
725
726 case 0x08:
727 APIC_LOCK(pDev, rcBusy);
728 apic_update_tpr(pDev, pApic, u64Value);
729 APIC_UNLOCK(pDev);
730 break;
731
732 case 0x09: case 0x0a:
733 Log(("apicWriteRegister: write to read-only register %d ignored\n", iReg));
734 break;
735
736 case 0x0b: /* EOI */
737 APIC_LOCK(pDev, rcBusy);
738 apic_eoi(pDev, pApic);
739 APIC_UNLOCK(pDev);
740 break;
741
742 case 0x0d:
743 APIC_LOCK(pDev, rcBusy);
744 pApic->log_dest = (u64Value >> 24) & 0xff;
745 APIC_UNLOCK(pDev);
746 break;
747
748 case 0x0e:
749 APIC_LOCK(pDev, rcBusy);
750 pApic->dest_mode = u64Value >> 28; /** @todo r=bird: range? This used to be 32-bit before morphed into an MSR handler. */
751 APIC_UNLOCK(pDev);
752 break;
753
754 case 0x0f:
755 APIC_LOCK(pDev, rcBusy);
756 pApic->spurious_vec = u64Value & 0x1ff;
757 apic_update_irq(pDev, pApic);
758 APIC_UNLOCK(pDev);
759 break;
760
761 case 0x10: case 0x11: case 0x12: case 0x13: case 0x14: case 0x15: case 0x16: case 0x17:
762 case 0x18: case 0x19: case 0x1a: case 0x1b: case 0x1c: case 0x1d: case 0x1e: case 0x1f:
763 case 0x20: case 0x21: case 0x22: case 0x23: case 0x24: case 0x25: case 0x26: case 0x27:
764 case 0x28:
765 Log(("apicWriteRegister: write to read-only register %d ignored\n", iReg));
766 break;
767
768 case 0x30:
769 APIC_LOCK(pDev, rcBusy);
770 pApic->icr[0] = (uint32_t)u64Value;
771 if (fMsr) /* Here one of the differences with regular APIC: ICR is single 64-bit register */
772 pApic->icr[1] = (uint32_t)(u64Value >> 32);
773 rc = apic_deliver(pDev, pApic, (pApic->icr[1] >> 24) & 0xff, (pApic->icr[0] >> 11) & 1,
774 (pApic->icr[0] >> 8) & 7, (pApic->icr[0] & 0xff),
775 (pApic->icr[0] >> 14) & 1, (pApic->icr[0] >> 15) & 1);
776 APIC_UNLOCK(pDev);
777 break;
778
779 case 0x31:
780 if (!fMsr)
781 {
782 APIC_LOCK(pDev, rcBusy);
783 pApic->icr[1] = (uint64_t)u64Value;
784 APIC_UNLOCK(pDev);
785 }
786 else
787 rc = apicWriteRegisterInvalid(pDev, pApic, iReg, u64Value, rcBusy, fMsr);
788 break;
789
790 case 0x32 + APIC_LVT_TIMER:
791 AssertCompile(APIC_LVT_TIMER == 0);
792 APIC_AND_TM_LOCK(pDev, pApic, rcBusy);
793 apicTimerSetLvt(pDev, pApic, u64Value);
794 APIC_AND_TM_UNLOCK(pDev, pApic);
795 break;
796
797 case 0x33: case 0x34: case 0x35: case 0x36: case 0x37:
798 APIC_LOCK(pDev, rcBusy);
799 pApic->lvt[iReg - 0x32] = u64Value;
800 APIC_UNLOCK(pDev);
801 break;
802
803 case 0x38:
804 APIC_AND_TM_LOCK(pDev, pApic, rcBusy);
805 apicTimerSetInitialCount(pDev, pApic, u64Value);
806 APIC_AND_TM_UNLOCK(pDev, pApic);
807 break;
808
809 case 0x39:
810 Log(("apicWriteRegister: write to read-only register %d ignored\n", iReg));
811 break;
812
813 case 0x3e:
814 {
815 APIC_LOCK(pDev, rcBusy);
816 pApic->divide_conf = u64Value & 0xb;
817 int v = (pApic->divide_conf & 3) | ((pApic->divide_conf >> 1) & 4);
818 pApic->count_shift = (v + 1) & 7;
819 APIC_UNLOCK(pDev);
820 break;
821 }
822
823 case 0x3f:
824 if (fMsr)
825 {
826 /* Self IPI, see x2APIC book 2.4.5 */
827 APIC_LOCK(pDev, rcBusy);
828 int vector = u64Value & 0xff;
829 VMCPUSET SelfSet;
830 VMCPUSET_EMPTY(&SelfSet);
831 VMCPUSET_ADD(&SelfSet, pApic->id);
832 rc = apic_bus_deliver(pDev,
833 &SelfSet,
834 0 /* Delivery mode - fixed */,
835 vector,
836 0 /* Polarity - conform to the bus */,
837 0 /* Trigger mode - edge */,
838 pDev->CTX_SUFF(pApicHlp)->pfnCalcIrqTag(pDev->CTX_SUFF(pDevIns), PDM_IRQ_LEVEL_HIGH));
839 APIC_UNLOCK(pDev);
840 break;
841 }
842 /* else: fall thru */
843
844 default:
845 rc = apicWriteRegisterInvalid(pDev, pApic, iReg, u64Value, rcBusy, fMsr);
846 break;
847 }
848
849 return rc;
850}
851
852
853/**
854 * apicReadRegister helper for dealing with invalid register access.
855 *
856 * @returns Strict VBox status code.
857 * @param pDev The PDM device instance.
858 * @param pApic The APIC being read to.
859 * @param iReg The APIC register index.
860 * @param pu64Value Where to store the value we've read.
861 * @param rcBusy The busy return code to employ. See
862 * PDMCritSectEnter for a description.
863 * @param fMsr Set if called via MSR, clear if MMIO.
864 */
865static int apicReadRegisterInvalid(APICDeviceInfo *pDev, APICState *pApic, uint32_t iReg, uint64_t *pu64Value,
866 int rcBusy, bool fMsr)
867{
868 Log(("apicReadRegisterInvalid/%u: iReg=%#x fMsr=%RTbool\n", pApic->phys_id, iReg, fMsr));
869 int rc = PDMDevHlpDBGFStop(pDev->CTX_SUFF(pDevIns), RT_SRC_POS,
870 "iReg=%#x fMsr=%RTbool id=%u\n", iReg, fMsr, pApic->phys_id);
871 APIC_LOCK(pDev, rcBusy);
872 pApic->esr |= ESR_ILLEGAL_ADDRESS;
873 APIC_UNLOCK(pDev);
874 *pu64Value = 0;
875 return rc;
876}
877
878
879/**
880 * Read from an APIC register via MMIO or MSR.
881 *
882 * @returns Strict VBox status code.
883 * @param pDev The PDM device instance.
884 * @param pApic The APIC being read to.
885 * @param iReg The APIC register index.
886 * @param pu64Value Where to store the value we've read.
887 * @param rcBusy The busy return code to employ. See
888 * PDMCritSectEnter for a description.
889 * @param fMsr Set if called via MSR, clear if MMIO.
890 */
891static int apicReadRegister(APICDeviceInfo *pDev, APICState *pApic, uint32_t iReg, uint64_t *pu64Value,
892 int rcBusy, bool fMsr)
893{
894 Assert(!PDMCritSectIsOwner(pDev->CTX_SUFF(pCritSect)));
895
896 int rc = VINF_SUCCESS;
897 switch (iReg)
898 {
899 case 0x02: /* id */
900 APIC_LOCK(pDev, rcBusy);
901 *pu64Value = pApic->id << 24;
902 APIC_UNLOCK(pDev);
903 break;
904
905 case 0x03: /* version */
906 APIC_LOCK(pDev, rcBusy);
907 *pu64Value = APIC_HW_VERSION
908 | ((APIC_LVT_NB - 1) << 16) /* Max LVT index */
909#if 0
910 | (0 << 24) /* Support for EOI broadcast suppression */
911#endif
912 ;
913 APIC_UNLOCK(pDev);
914 break;
915
916 case 0x08:
917 APIC_LOCK(pDev, rcBusy);
918 *pu64Value = pApic->tpr;
919 APIC_UNLOCK(pDev);
920 break;
921
922 case 0x09:
923 *pu64Value = apic_get_arb_pri(pApic);
924 break;
925
926 case 0x0a:
927 /* ppr */
928 APIC_LOCK(pDev, rcBusy);
929 *pu64Value = apic_get_ppr(pApic);
930 APIC_UNLOCK(pDev);
931 break;
932
933 case 0x0b:
934 Log(("apicReadRegister: %x -> write only returning 0\n", iReg));
935 *pu64Value = 0;
936 break;
937
938 case 0x0d:
939 APIC_LOCK(pDev, rcBusy);
940 *pu64Value = (uint64_t)pApic->log_dest << 24;
941 APIC_UNLOCK(pDev);
942 break;
943
944 case 0x0e:
945 /* Bottom 28 bits are always 1 */
946 APIC_LOCK(pDev, rcBusy);
947 *pu64Value = ((uint64_t)pApic->dest_mode << 28) | UINT32_C(0xfffffff);
948 APIC_UNLOCK(pDev);
949 break;
950
951 case 0x0f:
952 APIC_LOCK(pDev, rcBusy);
953 *pu64Value = pApic->spurious_vec;
954 APIC_UNLOCK(pDev);
955 break;
956
957 case 0x10: case 0x11: case 0x12: case 0x13: case 0x14: case 0x15: case 0x16: case 0x17:
958 APIC_LOCK(pDev, rcBusy);
959 *pu64Value = pApic->isr.au32Bitmap[iReg & 7];
960 APIC_UNLOCK(pDev);
961 break;
962
963 case 0x18: case 0x19: case 0x1a: case 0x1b: case 0x1c: case 0x1d: case 0x1e: case 0x1f:
964 APIC_LOCK(pDev, rcBusy);
965 *pu64Value = pApic->tmr.au32Bitmap[iReg & 7];
966 APIC_UNLOCK(pDev);
967 break;
968
969 case 0x20: case 0x21: case 0x22: case 0x23: case 0x24: case 0x25: case 0x26: case 0x27:
970 APIC_LOCK(pDev, rcBusy);
971 *pu64Value = pApic->irr.au32Bitmap[iReg & 7];
972 APIC_UNLOCK(pDev);
973 break;
974
975 case 0x28:
976 APIC_LOCK(pDev, rcBusy);
977 *pu64Value = pApic->esr;
978 APIC_UNLOCK(pDev);
979 break;
980
981 case 0x30:
982 /* Here one of the differences with regular APIC: ICR is single 64-bit register */
983 APIC_LOCK(pDev, rcBusy);
984 if (fMsr)
985 *pu64Value = RT_MAKE_U64(pApic->icr[0], pApic->icr[1]);
986 else
987 *pu64Value = pApic->icr[0];
988 APIC_UNLOCK(pDev);
989 break;
990
991 case 0x31:
992 if (fMsr)
993 rc = apicReadRegisterInvalid(pDev, pApic, iReg, pu64Value, rcBusy, fMsr);
994 else
995 {
996 APIC_LOCK(pDev, rcBusy);
997 *pu64Value = pApic->icr[1];
998 APIC_UNLOCK(pDev);
999 }
1000 break;
1001
1002 case 0x32: case 0x33: case 0x34: case 0x35: case 0x36: case 0x37:
1003 APIC_LOCK(pDev, rcBusy);
1004 *pu64Value = pApic->lvt[iReg - 0x32];
1005 APIC_UNLOCK(pDev);
1006 break;
1007
1008 case 0x38:
1009 APIC_LOCK(pDev, rcBusy);
1010 *pu64Value = pApic->initial_count;
1011 APIC_UNLOCK(pDev);
1012 break;
1013
1014 case 0x39:
1015 APIC_AND_TM_LOCK(pDev, pApic, rcBusy);
1016 *pu64Value = apic_get_current_count(pDev, pApic);
1017 APIC_AND_TM_UNLOCK(pDev, pApic);
1018 break;
1019
1020 case 0x3e:
1021 APIC_LOCK(pDev, rcBusy);
1022 *pu64Value = pApic->divide_conf;
1023 APIC_UNLOCK(pDev);
1024 break;
1025
1026 case 0x3f:
1027 if (fMsr)
1028 {
1029 /* Self IPI register is write only */
1030 Log(("apicReadMSR: read from write-only register %d ignored\n", iReg));
1031 *pu64Value = 0;
1032 }
1033 else
1034 rc = apicReadRegisterInvalid(pDev, pApic, iReg, pu64Value, rcBusy, fMsr);
1035 break;
1036 case 0x2f: /** @todo Correctable machine check exception vector, implement me! */
1037 default:
1038 /**
1039 * @todo: according to spec when APIC writes to ESR it msut raise error interrupt,
1040 * i.e. LVT[5]
1041 */
1042 rc = apicReadRegisterInvalid(pDev, pApic, iReg, pu64Value, rcBusy, fMsr);
1043 break;
1044 }
1045 return rc;
1046}
1047
1048/**
1049 * @interface_method_impl{PDMAPICREG,pfnWriteMSRR3}
1050 */
1051PDMBOTHCBDECL(int) apicWriteMSR(PPDMDEVINS pDevIns, VMCPUID idCpu, uint32_t u32Reg, uint64_t u64Value)
1052{
1053 APICDeviceInfo *pDev = PDMINS_2_DATA(pDevIns, APICDeviceInfo *);
1054 if (pDev->enmVersion < PDMAPICVERSION_X2APIC)
1055 return VERR_EM_INTERPRETER; /** @todo tell the caller to raise hell (\#GP(0)). */
1056
1057 APICState *pApic = getLapicById(pDev, idCpu);
1058 uint32_t iReg = (u32Reg - MSR_IA32_X2APIC_START) & 0xff;
1059 return apicWriteRegister(pDev, pApic, iReg, u64Value, VINF_SUCCESS /*rcBusy*/, true /*fMsr*/);
1060}
1061
1062
1063/**
1064 * @interface_method_impl{PDMAPICREG,pfnReadMSRR3}
1065 */
1066PDMBOTHCBDECL(int) apicReadMSR(PPDMDEVINS pDevIns, VMCPUID idCpu, uint32_t u32Reg, uint64_t *pu64Value)
1067{
1068 APICDeviceInfo *pDev = PDMINS_2_DATA(pDevIns, APICDeviceInfo *);
1069
1070 if (pDev->enmVersion < PDMAPICVERSION_X2APIC)
1071 return VERR_EM_INTERPRETER;
1072
1073 APICState *pApic = getLapicById(pDev, idCpu);
1074 uint32_t iReg = (u32Reg - MSR_IA32_X2APIC_START) & 0xff;
1075 return apicReadRegister(pDev, pApic, iReg, pu64Value, VINF_SUCCESS /*rcBusy*/, true /*fMsr*/);
1076}
1077
1078/**
1079 * More or less private interface between IOAPIC, only PDM is responsible
1080 * for connecting the two devices.
1081 */
1082PDMBOTHCBDECL(int) apicBusDeliverCallback(PPDMDEVINS pDevIns, uint8_t u8Dest, uint8_t u8DestMode,
1083 uint8_t u8DeliveryMode, uint8_t iVector, uint8_t u8Polarity,
1084 uint8_t u8TriggerMode, uint32_t uTagSrc)
1085{
1086 APICDeviceInfo *pDev = PDMINS_2_DATA(pDevIns, APICDeviceInfo *);
1087 Assert(PDMCritSectIsOwner(pDev->CTX_SUFF(pCritSect)));
1088 LogFlow(("apicBusDeliverCallback: pDevIns=%p u8Dest=%#x u8DestMode=%#x u8DeliveryMode=%#x iVector=%#x u8Polarity=%#x u8TriggerMode=%#x uTagSrc=%#x\n",
1089 pDevIns, u8Dest, u8DestMode, u8DeliveryMode, iVector, u8Polarity, u8TriggerMode, uTagSrc));
1090 VMCPUSET DstSet;
1091 return apic_bus_deliver(pDev, apic_get_delivery_bitmask(pDev, u8Dest, u8DestMode, &DstSet),
1092 u8DeliveryMode, iVector, u8Polarity, u8TriggerMode, uTagSrc);
1093}
1094
1095/**
1096 * Local interrupt delivery, for devices attached to the CPU's LINT0/LINT1 pin.
1097 * Normally used for 8259A PIC and NMI.
1098 */
1099PDMBOTHCBDECL(int) apicLocalInterrupt(PPDMDEVINS pDevIns, uint8_t u8Pin, uint8_t u8Level)
1100{
1101 APICDeviceInfo *pDev = PDMINS_2_DATA(pDevIns, APICDeviceInfo *);
1102 APICState *s = getLapicById(pDev, 0);
1103
1104 Assert(PDMCritSectIsOwner(pDev->CTX_SUFF(pCritSect)));
1105 LogFlow(("apicLocalInterrupt: pDevIns=%p u8Pin=%x u8Level=%x\n", pDevIns, u8Pin, u8Level));
1106
1107 /* If LAPIC is disabled, go straight to the CPU. */
1108 if (!(s->spurious_vec & APIC_SV_ENABLE))
1109 {
1110 LogFlow(("apicLocalInterrupt: LAPIC disabled, delivering directly to CPU core.\n"));
1111 if (u8Level)
1112 cpuSetInterrupt(pDev, s, PDMAPICIRQ_EXTINT);
1113 else
1114 cpuClearInterrupt(pDev, s, PDMAPICIRQ_EXTINT);
1115
1116 return VINF_SUCCESS;
1117 }
1118
1119 /* If LAPIC is enabled, interrupts are subject to LVT programming. */
1120
1121 /* There are only two local interrupt pins. */
1122 AssertMsgReturn(u8Pin <= 1, ("Invalid LAPIC pin %d\n", u8Pin), VERR_INVALID_PARAMETER);
1123
1124 /* NB: We currently only deliver local interrupts to the first CPU. In theory they
1125 * should be delivered to all CPUs and it is the guest's responsibility to ensure
1126 * no more than one CPU has the interrupt unmasked.
1127 */
1128 uint32_t u32Lvec;
1129
1130 u32Lvec = s->lvt[APIC_LVT_LINT0 + u8Pin]; /* Fetch corresponding LVT entry. */
1131 /* Drop int if entry is masked. May not be correct for level-triggered interrupts. */
1132 if (!(u32Lvec & APIC_LVT_MASKED))
1133 { uint8_t u8Delivery;
1134 PDMAPICIRQ enmType;
1135
1136 u8Delivery = (u32Lvec >> 8) & 7;
1137 switch (u8Delivery)
1138 {
1139 case APIC_DM_EXTINT:
1140 Assert(u8Pin == 0); /* PIC should be wired to LINT0. */
1141 enmType = PDMAPICIRQ_EXTINT;
1142 /* ExtINT can be both set and cleared, NMI/SMI/INIT can only be set. */
1143 LogFlow(("apicLocalInterrupt: %s ExtINT interrupt\n", u8Level ? "setting" : "clearing"));
1144 if (u8Level)
1145 cpuSetInterrupt(pDev, s, enmType);
1146 else
1147 cpuClearInterrupt(pDev, s, enmType);
1148 return VINF_SUCCESS;
1149 case APIC_DM_NMI:
1150 /* External NMI should be wired to LINT1, but Linux sometimes programs
1151 * LVT0 to NMI delivery mode as well.
1152 */
1153 enmType = PDMAPICIRQ_NMI;
1154 /* Currently delivering NMIs through here causes problems with NMI watchdogs
1155 * on certain Linux kernels, e.g. 64-bit CentOS 5.3. Disable NMIs for now.
1156 */
1157 return VINF_SUCCESS;
1158 case APIC_DM_SMI:
1159 enmType = PDMAPICIRQ_SMI;
1160 break;
1161 case APIC_DM_FIXED:
1162 {
1163 /** @todo implement APIC_DM_FIXED! */
1164 static unsigned s_c = 0;
1165 if (s_c++ < 5)
1166 LogRel(("delivery type APIC_DM_FIXED not implemented. u8Pin=%d u8Level=%d\n", u8Pin, u8Level));
1167 return VINF_SUCCESS;
1168 }
1169 case APIC_DM_INIT:
1170 /** @todo implement APIC_DM_INIT? */
1171 default:
1172 {
1173 static unsigned s_c = 0;
1174 if (s_c++ < 100)
1175 AssertLogRelMsgFailed(("delivery type %d not implemented. u8Pin=%d u8Level=%d\n", u8Delivery, u8Pin, u8Level));
1176 return VERR_INTERNAL_ERROR_4;
1177 }
1178 }
1179 LogFlow(("apicLocalInterrupt: setting local interrupt type %d\n", enmType));
1180 cpuSetInterrupt(pDev, s, enmType);
1181 }
1182 return VINF_SUCCESS;
1183}
1184
1185static int apic_get_ppr(APICState const *s)
1186{
1187 int ppr;
1188
1189 int tpr = (s->tpr >> 4);
1190 int isrv = Apic256BitReg_FindLastSetBit(&s->isr, 0);
1191 isrv >>= 4;
1192 if (tpr >= isrv)
1193 ppr = s->tpr;
1194 else
1195 ppr = isrv << 4;
1196 return ppr;
1197}
1198
1199static int apic_get_ppr_zero_tpr(APICState *s)
1200{
1201 return Apic256BitReg_FindLastSetBit(&s->isr, 0);
1202}
1203
1204static int apic_get_arb_pri(APICState const *s)
1205{
1206 /** @todo XXX: arbitration */
1207 return 0;
1208}
1209
1210/* signal the CPU if an irq is pending */
1211static bool apic_update_irq(APICDeviceInfo *pDev, APICState* s)
1212{
1213 if (!(s->spurious_vec & APIC_SV_ENABLE))
1214 {
1215 /* Clear any pending APIC interrupt action flag. */
1216 cpuClearInterrupt(pDev, s);
1217 return false;
1218 }
1219
1220 int irrv = Apic256BitReg_FindLastSetBit(&s->irr, -1);
1221 if (irrv < 0)
1222 return false;
1223 int ppr = apic_get_ppr(s);
1224 if (ppr && (irrv & 0xf0) <= (ppr & 0xf0))
1225 return false;
1226 cpuSetInterrupt(pDev, s);
1227 return true;
1228}
1229
1230/* Check if the APIC has a pending interrupt/if a TPR change would active one. */
1231PDMBOTHCBDECL(bool) apicHasPendingIrq(PPDMDEVINS pDevIns, VMCPUID idCpu)
1232{
1233 APICDeviceInfo *pDev = PDMINS_2_DATA(pDevIns, APICDeviceInfo *);
1234 if (!pDev)
1235 return false;
1236
1237 /* We don't perform any locking here as that would cause a lot of contention for VT-x/AMD-V. */
1238
1239 APICState *s = getLapicById(pDev, idCpu);
1240
1241 /*
1242 * All our callbacks now come from single IOAPIC, thus locking
1243 * seems to be excessive now
1244 */
1245 /** @todo check excessive locking whatever... */
1246 int irrv = Apic256BitReg_FindLastSetBit(&s->irr, -1);
1247 if (irrv < 0)
1248 return false;
1249
1250 int ppr = apic_get_ppr_zero_tpr(s);
1251
1252 if (ppr && (irrv & 0xf0) <= (ppr & 0xf0))
1253 return false;
1254
1255 return true;
1256}
1257
1258static void apic_update_tpr(APICDeviceInfo *pDev, APICState* s, uint32_t val)
1259{
1260 bool fIrqIsActive = false;
1261 bool fIrqWasActive = false;
1262
1263 fIrqWasActive = apic_update_irq(pDev, s);
1264 s->tpr = val;
1265 fIrqIsActive = apic_update_irq(pDev, s);
1266
1267 /* If an interrupt is pending and now masked, then clear the FF flag. */
1268 if (fIrqWasActive && !fIrqIsActive)
1269 {
1270 Log(("apic_update_tpr: deactivate interrupt that was masked by the TPR update (%x)\n", val));
1271 STAM_COUNTER_INC(&pDev->StatClearedActiveIrq);
1272 cpuClearInterrupt(pDev, s);
1273 }
1274}
1275
1276static void apic_set_irq(APICDeviceInfo *pDev, APICState* s, int vector_num, int trigger_mode, uint32_t uTagSrc)
1277{
1278 LogFlow(("CPU%d: apic_set_irq vector=%x trigger_mode=%x uTagSrc=%#x\n", s->phys_id, vector_num, trigger_mode, uTagSrc));
1279
1280 Apic256BitReg_SetBit(&s->irr, vector_num);
1281 if (trigger_mode)
1282 Apic256BitReg_SetBit(&s->tmr, vector_num);
1283 else
1284 Apic256BitReg_ClearBit(&s->tmr, vector_num);
1285
1286 if (!s->auTags[vector_num])
1287 s->auTags[vector_num] = uTagSrc;
1288 else
1289 s->auTags[vector_num] |= RT_BIT_32(31);
1290
1291 apic_update_irq(pDev, s);
1292}
1293
1294static void apic_eoi(APICDeviceInfo *pDev, APICState* s)
1295{
1296 int isrv = Apic256BitReg_FindLastSetBit(&s->isr, -1);
1297 if (isrv < 0)
1298 return;
1299 Apic256BitReg_ClearBit(&s->isr, isrv);
1300 LogFlow(("CPU%d: apic_eoi isrv=%x\n", s->phys_id, isrv));
1301 /** @todo XXX: send the EOI packet to the APIC bus to allow the I/O APIC to
1302 * set the remote IRR bit for level triggered interrupts. */
1303 apic_update_irq(pDev, s);
1304}
1305
1306static PVMCPUSET apic_get_delivery_bitmask(APICDeviceInfo *pDev, uint8_t dest, uint8_t dest_mode, PVMCPUSET pDstSet)
1307{
1308 VMCPUSET_EMPTY(pDstSet);
1309
1310 if (dest_mode == 0)
1311 {
1312 if (dest == 0xff) /* The broadcast ID. */
1313 VMCPUSET_FILL(pDstSet);
1314 else
1315 VMCPUSET_ADD(pDstSet, dest);
1316 }
1317 else
1318 {
1319 /** @todo XXX: cluster mode */
1320 APIC_FOREACH_BEGIN(pDev);
1321 if (pCurApic->dest_mode == APIC_DESTMODE_FLAT)
1322 {
1323 if (dest & pCurApic->log_dest)
1324 VMCPUSET_ADD(pDstSet, iCurApic);
1325 }
1326 else if (pCurApic->dest_mode == APIC_DESTMODE_CLUSTER)
1327 {
1328 if ( (dest & 0xf0) == (pCurApic->log_dest & 0xf0)
1329 && (dest & pCurApic->log_dest & 0x0f))
1330 VMCPUSET_ADD(pDstSet, iCurApic);
1331 }
1332 APIC_FOREACH_END();
1333 }
1334
1335 return pDstSet;
1336}
1337
1338#ifdef IN_RING3
1339static void apic_init_ipi(APICDeviceInfo* pDev, APICState *s)
1340{
1341 int i;
1342
1343 for(i = 0; i < APIC_LVT_NB; i++)
1344 s->lvt[i] = 1 << 16; /* mask LVT */
1345 s->tpr = 0;
1346 s->spurious_vec = 0xff;
1347 s->log_dest = 0;
1348 s->dest_mode = 0xff; /** @todo 0xff???? */
1349 Apic256BitReg_Empty(&s->isr);
1350 Apic256BitReg_Empty(&s->tmr);
1351 Apic256BitReg_Empty(&s->irr);
1352 s->esr = 0;
1353 memset(s->icr, 0, sizeof(s->icr));
1354 s->divide_conf = 0;
1355 s->count_shift = 1;
1356 s->initial_count = 0;
1357 s->initial_count_load_time = 0;
1358 s->next_time = 0;
1359}
1360
1361
1362static void apicSendInitIpi(APICDeviceInfo* pDev, APICState *s)
1363{
1364 apic_init_ipi(pDev, s);
1365 cpuSendInitIpi(pDev, s);
1366}
1367
1368/* send a SIPI message to the CPU to start it */
1369static void apic_startup(APICDeviceInfo* pDev, APICState *s, int vector_num)
1370{
1371 Log(("[SMP] apic_startup: %d on CPUs %d\n", vector_num, s->phys_id));
1372 cpuSendSipi(pDev, s, vector_num);
1373}
1374#endif /* IN_RING3 */
1375
1376static int apic_deliver(APICDeviceInfo *pDev, APICState *s,
1377 uint8_t dest, uint8_t dest_mode,
1378 uint8_t delivery_mode, uint8_t vector_num,
1379 uint8_t polarity, uint8_t trigger_mode)
1380{
1381 int dest_shorthand = (s->icr[0] >> 18) & 3;
1382 LogFlow(("apic_deliver dest=%x dest_mode=%x dest_shorthand=%x delivery_mode=%x vector_num=%x polarity=%x trigger_mode=%x uTagSrc=%#x\n", dest, dest_mode, dest_shorthand, delivery_mode, vector_num, polarity, trigger_mode));
1383
1384 VMCPUSET DstSet;
1385 switch (dest_shorthand)
1386 {
1387 case 0:
1388 apic_get_delivery_bitmask(pDev, dest, dest_mode, &DstSet);
1389 break;
1390 case 1:
1391 VMCPUSET_EMPTY(&DstSet);
1392 VMCPUSET_ADD(&DstSet, s->id);
1393 break;
1394 case 2:
1395 VMCPUSET_FILL(&DstSet);
1396 break;
1397 case 3:
1398 VMCPUSET_FILL(&DstSet);
1399 VMCPUSET_DEL(&DstSet, s->id);
1400 break;
1401 }
1402
1403 switch (delivery_mode)
1404 {
1405 case APIC_DM_INIT:
1406 {
1407 uint32_t const trig_mode = (s->icr[0] >> 15) & 1;
1408 uint32_t const level = (s->icr[0] >> 14) & 1;
1409 if (level == 0 && trig_mode == 1)
1410 {
1411 APIC_FOREACH_IN_SET_BEGIN(pDev, &DstSet);
1412 pCurApic->arb_id = pCurApic->id;
1413 APIC_FOREACH_END();
1414 Log(("CPU%d: APIC_DM_INIT arbitration id(s) set\n", s->phys_id));
1415 return VINF_SUCCESS;
1416 }
1417 break;
1418 }
1419
1420 case APIC_DM_SIPI:
1421# ifdef IN_RING3
1422 APIC_FOREACH_IN_SET_BEGIN(pDev, &DstSet);
1423 apic_startup(pDev, pCurApic, vector_num);
1424 APIC_FOREACH_END();
1425 return VINF_SUCCESS;
1426# else
1427 /* We shall send SIPI only in R3, R0 calls should be
1428 rescheduled to R3 */
1429 return VINF_IOM_R3_MMIO_WRITE;
1430# endif
1431 }
1432
1433 return apic_bus_deliver(pDev, &DstSet, delivery_mode, vector_num,
1434 polarity, trigger_mode,
1435 pDev->CTX_SUFF(pApicHlp)->pfnCalcIrqTag(pDev->CTX_SUFF(pDevIns), PDM_IRQ_LEVEL_HIGH));
1436}
1437
1438
1439PDMBOTHCBDECL(int) apicGetInterrupt(PPDMDEVINS pDevIns, VMCPUID idCpu, uint32_t *puTagSrc)
1440{
1441 APICDeviceInfo *pDev = PDMINS_2_DATA(pDevIns, APICDeviceInfo *);
1442 /* if the APIC is not installed or enabled, we let the 8259 handle the
1443 IRQs */
1444 if (!pDev)
1445 {
1446 Log(("apic_get_interrupt: returns -1 (!s)\n"));
1447 return -1;
1448 }
1449
1450 Assert(PDMCritSectIsOwner(pDev->CTX_SUFF(pCritSect)));
1451
1452 APICState *s = getLapicById(pDev, idCpu);
1453
1454 if (!(s->spurious_vec & APIC_SV_ENABLE))
1455 {
1456 Log(("CPU%d: apic_get_interrupt: returns -1 (APIC_SV_ENABLE)\n", s->phys_id));
1457 return -1;
1458 }
1459
1460 /** @todo XXX: spurious IRQ handling */
1461 int intno = Apic256BitReg_FindLastSetBit(&s->irr, -1);
1462 if (intno < 0)
1463 {
1464 Log(("CPU%d: apic_get_interrupt: returns -1 (irr)\n", s->phys_id));
1465 return -1;
1466 }
1467
1468 if (s->tpr && (uint32_t)intno <= s->tpr)
1469 {
1470 *puTagSrc = 0;
1471 Log(("apic_get_interrupt: returns %d (sp)\n", s->spurious_vec & 0xff));
1472 return s->spurious_vec & 0xff;
1473 }
1474
1475 Apic256BitReg_ClearBit(&s->irr, intno);
1476 Apic256BitReg_SetBit(&s->isr, intno);
1477
1478 *puTagSrc = s->auTags[intno];
1479 s->auTags[intno] = 0;
1480
1481 apic_update_irq(pDev, s);
1482
1483 LogFlow(("CPU%d: apic_get_interrupt: returns %d / %#x\n", s->phys_id, intno, *puTagSrc));
1484 return intno;
1485}
1486
1487/**
1488 * @remarks Caller (apicReadRegister) takes both the TM and APIC locks before
1489 * calling this function.
1490 */
1491static uint32_t apic_get_current_count(APICDeviceInfo const *pDev, APICState const *pApic)
1492{
1493 int64_t d = (TMTimerGet(pApic->CTX_SUFF(pTimer)) - pApic->initial_count_load_time)
1494 >> pApic->count_shift;
1495
1496 uint32_t val;
1497 if (pApic->lvt[APIC_LVT_TIMER] & APIC_LVT_TIMER_PERIODIC)
1498 /* periodic */
1499 val = pApic->initial_count - (d % ((uint64_t)pApic->initial_count + 1));
1500 else if (d >= pApic->initial_count)
1501 val = 0;
1502 else
1503 val = pApic->initial_count - d;
1504
1505 return val;
1506}
1507
1508/**
1509 * Does the frequency hinting and logging.
1510 *
1511 * @param pApic The device state.
1512 */
1513DECLINLINE(void) apicDoFrequencyHinting(APICState *pApic)
1514{
1515 if ( pApic->uHintedInitialCount != pApic->initial_count
1516 || pApic->uHintedCountShift != (uint32_t)pApic->count_shift)
1517 {
1518 pApic->uHintedInitialCount = pApic->initial_count;
1519 pApic->uHintedCountShift = pApic->count_shift;
1520
1521 uint32_t uHz;
1522 if (pApic->initial_count > 0)
1523 {
1524 Assert((unsigned)pApic->count_shift < 30);
1525 uint64_t cTickPerPeriod = ((uint64_t)pApic->initial_count + 1) << pApic->count_shift;
1526 uHz = TMTimerGetFreq(pApic->CTX_SUFF(pTimer)) / cTickPerPeriod;
1527 }
1528 else
1529 uHz = 0;
1530 TMTimerSetFrequencyHint(pApic->CTX_SUFF(pTimer), uHz);
1531 Log(("apic: %u Hz\n", uHz));
1532 }
1533}
1534
1535/**
1536 * Implementation of the 0380h access: Timer reset + new initial count.
1537 *
1538 * @param pDev The device state.
1539 * @param pApic The APIC sub-device state.
1540 * @param u32NewInitialCount The new initial count for the timer.
1541 */
1542static void apicTimerSetInitialCount(APICDeviceInfo *pDev, APICState *pApic, uint32_t u32NewInitialCount)
1543{
1544 STAM_COUNTER_INC(&pApic->StatTimerSetInitialCount);
1545 pApic->initial_count = u32NewInitialCount;
1546
1547 /*
1548 * Don't (re-)arm the timer if the it's masked or if it's
1549 * a zero length one-shot timer.
1550 */
1551 if ( !(pApic->lvt[APIC_LVT_TIMER] & APIC_LVT_MASKED)
1552 && u32NewInitialCount > 0)
1553 {
1554 /*
1555 * Calculate the relative next time and perform a combined timer get/set
1556 * operation. This avoids racing the clock between get and set.
1557 */
1558 uint64_t cTicksNext = u32NewInitialCount;
1559 cTicksNext += 1;
1560 cTicksNext <<= pApic->count_shift;
1561 TMTimerSetRelative(pApic->CTX_SUFF(pTimer), cTicksNext, &pApic->initial_count_load_time);
1562 pApic->next_time = pApic->initial_count_load_time + cTicksNext;
1563 pApic->fTimerArmed = true;
1564 apicDoFrequencyHinting(pApic);
1565 STAM_COUNTER_INC(&pApic->StatTimerSetInitialCountArm);
1566 Log(("apicTimerSetInitialCount: cTicksNext=%'llu (%#llx) ic=%#x sh=%#x nxt=%#llx\n",
1567 cTicksNext, cTicksNext, u32NewInitialCount, pApic->count_shift, pApic->next_time));
1568 }
1569 else
1570 {
1571 /* Stop it if necessary and record the load time for unmasking. */
1572 if (pApic->fTimerArmed)
1573 {
1574 STAM_COUNTER_INC(&pApic->StatTimerSetInitialCountDisarm);
1575 TMTimerStop(pApic->CTX_SUFF(pTimer));
1576 pApic->fTimerArmed = false;
1577 pApic->uHintedCountShift = pApic->uHintedInitialCount = 0;
1578 }
1579 pApic->initial_count_load_time = TMTimerGet(pApic->CTX_SUFF(pTimer));
1580 Log(("apicTimerSetInitialCount: ic=%#x sh=%#x iclt=%#llx\n", u32NewInitialCount, pApic->count_shift, pApic->initial_count_load_time));
1581 }
1582}
1583
1584/**
1585 * Implementation of the 0320h access: change the LVT flags.
1586 *
1587 * @param pDev The device state.
1588 * @param pApic The APIC sub-device state to operate on.
1589 * @param fNew The new flags.
1590 */
1591static void apicTimerSetLvt(APICDeviceInfo *pDev, APICState *pApic, uint32_t fNew)
1592{
1593 STAM_COUNTER_INC(&pApic->StatTimerSetLvt);
1594
1595 /*
1596 * Make the flag change, saving the old ones so we can avoid
1597 * unnecessary work.
1598 */
1599 uint32_t const fOld = pApic->lvt[APIC_LVT_TIMER];
1600 pApic->lvt[APIC_LVT_TIMER] = fNew;
1601
1602 /* Only the masked and peridic bits are relevant (see apic_timer_update). */
1603 if ( (fOld & (APIC_LVT_MASKED | APIC_LVT_TIMER_PERIODIC))
1604 != (fNew & (APIC_LVT_MASKED | APIC_LVT_TIMER_PERIODIC)))
1605 {
1606 /*
1607 * If changed to one-shot from periodic, stop the timer if we're not
1608 * in the first period.
1609 */
1610 /** @todo check how clearing the periodic flag really should behave when not
1611 * in period 1. The current code just mirrors the behavior of the
1612 * original implementation. */
1613 if ( (fOld & APIC_LVT_TIMER_PERIODIC)
1614 && !(fNew & APIC_LVT_TIMER_PERIODIC))
1615 {
1616 STAM_COUNTER_INC(&pApic->StatTimerSetLvtClearPeriodic);
1617 uint64_t cTicks = (pApic->next_time - pApic->initial_count_load_time) >> pApic->count_shift;
1618 if (cTicks >= pApic->initial_count)
1619 {
1620 /* not first period, stop it. */
1621 TMTimerStop(pApic->CTX_SUFF(pTimer));
1622 pApic->fTimerArmed = false;
1623 pApic->uHintedCountShift = pApic->uHintedInitialCount = 0;
1624 }
1625 /* else: first period, let it fire normally. */
1626 }
1627
1628 /*
1629 * We postpone stopping the timer when it's masked, this way we can
1630 * avoid some timer work when the guest temporarily masks the timer.
1631 * (apicR3TimerCallback will stop it if still masked.)
1632 */
1633 if (fNew & APIC_LVT_MASKED)
1634 STAM_COUNTER_INC(&pApic->StatTimerSetLvtPostponed);
1635 else if (pApic->fTimerArmed)
1636 STAM_COUNTER_INC(&pApic->StatTimerSetLvtArmed);
1637 /*
1638 * If unmasked, not armed and with a valid initial count value (according
1639 * to our interpretation of the spec), we will have to rearm the timer so
1640 * it will fire at the end of the current period.
1641 *
1642 * N.B. This is code is currently RACING the virtual sync clock!
1643 */
1644 else if ( (fOld & APIC_LVT_MASKED)
1645 && pApic->initial_count > 0)
1646 {
1647 STAM_COUNTER_INC(&pApic->StatTimerSetLvtArm);
1648 for (unsigned cTries = 0; ; cTries++)
1649 {
1650 uint64_t NextTS;
1651 uint64_t cTicks = (TMTimerGet(pApic->CTX_SUFF(pTimer)) - pApic->initial_count_load_time) >> pApic->count_shift;
1652 if (fNew & APIC_LVT_TIMER_PERIODIC)
1653 NextTS = ((cTicks / ((uint64_t)pApic->initial_count + 1)) + 1) * ((uint64_t)pApic->initial_count + 1);
1654 else
1655 {
1656 if (cTicks >= pApic->initial_count)
1657 break;
1658 NextTS = (uint64_t)pApic->initial_count + 1;
1659 }
1660 NextTS <<= pApic->count_shift;
1661 NextTS += pApic->initial_count_load_time;
1662
1663 /* Try avoid the assertion in TM.cpp... this isn't perfect! */
1664 if ( NextTS > TMTimerGet(pApic->CTX_SUFF(pTimer))
1665 || cTries > 10)
1666 {
1667 TMTimerSet(pApic->CTX_SUFF(pTimer), NextTS);
1668 pApic->next_time = NextTS;
1669 pApic->fTimerArmed = true;
1670 apicDoFrequencyHinting(pApic);
1671 Log(("apicTimerSetLvt: ic=%#x sh=%#x nxt=%#llx\n", pApic->initial_count, pApic->count_shift, pApic->next_time));
1672 break;
1673 }
1674 STAM_COUNTER_INC(&pApic->StatTimerSetLvtArmRetries);
1675 }
1676 }
1677 }
1678 else
1679 STAM_COUNTER_INC(&pApic->StatTimerSetLvtNoRelevantChange);
1680}
1681
1682# ifdef IN_RING3
1683/**
1684 * Timer callback function.
1685 *
1686 * @param pDevIns The device state.
1687 * @param pTimer The timer handle.
1688 * @param pvUser User argument pointing to the APIC instance.
1689 */
1690static DECLCALLBACK(void) apicR3TimerCallback(PPDMDEVINS pDevIns, PTMTIMER pTimer, void *pvUser)
1691{
1692 APICDeviceInfo *pDev = PDMINS_2_DATA(pDevIns, APICDeviceInfo *);
1693 APICState *pApic = (APICState *)pvUser;
1694 Assert(pApic->pTimerR3 == pTimer);
1695 Assert(pApic->fTimerArmed);
1696 Assert(PDMCritSectIsOwner(pDev->pCritSectR3));
1697 Assert(TMTimerIsLockOwner(pTimer));
1698
1699 if (!(pApic->lvt[APIC_LVT_TIMER] & APIC_LVT_MASKED)) {
1700 LogFlow(("apic_timer: trigger irq\n"));
1701 apic_set_irq(pDev, pApic, pApic->lvt[APIC_LVT_TIMER] & 0xff, APIC_TRIGGER_EDGE,
1702 pDev->CTX_SUFF(pApicHlp)->pfnCalcIrqTag(pDevIns, PDM_IRQ_LEVEL_HIGH));
1703
1704 if ( (pApic->lvt[APIC_LVT_TIMER] & APIC_LVT_TIMER_PERIODIC)
1705 && pApic->initial_count > 0) {
1706 /* new interval. */
1707 pApic->next_time += (((uint64_t)pApic->initial_count + 1) << pApic->count_shift);
1708 TMTimerSet(pApic->CTX_SUFF(pTimer), pApic->next_time);
1709 pApic->fTimerArmed = true;
1710 apicDoFrequencyHinting(pApic);
1711 Log2(("apicR3TimerCallback: ic=%#x sh=%#x nxt=%#llx\n", pApic->initial_count, pApic->count_shift, pApic->next_time));
1712 } else {
1713 /* single shot or disabled. */
1714 pApic->fTimerArmed = false;
1715 pApic->uHintedCountShift = pApic->uHintedInitialCount = 0;
1716 }
1717 } else {
1718 /* masked, do not rearm. */
1719 pApic->fTimerArmed = false;
1720 pApic->uHintedCountShift = pApic->uHintedInitialCount = 0;
1721 }
1722}
1723
1724static void apic_save(SSMHANDLE* f, void *opaque)
1725{
1726 APICState *s = (APICState*)opaque;
1727 int i;
1728
1729 SSMR3PutU32(f, s->apicbase);
1730 SSMR3PutU32(f, s->id);
1731 SSMR3PutU32(f, s->phys_id);
1732 SSMR3PutU32(f, s->arb_id);
1733 SSMR3PutU32(f, s->tpr);
1734 SSMR3PutU32(f, s->spurious_vec);
1735 SSMR3PutU8(f, s->log_dest);
1736 SSMR3PutU8(f, s->dest_mode);
1737 for (i = 0; i < 8; i++) {
1738 SSMR3PutU32(f, s->isr.au32Bitmap[i]);
1739 SSMR3PutU32(f, s->tmr.au32Bitmap[i]);
1740 SSMR3PutU32(f, s->irr.au32Bitmap[i]);
1741 }
1742 for (i = 0; i < APIC_LVT_NB; i++) {
1743 SSMR3PutU32(f, s->lvt[i]);
1744 }
1745 SSMR3PutU32(f, s->esr);
1746 SSMR3PutU32(f, s->icr[0]);
1747 SSMR3PutU32(f, s->icr[1]);
1748 SSMR3PutU32(f, s->divide_conf);
1749 SSMR3PutU32(f, s->count_shift);
1750 SSMR3PutU32(f, s->initial_count);
1751 SSMR3PutU64(f, s->initial_count_load_time);
1752 SSMR3PutU64(f, s->next_time);
1753
1754 TMR3TimerSave(s->CTX_SUFF(pTimer), f);
1755}
1756
1757static int apic_load(SSMHANDLE *f, void *opaque, int version_id)
1758{
1759 APICState *s = (APICState*)opaque;
1760 int i;
1761
1762 /** @todo XXX: what if the base changes? (registered memory regions) */
1763 SSMR3GetU32(f, &s->apicbase);
1764
1765 switch (version_id)
1766 {
1767 case APIC_SAVED_STATE_VERSION_ANCIENT:
1768 {
1769 uint8_t val = 0;
1770 SSMR3GetU8(f, &val);
1771 s->id = val;
1772 /* UP only in old saved states */
1773 s->phys_id = 0;
1774 SSMR3GetU8(f, &val);
1775 s->arb_id = val;
1776 break;
1777 }
1778 case APIC_SAVED_STATE_VERSION:
1779 case APIC_SAVED_STATE_VERSION_VBOX_30:
1780 SSMR3GetU32(f, &s->id);
1781 SSMR3GetU32(f, &s->phys_id);
1782 SSMR3GetU32(f, &s->arb_id);
1783 break;
1784 default:
1785 return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
1786 }
1787 SSMR3GetU32(f, &s->tpr);
1788 SSMR3GetU32(f, &s->spurious_vec);
1789 SSMR3GetU8(f, &s->log_dest);
1790 SSMR3GetU8(f, &s->dest_mode);
1791 for (i = 0; i < 8; i++) {
1792 SSMR3GetU32(f, &s->isr.au32Bitmap[i]);
1793 SSMR3GetU32(f, &s->tmr.au32Bitmap[i]);
1794 SSMR3GetU32(f, &s->irr.au32Bitmap[i]);
1795 }
1796 for (i = 0; i < APIC_LVT_NB; i++) {
1797 SSMR3GetU32(f, &s->lvt[i]);
1798 }
1799 SSMR3GetU32(f, &s->esr);
1800 SSMR3GetU32(f, &s->icr[0]);
1801 SSMR3GetU32(f, &s->icr[1]);
1802 SSMR3GetU32(f, &s->divide_conf);
1803 SSMR3GetU32(f, (uint32_t *)&s->count_shift);
1804 SSMR3GetU32(f, (uint32_t *)&s->initial_count);
1805 SSMR3GetU64(f, (uint64_t *)&s->initial_count_load_time);
1806 SSMR3GetU64(f, (uint64_t *)&s->next_time);
1807
1808 int rc = TMR3TimerLoad(s->CTX_SUFF(pTimer), f);
1809 AssertRCReturn(rc, rc);
1810 s->uHintedCountShift = s->uHintedInitialCount = 0;
1811 s->fTimerArmed = TMTimerIsActive(s->CTX_SUFF(pTimer));
1812 if (s->fTimerArmed)
1813 apicDoFrequencyHinting(s);
1814
1815 return VINF_SUCCESS; /** @todo darn mess! */
1816}
1817
1818#endif /* IN_RING3 */
1819
1820/* LAPIC */
1821PDMBOTHCBDECL(int) apicMMIORead(PPDMDEVINS pDevIns, void *pvUser, RTGCPHYS GCPhysAddr, void *pv, unsigned cb)
1822{
1823 APICDeviceInfo *pDev = PDMINS_2_DATA(pDevIns, APICDeviceInfo *);
1824 APICState *s = getLapic(pDev);
1825
1826 Log(("CPU%d: apicMMIORead at %llx\n", s->phys_id, (uint64_t)GCPhysAddr));
1827
1828 /** @todo add LAPIC range validity checks (different LAPICs can
1829 * theoretically have different physical addresses, see @bugref{3092}) */
1830
1831 STAM_COUNTER_INC(&CTXSUFF(pDev->StatMMIORead));
1832 switch (cb)
1833 {
1834 case 1:
1835 /** @todo this is not how recent APIC behave! We will fix
1836 * this via the IOM. */
1837 *(uint8_t *)pv = 0;
1838 break;
1839
1840 case 2:
1841 /** @todo this is not how recent APIC behave! */
1842 *(uint16_t *)pv = 0;
1843 break;
1844
1845 case 4:
1846 {
1847#if 0 /** @note experimental */
1848#ifndef IN_RING3
1849 uint32_t index = (GCPhysAddr >> 4) & 0xff;
1850
1851 if ( index == 0x08 /* TPR */
1852 && ++s->cTPRPatchAttempts < APIC_MAX_PATCH_ATTEMPTS)
1853 {
1854#ifdef IN_RC
1855 pDevIns->pDevHlpGC->pfnPATMSetMMIOPatchInfo(pDevIns, GCPhysAddr, &s->tpr);
1856#else
1857 RTGCPTR pDevInsGC = PDMINS2DATA_GCPTR(pDevIns);
1858 pDevIns->pHlpR0->pfnPATMSetMMIOPatchInfo(pDevIns, GCPhysAddr, pDevIns + RT_OFFSETOF(APICState, tpr));
1859#endif
1860 return VINF_PATM_HC_MMIO_PATCH_READ;
1861 }
1862#endif
1863#endif /* experimental */
1864
1865 /* It does its own locking. */
1866 uint64_t u64Value = 0;
1867 int rc = apicReadRegister(pDev, s, (GCPhysAddr >> 4) & 0xff, &u64Value,
1868 VINF_IOM_R3_MMIO_READ, false /*fMsr*/);
1869 *(uint32_t *)pv = (uint32_t)u64Value;
1870 return rc;
1871 }
1872
1873 default:
1874 AssertReleaseMsgFailed(("cb=%d\n", cb)); /* for now we assume simple accesses. */
1875 return VERR_INTERNAL_ERROR;
1876 }
1877 return VINF_SUCCESS;
1878}
1879
1880PDMBOTHCBDECL(int) apicMMIOWrite(PPDMDEVINS pDevIns, void *pvUser, RTGCPHYS GCPhysAddr, void const *pv, unsigned cb)
1881{
1882 APICDeviceInfo *pDev = PDMINS_2_DATA(pDevIns, APICDeviceInfo *);
1883 APICState *s = getLapic(pDev);
1884
1885 Log(("CPU%d: apicMMIOWrite at %llx\n", s->phys_id, (uint64_t)GCPhysAddr));
1886
1887 /** @todo: add LAPIC range validity checks (multiple LAPICs can theoretically have
1888 * different physical addresses, see @bugref{3092}) */
1889
1890 STAM_COUNTER_INC(&CTXSUFF(pDev->StatMMIOWrite));
1891 switch (cb)
1892 {
1893 case 1:
1894 case 2:
1895 /* ignore */
1896 break;
1897
1898 case 4:
1899 /* It does its own locking. */
1900 return apicWriteRegister(pDev, s, (GCPhysAddr >> 4) & 0xff, *(uint32_t const *)pv,
1901 VINF_IOM_R3_MMIO_WRITE, false /*fMsr*/);
1902
1903 default:
1904 AssertReleaseMsgFailed(("cb=%d\n", cb)); /* for now we assume simple accesses. */
1905 return VERR_INTERNAL_ERROR;
1906 }
1907 return VINF_SUCCESS;
1908}
1909
1910#ifdef IN_RING3
1911
1912/**
1913 * Wrapper around apicReadRegister.
1914 *
1915 * @returns 64-bit register value.
1916 * @param pDev The PDM device instance.
1917 * @param pApic The Local APIC in question.
1918 * @param iReg The APIC register index.
1919 */
1920static uint64_t apicR3InfoReadReg(APICDeviceInfo *pDev, APICState *pApic, uint32_t iReg)
1921{
1922 uint64_t u64Value;
1923 int rc = apicReadRegister(pDev, pApic, iReg, &u64Value, VINF_SUCCESS, true /*fMsr*/);
1924 AssertRCReturn(rc, UINT64_MAX);
1925 return u64Value;
1926}
1927
1928
1929/**
1930 * Print a 8-DWORD Local APIC bit map (256 bits).
1931 *
1932 * @param pDev The PDM device instance.
1933 * @param pApic The Local APIC in question.
1934 * @param pHlp The output helper.
1935 * @param iStartReg The register to start at.
1936 */
1937static void apicR3DumpVec(APICDeviceInfo *pDev, APICState *pApic, PCDBGFINFOHLP pHlp, uint32_t iStartReg)
1938{
1939 for (uint32_t i = 0; i < 8; i++)
1940 pHlp->pfnPrintf(pHlp, "%08x", apicR3InfoReadReg(pDev, pApic, iStartReg + i));
1941 pHlp->pfnPrintf(pHlp, "\n");
1942}
1943
1944/**
1945 * Print basic Local APIC state.
1946 *
1947 * @param pDev The PDM device instance.
1948 * @param pApic The Local APIC in question.
1949 * @param pHlp The output helper.
1950 */
1951static void apicR3InfoBasic(APICDeviceInfo *pDev, APICState *pApic, PCDBGFINFOHLP pHlp)
1952{
1953 uint64_t u64;
1954
1955 pHlp->pfnPrintf(pHlp, "Local APIC at %08llx:\n", pApic->apicbase);
1956 u64 = apicR3InfoReadReg(pDev, pApic, 0x2);
1957 pHlp->pfnPrintf(pHlp, " LAPIC ID : %08llx\n", u64);
1958 pHlp->pfnPrintf(pHlp, " APIC ID = %02llx\n", (u64 >> 24) & 0xff);
1959 u64 = apicR3InfoReadReg(pDev, pApic, 0x3);
1960 pHlp->pfnPrintf(pHlp, " APIC VER : %08llx\n", u64);
1961 pHlp->pfnPrintf(pHlp, " version = %02x\n", (int)RT_BYTE1(u64));
1962 pHlp->pfnPrintf(pHlp, " lvts = %d\n", (int)RT_BYTE3(u64) + 1);
1963 u64 = apicR3InfoReadReg(pDev, pApic, 0x8);
1964 pHlp->pfnPrintf(pHlp, " TPR : %08llx\n", u64);
1965 pHlp->pfnPrintf(pHlp, " task pri = %lld/%lld\n", (u64 >> 4) & 0xf, u64 & 0xf);
1966 u64 = apicR3InfoReadReg(pDev, pApic, 0xA);
1967 pHlp->pfnPrintf(pHlp, " PPR : %08llx\n", u64);
1968 pHlp->pfnPrintf(pHlp, " cpu pri = %lld/%lld\n", (u64 >> 4) & 0xf, u64 & 0xf);
1969 u64 = apicR3InfoReadReg(pDev, pApic, 0xD);
1970 pHlp->pfnPrintf(pHlp, " LDR : %08llx\n", u64);
1971 pHlp->pfnPrintf(pHlp, " log id = %02llx\n", (u64 >> 24) & 0xff);
1972 pHlp->pfnPrintf(pHlp, " DFR : %08llx\n", apicR3InfoReadReg(pDev, pApic, 0xE));
1973 u64 = apicR3InfoReadReg(pDev, pApic, 0xF);
1974 pHlp->pfnPrintf(pHlp, " SVR : %08llx\n", u64);
1975 pHlp->pfnPrintf(pHlp, " focus = %s\n", u64 & RT_BIT(9) ? "check off" : "check on");
1976 pHlp->pfnPrintf(pHlp, " lapic = %s\n", u64 & RT_BIT(8) ? "ENABLED" : "DISABLED");
1977 pHlp->pfnPrintf(pHlp, " vector = %02x\n", (unsigned)RT_BYTE1(u64));
1978 pHlp->pfnPrintf(pHlp, " ISR : ");
1979 apicR3DumpVec(pDev, pApic, pHlp, 0x10);
1980 int iMax = Apic256BitReg_FindLastSetBit(&pApic->isr, -1);
1981 pHlp->pfnPrintf(pHlp, " highest = %02x\n", iMax == -1 ? 0 : iMax);
1982 pHlp->pfnPrintf(pHlp, " IRR : ");
1983 apicR3DumpVec(pDev, pApic, pHlp, 0x20);
1984 iMax = Apic256BitReg_FindLastSetBit(&pApic->irr, -1);
1985 pHlp->pfnPrintf(pHlp, " highest = %02X\n", iMax == -1 ? 0 : iMax);
1986}
1987
1988
1989/**
1990 * Print the more interesting Local APIC LVT entries.
1991 *
1992 * @param pDev The PDM device instance.
1993 * @param pApic The Local APIC in question.
1994 * @param pHlp The output helper.
1995 */
1996static void apicR3InfoLVT(APICDeviceInfo *pDev, APICState *pApic, PCDBGFINFOHLP pHlp)
1997{
1998 static const char * const s_apszDeliveryModes[] =
1999 {
2000 "Fixed ", "Reserved", "SMI", "Reserved", "NMI", "INIT", "Reserved", "ExtINT"
2001 };
2002 uint64_t u64;
2003
2004 u64 = apicR3InfoReadReg(pDev, pApic, 0x32);
2005 pHlp->pfnPrintf(pHlp, " LVT Timer : %08llx\n", u64);
2006 pHlp->pfnPrintf(pHlp, " mode = %s\n", u64 & RT_BIT(17) ? "periodic" : "one-shot");
2007 pHlp->pfnPrintf(pHlp, " mask = %llu\n", (u64 >> 16) & 1);
2008 pHlp->pfnPrintf(pHlp, " status = %s\n", u64 & RT_BIT(12) ? "pending" : "idle");
2009 pHlp->pfnPrintf(pHlp, " vector = %02llx\n", u64 & 0xff);
2010 u64 = apicR3InfoReadReg(pDev, pApic, 0x35);
2011 pHlp->pfnPrintf(pHlp, " LVT LINT0 : %08llx\n", u64);
2012 pHlp->pfnPrintf(pHlp, " mask = %llu\n", (u64 >> 16) & 1);
2013 pHlp->pfnPrintf(pHlp, " trigger = %s\n", u64 & RT_BIT(15) ? "level" : "edge");
2014 pHlp->pfnPrintf(pHlp, " rem irr = %llu\n", (u64 >> 14) & 1);
2015 pHlp->pfnPrintf(pHlp, " polarty = %llu\n", (u64 >> 13) & 1);
2016 pHlp->pfnPrintf(pHlp, " status = %s\n", u64 & RT_BIT(12) ? "pending" : "idle");
2017 pHlp->pfnPrintf(pHlp, " delivry = %s\n", s_apszDeliveryModes[(u64 >> 8) & 7]);
2018 pHlp->pfnPrintf(pHlp, " vector = %02llx\n", u64 & 0xff);
2019 u64 = apicR3InfoReadReg(pDev, pApic, 0x36);
2020 pHlp->pfnPrintf(pHlp, " LVT LINT1 : %08llx\n", u64);
2021 pHlp->pfnPrintf(pHlp, " mask = %llu\n", (u64 >> 16) & 1);
2022 pHlp->pfnPrintf(pHlp, " trigger = %s\n", u64 & RT_BIT(15) ? "level" : "edge");
2023 pHlp->pfnPrintf(pHlp, " rem irr = %lld\n", (u64 >> 14) & 1);
2024 pHlp->pfnPrintf(pHlp, " polarty = %lld\n", (u64 >> 13) & 1);
2025 pHlp->pfnPrintf(pHlp, " status = %s\n", u64 & RT_BIT(12) ? "pending" : "idle");
2026 pHlp->pfnPrintf(pHlp, " delivry = %s\n", s_apszDeliveryModes[(u64 >> 8) & 7]);
2027 pHlp->pfnPrintf(pHlp, " vector = %02llx\n", u64 & 0xff);
2028}
2029
2030
2031/**
2032 * Print LAPIC timer state.
2033 *
2034 * @param pDev The PDM device instance.
2035 * @param pApic The Local APIC in question.
2036 * @param pHlp The output helper.
2037 */
2038static void apicR3InfoTimer(APICDeviceInfo *pDev, APICState *pApic, PCDBGFINFOHLP pHlp)
2039{
2040 pHlp->pfnPrintf(pHlp, "Local APIC timer:\n");
2041 pHlp->pfnPrintf(pHlp, " Initial count : %08llx\n", apicR3InfoReadReg(pDev, pApic, 0x38));
2042 pHlp->pfnPrintf(pHlp, " Current count : %08llx\n", apicR3InfoReadReg(pDev, pApic, 0x39));
2043 uint64_t u64 = apicR3InfoReadReg(pDev, pApic, 0x3e);
2044 pHlp->pfnPrintf(pHlp, " Divide config : %08llx\n", u64);
2045 unsigned uDivider = ((u64 >> 1) & 0x04) | (u64 & 0x03);
2046 pHlp->pfnPrintf(pHlp, " divider = %u\n", uDivider == 7 ? 1 : 2 << uDivider);
2047}
2048
2049
2050/**
2051 * @callback_method_impl{FNDBGFHANDLERDEV,
2052 * Dumps the Local APIC state according to given argument.}
2053 */
2054static DECLCALLBACK(void) apicR3Info(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
2055{
2056 APICDeviceInfo *pDev = PDMINS_2_DATA(pDevIns, APICDeviceInfo *);
2057 APICState *pApic = getLapic(pDev);
2058
2059 if (pszArgs == NULL || !strcmp(pszArgs, "basic"))
2060 apicR3InfoBasic(pDev, pApic, pHlp);
2061 else if (!strcmp(pszArgs, "lvt"))
2062 apicR3InfoLVT(pDev, pApic, pHlp);
2063 else if (!strcmp(pszArgs, "timer"))
2064 apicR3InfoTimer(pDev, pApic, pHlp);
2065 else
2066 pHlp->pfnPrintf(pHlp, "Invalid argument. Recognized arguments are 'basic', 'lvt', 'timer'.\n");
2067}
2068
2069
2070/**
2071 * @copydoc FNSSMDEVLIVEEXEC
2072 */
2073static DECLCALLBACK(int) apicR3LiveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t uPass)
2074{
2075 APICDeviceInfo *pDev = PDMINS_2_DATA(pDevIns, APICDeviceInfo *);
2076
2077 SSMR3PutU32( pSSM, pDev->cCpus);
2078 SSMR3PutBool(pSSM, pDev->fIoApic);
2079 SSMR3PutU32( pSSM, pDev->enmVersion);
2080 AssertCompile(PDMAPICVERSION_APIC == 2);
2081
2082 return VINF_SSM_DONT_CALL_AGAIN;
2083}
2084
2085
2086/**
2087 * @copydoc FNSSMDEVSAVEEXEC
2088 */
2089static DECLCALLBACK(int) apicR3SaveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
2090{
2091 APICDeviceInfo *pDev = PDMINS_2_DATA(pDevIns, APICDeviceInfo *);
2092
2093 /* config */
2094 apicR3LiveExec(pDevIns, pSSM, SSM_PASS_FINAL);
2095
2096 /* save all APICs data */ /** @todo: is it correct? */
2097 APIC_FOREACH_BEGIN(pDev);
2098 apic_save(pSSM, pCurApic);
2099 APIC_FOREACH_END();
2100
2101 return VINF_SUCCESS;
2102}
2103
2104/**
2105 * @copydoc FNSSMDEVLOADEXEC
2106 */
2107static DECLCALLBACK(int) apicR3LoadExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
2108{
2109 APICDeviceInfo *pDev = PDMINS_2_DATA(pDevIns, APICDeviceInfo *);
2110
2111 if ( uVersion != APIC_SAVED_STATE_VERSION
2112 && uVersion != APIC_SAVED_STATE_VERSION_VBOX_30
2113 && uVersion != APIC_SAVED_STATE_VERSION_ANCIENT)
2114 return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
2115
2116 /* config */
2117 if (uVersion > APIC_SAVED_STATE_VERSION_VBOX_30)
2118 {
2119 uint32_t cCpus;
2120 int rc = SSMR3GetU32(pSSM, &cCpus); AssertRCReturn(rc, rc);
2121 if (cCpus != pDev->cCpus)
2122 return SSMR3SetCfgError(pSSM, RT_SRC_POS, N_("Config mismatch - cCpus: saved=%#x config=%#x"), cCpus, pDev->cCpus);
2123
2124 bool fIoApic;
2125 rc = SSMR3GetBool(pSSM, &fIoApic); AssertRCReturn(rc, rc);
2126 if (fIoApic != pDev->fIoApic)
2127 return SSMR3SetCfgError(pSSM, RT_SRC_POS, N_("Config mismatch - fIoApic: saved=%RTbool config=%RTbool"), fIoApic, pDev->fIoApic);
2128
2129 uint32_t uApicVersion;
2130 rc = SSMR3GetU32(pSSM, &uApicVersion); AssertRCReturn(rc, rc);
2131 if (uApicVersion != (uint32_t)pDev->enmVersion)
2132 return SSMR3SetCfgError(pSSM, RT_SRC_POS, N_("Config mismatch - uApicVersion: saved=%#x config=%#x"), uApicVersion, pDev->enmVersion);
2133 }
2134
2135 if (uPass != SSM_PASS_FINAL)
2136 return VINF_SUCCESS;
2137
2138 /* load all APICs data */ /** @todo: is it correct? */
2139 APIC_LOCK(pDev, VERR_INTERNAL_ERROR_3);
2140
2141 int rc = VINF_SUCCESS;
2142 APIC_FOREACH_BEGIN(pDev);
2143 rc = apic_load(pSSM, pCurApic, uVersion);
2144 if (RT_FAILURE(rc))
2145 break;
2146 APIC_FOREACH_END();
2147
2148 APIC_UNLOCK(pDev);
2149 return rc;
2150}
2151
2152/**
2153 * @copydoc FNPDMDEVRESET
2154 */
2155static DECLCALLBACK(void) apicR3Reset(PPDMDEVINS pDevIns)
2156{
2157 APICDeviceInfo *pDev = PDMINS_2_DATA(pDevIns, APICDeviceInfo *);
2158 TMTimerLock(pDev->paLapicsR3[0].pTimerR3, VERR_IGNORED);
2159 APIC_LOCK_VOID(pDev, VERR_IGNORED);
2160
2161 /* Reset all APICs. */
2162 for (VMCPUID i = 0; i < pDev->cCpus; i++)
2163 {
2164 APICState *pApic = &pDev->CTX_SUFF(paLapics)[i];
2165 TMTimerStop(pApic->CTX_SUFF(pTimer));
2166
2167 /* Clear LAPIC state as if an INIT IPI was sent. */
2168 apic_init_ipi(pDev, pApic);
2169
2170 /* The IDs are not touched by apic_init_ipi() and must be reset now. */
2171 pApic->arb_id = pApic->id = i;
2172 Assert(pApic->id == pApic->phys_id); /* The two should match again. */
2173
2174 /* Reset should re-enable the APIC, see comment in msi.h */
2175 pApic->apicbase = VBOX_MSI_ADDR_BASE | MSR_IA32_APICBASE_ENABLE;
2176 if (pApic->phys_id == 0)
2177 pApic->apicbase |= MSR_IA32_APICBASE_BSP;
2178
2179 /* Clear any pending APIC interrupt action flag. */
2180 cpuClearInterrupt(pDev, pApic);
2181 }
2182 /** @todo r=bird: Why is this done everytime, while the constructor first
2183 * checks the CPUID? Who is right? */
2184 pDev->pApicHlpR3->pfnChangeFeature(pDev->pDevInsR3, pDev->enmVersion);
2185
2186 APIC_UNLOCK(pDev);
2187 TMTimerUnlock(pDev->paLapicsR3[0].pTimerR3);
2188}
2189
2190
2191/**
2192 * @copydoc FNPDMDEVRELOCATE
2193 */
2194static DECLCALLBACK(void) apicR3Relocate(PPDMDEVINS pDevIns, RTGCINTPTR offDelta)
2195{
2196 APICDeviceInfo *pDev = PDMINS_2_DATA(pDevIns, APICDeviceInfo *);
2197 pDev->pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
2198 pDev->pApicHlpRC = pDev->pApicHlpR3->pfnGetRCHelpers(pDevIns);
2199 pDev->paLapicsRC = MMHyperR3ToRC(PDMDevHlpGetVM(pDevIns), pDev->paLapicsR3);
2200 pDev->pCritSectRC = pDev->pApicHlpR3->pfnGetRCCritSect(pDevIns);
2201 for (uint32_t i = 0; i < pDev->cCpus; i++)
2202 pDev->paLapicsR3[i].pTimerRC = TMTimerRCPtr(pDev->paLapicsR3[i].pTimerR3);
2203}
2204
2205
2206/**
2207 * Initializes the state of one local APIC.
2208 *
2209 * @param pApic The Local APIC state to init.
2210 * @param id The Local APIC ID.
2211 */
2212DECLINLINE(void) initApicData(APICState *pApic, uint8_t id)
2213{
2214 memset(pApic, 0, sizeof(*pApic));
2215
2216 /* See comment in msi.h for LAPIC base info. */
2217 pApic->apicbase = VBOX_MSI_ADDR_BASE | MSR_IA32_APICBASE_ENABLE;
2218 if (id == 0) /* Mark first CPU as BSP. */
2219 pApic->apicbase |= MSR_IA32_APICBASE_BSP;
2220
2221 for (int i = 0; i < APIC_LVT_NB; i++)
2222 pApic->lvt[i] = RT_BIT_32(16); /* mask LVT */
2223
2224 pApic->spurious_vec = 0xff;
2225 pApic->phys_id = id;
2226 pApic->id = id;
2227}
2228
2229
2230/**
2231 * @copydoc FNPDMDEVCONSTRUCT
2232 */
2233static DECLCALLBACK(int) apicR3Construct(PPDMDEVINS pDevIns, int iInstance, PCFGMNODE pCfg)
2234{
2235 APICDeviceInfo *pDev = PDMINS_2_DATA(pDevIns, APICDeviceInfo *);
2236 uint32_t i;
2237
2238 /*
2239 * Only single device instance.
2240 */
2241 Assert(iInstance == 0);
2242
2243 /*
2244 * Validate configuration.
2245 */
2246 PDMDEV_VALIDATE_CONFIG_RETURN(pDevIns, "IOAPIC|RZEnabled|NumCPUs", "");
2247
2248 bool fIoApic;
2249 int rc = CFGMR3QueryBoolDef(pCfg, "IOAPIC", &fIoApic, true);
2250 if (RT_FAILURE(rc))
2251 return PDMDEV_SET_ERROR(pDevIns, rc,
2252 N_("Configuration error: Failed to read \"IOAPIC\""));
2253
2254 bool fRZEnabled;
2255 rc = CFGMR3QueryBoolDef(pCfg, "RZEnabled", &fRZEnabled, true);
2256 if (RT_FAILURE(rc))
2257 return PDMDEV_SET_ERROR(pDevIns, rc,
2258 N_("Configuration error: Failed to query boolean value \"RZEnabled\""));
2259
2260 uint32_t cCpus;
2261 rc = CFGMR3QueryU32Def(pCfg, "NumCPUs", &cCpus, 1);
2262 if (RT_FAILURE(rc))
2263 return PDMDEV_SET_ERROR(pDevIns, rc,
2264 N_("Configuration error: Failed to query integer value \"NumCPUs\""));
2265
2266 Log(("APIC: cCpus=%d fRZEnabled=%RTbool fIoApic=%RTbool\n", cCpus, fRZEnabled, fIoApic));
2267 if (cCpus > 255)
2268 return PDMDEV_SET_ERROR(pDevIns, rc,
2269 N_("Configuration error: Invalid value for \"NumCPUs\""));
2270
2271 /*
2272 * Init the data.
2273 */
2274 pDev->pDevInsR3 = pDevIns;
2275 pDev->pDevInsR0 = PDMDEVINS_2_R0PTR(pDevIns);
2276 pDev->pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
2277 pDev->cCpus = cCpus;
2278 pDev->fIoApic = fIoApic;
2279 /* Use PDMAPICVERSION_X2APIC to activate x2APIC mode */
2280 pDev->enmVersion = PDMAPICVERSION_APIC;
2281
2282 /* Disable locking in this device. */
2283 rc = PDMDevHlpSetDeviceCritSect(pDevIns, PDMDevHlpCritSectGetNop(pDevIns));
2284 AssertRCReturn(rc, rc);
2285
2286 PVM pVM = PDMDevHlpGetVM(pDevIns);
2287
2288 /*
2289 * We are not freeing this memory, as it's automatically released when guest exits.
2290 */
2291 rc = MMHyperAlloc(pVM, cCpus * sizeof(APICState), 1, MM_TAG_PDM_DEVICE_USER, (void **)&pDev->paLapicsR3);
2292 if (RT_FAILURE(rc))
2293 return VERR_NO_MEMORY;
2294 pDev->paLapicsR0 = MMHyperR3ToR0(pVM, pDev->paLapicsR3);
2295 pDev->paLapicsRC = MMHyperR3ToRC(pVM, pDev->paLapicsR3);
2296
2297 for (i = 0; i < cCpus; i++)
2298 initApicData(&pDev->paLapicsR3[i], i);
2299
2300 /*
2301 * Register the APIC.
2302 */
2303 PDMAPICREG ApicReg;
2304 ApicReg.u32Version = PDM_APICREG_VERSION;
2305 ApicReg.pfnGetInterruptR3 = apicGetInterrupt;
2306 ApicReg.pfnHasPendingIrqR3 = apicHasPendingIrq;
2307 ApicReg.pfnSetBaseR3 = apicSetBase;
2308 ApicReg.pfnGetBaseR3 = apicGetBase;
2309 ApicReg.pfnSetTPRR3 = apicSetTPR;
2310 ApicReg.pfnGetTPRR3 = apicGetTPR;
2311 ApicReg.pfnWriteMSRR3 = apicWriteMSR;
2312 ApicReg.pfnReadMSRR3 = apicReadMSR;
2313 ApicReg.pfnBusDeliverR3 = apicBusDeliverCallback;
2314 ApicReg.pfnLocalInterruptR3 = apicLocalInterrupt;
2315 if (fRZEnabled)
2316 {
2317 ApicReg.pszGetInterruptRC = "apicGetInterrupt";
2318 ApicReg.pszHasPendingIrqRC = "apicHasPendingIrq";
2319 ApicReg.pszSetBaseRC = "apicSetBase";
2320 ApicReg.pszGetBaseRC = "apicGetBase";
2321 ApicReg.pszSetTPRRC = "apicSetTPR";
2322 ApicReg.pszGetTPRRC = "apicGetTPR";
2323 ApicReg.pszWriteMSRRC = "apicWriteMSR";
2324 ApicReg.pszReadMSRRC = "apicReadMSR";
2325 ApicReg.pszBusDeliverRC = "apicBusDeliverCallback";
2326 ApicReg.pszLocalInterruptRC = "apicLocalInterrupt";
2327
2328 ApicReg.pszGetInterruptR0 = "apicGetInterrupt";
2329 ApicReg.pszHasPendingIrqR0 = "apicHasPendingIrq";
2330 ApicReg.pszSetBaseR0 = "apicSetBase";
2331 ApicReg.pszGetBaseR0 = "apicGetBase";
2332 ApicReg.pszSetTPRR0 = "apicSetTPR";
2333 ApicReg.pszGetTPRR0 = "apicGetTPR";
2334 ApicReg.pszWriteMSRR0 = "apicWriteMSR";
2335 ApicReg.pszReadMSRR0 = "apicReadMSR";
2336 ApicReg.pszBusDeliverR0 = "apicBusDeliverCallback";
2337 ApicReg.pszLocalInterruptR0 = "apicLocalInterrupt";
2338 }
2339 else
2340 {
2341 ApicReg.pszGetInterruptRC = NULL;
2342 ApicReg.pszHasPendingIrqRC = NULL;
2343 ApicReg.pszSetBaseRC = NULL;
2344 ApicReg.pszGetBaseRC = NULL;
2345 ApicReg.pszSetTPRRC = NULL;
2346 ApicReg.pszGetTPRRC = NULL;
2347 ApicReg.pszWriteMSRRC = NULL;
2348 ApicReg.pszReadMSRRC = NULL;
2349 ApicReg.pszBusDeliverRC = NULL;
2350 ApicReg.pszLocalInterruptRC = NULL;
2351
2352 ApicReg.pszGetInterruptR0 = NULL;
2353 ApicReg.pszHasPendingIrqR0 = NULL;
2354 ApicReg.pszSetBaseR0 = NULL;
2355 ApicReg.pszGetBaseR0 = NULL;
2356 ApicReg.pszSetTPRR0 = NULL;
2357 ApicReg.pszGetTPRR0 = NULL;
2358 ApicReg.pszWriteMSRR0 = NULL;
2359 ApicReg.pszReadMSRR0 = NULL;
2360 ApicReg.pszBusDeliverR0 = NULL;
2361 ApicReg.pszLocalInterruptR0 = NULL;
2362 }
2363
2364 rc = PDMDevHlpAPICRegister(pDevIns, &ApicReg, &pDev->pApicHlpR3);
2365 AssertLogRelRCReturn(rc, rc);
2366 pDev->pCritSectR3 = pDev->pApicHlpR3->pfnGetR3CritSect(pDevIns);
2367
2368 /*
2369 * The CPUID feature bit.
2370 */
2371 /** @todo r=bird: See remark in the apicR3Reset. */
2372 uint32_t u32Eax, u32Ebx, u32Ecx, u32Edx;
2373 PDMDevHlpGetCpuId(pDevIns, 0, &u32Eax, &u32Ebx, &u32Ecx, &u32Edx);
2374 if (u32Eax >= 1)
2375 {
2376 if ( fIoApic /* If IOAPIC is enabled, enable Local APIC in any case */
2377 || ( u32Ebx == X86_CPUID_VENDOR_INTEL_EBX
2378 && u32Ecx == X86_CPUID_VENDOR_INTEL_ECX
2379 && u32Edx == X86_CPUID_VENDOR_INTEL_EDX /* GenuineIntel */)
2380 || ( u32Ebx == X86_CPUID_VENDOR_AMD_EBX
2381 && u32Ecx == X86_CPUID_VENDOR_AMD_ECX
2382 && u32Edx == X86_CPUID_VENDOR_AMD_EDX /* AuthenticAMD */))
2383 {
2384 LogRel(("Activating Local APIC\n"));
2385 pDev->pApicHlpR3->pfnChangeFeature(pDevIns, pDev->enmVersion);
2386 }
2387 }
2388
2389 /*
2390 * Register the MMIO range.
2391 */
2392 /** @todo: shall reregister, if base changes. */
2393 uint32_t ApicBase = pDev->paLapicsR3[0].apicbase & ~0xfff;
2394 rc = PDMDevHlpMMIORegister(pDevIns, ApicBase, 0x1000, pDev,
2395 IOMMMIO_FLAGS_READ_PASSTHRU | IOMMMIO_FLAGS_WRITE_PASSTHRU,
2396 apicMMIOWrite, apicMMIORead, "APIC Memory");
2397 if (RT_FAILURE(rc))
2398 return rc;
2399
2400 if (fRZEnabled)
2401 {
2402 pDev->pApicHlpRC = pDev->pApicHlpR3->pfnGetRCHelpers(pDevIns);
2403 pDev->pCritSectRC = pDev->pApicHlpR3->pfnGetRCCritSect(pDevIns);
2404 rc = PDMDevHlpMMIORegisterRC(pDevIns, ApicBase, 0x1000, NIL_RTRCPTR /*pvUser*/, "apicMMIOWrite", "apicMMIORead");
2405 if (RT_FAILURE(rc))
2406 return rc;
2407
2408 pDev->pApicHlpR0 = pDev->pApicHlpR3->pfnGetR0Helpers(pDevIns);
2409 pDev->pCritSectR0 = pDev->pApicHlpR3->pfnGetR0CritSect(pDevIns);
2410 rc = PDMDevHlpMMIORegisterR0(pDevIns, ApicBase, 0x1000, NIL_RTR0PTR /*pvUser*/, "apicMMIOWrite", "apicMMIORead");
2411 if (RT_FAILURE(rc))
2412 return rc;
2413 }
2414
2415 /*
2416 * Create the APIC timers.
2417 */
2418 for (i = 0; i < cCpus; i++)
2419 {
2420 APICState *pApic = &pDev->paLapicsR3[i];
2421 pApic->pszDesc = MMR3HeapAPrintf(pVM, MM_TAG_PDM_DEVICE_USER, "APIC Timer #%u", i);
2422 rc = PDMDevHlpTMTimerCreate(pDevIns, TMCLOCK_VIRTUAL_SYNC, apicR3TimerCallback, pApic,
2423 TMTIMER_FLAGS_NO_CRIT_SECT, pApic->pszDesc, &pApic->pTimerR3);
2424 if (RT_FAILURE(rc))
2425 return rc;
2426 pApic->pTimerR0 = TMTimerR0Ptr(pApic->pTimerR3);
2427 pApic->pTimerRC = TMTimerRCPtr(pApic->pTimerR3);
2428 TMR3TimerSetCritSect(pApic->pTimerR3, pDev->pCritSectR3);
2429 }
2430
2431 /*
2432 * Saved state.
2433 */
2434 rc = PDMDevHlpSSMRegister3(pDevIns, APIC_SAVED_STATE_VERSION, sizeof(*pDev),
2435 apicR3LiveExec, apicR3SaveExec, apicR3LoadExec);
2436 if (RT_FAILURE(rc))
2437 return rc;
2438
2439 /*
2440 * Register debugger info callback.
2441 */
2442 PDMDevHlpDBGFInfoRegister(pDevIns, "apic", "Display Local APIC state for current CPU. "
2443 "Recognizes 'basic', 'lvt', 'timer' as arguments, defaulting to 'basic'.", apicR3Info);
2444
2445#ifdef VBOX_WITH_STATISTICS
2446 /*
2447 * Statistics.
2448 */
2449 PDMDevHlpSTAMRegister(pDevIns, &pDev->StatMMIOReadGC, STAMTYPE_COUNTER, "/Devices/APIC/MMIOReadGC", STAMUNIT_OCCURENCES, "Number of APIC MMIO reads in GC.");
2450 PDMDevHlpSTAMRegister(pDevIns, &pDev->StatMMIOReadHC, STAMTYPE_COUNTER, "/Devices/APIC/MMIOReadHC", STAMUNIT_OCCURENCES, "Number of APIC MMIO reads in HC.");
2451 PDMDevHlpSTAMRegister(pDevIns, &pDev->StatMMIOWriteGC, STAMTYPE_COUNTER, "/Devices/APIC/MMIOWriteGC", STAMUNIT_OCCURENCES, "Number of APIC MMIO writes in GC.");
2452 PDMDevHlpSTAMRegister(pDevIns, &pDev->StatMMIOWriteHC, STAMTYPE_COUNTER, "/Devices/APIC/MMIOWriteHC", STAMUNIT_OCCURENCES, "Number of APIC MMIO writes in HC.");
2453 PDMDevHlpSTAMRegister(pDevIns, &pDev->StatClearedActiveIrq,STAMTYPE_COUNTER, "/Devices/APIC/MaskedActiveIRQ", STAMUNIT_OCCURENCES, "Number of cleared irqs.");
2454 for (i = 0; i < cCpus; i++)
2455 {
2456 APICState *pApic = &pDev->paLapicsR3[i];
2457 PDMDevHlpSTAMRegisterF(pDevIns, &pApic->StatTimerSetInitialCount, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, "Calls to apicTimerSetInitialCount.", "/Devices/APIC/%u/TimerSetInitialCount", i);
2458 PDMDevHlpSTAMRegisterF(pDevIns, &pApic->StatTimerSetInitialCountArm, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, "TMTimerSetRelative calls.", "/Devices/APIC/%u/TimerSetInitialCount/Arm", i);
2459 PDMDevHlpSTAMRegisterF(pDevIns, &pApic->StatTimerSetInitialCountDisarm, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, "TMTimerStop calls.", "/Devices/APIC/%u/TimerSetInitialCount/Disasm", i);
2460 PDMDevHlpSTAMRegisterF(pDevIns, &pApic->StatTimerSetLvt, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, "Calls to apicTimerSetLvt.", "/Devices/APIC/%u/TimerSetLvt", i);
2461 PDMDevHlpSTAMRegisterF(pDevIns, &pApic->StatTimerSetLvtClearPeriodic, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, "Clearing APIC_LVT_TIMER_PERIODIC.", "/Devices/APIC/%u/TimerSetLvt/ClearPeriodic", i);
2462 PDMDevHlpSTAMRegisterF(pDevIns, &pApic->StatTimerSetLvtPostponed, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, "TMTimerStop postponed.", "/Devices/APIC/%u/TimerSetLvt/Postponed", i);
2463 PDMDevHlpSTAMRegisterF(pDevIns, &pApic->StatTimerSetLvtArmed, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, "TMTimerSet avoided.", "/Devices/APIC/%u/TimerSetLvt/Armed", i);
2464 PDMDevHlpSTAMRegisterF(pDevIns, &pApic->StatTimerSetLvtArm, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, "TMTimerSet necessary.", "/Devices/APIC/%u/TimerSetLvt/Arm", i);
2465 PDMDevHlpSTAMRegisterF(pDevIns, &pApic->StatTimerSetLvtArmRetries, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, "TMTimerSet retries.", "/Devices/APIC/%u/TimerSetLvt/ArmRetries", i);
2466 PDMDevHlpSTAMRegisterF(pDevIns, &pApic->StatTimerSetLvtNoRelevantChange,STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, "No relevant flags changed.", "/Devices/APIC/%u/TimerSetLvt/NoRelevantChange", i);
2467 }
2468#endif
2469
2470 return VINF_SUCCESS;
2471}
2472
2473
2474/**
2475 * APIC device registration structure.
2476 */
2477const PDMDEVREG g_DeviceAPIC =
2478{
2479 /* u32Version */
2480 PDM_DEVREG_VERSION,
2481 /* szName */
2482 "apic",
2483 /* szRCMod */
2484 "VBoxDD2GC.gc",
2485 /* szR0Mod */
2486 "VBoxDD2R0.r0",
2487 /* pszDescription */
2488 "Advanced Programmable Interrupt Controller (APIC) Device",
2489 /* fFlags */
2490 PDM_DEVREG_FLAGS_HOST_BITS_DEFAULT | PDM_DEVREG_FLAGS_GUEST_BITS_32_64 | PDM_DEVREG_FLAGS_PAE36 | PDM_DEVREG_FLAGS_RC | PDM_DEVREG_FLAGS_R0,
2491 /* fClass */
2492 PDM_DEVREG_CLASS_PIC,
2493 /* cMaxInstances */
2494 1,
2495 /* cbInstance */
2496 sizeof(APICState),
2497 /* pfnConstruct */
2498 apicR3Construct,
2499 /* pfnDestruct */
2500 NULL,
2501 /* pfnRelocate */
2502 apicR3Relocate,
2503 /* pfnIOCtl */
2504 NULL,
2505 /* pfnPowerOn */
2506 NULL,
2507 /* pfnReset */
2508 apicR3Reset,
2509 /* pfnSuspend */
2510 NULL,
2511 /* pfnResume */
2512 NULL,
2513 /* pfnAttach */
2514 NULL,
2515 /* pfnDetach */
2516 NULL,
2517 /* pfnQueryInterface. */
2518 NULL,
2519 /* pfnInitComplete */
2520 NULL,
2521 /* pfnPowerOff */
2522 NULL,
2523 /* pfnSoftReset */
2524 NULL,
2525 /* u32VersionEnd */
2526 PDM_DEVREG_VERSION
2527};
2528
2529#endif /* IN_RING3 */
2530#endif /* !VBOX_DEVICE_STRUCT_TESTCASE */
2531
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