DevAPIC.cpp@ 37636

Last change on this file since 37636 was 37636, checked in by vboxsync, 13 years ago
Changed FNIOMMMIOWRITE to take a const buffer pointer.
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1	/* $Id: DevAPIC.cpp 37636 2011-06-24 14:59:59Z vboxsync $ */
2	/** @file
3	* Advanced Programmable Interrupt Controller (APIC) Device and
4	* I/O Advanced Programmable Interrupt Controller (IO-APIC) Device.
5	*/
6
7	/*
8	* Copyright (C) 2006-2010 Oracle Corporation
9	*
10	* This file is part of VirtualBox Open Source Edition (OSE), as
11	* available from http://www.virtualbox.org. This file is free software;
12	* you can redistribute it and/or modify it under the terms of the GNU
13	* General Public License (GPL) as published by the Free Software
14	* Foundation, in version 2 as it comes in the "COPYING" file of the
15	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
16	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
17	* --------------------------------------------------------------------
18	*
19	* This code is based on:
20	*
21	* apic.c revision 1.5 @@OSETODO
22	*
23	* APIC support
24	*
25	* Copyright (c) 2004-2005 Fabrice Bellard
26	*
27	* This library is free software; you can redistribute it and/or
28	* modify it under the terms of the GNU Lesser General Public
29	* License as published by the Free Software Foundation; either
30	* version 2 of the License, or (at your option) any later version.
31	*
32	* This library is distributed in the hope that it will be useful,
33	* but WITHOUT ANY WARRANTY; without even the implied warranty of
34	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
35	* Lesser General Public License for more details.
36	*
37	* You should have received a copy of the GNU Lesser General Public
38	* License along with this library; if not, write to the Free Software
39	* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
40	*/
41
42	/*******************************************************************************
43	* Header Files *
44	*******************************************************************************/
45	#define LOG_GROUP LOG_GROUP_DEV_APIC
46	#include <VBox/vmm/pdmdev.h>
47
48	#include <VBox/log.h>
49	#include <VBox/vmm/stam.h>
50	#include <iprt/assert.h>
51	#include <iprt/asm.h>
52
53	#include <VBox/msi.h>
54
55	#include "VBoxDD2.h"
56	#include "DevApic.h"
57
58	/*******************************************************************************
59	* Defined Constants And Macros *
60	*******************************************************************************/
61	#define MSR_IA32_APICBASE 0x1b
62	#define MSR_IA32_APICBASE_BSP (1<<8)
63	#define MSR_IA32_APICBASE_ENABLE (1<<11)
64	#define MSR_IA32_APICBASE_X2ENABLE (1<<10)
65	#define MSR_IA32_APICBASE_BASE (0xfffff<<12)
66
67	#ifdef _MSC_VER
68	# pragma warning(disable:4244)
69	#endif
70
71	/** The current saved state version.*/
72	#define APIC_SAVED_STATE_VERSION 3
73	/** The saved state version used by VirtualBox v3 and earlier.
74	* This does not include the config. */
75	#define APIC_SAVED_STATE_VERSION_VBOX_30 2
76	/** Some ancient version... */
77	#define APIC_SAVED_STATE_VERSION_ANCIENT 1
78
79	/* version 0x14: Pentium 4, Xeon; LVT count depends on that */
80	#define APIC_HW_VERSION 0x14
81
82	/** @def APIC_LOCK
83	* Acquires the PDM lock. */
84	#define APIC_LOCK(a_pDev, rcBusy) \
85	do { \
86	int rc2 = PDMCritSectEnter((a_pDev)->CTX_SUFF(pCritSect), (rcBusy)); \
87	if (rc2 != VINF_SUCCESS) \
88	return rc2; \
89	} while (0)
90
91	/** @def APIC_LOCK_VOID
92	* Acquires the PDM lock and does not expect failure (i.e. ring-3 only!). */
93	#define APIC_LOCK_VOID(a_pDev, rcBusy) \
94	do { \
95	int rc2 = PDMCritSectEnter((a_pDev)->CTX_SUFF(pCritSect), (rcBusy)); \
96	AssertLogRelRCReturnVoid(rc2); \
97	} while (0)
98
99	/** @def APIC_UNLOCK
100	* Releases the PDM lock. */
101	#define APIC_UNLOCK(a_pDev) \
102	PDMCritSectLeave((a_pDev)->CTX_SUFF(pCritSect))
103
104	/** @def APIC_AND_TM_LOCK
105	* Acquires the virtual sync clock lock as well as the PDM lock. */
106	#define APIC_AND_TM_LOCK(a_pDev, a_pAcpi, rcBusy) \
107	do { \
108	int rc2 = TMTimerLock((a_pAcpi)->CTX_SUFF(pTimer), (rcBusy)); \
109	if (rc2 != VINF_SUCCESS) \
110	return rc2; \
111	rc2 = PDMCritSectEnter((a_pDev)->CTX_SUFF(pCritSect), (rcBusy)); \
112	if (rc2 != VINF_SUCCESS) \
113	{ \
114	TMTimerUnlock((a_pAcpi)->CTX_SUFF(pTimer)); \
115	return rc2; \
116	} \
117	} while (0)
118
119	/** @def APIC_AND_TM_UNLOCK
120	* Releases the PDM lock as well as the TM virtual sync clock lock. */
121	#define APIC_AND_TM_UNLOCK(a_pDev, a_pAcpi) \
122	do { \
123	TMTimerUnlock((a_pAcpi)->CTX_SUFF(pTimer)); \
124	PDMCritSectLeave((a_pDev)->CTX_SUFF(pCritSect)); \
125	} while (0)
126
127	#define foreach_apic(pDev, mask, code) \
128	do { \
129	APICState *apic = (pDev)->CTX_SUFF(paLapics); \
130	for (uint32_t i = 0; i < (pDev)->cCpus; i++) \
131	{ \
132	if (mask & (1 << (apic->id))) \
133	{ \
134	code; \
135	} \
136	apic++; \
137	} \
138	} while (0)
139
140	# define set_bit(pvBitmap, iBit) ASMBitSet(pvBitmap, iBit)
141	# define reset_bit(pvBitmap, iBit) ASMBitClear(pvBitmap, iBit)
142	# define fls_bit(value) (ASMBitLastSetU32(value) - 1)
143	# define ffs_bit(value) (ASMBitFirstSetU32(value) - 1)
144
145	#define DEBUG_APIC
146
147	/* APIC Local Vector Table */
148	#define APIC_LVT_TIMER 0
149	#define APIC_LVT_THERMAL 1
150	#define APIC_LVT_PERFORM 2
151	#define APIC_LVT_LINT0 3
152	#define APIC_LVT_LINT1 4
153	#define APIC_LVT_ERROR 5
154	#define APIC_LVT_NB 6
155
156	/* APIC delivery modes */
157	#define APIC_DM_FIXED 0
158	#define APIC_DM_LOWPRI 1
159	#define APIC_DM_SMI 2
160	#define APIC_DM_NMI 4
161	#define APIC_DM_INIT 5
162	#define APIC_DM_SIPI 6
163	#define APIC_DM_EXTINT 7
164
165	/* APIC destination mode */
166	#define APIC_DESTMODE_FLAT 0xf
167	#define APIC_DESTMODE_CLUSTER 0x0
168
169	#define APIC_TRIGGER_EDGE 0
170	#define APIC_TRIGGER_LEVEL 1
171
172	#define APIC_LVT_TIMER_PERIODIC (1<<17)
173	#define APIC_LVT_MASKED (1<<16)
174	#define APIC_LVT_LEVEL_TRIGGER (1<<15)
175	#define APIC_LVT_REMOTE_IRR (1<<14)
176	#define APIC_INPUT_POLARITY (1<<13)
177	#define APIC_SEND_PENDING (1<<12)
178
179	#define ESR_ILLEGAL_ADDRESS (1 << 7)
180
181	#define APIC_SV_ENABLE (1 << 8)
182
183	#define APIC_MAX_PATCH_ATTEMPTS 100
184
185	typedef uint32_t PhysApicId;
186	typedef uint32_t LogApicId;
187
188
189	/*******************************************************************************
190	* Structures and Typedefs *
191	*******************************************************************************/
192	typedef struct APICState {
193	uint32_t apicbase;
194	/* Task priority register (interrupt level) */
195	uint32_t tpr;
196	/* Logical APIC id - user programmable */
197	LogApicId id;
198	/* Physical APIC id - not visible to user, constant */
199	PhysApicId phys_id;
200	/** @todo: is it logical or physical? Not really used anyway now. */
201	PhysApicId arb_id;
202	uint32_t spurious_vec;
203	uint8_t log_dest;
204	uint8_t dest_mode;
205	uint32_t isr[8]; /* in service register */
206	uint32_t tmr[8]; /* trigger mode register */
207	uint32_t irr[8]; /* interrupt request register */
208	uint32_t lvt[APIC_LVT_NB];
209	uint32_t esr; /* error register */
210	uint32_t icr[2];
211	uint32_t divide_conf;
212	int count_shift;
213	uint32_t initial_count;
214	uint32_t Alignment0;
215
216	/** The time stamp of the initial_count load, i.e. when it was started. */
217	uint64_t initial_count_load_time;
218	/** The time stamp of the next timer callback. */
219	uint64_t next_time;
220	/** The APIC timer - R3 Ptr. */
221	PTMTIMERR3 pTimerR3;
222	/** The APIC timer - R0 Ptr. */
223	PTMTIMERR0 pTimerR0;
224	/** The APIC timer - RC Ptr. */
225	PTMTIMERRC pTimerRC;
226	/** Whether the timer is armed or not */
227	bool fTimerArmed;
228	/** Alignment */
229	bool afAlignment[3];
230	/** The initial_count value used for the current frequency hint. */
231	uint32_t uHintedInitialCount;
232	/** The count_shift value used for the current frequency hint. */
233	uint32_t uHintedCountShift;
234	/** Timer description timer. */
235	R3PTRTYPE(char *) pszDesc;
236	# ifdef VBOX_WITH_STATISTICS
237	# if HC_ARCH_BITS == 32
238	uint32_t u32Alignment0;
239	# endif
240	STAMCOUNTER StatTimerSetInitialCount;
241	STAMCOUNTER StatTimerSetInitialCountArm;
242	STAMCOUNTER StatTimerSetInitialCountDisarm;
243	STAMCOUNTER StatTimerSetLvt;
244	STAMCOUNTER StatTimerSetLvtClearPeriodic;
245	STAMCOUNTER StatTimerSetLvtPostponed;
246	STAMCOUNTER StatTimerSetLvtArmed;
247	STAMCOUNTER StatTimerSetLvtArm;
248	STAMCOUNTER StatTimerSetLvtArmRetries;
249	STAMCOUNTER StatTimerSetLvtNoRelevantChange;
250	# endif
251
252	} APICState;
253
254	AssertCompileMemberAlignment(APICState, initial_count_load_time, 8);
255	# ifdef VBOX_WITH_STATISTICS
256	AssertCompileMemberAlignment(APICState, StatTimerSetInitialCount, 8);
257	# endif
258
259	typedef struct
260	{
261	/** The device instance - R3 Ptr. */
262	PPDMDEVINSR3 pDevInsR3;
263	/** The APIC helpers - R3 Ptr. */
264	PCPDMAPICHLPR3 pApicHlpR3;
265	/** LAPICs states - R3 Ptr */
266	R3PTRTYPE(APICState *) paLapicsR3;
267	/** The critical section - R3 Ptr. */
268	R3PTRTYPE(PPDMCRITSECT) pCritSectR3;
269
270	/** The device instance - R0 Ptr. */
271	PPDMDEVINSR0 pDevInsR0;
272	/** The APIC helpers - R0 Ptr. */
273	PCPDMAPICHLPR0 pApicHlpR0;
274	/** LAPICs states - R0 Ptr */
275	R0PTRTYPE(APICState *) paLapicsR0;
276	/** The critical section - R3 Ptr. */
277	R0PTRTYPE(PPDMCRITSECT) pCritSectR0;
278
279	/** The device instance - RC Ptr. */
280	PPDMDEVINSRC pDevInsRC;
281	/** The APIC helpers - RC Ptr. */
282	PCPDMAPICHLPRC pApicHlpRC;
283	/** LAPICs states - RC Ptr */
284	RCPTRTYPE(APICState *) paLapicsRC;
285	/** The critical section - R3 Ptr. */
286	RCPTRTYPE(PPDMCRITSECT) pCritSectRC;
287
288	/** APIC specification version in this virtual hardware configuration. */
289	PDMAPICVERSION enmVersion;
290
291	/** Number of attempts made to optimize TPR accesses. */
292	uint32_t cTPRPatchAttempts;
293
294	/** Number of CPUs on the system (same as LAPIC count). */
295	uint32_t cCpus;
296	/** Whether we've got an IO APIC or not. */
297	bool fIoApic;
298	/** Alignment padding. */
299	bool afPadding[3];
300
301	# ifdef VBOX_WITH_STATISTICS
302	STAMCOUNTER StatMMIOReadGC;
303	STAMCOUNTER StatMMIOReadHC;
304	STAMCOUNTER StatMMIOWriteGC;
305	STAMCOUNTER StatMMIOWriteHC;
306	STAMCOUNTER StatClearedActiveIrq;
307	# endif
308	} APICDeviceInfo;
309	# ifdef VBOX_WITH_STATISTICS
310	AssertCompileMemberAlignment(APICDeviceInfo, StatMMIOReadGC, 8);
311	# endif
312
313	#ifndef VBOX_DEVICE_STRUCT_TESTCASE
314
315	/*******************************************************************************
316	* Internal Functions *
317	*******************************************************************************/
318	static void apic_update_tpr(APICDeviceInfo pDev, APICState s, uint32_t val);
319
320	static void apic_eoi(APICDeviceInfo pDev, APICState s); /* */
321	static uint32_t apic_get_delivery_bitmask(APICDeviceInfo* pDev, uint8_t dest, uint8_t dest_mode);
322	static int apic_deliver(APICDeviceInfo* pDev, APICState *s,
323	uint8_t dest, uint8_t dest_mode,
324	uint8_t delivery_mode, uint8_t vector_num,
325	uint8_t polarity, uint8_t trigger_mode);
326	static int apic_get_arb_pri(APICState *s);
327	static int apic_get_ppr(APICState *s);
328	static uint32_t apic_get_current_count(APICDeviceInfo* pDev, APICState *s);
329	static void apicTimerSetInitialCount(APICDeviceInfo pDev, APICState s, uint32_t initial_count);
330	static void apicTimerSetLvt(APICDeviceInfo pDev, APICState pApic, uint32_t fNew);
331	static void apicSendInitIpi(APICDeviceInfo* pDev, APICState *s);
332
333	static void apic_init_ipi(APICDeviceInfo* pDev, APICState *s);
334	static void apic_set_irq(APICDeviceInfo* pDev, APICState *s, int vector_num, int trigger_mode);
335	static bool apic_update_irq(APICDeviceInfo* pDev, APICState *s);
336
337
338	DECLINLINE(APICState) getLapicById(APICDeviceInfo pDev, VMCPUID id)
339	{
340	AssertFatalMsg(id < pDev->cCpus, ("CPU id %d out of range\n", id));
341	return &pDev->CTX_SUFF(paLapics)[id];
342	}
343
344	DECLINLINE(APICState) getLapic(APICDeviceInfo pDev)
345	{
346	/* LAPIC's array is indexed by CPU id */
347	VMCPUID id = pDev->CTX_SUFF(pApicHlp)->pfnGetCpuId(pDev->CTX_SUFF(pDevIns));
348	return getLapicById(pDev, id);
349	}
350
351	DECLINLINE(VMCPUID) getCpuFromLapic(APICDeviceInfo* pDev, APICState *s)
352	{
353	/* for now we assume LAPIC physical id == CPU id */
354	return VMCPUID(s->phys_id);
355	}
356
357	DECLINLINE(void) cpuSetInterrupt(APICDeviceInfo* pDev, APICState *s, PDMAPICIRQ enmType = PDMAPICIRQ_HARDWARE)
358	{
359	LogFlow(("apic: setting interrupt flag for cpu %d\n", getCpuFromLapic(pDev, s)));
360	pDev->CTX_SUFF(pApicHlp)->pfnSetInterruptFF(pDev->CTX_SUFF(pDevIns), enmType,
361	getCpuFromLapic(pDev, s));
362	}
363
364	DECLINLINE(void) cpuClearInterrupt(APICDeviceInfo* pDev, APICState *s, PDMAPICIRQ enmType = PDMAPICIRQ_HARDWARE)
365	{
366	LogFlow(("apic: clear interrupt flag\n"));
367	pDev->CTX_SUFF(pApicHlp)->pfnClearInterruptFF(pDev->CTX_SUFF(pDevIns), enmType,
368	getCpuFromLapic(pDev, s));
369	}
370
371	# ifdef IN_RING3
372
373	DECLINLINE(void) cpuSendSipi(APICDeviceInfo* pDev, APICState *s, int vector)
374	{
375	Log2(("apic: send SIPI vector=%d\n", vector));
376
377	pDev->pApicHlpR3->pfnSendSipi(pDev->pDevInsR3,
378	getCpuFromLapic(pDev, s),
379	vector);
380	}
381
382	DECLINLINE(void) cpuSendInitIpi(APICDeviceInfo* pDev, APICState *s)
383	{
384	Log2(("apic: send init IPI\n"));
385
386	pDev->pApicHlpR3->pfnSendInitIpi(pDev->pDevInsR3,
387	getCpuFromLapic(pDev, s));
388	}
389
390	# endif /* IN_RING3 */
391
392	DECLINLINE(uint32_t) getApicEnableBits(APICDeviceInfo* pDev)
393	{
394	switch (pDev->enmVersion)
395	{
396	case PDMAPICVERSION_NONE:
397	return 0;
398	case PDMAPICVERSION_APIC:
399	return MSR_IA32_APICBASE_ENABLE;
400	case PDMAPICVERSION_X2APIC:
401	return MSR_IA32_APICBASE_ENABLE \| MSR_IA32_APICBASE_X2ENABLE ;
402	default:
403	AssertMsgFailed(("Unsupported APIC version %d\n", pDev->enmVersion));
404	return 0;
405	}
406	}
407
408	DECLINLINE(PDMAPICVERSION) getApicMode(APICState *apic)
409	{
410	switch (((apic->apicbase) >> 10) & 0x3)
411	{
412	case 0:
413	return PDMAPICVERSION_NONE;
414	case 1:
415	default:
416	/* Invalid */
417	return PDMAPICVERSION_NONE;
418	case 2:
419	return PDMAPICVERSION_APIC;
420	case 3:
421	return PDMAPICVERSION_X2APIC;
422	}
423	}
424
425	static int apic_bus_deliver(APICDeviceInfo* pDev,
426	uint32_t deliver_bitmask, uint8_t delivery_mode,
427	uint8_t vector_num, uint8_t polarity,
428	uint8_t trigger_mode)
429	{
430	LogFlow(("apic_bus_deliver mask=%x mode=%x vector=%x polarity=%x trigger_mode=%x\n", deliver_bitmask, delivery_mode, vector_num, polarity, trigger_mode));
431	switch (delivery_mode) {
432	case APIC_DM_LOWPRI:
433	{
434	int d = -1;
435	if (deliver_bitmask)
436	d = ffs_bit(deliver_bitmask);
437	if (d >= 0)
438	{
439	APICState* apic = getLapicById(pDev, d);
440	apic_set_irq(pDev, apic, vector_num, trigger_mode);
441	}
442	return VINF_SUCCESS;
443	}
444	case APIC_DM_FIXED:
445	/* XXX: arbitration */
446	break;
447
448	case APIC_DM_SMI:
449	foreach_apic(pDev, deliver_bitmask,
450	cpuSetInterrupt(pDev, apic, PDMAPICIRQ_SMI));
451	return VINF_SUCCESS;
452
453	case APIC_DM_NMI:
454	foreach_apic(pDev, deliver_bitmask,
455	cpuSetInterrupt(pDev, apic, PDMAPICIRQ_NMI));
456	return VINF_SUCCESS;
457
458	case APIC_DM_INIT:
459	/* normal INIT IPI sent to processors */
460	#ifdef IN_RING3
461	foreach_apic(pDev, deliver_bitmask,
462	apicSendInitIpi(pDev, apic));
463	return VINF_SUCCESS;
464	#else
465	/* We shall send init IPI only in R3, R0 calls should be
466	rescheduled to R3 */
467	return VINF_IOM_HC_MMIO_READ_WRITE;
468	#endif /* IN_RING3 */
469	case APIC_DM_EXTINT:
470	/* handled in I/O APIC code */
471	break;
472
473	default:
474	return VINF_SUCCESS;
475	}
476
477	foreach_apic(pDev, deliver_bitmask,
478	apic_set_irq (pDev, apic, vector_num, trigger_mode));
479	return VINF_SUCCESS;
480	}
481
482
483	PDMBOTHCBDECL(void) apicSetBase(PPDMDEVINS pDevIns, uint64_t val)
484	{
485	APICDeviceInfo pDev = PDMINS_2_DATA(pDevIns, APICDeviceInfo );
486	Assert(PDMCritSectIsOwner(pDev->CTX_SUFF(pCritSect)));
487	APICState s = getLapic(pDev); /* @todo fix interface */
488	Log(("apicSetBase: %016RX64\n", val));
489
490	/** @todo: do we need to lock here ? */
491	/* APIC_LOCK_VOID(pDev, VERR_INTERNAL_ERROR); */
492	/** @todo If this change is valid immediately, then we should change the MMIO registration! */
493	/* We cannot change if this CPU is BSP or not by writing to MSR - it's hardwired */
494	PDMAPICVERSION oldMode = getApicMode(s);
495	s->apicbase =
496	(val & 0xfffff000) \| /* base */
497	(val & getApicEnableBits(pDev)) \| /* mode */
498	(s->apicbase & MSR_IA32_APICBASE_BSP) /* keep BSP bit */;
499	PDMAPICVERSION newMode = getApicMode(s);
500
501	if (oldMode != newMode)
502	{
503	switch (newMode)
504	{
505	case PDMAPICVERSION_NONE:
506	{
507	s->spurious_vec &= ~APIC_SV_ENABLE;
508	/* Clear any pending APIC interrupt action flag. */
509	cpuClearInterrupt(pDev, s);
510	/** @todo: why do we do that? */
511	pDev->CTX_SUFF(pApicHlp)->pfnChangeFeature(pDevIns, PDMAPICVERSION_NONE);
512	break;
513	}
514	case PDMAPICVERSION_APIC:
515	/** @todo: map MMIO ranges, if needed */
516	break;
517	case PDMAPICVERSION_X2APIC:
518	/** @todo: unmap MMIO ranges of this APIC, according to the spec */
519	break;
520	default:
521	break;
522	}
523	}
524	/* APIC_UNLOCK(pDev); */
525	}
526
527	PDMBOTHCBDECL(uint64_t) apicGetBase(PPDMDEVINS pDevIns)
528	{
529	APICDeviceInfo pDev = PDMINS_2_DATA(pDevIns, APICDeviceInfo );
530	Assert(PDMCritSectIsOwner(pDev->CTX_SUFF(pCritSect)));
531	APICState s = getLapic(pDev); /* @todo fix interface */
532	LogFlow(("apicGetBase: %016llx\n", (uint64_t)s->apicbase));
533	return s->apicbase;
534	}
535
536	PDMBOTHCBDECL(void) apicSetTPR(PPDMDEVINS pDevIns, VMCPUID idCpu, uint8_t val)
537	{
538	APICDeviceInfo pDev = PDMINS_2_DATA(pDevIns, APICDeviceInfo );
539	Assert(PDMCritSectIsOwner(pDev->CTX_SUFF(pCritSect)));
540	APICState *s = getLapicById(pDev, idCpu);
541	LogFlow(("apicSetTPR: val=%#x (trp %#x -> %#x)\n", val, s->tpr, val));
542	apic_update_tpr(pDev, s, val);
543	}
544
545	PDMBOTHCBDECL(uint8_t) apicGetTPR(PPDMDEVINS pDevIns, VMCPUID idCpu)
546	{
547	/* We don't perform any locking here as that would cause a lot of contention for VT-x/AMD-V. */
548	APICDeviceInfo pDev = PDMINS_2_DATA(pDevIns, APICDeviceInfo );
549	APICState *s = getLapicById(pDev, idCpu);
550	Log2(("apicGetTPR: returns %#x\n", s->tpr));
551	return s->tpr;
552	}
553
554	/**
555	* Writes to an APIC register via MMIO or MSR.
556	*
557	* @returns Strict VBox status code.
558	* @param pDev The PDM device instance.
559	* @param pApic The APIC being written to.
560	* @param iReg The APIC register index.
561	* @param u64Value The value being written.
562	* @param rcBusy The busy return code to employ. See
563	* PDMCritSectEnter for a description.
564	* @param fMsr Set if called via MSR, clear if MMIO.
565	*/
566	static int apicWriteRegister(APICDeviceInfo pDev, APICState pApic, uint32_t iReg, uint64_t u64Value,
567	int rcBusy, bool fMsr)
568	{
569	Assert(!PDMCritSectIsOwner(pDev->CTX_SUFF(pCritSect)));
570
571	int rc = VINF_SUCCESS;
572	switch (iReg)
573	{
574	case 0x02:
575	APIC_LOCK(pDev, rcBusy);
576	pApic->id = (u64Value >> 24); /** @todo r=bird: Is the range supposed to be 40 bits??? */
577	APIC_UNLOCK(pDev);
578	break;
579
580	case 0x03:
581	/* read only, ignore write. */
582	break;
583
584	case 0x08:
585	APIC_LOCK(pDev, rcBusy);
586	apic_update_tpr(pDev, pApic, u64Value);
587	APIC_UNLOCK(pDev);
588	break;
589
590	case 0x09: case 0x0a:
591	Log(("apicWriteRegister: write to read-only register %d ignored\n", iReg));
592	break;
593
594	case 0x0b: /* EOI */
595	APIC_LOCK(pDev, rcBusy);
596	apic_eoi(pDev, pApic);
597	APIC_UNLOCK(pDev);
598	break;
599
600	case 0x0d:
601	APIC_LOCK(pDev, rcBusy);
602	pApic->log_dest = (u64Value >> 24) & 0xff;
603	APIC_UNLOCK(pDev);
604	break;
605
606	case 0x0e:
607	APIC_LOCK(pDev, rcBusy);
608	pApic->dest_mode = u64Value >> 28; /** @todo r=bird: range? This used to be 32-bit before morphed into an MSR handler. */
609	APIC_UNLOCK(pDev);
610	break;
611
612	case 0x0f:
613	APIC_LOCK(pDev, rcBusy);
614	pApic->spurious_vec = u64Value & 0x1ff;
615	apic_update_irq(pDev, pApic);
616	APIC_UNLOCK(pDev);
617	break;
618
619	case 0x10: case 0x11: case 0x12: case 0x13: case 0x14: case 0x15: case 0x16: case 0x17:
620	case 0x18: case 0x19: case 0x1a: case 0x1b: case 0x1c: case 0x1d: case 0x1e: case 0x1f:
621	case 0x20: case 0x21: case 0x22: case 0x23: case 0x24: case 0x25: case 0x26: case 0x27:
622	case 0x28:
623	Log(("apicWriteRegister: write to read-only register %d ignored\n", iReg));
624	break;
625
626	case 0x30:
627	APIC_LOCK(pDev, rcBusy);
628	pApic->icr[0] = (uint32_t)u64Value;
629	if (fMsr) /* Here one of the differences with regular APIC: ICR is single 64-bit register */
630	pApic->icr[1] = (uint32_t)(u64Value >> 32);
631	rc = apic_deliver(pDev, pApic, (pApic->icr[1] >> 24) & 0xff, (pApic->icr[0] >> 11) & 1,
632	(pApic->icr[0] >> 8) & 7, (pApic->icr[0] & 0xff),
633	(pApic->icr[0] >> 14) & 1, (pApic->icr[0] >> 15) & 1);
634	APIC_UNLOCK(pDev);
635	break;
636
637	case 0x31:
638	APIC_LOCK(pDev, rcBusy);
639	if (!fMsr)
640	pApic->icr[1] = (uint64_t)u64Value;
641	else
642	pApic->esr \|= ESR_ILLEGAL_ADDRESS;
643	APIC_UNLOCK(pDev);
644	break;
645
646	case 0x32 + APIC_LVT_TIMER:
647	AssertCompile(APIC_LVT_TIMER == 0);
648	APIC_AND_TM_LOCK(pDev, pApic, rcBusy);
649	apicTimerSetLvt(pDev, pApic, u64Value);
650	APIC_AND_TM_UNLOCK(pDev, pApic);
651	break;
652
653	case 0x33: case 0x34: case 0x35: case 0x36: case 0x37:
654	APIC_LOCK(pDev, rcBusy);
655	pApic->lvt[iReg - 0x32] = u64Value;
656	APIC_UNLOCK(pDev);
657	break;
658
659	case 0x38:
660	APIC_AND_TM_LOCK(pDev, pApic, rcBusy);
661	apicTimerSetInitialCount(pDev, pApic, u64Value);
662	APIC_AND_TM_UNLOCK(pDev, pApic);
663	break;
664
665	case 0x39:
666	Log(("apicWriteRegister: write to read-only register %d ignored\n", iReg));
667	break;
668
669	case 0x3e:
670	{
671	APIC_LOCK(pDev, rcBusy);
672	pApic->divide_conf = u64Value & 0xb;
673	int v = (pApic->divide_conf & 3) \| ((pApic->divide_conf >> 1) & 4);
674	pApic->count_shift = (v + 1) & 7;
675	APIC_UNLOCK(pDev);
676	break;
677	}
678
679	case 0x3f:
680	if (fMsr)
681	{
682	/* Self IPI, see x2APIC book 2.4.5 */
683	APIC_LOCK(pDev, rcBusy);
684	int vector = u64Value & 0xff;
685	rc = apic_bus_deliver(pDev,
686	1 << pApic->id /* Self */,
687	0 /* Delivery mode - fixed */,
688	vector,
689	0 /* Polarity - conform to the bus */,
690	0 /* Trigger mode - edge */);
691	APIC_UNLOCK(pDev);
692	break;
693	}
694	/* else: fall thru */
695	default:
696	AssertMsgFailed(("unknown iReg %x\n", iReg));
697	pApic->esr \|= ESR_ILLEGAL_ADDRESS;
698	break;
699	}
700
701	return rc;
702	}
703
704	/**
705	* @interface_method_impl{PDMAPICREG,pfnWriteMSRR3}
706	*/
707	PDMBOTHCBDECL(int) apicWriteMSR(PPDMDEVINS pDevIns, VMCPUID idCpu, uint32_t u32Reg, uint64_t u64Value)
708	{
709	APICDeviceInfo pDev = PDMINS_2_DATA(pDevIns, APICDeviceInfo );
710	if (pDev->enmVersion < PDMAPICVERSION_X2APIC)
711	return VERR_EM_INTERPRETER; /** @todo tell the caller to raise hell (\#GP(0)). */
712
713	APICState *pApic = getLapicById(pDev, idCpu);
714	uint32_t iReg = (u32Reg - MSR_IA32_APIC_START) & 0xff;
715	return apicWriteRegister(pDev, pApic, iReg, u64Value, VINF_SUCCESS /rcBusy/, true /fMsr/);
716	}
717
718
719	/**
720	* @interface_method_impl{PDMAPICREG,pfnReadMSRR3}
721	*/
722	PDMBOTHCBDECL(int) apicReadMSR(PPDMDEVINS pDevIns, VMCPUID idCpu, uint32_t u32Reg, uint64_t *pu64Value)
723	{
724	APICDeviceInfo pDev = PDMINS_2_DATA(pDevIns, APICDeviceInfo );
725	Assert(PDMCritSectIsOwner(pDev->CTX_SUFF(pCritSect)));
726
727	if (pDev->enmVersion < PDMAPICVERSION_X2APIC)
728	return VERR_EM_INTERPRETER;
729
730	uint32_t index = (u32Reg - MSR_IA32_APIC_START) & 0xff;
731	APICState *apic = getLapicById(pDev, idCpu);
732	uint64_t val = 0;
733	int rc = VINF_SUCCESS;
734
735	switch (index)
736	{
737	case 0x02: /* id */
738	val = apic->id << 24;
739	break;
740	case 0x03: /* version */
741	val = APIC_HW_VERSION
742	\| ((APIC_LVT_NB - 1) << 16) /* Max LVT index */
743	\| (0 << 24) /* Support for EOI broadcast suppression */;
744	break;
745	case 0x08:
746	val = apic->tpr;
747	break;
748	case 0x09:
749	val = apic_get_arb_pri(apic);
750	break;
751	case 0x0a:
752	/* ppr */
753	val = apic_get_ppr(apic);
754	break;
755	case 0x0b:
756	val = 0;
757	break;
758	case 0x0d:
759	val = (uint64_t)apic->log_dest << 24;
760	break;
761	case 0x0e:
762	/* Bottom 28 bits are always 1 */
763	val = ((uint64_t)apic->dest_mode << 28) \| 0xfffffff;
764	break;
765	case 0x0f:
766	val = apic->spurious_vec;
767	break;
768	case 0x10: case 0x11: case 0x12: case 0x13: case 0x14: case 0x15: case 0x16: case 0x17:
769	val = apic->isr[index & 7];
770	break;
771	case 0x18: case 0x19: case 0x1a: case 0x1b: case 0x1c: case 0x1d: case 0x1e: case 0x1f:
772	val = apic->tmr[index & 7];
773	break;
774	case 0x20: case 0x21: case 0x22: case 0x23: case 0x24: case 0x25: case 0x26: case 0x27:
775	val = apic->irr[index & 7];
776	break;
777	case 0x28:
778	val = apic->esr;
779	break;
780	case 0x30:
781	/* Here one of the differences with regular APIC: ICR is single 64-bit register */
782	val = ((uint64_t)apic->icr[1] << 32) \| apic->icr[0];
783	break;
784	case 0x32: case 0x33: case 0x34: case 0x35: case 0x36: case 0x37:
785	val = apic->lvt[index - 0x32];
786	break;
787	case 0x38:
788	val = apic->initial_count;
789	break;
790	case 0x39:
791	val = apic_get_current_count(pDev, apic);
792	break;
793	case 0x3e:
794	val = apic->divide_conf;
795	break;
796	case 0x3f:
797	/* Self IPI register is write only */
798	Log(("apicReadMSR: read from write-only register %d ignored\n", index));
799	break;
800	case 0x2f:
801	/**
802	* Correctable machine check exception vector, @todo: implement me!
803	*/
804	default:
805	AssertMsgFailed(("apicReadMSR: unknown index %x\n", index));
806	/**
807	* @todo: according to spec when APIC writes to ESR it msut raise error interrupt,
808	* i.e. LVT[5]
809	*/
810	apic->esr \|= ESR_ILLEGAL_ADDRESS;
811	val = 0;
812	break;
813	}
814	*pu64Value = val;
815	return rc;
816	}
817
818	/**
819	* More or less private interface between IOAPIC, only PDM is responsible
820	* for connecting the two devices.
821	*/
822	PDMBOTHCBDECL(int) apicBusDeliverCallback(PPDMDEVINS pDevIns, uint8_t u8Dest, uint8_t u8DestMode,
823	uint8_t u8DeliveryMode, uint8_t iVector, uint8_t u8Polarity,
824	uint8_t u8TriggerMode)
825	{
826	APICDeviceInfo pDev = PDMINS_2_DATA(pDevIns, APICDeviceInfo );
827	Assert(PDMCritSectIsOwner(pDev->CTX_SUFF(pCritSect)));
828	LogFlow(("apicBusDeliverCallback: pDevIns=%p u8Dest=%#x u8DestMode=%#x u8DeliveryMode=%#x iVector=%#x u8Polarity=%#x u8TriggerMode=%#x\n",
829	pDevIns, u8Dest, u8DestMode, u8DeliveryMode, iVector, u8Polarity, u8TriggerMode));
830	return apic_bus_deliver(pDev, apic_get_delivery_bitmask(pDev, u8Dest, u8DestMode),
831	u8DeliveryMode, iVector, u8Polarity, u8TriggerMode);
832	}
833
834	/**
835	* Local interrupt delivery, for devices attached to the CPU's LINT0/LINT1 pin.
836	* Normally used for 8259A PIC and NMI.
837	*/
838	PDMBOTHCBDECL(int) apicLocalInterrupt(PPDMDEVINS pDevIns, uint8_t u8Pin, uint8_t u8Level)
839	{
840	APICDeviceInfo pDev = PDMINS_2_DATA(pDevIns, APICDeviceInfo );
841	APICState *s = getLapicById(pDev, 0);
842
843	Assert(PDMCritSectIsOwner(pDev->CTX_SUFF(pCritSect)));
844	LogFlow(("apicLocalInterrupt: pDevIns=%p u8Pin=%x u8Level=%x\n", pDevIns, u8Pin, u8Level));
845
846	/* If LAPIC is disabled, go straight to the CPU. */
847	if (!(s->spurious_vec & APIC_SV_ENABLE))
848	{
849	LogFlow(("apicLocalInterrupt: LAPIC disabled, delivering directly to CPU core.\n"));
850	if (u8Level)
851	cpuSetInterrupt(pDev, s, PDMAPICIRQ_EXTINT);
852	else
853	cpuClearInterrupt(pDev, s, PDMAPICIRQ_EXTINT);
854
855	return VINF_SUCCESS;
856	}
857
858	/* If LAPIC is enabled, interrupts are subject to LVT programming. */
859
860	/* There are only two local interrupt pins. */
861	AssertMsgReturn(u8Pin <= 1, ("Invalid LAPIC pin %d\n", u8Pin), VERR_INVALID_PARAMETER);
862
863	/* NB: We currently only deliver local interrupts to the first CPU. In theory they
864	* should be delivered to all CPUs and it is the guest's responsibility to ensure
865	* no more than one CPU has the interrupt unmasked.
866	*/
867	uint32_t u32Lvec;
868
869	u32Lvec = s->lvt[APIC_LVT_LINT0 + u8Pin]; /* Fetch corresponding LVT entry. */
870	/* Drop int if entry is masked. May not be correct for level-triggered interrupts. */
871	if (!(u32Lvec & APIC_LVT_MASKED))
872	{ uint8_t u8Delivery;
873	PDMAPICIRQ enmType;
874
875	u8Delivery = (u32Lvec >> 8) & 7;
876	switch (u8Delivery)
877	{
878	case APIC_DM_EXTINT:
879	Assert(u8Pin == 0); /* PIC should be wired to LINT0. */
880	enmType = PDMAPICIRQ_EXTINT;
881	/* ExtINT can be both set and cleared, NMI/SMI/INIT can only be set. */
882	LogFlow(("apicLocalInterrupt: %s ExtINT interrupt\n", u8Level ? "setting" : "clearing"));
883	if (u8Level)
884	cpuSetInterrupt(pDev, s, enmType);
885	else
886	cpuClearInterrupt(pDev, s, enmType);
887	return VINF_SUCCESS;
888	case APIC_DM_NMI:
889	/* External NMI should be wired to LINT1, but Linux sometimes programs
890	* LVT0 to NMI delivery mode as well.
891	*/
892	enmType = PDMAPICIRQ_NMI;
893	/* Currently delivering NMIs through here causes problems with NMI watchdogs
894	* on certain Linux kernels, e.g. 64-bit CentOS 5.3. Disable NMIs for now.
895	*/
896	return VINF_SUCCESS;
897	case APIC_DM_SMI:
898	enmType = PDMAPICIRQ_SMI;
899	break;
900	case APIC_DM_FIXED:
901	{
902	/** @todo implement APIC_DM_FIXED! */
903	static unsigned s_c = 0;
904	if (s_c++ < 5)
905	LogRel(("delivery type APIC_DM_FIXED not implemented. u8Pin=%d u8Level=%d\n", u8Pin, u8Level));
906	return VINF_SUCCESS;
907	}
908	case APIC_DM_INIT:
909	/** @todo implement APIC_DM_INIT? */
910	default:
911	{
912	static unsigned s_c = 0;
913	if (s_c++ < 100)
914	AssertLogRelMsgFailed(("delivery type %d not implemented. u8Pin=%d u8Level=%d\n", u8Delivery, u8Pin, u8Level));
915	return VERR_INTERNAL_ERROR_4;
916	}
917	}
918	LogFlow(("apicLocalInterrupt: setting local interrupt type %d\n", enmType));
919	cpuSetInterrupt(pDev, s, enmType);
920	}
921	return VINF_SUCCESS;
922	}
923
924	/* return -1 if no bit is set */
925	static int get_highest_priority_int(uint32_t *tab)
926	{
927	int i;
928	for(i = 7; i >= 0; i--) {
929	if (tab[i] != 0) {
930	return i * 32 + fls_bit(tab[i]);
931	}
932	}
933	return -1;
934	}
935
936	static int apic_get_ppr(APICState *s)
937	{
938	int tpr, isrv, ppr;
939
940	tpr = (s->tpr >> 4);
941	isrv = get_highest_priority_int(s->isr);
942	if (isrv < 0)
943	isrv = 0;
944	isrv >>= 4;
945	if (tpr >= isrv)
946	ppr = s->tpr;
947	else
948	ppr = isrv << 4;
949	return ppr;
950	}
951
952	static int apic_get_ppr_zero_tpr(APICState *s)
953	{
954	int isrv;
955
956	isrv = get_highest_priority_int(s->isr);
957	if (isrv < 0)
958	isrv = 0;
959	return isrv;
960	}
961
962	static int apic_get_arb_pri(APICState *s)
963	{
964	/* XXX: arbitration */
965	return 0;
966	}
967
968	/* signal the CPU if an irq is pending */
969	static bool apic_update_irq(APICDeviceInfo pDev, APICState s)
970	{
971	int irrv, ppr;
972	if (!(s->spurious_vec & APIC_SV_ENABLE))
973	{
974	/* Clear any pending APIC interrupt action flag. */
975	cpuClearInterrupt(pDev, s);
976	return false;
977	}
978
979	irrv = get_highest_priority_int(s->irr);
980	if (irrv < 0)
981	return false;
982	ppr = apic_get_ppr(s);
983	if (ppr && (irrv & 0xf0) <= (ppr & 0xf0))
984	return false;
985	cpuSetInterrupt(pDev, s);
986	return true;
987	}
988
989	/* Check if the APIC has a pending interrupt/if a TPR change would active one. */
990	PDMBOTHCBDECL(bool) apicHasPendingIrq(PPDMDEVINS pDevIns)
991	{
992	int irrv, ppr;
993	APICDeviceInfo pDev = PDMINS_2_DATA(pDevIns, APICDeviceInfo );
994	if (!pDev)
995	return false;
996
997	/* We don't perform any locking here as that would cause a lot of contention for VT-x/AMD-V. */
998
999	APICState s = getLapic(pDev); /* @todo fix interface */
1000
1001	/*
1002	* All our callbacks now come from single IOAPIC, thus locking
1003	* seems to be excessive now (@todo: check)
1004	*/
1005	irrv = get_highest_priority_int(s->irr);
1006	if (irrv < 0)
1007	return false;
1008
1009	ppr = apic_get_ppr_zero_tpr(s);
1010
1011	if (ppr && (irrv & 0xf0) <= (ppr & 0xf0))
1012	return false;
1013
1014	return true;
1015	}
1016
1017	static void apic_update_tpr(APICDeviceInfo pDev, APICState s, uint32_t val)
1018	{
1019	bool fIrqIsActive = false;
1020	bool fIrqWasActive = false;
1021
1022	fIrqWasActive = apic_update_irq(pDev, s);
1023	s->tpr = val;
1024	fIrqIsActive = apic_update_irq(pDev, s);
1025
1026	/* If an interrupt is pending and now masked, then clear the FF flag. */
1027	if (fIrqWasActive && !fIrqIsActive)
1028	{
1029	Log(("apic_update_tpr: deactivate interrupt that was masked by the TPR update (%x)\n", val));
1030	STAM_COUNTER_INC(&pDev->StatClearedActiveIrq);
1031	cpuClearInterrupt(pDev, s);
1032	}
1033	}
1034
1035	static void apic_set_irq(APICDeviceInfo pDev, APICState s, int vector_num, int trigger_mode)
1036	{
1037	LogFlow(("CPU%d: apic_set_irq vector=%x, trigger_mode=%x\n", s->phys_id, vector_num, trigger_mode));
1038	set_bit(s->irr, vector_num);
1039	if (trigger_mode)
1040	set_bit(s->tmr, vector_num);
1041	else
1042	reset_bit(s->tmr, vector_num);
1043	apic_update_irq(pDev, s);
1044	}
1045
1046	static void apic_eoi(APICDeviceInfo pDev, APICState s)
1047	{
1048	int isrv;
1049	isrv = get_highest_priority_int(s->isr);
1050	if (isrv < 0)
1051	return;
1052	reset_bit(s->isr, isrv);
1053	LogFlow(("CPU%d: apic_eoi isrv=%x\n", s->phys_id, isrv));
1054	/* XXX: send the EOI packet to the APIC bus to allow the I/O APIC to
1055	set the remote IRR bit for level triggered interrupts. */
1056	apic_update_irq(pDev, s);
1057	}
1058
1059	static uint32_t apic_get_delivery_bitmask(APICDeviceInfo *pDev, uint8_t dest, uint8_t dest_mode)
1060	{
1061	uint32_t mask = 0;
1062
1063	if (dest_mode == 0)
1064	{
1065	if (dest == 0xff)
1066	mask = 0xff;
1067	else
1068	mask = 1 << dest;
1069	}
1070	else
1071	{
1072	APICState *apic = pDev->CTX_SUFF(paLapics);
1073	uint32_t i;
1074
1075	/* XXX: cluster mode */
1076	for(i = 0; i < pDev->cCpus; i++)
1077	{
1078	if (apic->dest_mode == APIC_DESTMODE_FLAT)
1079	{
1080	if (dest & apic->log_dest)
1081	mask \|= (1 << i);
1082	}
1083	else if (apic->dest_mode == APIC_DESTMODE_CLUSTER)
1084	{
1085	if ((dest & 0xf0) == (apic->log_dest & 0xf0)
1086	&&
1087	(dest & apic->log_dest & 0x0f))
1088	{
1089	mask \|= (1 << i);
1090	}
1091	}
1092	apic++;
1093	}
1094	}
1095
1096	return mask;
1097	}
1098
1099	#ifdef IN_RING3
1100	static void apic_init_ipi(APICDeviceInfo* pDev, APICState *s)
1101	{
1102	int i;
1103
1104	for(i = 0; i < APIC_LVT_NB; i++)
1105	s->lvt[i] = 1 << 16; /* mask LVT */
1106	s->tpr = 0;
1107	s->spurious_vec = 0xff;
1108	s->log_dest = 0;
1109	s->dest_mode = 0xff; /** @todo 0xff???? */
1110	memset(s->isr, 0, sizeof(s->isr));
1111	memset(s->tmr, 0, sizeof(s->tmr));
1112	memset(s->irr, 0, sizeof(s->irr));
1113	s->esr = 0;
1114	memset(s->icr, 0, sizeof(s->icr));
1115	s->divide_conf = 0;
1116	s->count_shift = 1;
1117	s->initial_count = 0;
1118	s->initial_count_load_time = 0;
1119	s->next_time = 0;
1120	}
1121
1122
1123	static void apicSendInitIpi(APICDeviceInfo* pDev, APICState *s)
1124	{
1125	apic_init_ipi(pDev, s);
1126	cpuSendInitIpi(pDev, s);
1127	}
1128
1129	/* send a SIPI message to the CPU to start it */
1130	static void apic_startup(APICDeviceInfo* pDev, APICState *s, int vector_num)
1131	{
1132	Log(("[SMP] apic_startup: %d on CPUs %d\n", vector_num, s->phys_id));
1133	cpuSendSipi(pDev, s, vector_num);
1134	}
1135	#endif /* IN_RING3 */
1136
1137	static int apic_deliver(APICDeviceInfo* pDev, APICState *s,
1138	uint8_t dest, uint8_t dest_mode,
1139	uint8_t delivery_mode, uint8_t vector_num,
1140	uint8_t polarity, uint8_t trigger_mode)
1141	{
1142	uint32_t deliver_bitmask = 0;
1143	int dest_shorthand = (s->icr[0] >> 18) & 3;
1144
1145	LogFlow(("apic_deliver dest=%x dest_mode=%x dest_shorthand=%x delivery_mode=%x vector_num=%x polarity=%x trigger_mode=%x\n", dest, dest_mode, dest_shorthand, delivery_mode, vector_num, polarity, trigger_mode));
1146
1147	switch (dest_shorthand) {
1148	case 0:
1149	deliver_bitmask = apic_get_delivery_bitmask(pDev, dest, dest_mode);
1150	break;
1151	case 1:
1152	deliver_bitmask = (1 << s->id);
1153	break;
1154	case 2:
1155	deliver_bitmask = 0xffffffff;
1156	break;
1157	case 3:
1158	deliver_bitmask = 0xffffffff & ~(1 << s->id);
1159	break;
1160	}
1161
1162	switch (delivery_mode) {
1163	case APIC_DM_INIT:
1164	{
1165	int trig_mode = (s->icr[0] >> 15) & 1;
1166	int level = (s->icr[0] >> 14) & 1;
1167	if (level == 0 && trig_mode == 1) {
1168	foreach_apic(pDev, deliver_bitmask,
1169	apic->arb_id = apic->id);
1170	Log(("CPU%d: APIC_DM_INIT arbitration id(s) set\n", s->phys_id));
1171	return VINF_SUCCESS;
1172	}
1173	}
1174	break;
1175
1176	case APIC_DM_SIPI:
1177	# ifdef IN_RING3
1178	foreach_apic(pDev, deliver_bitmask,
1179	apic_startup(pDev, apic, vector_num));
1180	return VINF_SUCCESS;
1181	# else
1182	/* We shall send SIPI only in R3, R0 calls should be
1183	rescheduled to R3 */
1184	return VINF_IOM_HC_MMIO_WRITE;
1185	# endif
1186	}
1187
1188	return apic_bus_deliver(pDev, deliver_bitmask, delivery_mode, vector_num,
1189	polarity, trigger_mode);
1190	}
1191
1192
1193	PDMBOTHCBDECL(int) apicGetInterrupt(PPDMDEVINS pDevIns)
1194	{
1195	APICDeviceInfo pDev = PDMINS_2_DATA(pDevIns, APICDeviceInfo );
1196	/* if the APIC is not installed or enabled, we let the 8259 handle the
1197	IRQs */
1198	if (!pDev)
1199	{
1200	Log(("apic_get_interrupt: returns -1 (!s)\n"));
1201	return -1;
1202	}
1203
1204	Assert(PDMCritSectIsOwner(pDev->CTX_SUFF(pCritSect)));
1205
1206	APICState s = getLapic(pDev); /* @todo fix interface */
1207	int intno;
1208
1209	if (!(s->spurious_vec & APIC_SV_ENABLE)) {
1210	Log(("CPU%d: apic_get_interrupt: returns -1 (APIC_SV_ENABLE)\n", s->phys_id));
1211	return -1;
1212	}
1213
1214	/* XXX: spurious IRQ handling */
1215	intno = get_highest_priority_int(s->irr);
1216	if (intno < 0) {
1217	Log(("CPU%d: apic_get_interrupt: returns -1 (irr)\n", s->phys_id));
1218	return -1;
1219	}
1220	if (s->tpr && (uint32_t)intno <= s->tpr) {
1221	Log(("apic_get_interrupt: returns %d (sp)\n", s->spurious_vec & 0xff));
1222	return s->spurious_vec & 0xff;
1223	}
1224	reset_bit(s->irr, intno);
1225	set_bit(s->isr, intno);
1226	apic_update_irq(pDev, s);
1227	LogFlow(("CPU%d: apic_get_interrupt: returns %d\n", s->phys_id, intno));
1228	return intno;
1229	}
1230
1231	/**
1232	* May return to ring-3 to acquire the TM and PDM lock.
1233	*/
1234	static uint32_t apic_get_current_count(APICDeviceInfo pDev, APICState s)
1235	{
1236	int64_t d;
1237	uint32_t val;
1238
1239	/* Acquire the timer lock w/ lock order kludge. */
1240	PDMCritSectLeave(pDev->CTX_SUFF(pCritSect));
1241	TMTimerLock(s->CTX_SUFF(pTimer), VINF_SUCCESS);
1242	PDMCritSectEnter(pDev->CTX_SUFF(pCritSect), VINF_SUCCESS);
1243
1244	d = (TMTimerGet(s->CTX_SUFF(pTimer)) - s->initial_count_load_time) >>
1245	s->count_shift;
1246
1247	if (s->lvt[APIC_LVT_TIMER] & APIC_LVT_TIMER_PERIODIC) {
1248	/* periodic */
1249	val = s->initial_count - (d % ((uint64_t)s->initial_count + 1));
1250	} else {
1251	if (d >= s->initial_count)
1252	val = 0;
1253	else
1254	val = s->initial_count - d;
1255	}
1256
1257	TMTimerUnlock(s->CTX_SUFF(pTimer));
1258
1259	return val;
1260	}
1261
1262	/**
1263	* Does the frequency hinting and logging.
1264	*
1265	* @param pApic The device state.
1266	*/
1267	DECLINLINE(void) apicDoFrequencyHinting(APICState *pApic)
1268	{
1269	if ( pApic->uHintedInitialCount != pApic->initial_count
1270	\|\| pApic->uHintedCountShift != (uint32_t)pApic->count_shift)
1271	{
1272	pApic->uHintedInitialCount = pApic->initial_count;
1273	pApic->uHintedCountShift = pApic->count_shift;
1274
1275	uint32_t uHz;
1276	if (pApic->initial_count > 0)
1277	{
1278	Assert((unsigned)pApic->count_shift < 30);
1279	uint64_t cTickPerPeriod = ((uint64_t)pApic->initial_count + 1) << pApic->count_shift;
1280	uHz = TMTimerGetFreq(pApic->CTX_SUFF(pTimer)) / cTickPerPeriod;
1281	}
1282	else
1283	uHz = 0;
1284	TMTimerSetFrequencyHint(pApic->CTX_SUFF(pTimer), uHz);
1285	Log(("apic: %u Hz\n", uHz));
1286	}
1287	}
1288
1289	/**
1290	* Implementation of the 0380h access: Timer reset + new initial count.
1291	*
1292	* @param pDev The device state.
1293	* @param pApic The APIC sub-device state.
1294	* @param u32NewInitialCount The new initial count for the timer.
1295	*/
1296	static void apicTimerSetInitialCount(APICDeviceInfo pDev, APICState pApic, uint32_t u32NewInitialCount)
1297	{
1298	STAM_COUNTER_INC(&pApic->StatTimerSetInitialCount);
1299	pApic->initial_count = u32NewInitialCount;
1300
1301	/*
1302	* Don't (re-)arm the timer if the it's masked or if it's
1303	* a zero length one-shot timer.
1304	*/
1305	if ( !(pApic->lvt[APIC_LVT_TIMER] & APIC_LVT_MASKED)
1306	&& u32NewInitialCount > 0)
1307	{
1308	/*
1309	* Calculate the relative next time and perform a combined timer get/set
1310	* operation. This avoids racing the clock between get and set.
1311	*/
1312	uint64_t cTicksNext = u32NewInitialCount;
1313	cTicksNext += 1;
1314	cTicksNext <<= pApic->count_shift;
1315	TMTimerSetRelative(pApic->CTX_SUFF(pTimer), cTicksNext, &pApic->initial_count_load_time);
1316	pApic->next_time = pApic->initial_count_load_time + cTicksNext;
1317	pApic->fTimerArmed = true;
1318	apicDoFrequencyHinting(pApic);
1319	STAM_COUNTER_INC(&pApic->StatTimerSetInitialCountArm);
1320	Log(("apicTimerSetInitialCount: cTicksNext=%'llu (%#llx) ic=%#x sh=%#x nxt=%#llx\n",
1321	cTicksNext, cTicksNext, u32NewInitialCount, pApic->count_shift, pApic->next_time));
1322	}
1323	else
1324	{
1325	/* Stop it if necessary and record the load time for unmasking. */
1326	if (pApic->fTimerArmed)
1327	{
1328	STAM_COUNTER_INC(&pApic->StatTimerSetInitialCountDisarm);
1329	TMTimerStop(pApic->CTX_SUFF(pTimer));
1330	pApic->fTimerArmed = false;
1331	pApic->uHintedCountShift = pApic->uHintedInitialCount = 0;
1332	}
1333	pApic->initial_count_load_time = TMTimerGet(pApic->CTX_SUFF(pTimer));
1334	Log(("apicTimerSetInitialCount: ic=%#x sh=%#x iclt=%#llx\n", u32NewInitialCount, pApic->count_shift, pApic->initial_count_load_time));
1335	}
1336	}
1337
1338	/**
1339	* Implementation of the 0320h access: change the LVT flags.
1340	*
1341	* @param pDev The device state.
1342	* @param pApic The APIC sub-device state to operate on.
1343	* @param fNew The new flags.
1344	*/
1345	static void apicTimerSetLvt(APICDeviceInfo pDev, APICState pApic, uint32_t fNew)
1346	{
1347	STAM_COUNTER_INC(&pApic->StatTimerSetLvt);
1348
1349	/*
1350	* Make the flag change, saving the old ones so we can avoid
1351	* unnecessary work.
1352	*/
1353	uint32_t const fOld = pApic->lvt[APIC_LVT_TIMER];
1354	pApic->lvt[APIC_LVT_TIMER] = fNew;
1355
1356	/* Only the masked and peridic bits are relevant (see apic_timer_update). */
1357	if ( (fOld & (APIC_LVT_MASKED \| APIC_LVT_TIMER_PERIODIC))
1358	!= (fNew & (APIC_LVT_MASKED \| APIC_LVT_TIMER_PERIODIC)))
1359	{
1360	/*
1361	* If changed to one-shot from periodic, stop the timer if we're not
1362	* in the first period.
1363	*/
1364	/** @todo check how clearing the periodic flag really should behave when not
1365	* in period 1. The current code just mirrors the behavior of the
1366	* original implementation. */
1367	if ( (fOld & APIC_LVT_TIMER_PERIODIC)
1368	&& !(fNew & APIC_LVT_TIMER_PERIODIC))
1369	{
1370	STAM_COUNTER_INC(&pApic->StatTimerSetLvtClearPeriodic);
1371	uint64_t cTicks = (pApic->next_time - pApic->initial_count_load_time) >> pApic->count_shift;
1372	if (cTicks >= pApic->initial_count)
1373	{
1374	/* not first period, stop it. */
1375	TMTimerStop(pApic->CTX_SUFF(pTimer));
1376	pApic->fTimerArmed = false;
1377	pApic->uHintedCountShift = pApic->uHintedInitialCount = 0;
1378	}
1379	/* else: first period, let it fire normally. */
1380	}
1381
1382	/*
1383	* We postpone stopping the timer when it's masked, this way we can
1384	* avoid some timer work when the guest temporarily masks the timer.
1385	* (apicTimerCallback will stop it if still masked.)
1386	*/
1387	if (fNew & APIC_LVT_MASKED)
1388	STAM_COUNTER_INC(&pApic->StatTimerSetLvtPostponed);
1389	else if (pApic->fTimerArmed)
1390	STAM_COUNTER_INC(&pApic->StatTimerSetLvtArmed);
1391	/*
1392	* If unmasked, not armed and with a valid initial count value (according
1393	* to our interpretation of the spec), we will have to rearm the timer so
1394	* it will fire at the end of the current period.
1395	*
1396	* N.B. This is code is currently RACING the virtual sync clock!
1397	*/
1398	else if ( (fOld & APIC_LVT_MASKED)
1399	&& pApic->initial_count > 0)
1400	{
1401	STAM_COUNTER_INC(&pApic->StatTimerSetLvtArm);
1402	for (unsigned cTries = 0; ; cTries++)
1403	{
1404	uint64_t NextTS;
1405	uint64_t cTicks = (TMTimerGet(pApic->CTX_SUFF(pTimer)) - pApic->initial_count_load_time) >> pApic->count_shift;
1406	if (fNew & APIC_LVT_TIMER_PERIODIC)
1407	NextTS = ((cTicks / ((uint64_t)pApic->initial_count + 1)) + 1) * ((uint64_t)pApic->initial_count + 1);
1408	else
1409	{
1410	if (cTicks >= pApic->initial_count)
1411	break;
1412	NextTS = (uint64_t)pApic->initial_count + 1;
1413	}
1414	NextTS <<= pApic->count_shift;
1415	NextTS += pApic->initial_count_load_time;
1416
1417	/* Try avoid the assertion in TM.cpp... this isn't perfect! */
1418	if ( NextTS > TMTimerGet(pApic->CTX_SUFF(pTimer))
1419	\|\| cTries > 10)
1420	{
1421	TMTimerSet(pApic->CTX_SUFF(pTimer), NextTS);
1422	pApic->next_time = NextTS;
1423	pApic->fTimerArmed = true;
1424	apicDoFrequencyHinting(pApic);
1425	Log(("apicTimerSetLvt: ic=%#x sh=%#x nxt=%#llx\n", pApic->initial_count, pApic->count_shift, pApic->next_time));
1426	break;
1427	}
1428	STAM_COUNTER_INC(&pApic->StatTimerSetLvtArmRetries);
1429	}
1430	}
1431	}
1432	else
1433	STAM_COUNTER_INC(&pApic->StatTimerSetLvtNoRelevantChange);
1434	}
1435
1436	# ifdef IN_RING3
1437	/**
1438	* Timer callback function.
1439	*
1440	* @param pDevIns The device state.
1441	* @param pTimer The timer handle.
1442	* @param pvUser User argument pointing to the APIC instance.
1443	*/
1444	static DECLCALLBACK(void) apicTimerCallback(PPDMDEVINS pDevIns, PTMTIMER pTimer, void *pvUser)
1445	{
1446	APICDeviceInfo pDev = PDMINS_2_DATA(pDevIns, APICDeviceInfo );
1447	APICState pApic = (APICState )pvUser;
1448	Assert(pApic->pTimerR3 == pTimer);
1449	Assert(pApic->fTimerArmed);
1450	Assert(PDMCritSectIsOwner(pDev->pCritSectR3));
1451	Assert(TMTimerIsLockOwner(pTimer));
1452
1453	if (!(pApic->lvt[APIC_LVT_TIMER] & APIC_LVT_MASKED)) {
1454	LogFlow(("apic_timer: trigger irq\n"));
1455	apic_set_irq(pDev, pApic, pApic->lvt[APIC_LVT_TIMER] & 0xff, APIC_TRIGGER_EDGE);
1456
1457	if ( (pApic->lvt[APIC_LVT_TIMER] & APIC_LVT_TIMER_PERIODIC)
1458	&& pApic->initial_count > 0) {
1459	/* new interval. */
1460	pApic->next_time += (((uint64_t)pApic->initial_count + 1) << pApic->count_shift);
1461	TMTimerSet(pApic->CTX_SUFF(pTimer), pApic->next_time);
1462	pApic->fTimerArmed = true;
1463	apicDoFrequencyHinting(pApic);
1464	Log2(("apicTimerCallback: ic=%#x sh=%#x nxt=%#llx\n", pApic->initial_count, pApic->count_shift, pApic->next_time));
1465	} else {
1466	/* single shot or disabled. */
1467	pApic->fTimerArmed = false;
1468	pApic->uHintedCountShift = pApic->uHintedInitialCount = 0;
1469	}
1470	} else {
1471	/* masked, do not rearm. */
1472	pApic->fTimerArmed = false;
1473	pApic->uHintedCountShift = pApic->uHintedInitialCount = 0;
1474	}
1475	}
1476	# endif /* IN_RING3 */
1477
1478	static uint32_t apic_mem_readl(APICDeviceInfo* pDev, APICState *s, RTGCPHYS addr)
1479	{
1480	uint32_t val;
1481	int index;
1482
1483	index = (addr >> 4) & 0xff;
1484
1485	switch(index) {
1486	case 0x02: /* id */
1487	val = s->id << 24;
1488	break;
1489	case 0x03: /* version */
1490	val = APIC_HW_VERSION \| ((APIC_LVT_NB - 1) << 16);
1491	break;
1492	case 0x08:
1493	val = s->tpr;
1494	break;
1495	case 0x09:
1496	val = apic_get_arb_pri(s);
1497	break;
1498	case 0x0a:
1499	/* ppr */
1500	val = apic_get_ppr(s);
1501	break;
1502	case 0x0b:
1503	Log(("apic_mem_readl %x %x -> write only returning 0\n", addr, index));
1504	val = 0;
1505	break;
1506	case 0x0d:
1507	val = s->log_dest << 24;
1508	break;
1509	case 0x0e:
1510	/* Bottom 28 bits are always 1 */
1511	val = (s->dest_mode << 28) \| 0xfffffff;
1512	break;
1513	case 0x0f:
1514	val = s->spurious_vec;
1515	break;
1516	case 0x10: case 0x11: case 0x12: case 0x13: case 0x14: case 0x15: case 0x16: case 0x17:
1517	val = s->isr[index & 7];
1518	break;
1519	case 0x18: case 0x19: case 0x1a: case 0x1b: case 0x1c: case 0x1d: case 0x1e: case 0x1f:
1520	val = s->tmr[index & 7];
1521	break;
1522	case 0x20: case 0x21: case 0x22: case 0x23: case 0x24: case 0x25: case 0x26: case 0x27:
1523	val = s->irr[index & 7];
1524	break;
1525	case 0x28:
1526	val = s->esr;
1527	break;
1528	case 0x30:
1529	case 0x31:
1530	val = s->icr[index & 1];
1531	break;
1532	case 0x32: case 0x33: case 0x34: case 0x35: case 0x36: case 0x37:
1533	val = s->lvt[index - 0x32];
1534	break;
1535	case 0x38:
1536	val = s->initial_count;
1537	break;
1538	case 0x39:
1539	val = apic_get_current_count(pDev, s);
1540	break;
1541	case 0x3e:
1542	val = s->divide_conf;
1543	break;
1544	case 0x2f:
1545	/**
1546	* Correctable machine check exception vector, @todo: implement me!
1547	*/
1548	default:
1549	AssertMsgFailed(("apic_mem_readl: unknown index %x\n", index));
1550	s->esr \|= ESR_ILLEGAL_ADDRESS;
1551	val = 0;
1552	break;
1553	}
1554	#ifdef DEBUG_APIC
1555	Log(("CPU%d: APIC read: %08x = %08x\n", s->phys_id, (uint32_t)addr, val));
1556	#endif
1557	return val;
1558	}
1559
1560	#ifdef IN_RING3
1561
1562	static void apic_save(SSMHANDLE* f, void *opaque)
1563	{
1564	APICState s = (APICState)opaque;
1565	int i;
1566
1567	SSMR3PutU32(f, s->apicbase);
1568	SSMR3PutU32(f, s->id);
1569	SSMR3PutU32(f, s->phys_id);
1570	SSMR3PutU32(f, s->arb_id);
1571	SSMR3PutU32(f, s->tpr);
1572	SSMR3PutU32(f, s->spurious_vec);
1573	SSMR3PutU8(f, s->log_dest);
1574	SSMR3PutU8(f, s->dest_mode);
1575	for (i = 0; i < 8; i++) {
1576	SSMR3PutU32(f, s->isr[i]);
1577	SSMR3PutU32(f, s->tmr[i]);
1578	SSMR3PutU32(f, s->irr[i]);
1579	}
1580	for (i = 0; i < APIC_LVT_NB; i++) {
1581	SSMR3PutU32(f, s->lvt[i]);
1582	}
1583	SSMR3PutU32(f, s->esr);
1584	SSMR3PutU32(f, s->icr[0]);
1585	SSMR3PutU32(f, s->icr[1]);
1586	SSMR3PutU32(f, s->divide_conf);
1587	SSMR3PutU32(f, s->count_shift);
1588	SSMR3PutU32(f, s->initial_count);
1589	SSMR3PutU64(f, s->initial_count_load_time);
1590	SSMR3PutU64(f, s->next_time);
1591
1592	TMR3TimerSave(s->CTX_SUFF(pTimer), f);
1593	}
1594
1595	static int apic_load(SSMHANDLE f, void opaque, int version_id)
1596	{
1597	APICState s = (APICState)opaque;
1598	int i;
1599
1600	/* XXX: what if the base changes? (registered memory regions) */
1601	SSMR3GetU32(f, &s->apicbase);
1602
1603	switch (version_id)
1604	{
1605	case APIC_SAVED_STATE_VERSION_ANCIENT:
1606	{
1607	uint8_t val = 0;
1608	SSMR3GetU8(f, &val);
1609	s->id = val;
1610	/* UP only in old saved states */
1611	s->phys_id = 0;
1612	SSMR3GetU8(f, &val);
1613	s->arb_id = val;
1614	break;
1615	}
1616	case APIC_SAVED_STATE_VERSION:
1617	case APIC_SAVED_STATE_VERSION_VBOX_30:
1618	SSMR3GetU32(f, &s->id);
1619	SSMR3GetU32(f, &s->phys_id);
1620	SSMR3GetU32(f, &s->arb_id);
1621	break;
1622	default:
1623	return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
1624	}
1625	SSMR3GetU32(f, &s->tpr);
1626	SSMR3GetU32(f, &s->spurious_vec);
1627	SSMR3GetU8(f, &s->log_dest);
1628	SSMR3GetU8(f, &s->dest_mode);
1629	for (i = 0; i < 8; i++) {
1630	SSMR3GetU32(f, &s->isr[i]);
1631	SSMR3GetU32(f, &s->tmr[i]);
1632	SSMR3GetU32(f, &s->irr[i]);
1633	}
1634	for (i = 0; i < APIC_LVT_NB; i++) {
1635	SSMR3GetU32(f, &s->lvt[i]);
1636	}
1637	SSMR3GetU32(f, &s->esr);
1638	SSMR3GetU32(f, &s->icr[0]);
1639	SSMR3GetU32(f, &s->icr[1]);
1640	SSMR3GetU32(f, &s->divide_conf);
1641	SSMR3GetU32(f, (uint32_t *)&s->count_shift);
1642	SSMR3GetU32(f, (uint32_t *)&s->initial_count);
1643	SSMR3GetU64(f, (uint64_t *)&s->initial_count_load_time);
1644	SSMR3GetU64(f, (uint64_t *)&s->next_time);
1645
1646	int rc = TMR3TimerLoad(s->CTX_SUFF(pTimer), f);
1647	s->uHintedCountShift = s->uHintedInitialCount = 0;
1648	s->fTimerArmed = TMTimerIsActive(s->CTX_SUFF(pTimer));
1649	if (s->fTimerArmed)
1650	apicDoFrequencyHinting(s);
1651
1652	return VINF_SUCCESS; /** @todo darn mess! */
1653	}
1654
1655	#endif /* IN_RING3 */
1656
1657	/* LAPIC */
1658	PDMBOTHCBDECL(int) apicMMIORead(PPDMDEVINS pDevIns, void pvUser, RTGCPHYS GCPhysAddr, void pv, unsigned cb)
1659	{
1660	APICDeviceInfo pDev = PDMINS_2_DATA(pDevIns, APICDeviceInfo );
1661	APICState *s = getLapic(pDev);
1662
1663	Log(("CPU%d: apicMMIORead at %llx\n", s->phys_id, (uint64_t)GCPhysAddr));
1664
1665	/** @todo: add LAPIC range validity checks (different LAPICs can theoretically have
1666	different physical addresses, see #3092) */
1667
1668	STAM_COUNTER_INC(&CTXSUFF(pDev->StatMMIORead));
1669	switch (cb)
1670	{
1671	case 1:
1672	(uint8_t )pv = 0;
1673	break;
1674
1675	case 2:
1676	(uint16_t )pv = 0;
1677	break;
1678
1679	case 4:
1680	{
1681	#if 0 /** @note experimental */
1682	#ifndef IN_RING3
1683	uint32_t index = (GCPhysAddr >> 4) & 0xff;
1684
1685	if ( index == 0x08 /* TPR */
1686	&& ++s->cTPRPatchAttempts < APIC_MAX_PATCH_ATTEMPTS)
1687	{
1688	#ifdef IN_RC
1689	pDevIns->pDevHlpGC->pfnPATMSetMMIOPatchInfo(pDevIns, GCPhysAddr, &s->tpr);
1690	#else
1691	RTGCPTR pDevInsGC = PDMINS2DATA_GCPTR(pDevIns);
1692	pDevIns->pHlpR0->pfnPATMSetMMIOPatchInfo(pDevIns, GCPhysAddr, pDevIns + RT_OFFSETOF(APICState, tpr));
1693	#endif
1694	return VINF_PATM_HC_MMIO_PATCH_READ;
1695	}
1696	#endif
1697	#endif /* experimental */
1698	APIC_LOCK(pDev, VINF_IOM_HC_MMIO_READ);
1699	(uint32_t )pv = apic_mem_readl(pDev, s, GCPhysAddr);
1700	APIC_UNLOCK(pDev);
1701	break;
1702	}
1703	default:
1704	AssertReleaseMsgFailed(("cb=%d\n", cb)); /* for now we assume simple accesses. */
1705	return VERR_INTERNAL_ERROR;
1706	}
1707	return VINF_SUCCESS;
1708	}
1709
1710	PDMBOTHCBDECL(int) apicMMIOWrite(PPDMDEVINS pDevIns, void pvUser, RTGCPHYS GCPhysAddr, void const pv, unsigned cb)
1711	{
1712	APICDeviceInfo pDev = PDMINS_2_DATA(pDevIns, APICDeviceInfo );
1713	APICState *s = getLapic(pDev);
1714
1715	Log(("CPU%d: apicMMIOWrite at %llx\n", s->phys_id, (uint64_t)GCPhysAddr));
1716
1717	/** @todo: add LAPIC range validity checks (multiple LAPICs can theoretically have
1718	different physical addresses, see #3092) */
1719
1720	STAM_COUNTER_INC(&CTXSUFF(pDev->StatMMIOWrite));
1721	switch (cb)
1722	{
1723	case 1:
1724	case 2:
1725	/* ignore */
1726	break;
1727
1728	case 4:
1729	/* It does its own locking. */
1730	return apicWriteRegister(pDev, s, (GCPhysAddr >> 4) & 0xff, (uint32_t const )pv,
1731	VINF_IOM_HC_MMIO_WRITE, false /fMsr/);
1732
1733	default:
1734	AssertReleaseMsgFailed(("cb=%d\n", cb)); /* for now we assume simple accesses. */
1735	return VERR_INTERNAL_ERROR;
1736	}
1737	return VINF_SUCCESS;
1738	}
1739
1740	#ifdef IN_RING3
1741
1742	/* Print a 8-dword LAPIC bit map (256 bits). */
1743	static void lapicDumpVec(APICDeviceInfo pDev, APICState lapic, PCDBGFINFOHLP pHlp, unsigned start)
1744	{
1745	unsigned i;
1746	uint32_t val;
1747
1748	for (i = 0; i < 8; ++i)
1749	{
1750	val = apic_mem_readl(pDev, lapic, start + (i << 4));
1751	pHlp->pfnPrintf(pHlp, "%08X", val);
1752	}
1753	pHlp->pfnPrintf(pHlp, "\n");
1754	}
1755
1756	/* Print basic LAPIC state. */
1757	static DECLCALLBACK(void) lapicInfoBasic(APICDeviceInfo pDev, APICState lapic, PCDBGFINFOHLP pHlp)
1758	{
1759	uint32_t val;
1760	unsigned max_lvt;
1761
1762	pHlp->pfnPrintf(pHlp, "Local APIC at %08X:\n", lapic->apicbase);
1763	val = apic_mem_readl(pDev, lapic, 0x20);
1764	pHlp->pfnPrintf(pHlp, " LAPIC ID : %08X\n", val);
1765	pHlp->pfnPrintf(pHlp, " APIC ID = %02X\n", (val >> 24) & 0xff);
1766	val = apic_mem_readl(pDev, lapic, 0x30);
1767	max_lvt = (val >> 16) & 0xff;
1768	pHlp->pfnPrintf(pHlp, " APIC VER : %08X\n", val);
1769	pHlp->pfnPrintf(pHlp, " version = %02X\n", val & 0xff);
1770	pHlp->pfnPrintf(pHlp, " lvts = %d\n", ((val >> 16) & 0xff) + 1);
1771	val = apic_mem_readl(pDev, lapic, 0x80);
1772	pHlp->pfnPrintf(pHlp, " TPR : %08X\n", val);
1773	pHlp->pfnPrintf(pHlp, " task pri = %d/%d\n", (val >> 4) & 0xf, val & 0xf);
1774	val = apic_mem_readl(pDev, lapic, 0xA0);
1775	pHlp->pfnPrintf(pHlp, " PPR : %08X\n", val);
1776	pHlp->pfnPrintf(pHlp, " cpu pri = %d/%d\n", (val >> 4) & 0xf, val & 0xf);
1777	val = apic_mem_readl(pDev, lapic, 0xD0);
1778	pHlp->pfnPrintf(pHlp, " LDR : %08X\n", val);
1779	pHlp->pfnPrintf(pHlp, " log id = %02X\n", (val >> 24) & 0xff);
1780	val = apic_mem_readl(pDev, lapic, 0xE0);
1781	pHlp->pfnPrintf(pHlp, " DFR : %08X\n", val);
1782	val = apic_mem_readl(pDev, lapic, 0xF0);
1783	pHlp->pfnPrintf(pHlp, " SVR : %08X\n", val);
1784	pHlp->pfnPrintf(pHlp, " focus = %s\n", val & (1 << 9) ? "check off" : "check on");
1785	pHlp->pfnPrintf(pHlp, " lapic = %s\n", val & (1 << 8) ? "ENABLED" : "DISABLED");
1786	pHlp->pfnPrintf(pHlp, " vector = %02X\n", val & 0xff);
1787	pHlp->pfnPrintf(pHlp, " ISR : ");
1788	lapicDumpVec(pDev, lapic, pHlp, 0x100);
1789	val = get_highest_priority_int(lapic->isr);
1790	pHlp->pfnPrintf(pHlp, " highest = %02X\n", val == ~0U ? 0 : val);
1791	pHlp->pfnPrintf(pHlp, " IRR : ");
1792	lapicDumpVec(pDev, lapic, pHlp, 0x200);
1793	val = get_highest_priority_int(lapic->irr);
1794	pHlp->pfnPrintf(pHlp, " highest = %02X\n", val == ~0U ? 0 : val);
1795	val = apic_mem_readl(pDev, lapic, 0x320);
1796	}
1797
1798	/* Print the more interesting LAPIC LVT entries. */
1799	static DECLCALLBACK(void) lapicInfoLVT(APICDeviceInfo pDev, APICState lapic, PCDBGFINFOHLP pHlp)
1800	{
1801	uint32_t val;
1802	static const char *dmodes[] = { "Fixed ", "Reserved", "SMI", "Reserved",
1803	"NMI", "INIT", "Reserved", "ExtINT" };
1804
1805	val = apic_mem_readl(pDev, lapic, 0x320);
1806	pHlp->pfnPrintf(pHlp, " LVT Timer : %08X\n", val);
1807	pHlp->pfnPrintf(pHlp, " mode = %s\n", val & (1 << 17) ? "periodic" : "one-shot");
1808	pHlp->pfnPrintf(pHlp, " mask = %d\n", (val >> 16) & 1);
1809	pHlp->pfnPrintf(pHlp, " status = %s\n", val & (1 << 12) ? "pending" : "idle");
1810	pHlp->pfnPrintf(pHlp, " vector = %02X\n", val & 0xff);
1811	val = apic_mem_readl(pDev, lapic, 0x350);
1812	pHlp->pfnPrintf(pHlp, " LVT LINT0 : %08X\n", val);
1813	pHlp->pfnPrintf(pHlp, " mask = %d\n", (val >> 16) & 1);
1814	pHlp->pfnPrintf(pHlp, " trigger = %s\n", val & (1 << 15) ? "level" : "edge");
1815	pHlp->pfnPrintf(pHlp, " rem irr = %d\n", (val >> 14) & 1);
1816	pHlp->pfnPrintf(pHlp, " polarty = %d\n", (val >> 13) & 1);
1817	pHlp->pfnPrintf(pHlp, " status = %s\n", val & (1 << 12) ? "pending" : "idle");
1818	pHlp->pfnPrintf(pHlp, " delivry = %s\n", dmodes[(val >> 8) & 7]);
1819	pHlp->pfnPrintf(pHlp, " vector = %02X\n", val & 0xff);
1820	val = apic_mem_readl(pDev, lapic, 0x360);
1821	pHlp->pfnPrintf(pHlp, " LVT LINT1 : %08X\n", val);
1822	pHlp->pfnPrintf(pHlp, " mask = %d\n", (val >> 16) & 1);
1823	pHlp->pfnPrintf(pHlp, " trigger = %s\n", val & (1 << 15) ? "level" : "edge");
1824	pHlp->pfnPrintf(pHlp, " rem irr = %d\n", (val >> 14) & 1);
1825	pHlp->pfnPrintf(pHlp, " polarty = %d\n", (val >> 13) & 1);
1826	pHlp->pfnPrintf(pHlp, " status = %s\n", val & (1 << 12) ? "pending" : "idle");
1827	pHlp->pfnPrintf(pHlp, " delivry = %s\n", dmodes[(val >> 8) & 7]);
1828	pHlp->pfnPrintf(pHlp, " vector = %02X\n", val & 0xff);
1829	}
1830
1831	/* Print LAPIC timer state. */
1832	static DECLCALLBACK(void) lapicInfoTimer(APICDeviceInfo pDev, APICState lapic, PCDBGFINFOHLP pHlp)
1833	{
1834	uint32_t val;
1835	unsigned divider;
1836
1837	pHlp->pfnPrintf(pHlp, "Local APIC timer:\n");
1838	val = apic_mem_readl(pDev, lapic, 0x380);
1839	pHlp->pfnPrintf(pHlp, " Initial count : %08X\n", val);
1840	val = apic_mem_readl(pDev, lapic, 0x390);
1841	pHlp->pfnPrintf(pHlp, " Current count : %08X\n", val);
1842	val = apic_mem_readl(pDev, lapic, 0x3E0);
1843	pHlp->pfnPrintf(pHlp, " Divide config : %08X\n", val);
1844	divider = ((val >> 1) & 0x04) \| (val & 0x03);
1845	pHlp->pfnPrintf(pHlp, " divider = %d\n", divider == 7 ? 1 : 2 << divider);
1846	}
1847
1848	/**
1849	* Info handler, device version. Dumps Local APIC(s) state according to given argument.
1850	*
1851	* @param pDevIns Device instance which registered the info.
1852	* @param pHlp Callback functions for doing output.
1853	* @param pszArgs Argument string. Optional.
1854	*/
1855	static DECLCALLBACK(void) lapicInfo(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
1856	{
1857	APICDeviceInfo pDev = PDMINS_2_DATA(pDevIns, APICDeviceInfo );
1858	APICState *lapic;
1859
1860	lapic = getLapic(pDev);
1861
1862	if (pszArgs == NULL \|\| !strcmp(pszArgs, "basic"))
1863	{
1864	lapicInfoBasic(pDev, lapic, pHlp);
1865	}
1866	else if (!strcmp(pszArgs, "lvt"))
1867	{
1868	lapicInfoLVT(pDev, lapic, pHlp);
1869	}
1870	else if (!strcmp(pszArgs, "timer"))
1871	{
1872	lapicInfoTimer(pDev, lapic, pHlp);
1873	}
1874	else
1875	{
1876	pHlp->pfnPrintf(pHlp, "Invalid argument. Recognized arguments are 'basic', 'lvt', 'timer'.\n");
1877	}
1878	}
1879
1880	/**
1881	* @copydoc FNSSMDEVLIVEEXEC
1882	*/
1883	static DECLCALLBACK(int) apicLiveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t uPass)
1884	{
1885	APICDeviceInfo pDev = PDMINS_2_DATA(pDevIns, APICDeviceInfo );
1886
1887	SSMR3PutU32( pSSM, pDev->cCpus);
1888	SSMR3PutBool(pSSM, pDev->fIoApic);
1889	SSMR3PutU32( pSSM, pDev->enmVersion);
1890	AssertCompile(PDMAPICVERSION_APIC == 2);
1891
1892	return VINF_SSM_DONT_CALL_AGAIN;
1893	}
1894
1895	/**
1896	* @copydoc FNSSMDEVSAVEEXEC
1897	*/
1898	static DECLCALLBACK(int) apicSaveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
1899	{
1900	APICDeviceInfo pDev = PDMINS_2_DATA(pDevIns, APICDeviceInfo );
1901
1902	/* config */
1903	apicLiveExec(pDevIns, pSSM, SSM_PASS_FINAL);
1904
1905	/* save all APICs data, @todo: is it correct? */
1906	foreach_apic(pDev, 0xffffffff, apic_save(pSSM, apic));
1907
1908	return VINF_SUCCESS;
1909	}
1910
1911	/**
1912	* @copydoc FNSSMDEVLOADEXEC
1913	*/
1914	static DECLCALLBACK(int) apicLoadExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
1915	{
1916	APICDeviceInfo pDev = PDMINS_2_DATA(pDevIns, APICDeviceInfo );
1917
1918	if ( uVersion != APIC_SAVED_STATE_VERSION
1919	&& uVersion != APIC_SAVED_STATE_VERSION_VBOX_30
1920	&& uVersion != APIC_SAVED_STATE_VERSION_ANCIENT)
1921	return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
1922
1923	/* config */
1924	if (uVersion > APIC_SAVED_STATE_VERSION_VBOX_30) {
1925	uint32_t cCpus;
1926	int rc = SSMR3GetU32(pSSM, &cCpus); AssertRCReturn(rc, rc);
1927	if (cCpus != pDev->cCpus)
1928	return SSMR3SetCfgError(pSSM, RT_SRC_POS, N_("Config mismatch - cCpus: saved=%#x config=%#x"), cCpus, pDev->cCpus);
1929	bool fIoApic;
1930	rc = SSMR3GetBool(pSSM, &fIoApic); AssertRCReturn(rc, rc);
1931	if (fIoApic != pDev->fIoApic)
1932	return SSMR3SetCfgError(pSSM, RT_SRC_POS, N_("Config mismatch - fIoApic: saved=%RTbool config=%RTbool"), fIoApic, pDev->fIoApic);
1933	uint32_t uApicVersion;
1934	rc = SSMR3GetU32(pSSM, &uApicVersion); AssertRCReturn(rc, rc);
1935	if (uApicVersion != (uint32_t)pDev->enmVersion)
1936	return SSMR3SetCfgError(pSSM, RT_SRC_POS, N_("Config mismatch - uApicVersion: saved=%#x config=%#x"), uApicVersion, pDev->enmVersion);
1937	}
1938
1939	if (uPass != SSM_PASS_FINAL)
1940	return VINF_SUCCESS;
1941
1942	/* load all APICs data / /* @todo: is it correct? */
1943	APIC_LOCK(pDev, VERR_INTERNAL_ERROR_3);
1944	foreach_apic(pDev, 0xffffffff,
1945	if (apic_load(pSSM, apic, uVersion)) {
1946	AssertFailed();
1947	APIC_UNLOCK(pDev);
1948	return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
1949	}
1950	);
1951	APIC_UNLOCK(pDev);
1952	return VINF_SUCCESS;
1953	}
1954
1955	/**
1956	* @copydoc FNPDMDEVRESET
1957	*/
1958	static DECLCALLBACK(void) apicReset(PPDMDEVINS pDevIns)
1959	{
1960	APICDeviceInfo pDev = PDMINS_2_DATA(pDevIns, APICDeviceInfo );
1961	TMTimerLock(pDev->paLapicsR3[0].pTimerR3, VERR_IGNORED);
1962	APIC_LOCK_VOID(pDev, VERR_IGNORED);
1963
1964	/* Reset all APICs. */
1965	for (VMCPUID i = 0; i < pDev->cCpus; i++) {
1966	APICState *pApic = &pDev->CTX_SUFF(paLapics)[i];
1967	TMTimerStop(pApic->CTX_SUFF(pTimer));
1968
1969	/* Clear LAPIC state as if an INIT IPI was sent. */
1970	apic_init_ipi(pDev, pApic);
1971	/* The IDs are not touched by apic_init_ipi() and must be reset now. */
1972	pApic->arb_id = pApic->id = i;
1973	Assert(pApic->id == pApic->phys_id); /* The two should match again. */
1974	/* Reset should re-enable the APIC, see comment in msi.h */
1975	pApic->apicbase = VBOX_MSI_ADDR_BASE \| MSR_IA32_APICBASE_ENABLE;
1976	if (pApic->phys_id == 0)
1977	pApic->apicbase \|= MSR_IA32_APICBASE_BSP;
1978
1979	/* Clear any pending APIC interrupt action flag. */
1980	cpuClearInterrupt(pDev, pApic);
1981	}
1982	/** @todo r=bird: Why is this done everytime, while the constructor first
1983	* checks the CPUID? Who is right? */
1984	pDev->pApicHlpR3->pfnChangeFeature(pDev->pDevInsR3, pDev->enmVersion);
1985
1986	APIC_UNLOCK(pDev);
1987	TMTimerUnlock(pDev->paLapicsR3[0].pTimerR3);
1988	}
1989
1990	/**
1991	* @copydoc FNPDMDEVRELOCATE
1992	*/
1993	static DECLCALLBACK(void) apicRelocate(PPDMDEVINS pDevIns, RTGCINTPTR offDelta)
1994	{
1995	APICDeviceInfo pDev = PDMINS_2_DATA(pDevIns, APICDeviceInfo );
1996	pDev->pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
1997	pDev->pApicHlpRC = pDev->pApicHlpR3->pfnGetRCHelpers(pDevIns);
1998	pDev->paLapicsRC = MMHyperR3ToRC(PDMDevHlpGetVM(pDevIns), pDev->paLapicsR3);
1999	pDev->pCritSectRC = pDev->pApicHlpR3->pfnGetRCCritSect(pDevIns);
2000	for (uint32_t i = 0; i < pDev->cCpus; i++)
2001	pDev->paLapicsR3[i].pTimerRC = TMTimerRCPtr(pDev->paLapicsR3[i].pTimerR3);
2002	}
2003
2004	DECLINLINE(void) initApicData(APICState* apic, uint8_t id)
2005	{
2006	int i;
2007	memset(apic, 0, sizeof(*apic));
2008
2009	/* See comment in msi.h for LAPIC base info */
2010	apic->apicbase = VBOX_MSI_ADDR_BASE \| MSR_IA32_APICBASE_ENABLE;
2011	/* Mark first CPU as BSP */
2012	if (id == 0)
2013	apic->apicbase \|= MSR_IA32_APICBASE_BSP;
2014	for (i = 0; i < APIC_LVT_NB; i++)
2015	apic->lvt[i] = 1 << 16; /* mask LVT */
2016	apic->spurious_vec = 0xff;
2017	apic->phys_id = apic->id = id;
2018	}
2019
2020	/**
2021	* @copydoc FNPDMDEVCONSTRUCT
2022	*/
2023	static DECLCALLBACK(int) apicConstruct(PPDMDEVINS pDevIns, int iInstance, PCFGMNODE pCfg)
2024	{
2025	PDMAPICREG ApicReg;
2026	int rc;
2027	uint32_t i;
2028	bool fIoApic;
2029	bool fGCEnabled;
2030	bool fR0Enabled;
2031	APICDeviceInfo pDev = PDMINS_2_DATA(pDevIns, APICDeviceInfo );
2032	uint32_t cCpus;
2033
2034	/*
2035	* Only single device instance.
2036	*/
2037	Assert(iInstance == 0);
2038
2039	/*
2040	* Validate configuration.
2041	*/
2042	if (!CFGMR3AreValuesValid(pCfg,
2043	"IOAPIC\0"
2044	"GCEnabled\0"
2045	"R0Enabled\0"
2046	"NumCPUs\0"))
2047	return VERR_PDM_DEVINS_UNKNOWN_CFG_VALUES;
2048
2049	rc = CFGMR3QueryBoolDef(pCfg, "IOAPIC", &fIoApic, true);
2050	if (RT_FAILURE(rc))
2051	return PDMDEV_SET_ERROR(pDevIns, rc,
2052	N_("Configuration error: Failed to read \"IOAPIC\""));
2053
2054	rc = CFGMR3QueryBoolDef(pCfg, "GCEnabled", &fGCEnabled, true);
2055	if (RT_FAILURE(rc))
2056	return PDMDEV_SET_ERROR(pDevIns, rc,
2057	N_("Configuration error: Failed to query boolean value \"GCEnabled\""));
2058
2059	rc = CFGMR3QueryBoolDef(pCfg, "R0Enabled", &fR0Enabled, true);
2060	if (RT_FAILURE(rc))
2061	return PDMDEV_SET_ERROR(pDevIns, rc,
2062	N_("Configuration error: Failed to query boolean value \"R0Enabled\""));
2063
2064	rc = CFGMR3QueryU32Def(pCfg, "NumCPUs", &cCpus, 1);
2065	if (RT_FAILURE(rc))
2066	return PDMDEV_SET_ERROR(pDevIns, rc,
2067	N_("Configuration error: Failed to query integer value \"NumCPUs\""));
2068
2069	Log(("APIC: cCpus=%d fR0Enabled=%RTbool fGCEnabled=%RTbool fIoApic=%RTbool\n", cCpus, fR0Enabled, fGCEnabled, fIoApic));
2070
2071	/** @todo Current implementation is limited to 32 CPUs due to the use of 32
2072	* bits bitmasks. */
2073	if (cCpus > 32)
2074	return PDMDEV_SET_ERROR(pDevIns, rc,
2075	N_("Configuration error: Invalid value for \"NumCPUs\""));
2076
2077	/*
2078	* Init the data.
2079	*/
2080	pDev->pDevInsR3 = pDevIns;
2081	pDev->pDevInsR0 = PDMDEVINS_2_R0PTR(pDevIns);
2082	pDev->pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
2083	pDev->cCpus = cCpus;
2084	pDev->fIoApic = fIoApic;
2085	/* Use PDMAPICVERSION_X2APIC to activate x2APIC mode */
2086	pDev->enmVersion = PDMAPICVERSION_APIC;
2087
2088	/* Disable locking in this device. */
2089	rc = PDMDevHlpSetDeviceCritSect(pDevIns, PDMDevHlpCritSectGetNop(pDevIns));
2090	AssertRCReturn(rc, rc);
2091
2092	PVM pVM = PDMDevHlpGetVM(pDevIns);
2093
2094	/*
2095	* We are not freeing this memory, as it's automatically released when guest exits.
2096	*/
2097	rc = MMHyperAlloc(pVM, cCpus * sizeof(APICState), 1, MM_TAG_PDM_DEVICE_USER, (void **)&pDev->paLapicsR3);
2098	if (RT_FAILURE(rc))
2099	return VERR_NO_MEMORY;
2100	pDev->paLapicsR0 = MMHyperR3ToR0(pVM, pDev->paLapicsR3);
2101	pDev->paLapicsRC = MMHyperR3ToRC(pVM, pDev->paLapicsR3);
2102
2103	for (i = 0; i < cCpus; i++)
2104	initApicData(&pDev->paLapicsR3[i], i);
2105
2106	/*
2107	* Register the APIC.
2108	*/
2109	ApicReg.u32Version = PDM_APICREG_VERSION;
2110	ApicReg.pfnGetInterruptR3 = apicGetInterrupt;
2111	ApicReg.pfnHasPendingIrqR3 = apicHasPendingIrq;
2112	ApicReg.pfnSetBaseR3 = apicSetBase;
2113	ApicReg.pfnGetBaseR3 = apicGetBase;
2114	ApicReg.pfnSetTPRR3 = apicSetTPR;
2115	ApicReg.pfnGetTPRR3 = apicGetTPR;
2116	ApicReg.pfnWriteMSRR3 = apicWriteMSR;
2117	ApicReg.pfnReadMSRR3 = apicReadMSR;
2118	ApicReg.pfnBusDeliverR3 = apicBusDeliverCallback;
2119	ApicReg.pfnLocalInterruptR3 = apicLocalInterrupt;
2120	if (fGCEnabled) {
2121	ApicReg.pszGetInterruptRC = "apicGetInterrupt";
2122	ApicReg.pszHasPendingIrqRC = "apicHasPendingIrq";
2123	ApicReg.pszSetBaseRC = "apicSetBase";
2124	ApicReg.pszGetBaseRC = "apicGetBase";
2125	ApicReg.pszSetTPRRC = "apicSetTPR";
2126	ApicReg.pszGetTPRRC = "apicGetTPR";
2127	ApicReg.pszWriteMSRRC = "apicWriteMSR";
2128	ApicReg.pszReadMSRRC = "apicReadMSR";
2129	ApicReg.pszBusDeliverRC = "apicBusDeliverCallback";
2130	ApicReg.pszLocalInterruptRC = "apicLocalInterrupt";
2131	} else {
2132	ApicReg.pszGetInterruptRC = NULL;
2133	ApicReg.pszHasPendingIrqRC = NULL;
2134	ApicReg.pszSetBaseRC = NULL;
2135	ApicReg.pszGetBaseRC = NULL;
2136	ApicReg.pszSetTPRRC = NULL;
2137	ApicReg.pszGetTPRRC = NULL;
2138	ApicReg.pszWriteMSRRC = NULL;
2139	ApicReg.pszReadMSRRC = NULL;
2140	ApicReg.pszBusDeliverRC = NULL;
2141	ApicReg.pszLocalInterruptRC = NULL;
2142	}
2143	if (fR0Enabled) {
2144	ApicReg.pszGetInterruptR0 = "apicGetInterrupt";
2145	ApicReg.pszHasPendingIrqR0 = "apicHasPendingIrq";
2146	ApicReg.pszSetBaseR0 = "apicSetBase";
2147	ApicReg.pszGetBaseR0 = "apicGetBase";
2148	ApicReg.pszSetTPRR0 = "apicSetTPR";
2149	ApicReg.pszGetTPRR0 = "apicGetTPR";
2150	ApicReg.pszWriteMSRR0 = "apicWriteMSR";
2151	ApicReg.pszReadMSRR0 = "apicReadMSR";
2152	ApicReg.pszBusDeliverR0 = "apicBusDeliverCallback";
2153	ApicReg.pszLocalInterruptR0 = "apicLocalInterrupt";
2154	} else {
2155	ApicReg.pszGetInterruptR0 = NULL;
2156	ApicReg.pszHasPendingIrqR0 = NULL;
2157	ApicReg.pszSetBaseR0 = NULL;
2158	ApicReg.pszGetBaseR0 = NULL;
2159	ApicReg.pszSetTPRR0 = NULL;
2160	ApicReg.pszGetTPRR0 = NULL;
2161	ApicReg.pszWriteMSRR0 = NULL;
2162	ApicReg.pszReadMSRR0 = NULL;
2163	ApicReg.pszBusDeliverR0 = NULL;
2164	ApicReg.pszLocalInterruptR0 = NULL;
2165	}
2166
2167	rc = PDMDevHlpAPICRegister(pDevIns, &ApicReg, &pDev->pApicHlpR3);
2168	AssertLogRelRCReturn(rc, rc);
2169	pDev->pCritSectR3 = pDev->pApicHlpR3->pfnGetR3CritSect(pDevIns);
2170
2171	/*
2172	* The the CPUID feature bit.
2173	*/
2174	/** @todo r=bird: See remark in the apicReset. */
2175	uint32_t u32Eax, u32Ebx, u32Ecx, u32Edx;
2176	PDMDevHlpGetCpuId(pDevIns, 0, &u32Eax, &u32Ebx, &u32Ecx, &u32Edx);
2177	if (u32Eax >= 1) {
2178	if ( fIoApic /* If IOAPIC is enabled, enable Local APIC in any case */
2179	\|\| ( u32Ebx == X86_CPUID_VENDOR_INTEL_EBX
2180	&& u32Ecx == X86_CPUID_VENDOR_INTEL_ECX
2181	&& u32Edx == X86_CPUID_VENDOR_INTEL_EDX /* GenuineIntel */)
2182	\|\| ( u32Ebx == X86_CPUID_VENDOR_AMD_EBX
2183	&& u32Ecx == X86_CPUID_VENDOR_AMD_ECX
2184	&& u32Edx == X86_CPUID_VENDOR_AMD_EDX /* AuthenticAMD */)) {
2185	LogRel(("Activating Local APIC\n"));
2186	pDev->pApicHlpR3->pfnChangeFeature(pDevIns, pDev->enmVersion);
2187	}
2188	}
2189
2190	/*
2191	* Register the MMIO range.
2192	* @todo: shall reregister, if base changes.
2193	*/
2194	uint32_t ApicBase = pDev->paLapicsR3[0].apicbase & ~0xfff;
2195	rc = PDMDevHlpMMIORegister(pDevIns, ApicBase, 0x1000, pDev,
2196	apicMMIOWrite, apicMMIORead, NULL, "APIC Memory");
2197	if (RT_FAILURE(rc))
2198	return rc;
2199
2200	if (fGCEnabled) {
2201	pDev->pApicHlpRC = pDev->pApicHlpR3->pfnGetRCHelpers(pDevIns);
2202	pDev->pCritSectRC = pDev->pApicHlpR3->pfnGetRCCritSect(pDevIns);
2203
2204	rc = PDMDevHlpMMIORegisterRC(pDevIns, ApicBase, 0x1000, 0,
2205	"apicMMIOWrite", "apicMMIORead", NULL);
2206	if (RT_FAILURE(rc))
2207	return rc;
2208	}
2209
2210	if (fR0Enabled) {
2211	pDev->pApicHlpR0 = pDev->pApicHlpR3->pfnGetR0Helpers(pDevIns);
2212	pDev->pCritSectR0 = pDev->pApicHlpR3->pfnGetR0CritSect(pDevIns);
2213
2214	rc = PDMDevHlpMMIORegisterR0(pDevIns, ApicBase, 0x1000, 0,
2215	"apicMMIOWrite", "apicMMIORead", NULL);
2216	if (RT_FAILURE(rc))
2217	return rc;
2218	}
2219
2220	/*
2221	* Create the APIC timers.
2222	*/
2223	for (i = 0; i < cCpus; i++) {
2224	APICState *pApic = &pDev->paLapicsR3[i];
2225	pApic->pszDesc = MMR3HeapAPrintf(pVM, MM_TAG_PDM_DEVICE_USER, "APIC Timer #%u", i);
2226	rc = PDMDevHlpTMTimerCreate(pDevIns, TMCLOCK_VIRTUAL_SYNC, apicTimerCallback, pApic,
2227	TMTIMER_FLAGS_NO_CRIT_SECT, pApic->pszDesc, &pApic->pTimerR3);
2228	if (RT_FAILURE(rc))
2229	return rc;
2230	pApic->pTimerR0 = TMTimerR0Ptr(pApic->pTimerR3);
2231	pApic->pTimerRC = TMTimerRCPtr(pApic->pTimerR3);
2232	TMR3TimerSetCritSect(pApic->pTimerR3, pDev->pCritSectR3);
2233	}
2234
2235	/*
2236	* Saved state.
2237	*/
2238	rc = PDMDevHlpSSMRegister3(pDevIns, APIC_SAVED_STATE_VERSION, sizeof(*pDev),
2239	apicLiveExec, apicSaveExec, apicLoadExec);
2240	if (RT_FAILURE(rc))
2241	return rc;
2242
2243	/*
2244	* Register debugger info callback.
2245	*/
2246	PDMDevHlpDBGFInfoRegister(pDevIns, "lapic", "Display Local APIC state for current CPU. "
2247	"Recognizes 'basic', 'lvt', 'timer' as arguments, defaulting to 'basic'.", lapicInfo);
2248
2249	#ifdef VBOX_WITH_STATISTICS
2250	/*
2251	* Statistics.
2252	*/
2253	PDMDevHlpSTAMRegister(pDevIns, &pDev->StatMMIOReadGC, STAMTYPE_COUNTER, "/Devices/APIC/MMIOReadGC", STAMUNIT_OCCURENCES, "Number of APIC MMIO reads in GC.");
2254	PDMDevHlpSTAMRegister(pDevIns, &pDev->StatMMIOReadHC, STAMTYPE_COUNTER, "/Devices/APIC/MMIOReadHC", STAMUNIT_OCCURENCES, "Number of APIC MMIO reads in HC.");
2255	PDMDevHlpSTAMRegister(pDevIns, &pDev->StatMMIOWriteGC, STAMTYPE_COUNTER, "/Devices/APIC/MMIOWriteGC", STAMUNIT_OCCURENCES, "Number of APIC MMIO writes in GC.");
2256	PDMDevHlpSTAMRegister(pDevIns, &pDev->StatMMIOWriteHC, STAMTYPE_COUNTER, "/Devices/APIC/MMIOWriteHC", STAMUNIT_OCCURENCES, "Number of APIC MMIO writes in HC.");
2257	PDMDevHlpSTAMRegister(pDevIns, &pDev->StatClearedActiveIrq,STAMTYPE_COUNTER, "/Devices/APIC/MaskedActiveIRQ", STAMUNIT_OCCURENCES, "Number of cleared irqs.");
2258	for (i = 0; i < cCpus; i++) {
2259	APICState *pApic = &pDev->paLapicsR3[i];
2260	PDMDevHlpSTAMRegisterF(pDevIns, &pApic->StatTimerSetInitialCount, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, "Calls to apicTimerSetInitialCount.", "/Devices/APIC/%u/TimerSetInitialCount", i);
2261	PDMDevHlpSTAMRegisterF(pDevIns, &pApic->StatTimerSetInitialCountArm, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, "TMTimerSetRelative calls.", "/Devices/APIC/%u/TimerSetInitialCount/Arm", i);
2262	PDMDevHlpSTAMRegisterF(pDevIns, &pApic->StatTimerSetInitialCountDisarm, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, "TMTimerStop calls.", "/Devices/APIC/%u/TimerSetInitialCount/Disasm", i);
2263	PDMDevHlpSTAMRegisterF(pDevIns, &pApic->StatTimerSetLvt, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, "Calls to apicTimerSetLvt.", "/Devices/APIC/%u/TimerSetLvt", i);
2264	PDMDevHlpSTAMRegisterF(pDevIns, &pApic->StatTimerSetLvtClearPeriodic, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, "Clearing APIC_LVT_TIMER_PERIODIC.", "/Devices/APIC/%u/TimerSetLvt/ClearPeriodic", i);
2265	PDMDevHlpSTAMRegisterF(pDevIns, &pApic->StatTimerSetLvtPostponed, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, "TMTimerStop postponed.", "/Devices/APIC/%u/TimerSetLvt/Postponed", i);
2266	PDMDevHlpSTAMRegisterF(pDevIns, &pApic->StatTimerSetLvtArmed, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, "TMTimerSet avoided.", "/Devices/APIC/%u/TimerSetLvt/Armed", i);
2267	PDMDevHlpSTAMRegisterF(pDevIns, &pApic->StatTimerSetLvtArm, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, "TMTimerSet necessary.", "/Devices/APIC/%u/TimerSetLvt/Arm", i);
2268	PDMDevHlpSTAMRegisterF(pDevIns, &pApic->StatTimerSetLvtArmRetries, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, "TMTimerSet retries.", "/Devices/APIC/%u/TimerSetLvt/ArmRetries", i);
2269	PDMDevHlpSTAMRegisterF(pDevIns, &pApic->StatTimerSetLvtNoRelevantChange,STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, "No relevant flags changed.", "/Devices/APIC/%u/TimerSetLvt/NoRelevantChange", i);
2270	}
2271	#endif
2272
2273	return VINF_SUCCESS;
2274	}
2275
2276
2277	/**
2278	* APIC device registration structure.
2279	*/
2280	const PDMDEVREG g_DeviceAPIC =
2281	{
2282	/* u32Version */
2283	PDM_DEVREG_VERSION,
2284	/* szName */
2285	"apic",
2286	/* szRCMod */
2287	"VBoxDD2GC.gc",
2288	/* szR0Mod */
2289	"VBoxDD2R0.r0",
2290	/* pszDescription */
2291	"Advanced Programmable Interrupt Controller (APIC) Device",
2292	/* fFlags */
2293	PDM_DEVREG_FLAGS_HOST_BITS_DEFAULT \| PDM_DEVREG_FLAGS_GUEST_BITS_32_64 \| PDM_DEVREG_FLAGS_PAE36 \| PDM_DEVREG_FLAGS_RC \| PDM_DEVREG_FLAGS_R0,
2294	/* fClass */
2295	PDM_DEVREG_CLASS_PIC,
2296	/* cMaxInstances */
2297	1,
2298	/* cbInstance */
2299	sizeof(APICState),
2300	/* pfnConstruct */
2301	apicConstruct,
2302	/* pfnDestruct */
2303	NULL,
2304	/* pfnRelocate */
2305	apicRelocate,
2306	/* pfnIOCtl */
2307	NULL,
2308	/* pfnPowerOn */
2309	NULL,
2310	/* pfnReset */
2311	apicReset,
2312	/* pfnSuspend */
2313	NULL,
2314	/* pfnResume */
2315	NULL,
2316	/* pfnAttach */
2317	NULL,
2318	/* pfnDetach */
2319	NULL,
2320	/* pfnQueryInterface. */
2321	NULL,
2322	/* pfnInitComplete */
2323	NULL,
2324	/* pfnPowerOff */
2325	NULL,
2326	/* pfnSoftReset */
2327	NULL,
2328	/* u32VersionEnd */
2329	PDM_DEVREG_VERSION
2330	};
2331
2332	#endif /* IN_RING3 */
2333	#endif /* !VBOX_DEVICE_STRUCT_TESTCASE */
2334

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source: vbox/trunk/src/VBox/Devices/PC/DevAPIC.cpp@ 37636

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