DevAPIC.cpp@ 34906

Last change on this file since 34906 was 33595, checked in by vboxsync, 14 years ago
src/*: more spelling fixes (logging), thanks Timeless!
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1	/* $Id: DevAPIC.cpp 33595 2010-10-29 10:35:00Z vboxsync $ */
2	/** @file
3	* Advanced Programmable Interrupt Controller (APIC) Device and
4	* I/O Advanced Programmable Interrupt Controller (IO-APIC) Device.
5	*/
6
7	/*
8	* Copyright (C) 2006-2010 Oracle Corporation
9	*
10	* This file is part of VirtualBox Open Source Edition (OSE), as
11	* available from http://www.virtualbox.org. This file is free software;
12	* you can redistribute it and/or modify it under the terms of the GNU
13	* General Public License (GPL) as published by the Free Software
14	* Foundation, in version 2 as it comes in the "COPYING" file of the
15	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
16	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
17	* --------------------------------------------------------------------
18	*
19	* This code is based on:
20	*
21	* apic.c revision 1.5 @@OSETODO
22	*/
23
24	/*******************************************************************************
25	* Header Files *
26	*******************************************************************************/
27	#define LOG_GROUP LOG_GROUP_DEV_APIC
28	#include <VBox/pdmdev.h>
29
30	#include <VBox/log.h>
31	#include <VBox/stam.h>
32	#include <iprt/assert.h>
33	#include <iprt/asm.h>
34
35	#include <VBox/msi.h>
36
37	#include "Builtins2.h"
38
39	#define MSR_IA32_APICBASE 0x1b
40	#define MSR_IA32_APICBASE_BSP (1<<8)
41	#define MSR_IA32_APICBASE_ENABLE (1<<11)
42	#define MSR_IA32_APICBASE_X2ENABLE (1<<10)
43	#define MSR_IA32_APICBASE_BASE (0xfffff<<12)
44
45	#ifdef _MSC_VER
46	# pragma warning(disable:4244)
47	#endif
48
49	/** The current saved state version.*/
50	#define APIC_SAVED_STATE_VERSION 3
51	/** The saved state version used by VirtualBox v3 and earlier.
52	* This does not include the config. */
53	#define APIC_SAVED_STATE_VERSION_VBOX_30 2
54	/** Some ancient version... */
55	#define APIC_SAVED_STATE_VERSION_ANCIENT 1
56
57	/* version 0x14: Pentium 4, Xeon; LVT count depends on that */
58	#define APIC_HW_VERSION 0x14
59
60	/** @def APIC_LOCK
61	* Acquires the PDM lock. */
62	#define APIC_LOCK(pThis, rcBusy) \
63	do { \
64	int rc2 = PDMCritSectEnter((pThis)->CTX_SUFF(pCritSect), (rcBusy)); \
65	if (rc2 != VINF_SUCCESS) \
66	return rc2; \
67	} while (0)
68
69	/** @def APIC_LOCK_VOID
70	* Acquires the PDM lock and does not expect failure (i.e. ring-3 only!). */
71	#define APIC_LOCK_VOID(pThis, rcBusy) \
72	do { \
73	int rc2 = PDMCritSectEnter((pThis)->CTX_SUFF(pCritSect), (rcBusy)); \
74	AssertLogRelRCReturnVoid(rc2); \
75	} while (0)
76
77	/** @def APIC_UNLOCK
78	* Releases the PDM lock. */
79	#define APIC_UNLOCK(pThis) \
80	PDMCritSectLeave((pThis)->CTX_SUFF(pCritSect))
81
82	/** @def IOAPIC_LOCK
83	* Acquires the PDM lock. */
84	#define IOAPIC_LOCK(pThis, rc) \
85	do { \
86	int rc2 = (pThis)->CTX_SUFF(pIoApicHlp)->pfnLock((pThis)->CTX_SUFF(pDevIns), rc); \
87	if (rc2 != VINF_SUCCESS) \
88	return rc2; \
89	} while (0)
90
91	/** @def IOAPIC_UNLOCK
92	* Releases the PDM lock. */
93	#define IOAPIC_UNLOCK(pThis) (pThis)->CTX_SUFF(pIoApicHlp)->pfnUnlock((pThis)->CTX_SUFF(pDevIns))
94
95
96	#define foreach_apic(dev, mask, code) \
97	do { \
98	uint32_t i; \
99	APICState *apic = (dev)->CTX_SUFF(paLapics); \
100	for (i = 0; i < (dev)->cCpus; i++) \
101	{ \
102	if (mask & (1 << (apic->id))) \
103	{ \
104	code; \
105	} \
106	apic++; \
107	} \
108	} while (0)
109
110	# define set_bit(pvBitmap, iBit) ASMBitSet(pvBitmap, iBit)
111	# define reset_bit(pvBitmap, iBit) ASMBitClear(pvBitmap, iBit)
112	# define fls_bit(value) (ASMBitLastSetU32(value) - 1)
113	# define ffs_bit(value) (ASMBitFirstSetU32(value) - 1)
114
115	/*
116	* APIC support
117	*
118	* Copyright (c) 2004-2005 Fabrice Bellard
119	*
120	* This library is free software; you can redistribute it and/or
121	* modify it under the terms of the GNU Lesser General Public
122	* License as published by the Free Software Foundation; either
123	* version 2 of the License, or (at your option) any later version.
124	*
125	* This library is distributed in the hope that it will be useful,
126	* but WITHOUT ANY WARRANTY; without even the implied warranty of
127	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
128	* Lesser General Public License for more details.
129	*
130	* You should have received a copy of the GNU Lesser General Public
131	* License along with this library; if not, write to the Free Software
132	* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
133	*/
134	#define DEBUG_APIC
135	#define DEBUG_IOAPIC
136
137	/* APIC Local Vector Table */
138	#define APIC_LVT_TIMER 0
139	#define APIC_LVT_THERMAL 1
140	#define APIC_LVT_PERFORM 2
141	#define APIC_LVT_LINT0 3
142	#define APIC_LVT_LINT1 4
143	#define APIC_LVT_ERROR 5
144	#define APIC_LVT_NB 6
145
146	/* APIC delivery modes */
147	#define APIC_DM_FIXED 0
148	#define APIC_DM_LOWPRI 1
149	#define APIC_DM_SMI 2
150	#define APIC_DM_NMI 4
151	#define APIC_DM_INIT 5
152	#define APIC_DM_SIPI 6
153	#define APIC_DM_EXTINT 7
154
155	/* APIC destination mode */
156	#define APIC_DESTMODE_FLAT 0xf
157	#define APIC_DESTMODE_CLUSTER 0x0
158
159	#define APIC_TRIGGER_EDGE 0
160	#define APIC_TRIGGER_LEVEL 1
161
162	#define APIC_LVT_TIMER_PERIODIC (1<<17)
163	#define APIC_LVT_MASKED (1<<16)
164	#define APIC_LVT_LEVEL_TRIGGER (1<<15)
165	#define APIC_LVT_REMOTE_IRR (1<<14)
166	#define APIC_INPUT_POLARITY (1<<13)
167	#define APIC_SEND_PENDING (1<<12)
168
169	#define IOAPIC_NUM_PINS 0x18
170
171	#define ESR_ILLEGAL_ADDRESS (1 << 7)
172
173	#define APIC_SV_ENABLE (1 << 8)
174
175	#define APIC_MAX_PATCH_ATTEMPTS 100
176
177	typedef uint32_t PhysApicId;
178	typedef uint32_t LogApicId;
179
180	typedef struct APICState {
181	uint32_t apicbase;
182	/* Task priority register (interrupt level) */
183	uint32_t tpr;
184	/* Logical APIC id - user programmable */
185	LogApicId id;
186	/* Physical APIC id - not visible to user, constant */
187	PhysApicId phys_id;
188	/** @todo: is it logical or physical? Not really used anyway now. */
189	PhysApicId arb_id;
190	uint32_t spurious_vec;
191	uint8_t log_dest;
192	uint8_t dest_mode;
193	uint32_t isr[8]; /* in service register */
194	uint32_t tmr[8]; /* trigger mode register */
195	uint32_t irr[8]; /* interrupt request register */
196	uint32_t lvt[APIC_LVT_NB];
197	uint32_t esr; /* error register */
198	uint32_t icr[2];
199	uint32_t divide_conf;
200	int count_shift;
201	uint32_t initial_count;
202	uint32_t Alignment0;
203
204	/** The time stamp of the initial_count load, i.e. when it was started. */
205	uint64_t initial_count_load_time;
206	/** The time stamp of the next timer callback. */
207	uint64_t next_time;
208	/** The APIC timer - R3 Ptr. */
209	PTMTIMERR3 pTimerR3;
210	/** The APIC timer - R0 Ptr. */
211	PTMTIMERR0 pTimerR0;
212	/** The APIC timer - RC Ptr. */
213	PTMTIMERRC pTimerRC;
214	/** Whether the timer is armed or not */
215	bool fTimerArmed;
216	/** Alignment */
217	bool afAlignment[3];
218	/** The initial_count value used for the current frequency hint. */
219	uint32_t uHintedInitialCount;
220	/** The count_shift value used for the current frequency hint. */
221	uint32_t uHintedCountShift;
222	/** Timer description timer. */
223	R3PTRTYPE(char *) pszDesc;
224	# ifdef VBOX_WITH_STATISTICS
225	# if HC_ARCH_BITS == 32
226	uint32_t u32Alignment0;
227	# endif
228	STAMCOUNTER StatTimerSetInitialCount;
229	STAMCOUNTER StatTimerSetInitialCountArm;
230	STAMCOUNTER StatTimerSetInitialCountDisarm;
231	STAMCOUNTER StatTimerSetLvt;
232	STAMCOUNTER StatTimerSetLvtClearPeriodic;
233	STAMCOUNTER StatTimerSetLvtPostponed;
234	STAMCOUNTER StatTimerSetLvtArmed;
235	STAMCOUNTER StatTimerSetLvtArm;
236	STAMCOUNTER StatTimerSetLvtArmRetries;
237	STAMCOUNTER StatTimerSetLvtNoRelevantChange;
238	# endif
239
240	} APICState;
241
242	AssertCompileMemberAlignment(APICState, initial_count_load_time, 8);
243	# ifdef VBOX_WITH_STATISTICS
244	AssertCompileMemberAlignment(APICState, StatTimerSetInitialCount, 8);
245	# endif
246
247	struct IOAPICState {
248	uint8_t id;
249	uint8_t ioregsel;
250
251	uint32_t irr;
252	uint64_t ioredtbl[IOAPIC_NUM_PINS];
253
254	/** The device instance - R3 Ptr. */
255	PPDMDEVINSR3 pDevInsR3;
256	/** The IOAPIC helpers - R3 Ptr. */
257	PCPDMIOAPICHLPR3 pIoApicHlpR3;
258
259	/** The device instance - R0 Ptr. */
260	PPDMDEVINSR0 pDevInsR0;
261	/** The IOAPIC helpers - R0 Ptr. */
262	PCPDMIOAPICHLPR0 pIoApicHlpR0;
263
264	/** The device instance - RC Ptr. */
265	PPDMDEVINSRC pDevInsRC;
266	/** The IOAPIC helpers - RC Ptr. */
267	PCPDMIOAPICHLPRC pIoApicHlpRC;
268
269	# ifdef VBOX_WITH_STATISTICS
270	STAMCOUNTER StatMMIOReadGC;
271	STAMCOUNTER StatMMIOReadHC;
272	STAMCOUNTER StatMMIOWriteGC;
273	STAMCOUNTER StatMMIOWriteHC;
274	STAMCOUNTER StatSetIrqGC;
275	STAMCOUNTER StatSetIrqHC;
276	# endif
277	};
278
279	typedef struct IOAPICState IOAPICState;
280
281	typedef struct
282	{
283	/** The device instance - R3 Ptr. */
284	PPDMDEVINSR3 pDevInsR3;
285	/** The APIC helpers - R3 Ptr. */
286	PCPDMAPICHLPR3 pApicHlpR3;
287	/** LAPICs states - R3 Ptr */
288	R3PTRTYPE(APICState *) paLapicsR3;
289	/** The critical section - R3 Ptr. */
290	R3PTRTYPE(PPDMCRITSECT) pCritSectR3;
291
292	/** The device instance - R0 Ptr. */
293	PPDMDEVINSR0 pDevInsR0;
294	/** The APIC helpers - R0 Ptr. */
295	PCPDMAPICHLPR0 pApicHlpR0;
296	/** LAPICs states - R0 Ptr */
297	R0PTRTYPE(APICState *) paLapicsR0;
298	/** The critical section - R3 Ptr. */
299	R0PTRTYPE(PPDMCRITSECT) pCritSectR0;
300
301	/** The device instance - RC Ptr. */
302	PPDMDEVINSRC pDevInsRC;
303	/** The APIC helpers - RC Ptr. */
304	PCPDMAPICHLPRC pApicHlpRC;
305	/** LAPICs states - RC Ptr */
306	RCPTRTYPE(APICState *) paLapicsRC;
307	/** The critical section - R3 Ptr. */
308	RCPTRTYPE(PPDMCRITSECT) pCritSectRC;
309
310	/** APIC specification version in this virtual hardware configuration. */
311	PDMAPICVERSION enmVersion;
312
313	/** Number of attempts made to optimize TPR accesses. */
314	uint32_t cTPRPatchAttempts;
315
316	/** Number of CPUs on the system (same as LAPIC count). */
317	uint32_t cCpus;
318	/** Whether we've got an IO APIC or not. */
319	bool fIoApic;
320	/** Alignment padding. */
321	bool afPadding[3];
322
323	# ifdef VBOX_WITH_STATISTICS
324	STAMCOUNTER StatMMIOReadGC;
325	STAMCOUNTER StatMMIOReadHC;
326	STAMCOUNTER StatMMIOWriteGC;
327	STAMCOUNTER StatMMIOWriteHC;
328	STAMCOUNTER StatClearedActiveIrq;
329	# endif
330	} APICDeviceInfo;
331	# ifdef VBOX_WITH_STATISTICS
332	AssertCompileMemberAlignment(APICDeviceInfo, StatMMIOReadGC, 8);
333	# endif
334
335	#ifndef VBOX_DEVICE_STRUCT_TESTCASE
336
337	/*******************************************************************************
338	* Internal Functions *
339	*******************************************************************************/
340	RT_C_DECLS_BEGIN
341	PDMBOTHCBDECL(int) apicMMIORead(PPDMDEVINS pDevIns, void pvUser, RTGCPHYS GCPhysAddr, void pv, unsigned cb);
342	PDMBOTHCBDECL(int) apicMMIOWrite(PPDMDEVINS pDevIns, void pvUser, RTGCPHYS GCPhysAddr, void pv, unsigned cb);
343	PDMBOTHCBDECL(int) apicGetInterrupt(PPDMDEVINS pDevIns);
344	PDMBOTHCBDECL(bool) apicHasPendingIrq(PPDMDEVINS pDevIns);
345	PDMBOTHCBDECL(void) apicSetBase(PPDMDEVINS pDevIns, uint64_t val);
346	PDMBOTHCBDECL(uint64_t) apicGetBase(PPDMDEVINS pDevIns);
347	PDMBOTHCBDECL(void) apicSetTPR(PPDMDEVINS pDevIns, VMCPUID idCpu, uint8_t val);
348	PDMBOTHCBDECL(uint8_t) apicGetTPR(PPDMDEVINS pDevIns, VMCPUID idCpu);
349	PDMBOTHCBDECL(int) apicBusDeliverCallback(PPDMDEVINS pDevIns, uint8_t u8Dest, uint8_t u8DestMode,
350	uint8_t u8DeliveryMode, uint8_t iVector, uint8_t u8Polarity,
351	uint8_t u8TriggerMode);
352	PDMBOTHCBDECL(int) apicLocalInterrupt(PPDMDEVINS pDevIns, uint8_t u8Pin, uint8_t u8Level);
353	PDMBOTHCBDECL(int) apicWriteMSR(PPDMDEVINS pDevIns, VMCPUID iCpu, uint32_t u32Reg, uint64_t u64Value);
354	PDMBOTHCBDECL(int) apicReadMSR(PPDMDEVINS pDevIns, VMCPUID iCpu, uint32_t u32Reg, uint64_t *pu64Value);
355	PDMBOTHCBDECL(int) ioapicMMIORead(PPDMDEVINS pDevIns, void pvUser, RTGCPHYS GCPhysAddr, void pv, unsigned cb);
356	PDMBOTHCBDECL(int) ioapicMMIOWrite(PPDMDEVINS pDevIns, void pvUser, RTGCPHYS GCPhysAddr, void pv, unsigned cb);
357	PDMBOTHCBDECL(void) ioapicSetIrq(PPDMDEVINS pDevIns, int iIrq, int iLevel);
358	PDMBOTHCBDECL(void) ioapicSendMsi(PPDMDEVINS pDevIns, RTGCPHYS GCAddr, uint32_t uValue);
359
360	static void apic_update_tpr(APICDeviceInfo dev, APICState s, uint32_t val);
361	RT_C_DECLS_END
362
363	static void apic_eoi(APICDeviceInfo dev, APICState s); /* */
364	static uint32_t apic_get_delivery_bitmask(APICDeviceInfo* dev, uint8_t dest, uint8_t dest_mode);
365	static int apic_deliver(APICDeviceInfo* dev, APICState *s,
366	uint8_t dest, uint8_t dest_mode,
367	uint8_t delivery_mode, uint8_t vector_num,
368	uint8_t polarity, uint8_t trigger_mode);
369	static int apic_get_arb_pri(APICState *s);
370	static int apic_get_ppr(APICState *s);
371	static uint32_t apic_get_current_count(APICDeviceInfo* dev, APICState *s);
372	static void apicTimerSetInitialCount(APICDeviceInfo dev, APICState s, uint32_t initial_count);
373	static void apicTimerSetLvt(APICDeviceInfo dev, APICState pThis, uint32_t fNew);
374	static void apicSendInitIpi(APICDeviceInfo* dev, APICState *s);
375
376	static void apic_init_ipi(APICDeviceInfo* dev, APICState *s);
377	static void apic_set_irq(APICDeviceInfo* dev, APICState *s, int vector_num, int trigger_mode);
378	static bool apic_update_irq(APICDeviceInfo* dev, APICState *s);
379
380
381	DECLINLINE(APICState) getLapicById(APICDeviceInfo dev, VMCPUID id)
382	{
383	AssertFatalMsg(id < dev->cCpus, ("CPU id %d out of range\n", id));
384	return &dev->CTX_SUFF(paLapics)[id];
385	}
386
387	DECLINLINE(APICState) getLapic(APICDeviceInfo dev)
388	{
389	/* LAPIC's array is indexed by CPU id */
390	VMCPUID id = dev->CTX_SUFF(pApicHlp)->pfnGetCpuId(dev->CTX_SUFF(pDevIns));
391	return getLapicById(dev, id);
392	}
393
394	DECLINLINE(VMCPUID) getCpuFromLapic(APICDeviceInfo* dev, APICState *s)
395	{
396	/* for now we assume LAPIC physical id == CPU id */
397	return VMCPUID(s->phys_id);
398	}
399
400	DECLINLINE(void) cpuSetInterrupt(APICDeviceInfo* dev, APICState *s, PDMAPICIRQ enmType = PDMAPICIRQ_HARDWARE)
401	{
402	LogFlow(("apic: setting interrupt flag for cpu %d\n", getCpuFromLapic(dev, s)));
403	dev->CTX_SUFF(pApicHlp)->pfnSetInterruptFF(dev->CTX_SUFF(pDevIns), enmType,
404	getCpuFromLapic(dev, s));
405	}
406
407	DECLINLINE(void) cpuClearInterrupt(APICDeviceInfo* dev, APICState *s, PDMAPICIRQ enmType = PDMAPICIRQ_HARDWARE)
408	{
409	LogFlow(("apic: clear interrupt flag\n"));
410	dev->CTX_SUFF(pApicHlp)->pfnClearInterruptFF(dev->CTX_SUFF(pDevIns), enmType,
411	getCpuFromLapic(dev, s));
412	}
413
414	# ifdef IN_RING3
415
416	DECLINLINE(void) cpuSendSipi(APICDeviceInfo* dev, APICState *s, int vector)
417	{
418	Log2(("apic: send SIPI vector=%d\n", vector));
419
420	dev->pApicHlpR3->pfnSendSipi(dev->pDevInsR3,
421	getCpuFromLapic(dev, s),
422	vector);
423	}
424
425	DECLINLINE(void) cpuSendInitIpi(APICDeviceInfo* dev, APICState *s)
426	{
427	Log2(("apic: send init IPI\n"));
428
429	dev->pApicHlpR3->pfnSendInitIpi(dev->pDevInsR3,
430	getCpuFromLapic(dev, s));
431	}
432
433	# endif /* IN_RING3 */
434
435	DECLINLINE(uint32_t) getApicEnableBits(APICDeviceInfo* dev)
436	{
437	switch (dev->enmVersion)
438	{
439	case PDMAPICVERSION_NONE:
440	return 0;
441	case PDMAPICVERSION_APIC:
442	return MSR_IA32_APICBASE_ENABLE;
443	case PDMAPICVERSION_X2APIC:
444	return MSR_IA32_APICBASE_ENABLE \| MSR_IA32_APICBASE_X2ENABLE ;
445	default:
446	AssertMsgFailed(("Unsupported APIC version %d\n", dev->enmVersion));
447	return 0;
448	}
449	}
450
451	DECLINLINE(PDMAPICVERSION) getApicMode(APICState *apic)
452	{
453	switch (((apic->apicbase) >> 10) & 0x3)
454	{
455	case 0:
456	return PDMAPICVERSION_NONE;
457	case 1:
458	default:
459	/* Invalid */
460	return PDMAPICVERSION_NONE;
461	case 2:
462	return PDMAPICVERSION_APIC;
463	case 3:
464	return PDMAPICVERSION_X2APIC;
465	}
466	}
467
468	static int apic_bus_deliver(APICDeviceInfo* dev,
469	uint32_t deliver_bitmask, uint8_t delivery_mode,
470	uint8_t vector_num, uint8_t polarity,
471	uint8_t trigger_mode)
472	{
473	LogFlow(("apic_bus_deliver mask=%x mode=%x vector=%x polarity=%x trigger_mode=%x\n", deliver_bitmask, delivery_mode, vector_num, polarity, trigger_mode));
474	switch (delivery_mode) {
475	case APIC_DM_LOWPRI:
476	{
477	int d = -1;
478	if (deliver_bitmask)
479	d = ffs_bit(deliver_bitmask);
480	if (d >= 0)
481	{
482	APICState* apic = getLapicById(dev, d);
483	apic_set_irq(dev, apic, vector_num, trigger_mode);
484	}
485	return VINF_SUCCESS;
486	}
487	case APIC_DM_FIXED:
488	/* XXX: arbitration */
489	break;
490
491	case APIC_DM_SMI:
492	foreach_apic(dev, deliver_bitmask,
493	cpuSetInterrupt(dev, apic, PDMAPICIRQ_SMI));
494	return VINF_SUCCESS;
495
496	case APIC_DM_NMI:
497	foreach_apic(dev, deliver_bitmask,
498	cpuSetInterrupt(dev, apic, PDMAPICIRQ_NMI));
499	return VINF_SUCCESS;
500
501	case APIC_DM_INIT:
502	/* normal INIT IPI sent to processors */
503	#ifdef IN_RING3
504	foreach_apic(dev, deliver_bitmask,
505	apicSendInitIpi(dev, apic));
506	return VINF_SUCCESS;
507	#else
508	/* We shall send init IPI only in R3, R0 calls should be
509	rescheduled to R3 */
510	return VINF_IOM_HC_MMIO_READ_WRITE;
511	#endif /* IN_RING3 */
512	case APIC_DM_EXTINT:
513	/* handled in I/O APIC code */
514	break;
515
516	default:
517	return VINF_SUCCESS;
518	}
519
520	foreach_apic(dev, deliver_bitmask,
521	apic_set_irq (dev, apic, vector_num, trigger_mode));
522	return VINF_SUCCESS;
523	}
524
525
526	PDMBOTHCBDECL(void) apicSetBase(PPDMDEVINS pDevIns, uint64_t val)
527	{
528	APICDeviceInfo dev = PDMINS_2_DATA(pDevIns, APICDeviceInfo );
529	Assert(PDMCritSectIsOwner(dev->CTX_SUFF(pCritSect)));
530	APICState s = getLapic(dev); /* @todo fix interface */
531	Log(("apicSetBase: %016RX64\n", val));
532
533	/** @todo: do we need to lock here ? */
534	/* APIC_LOCK_VOID(dev, VERR_INTERNAL_ERROR); */
535	/** @todo If this change is valid immediately, then we should change the MMIO registration! */
536	/* We cannot change if this CPU is BSP or not by writing to MSR - it's hardwired */
537	PDMAPICVERSION oldMode = getApicMode(s);
538	s->apicbase =
539	(val & 0xfffff000) \| /* base */
540	(val & getApicEnableBits(dev)) \| /* mode */
541	(s->apicbase & MSR_IA32_APICBASE_BSP) /* keep BSP bit */;
542	PDMAPICVERSION newMode = getApicMode(s);
543
544	if (oldMode != newMode)
545	{
546	switch (newMode)
547	{
548	case PDMAPICVERSION_NONE:
549	{
550	s->spurious_vec &= ~APIC_SV_ENABLE;
551	/* Clear any pending APIC interrupt action flag. */
552	cpuClearInterrupt(dev, s);
553	/** @todo: why do we do that? */
554	dev->CTX_SUFF(pApicHlp)->pfnChangeFeature(pDevIns, PDMAPICVERSION_NONE);
555	break;
556	}
557	case PDMAPICVERSION_APIC:
558	/** @todo: map MMIO ranges, if needed */
559	break;
560	case PDMAPICVERSION_X2APIC:
561	/** @todo: unmap MMIO ranges of this APIC, according to the spec */
562	break;
563	default:
564	break;
565	}
566	}
567	/* APIC_UNLOCK(dev); */
568	}
569
570	PDMBOTHCBDECL(uint64_t) apicGetBase(PPDMDEVINS pDevIns)
571	{
572	APICDeviceInfo dev = PDMINS_2_DATA(pDevIns, APICDeviceInfo );
573	Assert(PDMCritSectIsOwner(dev->CTX_SUFF(pCritSect)));
574	APICState s = getLapic(dev); /* @todo fix interface */
575	LogFlow(("apicGetBase: %016llx\n", (uint64_t)s->apicbase));
576	return s->apicbase;
577	}
578
579	PDMBOTHCBDECL(void) apicSetTPR(PPDMDEVINS pDevIns, VMCPUID idCpu, uint8_t val)
580	{
581	APICDeviceInfo dev = PDMINS_2_DATA(pDevIns, APICDeviceInfo );
582	Assert(PDMCritSectIsOwner(dev->CTX_SUFF(pCritSect)));
583	APICState *s = getLapicById(dev, idCpu);
584	LogFlow(("apicSetTPR: val=%#x (trp %#x -> %#x)\n", val, s->tpr, val));
585	apic_update_tpr(dev, s, val);
586	}
587
588	PDMBOTHCBDECL(uint8_t) apicGetTPR(PPDMDEVINS pDevIns, VMCPUID idCpu)
589	{
590	/* We don't perform any locking here as that would cause a lot of contention for VT-x/AMD-V. */
591	APICDeviceInfo dev = PDMINS_2_DATA(pDevIns, APICDeviceInfo );
592	APICState *s = getLapicById(dev, idCpu);
593	Log2(("apicGetTPR: returns %#x\n", s->tpr));
594	return s->tpr;
595	}
596
597	/**
598	* x2APIC MSR write interface.
599	*
600	* @returns VBox status code.
601	*
602	* @param pDevIns The device instance.
603	* @param idCpu The ID of the virtual CPU and thereby APIC index.
604	* @param u32Reg Register to write (ecx).
605	* @param u64Value The value to write (eax:edx / rax).
606	*
607	*/
608	PDMBOTHCBDECL(int) apicWriteMSR(PPDMDEVINS pDevIns, VMCPUID idCpu, uint32_t u32Reg, uint64_t u64Value)
609	{
610	APICDeviceInfo dev = PDMINS_2_DATA(pDevIns, APICDeviceInfo );
611	Assert(PDMCritSectIsOwner(dev->CTX_SUFF(pCritSect)));
612	int rc = VINF_SUCCESS;
613
614	if (dev->enmVersion < PDMAPICVERSION_X2APIC)
615	return VERR_EM_INTERPRETER;
616
617	APICState *pThis = getLapicById(dev, idCpu);
618
619	uint32_t index = (u32Reg - MSR_IA32_APIC_START) & 0xff;
620	switch (index)
621	{
622	case 0x02:
623	pThis->id = (u64Value >> 24);
624	break;
625	case 0x03:
626	break;
627	case 0x08:
628	apic_update_tpr(dev, pThis, u64Value);
629	break;
630	case 0x09: case 0x0a:
631	Log(("apicWriteMSR: write to read-only register %d ignored\n", index));
632	break;
633	case 0x0b: /* EOI */
634	apic_eoi(dev, pThis);
635	break;
636	case 0x0d:
637	pThis->log_dest = u64Value >> 24;
638	break;
639	case 0x0e:
640	pThis->dest_mode = u64Value >> 28;
641	break;
642	case 0x0f:
643	pThis->spurious_vec = u64Value & 0x1ff;
644	apic_update_irq(dev, pThis);
645	break;
646	case 0x10: case 0x11: case 0x12: case 0x13: case 0x14: case 0x15: case 0x16: case 0x17:
647	case 0x18: case 0x19: case 0x1a: case 0x1b: case 0x1c: case 0x1d: case 0x1e: case 0x1f:
648	case 0x20: case 0x21: case 0x22: case 0x23: case 0x24: case 0x25: case 0x26: case 0x27:
649	case 0x28:
650	Log(("apicWriteMSR: write to read-only register %d ignored\n", index));
651	break;
652
653	case 0x30:
654	/* Here one of the differences with regular APIC: ICR is single 64-bit register */
655	pThis->icr[0] = (uint32_t)u64Value;
656	pThis->icr[1] = (uint32_t)(u64Value >> 32);
657	rc = apic_deliver(dev, pThis, (pThis->icr[1] >> 24) & 0xff, (pThis->icr[0] >> 11) & 1,
658	(pThis->icr[0] >> 8) & 7, (pThis->icr[0] & 0xff),
659	(pThis->icr[0] >> 14) & 1, (pThis->icr[0] >> 15) & 1);
660	break;
661	case 0x32 + APIC_LVT_TIMER:
662	AssertCompile(APIC_LVT_TIMER == 0);
663	apicTimerSetLvt(dev, pThis, u64Value);
664	break;
665
666	case 0x33: case 0x34: case 0x35: case 0x36: case 0x37:
667	pThis->lvt[index - 0x32] = u64Value;
668	break;
669	case 0x38:
670	apicTimerSetInitialCount(dev, pThis, u64Value);
671	break;
672	case 0x39:
673	Log(("apicWriteMSR: write to read-only register %d ignored\n", index));
674	break;
675	case 0x3e:
676	{
677	int v;
678	pThis->divide_conf = u64Value & 0xb;
679	v = (pThis->divide_conf & 3) \| ((pThis->divide_conf >> 1) & 4);
680	pThis->count_shift = (v + 1) & 7;
681	break;
682	}
683	case 0x3f:
684	{
685	/* Self IPI, see x2APIC book 2.4.5 */
686	int vector = u64Value & 0xff;
687	rc = apic_bus_deliver(dev,
688	1 << getLapicById(dev, idCpu)->id /* Self */,
689	0 /* Delivery mode - fixed */,
690	vector,
691	0 /* Polarity - conform to the bus */,
692	0 /* Trigger mode - edge */);
693	break;
694	}
695	default:
696	AssertMsgFailed(("apicWriteMSR: unknown index %x\n", index));
697	pThis->esr \|= ESR_ILLEGAL_ADDRESS;
698	break;
699	}
700
701	return rc;
702	}
703
704	/**
705	* x2APIC MSR read interface.
706	*
707	* @returns VBox status code.
708	*
709	* @param pDevIns The device instance.
710	* @param idCpu The ID of the virtual CPU and thereby APIC index.
711	* @param u32Reg Register to write (ecx).
712	* @param pu64Value Where to return the value (eax:edx / rax).
713	*/
714	PDMBOTHCBDECL(int) apicReadMSR(PPDMDEVINS pDevIns, VMCPUID idCpu, uint32_t u32Reg, uint64_t *pu64Value)
715	{
716	APICDeviceInfo dev = PDMINS_2_DATA(pDevIns, APICDeviceInfo );
717	Assert(PDMCritSectIsOwner(dev->CTX_SUFF(pCritSect)));
718
719	if (dev->enmVersion < PDMAPICVERSION_X2APIC)
720	return VERR_EM_INTERPRETER;
721
722	uint32_t index = (u32Reg - MSR_IA32_APIC_START) & 0xff;
723	APICState* apic = getLapicById(dev, idCpu);
724	uint64_t val = 0;
725
726	switch (index)
727	{
728	case 0x02: /* id */
729	val = apic->id << 24;
730	break;
731	case 0x03: /* version */
732	val = APIC_HW_VERSION \|
733	((APIC_LVT_NB - 1) << 16) /* Max LVT index */ \|
734	(0 << 24) /* Support for EOI broadcast suppression */;
735	break;
736	case 0x08:
737	val = apic->tpr;
738	break;
739	case 0x09:
740	val = apic_get_arb_pri(apic);
741	break;
742	case 0x0a:
743	/* ppr */
744	val = apic_get_ppr(apic);
745	break;
746	case 0x0b:
747	val = 0;
748	break;
749	case 0x0d:
750	val = (uint64_t)apic->log_dest << 24;
751	break;
752	case 0x0e:
753	/* Bottom 28 bits are always 1 */
754	val = ((uint64_t)apic->dest_mode << 28) \| 0xfffffff;
755	break;
756	case 0x0f:
757	val = apic->spurious_vec;
758	break;
759	case 0x10: case 0x11: case 0x12: case 0x13: case 0x14: case 0x15: case 0x16: case 0x17:
760	val = apic->isr[index & 7];
761	break;
762	case 0x18: case 0x19: case 0x1a: case 0x1b: case 0x1c: case 0x1d: case 0x1e: case 0x1f:
763	val = apic->tmr[index & 7];
764	break;
765	case 0x20: case 0x21: case 0x22: case 0x23: case 0x24: case 0x25: case 0x26: case 0x27:
766	val = apic->irr[index & 7];
767	break;
768	case 0x28:
769	val = apic->esr;
770	break;
771	case 0x30:
772	/* Here one of the differences with regular APIC: ICR is single 64-bit register */
773	val = ((uint64_t)apic->icr[1] << 32) \| apic->icr[0];
774	break;
775	case 0x32: case 0x33: case 0x34: case 0x35: case 0x36: case 0x37:
776	val = apic->lvt[index - 0x32];
777	break;
778	case 0x38:
779	val = apic->initial_count;
780	break;
781	case 0x39:
782	val = apic_get_current_count(dev, apic);
783	break;
784	case 0x3e:
785	val = apic->divide_conf;
786	break;
787	case 0x3f:
788	/* Self IPI register is write only */
789	Log(("apicReadMSR: read from write-only register %d ignored\n", index));
790	break;
791	case 0x2f:
792	/**
793	* Correctable machine check exception vector, @todo: implement me!
794	*/
795	default:
796	AssertMsgFailed(("apicReadMSR: unknown index %x\n", index));
797	/**
798	* @todo: according to spec when APIC writes to ESR it msut raise error interrupt,
799	* i.e. LVT[5]
800	*/
801	apic->esr \|= ESR_ILLEGAL_ADDRESS;
802	val = 0;
803	break;
804	}
805	*pu64Value = val;
806	return VINF_SUCCESS;
807	}
808
809	/**
810	* More or less private interface between IOAPIC, only PDM is responsible
811	* for connecting the two devices.
812	*/
813	PDMBOTHCBDECL(int) apicBusDeliverCallback(PPDMDEVINS pDevIns, uint8_t u8Dest, uint8_t u8DestMode,
814	uint8_t u8DeliveryMode, uint8_t iVector, uint8_t u8Polarity,
815	uint8_t u8TriggerMode)
816	{
817	APICDeviceInfo dev = PDMINS_2_DATA(pDevIns, APICDeviceInfo );
818	Assert(PDMCritSectIsOwner(dev->CTX_SUFF(pCritSect)));
819	LogFlow(("apicBusDeliverCallback: pDevIns=%p u8Dest=%#x u8DestMode=%#x u8DeliveryMode=%#x iVector=%#x u8Polarity=%#x u8TriggerMode=%#x\n",
820	pDevIns, u8Dest, u8DestMode, u8DeliveryMode, iVector, u8Polarity, u8TriggerMode));
821	return apic_bus_deliver(dev, apic_get_delivery_bitmask(dev, u8Dest, u8DestMode),
822	u8DeliveryMode, iVector, u8Polarity, u8TriggerMode);
823	}
824
825	/**
826	* Local interrupt delivery, for devices attached to the CPU's LINT0/LINT1 pin.
827	* Normally used for 8259A PIC and NMI.
828	*/
829	PDMBOTHCBDECL(int) apicLocalInterrupt(PPDMDEVINS pDevIns, uint8_t u8Pin, uint8_t u8Level)
830	{
831	APICDeviceInfo dev = PDMINS_2_DATA(pDevIns, APICDeviceInfo );
832	APICState *s = getLapicById(dev, 0);
833
834	Assert(PDMCritSectIsOwner(dev->CTX_SUFF(pCritSect)));
835	LogFlow(("apicLocalInterrupt: pDevIns=%p u8Pin=%x u8Level=%x\n", pDevIns, u8Pin, u8Level));
836
837	/* If LAPIC is disabled, go straight to the CPU. */
838	if (!(s->spurious_vec & APIC_SV_ENABLE))
839	{
840	LogFlow(("apicLocalInterrupt: LAPIC disabled, delivering directly to CPU core.\n"));
841	if (u8Level)
842	cpuSetInterrupt(dev, s, PDMAPICIRQ_EXTINT);
843	else
844	cpuClearInterrupt(dev, s, PDMAPICIRQ_EXTINT);
845
846	return VINF_SUCCESS;
847	}
848
849	/* If LAPIC is enabled, interrupts are subject to LVT programming. */
850
851	/* There are only two local interrupt pins. */
852	AssertMsgReturn(u8Pin <= 1, ("Invalid LAPIC pin %d\n", u8Pin), VERR_INVALID_PARAMETER);
853
854	/* NB: We currently only deliver local interrupts to the first CPU. In theory they
855	* should be delivered to all CPUs and it is the guest's responsibility to ensure
856	* no more than one CPU has the interrupt unmasked.
857	*/
858	uint32_t u32Lvec;
859
860	u32Lvec = s->lvt[APIC_LVT_LINT0 + u8Pin]; /* Fetch corresponding LVT entry. */
861	/* Drop int if entry is masked. May not be correct for level-triggered interrupts. */
862	if (!(u32Lvec & APIC_LVT_MASKED))
863	{ uint8_t u8Delivery;
864	PDMAPICIRQ enmType;
865
866	u8Delivery = (u32Lvec >> 8) & 7;
867	switch (u8Delivery)
868	{
869	case APIC_DM_EXTINT:
870	Assert(u8Pin == 0); /* PIC should be wired to LINT0. */
871	enmType = PDMAPICIRQ_EXTINT;
872	/* ExtINT can be both set and cleared, NMI/SMI/INIT can only be set. */
873	LogFlow(("apicLocalInterrupt: %s ExtINT interrupt\n", u8Level ? "setting" : "clearing"));
874	if (u8Level)
875	cpuSetInterrupt(dev, s, enmType);
876	else
877	cpuClearInterrupt(dev, s, enmType);
878	return VINF_SUCCESS;
879	case APIC_DM_NMI:
880	/* External NMI should be wired to LINT1, but Linux sometimes programs
881	* LVT0 to NMI delivery mode as well.
882	*/
883	enmType = PDMAPICIRQ_NMI;
884	/* Currently delivering NMIs through here causes problems with NMI watchdogs
885	* on certain Linux kernels, e.g. 64-bit CentOS 5.3. Disable NMIs for now.
886	*/
887	return VINF_SUCCESS;
888	case APIC_DM_SMI:
889	enmType = PDMAPICIRQ_SMI;
890	break;
891	case APIC_DM_FIXED:
892	{
893	/** @todo implement APIC_DM_FIXED! */
894	static unsigned s_c = 0;
895	if (s_c++ < 5)
896	LogRel(("delivery type APIC_DM_FIXED not implemented. u8Pin=%d u8Level=%d\n", u8Pin, u8Level));
897	return VINF_SUCCESS;
898	}
899	case APIC_DM_INIT:
900	/** @todo implement APIC_DM_INIT? */
901	default:
902	{
903	static unsigned s_c = 0;
904	if (s_c++ < 100)
905	AssertLogRelMsgFailed(("delivery type %d not implemented. u8Pin=%d u8Level=%d\n", u8Delivery, u8Pin, u8Level));
906	return VERR_INTERNAL_ERROR_4;
907	}
908	}
909	LogFlow(("apicLocalInterrupt: setting local interrupt type %d\n", enmType));
910	cpuSetInterrupt(dev, s, enmType);
911	}
912	return VINF_SUCCESS;
913	}
914
915	/* return -1 if no bit is set */
916	static int get_highest_priority_int(uint32_t *tab)
917	{
918	int i;
919	for(i = 7; i >= 0; i--) {
920	if (tab[i] != 0) {
921	return i * 32 + fls_bit(tab[i]);
922	}
923	}
924	return -1;
925	}
926
927	static int apic_get_ppr(APICState *s)
928	{
929	int tpr, isrv, ppr;
930
931	tpr = (s->tpr >> 4);
932	isrv = get_highest_priority_int(s->isr);
933	if (isrv < 0)
934	isrv = 0;
935	isrv >>= 4;
936	if (tpr >= isrv)
937	ppr = s->tpr;
938	else
939	ppr = isrv << 4;
940	return ppr;
941	}
942
943	static int apic_get_ppr_zero_tpr(APICState *s)
944	{
945	int isrv;
946
947	isrv = get_highest_priority_int(s->isr);
948	if (isrv < 0)
949	isrv = 0;
950	return isrv;
951	}
952
953	static int apic_get_arb_pri(APICState *s)
954	{
955	/* XXX: arbitration */
956	return 0;
957	}
958
959	/* signal the CPU if an irq is pending */
960	static bool apic_update_irq(APICDeviceInfo dev, APICState s)
961	{
962	int irrv, ppr;
963	if (!(s->spurious_vec & APIC_SV_ENABLE))
964	{
965	/* Clear any pending APIC interrupt action flag. */
966	cpuClearInterrupt(dev, s);
967	return false;
968	}
969
970	irrv = get_highest_priority_int(s->irr);
971	if (irrv < 0)
972	return false;
973	ppr = apic_get_ppr(s);
974	if (ppr && (irrv & 0xf0) <= (ppr & 0xf0))
975	return false;
976	cpuSetInterrupt(dev, s);
977	return true;
978	}
979
980	/* Check if the APIC has a pending interrupt/if a TPR change would active one. */
981	PDMBOTHCBDECL(bool) apicHasPendingIrq(PPDMDEVINS pDevIns)
982	{
983	int irrv, ppr;
984	APICDeviceInfo dev = PDMINS_2_DATA(pDevIns, APICDeviceInfo );
985	if (!dev)
986	return false;
987
988	/* We don't perform any locking here as that would cause a lot of contention for VT-x/AMD-V. */
989
990	APICState s = getLapic(dev); /* @todo fix interface */
991
992	/*
993	* All our callbacks now come from single IOAPIC, thus locking
994	* seems to be excessive now (@todo: check)
995	*/
996	irrv = get_highest_priority_int(s->irr);
997	if (irrv < 0)
998	return false;
999
1000	ppr = apic_get_ppr_zero_tpr(s);
1001
1002	if (ppr && (irrv & 0xf0) <= (ppr & 0xf0))
1003	return false;
1004
1005	return true;
1006	}
1007
1008	static void apic_update_tpr(APICDeviceInfo dev, APICState s, uint32_t val)
1009	{
1010	bool fIrqIsActive = false;
1011	bool fIrqWasActive = false;
1012
1013	fIrqWasActive = apic_update_irq(dev, s);
1014	s->tpr = val;
1015	fIrqIsActive = apic_update_irq(dev, s);
1016
1017	/* If an interrupt is pending and now masked, then clear the FF flag. */
1018	if (fIrqWasActive && !fIrqIsActive)
1019	{
1020	Log(("apic_update_tpr: deactivate interrupt that was masked by the TPR update (%x)\n", val));
1021	STAM_COUNTER_INC(&dev->StatClearedActiveIrq);
1022	cpuClearInterrupt(dev, s);
1023	}
1024	}
1025
1026	static void apic_set_irq(APICDeviceInfo dev, APICState s, int vector_num, int trigger_mode)
1027	{
1028	LogFlow(("CPU%d: apic_set_irq vector=%x, trigger_mode=%x\n", s->phys_id, vector_num, trigger_mode));
1029	set_bit(s->irr, vector_num);
1030	if (trigger_mode)
1031	set_bit(s->tmr, vector_num);
1032	else
1033	reset_bit(s->tmr, vector_num);
1034	apic_update_irq(dev, s);
1035	}
1036
1037	static void apic_eoi(APICDeviceInfo dev, APICState s)
1038	{
1039	int isrv;
1040	isrv = get_highest_priority_int(s->isr);
1041	if (isrv < 0)
1042	return;
1043	reset_bit(s->isr, isrv);
1044	LogFlow(("CPU%d: apic_eoi isrv=%x\n", s->phys_id, isrv));
1045	/* XXX: send the EOI packet to the APIC bus to allow the I/O APIC to
1046	set the remote IRR bit for level triggered interrupts. */
1047	apic_update_irq(dev, s);
1048	}
1049
1050	static uint32_t apic_get_delivery_bitmask(APICDeviceInfo *dev, uint8_t dest, uint8_t dest_mode)
1051	{
1052	uint32_t mask = 0;
1053
1054	if (dest_mode == 0)
1055	{
1056	if (dest == 0xff)
1057	mask = 0xff;
1058	else
1059	mask = 1 << dest;
1060	}
1061	else
1062	{
1063	APICState *apic = dev->CTX_SUFF(paLapics);
1064	uint32_t i;
1065
1066	/* XXX: cluster mode */
1067	for(i = 0; i < dev->cCpus; i++)
1068	{
1069	if (apic->dest_mode == APIC_DESTMODE_FLAT)
1070	{
1071	if (dest & apic->log_dest)
1072	mask \|= (1 << i);
1073	}
1074	else if (apic->dest_mode == APIC_DESTMODE_CLUSTER)
1075	{
1076	if ((dest & 0xf0) == (apic->log_dest & 0xf0)
1077	&&
1078	(dest & apic->log_dest & 0x0f))
1079	{
1080	mask \|= (1 << i);
1081	}
1082	}
1083	apic++;
1084	}
1085	}
1086
1087	return mask;
1088	}
1089
1090	#ifdef IN_RING3
1091	static void apic_init_ipi(APICDeviceInfo* dev, APICState *s)
1092	{
1093	int i;
1094
1095	for(i = 0; i < APIC_LVT_NB; i++)
1096	s->lvt[i] = 1 << 16; /* mask LVT */
1097	s->tpr = 0;
1098	s->spurious_vec = 0xff;
1099	s->log_dest = 0;
1100	s->dest_mode = 0xff;
1101	memset(s->isr, 0, sizeof(s->isr));
1102	memset(s->tmr, 0, sizeof(s->tmr));
1103	memset(s->irr, 0, sizeof(s->irr));
1104	s->esr = 0;
1105	memset(s->icr, 0, sizeof(s->icr));
1106	s->divide_conf = 0;
1107	s->count_shift = 1;
1108	s->initial_count = 0;
1109	s->initial_count_load_time = 0;
1110	s->next_time = 0;
1111	}
1112
1113
1114	static void apicSendInitIpi(APICDeviceInfo* dev, APICState *s)
1115	{
1116	apic_init_ipi(dev, s);
1117	cpuSendInitIpi(dev, s);
1118	}
1119
1120	/* send a SIPI message to the CPU to start it */
1121	static void apic_startup(APICDeviceInfo* dev, APICState *s, int vector_num)
1122	{
1123	Log(("[SMP] apic_startup: %d on CPUs %d\n", vector_num, s->phys_id));
1124	cpuSendSipi(dev, s, vector_num);
1125	}
1126	#endif /* IN_RING3 */
1127
1128	static int apic_deliver(APICDeviceInfo* dev, APICState *s,
1129	uint8_t dest, uint8_t dest_mode,
1130	uint8_t delivery_mode, uint8_t vector_num,
1131	uint8_t polarity, uint8_t trigger_mode)
1132	{
1133	uint32_t deliver_bitmask = 0;
1134	int dest_shorthand = (s->icr[0] >> 18) & 3;
1135
1136	LogFlow(("apic_deliver dest=%x dest_mode=%x dest_shorthand=%x delivery_mode=%x vector_num=%x polarity=%x trigger_mode=%x\n", dest, dest_mode, dest_shorthand, delivery_mode, vector_num, polarity, trigger_mode));
1137
1138	switch (dest_shorthand) {
1139	case 0:
1140	deliver_bitmask = apic_get_delivery_bitmask(dev, dest, dest_mode);
1141	break;
1142	case 1:
1143	deliver_bitmask = (1 << s->id);
1144	break;
1145	case 2:
1146	deliver_bitmask = 0xffffffff;
1147	break;
1148	case 3:
1149	deliver_bitmask = 0xffffffff & ~(1 << s->id);
1150	break;
1151	}
1152
1153	switch (delivery_mode) {
1154	case APIC_DM_INIT:
1155	{
1156	int trig_mode = (s->icr[0] >> 15) & 1;
1157	int level = (s->icr[0] >> 14) & 1;
1158	if (level == 0 && trig_mode == 1) {
1159	foreach_apic(dev, deliver_bitmask,
1160	apic->arb_id = apic->id);
1161	Log(("CPU%d: APIC_DM_INIT arbitration id(s) set\n", s->phys_id));
1162	return VINF_SUCCESS;
1163	}
1164	}
1165	break;
1166
1167	case APIC_DM_SIPI:
1168	# ifdef IN_RING3
1169	foreach_apic(dev, deliver_bitmask,
1170	apic_startup(dev, apic, vector_num));
1171	return VINF_SUCCESS;
1172	# else
1173	/* We shall send SIPI only in R3, R0 calls should be
1174	rescheduled to R3 */
1175	return VINF_IOM_HC_MMIO_WRITE;
1176	# endif
1177	}
1178
1179	return apic_bus_deliver(dev, deliver_bitmask, delivery_mode, vector_num,
1180	polarity, trigger_mode);
1181	}
1182
1183
1184	PDMBOTHCBDECL(int) apicGetInterrupt(PPDMDEVINS pDevIns)
1185	{
1186	APICDeviceInfo dev = PDMINS_2_DATA(pDevIns, APICDeviceInfo );
1187	/* if the APIC is not installed or enabled, we let the 8259 handle the
1188	IRQs */
1189	if (!dev)
1190	{
1191	Log(("apic_get_interrupt: returns -1 (!s)\n"));
1192	return -1;
1193	}
1194
1195	Assert(PDMCritSectIsOwner(dev->CTX_SUFF(pCritSect)));
1196
1197	APICState s = getLapic(dev); /* @todo fix interface */
1198	int intno;
1199
1200	if (!(s->spurious_vec & APIC_SV_ENABLE)) {
1201	Log(("CPU%d: apic_get_interrupt: returns -1 (APIC_SV_ENABLE)\n", s->phys_id));
1202	return -1;
1203	}
1204
1205	/* XXX: spurious IRQ handling */
1206	intno = get_highest_priority_int(s->irr);
1207	if (intno < 0) {
1208	Log(("CPU%d: apic_get_interrupt: returns -1 (irr)\n", s->phys_id));
1209	return -1;
1210	}
1211	if (s->tpr && (uint32_t)intno <= s->tpr) {
1212	Log(("apic_get_interrupt: returns %d (sp)\n", s->spurious_vec & 0xff));
1213	return s->spurious_vec & 0xff;
1214	}
1215	reset_bit(s->irr, intno);
1216	set_bit(s->isr, intno);
1217	apic_update_irq(dev, s);
1218	LogFlow(("CPU%d: apic_get_interrupt: returns %d\n", s->phys_id, intno));
1219	return intno;
1220	}
1221
1222	static uint32_t apic_get_current_count(APICDeviceInfo dev, APICState s)
1223	{
1224	int64_t d;
1225	uint32_t val;
1226
1227	d = (TMTimerGet(s->CTX_SUFF(pTimer)) - s->initial_count_load_time) >>
1228	s->count_shift;
1229
1230	if (s->lvt[APIC_LVT_TIMER] & APIC_LVT_TIMER_PERIODIC) {
1231	/* periodic */
1232	val = s->initial_count - (d % ((uint64_t)s->initial_count + 1));
1233	} else {
1234	if (d >= s->initial_count)
1235	val = 0;
1236	else
1237	val = s->initial_count - d;
1238	}
1239	return val;
1240	}
1241
1242	/**
1243	* Does the frequency hinting and logging.
1244	*
1245	* @param pThis The device state.
1246	*/
1247	DECLINLINE(void) apicDoFrequencyHinting(APICState *pThis)
1248	{
1249	if ( pThis->uHintedInitialCount != pThis->initial_count
1250	\|\| pThis->uHintedCountShift != (uint32_t)pThis->count_shift)
1251	{
1252	pThis->uHintedInitialCount = pThis->initial_count;
1253	pThis->uHintedCountShift = pThis->count_shift;
1254
1255	uint32_t uHz;
1256	if (pThis->initial_count > 0)
1257	{
1258	Assert((unsigned)pThis->count_shift < 30);
1259	uint64_t cTickPerPeriod = ((uint64_t)pThis->initial_count + 1) << pThis->count_shift;
1260	uHz = TMTimerGetFreq(pThis->CTX_SUFF(pTimer)) / cTickPerPeriod;
1261	}
1262	else
1263	uHz = 0;
1264	TMTimerSetFrequencyHint(pThis->CTX_SUFF(pTimer), uHz);
1265	Log(("apic: %u Hz\n", uHz));
1266	}
1267	}
1268
1269	/**
1270	* Implementation of the 0380h access: Timer reset + new initial count.
1271	*
1272	* @param dev The device state.
1273	* @param pThis The APIC sub-device state.
1274	* @param u32NewInitialCount The new initial count for the timer.
1275	*/
1276	static void apicTimerSetInitialCount(APICDeviceInfo dev, APICState pThis, uint32_t u32NewInitialCount)
1277	{
1278	STAM_COUNTER_INC(&pThis->StatTimerSetInitialCount);
1279	pThis->initial_count = u32NewInitialCount;
1280
1281	/*
1282	* Don't (re-)arm the timer if the it's masked or if it's
1283	* a zero length one-shot timer.
1284	*/
1285	if ( !(pThis->lvt[APIC_LVT_TIMER] & APIC_LVT_MASKED)
1286	&& u32NewInitialCount > 0)
1287	{
1288	/*
1289	* Calculate the relative next time and perform a combined timer get/set
1290	* operation. This avoids racing the clock between get and set.
1291	*/
1292	uint64_t cTicksNext = u32NewInitialCount;
1293	cTicksNext += 1;
1294	cTicksNext <<= pThis->count_shift;
1295	TMTimerSetRelative(pThis->CTX_SUFF(pTimer), cTicksNext, &pThis->initial_count_load_time);
1296	pThis->next_time = pThis->initial_count_load_time + cTicksNext;
1297	pThis->fTimerArmed = true;
1298	apicDoFrequencyHinting(pThis);
1299	STAM_COUNTER_INC(&pThis->StatTimerSetInitialCountArm);
1300	Log(("apicTimerSetInitialCount: cTicksNext=%'llu (%#llx) ic=%#x sh=%#x nxt=%#llx\n", cTicksNext, cTicksNext, u32NewInitialCount, pThis->count_shift, pThis->next_time));
1301	}
1302	else
1303	{
1304	/* Stop it if necessary and record the load time for unmasking. */
1305	if (pThis->fTimerArmed)
1306	{
1307	STAM_COUNTER_INC(&pThis->StatTimerSetInitialCountDisarm);
1308	TMTimerStop(pThis->CTX_SUFF(pTimer));
1309	pThis->fTimerArmed = false;
1310	pThis->uHintedCountShift = pThis->uHintedInitialCount = 0;
1311	}
1312	pThis->initial_count_load_time = TMTimerGet(pThis->CTX_SUFF(pTimer));
1313	Log(("apicTimerSetInitialCount: ic=%#x sh=%#x iclt=%#llx\n", u32NewInitialCount, pThis->count_shift, pThis->initial_count_load_time));
1314	}
1315	}
1316
1317	/**
1318	* Implementation of the 0320h access: change the LVT flags.
1319	*
1320	* @param dev The device state.
1321	* @param pThis The APIC sub-device state to operate on.
1322	* @param fNew The new flags.
1323	*/
1324	static void apicTimerSetLvt(APICDeviceInfo dev, APICState pThis, uint32_t fNew)
1325	{
1326	STAM_COUNTER_INC(&pThis->StatTimerSetLvt);
1327
1328	/*
1329	* Make the flag change, saving the old ones so we can avoid
1330	* unnecessary work.
1331	*/
1332	uint32_t const fOld = pThis->lvt[APIC_LVT_TIMER];
1333	pThis->lvt[APIC_LVT_TIMER] = fNew;
1334
1335	/* Only the masked and peridic bits are relevant (see apic_timer_update). */
1336	if ( (fOld & (APIC_LVT_MASKED \| APIC_LVT_TIMER_PERIODIC))
1337	!= (fNew & (APIC_LVT_MASKED \| APIC_LVT_TIMER_PERIODIC)))
1338	{
1339	/*
1340	* If changed to one-shot from periodic, stop the timer if we're not
1341	* in the first period.
1342	*/
1343	/** @todo check how clearing the periodic flag really should behave when not
1344	* in period 1. The current code just mirrors the behavior of the
1345	* original implementation. */
1346	if ( (fOld & APIC_LVT_TIMER_PERIODIC)
1347	&& !(fNew & APIC_LVT_TIMER_PERIODIC))
1348	{
1349	STAM_COUNTER_INC(&pThis->StatTimerSetLvtClearPeriodic);
1350	uint64_t cTicks = (pThis->next_time - pThis->initial_count_load_time) >> pThis->count_shift;
1351	if (cTicks >= pThis->initial_count)
1352	{
1353	/* not first period, stop it. */
1354	TMTimerStop(pThis->CTX_SUFF(pTimer));
1355	pThis->fTimerArmed = false;
1356	pThis->uHintedCountShift = pThis->uHintedInitialCount = 0;
1357	}
1358	/* else: first period, let it fire normally. */
1359	}
1360
1361	/*
1362	* We postpone stopping the timer when it's masked, this way we can
1363	* avoid some timer work when the guest temporarily masks the timer.
1364	* (apicTimerCallback will stop it if still masked.)
1365	*/
1366	if (fNew & APIC_LVT_MASKED)
1367	STAM_COUNTER_INC(&pThis->StatTimerSetLvtPostponed);
1368	else if (pThis->fTimerArmed)
1369	STAM_COUNTER_INC(&pThis->StatTimerSetLvtArmed);
1370	/*
1371	* If unmasked, not armed and with a valid initial count value (according
1372	* to our interpretation of the spec), we will have to rearm the timer so
1373	* it will fire at the end of the current period.
1374	*
1375	* N.B. This is code is currently RACING the virtual sync clock!
1376	*/
1377	else if ( (fOld & APIC_LVT_MASKED)
1378	&& pThis->initial_count > 0)
1379	{
1380	STAM_COUNTER_INC(&pThis->StatTimerSetLvtArm);
1381	for (unsigned cTries = 0; ; cTries++)
1382	{
1383	uint64_t NextTS;
1384	uint64_t cTicks = (TMTimerGet(pThis->CTX_SUFF(pTimer)) - pThis->initial_count_load_time) >> pThis->count_shift;
1385	if (fNew & APIC_LVT_TIMER_PERIODIC)
1386	NextTS = ((cTicks / ((uint64_t)pThis->initial_count + 1)) + 1) * ((uint64_t)pThis->initial_count + 1);
1387	else
1388	{
1389	if (cTicks >= pThis->initial_count)
1390	break;
1391	NextTS = (uint64_t)pThis->initial_count + 1;
1392	}
1393	NextTS <<= pThis->count_shift;
1394	NextTS += pThis->initial_count_load_time;
1395
1396	/* Try avoid the assertion in TM.cpp... this isn't perfect! */
1397	if ( NextTS > TMTimerGet(pThis->CTX_SUFF(pTimer))
1398	\|\| cTries > 10)
1399	{
1400	TMTimerSet(pThis->CTX_SUFF(pTimer), NextTS);
1401	pThis->next_time = NextTS;
1402	pThis->fTimerArmed = true;
1403	apicDoFrequencyHinting(pThis);
1404	Log(("apicTimerSetLvt: ic=%#x sh=%#x nxt=%#llx\n", pThis->initial_count, pThis->count_shift, pThis->next_time));
1405	break;
1406	}
1407	STAM_COUNTER_INC(&pThis->StatTimerSetLvtArmRetries);
1408	}
1409	}
1410	}
1411	else
1412	STAM_COUNTER_INC(&pThis->StatTimerSetLvtNoRelevantChange);
1413	}
1414
1415	# ifdef IN_RING3
1416	/**
1417	* Timer callback function.
1418	*
1419	* @param pDevIns The device state.
1420	* @param pTimer The timer handle.
1421	* @param pvUser User argument pointing to the APIC instance.
1422	*/
1423	static DECLCALLBACK(void) apicTimerCallback(PPDMDEVINS pDevIns, PTMTIMER pTimer, void *pvUser)
1424	{
1425	APICDeviceInfo dev = PDMINS_2_DATA(pDevIns, APICDeviceInfo );
1426	APICState pThis = (APICState )pvUser;
1427	Assert(pThis->pTimerR3 == pTimer);
1428	Assert(pThis->fTimerArmed);
1429
1430	if (!(pThis->lvt[APIC_LVT_TIMER] & APIC_LVT_MASKED)) {
1431	LogFlow(("apic_timer: trigger irq\n"));
1432	apic_set_irq(dev, pThis, pThis->lvt[APIC_LVT_TIMER] & 0xff, APIC_TRIGGER_EDGE);
1433
1434	if ( (pThis->lvt[APIC_LVT_TIMER] & APIC_LVT_TIMER_PERIODIC)
1435	&& pThis->initial_count > 0) {
1436	/* new interval. */
1437	pThis->next_time += (((uint64_t)pThis->initial_count + 1) << pThis->count_shift);
1438	TMTimerSet(pThis->CTX_SUFF(pTimer), pThis->next_time);
1439	pThis->fTimerArmed = true;
1440	apicDoFrequencyHinting(pThis);
1441	Log2(("apicTimerCallback: ic=%#x sh=%#x nxt=%#llx\n", pThis->initial_count, pThis->count_shift, pThis->next_time));
1442	} else {
1443	/* single shot or disabled. */
1444	pThis->fTimerArmed = false;
1445	pThis->uHintedCountShift = pThis->uHintedInitialCount = 0;
1446	}
1447	} else {
1448	/* masked, do not rearm. */
1449	pThis->fTimerArmed = false;
1450	pThis->uHintedCountShift = pThis->uHintedInitialCount = 0;
1451	}
1452	}
1453	# endif /* IN_RING3 */
1454
1455	static uint32_t apic_mem_readl(APICDeviceInfo* dev, APICState *s, RTGCPHYS addr)
1456	{
1457	uint32_t val;
1458	int index;
1459
1460	index = (addr >> 4) & 0xff;
1461
1462	switch(index) {
1463	case 0x02: /* id */
1464	val = s->id << 24;
1465	break;
1466	case 0x03: /* version */
1467	val = APIC_HW_VERSION \| ((APIC_LVT_NB - 1) << 16);
1468	break;
1469	case 0x08:
1470	val = s->tpr;
1471	break;
1472	case 0x09:
1473	val = apic_get_arb_pri(s);
1474	break;
1475	case 0x0a:
1476	/* ppr */
1477	val = apic_get_ppr(s);
1478	break;
1479	case 0x0b:
1480	Log(("apic_mem_readl %x %x -> write only returning 0\n", addr, index));
1481	val = 0;
1482	break;
1483	case 0x0d:
1484	val = s->log_dest << 24;
1485	break;
1486	case 0x0e:
1487	/* Bottom 28 bits are always 1 */
1488	val = (s->dest_mode << 28) \| 0xfffffff;
1489	break;
1490	case 0x0f:
1491	val = s->spurious_vec;
1492	break;
1493	case 0x10: case 0x11: case 0x12: case 0x13: case 0x14: case 0x15: case 0x16: case 0x17:
1494	val = s->isr[index & 7];
1495	break;
1496	case 0x18: case 0x19: case 0x1a: case 0x1b: case 0x1c: case 0x1d: case 0x1e: case 0x1f:
1497	val = s->tmr[index & 7];
1498	break;
1499	case 0x20: case 0x21: case 0x22: case 0x23: case 0x24: case 0x25: case 0x26: case 0x27:
1500	val = s->irr[index & 7];
1501	break;
1502	case 0x28:
1503	val = s->esr;
1504	break;
1505	case 0x30:
1506	case 0x31:
1507	val = s->icr[index & 1];
1508	break;
1509	case 0x32: case 0x33: case 0x34: case 0x35: case 0x36: case 0x37:
1510	val = s->lvt[index - 0x32];
1511	break;
1512	case 0x38:
1513	val = s->initial_count;
1514	break;
1515	case 0x39:
1516	val = apic_get_current_count(dev, s);
1517	break;
1518	case 0x3e:
1519	val = s->divide_conf;
1520	break;
1521	case 0x2f:
1522	/**
1523	* Correctable machine check exception vector, @todo: implement me!
1524	*/
1525	default:
1526	AssertMsgFailed(("apic_mem_readl: unknown index %x\n", index));
1527	s->esr \|= ESR_ILLEGAL_ADDRESS;
1528	val = 0;
1529	break;
1530	}
1531	#ifdef DEBUG_APIC
1532	Log(("CPU%d: APIC read: %08x = %08x\n", s->phys_id, (uint32_t)addr, val));
1533	#endif
1534	return val;
1535	}
1536
1537	static int apic_mem_writel(APICDeviceInfo* dev, APICState *s, RTGCPHYS addr, uint32_t val)
1538	{
1539	int rc = VINF_SUCCESS;
1540	int index;
1541
1542	#ifdef DEBUG_APIC
1543	Log(("CPU%d: APIC write: %08x = %08x\n", s->phys_id, (uint32_t)addr, val));
1544	#endif
1545
1546	index = (addr >> 4) & 0xff;
1547
1548	switch(index) {
1549	case 0x02:
1550	s->id = (val >> 24);
1551	break;
1552	case 0x03:
1553	Log(("apic_mem_writel: write to version register; ignored\n"));
1554	break;
1555	case 0x08:
1556	apic_update_tpr(dev, s, val);
1557	break;
1558	case 0x09:
1559	case 0x0a:
1560	Log(("apic_mem_writel: write to read-only register %d ignored\n", index));
1561	break;
1562	case 0x0b: /* EOI */
1563	apic_eoi(dev, s);
1564	break;
1565	case 0x0d:
1566	s->log_dest = val >> 24;
1567	break;
1568	case 0x0e:
1569	s->dest_mode = val >> 28;
1570	break;
1571	case 0x0f:
1572	s->spurious_vec = val & 0x1ff;
1573	apic_update_irq(dev, s);
1574	break;
1575	case 0x10: case 0x11: case 0x12: case 0x13: case 0x14: case 0x15: case 0x16: case 0x17:
1576	case 0x18: case 0x19: case 0x1a: case 0x1b: case 0x1c: case 0x1d: case 0x1e: case 0x1f:
1577	case 0x20: case 0x21: case 0x22: case 0x23: case 0x24: case 0x25: case 0x26: case 0x27:
1578	case 0x28:
1579	Log(("apic_mem_writel: write to read-only register %d ignored\n", index));
1580	break;
1581
1582	case 0x30:
1583	s->icr[0] = val;
1584	rc = apic_deliver(dev, s, (s->icr[1] >> 24) & 0xff,
1585	(s->icr[0] >> 11) & 1,
1586	(s->icr[0] >> 8) & 7, (s->icr[0] & 0xff),
1587	(s->icr[0] >> 14) & 1, (s->icr[0] >> 15) & 1);
1588	break;
1589	case 0x31:
1590	s->icr[1] = val;
1591	break;
1592	case 0x32 + APIC_LVT_TIMER:
1593	AssertCompile(APIC_LVT_TIMER == 0);
1594	apicTimerSetLvt(dev, s, val);
1595	break;
1596	case 0x33: case 0x34: case 0x35: case 0x36: case 0x37:
1597	{
1598	int n = index - 0x32;
1599	s->lvt[n] = val;
1600	}
1601	break;
1602	case 0x38:
1603	apicTimerSetInitialCount(dev, s, val);
1604	break;
1605	case 0x39:
1606	Log(("apic_mem_writel: write to read-only register %d ignored\n", index));
1607	break;
1608	case 0x3e:
1609	{
1610	int v;
1611	s->divide_conf = val & 0xb;
1612	v = (s->divide_conf & 3) \| ((s->divide_conf >> 1) & 4);
1613	s->count_shift = (v + 1) & 7;
1614	}
1615	break;
1616	default:
1617	AssertMsgFailed(("apic_mem_writel: unknown index %x\n", index));
1618	s->esr \|= ESR_ILLEGAL_ADDRESS;
1619	break;
1620	}
1621	return rc;
1622	}
1623
1624	#ifdef IN_RING3
1625
1626	static void apic_save(SSMHANDLE* f, void *opaque)
1627	{
1628	APICState s = (APICState)opaque;
1629	int i;
1630
1631	SSMR3PutU32(f, s->apicbase);
1632	SSMR3PutU32(f, s->id);
1633	SSMR3PutU32(f, s->phys_id);
1634	SSMR3PutU32(f, s->arb_id);
1635	SSMR3PutU32(f, s->tpr);
1636	SSMR3PutU32(f, s->spurious_vec);
1637	SSMR3PutU8(f, s->log_dest);
1638	SSMR3PutU8(f, s->dest_mode);
1639	for (i = 0; i < 8; i++) {
1640	SSMR3PutU32(f, s->isr[i]);
1641	SSMR3PutU32(f, s->tmr[i]);
1642	SSMR3PutU32(f, s->irr[i]);
1643	}
1644	for (i = 0; i < APIC_LVT_NB; i++) {
1645	SSMR3PutU32(f, s->lvt[i]);
1646	}
1647	SSMR3PutU32(f, s->esr);
1648	SSMR3PutU32(f, s->icr[0]);
1649	SSMR3PutU32(f, s->icr[1]);
1650	SSMR3PutU32(f, s->divide_conf);
1651	SSMR3PutU32(f, s->count_shift);
1652	SSMR3PutU32(f, s->initial_count);
1653	SSMR3PutU64(f, s->initial_count_load_time);
1654	SSMR3PutU64(f, s->next_time);
1655
1656	TMR3TimerSave(s->CTX_SUFF(pTimer), f);
1657	}
1658
1659	static int apic_load(SSMHANDLE f, void opaque, int version_id)
1660	{
1661	APICState s = (APICState)opaque;
1662	int i;
1663
1664	/* XXX: what if the base changes? (registered memory regions) */
1665	SSMR3GetU32(f, &s->apicbase);
1666
1667	switch (version_id)
1668	{
1669	case APIC_SAVED_STATE_VERSION_ANCIENT:
1670	{
1671	uint8_t val = 0;
1672	SSMR3GetU8(f, &val);
1673	s->id = val;
1674	/* UP only in old saved states */
1675	s->phys_id = 0;
1676	SSMR3GetU8(f, &val);
1677	s->arb_id = val;
1678	break;
1679	}
1680	case APIC_SAVED_STATE_VERSION:
1681	case APIC_SAVED_STATE_VERSION_VBOX_30:
1682	SSMR3GetU32(f, &s->id);
1683	SSMR3GetU32(f, &s->phys_id);
1684	SSMR3GetU32(f, &s->arb_id);
1685	break;
1686	default:
1687	return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
1688	}
1689	SSMR3GetU32(f, &s->tpr);
1690	SSMR3GetU32(f, &s->spurious_vec);
1691	SSMR3GetU8(f, &s->log_dest);
1692	SSMR3GetU8(f, &s->dest_mode);
1693	for (i = 0; i < 8; i++) {
1694	SSMR3GetU32(f, &s->isr[i]);
1695	SSMR3GetU32(f, &s->tmr[i]);
1696	SSMR3GetU32(f, &s->irr[i]);
1697	}
1698	for (i = 0; i < APIC_LVT_NB; i++) {
1699	SSMR3GetU32(f, &s->lvt[i]);
1700	}
1701	SSMR3GetU32(f, &s->esr);
1702	SSMR3GetU32(f, &s->icr[0]);
1703	SSMR3GetU32(f, &s->icr[1]);
1704	SSMR3GetU32(f, &s->divide_conf);
1705	SSMR3GetU32(f, (uint32_t *)&s->count_shift);
1706	SSMR3GetU32(f, (uint32_t *)&s->initial_count);
1707	SSMR3GetU64(f, (uint64_t *)&s->initial_count_load_time);
1708	SSMR3GetU64(f, (uint64_t *)&s->next_time);
1709
1710	int rc = TMR3TimerLoad(s->CTX_SUFF(pTimer), f);
1711	s->uHintedCountShift = s->uHintedInitialCount = 0;
1712	s->fTimerArmed = TMTimerIsActive(s->CTX_SUFF(pTimer));
1713	if (s->fTimerArmed)
1714	apicDoFrequencyHinting(s);
1715
1716	return VINF_SUCCESS; /** @todo darn mess! */
1717	}
1718	#endif /* IN_RING3 */
1719
1720	static void ioapic_service(IOAPICState *s)
1721	{
1722	uint8_t i;
1723	uint8_t trig_mode;
1724	uint8_t vector;
1725	uint8_t delivery_mode;
1726	uint32_t mask;
1727	uint64_t entry;
1728	uint8_t dest;
1729	uint8_t dest_mode;
1730	uint8_t polarity;
1731
1732	for (i = 0; i < IOAPIC_NUM_PINS; i++) {
1733	mask = 1 << i;
1734	if (s->irr & mask) {
1735	entry = s->ioredtbl[i];
1736	if (!(entry & APIC_LVT_MASKED)) {
1737	trig_mode = ((entry >> 15) & 1);
1738	dest = entry >> 56;
1739	dest_mode = (entry >> 11) & 1;
1740	delivery_mode = (entry >> 8) & 7;
1741	polarity = (entry >> 13) & 1;
1742	if (trig_mode == APIC_TRIGGER_EDGE)
1743	s->irr &= ~mask;
1744	if (delivery_mode == APIC_DM_EXTINT)
1745	/* malc: i'm still not so sure about ExtINT delivery */
1746	{
1747	AssertMsgFailed(("Delivery mode ExtINT"));
1748	vector = 0xff; /* incorrect but shuts up gcc. */
1749	}
1750	else
1751	vector = entry & 0xff;
1752
1753	int rc = s->CTX_SUFF(pIoApicHlp)->pfnApicBusDeliver(s->CTX_SUFF(pDevIns),
1754	dest,
1755	dest_mode,
1756	delivery_mode,
1757	vector,
1758	polarity,
1759	trig_mode);
1760	/* We must be sure that attempts to reschedule in R3
1761	never get here */
1762	Assert(rc == VINF_SUCCESS);
1763	}
1764	}
1765	}
1766	}
1767
1768
1769	static void ioapic_set_irq(void *opaque, int vector, int level)
1770	{
1771	IOAPICState s = (IOAPICState)opaque;
1772
1773	if (vector >= 0 && vector < IOAPIC_NUM_PINS) {
1774	uint32_t mask = 1 << vector;
1775	uint64_t entry = s->ioredtbl[vector];
1776
1777	if ((entry >> 15) & 1) {
1778	/* level triggered */
1779	if (level) {
1780	s->irr \|= mask;
1781	ioapic_service(s);
1782	if ((level & PDM_IRQ_LEVEL_FLIP_FLOP) == PDM_IRQ_LEVEL_FLIP_FLOP) {
1783	s->irr &= ~mask;
1784	}
1785	} else {
1786	s->irr &= ~mask;
1787	}
1788	} else {
1789	/* edge triggered */
1790	if (level) {
1791	s->irr \|= mask;
1792	ioapic_service(s);
1793	}
1794	}
1795	}
1796	}
1797
1798	static uint32_t ioapic_mem_readl(void *opaque, RTGCPHYS addr)
1799	{
1800	IOAPICState s = (IOAPICState)opaque;
1801	int index;
1802	uint32_t val = 0;
1803
1804	addr &= 0xff;
1805	if (addr == 0x00) {
1806	val = s->ioregsel;
1807	} else if (addr == 0x10) {
1808	switch (s->ioregsel) {
1809	case 0x00:
1810	val = s->id << 24;
1811	break;
1812	case 0x01:
1813	val = 0x11 \| ((IOAPIC_NUM_PINS - 1) << 16); /* version 0x11 */
1814	break;
1815	case 0x02:
1816	val = 0;
1817	break;
1818	default:
1819	index = (s->ioregsel - 0x10) >> 1;
1820	if (index >= 0 && index < IOAPIC_NUM_PINS) {
1821	if (s->ioregsel & 1)
1822	val = s->ioredtbl[index] >> 32;
1823	else
1824	val = s->ioredtbl[index] & 0xffffffff;
1825	}
1826	}
1827	#ifdef DEBUG_IOAPIC
1828	Log(("I/O APIC read: %08x = %08x\n", s->ioregsel, val));
1829	#endif
1830	}
1831	return val;
1832	}
1833
1834	static void ioapic_mem_writel(void *opaque, RTGCPHYS addr, uint32_t val)
1835	{
1836	IOAPICState s = (IOAPICState)opaque;
1837	int index;
1838
1839	addr &= 0xff;
1840	if (addr == 0x00) {
1841	s->ioregsel = val;
1842	return;
1843	} else if (addr == 0x10) {
1844	#ifdef DEBUG_IOAPIC
1845	Log(("I/O APIC write: %08x = %08x\n", s->ioregsel, val));
1846	#endif
1847	switch (s->ioregsel) {
1848	case 0x00:
1849	s->id = (val >> 24) & 0xff;
1850	return;
1851	case 0x01:
1852	case 0x02:
1853	return;
1854	default:
1855	index = (s->ioregsel - 0x10) >> 1;
1856	if (index >= 0 && index < IOAPIC_NUM_PINS) {
1857	if (s->ioregsel & 1) {
1858	s->ioredtbl[index] &= 0xffffffff;
1859	s->ioredtbl[index] \|= (uint64_t)val << 32;
1860	} else {
1861	/* According to IOAPIC spec, vectors should be from 0x10 to 0xfe */
1862	uint8_t vec = val & 0xff;
1863	if ((val & APIC_LVT_MASKED) \|\|
1864	((vec >= 0x10) && (vec < 0xff)))
1865	{
1866	s->ioredtbl[index] &= ~0xffffffffULL;
1867	s->ioredtbl[index] \|= val;
1868	}
1869	else
1870	{
1871	/*
1872	* Linux 2.6 kernels has pretty strange function
1873	* unlock_ExtINT_logic() which writes
1874	* absolutely bogus (all 0) value into the vector
1875	* with pretty vague explanation why.
1876	* So we just ignore such writes.
1877	*/
1878	LogRel(("IOAPIC GUEST BUG: bad vector writing %x(sel=%x) to %d\n", val, s->ioregsel, index));
1879	}
1880	}
1881	ioapic_service(s);
1882	}
1883	}
1884	}
1885	}
1886
1887	#ifdef IN_RING3
1888
1889	static void ioapic_save(SSMHANDLE f, void opaque)
1890	{
1891	IOAPICState s = (IOAPICState)opaque;
1892	int i;
1893
1894	SSMR3PutU8(f, s->id);
1895	SSMR3PutU8(f, s->ioregsel);
1896	for (i = 0; i < IOAPIC_NUM_PINS; i++) {
1897	SSMR3PutU64(f, s->ioredtbl[i]);
1898	}
1899	}
1900
1901	static int ioapic_load(SSMHANDLE f, void opaque, int version_id)
1902	{
1903	IOAPICState s = (IOAPICState)opaque;
1904	int i;
1905
1906	if (version_id != 1)
1907	return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
1908
1909	SSMR3GetU8(f, &s->id);
1910	SSMR3GetU8(f, &s->ioregsel);
1911	for (i = 0; i < IOAPIC_NUM_PINS; i++) {
1912	SSMR3GetU64(f, &s->ioredtbl[i]);
1913	}
1914	return 0;
1915	}
1916
1917	static void ioapic_reset(void *opaque)
1918	{
1919	IOAPICState s = (IOAPICState)opaque;
1920	PPDMDEVINSR3 pDevIns = s->pDevInsR3;
1921	PCPDMIOAPICHLPR3 pIoApicHlp = s->pIoApicHlpR3;
1922	int i;
1923
1924	memset(s, 0, sizeof(*s));
1925	for(i = 0; i < IOAPIC_NUM_PINS; i++)
1926	s->ioredtbl[i] = 1 << 16; /* mask LVT */
1927
1928	if (pDevIns)
1929	{
1930	s->pDevInsR3 = pDevIns;
1931	s->pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
1932	s->pDevInsR0 = PDMDEVINS_2_R0PTR(pDevIns);
1933	}
1934	if (pIoApicHlp)
1935	{
1936	s->pIoApicHlpR3 = pIoApicHlp;
1937	s->pIoApicHlpRC = s->pIoApicHlpR3->pfnGetRCHelpers(pDevIns);
1938	s->pIoApicHlpR0 = s->pIoApicHlpR3->pfnGetR0Helpers(pDevIns);
1939	}
1940	}
1941
1942	#endif /* IN_RING3 */
1943
1944	/* LAPIC */
1945	PDMBOTHCBDECL(int) apicMMIORead(PPDMDEVINS pDevIns, void pvUser, RTGCPHYS GCPhysAddr, void pv, unsigned cb)
1946	{
1947	APICDeviceInfo dev = PDMINS_2_DATA(pDevIns, APICDeviceInfo );
1948	APICState *s = getLapic(dev);
1949
1950	Log(("CPU%d: apicMMIORead at %llx\n", s->phys_id, (uint64_t)GCPhysAddr));
1951
1952	/** @todo: add LAPIC range validity checks (different LAPICs can theoretically have
1953	different physical addresses, see #3092) */
1954
1955	STAM_COUNTER_INC(&CTXSUFF(dev->StatMMIORead));
1956	switch (cb)
1957	{
1958	case 1:
1959	(uint8_t )pv = 0;
1960	break;
1961
1962	case 2:
1963	(uint16_t )pv = 0;
1964	break;
1965
1966	case 4:
1967	{
1968	#if 0 /** @note experimental */
1969	#ifndef IN_RING3
1970	uint32_t index = (GCPhysAddr >> 4) & 0xff;
1971
1972	if ( index == 0x08 /* TPR */
1973	&& ++s->cTPRPatchAttempts < APIC_MAX_PATCH_ATTEMPTS)
1974	{
1975	#ifdef IN_RC
1976	pDevIns->pDevHlpGC->pfnPATMSetMMIOPatchInfo(pDevIns, GCPhysAddr, &s->tpr);
1977	#else
1978	RTGCPTR pDevInsGC = PDMINS2DATA_GCPTR(pDevIns);
1979	pDevIns->pHlpR0->pfnPATMSetMMIOPatchInfo(pDevIns, GCPhysAddr, pDevIns + RT_OFFSETOF(APICState, tpr));
1980	#endif
1981	return VINF_PATM_HC_MMIO_PATCH_READ;
1982	}
1983	#endif
1984	#endif /* experimental */
1985	APIC_LOCK(dev, VINF_IOM_HC_MMIO_READ);
1986	(uint32_t )pv = apic_mem_readl(dev, s, GCPhysAddr);
1987	APIC_UNLOCK(dev);
1988	break;
1989	}
1990	default:
1991	AssertReleaseMsgFailed(("cb=%d\n", cb)); /* for now we assume simple accesses. */
1992	return VERR_INTERNAL_ERROR;
1993	}
1994	return VINF_SUCCESS;
1995	}
1996
1997	PDMBOTHCBDECL(int) apicMMIOWrite(PPDMDEVINS pDevIns, void pvUser, RTGCPHYS GCPhysAddr, void pv, unsigned cb)
1998	{
1999	APICDeviceInfo dev = PDMINS_2_DATA(pDevIns, APICDeviceInfo );
2000	APICState *s = getLapic(dev);
2001
2002	Log(("CPU%d: apicMMIOWrite at %llx\n", s->phys_id, (uint64_t)GCPhysAddr));
2003
2004	/** @todo: add LAPIC range validity checks (multiple LAPICs can theoretically have
2005	different physical addresses, see #3092) */
2006
2007	STAM_COUNTER_INC(&CTXSUFF(dev->StatMMIOWrite));
2008	switch (cb)
2009	{
2010	case 1:
2011	case 2:
2012	/* ignore */
2013	break;
2014
2015	case 4:
2016	{
2017	int rc;
2018	APIC_LOCK(dev, VINF_IOM_HC_MMIO_WRITE);
2019	rc = apic_mem_writel(dev, s, GCPhysAddr, (uint32_t )pv);
2020	APIC_UNLOCK(dev);
2021	return rc;
2022	}
2023
2024	default:
2025	AssertReleaseMsgFailed(("cb=%d\n", cb)); /* for now we assume simple accesses. */
2026	return VERR_INTERNAL_ERROR;
2027	}
2028	return VINF_SUCCESS;
2029	}
2030
2031	#ifdef IN_RING3
2032
2033	/* Print a 8-dword LAPIC bit map (256 bits). */
2034	static void lapicDumpVec(APICDeviceInfo dev, APICState lapic, PCDBGFINFOHLP pHlp, unsigned start)
2035	{
2036	unsigned i;
2037	uint32_t val;
2038
2039	for (i = 0; i < 8; ++i)
2040	{
2041	val = apic_mem_readl(dev, lapic, start + (i << 4));
2042	pHlp->pfnPrintf(pHlp, "%08X", val);
2043	}
2044	pHlp->pfnPrintf(pHlp, "\n");
2045	}
2046
2047	/* Print basic LAPIC state. */
2048	static DECLCALLBACK(void) lapicInfoBasic(APICDeviceInfo dev, APICState lapic, PCDBGFINFOHLP pHlp)
2049	{
2050	uint32_t val;
2051	unsigned max_lvt;
2052
2053	pHlp->pfnPrintf(pHlp, "Local APIC at %08X:\n", lapic->apicbase);
2054	val = apic_mem_readl(dev, lapic, 0x20);
2055	pHlp->pfnPrintf(pHlp, " LAPIC ID : %08X\n", val);
2056	pHlp->pfnPrintf(pHlp, " APIC ID = %02X\n", (val >> 24) & 0xff);
2057	val = apic_mem_readl(dev, lapic, 0x30);
2058	max_lvt = (val >> 16) & 0xff;
2059	pHlp->pfnPrintf(pHlp, " APIC VER : %08X\n", val);
2060	pHlp->pfnPrintf(pHlp, " version = %02X\n", val & 0xff);
2061	pHlp->pfnPrintf(pHlp, " lvts = %d\n", ((val >> 16) & 0xff) + 1);
2062	val = apic_mem_readl(dev, lapic, 0x80);
2063	pHlp->pfnPrintf(pHlp, " TPR : %08X\n", val);
2064	pHlp->pfnPrintf(pHlp, " task pri = %d/%d\n", (val >> 4) & 0xf, val & 0xf);
2065	val = apic_mem_readl(dev, lapic, 0xA0);
2066	pHlp->pfnPrintf(pHlp, " PPR : %08X\n", val);
2067	pHlp->pfnPrintf(pHlp, " cpu pri = %d/%d\n", (val >> 4) & 0xf, val & 0xf);
2068	val = apic_mem_readl(dev, lapic, 0xD0);
2069	pHlp->pfnPrintf(pHlp, " LDR : %08X\n", val);
2070	pHlp->pfnPrintf(pHlp, " log id = %02X\n", (val >> 24) & 0xff);
2071	val = apic_mem_readl(dev, lapic, 0xE0);
2072	pHlp->pfnPrintf(pHlp, " DFR : %08X\n", val);
2073	val = apic_mem_readl(dev, lapic, 0xF0);
2074	pHlp->pfnPrintf(pHlp, " SVR : %08X\n", val);
2075	pHlp->pfnPrintf(pHlp, " focus = %s\n", val & (1 << 9) ? "check off" : "check on");
2076	pHlp->pfnPrintf(pHlp, " lapic = %s\n", val & (1 << 8) ? "ENABLED" : "DISABLED");
2077	pHlp->pfnPrintf(pHlp, " vector = %02X\n", val & 0xff);
2078	pHlp->pfnPrintf(pHlp, " ISR : ");
2079	lapicDumpVec(dev, lapic, pHlp, 0x100);
2080	val = get_highest_priority_int(lapic->isr);
2081	pHlp->pfnPrintf(pHlp, " highest = %02X\n", val == ~0U ? 0 : val);
2082	pHlp->pfnPrintf(pHlp, " IRR : ");
2083	lapicDumpVec(dev, lapic, pHlp, 0x200);
2084	val = get_highest_priority_int(lapic->irr);
2085	pHlp->pfnPrintf(pHlp, " highest = %02X\n", val == ~0U ? 0 : val);
2086	val = apic_mem_readl(dev, lapic, 0x320);
2087	}
2088
2089	/* Print the more interesting LAPIC LVT entries. */
2090	static DECLCALLBACK(void) lapicInfoLVT(APICDeviceInfo dev, APICState lapic, PCDBGFINFOHLP pHlp)
2091	{
2092	uint32_t val;
2093	static const char *dmodes[] = { "Fixed ", "Reserved", "SMI", "Reserved",
2094	"NMI", "INIT", "Reserved", "ExtINT" };
2095
2096	val = apic_mem_readl(dev, lapic, 0x320);
2097	pHlp->pfnPrintf(pHlp, " LVT Timer : %08X\n", val);
2098	pHlp->pfnPrintf(pHlp, " mode = %s\n", val & (1 << 17) ? "periodic" : "one-shot");
2099	pHlp->pfnPrintf(pHlp, " mask = %d\n", (val >> 16) & 1);
2100	pHlp->pfnPrintf(pHlp, " status = %s\n", val & (1 << 12) ? "pending" : "idle");
2101	pHlp->pfnPrintf(pHlp, " vector = %02X\n", val & 0xff);
2102	val = apic_mem_readl(dev, lapic, 0x350);
2103	pHlp->pfnPrintf(pHlp, " LVT LINT0 : %08X\n", val);
2104	pHlp->pfnPrintf(pHlp, " mask = %d\n", (val >> 16) & 1);
2105	pHlp->pfnPrintf(pHlp, " trigger = %s\n", val & (1 << 15) ? "level" : "edge");
2106	pHlp->pfnPrintf(pHlp, " rem irr = %d\n", (val >> 14) & 1);
2107	pHlp->pfnPrintf(pHlp, " polarty = %d\n", (val >> 13) & 1);
2108	pHlp->pfnPrintf(pHlp, " status = %s\n", val & (1 << 12) ? "pending" : "idle");
2109	pHlp->pfnPrintf(pHlp, " delivry = %s\n", dmodes[(val >> 8) & 7]);
2110	pHlp->pfnPrintf(pHlp, " vector = %02X\n", val & 0xff);
2111	val = apic_mem_readl(dev, lapic, 0x360);
2112	pHlp->pfnPrintf(pHlp, " LVT LINT1 : %08X\n", val);
2113	pHlp->pfnPrintf(pHlp, " mask = %d\n", (val >> 16) & 1);
2114	pHlp->pfnPrintf(pHlp, " trigger = %s\n", val & (1 << 15) ? "level" : "edge");
2115	pHlp->pfnPrintf(pHlp, " rem irr = %d\n", (val >> 14) & 1);
2116	pHlp->pfnPrintf(pHlp, " polarty = %d\n", (val >> 13) & 1);
2117	pHlp->pfnPrintf(pHlp, " status = %s\n", val & (1 << 12) ? "pending" : "idle");
2118	pHlp->pfnPrintf(pHlp, " delivry = %s\n", dmodes[(val >> 8) & 7]);
2119	pHlp->pfnPrintf(pHlp, " vector = %02X\n", val & 0xff);
2120	}
2121
2122	/* Print LAPIC timer state. */
2123	static DECLCALLBACK(void) lapicInfoTimer(APICDeviceInfo dev, APICState lapic, PCDBGFINFOHLP pHlp)
2124	{
2125	uint32_t val;
2126	unsigned divider;
2127
2128	pHlp->pfnPrintf(pHlp, "Local APIC timer:\n");
2129	val = apic_mem_readl(dev, lapic, 0x380);
2130	pHlp->pfnPrintf(pHlp, " Initial count : %08X\n", val);
2131	val = apic_mem_readl(dev, lapic, 0x390);
2132	pHlp->pfnPrintf(pHlp, " Current count : %08X\n", val);
2133	val = apic_mem_readl(dev, lapic, 0x3E0);
2134	pHlp->pfnPrintf(pHlp, " Divide config : %08X\n", val);
2135	divider = ((val >> 1) & 0x04) \| (val & 0x03);
2136	pHlp->pfnPrintf(pHlp, " divider = %d\n", divider == 7 ? 1 : 2 << divider);
2137	}
2138
2139	/**
2140	* Info handler, device version. Dumps Local APIC(s) state according to given argument.
2141	*
2142	* @param pDevIns Device instance which registered the info.
2143	* @param pHlp Callback functions for doing output.
2144	* @param pszArgs Argument string. Optional.
2145	*/
2146	static DECLCALLBACK(void) lapicInfo(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
2147	{
2148	APICDeviceInfo dev = PDMINS_2_DATA(pDevIns, APICDeviceInfo );
2149	APICState *lapic;
2150
2151	lapic = getLapic(dev);
2152
2153	if (pszArgs == NULL \|\| !strcmp(pszArgs, "basic"))
2154	{
2155	lapicInfoBasic(dev, lapic, pHlp);
2156	}
2157	else if (!strcmp(pszArgs, "lvt"))
2158	{
2159	lapicInfoLVT(dev, lapic, pHlp);
2160	}
2161	else if (!strcmp(pszArgs, "timer"))
2162	{
2163	lapicInfoTimer(dev, lapic, pHlp);
2164	}
2165	else
2166	{
2167	pHlp->pfnPrintf(pHlp, "Invalid argument. Recognized arguments are 'basic', 'lvt', 'timer'.\n");
2168	}
2169	}
2170
2171	/**
2172	* @copydoc FNSSMDEVLIVEEXEC
2173	*/
2174	static DECLCALLBACK(int) apicLiveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t uPass)
2175	{
2176	APICDeviceInfo pThis = PDMINS_2_DATA(pDevIns, APICDeviceInfo );
2177
2178	SSMR3PutU32( pSSM, pThis->cCpus);
2179	SSMR3PutBool(pSSM, pThis->fIoApic);
2180	SSMR3PutU32( pSSM, pThis->enmVersion);
2181	AssertCompile(PDMAPICVERSION_APIC == 2);
2182
2183	return VINF_SSM_DONT_CALL_AGAIN;
2184	}
2185
2186	/**
2187	* @copydoc FNSSMDEVSAVEEXEC
2188	*/
2189	static DECLCALLBACK(int) apicSaveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
2190	{
2191	APICDeviceInfo dev = PDMINS_2_DATA(pDevIns, APICDeviceInfo );
2192
2193	/* config */
2194	apicLiveExec(pDevIns, pSSM, SSM_PASS_FINAL);
2195
2196	/* save all APICs data, @todo: is it correct? */
2197	foreach_apic(dev, 0xffffffff, apic_save(pSSM, apic));
2198
2199	return VINF_SUCCESS;
2200	}
2201
2202	/**
2203	* @copydoc FNSSMDEVLOADEXEC
2204	*/
2205	static DECLCALLBACK(int) apicLoadExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
2206	{
2207	APICDeviceInfo pThis = PDMINS_2_DATA(pDevIns, APICDeviceInfo );
2208
2209	if ( uVersion != APIC_SAVED_STATE_VERSION
2210	&& uVersion != APIC_SAVED_STATE_VERSION_VBOX_30
2211	&& uVersion != APIC_SAVED_STATE_VERSION_ANCIENT)
2212	return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
2213
2214	/* config */
2215	if (uVersion > APIC_SAVED_STATE_VERSION_VBOX_30) {
2216	uint32_t cCpus;
2217	int rc = SSMR3GetU32(pSSM, &cCpus); AssertRCReturn(rc, rc);
2218	if (cCpus != pThis->cCpus)
2219	return SSMR3SetCfgError(pSSM, RT_SRC_POS, N_("Config mismatch - cCpus: saved=%#x config=%#x"), cCpus, pThis->cCpus);
2220	bool fIoApic;
2221	rc = SSMR3GetBool(pSSM, &fIoApic); AssertRCReturn(rc, rc);
2222	if (fIoApic != pThis->fIoApic)
2223	return SSMR3SetCfgError(pSSM, RT_SRC_POS, N_("Config mismatch - fIoApic: saved=%RTbool config=%RTbool"), fIoApic, pThis->fIoApic);
2224	uint32_t uApicVersion;
2225	rc = SSMR3GetU32(pSSM, &uApicVersion); AssertRCReturn(rc, rc);
2226	if (uApicVersion != (uint32_t)pThis->enmVersion)
2227	return SSMR3SetCfgError(pSSM, RT_SRC_POS, N_("Config mismatch - uApicVersion: saved=%#x config=%#x"), uApicVersion, pThis->enmVersion);
2228	}
2229
2230	if (uPass != SSM_PASS_FINAL)
2231	return VINF_SUCCESS;
2232
2233	/* load all APICs data / /* @todo: is it correct? */
2234	APIC_LOCK(pThis, VERR_INTERNAL_ERROR_3);
2235	foreach_apic(pThis, 0xffffffff,
2236	if (apic_load(pSSM, apic, uVersion)) {
2237	AssertFailed();
2238	APIC_UNLOCK(pThis);
2239	return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
2240	}
2241	);
2242	APIC_UNLOCK(pThis);
2243	return VINF_SUCCESS;
2244	}
2245
2246	/**
2247	* @copydoc FNPDMDEVRESET
2248	*/
2249	static DECLCALLBACK(void) apicReset(PPDMDEVINS pDevIns)
2250	{
2251	APICDeviceInfo dev = PDMINS_2_DATA(pDevIns, APICDeviceInfo );
2252	unsigned i;
2253
2254	APIC_LOCK_VOID(dev, VERR_INTERNAL_ERROR);
2255
2256	/* Reset all APICs. */
2257	for (i = 0; i < dev->cCpus; i++) {
2258	APICState *pApic = &dev->CTX_SUFF(paLapics)[i];
2259	TMTimerStop(pApic->CTX_SUFF(pTimer));
2260
2261	/* Clear LAPIC state as if an INIT IPI was sent. */
2262	apic_init_ipi(dev, pApic);
2263	/* The IDs are not touched by apic_init_ipi() and must be reset now. */
2264	pApic->arb_id = pApic->id = i;
2265	Assert(pApic->id == pApic->phys_id); /* The two should match again. */
2266	/* Reset should re-enable the APIC, see comment in msi.h */
2267	pApic->apicbase = VBOX_MSI_ADDR_BASE \| MSR_IA32_APICBASE_ENABLE;
2268	if (pApic->phys_id == 0)
2269	pApic->apicbase \|= MSR_IA32_APICBASE_BSP;
2270
2271	/* Clear any pending APIC interrupt action flag. */
2272	cpuClearInterrupt(dev, pApic);
2273	}
2274	/** @todo r=bird: Why is this done everytime, while the constructor first
2275	* checks the CPUID? Who is right? */
2276	dev->pApicHlpR3->pfnChangeFeature(dev->pDevInsR3, dev->enmVersion);
2277
2278	APIC_UNLOCK(dev);
2279	}
2280
2281	/**
2282	* @copydoc FNPDMDEVRELOCATE
2283	*/
2284	static DECLCALLBACK(void) apicRelocate(PPDMDEVINS pDevIns, RTGCINTPTR offDelta)
2285	{
2286	APICDeviceInfo pThis = PDMINS_2_DATA(pDevIns, APICDeviceInfo );
2287	pThis->pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
2288	pThis->pApicHlpRC = pThis->pApicHlpR3->pfnGetRCHelpers(pDevIns);
2289	pThis->paLapicsRC = MMHyperR3ToRC(PDMDevHlpGetVM(pDevIns), pThis->paLapicsR3);
2290	pThis->pCritSectRC = pThis->pApicHlpR3->pfnGetRCCritSect(pDevIns);
2291	for (uint32_t i = 0; i < pThis->cCpus; i++)
2292	pThis->paLapicsR3[i].pTimerRC = TMTimerRCPtr(pThis->paLapicsR3[i].pTimerR3);
2293	}
2294
2295	DECLINLINE(void) initApicData(APICState* apic, uint8_t id)
2296	{
2297	int i;
2298	memset(apic, 0, sizeof(*apic));
2299
2300	/* See comment in msi.h for LAPIC base info */
2301	apic->apicbase = VBOX_MSI_ADDR_BASE \| MSR_IA32_APICBASE_ENABLE;
2302	/* Mark first CPU as BSP */
2303	if (id == 0)
2304	apic->apicbase \|= MSR_IA32_APICBASE_BSP;
2305	for (i = 0; i < APIC_LVT_NB; i++)
2306	apic->lvt[i] = 1 << 16; /* mask LVT */
2307	apic->spurious_vec = 0xff;
2308	apic->phys_id = apic->id = id;
2309	}
2310
2311	/**
2312	* @copydoc FNPDMDEVCONSTRUCT
2313	*/
2314	static DECLCALLBACK(int) apicConstruct(PPDMDEVINS pDevIns, int iInstance, PCFGMNODE pCfg)
2315	{
2316	PDMAPICREG ApicReg;
2317	int rc;
2318	uint32_t i;
2319	bool fIoApic;
2320	bool fGCEnabled;
2321	bool fR0Enabled;
2322	APICDeviceInfo pThis = PDMINS_2_DATA(pDevIns, APICDeviceInfo );
2323	uint32_t cCpus;
2324
2325	/*
2326	* Only single device instance.
2327	*/
2328	Assert(iInstance == 0);
2329
2330	/*
2331	* Validate configuration.
2332	*/
2333	if (!CFGMR3AreValuesValid(pCfg,
2334	"IOAPIC\0"
2335	"GCEnabled\0"
2336	"R0Enabled\0"
2337	"NumCPUs\0"))
2338	return VERR_PDM_DEVINS_UNKNOWN_CFG_VALUES;
2339
2340	rc = CFGMR3QueryBoolDef(pCfg, "IOAPIC", &fIoApic, true);
2341	if (RT_FAILURE(rc))
2342	return PDMDEV_SET_ERROR(pDevIns, rc,
2343	N_("Configuration error: Failed to read \"IOAPIC\""));
2344
2345	rc = CFGMR3QueryBoolDef(pCfg, "GCEnabled", &fGCEnabled, true);
2346	if (RT_FAILURE(rc))
2347	return PDMDEV_SET_ERROR(pDevIns, rc,
2348	N_("Configuration error: Failed to query boolean value \"GCEnabled\""));
2349
2350	rc = CFGMR3QueryBoolDef(pCfg, "R0Enabled", &fR0Enabled, true);
2351	if (RT_FAILURE(rc))
2352	return PDMDEV_SET_ERROR(pDevIns, rc,
2353	N_("Configuration error: Failed to query boolean value \"R0Enabled\""));
2354
2355	rc = CFGMR3QueryU32Def(pCfg, "NumCPUs", &cCpus, 1);
2356	if (RT_FAILURE(rc))
2357	return PDMDEV_SET_ERROR(pDevIns, rc,
2358	N_("Configuration error: Failed to query integer value \"NumCPUs\""));
2359
2360	Log(("APIC: cCpus=%d fR0Enabled=%RTbool fGCEnabled=%RTbool fIoApic=%RTbool\n", cCpus, fR0Enabled, fGCEnabled, fIoApic));
2361
2362	/** @todo Current implementation is limited to 32 CPUs due to the use of 32
2363	* bits bitmasks. */
2364	if (cCpus > 32)
2365	return PDMDEV_SET_ERROR(pDevIns, rc,
2366	N_("Configuration error: Invalid value for \"NumCPUs\""));
2367
2368	/*
2369	* Init the data.
2370	*/
2371	pThis->pDevInsR3 = pDevIns;
2372	pThis->pDevInsR0 = PDMDEVINS_2_R0PTR(pDevIns);
2373	pThis->pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
2374	pThis->cCpus = cCpus;
2375	pThis->fIoApic = fIoApic;
2376	/* Use PDMAPICVERSION_X2APIC to activate x2APIC mode */
2377	pThis->enmVersion = PDMAPICVERSION_APIC;
2378
2379	PVM pVM = PDMDevHlpGetVM(pDevIns);
2380	/*
2381	* We are not freeing this memory, as it's automatically released when guest exits.
2382	*/
2383	rc = MMHyperAlloc(pVM, cCpus * sizeof(APICState), 1, MM_TAG_PDM_DEVICE_USER, (void **)&pThis->paLapicsR3);
2384	if (RT_FAILURE(rc))
2385	return VERR_NO_MEMORY;
2386	pThis->paLapicsR0 = MMHyperR3ToR0(pVM, pThis->paLapicsR3);
2387	pThis->paLapicsRC = MMHyperR3ToRC(pVM, pThis->paLapicsR3);
2388
2389	for (i = 0; i < cCpus; i++)
2390	initApicData(&pThis->paLapicsR3[i], i);
2391
2392	/*
2393	* Register the APIC.
2394	*/
2395	ApicReg.u32Version = PDM_APICREG_VERSION;
2396	ApicReg.pfnGetInterruptR3 = apicGetInterrupt;
2397	ApicReg.pfnHasPendingIrqR3 = apicHasPendingIrq;
2398	ApicReg.pfnSetBaseR3 = apicSetBase;
2399	ApicReg.pfnGetBaseR3 = apicGetBase;
2400	ApicReg.pfnSetTPRR3 = apicSetTPR;
2401	ApicReg.pfnGetTPRR3 = apicGetTPR;
2402	ApicReg.pfnWriteMSRR3 = apicWriteMSR;
2403	ApicReg.pfnReadMSRR3 = apicReadMSR;
2404	ApicReg.pfnBusDeliverR3 = apicBusDeliverCallback;
2405	ApicReg.pfnLocalInterruptR3 = apicLocalInterrupt;
2406	if (fGCEnabled) {
2407	ApicReg.pszGetInterruptRC = "apicGetInterrupt";
2408	ApicReg.pszHasPendingIrqRC = "apicHasPendingIrq";
2409	ApicReg.pszSetBaseRC = "apicSetBase";
2410	ApicReg.pszGetBaseRC = "apicGetBase";
2411	ApicReg.pszSetTPRRC = "apicSetTPR";
2412	ApicReg.pszGetTPRRC = "apicGetTPR";
2413	ApicReg.pszWriteMSRRC = "apicWriteMSR";
2414	ApicReg.pszReadMSRRC = "apicReadMSR";
2415	ApicReg.pszBusDeliverRC = "apicBusDeliverCallback";
2416	ApicReg.pszLocalInterruptRC = "apicLocalInterrupt";
2417	} else {
2418	ApicReg.pszGetInterruptRC = NULL;
2419	ApicReg.pszHasPendingIrqRC = NULL;
2420	ApicReg.pszSetBaseRC = NULL;
2421	ApicReg.pszGetBaseRC = NULL;
2422	ApicReg.pszSetTPRRC = NULL;
2423	ApicReg.pszGetTPRRC = NULL;
2424	ApicReg.pszWriteMSRRC = NULL;
2425	ApicReg.pszReadMSRRC = NULL;
2426	ApicReg.pszBusDeliverRC = NULL;
2427	ApicReg.pszLocalInterruptRC = NULL;
2428	}
2429	if (fR0Enabled) {
2430	ApicReg.pszGetInterruptR0 = "apicGetInterrupt";
2431	ApicReg.pszHasPendingIrqR0 = "apicHasPendingIrq";
2432	ApicReg.pszSetBaseR0 = "apicSetBase";
2433	ApicReg.pszGetBaseR0 = "apicGetBase";
2434	ApicReg.pszSetTPRR0 = "apicSetTPR";
2435	ApicReg.pszGetTPRR0 = "apicGetTPR";
2436	ApicReg.pszWriteMSRR0 = "apicWriteMSR";
2437	ApicReg.pszReadMSRR0 = "apicReadMSR";
2438	ApicReg.pszBusDeliverR0 = "apicBusDeliverCallback";
2439	ApicReg.pszLocalInterruptR0 = "apicLocalInterrupt";
2440	} else {
2441	ApicReg.pszGetInterruptR0 = NULL;
2442	ApicReg.pszHasPendingIrqR0 = NULL;
2443	ApicReg.pszSetBaseR0 = NULL;
2444	ApicReg.pszGetBaseR0 = NULL;
2445	ApicReg.pszSetTPRR0 = NULL;
2446	ApicReg.pszGetTPRR0 = NULL;
2447	ApicReg.pszWriteMSRR0 = NULL;
2448	ApicReg.pszReadMSRR0 = NULL;
2449	ApicReg.pszBusDeliverR0 = NULL;
2450	ApicReg.pszLocalInterruptR0 = NULL;
2451	}
2452
2453	rc = PDMDevHlpAPICRegister(pDevIns, &ApicReg, &pThis->pApicHlpR3);
2454	AssertLogRelRCReturn(rc, rc);
2455	pThis->pCritSectR3 = pThis->pApicHlpR3->pfnGetR3CritSect(pDevIns);
2456
2457	/*
2458	* The the CPUID feature bit.
2459	*/
2460	/** @todo r=bird: See remark in the apicReset. */
2461	uint32_t u32Eax, u32Ebx, u32Ecx, u32Edx;
2462	PDMDevHlpGetCpuId(pDevIns, 0, &u32Eax, &u32Ebx, &u32Ecx, &u32Edx);
2463	if (u32Eax >= 1) {
2464	if ( fIoApic /* If IOAPIC is enabled, enable Local APIC in any case */
2465	\|\| ( u32Ebx == X86_CPUID_VENDOR_INTEL_EBX
2466	&& u32Ecx == X86_CPUID_VENDOR_INTEL_ECX
2467	&& u32Edx == X86_CPUID_VENDOR_INTEL_EDX /* GenuineIntel */)
2468	\|\| ( u32Ebx == X86_CPUID_VENDOR_AMD_EBX
2469	&& u32Ecx == X86_CPUID_VENDOR_AMD_ECX
2470	&& u32Edx == X86_CPUID_VENDOR_AMD_EDX /* AuthenticAMD */)) {
2471	LogRel(("Activating Local APIC\n"));
2472	pThis->pApicHlpR3->pfnChangeFeature(pDevIns, pThis->enmVersion);
2473	}
2474	}
2475
2476	/*
2477	* Register the MMIO range.
2478	* @todo: shall reregister, if base changes.
2479	*/
2480	uint32_t ApicBase = pThis->paLapicsR3[0].apicbase & ~0xfff;
2481	rc = PDMDevHlpMMIORegister(pDevIns, ApicBase, 0x1000, pThis,
2482	apicMMIOWrite, apicMMIORead, NULL, "APIC Memory");
2483	if (RT_FAILURE(rc))
2484	return rc;
2485
2486	if (fGCEnabled) {
2487	pThis->pApicHlpRC = pThis->pApicHlpR3->pfnGetRCHelpers(pDevIns);
2488	pThis->pCritSectRC = pThis->pApicHlpR3->pfnGetRCCritSect(pDevIns);
2489
2490	rc = PDMDevHlpMMIORegisterRC(pDevIns, ApicBase, 0x1000, 0,
2491	"apicMMIOWrite", "apicMMIORead", NULL);
2492	if (RT_FAILURE(rc))
2493	return rc;
2494	}
2495
2496	if (fR0Enabled) {
2497	pThis->pApicHlpR0 = pThis->pApicHlpR3->pfnGetR0Helpers(pDevIns);
2498	pThis->pCritSectR0 = pThis->pApicHlpR3->pfnGetR0CritSect(pDevIns);
2499
2500	rc = PDMDevHlpMMIORegisterR0(pDevIns, ApicBase, 0x1000, 0,
2501	"apicMMIOWrite", "apicMMIORead", NULL);
2502	if (RT_FAILURE(rc))
2503	return rc;
2504	}
2505
2506	/*
2507	* Create the APIC timers.
2508	*/
2509	for (i = 0; i < cCpus; i++) {
2510	APICState *pApic = &pThis->paLapicsR3[i];
2511	pApic->pszDesc = MMR3HeapAPrintf(pVM, MM_TAG_PDM_DEVICE_USER, "APIC Timer #%u", i);
2512	rc = PDMDevHlpTMTimerCreate(pDevIns, TMCLOCK_VIRTUAL_SYNC, apicTimerCallback, pApic,
2513	TMTIMER_FLAGS_NO_CRIT_SECT, pApic->pszDesc, &pApic->pTimerR3);
2514	if (RT_FAILURE(rc))
2515	return rc;
2516	pApic->pTimerR0 = TMTimerR0Ptr(pApic->pTimerR3);
2517	pApic->pTimerRC = TMTimerRCPtr(pApic->pTimerR3);
2518	TMR3TimerSetCritSect(pApic->pTimerR3, pThis->pCritSectR3);
2519	}
2520
2521	/*
2522	* Saved state.
2523	*/
2524	rc = PDMDevHlpSSMRegister3(pDevIns, APIC_SAVED_STATE_VERSION, sizeof(*pThis),
2525	apicLiveExec, apicSaveExec, apicLoadExec);
2526	if (RT_FAILURE(rc))
2527	return rc;
2528
2529	/*
2530	* Register debugger info callback.
2531	*/
2532	PDMDevHlpDBGFInfoRegister(pDevIns, "lapic", "Display Local APIC state for current CPU. "
2533	"Recognizes 'basic', 'lvt', 'timer' as arguments, defaulting to 'basic'.", lapicInfo);
2534
2535	#ifdef VBOX_WITH_STATISTICS
2536	/*
2537	* Statistics.
2538	*/
2539	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMMIOReadGC, STAMTYPE_COUNTER, "/Devices/APIC/MMIOReadGC", STAMUNIT_OCCURENCES, "Number of APIC MMIO reads in GC.");
2540	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMMIOReadHC, STAMTYPE_COUNTER, "/Devices/APIC/MMIOReadHC", STAMUNIT_OCCURENCES, "Number of APIC MMIO reads in HC.");
2541	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMMIOWriteGC, STAMTYPE_COUNTER, "/Devices/APIC/MMIOWriteGC", STAMUNIT_OCCURENCES, "Number of APIC MMIO writes in GC.");
2542	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMMIOWriteHC, STAMTYPE_COUNTER, "/Devices/APIC/MMIOWriteHC", STAMUNIT_OCCURENCES, "Number of APIC MMIO writes in HC.");
2543	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatClearedActiveIrq,STAMTYPE_COUNTER, "/Devices/APIC/MaskedActiveIRQ", STAMUNIT_OCCURENCES, "Number of cleared irqs.");
2544	for (i = 0; i < cCpus; i++) {
2545	APICState *pApic = &pThis->paLapicsR3[i];
2546	PDMDevHlpSTAMRegisterF(pDevIns, &pApic->StatTimerSetInitialCount, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, "Calls to apicTimerSetInitialCount.", "/Devices/APIC/%u/TimerSetInitialCount", i);
2547	PDMDevHlpSTAMRegisterF(pDevIns, &pApic->StatTimerSetInitialCountArm, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, "TMTimerSetRelative calls.", "/Devices/APIC/%u/TimerSetInitialCount/Arm", i);
2548	PDMDevHlpSTAMRegisterF(pDevIns, &pApic->StatTimerSetInitialCountDisarm, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, "TMTimerStop calls.", "/Devices/APIC/%u/TimerSetInitialCount/Disasm", i);
2549	PDMDevHlpSTAMRegisterF(pDevIns, &pApic->StatTimerSetLvt, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, "Calls to apicTimerSetLvt.", "/Devices/APIC/%u/TimerSetLvt", i);
2550	PDMDevHlpSTAMRegisterF(pDevIns, &pApic->StatTimerSetLvtClearPeriodic, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, "Clearing APIC_LVT_TIMER_PERIODIC.", "/Devices/APIC/%u/TimerSetLvt/ClearPeriodic", i);
2551	PDMDevHlpSTAMRegisterF(pDevIns, &pApic->StatTimerSetLvtPostponed, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, "TMTimerStop postponed.", "/Devices/APIC/%u/TimerSetLvt/Postponed", i);
2552	PDMDevHlpSTAMRegisterF(pDevIns, &pApic->StatTimerSetLvtArmed, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, "TMTimerSet avoided.", "/Devices/APIC/%u/TimerSetLvt/Armed", i);
2553	PDMDevHlpSTAMRegisterF(pDevIns, &pApic->StatTimerSetLvtArm, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, "TMTimerSet necessary.", "/Devices/APIC/%u/TimerSetLvt/Arm", i);
2554	PDMDevHlpSTAMRegisterF(pDevIns, &pApic->StatTimerSetLvtArmRetries, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, "TMTimerSet retries.", "/Devices/APIC/%u/TimerSetLvt/ArmRetries", i);
2555	PDMDevHlpSTAMRegisterF(pDevIns, &pApic->StatTimerSetLvtNoRelevantChange,STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, "No relevant flags changed.", "/Devices/APIC/%u/TimerSetLvt/NoRelevantChange", i);
2556	}
2557	#endif
2558
2559	return VINF_SUCCESS;
2560	}
2561
2562
2563	/**
2564	* APIC device registration structure.
2565	*/
2566	const PDMDEVREG g_DeviceAPIC =
2567	{
2568	/* u32Version */
2569	PDM_DEVREG_VERSION,
2570	/* szName */
2571	"apic",
2572	/* szRCMod */
2573	"VBoxDD2GC.gc",
2574	/* szR0Mod */
2575	"VBoxDD2R0.r0",
2576	/* pszDescription */
2577	"Advanced Programmable Interrupt Controller (APIC) Device",
2578	/* fFlags */
2579	PDM_DEVREG_FLAGS_HOST_BITS_DEFAULT \| PDM_DEVREG_FLAGS_GUEST_BITS_32_64 \| PDM_DEVREG_FLAGS_PAE36 \| PDM_DEVREG_FLAGS_RC \| PDM_DEVREG_FLAGS_R0,
2580	/* fClass */
2581	PDM_DEVREG_CLASS_PIC,
2582	/* cMaxInstances */
2583	1,
2584	/* cbInstance */
2585	sizeof(APICState),
2586	/* pfnConstruct */
2587	apicConstruct,
2588	/* pfnDestruct */
2589	NULL,
2590	/* pfnRelocate */
2591	apicRelocate,
2592	/* pfnIOCtl */
2593	NULL,
2594	/* pfnPowerOn */
2595	NULL,
2596	/* pfnReset */
2597	apicReset,
2598	/* pfnSuspend */
2599	NULL,
2600	/* pfnResume */
2601	NULL,
2602	/* pfnAttach */
2603	NULL,
2604	/* pfnDetach */
2605	NULL,
2606	/* pfnQueryInterface. */
2607	NULL,
2608	/* pfnInitComplete */
2609	NULL,
2610	/* pfnPowerOff */
2611	NULL,
2612	/* pfnSoftReset */
2613	NULL,
2614	/* u32VersionEnd */
2615	PDM_DEVREG_VERSION
2616	};
2617
2618	#endif /* IN_RING3 */
2619
2620
2621	/* IOAPIC */
2622
2623	PDMBOTHCBDECL(int) ioapicMMIORead(PPDMDEVINS pDevIns, void pvUser, RTGCPHYS GCPhysAddr, void pv, unsigned cb)
2624	{
2625	IOAPICState s = PDMINS_2_DATA(pDevIns, IOAPICState );
2626	IOAPIC_LOCK(s, VINF_IOM_HC_MMIO_READ);
2627
2628	STAM_COUNTER_INC(&CTXSUFF(s->StatMMIORead));
2629	switch (cb) {
2630	case 1:
2631	(uint8_t )pv = ioapic_mem_readl(s, GCPhysAddr);
2632	break;
2633
2634	case 2:
2635	(uint16_t )pv = ioapic_mem_readl(s, GCPhysAddr);
2636	break;
2637
2638	case 4:
2639	(uint32_t )pv = ioapic_mem_readl(s, GCPhysAddr);
2640	break;
2641
2642	default:
2643	AssertReleaseMsgFailed(("cb=%d\n", cb)); /* for now we assume simple accesses. */
2644	IOAPIC_UNLOCK(s);
2645	return VERR_INTERNAL_ERROR;
2646	}
2647	IOAPIC_UNLOCK(s);
2648	return VINF_SUCCESS;
2649	}
2650
2651	PDMBOTHCBDECL(int) ioapicMMIOWrite(PPDMDEVINS pDevIns, void pvUser, RTGCPHYS GCPhysAddr, void pv, unsigned cb)
2652	{
2653	IOAPICState s = PDMINS_2_DATA(pDevIns, IOAPICState );
2654
2655	STAM_COUNTER_INC(&CTXSUFF(s->StatMMIOWrite));
2656	switch (cb) {
2657	case 1:
2658	case 2:
2659	case 4:
2660	IOAPIC_LOCK(s, VINF_IOM_HC_MMIO_WRITE);
2661	ioapic_mem_writel(s, GCPhysAddr, (uint32_t )pv);
2662	IOAPIC_UNLOCK(s);
2663	break;
2664
2665	default:
2666	AssertReleaseMsgFailed(("cb=%d\n", cb)); /* for now we assume simple accesses. */
2667	return VERR_INTERNAL_ERROR;
2668	}
2669	return VINF_SUCCESS;
2670	}
2671
2672	PDMBOTHCBDECL(void) ioapicSetIrq(PPDMDEVINS pDevIns, int iIrq, int iLevel)
2673	{
2674	/* PDM lock is taken here; @todo add assertion */
2675	IOAPICState pThis = PDMINS_2_DATA(pDevIns, IOAPICState );
2676	STAM_COUNTER_INC(&pThis->CTXSUFF(StatSetIrq));
2677	LogFlow(("ioapicSetIrq: iIrq=%d iLevel=%d\n", iIrq, iLevel));
2678	ioapic_set_irq(pThis, iIrq, iLevel);
2679	}
2680
2681	PDMBOTHCBDECL(void) ioapicSendMsi(PPDMDEVINS pDevIns, RTGCPHYS GCAddr, uint32_t uValue)
2682	{
2683	IOAPICState pThis = PDMINS_2_DATA(pDevIns, IOAPICState );
2684
2685	LogFlow(("ioapicSendMsi: Address=%p uValue=%\n", GCAddr, uValue));
2686
2687	uint8_t dest = (GCAddr & VBOX_MSI_ADDR_DEST_ID_MASK) >> VBOX_MSI_ADDR_DEST_ID_SHIFT;
2688	uint8_t vector_num = (uValue & VBOX_MSI_DATA_VECTOR_MASK) >> VBOX_MSI_DATA_VECTOR_SHIFT;
2689	uint8_t dest_mode = (GCAddr >> VBOX_MSI_ADDR_DEST_MODE_SHIFT) & 0x1;
2690	uint8_t trigger_mode = (uValue >> VBOX_MSI_DATA_TRIGGER_SHIFT) & 0x1;
2691	uint8_t delivery_mode = (uValue >> VBOX_MSI_DATA_DELIVERY_MODE_SHIFT) & 0x7;
2692	/**
2693	* This bit indicates whether the message should be directed to the
2694	* processor with the lowest interrupt priority among
2695	* processors that can receive the interrupt, ignored ATM.
2696	*/
2697	uint8_t redir_hint = (GCAddr >> VBOX_MSI_ADDR_REDIRECTION_SHIFT) & 0x1;
2698
2699	int rc = pThis->CTX_SUFF(pIoApicHlp)->pfnApicBusDeliver(pDevIns,
2700	dest,
2701	dest_mode,
2702	delivery_mode,
2703	vector_num,
2704	0 /* polarity, n/a */,
2705	trigger_mode);
2706	/* We must be sure that attempts to reschedule in R3
2707	never get here */
2708	Assert(rc == VINF_SUCCESS);
2709	}
2710
2711	#ifdef IN_RING3
2712
2713	/**
2714	* Info handler, device version. Dumps I/O APIC state.
2715	*
2716	* @param pDevIns Device instance which registered the info.
2717	* @param pHlp Callback functions for doing output.
2718	* @param pszArgs Argument string. Optional and specific to the handler.
2719	*/
2720	static DECLCALLBACK(void) ioapicInfo(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
2721	{
2722	IOAPICState s = PDMINS_2_DATA(pDevIns, IOAPICState );
2723	uint32_t val;
2724	unsigned i;
2725	unsigned max_redir;
2726
2727	pHlp->pfnPrintf(pHlp, "I/O APIC at %08X:\n", 0xfec00000);
2728	val = s->id << 24; /* Would be nice to call ioapic_mem_readl() directly, but that's not so simple. */
2729	pHlp->pfnPrintf(pHlp, " IOAPICID : %08X\n", val);
2730	pHlp->pfnPrintf(pHlp, " APIC ID = %02X\n", (val >> 24) & 0xff);
2731	val = 0x11 \| ((IOAPIC_NUM_PINS - 1) << 16);
2732	max_redir = (val >> 16) & 0xff;
2733	pHlp->pfnPrintf(pHlp, " IOAPICVER : %08X\n", val);
2734	pHlp->pfnPrintf(pHlp, " version = %02X\n", val & 0xff);
2735	pHlp->pfnPrintf(pHlp, " redirs = %d\n", ((val >> 16) & 0xff) + 1);
2736	val = 0;
2737	pHlp->pfnPrintf(pHlp, " IOAPICARB : %08X\n", val);
2738	pHlp->pfnPrintf(pHlp, " arb ID = %02X\n", (val >> 24) & 0xff);
2739	Assert(sizeof(s->ioredtbl) / sizeof(s->ioredtbl[0]) > max_redir);
2740	pHlp->pfnPrintf(pHlp, "I/O redirection table\n");
2741	pHlp->pfnPrintf(pHlp, " idx dst_mode dst_addr mask trigger rirr polarity dlvr_st dlvr_mode vector\n");
2742	for (i = 0; i <= max_redir; ++i)
2743	{
2744	static const char *dmodes[] = { "Fixed ", "LowPri", "SMI ", "Resrvd",
2745	"NMI ", "INIT ", "Resrvd", "ExtINT" };
2746
2747	pHlp->pfnPrintf(pHlp, " %02d %s %02X %d %s %d %s %s %s %3d (%016llX)\n",
2748	i,
2749	s->ioredtbl[i] & (1 << 11) ? "log " : "phys", /* dest mode */
2750	(int)(s->ioredtbl[i] >> 56), /* dest addr */
2751	(int)(s->ioredtbl[i] >> 16) & 1, /* mask */
2752	s->ioredtbl[i] & (1 << 15) ? "level" : "edge ", /* trigger */
2753	(int)(s->ioredtbl[i] >> 14) & 1, /* remote IRR */
2754	s->ioredtbl[i] & (1 << 13) ? "activelo" : "activehi", /* polarity */
2755	s->ioredtbl[i] & (1 << 12) ? "pend" : "idle", /* delivery status */
2756	dmodes[(s->ioredtbl[i] >> 8) & 0x07], /* delivery mode */
2757	(int)s->ioredtbl[i] & 0xff, /* vector */
2758	s->ioredtbl[i] /* entire register */
2759	);
2760	}
2761	}
2762
2763	/**
2764	* @copydoc FNSSMDEVSAVEEXEC
2765	*/
2766	static DECLCALLBACK(int) ioapicSaveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
2767	{
2768	IOAPICState s = PDMINS_2_DATA(pDevIns, IOAPICState );
2769	ioapic_save(pSSM, s);
2770	return VINF_SUCCESS;
2771	}
2772
2773	/**
2774	* @copydoc FNSSMDEVLOADEXEC
2775	*/
2776	static DECLCALLBACK(int) ioapicLoadExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
2777	{
2778	IOAPICState s = PDMINS_2_DATA(pDevIns, IOAPICState );
2779
2780	if (ioapic_load(pSSM, s, uVersion)) {
2781	AssertFailed();
2782	return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
2783	}
2784	Assert(uPass == SSM_PASS_FINAL); NOREF(uPass);
2785
2786	return VINF_SUCCESS;
2787	}
2788
2789	/**
2790	* @copydoc FNPDMDEVRESET
2791	*/
2792	static DECLCALLBACK(void) ioapicReset(PPDMDEVINS pDevIns)
2793	{
2794	IOAPICState s = PDMINS_2_DATA(pDevIns, IOAPICState );
2795	s->pIoApicHlpR3->pfnLock(pDevIns, VERR_INTERNAL_ERROR);
2796	ioapic_reset(s);
2797	IOAPIC_UNLOCK(s);
2798	}
2799
2800	/**
2801	* @copydoc FNPDMDEVRELOCATE
2802	*/
2803	static DECLCALLBACK(void) ioapicRelocate(PPDMDEVINS pDevIns, RTGCINTPTR offDelta)
2804	{
2805	IOAPICState s = PDMINS_2_DATA(pDevIns, IOAPICState );
2806	s->pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
2807	s->pIoApicHlpRC = s->pIoApicHlpR3->pfnGetRCHelpers(pDevIns);
2808	}
2809
2810	/**
2811	* @copydoc FNPDMDEVCONSTRUCT
2812	*/
2813	static DECLCALLBACK(int) ioapicConstruct(PPDMDEVINS pDevIns, int iInstance, PCFGMNODE pCfg)
2814	{
2815	IOAPICState s = PDMINS_2_DATA(pDevIns, IOAPICState );
2816	PDMIOAPICREG IoApicReg;
2817	bool fGCEnabled;
2818	bool fR0Enabled;
2819	int rc;
2820
2821	Assert(iInstance == 0);
2822
2823	/*
2824	* Validate and read the configuration.
2825	*/
2826	if (!CFGMR3AreValuesValid(pCfg, "GCEnabled\0" "R0Enabled\0"))
2827	return VERR_PDM_DEVINS_UNKNOWN_CFG_VALUES;
2828
2829	rc = CFGMR3QueryBoolDef(pCfg, "GCEnabled", &fGCEnabled, true);
2830	if (RT_FAILURE(rc))
2831	return PDMDEV_SET_ERROR(pDevIns, rc,
2832	N_("Configuration error: Failed to query boolean value \"GCEnabled\""));
2833
2834	rc = CFGMR3QueryBoolDef(pCfg, "R0Enabled", &fR0Enabled, true);
2835	if (RT_FAILURE(rc))
2836	return PDMDEV_SET_ERROR(pDevIns, rc,
2837	N_("Configuration error: Failed to query boolean value \"R0Enabled\""));
2838	Log(("IOAPIC: fR0Enabled=%RTbool fGCEnabled=%RTbool\n", fR0Enabled, fGCEnabled));
2839
2840	/*
2841	* Initialize the state data.
2842	*/
2843
2844	s->pDevInsR3 = pDevIns;
2845	s->pDevInsR0 = PDMDEVINS_2_R0PTR(pDevIns);
2846	s->pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
2847	ioapic_reset(s);
2848	s->id = 0;
2849
2850	/*
2851	* Register the IOAPIC and get helpers.
2852	*/
2853	IoApicReg.u32Version = PDM_IOAPICREG_VERSION;
2854	IoApicReg.pfnSetIrqR3 = ioapicSetIrq;
2855	IoApicReg.pszSetIrqRC = fGCEnabled ? "ioapicSetIrq" : NULL;
2856	IoApicReg.pszSetIrqR0 = fR0Enabled ? "ioapicSetIrq" : NULL;
2857	IoApicReg.pfnSendMsiR3 = ioapicSendMsi;
2858	IoApicReg.pszSendMsiRC = fGCEnabled ? "ioapicSendMsi" : NULL;
2859	IoApicReg.pszSendMsiR0 = fR0Enabled ? "ioapicSendMsi" : NULL;
2860
2861	rc = PDMDevHlpIOAPICRegister(pDevIns, &IoApicReg, &s->pIoApicHlpR3);
2862	if (RT_FAILURE(rc))
2863	{
2864	AssertMsgFailed(("IOAPICRegister -> %Rrc\n", rc));
2865	return rc;
2866	}
2867
2868	/*
2869	* Register MMIO callbacks and saved state.
2870	*/
2871	rc = PDMDevHlpMMIORegister(pDevIns, 0xfec00000, 0x1000, s,
2872	ioapicMMIOWrite, ioapicMMIORead, NULL, "I/O APIC Memory");
2873	if (RT_FAILURE(rc))
2874	return rc;
2875
2876	if (fGCEnabled) {
2877	s->pIoApicHlpRC = s->pIoApicHlpR3->pfnGetRCHelpers(pDevIns);
2878
2879	rc = PDMDevHlpMMIORegisterRC(pDevIns, 0xfec00000, 0x1000, 0,
2880	"ioapicMMIOWrite", "ioapicMMIORead", NULL);
2881	if (RT_FAILURE(rc))
2882	return rc;
2883	}
2884
2885	if (fR0Enabled) {
2886	s->pIoApicHlpR0 = s->pIoApicHlpR3->pfnGetR0Helpers(pDevIns);
2887
2888	rc = PDMDevHlpMMIORegisterR0(pDevIns, 0xfec00000, 0x1000, 0,
2889	"ioapicMMIOWrite", "ioapicMMIORead", NULL);
2890	if (RT_FAILURE(rc))
2891	return rc;
2892	}
2893
2894	rc = PDMDevHlpSSMRegister(pDevIns, 1 /* version /, sizeof(s), ioapicSaveExec, ioapicLoadExec);
2895	if (RT_FAILURE(rc))
2896	return rc;
2897
2898	/*
2899	* Register debugger info callback.
2900	*/
2901	PDMDevHlpDBGFInfoRegister(pDevIns, "ioapic", "Display I/O APIC state.", ioapicInfo);
2902
2903	#ifdef VBOX_WITH_STATISTICS
2904	/*
2905	* Statistics.
2906	*/
2907	PDMDevHlpSTAMRegister(pDevIns, &s->StatMMIOReadGC, STAMTYPE_COUNTER, "/Devices/IOAPIC/MMIOReadGC", STAMUNIT_OCCURENCES, "Number of IOAPIC MMIO reads in GC.");
2908	PDMDevHlpSTAMRegister(pDevIns, &s->StatMMIOReadHC, STAMTYPE_COUNTER, "/Devices/IOAPIC/MMIOReadHC", STAMUNIT_OCCURENCES, "Number of IOAPIC MMIO reads in HC.");
2909	PDMDevHlpSTAMRegister(pDevIns, &s->StatMMIOWriteGC, STAMTYPE_COUNTER, "/Devices/IOAPIC/MMIOWriteGC", STAMUNIT_OCCURENCES, "Number of IOAPIC MMIO writes in GC.");
2910	PDMDevHlpSTAMRegister(pDevIns, &s->StatMMIOWriteHC, STAMTYPE_COUNTER, "/Devices/IOAPIC/MMIOWriteHC", STAMUNIT_OCCURENCES, "Number of IOAPIC MMIO writes in HC.");
2911	PDMDevHlpSTAMRegister(pDevIns, &s->StatSetIrqGC, STAMTYPE_COUNTER, "/Devices/IOAPIC/SetIrqGC", STAMUNIT_OCCURENCES, "Number of IOAPIC SetIrq calls in GC.");
2912	PDMDevHlpSTAMRegister(pDevIns, &s->StatSetIrqHC, STAMTYPE_COUNTER, "/Devices/IOAPIC/SetIrqHC", STAMUNIT_OCCURENCES, "Number of IOAPIC SetIrq calls in HC.");
2913	#endif
2914
2915	return VINF_SUCCESS;
2916	}
2917
2918	/**
2919	* IO APIC device registration structure.
2920	*/
2921	const PDMDEVREG g_DeviceIOAPIC =
2922	{
2923	/* u32Version */
2924	PDM_DEVREG_VERSION,
2925	/* szName */
2926	"ioapic",
2927	/* szRCMod */
2928	"VBoxDD2GC.gc",
2929	/* szR0Mod */
2930	"VBoxDD2R0.r0",
2931	/* pszDescription */
2932	"I/O Advanced Programmable Interrupt Controller (IO-APIC) Device",
2933	/* fFlags */
2934	PDM_DEVREG_FLAGS_HOST_BITS_DEFAULT \| PDM_DEVREG_FLAGS_GUEST_BITS_32_64 \| PDM_DEVREG_FLAGS_PAE36 \| PDM_DEVREG_FLAGS_RC \| PDM_DEVREG_FLAGS_R0,
2935	/* fClass */
2936	PDM_DEVREG_CLASS_PIC,
2937	/* cMaxInstances */
2938	1,
2939	/* cbInstance */
2940	sizeof(IOAPICState),
2941	/* pfnConstruct */
2942	ioapicConstruct,
2943	/* pfnDestruct */
2944	NULL,
2945	/* pfnRelocate */
2946	ioapicRelocate,
2947	/* pfnIOCtl */
2948	NULL,
2949	/* pfnPowerOn */
2950	NULL,
2951	/* pfnReset */
2952	ioapicReset,
2953	/* pfnSuspend */
2954	NULL,
2955	/* pfnResume */
2956	NULL,
2957	/* pfnAttach */
2958	NULL,
2959	/* pfnDetach */
2960	NULL,
2961	/* pfnQueryInterface. */
2962	NULL,
2963	/* pfnInitComplete */
2964	NULL,
2965	/* pfnPowerOff */
2966	NULL,
2967	/* pfnSoftReset */
2968	NULL,
2969	/* u32VersionEnd */
2970	PDM_DEVREG_VERSION
2971	};
2972
2973	#endif /* IN_RING3 */
2974	#endif /* !VBOX_DEVICE_STRUCT_TESTCASE */

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source: vbox/trunk/src/VBox/Devices/PC/DevAPIC.cpp@ 34906

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