VirtualBox

source: vbox/trunk/src/VBox/Devices/PC/DevAPIC.cpp@ 14831

Last change on this file since 14831 was 13832, checked in by vboxsync, 16 years ago

IN_GC -> IN_RC.
  • Property svn:eol-style set to native
  • Property svn:keywords set to Id
File size: 80.2 KB
Line 
1#ifdef VBOX
2/* $Id: DevAPIC.cpp 13832 2008-11-05 02:01:12Z vboxsync $ */
3/** @file
4 * Advanced Programmable Interrupt Controller (APIC) Device and
5 * I/O Advanced Programmable Interrupt Controller (IO-APIC) Device.
6 */
7
8/*
9 * Copyright (C) 2006-2007 Sun Microsystems, Inc.
10 *
11 * This file is part of VirtualBox Open Source Edition (OSE), as
12 * available from http://www.virtualbox.org. This file is free software;
13 * you can redistribute it and/or modify it under the terms of the GNU
14 * General Public License (GPL) as published by the Free Software
15 * Foundation, in version 2 as it comes in the "COPYING" file of the
16 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
17 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
18 *
19 * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
20 * Clara, CA 95054 USA or visit http://www.sun.com if you need
21 * additional information or have any questions.
22 * --------------------------------------------------------------------
23 *
24 * This code is based on:
25 *
26 * apic.c revision 1.5 @@OSETODO
27 */
28
29/*******************************************************************************
30* Header Files *
31*******************************************************************************/
32#define LOG_GROUP LOG_GROUP_DEV_APIC
33#include <VBox/pdmdev.h>
34
35#include <VBox/log.h>
36#include <VBox/stam.h>
37#include <iprt/assert.h>
38#include <iprt/asm.h>
39
40#include "Builtins2.h"
41#include "vl_vbox.h"
42
43#define MSR_IA32_APICBASE 0x1b
44#define MSR_IA32_APICBASE_BSP (1<<8)
45#define MSR_IA32_APICBASE_ENABLE (1<<11)
46#ifdef VBOX
47#define MSR_IA32_APICBASE_X2ENABLE (1<<10)
48#endif
49#define MSR_IA32_APICBASE_BASE (0xfffff<<12)
50
51#ifndef EINVAL
52# define EINVAL 1
53#endif
54
55#ifdef _MSC_VER
56# pragma warning(disable:4244)
57#endif
58
59/** @def APIC_LOCK
60 * Acquires the PDM lock. */
61#define APIC_LOCK(pThis, rc) \
62 do { \
63 int rc2 = (pThis)->CTX_SUFF(pApicHlp)->pfnLock((pThis)->CTX_SUFF(pDevIns), rc); \
64 if (rc2 != VINF_SUCCESS) \
65 return rc2; \
66 } while (0)
67
68/** @def APIC_LOCK_VOID
69 * Acquires the PDM lock and does not expect failure (i.e. ring-3 only!). */
70#define APIC_LOCK_VOID(pThis, rc) \
71 do { \
72 int rc2 = (pThis)->CTX_SUFF(pApicHlp)->pfnLock((pThis)->CTX_SUFF(pDevIns), rc); \
73 AssertLogRelRCReturnVoid(rc2); \
74 } while (0)
75
76/** @def APIC_UNLOCK
77 * Releases the PDM lock. */
78#define APIC_UNLOCK(pThis) \
79 (pThis)->CTX_SUFF(pApicHlp)->pfnUnlock((pThis)->CTX_SUFF(pDevIns))
80
81/** @def IOAPIC_LOCK
82 * Acquires the PDM lock. */
83#define IOAPIC_LOCK(pThis, rc) \
84 do { \
85 int rc2 = (pThis)->CTX_SUFF(pIoApicHlp)->pfnLock((pThis)->CTX_SUFF(pDevIns), rc); \
86 if (rc2 != VINF_SUCCESS) \
87 return rc2; \
88 } while (0)
89
90/** @def IOAPIC_UNLOCK
91 * Releases the PDM lock. */
92#define IOAPIC_UNLOCK(pThis) (pThis)->CTX_SUFF(pIoApicHlp)->pfnUnlock((pThis)->CTX_SUFF(pDevIns))
93
94/** @def LAPIC_BASE
95 * Return address of first LAPIC state. */
96#define LAPIC_BASE(pThis) ((APICState*)(pThis)->CTX_SUFF(pLapics))
97
98#define foreach_apic(dev, mask, code) \
99 do { \
100 uint32_t i; \
101 APICState* apic = LAPIC_BASE(dev); \
102 for (i = 0; i < dev->cCpus; i++) \
103 { \
104 if (mask & (1 << (apic->id))) \
105 { \
106 code; \
107 } \
108 apic++; \
109 } \
110 } while (0)
111
112# define set_bit(pvBitmap, iBit) ASMBitSet(pvBitmap, iBit)
113# define reset_bit(pvBitmap, iBit) ASMBitClear(pvBitmap, iBit)
114# define fls_bit(value) (ASMBitLastSetU32(value) - 1)
115# define ffs_bit(value) (ASMBitFirstSetU32(value) - 1)
116
117#endif /* VBOX */
118
119/*
120 * APIC support
121 *
122 * Copyright (c) 2004-2005 Fabrice Bellard
123 *
124 * This library is free software; you can redistribute it and/or
125 * modify it under the terms of the GNU Lesser General Public
126 * License as published by the Free Software Foundation; either
127 * version 2 of the License, or (at your option) any later version.
128 *
129 * This library is distributed in the hope that it will be useful,
130 * but WITHOUT ANY WARRANTY; without even the implied warranty of
131 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
132 * Lesser General Public License for more details.
133 *
134 * You should have received a copy of the GNU Lesser General Public
135 * License along with this library; if not, write to the Free Software
136 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
137 */
138#ifndef VBOX
139#include "vl.h"
140#endif
141
142#define DEBUG_APIC
143#define DEBUG_IOAPIC
144
145/* APIC Local Vector Table */
146#define APIC_LVT_TIMER 0
147#define APIC_LVT_THERMAL 1
148#define APIC_LVT_PERFORM 2
149#define APIC_LVT_LINT0 3
150#define APIC_LVT_LINT1 4
151#define APIC_LVT_ERROR 5
152#define APIC_LVT_NB 6
153
154/* APIC delivery modes */
155#define APIC_DM_FIXED 0
156#define APIC_DM_LOWPRI 1
157#define APIC_DM_SMI 2
158#define APIC_DM_NMI 4
159#define APIC_DM_INIT 5
160#define APIC_DM_SIPI 6
161#define APIC_DM_EXTINT 7
162
163/* APIC destination mode */
164#define APIC_DESTMODE_FLAT 0xf
165#define APIC_DESTMODE_CLUSTER 1
166
167#define APIC_TRIGGER_EDGE 0
168#define APIC_TRIGGER_LEVEL 1
169
170#define APIC_LVT_TIMER_PERIODIC (1<<17)
171#define APIC_LVT_MASKED (1<<16)
172#define APIC_LVT_LEVEL_TRIGGER (1<<15)
173#define APIC_LVT_REMOTE_IRR (1<<14)
174#define APIC_INPUT_POLARITY (1<<13)
175#define APIC_SEND_PENDING (1<<12)
176
177#define IOAPIC_NUM_PINS 0x18
178
179#define ESR_ILLEGAL_ADDRESS (1 << 7)
180
181#define APIC_SV_ENABLE (1 << 8)
182
183#ifdef VBOX
184#define APIC_MAX_PATCH_ATTEMPTS 100
185
186typedef uint32_t PhysApicId;
187typedef uint32_t LogApicId;
188#endif
189
190typedef struct APICState {
191#ifndef VBOX
192 CPUState *cpu_env;
193#endif /* !VBOX */
194 uint32_t apicbase;
195#ifdef VBOX
196 /* Task priority register (interrupt level) */
197 uint32_t tpr;
198 /* Logical APIC id */
199 LogApicId id;
200 /* Physical APIC id */
201 PhysApicId phys_id;
202 /** @todo: is it logical or physical? Not really used anyway now. */
203 PhysApicId arb_id;
204#else
205 uint8_t tpr;
206 uint8_t id;
207 uint8_t arb_id;
208#endif
209 uint32_t spurious_vec;
210 uint8_t log_dest;
211 uint8_t dest_mode;
212 uint32_t isr[8]; /* in service register */
213 uint32_t tmr[8]; /* trigger mode register */
214 uint32_t irr[8]; /* interrupt request register */
215 uint32_t lvt[APIC_LVT_NB];
216 uint32_t esr; /* error register */
217 uint32_t icr[2];
218 uint32_t divide_conf;
219 int count_shift;
220 uint32_t initial_count;
221#ifdef VBOX
222 uint32_t Alignment0;
223#endif
224 int64_t initial_count_load_time, next_time;
225#ifndef VBOX
226 QEMUTimer *timer;
227 struct APICState *next_apic;
228#else
229 /** The APIC timer - R3 Ptr. */
230 PTMTIMERR3 pTimerR3;
231
232 /** The APIC timer - R0 Ptr. */
233 PTMTIMERR0 pTimerR0;
234
235 /** The APIC timer - RC Ptr. */
236 PTMTIMERRC pTimerRC;
237
238 /** Alignment */
239 uint32_t Alignment1;
240#endif /* VBOX */
241} APICState;
242
243struct IOAPICState {
244 uint8_t id;
245 uint8_t ioregsel;
246
247 uint32_t irr;
248 uint64_t ioredtbl[IOAPIC_NUM_PINS];
249
250#ifdef VBOX
251 /** The device instance - R3 Ptr. */
252 PPDMDEVINSR3 pDevInsR3;
253 /** The IOAPIC helpers - R3 Ptr. */
254 PCPDMIOAPICHLPR3 pIoApicHlpR3;
255
256 /** The device instance - R0 Ptr. */
257 PPDMDEVINSR0 pDevInsR0;
258 /** The IOAPIC helpers - R0 Ptr. */
259 PCPDMIOAPICHLPR0 pIoApicHlpR0;
260
261 /** The device instance - RC Ptr. */
262 PPDMDEVINSRC pDevInsRC;
263 /** The IOAPIC helpers - RC Ptr. */
264 PCPDMIOAPICHLPRC pIoApicHlpRC;
265
266# ifdef VBOX_WITH_STATISTICS
267 STAMCOUNTER StatMMIOReadGC;
268 STAMCOUNTER StatMMIOReadHC;
269 STAMCOUNTER StatMMIOWriteGC;
270 STAMCOUNTER StatMMIOWriteHC;
271 STAMCOUNTER StatSetIrqGC;
272 STAMCOUNTER StatSetIrqHC;
273# endif
274#endif /* VBOX */
275};
276
277#ifdef VBOX
278typedef struct IOAPICState IOAPICState;
279
280typedef struct
281{
282 /** The device instance - R3 Ptr. */
283 PPDMDEVINSR3 pDevInsR3;
284 /** The APIC helpers - R3 Ptr. */
285 PCPDMAPICHLPR3 pApicHlpR3;
286 /** LAPICs states - R3 Ptr */
287 RTR3PTR pLapicsR3;
288
289 /** The device instance - R0 Ptr. */
290 PPDMDEVINSR0 pDevInsR0;
291 /** The APIC helpers - R0 Ptr. */
292 PCPDMAPICHLPR0 pApicHlpR0;
293 /** LAPICs states - R0 Ptr */
294 RTR0PTR pLapicsR0;
295
296 /** The device instance - RC Ptr. */
297 PPDMDEVINSRC pDevInsRC;
298 /** The APIC helpers - RC Ptr. */
299 PCPDMAPICHLPRC pApicHlpRC;
300 /** LAPICs states - RC Ptr */
301 RTRCPTR pLapicsRC;
302
303 /** APIC specification version in this virtual hardware configuration. */
304 PDMAPICVERSION enmVersion;
305
306 /** Number of attempts made to optimize TPR accesses. */
307 uint32_t ulTPRPatchAttempts;
308
309 /** Number of CPUs on the system (same as LAPIC count). */
310 uint32_t cCpus;
311
312# ifdef VBOX_WITH_STATISTICS
313 STAMCOUNTER StatMMIOReadGC;
314 STAMCOUNTER StatMMIOReadHC;
315 STAMCOUNTER StatMMIOWriteGC;
316 STAMCOUNTER StatMMIOWriteHC;
317 STAMCOUNTER StatClearedActiveIrq;
318# endif
319} APICDeviceInfo;
320
321static void apic_eoi(APICDeviceInfo *dev, APICState* s);
322static void apic_deliver(APICDeviceInfo* dev, APICState *s,
323 uint8_t dest, uint8_t dest_mode,
324 uint8_t delivery_mode, uint8_t vector_num,
325 uint8_t polarity, uint8_t trigger_mode);
326static void apic_timer_update(APICDeviceInfo* dev, APICState *s,
327 int64_t current_time);
328static int apic_get_arb_pri(APICState *s);
329static int apic_get_ppr(APICState *s);
330static uint32_t apic_get_current_count(APICDeviceInfo* dev, APICState *s);
331
332
333DECLINLINE(APICState*) getLapicById(APICDeviceInfo* dev, VMCPUID id)
334{
335 AssertFatalMsg(id < dev->cCpus, ("CPU id %d out of range\n", id));
336 return LAPIC_BASE(dev) + id;
337}
338
339DECLINLINE(APICState*) getLapic(APICDeviceInfo* dev)
340{
341 /* LAPIC's array is indexed by CPU id */
342 VMCPUID id = dev->CTX_SUFF(pApicHlp)->pfnGetCpuId(dev->CTX_SUFF(pDevIns));
343 return getLapicById(dev, id);
344}
345
346DECLINLINE(VMCPUID) getCpuFromLapic(APICDeviceInfo* dev, APICState *s)
347{
348 /* for now we assume LAPIC physical id == CPU id */
349 return VMCPUID(s->phys_id);
350}
351
352DECLINLINE(void) cpuSetInterrupt(APICDeviceInfo* dev, APICState *s)
353{
354 dev->CTX_SUFF(pApicHlp)->pfnSetInterruptFF(dev->CTX_SUFF(pDevIns),
355 getCpuFromLapic(dev, s));
356}
357
358DECLINLINE(void) cpuClearInterrupt(APICDeviceInfo* dev, APICState *s)
359{
360 dev->CTX_SUFF(pApicHlp)->pfnClearInterruptFF(dev->CTX_SUFF(pDevIns),
361 getCpuFromLapic(dev, s));
362}
363
364DECLINLINE(uint32_t) getApicEnableBits(APICDeviceInfo* dev)
365{
366 switch (dev->enmVersion)
367 {
368 case PDMAPICVERSION_NONE:
369 return 0;
370 case PDMAPICVERSION_APIC:
371 return MSR_IA32_APICBASE_ENABLE;
372 case PDMAPICVERSION_X2APIC:
373 return MSR_IA32_APICBASE_ENABLE | MSR_IA32_APICBASE_X2ENABLE ;
374 default:
375 AssertMsgFailed(("Unsuported APIC version %d\n", dev->enmVersion));
376 return 0;
377 }
378}
379
380DECLINLINE(PDMAPICVERSION) getApicMode(APICState *apic)
381{
382 switch (((apic->apicbase) >> 10) & 0x3)
383 {
384 case 0:
385 return PDMAPICVERSION_NONE;
386 case 1:
387 default:
388 /* Invalid */
389 return PDMAPICVERSION_NONE;
390 case 2:
391 return PDMAPICVERSION_APIC;
392 case 3:
393 return PDMAPICVERSION_X2APIC;
394 }
395}
396
397#endif /* VBOX */
398
399#ifndef VBOX_DEVICE_STRUCT_TESTCASE
400#ifndef VBOX
401static int apic_io_memory;
402static APICState *first_local_apic = NULL;
403static int last_apic_id = 0;
404#endif /* !VBOX */
405
406static void apic_init_ipi(APICState *s);
407static void apic_set_irq(APICDeviceInfo* dev, APICState *s, int vector_num, int trigger_mode);
408static bool apic_update_irq(APICDeviceInfo* dev, APICState *s);
409
410#ifdef VBOX
411static uint32_t apic_get_delivery_bitmask(APICDeviceInfo* dev, uint8_t dest, uint8_t dest_mode);
412__BEGIN_DECLS
413PDMBOTHCBDECL(int) apicMMIORead(PPDMDEVINS pDevIns, void *pvUser, RTGCPHYS GCPhysAddr, void *pv, unsigned cb);
414PDMBOTHCBDECL(int) apicMMIOWrite(PPDMDEVINS pDevIns, void *pvUser, RTGCPHYS GCPhysAddr, void *pv, unsigned cb);
415PDMBOTHCBDECL(int) apicGetInterrupt(PPDMDEVINS pDevIns);
416PDMBOTHCBDECL(bool) apicHasPendingIrq(PPDMDEVINS pDevIns);
417PDMBOTHCBDECL(void) apicSetBase(PPDMDEVINS pDevIns, uint64_t val);
418PDMBOTHCBDECL(uint64_t) apicGetBase(PPDMDEVINS pDevIns);
419PDMBOTHCBDECL(void) apicSetTPR(PPDMDEVINS pDevIns, uint8_t val);
420PDMBOTHCBDECL(uint8_t) apicGetTPR(PPDMDEVINS pDevIns);
421PDMBOTHCBDECL(void) apicBusDeliverCallback(PPDMDEVINS pDevIns, uint8_t u8Dest, uint8_t u8DestMode,
422 uint8_t u8DeliveryMode, uint8_t iVector, uint8_t u8Polarity,
423 uint8_t u8TriggerMode);
424PDMBOTHCBDECL(int) apicWriteMSR(PPDMDEVINS pDevIns, VMCPUID iCpu, uint32_t u32Reg, uint64_t u64Value);
425PDMBOTHCBDECL(int) apicReadMSR(PPDMDEVINS pDevIns, VMCPUID iCpu, uint32_t u32Reg, uint64_t *pu64Value);
426PDMBOTHCBDECL(int) ioapicMMIORead(PPDMDEVINS pDevIns, void *pvUser, RTGCPHYS GCPhysAddr, void *pv, unsigned cb);
427PDMBOTHCBDECL(int) ioapicMMIOWrite(PPDMDEVINS pDevIns, void *pvUser, RTGCPHYS GCPhysAddr, void *pv, unsigned cb);
428PDMBOTHCBDECL(void) ioapicSetIrq(PPDMDEVINS pDevIns, int iIrq, int iLevel);
429
430static void apic_update_tpr(APICDeviceInfo *dev, APICState* s, uint32_t val);
431__END_DECLS
432#endif /* VBOX */
433
434#ifndef VBOX
435static void apic_bus_deliver(uint32_t deliver_bitmask, uint8_t delivery_mode,
436 uint8_t vector_num, uint8_t polarity,
437 uint8_t trigger_mode)
438{
439 APICState *apic_iter;
440#else /* VBOX */
441static void apic_bus_deliver(APICDeviceInfo* dev,
442 uint32_t deliver_bitmask, uint8_t delivery_mode,
443 uint8_t vector_num, uint8_t polarity,
444 uint8_t trigger_mode)
445{
446#endif /* VBOX */
447
448 LogFlow(("apic_bus_deliver mask=%x mode=%x vector=%x polarity=%x trigger_mode=%x\n", deliver_bitmask, delivery_mode, vector_num, polarity, trigger_mode));
449 switch (delivery_mode) {
450 case APIC_DM_LOWPRI:
451 {
452 int d = -1;
453 if (deliver_bitmask)
454 d = ffs_bit(deliver_bitmask);
455 if (d >= 0)
456 {
457 APICState* apic = getLapicById(dev, d);
458 apic_set_irq(dev, apic, vector_num, trigger_mode);
459 }
460 return;
461 }
462 case APIC_DM_FIXED:
463 /* XXX: arbitration */
464 break;
465
466 case APIC_DM_SMI:
467 /** @todo: what do we really do with SMI */
468 foreach_apic(dev, deliver_bitmask,
469 cpuSetInterrupt(dev, apic));
470 return;
471
472 case APIC_DM_NMI:
473 /** @todo: what do we really do with NMI */
474 foreach_apic(dev, deliver_bitmask,
475 cpuSetInterrupt(dev, apic));
476 return;
477
478 case APIC_DM_INIT:
479 /* normal INIT IPI sent to processors */
480#ifdef VBOX
481 foreach_apic(dev, deliver_bitmask,
482 apic_init_ipi(apic));
483#else
484 for (apic_iter = first_local_apic; apic_iter != NULL;
485 apic_iter = apic_iter->next_apic) {
486 apic_init_ipi(apic_iter);
487 }
488#endif
489 return;
490
491 case APIC_DM_EXTINT:
492 /* handled in I/O APIC code */
493 break;
494
495 default:
496 return;
497 }
498
499#ifdef VBOX
500 foreach_apic(dev, deliver_bitmask,
501 apic_set_irq (dev, apic, vector_num, trigger_mode));
502#else /* VBOX */
503 for (apic_iter = first_local_apic; apic_iter != NULL;
504 apic_iter = apic_iter->next_apic) {
505 if (deliver_bitmask & (1 << apic_iter->id))
506 apic_set_irq(apic_iter, vector_num, trigger_mode);
507 }
508#endif /* VBOX */
509}
510
511#ifndef VBOX
512void cpu_set_apic_base(CPUState *env, uint64_t val)
513{
514 APICState *s = env->apic_state;
515#ifdef DEBUG_APIC
516 Log(("cpu_set_apic_base: %016llx\n", val));
517#endif
518
519 s->apicbase = (val & 0xfffff000) |
520 (s->apicbase & (MSR_IA32_APICBASE_BSP | MSR_IA32_APICBASE_ENABLE));
521 /* if disabled, cannot be enabled again */
522 if (!(val & MSR_IA32_APICBASE_ENABLE)) {
523 s->apicbase &= ~MSR_IA32_APICBASE_ENABLE;
524 env->cpuid_features &= ~CPUID_APIC;
525 s->spurious_vec &= ~APIC_SV_ENABLE;
526 }
527}
528#else /* VBOX */
529PDMBOTHCBDECL(void) apicSetBase(PPDMDEVINS pDevIns, uint64_t val)
530{
531 APICDeviceInfo *dev = PDMINS_2_DATA(pDevIns, APICDeviceInfo *);
532 APICState *s = getLapic(dev);
533 Log(("cpu_set_apic_base: %016RX64\n", val));
534
535 /** @todo: do we need to lock here ? */
536 /* APIC_LOCK_VOID(dev, VERR_INTERNAL_ERROR); */
537 /** @todo If this change is valid immediately, then we should change the MMIO registration! */
538 /* We cannot change if this CPU is BSP or not by writing to MSR - it's hardwired */
539 PDMAPICVERSION oldMode = getApicMode(s);
540 s->apicbase =
541 (val & 0xfffff000) | /* base */
542 (val & getApicEnableBits(dev)) | /* mode */
543 (s->apicbase & MSR_IA32_APICBASE_BSP) /* keep BSP bit */;
544 PDMAPICVERSION newMode = getApicMode(s);
545
546 if (oldMode != newMode)
547 {
548 switch (newMode)
549 {
550 case PDMAPICVERSION_NONE:
551 {
552 s->spurious_vec &= ~APIC_SV_ENABLE;
553 /* Clear any pending APIC interrupt action flag. */
554 cpuClearInterrupt(dev, s);
555 /** @todo: why do we do that? */
556 dev->CTX_SUFF(pApicHlp)->pfnChangeFeature(pDevIns, PDMAPICVERSION_NONE);
557 break;
558 }
559 case PDMAPICVERSION_APIC:
560 /** @todo: map MMIO ranges, if needed */
561 break;
562 case PDMAPICVERSION_X2APIC:
563 /** @todo: unmap MMIO ranges of this APIC, according to the spec */
564 break;
565 default:
566 break;
567 }
568 }
569 /* APIC_UNLOCK(dev); */
570}
571#endif /* VBOX */
572#ifndef VBOX
573
574uint64_t cpu_get_apic_base(CPUState *env)
575{
576 APICState *s = env->apic_state;
577#ifdef DEBUG_APIC
578 Log(("cpu_get_apic_base: %016llx\n", (uint64_t)s->apicbase));
579#endif
580 return s->apicbase;
581}
582
583void cpu_set_apic_tpr(CPUX86State *env, uint8_t val)
584{
585 APICState *s = env->apic_state;
586 s->tpr = (val & 0x0f) << 4;
587 apic_update_irq(s);
588}
589
590uint8_t cpu_get_apic_tpr(CPUX86State *env)
591{
592 APICState *s = env->apic_state;
593 return s->tpr >> 4;
594}
595
596static int fls_bit(int value)
597{
598 unsigned int ret = 0;
599
600#ifdef HOST_I386
601 __asm__ __volatile__ ("bsr %1, %0\n" : "+r" (ret) : "rm" (value));
602 return ret;
603#else
604 if (value > 0xffff)
605 value >>= 16, ret = 16;
606 if (value > 0xff)
607 value >>= 8, ret += 8;
608 if (value > 0xf)
609 value >>= 4, ret += 4;
610 if (value > 0x3)
611 value >>= 2, ret += 2;
612 return ret + (value >> 1);
613#endif
614}
615
616static inline void set_bit(uint32_t *tab, int index)
617{
618 int i, mask;
619 i = index >> 5;
620 mask = 1 << (index & 0x1f);
621 tab[i] |= mask;
622}
623
624static inline void reset_bit(uint32_t *tab, int index)
625{
626 int i, mask;
627 i = index >> 5;
628 mask = 1 << (index & 0x1f);
629 tab[i] &= ~mask;
630}
631
632
633#else /* VBOX */
634
635PDMBOTHCBDECL(uint64_t) apicGetBase(PPDMDEVINS pDevIns)
636{
637 APICDeviceInfo *dev = PDMINS_2_DATA(pDevIns, APICDeviceInfo *);
638 APICState *s = getLapic(dev);
639 Log(("apicGetBase: %016llx\n", (uint64_t)s->apicbase));
640 return s->apicbase;
641}
642
643PDMBOTHCBDECL(void) apicSetTPR(PPDMDEVINS pDevIns, uint8_t val)
644{
645 APICDeviceInfo *dev = PDMINS_2_DATA(pDevIns, APICDeviceInfo *);
646 APICState *s = getLapic(dev);
647 LogFlow(("apicSetTPR: val=%#x (trp %#x -> %#x)\n", val, s->tpr, (val & 0x0f) << 4));
648 apic_update_tpr(dev, s, (val & 0x0f) << 4);
649}
650
651PDMBOTHCBDECL(uint8_t) apicGetTPR(PPDMDEVINS pDevIns)
652{
653 APICDeviceInfo *dev = PDMINS_2_DATA(pDevIns, APICDeviceInfo *);
654 APICState *s = getLapic(dev);
655 Log2(("apicGetTPR: returns %#x\n", s->tpr >> 4));
656 return s->tpr >> 4;
657}
658
659PDMBOTHCBDECL(int) apicWriteMSR(PPDMDEVINS pDevIns, VMCPUID idCpu, uint32_t u32Reg, uint64_t u64Value)
660{
661 APICDeviceInfo *dev = PDMINS_2_DATA(pDevIns, APICDeviceInfo *);
662
663 if (dev->enmVersion < PDMAPICVERSION_X2APIC)
664 return VERR_EM_INTERPRETER;
665
666 uint32_t index = (u32Reg - MSR_IA32_APIC_START) & 0xff;
667 //LogRel(("nike: WRMSR on %d: to %x written %llx\n", idCpu, index, u64Value));
668
669 APICState* apic = getLapicById(dev, idCpu);
670
671 switch (index)
672 {
673 case 0x02:
674 apic->id = (u64Value >> 24);
675 break;
676 case 0x03:
677 break;
678 case 0x08:
679 apic_update_tpr(dev, apic, u64Value);
680 break;
681 case 0x09: case 0x0a:
682 Log(("apicWriteMSR: write to read-only register %d ignored\n", index));
683 break;
684 case 0x0b: /* EOI */
685 apic_eoi(dev, apic);
686 break;
687 case 0x0d:
688 apic->log_dest = u64Value >> 24;
689 break;
690 case 0x0e:
691 apic->dest_mode = u64Value >> 28;
692 break;
693 case 0x0f:
694 apic->spurious_vec = u64Value & 0x1ff;
695 apic_update_irq(dev, apic);
696 break;
697 case 0x10: case 0x11: case 0x12: case 0x13: case 0x14: case 0x15: case 0x16: case 0x17:
698 case 0x18: case 0x19: case 0x1a: case 0x1b: case 0x1c: case 0x1d: case 0x1e: case 0x1f:
699 case 0x20: case 0x21: case 0x22: case 0x23: case 0x24: case 0x25: case 0x26: case 0x27:
700 case 0x28:
701 Log(("apicWriteMSR: write to read-only register %d ignored\n", index));
702 break;
703
704 case 0x30:
705 /* Here one of the differences with regular APIC: ICR is single 64-bit register */
706 apic->icr[0] = (uint32_t)u64Value;
707 apic->icr[1] = (uint32_t)(u64Value >> 32);
708 apic_deliver(dev, apic, (apic->icr[1] >> 24) & 0xff, (apic->icr[0] >> 11) & 1,
709 (apic->icr[0] >> 8) & 7, (apic->icr[0] & 0xff),
710 (apic->icr[0] >> 14) & 1, (apic->icr[0] >> 15) & 1);
711 break;
712 case 0x32: case 0x33: case 0x34: case 0x35: case 0x36: case 0x37:
713 {
714 int n = index - 0x32;
715 apic->lvt[n] = u64Value;
716 if (n == APIC_LVT_TIMER)
717 apic_timer_update(dev, apic, TMTimerGet(apic->CTX_SUFF(pTimer)));
718 }
719 break;
720 case 0x38:
721 apic->initial_count = u64Value;
722 apic->initial_count_load_time = TMTimerGet(apic->CTX_SUFF(pTimer));
723 apic_timer_update(dev, apic, apic->initial_count_load_time);
724 break;
725 case 0x39:
726 Log(("apicWriteMSR: write to read-only register %d ignored\n", index));
727 break;
728 case 0x3e:
729 {
730 int v;
731 apic->divide_conf = u64Value & 0xb;
732 v = (apic->divide_conf & 3) | ((apic->divide_conf >> 1) & 4);
733 apic->count_shift = (v + 1) & 7;
734 break;
735 }
736 case 0x3f:
737 {
738 /* Self IPI, see x2APIC book 2.4.5 */
739 int vector = u64Value & 0xff;
740 apic_bus_deliver(dev,
741 1 << getLapicById(dev, idCpu)->id /* Self */,
742 0 /* Delivery mode - fixed */,
743 vector,
744 0 /* Polarity - conform to the bus */,
745 0 /* Trigger mode - edge */);
746 break;
747 }
748 default:
749 AssertMsgFailed(("apicWriteMSR: unknown index %x\n", index));
750 apic->esr |= ESR_ILLEGAL_ADDRESS;
751 break;
752 }
753
754 return VINF_SUCCESS;
755}
756PDMBOTHCBDECL(int) apicReadMSR(PPDMDEVINS pDevIns, VMCPUID idCpu, uint32_t u32Reg, uint64_t *pu64Value)
757{
758 APICDeviceInfo *dev = PDMINS_2_DATA(pDevIns, APICDeviceInfo *);
759
760 if (dev->enmVersion < PDMAPICVERSION_X2APIC)
761 return VERR_EM_INTERPRETER;
762
763 uint32_t index = (u32Reg - MSR_IA32_APIC_START) & 0xff;
764 //LogRel(("nike: RDMSR on %d: read from %x\n", idCpu, index));
765 APICState* apic = getLapicById(dev, idCpu);
766 uint64_t val = 0;
767
768 switch (index)
769 {
770 case 0x02: /* id */
771 val = apic->id << 24;
772 break;
773 case 0x03: /* version */
774 val = 0x11 | ((APIC_LVT_NB - 1) << 16); /* version 0x11 */
775 break;
776 case 0x08:
777 val = apic->tpr;
778 break;
779 case 0x09:
780 val = apic_get_arb_pri(apic);
781 break;
782 case 0x0a:
783 /* ppr */
784 val = apic_get_ppr(apic);
785 break;
786 case 0x0b:
787 val = 0;
788 break;
789 case 0x0d:
790 val = apic->log_dest << 24;
791 break;
792 case 0x0e:
793 /* Bottom 28 bits are always 1 */
794 val = (apic->dest_mode << 28) | 0xfffffff;
795 break;
796 case 0x0f:
797 val = apic->spurious_vec;
798 break;
799 case 0x10: case 0x11: case 0x12: case 0x13: case 0x14: case 0x15: case 0x16: case 0x17:
800 val = apic->isr[index & 7];
801 break;
802 case 0x18: case 0x19: case 0x1a: case 0x1b: case 0x1c: case 0x1d: case 0x1e: case 0x1f:
803 val = apic->tmr[index & 7];
804 break;
805 case 0x20: case 0x21: case 0x22: case 0x23: case 0x24: case 0x25: case 0x26: case 0x27:
806 val = apic->irr[index & 7];
807 break;
808 case 0x28:
809 val = apic->esr;
810 break;
811 case 0x30:
812 /* Here one of the differences with regular APIC: ICR is single 64-bit register */
813 val = ((uint64_t)apic->icr[0x31] << 32) | apic->icr[0x30];
814 break;
815 case 0x32: case 0x33: case 0x34: case 0x35: case 0x36: case 0x37:
816 val = apic->lvt[index - 0x32];
817 break;
818 case 0x38:
819 val = apic->initial_count;
820 break;
821 case 0x39:
822 val = apic_get_current_count(dev, apic);
823 break;
824 case 0x3e:
825 val = apic->divide_conf;
826 break;
827 case 0x3f:
828 /* Self IPI register is write only */
829 Log(("apicReadMSR: read from write-only register %d ignored\n", index));
830 break;
831 default:
832 AssertMsgFailed(("apicReadMSR: unknown index %x\n", index));
833 apic->esr |= ESR_ILLEGAL_ADDRESS;
834 val = 0;
835 break;
836 }
837 *pu64Value = val;
838 return VINF_SUCCESS;
839}
840
841/**
842 * More or less private interface between IOAPIC, only PDM is responsible
843 * for connecting the two devices.
844 */
845PDMBOTHCBDECL(void) apicBusDeliverCallback(PPDMDEVINS pDevIns, uint8_t u8Dest, uint8_t u8DestMode,
846 uint8_t u8DeliveryMode, uint8_t iVector, uint8_t u8Polarity,
847 uint8_t u8TriggerMode)
848{
849 APICDeviceInfo *dev = PDMINS_2_DATA(pDevIns, APICDeviceInfo *);
850 LogFlow(("apicBusDeliverCallback: pDevIns=%p u8Dest=%#x u8DestMode=%#x u8DeliveryMode=%#x iVector=%#x u8Polarity=%#x u8TriggerMode=%#x\n",
851 pDevIns, u8Dest, u8DestMode, u8DeliveryMode, iVector, u8Polarity, u8TriggerMode));
852 apic_bus_deliver(dev, apic_get_delivery_bitmask(dev, u8Dest, u8DestMode),
853 u8DeliveryMode, iVector, u8Polarity, u8TriggerMode);
854}
855
856#endif /* VBOX */
857
858/* return -1 if no bit is set */
859static int get_highest_priority_int(uint32_t *tab)
860{
861 int i;
862 for(i = 7; i >= 0; i--) {
863 if (tab[i] != 0) {
864 return i * 32 + fls_bit(tab[i]);
865 }
866 }
867 return -1;
868}
869
870static int apic_get_ppr(APICState *s)
871{
872 int tpr, isrv, ppr;
873
874 tpr = (s->tpr >> 4);
875 isrv = get_highest_priority_int(s->isr);
876 if (isrv < 0)
877 isrv = 0;
878 isrv >>= 4;
879 if (tpr >= isrv)
880 ppr = s->tpr;
881 else
882 ppr = isrv << 4;
883 return ppr;
884}
885
886static int apic_get_ppr_zero_tpr(APICState *s)
887{
888 int isrv;
889
890 isrv = get_highest_priority_int(s->isr);
891 if (isrv < 0)
892 isrv = 0;
893 return isrv;
894}
895
896static int apic_get_arb_pri(APICState *s)
897{
898 /* XXX: arbitration */
899 return 0;
900}
901
902/* signal the CPU if an irq is pending */
903static bool apic_update_irq(APICDeviceInfo *dev, APICState* s)
904{
905 int irrv, ppr;
906 if (!(s->spurious_vec & APIC_SV_ENABLE))
907#ifdef VBOX
908 {
909 /* Clear any pending APIC interrupt action flag. */
910 cpuClearInterrupt(dev, s);
911 return false;
912 }
913#else
914 return false;
915#endif /* VBOX */
916 irrv = get_highest_priority_int(s->irr);
917 if (irrv < 0)
918 return false;
919 ppr = apic_get_ppr(s);
920 if (ppr && (irrv & 0xf0) <= (ppr & 0xf0))
921 return false;
922#ifndef VBOX
923 cpu_interrupt(s->cpu_env, CPU_INTERRUPT_HARD);
924#else
925 cpuSetInterrupt(dev, s);
926 return true;
927#endif
928}
929
930#ifdef VBOX
931
932/* Check if the APIC has a pending interrupt/if a TPR change would active one. */
933PDMBOTHCBDECL(bool) apicHasPendingIrq(PPDMDEVINS pDevIns)
934{
935 int irrv, ppr;
936 APICDeviceInfo *dev = PDMINS_2_DATA(pDevIns, APICDeviceInfo *);
937 if (!dev)
938 return false;
939 APICState *s = getLapic(dev);
940
941 /*
942 * All our callbacks now come from single IOAPIC, thus locking
943 * seems to be excessive now (@todo: check)
944 */
945 irrv = get_highest_priority_int(s->irr);
946 if (irrv < 0)
947 return false;
948
949 ppr = apic_get_ppr_zero_tpr(s);
950
951 if (ppr && (irrv & 0xf0) <= (ppr & 0xf0))
952 return false;
953
954 return true;
955}
956
957static void apic_update_tpr(APICDeviceInfo *dev, APICState* s, uint32_t val)
958{
959 bool fIrqIsActive = false;
960 bool fIrqWasActive = false;
961
962 fIrqWasActive = apic_update_irq(dev, s);
963 s->tpr = val;
964 fIrqIsActive = apic_update_irq(dev, s);
965
966 /* If an interrupt is pending and now masked, then clear the FF flag. */
967 if (fIrqWasActive && !fIrqIsActive)
968 {
969 Log(("apic_update_tpr: deactivate interrupt that was masked by the TPR update (%x)\n", val));
970 STAM_COUNTER_INC(&dev->StatClearedActiveIrq);
971 cpuClearInterrupt(dev, s);
972 }
973}
974#endif
975
976static void apic_set_irq(APICDeviceInfo *dev, APICState* s, int vector_num, int trigger_mode)
977{
978 LogFlow(("apic_set_irq vector=%x, trigger_mode=%x\n", vector_num, trigger_mode));
979 set_bit(s->irr, vector_num);
980 if (trigger_mode)
981 set_bit(s->tmr, vector_num);
982 else
983 reset_bit(s->tmr, vector_num);
984 apic_update_irq(dev, s);
985}
986
987static void apic_eoi(APICDeviceInfo *dev, APICState* s)
988{
989 int isrv;
990 isrv = get_highest_priority_int(s->isr);
991 if (isrv < 0)
992 return;
993 reset_bit(s->isr, isrv);
994 LogFlow(("apic_eoi isrv=%x\n", isrv));
995 /* XXX: send the EOI packet to the APIC bus to allow the I/O APIC to
996 set the remote IRR bit for level triggered interrupts. */
997 apic_update_irq(dev, s);
998}
999
1000#ifndef VBOX
1001static uint32_t apic_get_delivery_bitmask(uint8_t dest, uint8_t dest_mode)
1002#else /* VBOX */
1003static uint32_t apic_get_delivery_bitmask(APICDeviceInfo *dev, uint8_t dest, uint8_t dest_mode)
1004#endif /* VBOX */
1005{
1006 uint32_t mask = 0;
1007
1008 if (dest_mode == 0)
1009 {
1010 if (dest == 0xff)
1011 mask = 0xff;
1012 else
1013 mask = 1 << dest;
1014 }
1015 else
1016 {
1017 APICState *apic = LAPIC_BASE(dev);
1018 uint32_t i;
1019
1020 /* XXX: cluster mode */
1021 for(i = 0; i < dev->cCpus; i++)
1022 {
1023 if (apic->dest_mode == 0xf)
1024 {
1025 if (dest & apic->log_dest)
1026 mask |= (1 << apic->id);
1027 }
1028 else if (apic->dest_mode == 0x0)
1029 {
1030 if ((dest & 0xf0) == (apic->log_dest & 0xf0)
1031 &&
1032 (dest & apic->log_dest & 0x0f))
1033 {
1034 mask |= (1 << i);
1035 }
1036 }
1037 }
1038 apic++;
1039 }
1040
1041 return mask;
1042}
1043
1044static void apic_init_ipi(APICState *s)
1045{
1046 int i;
1047
1048 for(i = 0; i < APIC_LVT_NB; i++)
1049 s->lvt[i] = 1 << 16; /* mask LVT */
1050 s->tpr = 0;
1051 s->spurious_vec = 0xff;
1052 s->log_dest = 0;
1053 s->dest_mode = 0xff;
1054 memset(s->isr, 0, sizeof(s->isr));
1055 memset(s->tmr, 0, sizeof(s->tmr));
1056 memset(s->irr, 0, sizeof(s->irr));
1057 s->esr = 0;
1058 memset(s->icr, 0, sizeof(s->icr));
1059 s->divide_conf = 0;
1060 s->count_shift = 0;
1061 s->initial_count = 0;
1062 s->initial_count_load_time = 0;
1063 s->next_time = 0;
1064}
1065
1066
1067/* send a SIPI message to the CPU to start it */
1068static void apic_startup(APICDeviceInfo* dev, APICState *s, int vector_num)
1069{
1070#ifndef VBOX
1071 CPUState *env = s->cpu_env;
1072 if (!env->halted)
1073 return;
1074 env->eip = 0;
1075 cpu_x86_load_seg_cache(env, R_CS, vector_num << 8, vector_num << 12,
1076 0xffff, 0);
1077 env->halted = 0;
1078#else
1079 /** @todo: init CPUs */
1080 LogRel(("[SMP] apic_startup: %d on CPUs %d\n", vector_num, s->id));
1081#endif
1082}
1083static void apic_deliver(APICDeviceInfo* dev, APICState *s,
1084 uint8_t dest, uint8_t dest_mode,
1085 uint8_t delivery_mode, uint8_t vector_num,
1086 uint8_t polarity, uint8_t trigger_mode)
1087{
1088 uint32_t deliver_bitmask = 0;
1089 int dest_shorthand = (s->icr[0] >> 18) & 3;
1090#ifndef VBOX
1091 APICState *apic_iter;
1092#endif /* !VBOX */
1093
1094 LogFlow(("apic_deliver dest=%x dest_mode=%x delivery_mode=%x vector_num=%x polarity=%x trigger_mode=%x\n", dest, dest_mode, delivery_mode, vector_num, polarity, trigger_mode));
1095
1096 switch (dest_shorthand) {
1097 case 0:
1098#ifndef VBOX
1099 deliver_bitmask = apic_get_delivery_bitmask(dest, dest_mode);
1100#else /* VBOX */
1101 deliver_bitmask = apic_get_delivery_bitmask(dev, dest, dest_mode);
1102#endif /* !VBOX */
1103 break;
1104 case 1:
1105 deliver_bitmask = (1 << s->id);
1106 break;
1107 case 2:
1108 deliver_bitmask = 0xffffffff;
1109 break;
1110 case 3:
1111 deliver_bitmask = 0xffffffff & ~(1 << s->id);
1112 break;
1113 }
1114
1115 switch (delivery_mode) {
1116 case APIC_DM_LOWPRI:
1117 /* XXX: serch for focus processor, arbitration */
1118 dest = s->id;
1119
1120 case APIC_DM_INIT:
1121 {
1122 int trig_mode = (s->icr[0] >> 15) & 1;
1123 int level = (s->icr[0] >> 14) & 1;
1124 if (level == 0 && trig_mode == 1) {
1125#ifdef VBOX
1126 foreach_apic(dev, deliver_bitmask,
1127 apic->arb_id = apic->id);
1128#else /* !VBOX */
1129 for (apic_iter = first_local_apic; apic_iter != NULL;
1130 apic_iter = apic_iter->next_apic) {
1131 if (deliver_bitmask & (1 << apic_iter->id)) {
1132 apic_iter->arb_id = apic_iter->id;
1133 }
1134 }
1135#endif /* !VBOX */
1136 return;
1137 }
1138 }
1139 break;
1140
1141 case APIC_DM_SIPI:
1142#ifndef VBOX
1143 for (apic_iter = first_local_apic; apic_iter != NULL;
1144 apic_iter = apic_iter->next_apic) {
1145 if (deliver_bitmask & (1 << apic_iter->id)) {
1146 /* XXX: SMP support */
1147 /* apic_startup(apic_iter); */
1148 }
1149 }
1150#else
1151 foreach_apic(dev, deliver_bitmask,
1152 apic_startup(dev, apic, vector_num));
1153#endif /* !VBOX */
1154 return;
1155 }
1156
1157#ifndef VBOX
1158 apic_bus_deliver(deliver_bitmask, delivery_mode, vector_num, polarity,
1159 trigger_mode);
1160#else /* VBOX */
1161 apic_bus_deliver(dev, deliver_bitmask, delivery_mode, vector_num, polarity,
1162 trigger_mode);
1163#endif /* VBOX */
1164}
1165
1166
1167PDMBOTHCBDECL(int) apicGetInterrupt(PPDMDEVINS pDevIns)
1168{
1169 APICDeviceInfo *dev = PDMINS_2_DATA(pDevIns, APICDeviceInfo *);
1170 /* if the APIC is not installed or enabled, we let the 8259 handle the
1171 IRQs */
1172 if (!dev)
1173 {
1174 Log(("apic_get_interrupt: returns -1 (!s)\n"));
1175 return -1;
1176 }
1177
1178 APIC_LOCK(dev, VERR_INTERNAL_ERROR);
1179
1180 APICState *s = getLapic(dev);
1181 int intno;
1182
1183 if (!(s->spurious_vec & APIC_SV_ENABLE)) {
1184 Log(("apic_get_interrupt: returns -1 (APIC_SV_ENABLE)\n"));
1185 return -1;
1186 }
1187
1188 /* XXX: spurious IRQ handling */
1189 intno = get_highest_priority_int(s->irr);
1190 if (intno < 0) {
1191 Log(("apic_get_interrupt: returns -1 (irr)\n"));
1192 return -1;
1193 }
1194 if (s->tpr && (uint32_t)intno <= s->tpr) {
1195 Log(("apic_get_interrupt: returns %d (sp)\n", s->spurious_vec & 0xff));
1196 return s->spurious_vec & 0xff;
1197 }
1198 reset_bit(s->irr, intno);
1199 set_bit(s->isr, intno);
1200 apic_update_irq(dev, s);
1201 LogFlow(("apic_get_interrupt: returns %d\n", intno));
1202 APIC_UNLOCK(dev);
1203 return intno;
1204}
1205
1206static uint32_t apic_get_current_count(APICDeviceInfo* dev, APICState *s)
1207{
1208 int64_t d;
1209 uint32_t val;
1210#ifndef VBOX
1211 d = (qemu_get_clock(vm_clock) - s->initial_count_load_time) >>
1212 s->count_shift;
1213#else /* VBOX */
1214 d = (TMTimerGet(s->CTX_SUFF(pTimer)) - s->initial_count_load_time) >>
1215 s->count_shift;
1216#endif /* VBOX */
1217 if (s->lvt[APIC_LVT_TIMER] & APIC_LVT_TIMER_PERIODIC) {
1218 /* periodic */
1219 val = s->initial_count - (d % ((uint64_t)s->initial_count + 1));
1220 } else {
1221 if (d >= s->initial_count)
1222 val = 0;
1223 else
1224 val = s->initial_count - d;
1225 }
1226 return val;
1227}
1228
1229static void apic_timer_update(APICDeviceInfo* dev, APICState *s, int64_t current_time)
1230{
1231 int64_t next_time, d;
1232
1233 if (!(s->lvt[APIC_LVT_TIMER] & APIC_LVT_MASKED)) {
1234 d = (current_time - s->initial_count_load_time) >>
1235 s->count_shift;
1236 if (s->lvt[APIC_LVT_TIMER] & APIC_LVT_TIMER_PERIODIC) {
1237 d = ((d / ((uint64_t)s->initial_count + 1)) + 1) * ((uint64_t)s->initial_count + 1);
1238 } else {
1239 if (d >= s->initial_count)
1240 goto no_timer;
1241 d = (uint64_t)s->initial_count + 1;
1242 }
1243 next_time = s->initial_count_load_time + (d << s->count_shift);
1244#ifndef VBOX
1245 qemu_mod_timer(s->timer, next_time);
1246#else
1247 TMTimerSet(s->CTX_SUFF(pTimer), next_time);
1248#endif
1249 s->next_time = next_time;
1250 } else {
1251 no_timer:
1252#ifndef VBOX
1253 qemu_del_timer(s->timer);
1254#else
1255 TMTimerStop(s->CTX_SUFF(pTimer));
1256#endif
1257 }
1258}
1259
1260#ifdef IN_RING3
1261#ifndef VBOX
1262static void apic_timer(void *opaque)
1263{
1264 APICState *s = opaque;
1265#else /* VBOX */
1266static DECLCALLBACK(void) apicTimer(PPDMDEVINS pDevIns, PTMTIMER pTimer)
1267{
1268 APICDeviceInfo *dev = PDMINS_2_DATA(pDevIns, APICDeviceInfo *);
1269 APICState *s = getLapic(dev);
1270
1271 APIC_LOCK_VOID(dev, VERR_INTERNAL_ERROR);
1272#endif /* VBOX */
1273
1274 if (!(s->lvt[APIC_LVT_TIMER] & APIC_LVT_MASKED)) {
1275 LogFlow(("apic_timer: trigger irq\n"));
1276 apic_set_irq(dev, s, s->lvt[APIC_LVT_TIMER] & 0xff, APIC_TRIGGER_EDGE);
1277 }
1278 apic_timer_update(dev, s, s->next_time);
1279
1280#ifdef VBOX
1281 APIC_UNLOCK(dev);
1282#endif
1283}
1284#endif /* IN_RING3 */
1285
1286#ifndef VBOX
1287static uint32_t apic_mem_readb(void *opaque, target_phys_addr_t addr)
1288{
1289 return 0;
1290}
1291static uint32_t apic_mem_readw(void *opaque, target_phys_addr_t addr)
1292{
1293 return 0;
1294}
1295
1296static void apic_mem_writeb(void *opaque, target_phys_addr_t addr, uint32_t val)
1297{
1298}
1299
1300static void apic_mem_writew(void *opaque, target_phys_addr_t addr, uint32_t val)
1301{
1302}
1303#endif /* !VBOX */
1304
1305
1306#ifndef VBOX
1307static uint32_t apic_mem_readl(void *opaque, target_phys_addr_t addr)
1308{
1309 CPUState *env;
1310 APICState *s;
1311#else /* VBOX */
1312static uint32_t apic_mem_readl(APICDeviceInfo* dev, APICState *s, target_phys_addr_t addr)
1313{
1314#endif /* VBOX */
1315 uint32_t val;
1316 int index;
1317
1318#ifndef VBOX
1319 env = cpu_single_env;
1320 if (!env)
1321 return 0;
1322 s = env->apic_state;
1323#endif /* !VBOX */
1324
1325 index = (addr >> 4) & 0xff;
1326 switch(index) {
1327 case 0x02: /* id */
1328 val = s->id << 24;
1329 break;
1330 case 0x03: /* version */
1331 val = 0x11 | ((APIC_LVT_NB - 1) << 16); /* version 0x11 */
1332 break;
1333 case 0x08:
1334 val = s->tpr;
1335 break;
1336 case 0x09:
1337 val = apic_get_arb_pri(s);
1338 break;
1339 case 0x0a:
1340 /* ppr */
1341 val = apic_get_ppr(s);
1342 break;
1343 case 0x0b:
1344 Log(("apic_mem_readl %x %x -> write only returning 0\n", addr, index));
1345 val = 0;
1346 break;
1347 case 0x0d:
1348 val = s->log_dest << 24;
1349 break;
1350 case 0x0e:
1351#ifdef VBOX
1352 /* Bottom 28 bits are always 1 */
1353 val = (s->dest_mode << 28) | 0xfffffff;
1354#else
1355 val = s->dest_mode << 28;
1356#endif
1357 break;
1358 case 0x0f:
1359 val = s->spurious_vec;
1360 break;
1361#ifndef VBOX
1362 case 0x10 ... 0x17:
1363#else /* VBOX */
1364 case 0x10: case 0x11: case 0x12: case 0x13: case 0x14: case 0x15: case 0x16: case 0x17:
1365#endif /* VBOX */
1366 val = s->isr[index & 7];
1367 break;
1368#ifndef VBOX
1369 case 0x18 ... 0x1f:
1370#else /* VBOX */
1371 case 0x18: case 0x19: case 0x1a: case 0x1b: case 0x1c: case 0x1d: case 0x1e: case 0x1f:
1372#endif /* VBOX */
1373 val = s->tmr[index & 7];
1374 break;
1375#ifndef VBOX
1376 case 0x20 ... 0x27:
1377#else /* VBOX */
1378 case 0x20: case 0x21: case 0x22: case 0x23: case 0x24: case 0x25: case 0x26: case 0x27:
1379#endif /* VBOX */
1380 val = s->irr[index & 7];
1381 break;
1382 case 0x28:
1383 val = s->esr;
1384 break;
1385 case 0x30:
1386 case 0x31:
1387 val = s->icr[index & 1];
1388 break;
1389#ifndef VBOX
1390 case 0x32 ... 0x37:
1391#else /* VBOX */
1392 case 0x32: case 0x33: case 0x34: case 0x35: case 0x36: case 0x37:
1393#endif /* VBOX */
1394 val = s->lvt[index - 0x32];
1395 break;
1396 case 0x38:
1397 val = s->initial_count;
1398 break;
1399 case 0x39:
1400 val = apic_get_current_count(dev, s);
1401 break;
1402 case 0x3e:
1403 val = s->divide_conf;
1404 break;
1405 default:
1406 AssertMsgFailed(("apic_mem_readl: unknown index %x\n", index));
1407 s->esr |= ESR_ILLEGAL_ADDRESS;
1408 val = 0;
1409 break;
1410 }
1411#ifdef DEBUG_APIC
1412 Log(("APIC read: %08x = %08x\n", (uint32_t)addr, val));
1413#endif
1414 return val;
1415}
1416
1417#ifndef VBOX
1418static void apic_mem_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
1419{
1420 CPUState *env;
1421 APICState *s;
1422#else /* VBOX */
1423static int apic_mem_writel(APICDeviceInfo* dev, APICState *s, target_phys_addr_t addr, uint32_t val)
1424{
1425#endif /* VBOX */
1426 int index;
1427
1428#ifndef VBOX
1429 env = cpu_single_env;
1430 if (!env)
1431 return;
1432 s = env->apic_state;
1433#endif /* !VBOX */
1434
1435#ifdef DEBUG_APIC
1436 Log(("APIC write: %08x = %08x\n", (uint32_t)addr, val));
1437#endif
1438
1439 index = (addr >> 4) & 0xff;
1440 switch(index) {
1441 case 0x02:
1442 s->id = (val >> 24);
1443 break;
1444 case 0x03:
1445 Log(("apic_mem_writel: write to version register; ignored\n"));
1446 break;
1447 case 0x08:
1448#ifdef VBOX
1449 apic_update_tpr(dev, s, val);
1450#else
1451 s->tpr = val;
1452 apic_update_irq(s);
1453#endif
1454 break;
1455 case 0x09:
1456 case 0x0a:
1457 Log(("apic_mem_writel: write to read-only register %d ignored\n", index));
1458 break;
1459 case 0x0b: /* EOI */
1460 apic_eoi(dev, s);
1461 break;
1462 case 0x0d:
1463 s->log_dest = val >> 24;
1464 break;
1465 case 0x0e:
1466 s->dest_mode = val >> 28;
1467 break;
1468 case 0x0f:
1469 s->spurious_vec = val & 0x1ff;
1470 apic_update_irq(dev, s);
1471 break;
1472#ifndef VBOX
1473 case 0x10 ... 0x17:
1474 case 0x18 ... 0x1f:
1475 case 0x20 ... 0x27:
1476 case 0x28:
1477#else
1478 case 0x10: case 0x11: case 0x12: case 0x13: case 0x14: case 0x15: case 0x16: case 0x17:
1479 case 0x18: case 0x19: case 0x1a: case 0x1b: case 0x1c: case 0x1d: case 0x1e: case 0x1f:
1480 case 0x20: case 0x21: case 0x22: case 0x23: case 0x24: case 0x25: case 0x26: case 0x27:
1481 case 0x28:
1482 Log(("apic_mem_writel: write to read-only register %d ignored\n", index));
1483#endif
1484 break;
1485
1486 case 0x30:
1487 s->icr[0] = val;
1488 apic_deliver(dev, s, (s->icr[1] >> 24) & 0xff, (s->icr[0] >> 11) & 1,
1489 (s->icr[0] >> 8) & 7, (s->icr[0] & 0xff),
1490 (s->icr[0] >> 14) & 1, (s->icr[0] >> 15) & 1);
1491 break;
1492 case 0x31:
1493 s->icr[1] = val;
1494 break;
1495#ifndef VBOX
1496 case 0x32 ... 0x37:
1497#else /* VBOX */
1498 case 0x32: case 0x33: case 0x34: case 0x35: case 0x36: case 0x37:
1499#endif /* VBOX */
1500 {
1501 int n = index - 0x32;
1502 s->lvt[n] = val;
1503 if (n == APIC_LVT_TIMER)
1504#ifndef VBOX
1505 apic_timer_update(s, qemu_get_clock(vm_clock));
1506#else /* VBOX */
1507 apic_timer_update(dev, s, TMTimerGet(s->CTX_SUFF(pTimer)));
1508#endif /* VBOX*/
1509 }
1510 break;
1511 case 0x38:
1512 s->initial_count = val;
1513#ifndef VBOX
1514 s->initial_count_load_time = qemu_get_clock(vm_clock);
1515#else /* VBOX */
1516 s->initial_count_load_time = TMTimerGet(s->CTX_SUFF(pTimer));
1517#endif /* VBOX*/
1518 apic_timer_update(dev, s, s->initial_count_load_time);
1519 break;
1520 case 0x39:
1521 Log(("apic_mem_writel: write to read-only register %d ignored\n", index));
1522 break;
1523 case 0x3e:
1524 {
1525 int v;
1526 s->divide_conf = val & 0xb;
1527 v = (s->divide_conf & 3) | ((s->divide_conf >> 1) & 4);
1528 s->count_shift = (v + 1) & 7;
1529 }
1530 break;
1531 default:
1532 AssertMsgFailed(("apic_mem_writel: unknown index %x\n", index));
1533 s->esr |= ESR_ILLEGAL_ADDRESS;
1534 break;
1535 }
1536#ifdef VBOX
1537 return VINF_SUCCESS;
1538#endif
1539}
1540
1541#ifdef IN_RING3
1542
1543static void apic_save(QEMUFile *f, void *opaque)
1544{
1545 APICState *s = (APICState*)opaque;
1546 int i;
1547
1548 qemu_put_be32s(f, &s->apicbase);
1549#ifdef VBOX
1550 qemu_put_be32s(f, &s->id);
1551 qemu_put_be32s(f, &s->phys_id);
1552 qemu_put_be32s(f, &s->arb_id);
1553 qemu_put_be32s(f, &s->tpr);
1554#else
1555 qemu_put_8s(f, &s->id);
1556 qemu_put_8s(f, &s->arb_id);
1557 qemu_put_8s(f, &s->tpr);
1558#endif
1559 qemu_put_be32s(f, &s->spurious_vec);
1560 qemu_put_8s(f, &s->log_dest);
1561 qemu_put_8s(f, &s->dest_mode);
1562 for (i = 0; i < 8; i++) {
1563 qemu_put_be32s(f, &s->isr[i]);
1564 qemu_put_be32s(f, &s->tmr[i]);
1565 qemu_put_be32s(f, &s->irr[i]);
1566 }
1567 for (i = 0; i < APIC_LVT_NB; i++) {
1568 qemu_put_be32s(f, &s->lvt[i]);
1569 }
1570 qemu_put_be32s(f, &s->esr);
1571 qemu_put_be32s(f, &s->icr[0]);
1572 qemu_put_be32s(f, &s->icr[1]);
1573 qemu_put_be32s(f, &s->divide_conf);
1574 qemu_put_be32s(f, &s->count_shift);
1575 qemu_put_be32s(f, &s->initial_count);
1576 qemu_put_be64s(f, &s->initial_count_load_time);
1577 qemu_put_be64s(f, &s->next_time);
1578
1579#ifdef VBOX
1580 TMR3TimerSave(s->CTX_SUFF(pTimer), f);
1581#endif
1582}
1583
1584static int apic_load(QEMUFile *f, void *opaque, int version_id)
1585{
1586 APICState *s = (APICState*)opaque;
1587 int i;
1588
1589#ifdef VBOX
1590 if ((version_id < 1) || (version_id > 2))
1591 return -EINVAL;
1592
1593 /* XXX: what if the base changes? (registered memory regions) */
1594 qemu_get_be32s(f, &s->apicbase);
1595
1596 switch (version_id)
1597 {
1598 case 1:
1599 {
1600 uint8_t val = 0;
1601 qemu_get_8s(f, &val);
1602 s->id = val;
1603 /* UP only in old saved states */
1604 s->phys_id = 0;
1605 qemu_get_8s(f, &val);
1606 s->arb_id = val;
1607 break;
1608 }
1609 case 2:
1610 qemu_get_be32s(f, &s->id);
1611 qemu_get_be32s(f, &s->phys_id);
1612 qemu_get_be32s(f, &s->arb_id);
1613 break;
1614 }
1615 qemu_get_be32s(f, &s->tpr);
1616#else
1617 if (version_id != 1)
1618 return -EINVAL;
1619
1620 /* XXX: what if the base changes? (registered memory regions) */
1621 qemu_get_be32s(f, &s->apicbase);
1622 qemu_get_8s(f, &s->id);
1623 qemu_get_8s(f, &s->arb_id);
1624 qemu_get_8s(f, &s->tpr);
1625#endif
1626 qemu_get_be32s(f, &s->spurious_vec);
1627 qemu_get_8s(f, &s->log_dest);
1628 qemu_get_8s(f, &s->dest_mode);
1629 for (i = 0; i < 8; i++) {
1630 qemu_get_be32s(f, &s->isr[i]);
1631 qemu_get_be32s(f, &s->tmr[i]);
1632 qemu_get_be32s(f, &s->irr[i]);
1633 }
1634 for (i = 0; i < APIC_LVT_NB; i++) {
1635 qemu_get_be32s(f, &s->lvt[i]);
1636 }
1637 qemu_get_be32s(f, &s->esr);
1638 qemu_get_be32s(f, &s->icr[0]);
1639 qemu_get_be32s(f, &s->icr[1]);
1640 qemu_get_be32s(f, &s->divide_conf);
1641 qemu_get_be32s(f, (uint32_t *)&s->count_shift);
1642 qemu_get_be32s(f, (uint32_t *)&s->initial_count);
1643 qemu_get_be64s(f, (uint64_t *)&s->initial_count_load_time);
1644 qemu_get_be64s(f, (uint64_t *)&s->next_time);
1645
1646#ifdef VBOX
1647 TMR3TimerLoad(s->CTX_SUFF(pTimer), f);
1648#endif
1649
1650 return VINF_SUCCESS;
1651}
1652#ifndef VBOX
1653static void apic_reset(void *opaque)
1654{
1655 APICState *s = (APICState*)opaque;
1656 apic_init_ipi(s);
1657}
1658#endif
1659
1660#endif /* IN_RING3 */
1661
1662#ifndef VBOX
1663static CPUReadMemoryFunc *apic_mem_read[3] = {
1664 apic_mem_readb,
1665 apic_mem_readw,
1666 apic_mem_readl,
1667};
1668
1669static CPUWriteMemoryFunc *apic_mem_write[3] = {
1670 apic_mem_writeb,
1671 apic_mem_writew,
1672 apic_mem_writel,
1673};
1674
1675int apic_init(CPUState *env)
1676{
1677 APICState *s;
1678
1679 s = qemu_mallocz(sizeof(APICState));
1680 if (!s)
1681 return -1;
1682 env->apic_state = s;
1683 apic_init_ipi(s);
1684 s->id = last_apic_id++;
1685 s->cpu_env = env;
1686 s->apicbase = 0xfee00000 |
1687 (s->id ? 0 : MSR_IA32_APICBASE_BSP) | MSR_IA32_APICBASE_ENABLE;
1688
1689 /* XXX: mapping more APICs at the same memory location */
1690 if (apic_io_memory == 0) {
1691 /* NOTE: the APIC is directly connected to the CPU - it is not
1692 on the global memory bus. */
1693 apic_io_memory = cpu_register_io_memory(0, apic_mem_read,
1694 apic_mem_write, NULL);
1695 cpu_register_physical_memory(s->apicbase & ~0xfff, 0x1000,
1696 apic_io_memory);
1697 }
1698 s->timer = qemu_new_timer(vm_clock, apic_timer, s);
1699
1700 register_savevm("apic", 0, 1, apic_save, apic_load, s);
1701 qemu_register_reset(apic_reset, s);
1702
1703 s->next_apic = first_local_apic;
1704 first_local_apic = s;
1705
1706 return 0;
1707}
1708#endif /* !VBOX */
1709
1710static void ioapic_service(IOAPICState *s)
1711{
1712 uint8_t i;
1713 uint8_t trig_mode;
1714 uint8_t vector;
1715 uint8_t delivery_mode;
1716 uint32_t mask;
1717 uint64_t entry;
1718 uint8_t dest;
1719 uint8_t dest_mode;
1720 uint8_t polarity;
1721
1722 for (i = 0; i < IOAPIC_NUM_PINS; i++) {
1723 mask = 1 << i;
1724 if (s->irr & mask) {
1725 entry = s->ioredtbl[i];
1726 if (!(entry & APIC_LVT_MASKED)) {
1727 trig_mode = ((entry >> 15) & 1);
1728 dest = entry >> 56;
1729 dest_mode = (entry >> 11) & 1;
1730 delivery_mode = (entry >> 8) & 7;
1731 polarity = (entry >> 13) & 1;
1732 if (trig_mode == APIC_TRIGGER_EDGE)
1733 s->irr &= ~mask;
1734 if (delivery_mode == APIC_DM_EXTINT)
1735#ifndef VBOX /* malc: i'm still not so sure about ExtINT delivery */
1736 vector = pic_read_irq(isa_pic);
1737#else /* VBOX */
1738 {
1739 AssertMsgFailed(("Delivery mode ExtINT"));
1740 vector = 0xff; /* incorrect but shuts up gcc. */
1741 }
1742#endif /* VBOX */
1743 else
1744 vector = entry & 0xff;
1745
1746#ifndef VBOX
1747 apic_bus_deliver(apic_get_delivery_bitmask(dest, dest_mode),
1748 delivery_mode, vector, polarity, trig_mode);
1749#else /* VBOX */
1750 s->CTX_SUFF(pIoApicHlp)->pfnApicBusDeliver(s->CTX_SUFF(pDevIns),
1751 dest,
1752 dest_mode,
1753 delivery_mode,
1754 vector,
1755 polarity,
1756 trig_mode);
1757#endif /* VBOX */
1758 }
1759 }
1760 }
1761}
1762
1763#ifdef VBOX
1764static
1765#endif
1766void ioapic_set_irq(void *opaque, int vector, int level)
1767{
1768 IOAPICState *s = (IOAPICState*)opaque;
1769
1770 if (vector >= 0 && vector < IOAPIC_NUM_PINS) {
1771 uint32_t mask = 1 << vector;
1772 uint64_t entry = s->ioredtbl[vector];
1773
1774 if ((entry >> 15) & 1) {
1775 /* level triggered */
1776 if (level) {
1777 s->irr |= mask;
1778 ioapic_service(s);
1779#ifdef VBOX
1780 if ((level & PDM_IRQ_LEVEL_FLIP_FLOP) == PDM_IRQ_LEVEL_FLIP_FLOP) {
1781 s->irr &= ~mask;
1782 }
1783#endif
1784 } else {
1785 s->irr &= ~mask;
1786 }
1787 } else {
1788 /* edge triggered */
1789 if (level) {
1790 s->irr |= mask;
1791 ioapic_service(s);
1792 }
1793 }
1794 }
1795}
1796
1797static uint32_t ioapic_mem_readl(void *opaque, target_phys_addr_t addr)
1798{
1799 IOAPICState *s = (IOAPICState*)opaque;
1800 int index;
1801 uint32_t val = 0;
1802
1803 addr &= 0xff;
1804 if (addr == 0x00) {
1805 val = s->ioregsel;
1806 } else if (addr == 0x10) {
1807 switch (s->ioregsel) {
1808 case 0x00:
1809 val = s->id << 24;
1810 break;
1811 case 0x01:
1812 val = 0x11 | ((IOAPIC_NUM_PINS - 1) << 16); /* version 0x11 */
1813 break;
1814 case 0x02:
1815 val = 0;
1816 break;
1817 default:
1818 index = (s->ioregsel - 0x10) >> 1;
1819 if (index >= 0 && index < IOAPIC_NUM_PINS) {
1820 if (s->ioregsel & 1)
1821 val = s->ioredtbl[index] >> 32;
1822 else
1823 val = s->ioredtbl[index] & 0xffffffff;
1824 }
1825 }
1826#ifdef DEBUG_IOAPIC
1827 Log(("I/O APIC read: %08x = %08x\n", s->ioregsel, val));
1828#endif
1829 }
1830 return val;
1831}
1832
1833static void ioapic_mem_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
1834{
1835 IOAPICState *s = (IOAPICState*)opaque;
1836 int index;
1837
1838 addr &= 0xff;
1839 if (addr == 0x00) {
1840 s->ioregsel = val;
1841 return;
1842 } else if (addr == 0x10) {
1843#ifdef DEBUG_IOAPIC
1844 Log(("I/O APIC write: %08x = %08x\n", s->ioregsel, val));
1845#endif
1846 switch (s->ioregsel) {
1847 case 0x00:
1848 s->id = (val >> 24) & 0xff;
1849 return;
1850 case 0x01:
1851 case 0x02:
1852 return;
1853 default:
1854 index = (s->ioregsel - 0x10) >> 1;
1855 if (index >= 0 && index < IOAPIC_NUM_PINS) {
1856 if (s->ioregsel & 1) {
1857 s->ioredtbl[index] &= 0xffffffff;
1858 s->ioredtbl[index] |= (uint64_t)val << 32;
1859 } else {
1860#ifdef VBOX
1861 /* According to IOAPIC spec, vectors should be from 0x10 to 0xfe */
1862 uint8_t vec = val & 0xff;
1863 if ((val & APIC_LVT_MASKED) ||
1864 ((vec >= 0x10) && (vec < 0xff)))
1865 {
1866 s->ioredtbl[index] &= ~0xffffffffULL;
1867 s->ioredtbl[index] |= val;
1868 }
1869 else
1870 {
1871 /*
1872 * Linux 2.6 kernels has pretty strange function
1873 * unlock_ExtINT_logic() which writes
1874 * absolutely bogus (all 0) value into the vector
1875 * with pretty vague explanation why.
1876 * So we just ignore such writes.
1877 */
1878 LogRel(("IOAPIC GUEST BUG: bad vector writing %x(sel=%x) to %d\n", val, s->ioregsel, index));
1879 }
1880 }
1881#else
1882 s->ioredtbl[index] &= ~0xffffffffULL;
1883 s->ioredtbl[index] |= val;
1884#endif
1885 ioapic_service(s);
1886 }
1887 }
1888 }
1889}
1890
1891#ifdef IN_RING3
1892
1893static void ioapic_save(QEMUFile *f, void *opaque)
1894{
1895 IOAPICState *s = (IOAPICState*)opaque;
1896 int i;
1897
1898 qemu_put_8s(f, &s->id);
1899 qemu_put_8s(f, &s->ioregsel);
1900 for (i = 0; i < IOAPIC_NUM_PINS; i++) {
1901 qemu_put_be64s(f, &s->ioredtbl[i]);
1902 }
1903}
1904
1905static int ioapic_load(QEMUFile *f, void *opaque, int version_id)
1906{
1907 IOAPICState *s = (IOAPICState*)opaque;
1908 int i;
1909
1910 if (version_id != 1)
1911 return -EINVAL;
1912
1913 qemu_get_8s(f, &s->id);
1914 qemu_get_8s(f, &s->ioregsel);
1915 for (i = 0; i < IOAPIC_NUM_PINS; i++) {
1916 qemu_get_be64s(f, &s->ioredtbl[i]);
1917 }
1918 return 0;
1919}
1920
1921static void ioapic_reset(void *opaque)
1922{
1923 IOAPICState *s = (IOAPICState*)opaque;
1924#ifdef VBOX
1925 PPDMDEVINSR3 pDevIns = s->pDevInsR3;
1926 PCPDMIOAPICHLPR3 pIoApicHlp = s->pIoApicHlpR3;
1927#endif
1928 int i;
1929
1930 memset(s, 0, sizeof(*s));
1931 for(i = 0; i < IOAPIC_NUM_PINS; i++)
1932 s->ioredtbl[i] = 1 << 16; /* mask LVT */
1933
1934#ifdef VBOX
1935 if (pDevIns)
1936 {
1937 s->pDevInsR3 = pDevIns;
1938 s->pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
1939 s->pDevInsR0 = PDMDEVINS_2_R0PTR(pDevIns);
1940 }
1941 if (pIoApicHlp)
1942 {
1943 s->pIoApicHlpR3 = pIoApicHlp;
1944 s->pIoApicHlpRC = s->pIoApicHlpR3->pfnGetRCHelpers(pDevIns);
1945 s->pIoApicHlpR0 = s->pIoApicHlpR3->pfnGetR0Helpers(pDevIns);
1946 }
1947#endif
1948}
1949
1950#endif /* IN_RING3 */
1951
1952#ifndef VBOX
1953static CPUReadMemoryFunc *ioapic_mem_read[3] = {
1954 ioapic_mem_readl,
1955 ioapic_mem_readl,
1956 ioapic_mem_readl,
1957};
1958
1959static CPUWriteMemoryFunc *ioapic_mem_write[3] = {
1960 ioapic_mem_writel,
1961 ioapic_mem_writel,
1962 ioapic_mem_writel,
1963};
1964
1965IOAPICState *ioapic_init(void)
1966{
1967 IOAPICState *s;
1968 int io_memory;
1969
1970 s = qemu_mallocz(sizeof(IOAPICState));
1971 if (!s)
1972 return NULL;
1973 ioapic_reset(s);
1974 s->id = last_apic_id++;
1975
1976 io_memory = cpu_register_io_memory(0, ioapic_mem_read,
1977 ioapic_mem_write, s);
1978 cpu_register_physical_memory(0xfec00000, 0x1000, io_memory);
1979
1980 register_savevm("ioapic", 0, 1, ioapic_save, ioapic_load, s);
1981 qemu_register_reset(ioapic_reset, s);
1982
1983 return s;
1984}
1985#endif /* !VBOX */
1986
1987/* LAPIC */
1988PDMBOTHCBDECL(int) apicMMIORead(PPDMDEVINS pDevIns, void *pvUser, RTGCPHYS GCPhysAddr, void *pv, unsigned cb)
1989{
1990 APICDeviceInfo *dev = PDMINS_2_DATA(pDevIns, APICDeviceInfo *);
1991 APICState *s = getLapic(dev);
1992
1993#ifdef VBOX_WITH_SMP_GUESTS
1994 LogRel(("[SMP] apicMMIORead at %llx\n", (uint64_t)GCPhysAddr));
1995#endif
1996
1997 /** @todo: add LAPIC range validity checks (different LAPICs can theoretically have
1998 different physical addresses, see #3092) */
1999
2000 STAM_COUNTER_INC(&CTXSUFF(dev->StatMMIORead));
2001 switch (cb)
2002 {
2003 case 1:
2004 *(uint8_t *)pv = 0;
2005 break;
2006
2007 case 2:
2008 *(uint16_t *)pv = 0;
2009 break;
2010
2011 case 4:
2012 {
2013#if 0 /** @note experimental */
2014#ifndef IN_RING3
2015 uint32_t index = (GCPhysAddr >> 4) & 0xff;
2016
2017 if ( index == 0x08 /* TPR */
2018 && ++s->ulTPRPatchAttempts < APIC_MAX_PATCH_ATTEMPTS)
2019 {
2020#ifdef IN_RC
2021 pDevIns->pDevHlpGC->pfnPATMSetMMIOPatchInfo(pDevIns, GCPhysAddr, &s->tpr);
2022#else
2023 RTGCPTR pDevInsGC = PDMINS2DATA_GCPTR(pDevIns);
2024 pDevIns->pDevHlpR0->pfnPATMSetMMIOPatchInfo(pDevIns, GCPhysAddr, pDevIns + RT_OFFSETOF(APICState, tpr));
2025#endif
2026 return VINF_PATM_HC_MMIO_PATCH_READ;
2027 }
2028#endif
2029#endif /* experimental */
2030 APIC_LOCK(dev, VINF_IOM_HC_MMIO_READ);
2031 *(uint32_t *)pv = apic_mem_readl(dev, s, GCPhysAddr);
2032 APIC_UNLOCK(dev);
2033 break;
2034 }
2035 default:
2036 AssertReleaseMsgFailed(("cb=%d\n", cb)); /* for now we assume simple accesses. */
2037 return VERR_INTERNAL_ERROR;
2038 }
2039 return VINF_SUCCESS;
2040}
2041
2042PDMBOTHCBDECL(int) apicMMIOWrite(PPDMDEVINS pDevIns, void *pvUser, RTGCPHYS GCPhysAddr, void *pv, unsigned cb)
2043{
2044 APICDeviceInfo *dev = PDMINS_2_DATA(pDevIns, APICDeviceInfo *);
2045 APICState *s = getLapic(dev);
2046
2047#ifdef VBOX_WITH_SMP_GUESTS
2048 LogRel(("[SMP] apicMMIOWrite at %llx\n", (uint64_t)GCPhysAddr));
2049#endif
2050
2051 /** @todo: add LAPIC range validity checks (multiple LAPICs can theoretically have
2052 different physical addresses, see #3092) */
2053
2054 STAM_COUNTER_INC(&CTXSUFF(dev->StatMMIOWrite));
2055 switch (cb)
2056 {
2057 case 1:
2058 case 2:
2059 /* ignore */
2060 break;
2061
2062 case 4:
2063 {
2064 int rc;
2065 APIC_LOCK(dev, VINF_IOM_HC_MMIO_WRITE);
2066 rc = apic_mem_writel(dev, s, GCPhysAddr, *(uint32_t *)pv);
2067 APIC_UNLOCK(dev);
2068 return rc;
2069 }
2070
2071 default:
2072 AssertReleaseMsgFailed(("cb=%d\n", cb)); /* for now we assume simple accesses. */
2073 return VERR_INTERNAL_ERROR;
2074 }
2075 return VINF_SUCCESS;
2076}
2077
2078#ifdef IN_RING3
2079
2080/**
2081 * @copydoc FNSSMDEVSAVEEXEC
2082 */
2083static DECLCALLBACK(int) apicSaveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSMHandle)
2084{
2085 APICDeviceInfo *dev = PDMINS_2_DATA(pDevIns, APICDeviceInfo *);
2086
2087 /* save all APICs data, @todo: is it correct? */
2088 foreach_apic(dev, 0xffffffff, apic_save(pSSMHandle, apic));
2089
2090 return VINF_SUCCESS;
2091}
2092
2093/**
2094 * @copydoc FNSSMDEVLOADEXEC
2095 */
2096static DECLCALLBACK(int) apicLoadExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSMHandle, uint32_t u32Version)
2097{
2098 APICDeviceInfo *dev = PDMINS_2_DATA(pDevIns, APICDeviceInfo *);
2099 /* load all APICs data, @todo: is it correct? */
2100 foreach_apic(dev, 0xffffffff,
2101 if (apic_load(pSSMHandle, apic, u32Version))
2102 {
2103 AssertFailed();
2104 return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
2105 }
2106 );
2107 return VINF_SUCCESS;
2108}
2109
2110/**
2111 * @copydoc FNPDMDEVRESET
2112 */
2113static DECLCALLBACK(void) apicReset(PPDMDEVINS pDevIns)
2114{
2115 APICDeviceInfo* dev = PDMINS_2_DATA(pDevIns, APICDeviceInfo *);
2116 APICState *s = getLapic(dev);
2117
2118 APIC_LOCK_VOID(dev, VERR_INTERNAL_ERROR);
2119
2120 TMTimerStop(s->CTX_SUFF(pTimer));
2121
2122 apic_init_ipi(s);
2123 /* malc, I've removed the initing duplicated in apic_init_ipi(). This
2124 * arb_id was left over.. */
2125 s->arb_id = 0;
2126 /* Reset should re-enable the APIC. */
2127 s->apicbase = 0xfee00000 | MSR_IA32_APICBASE_ENABLE;
2128 if (s->phys_id == 0)
2129 s->apicbase |= MSR_IA32_APICBASE_BSP;
2130 dev->pApicHlpR3->pfnChangeFeature(dev->pDevInsR3, dev->enmVersion);
2131 /* Clear any pending APIC interrupt action flag. */
2132 cpuClearInterrupt(dev, s);
2133 APIC_UNLOCK(dev);
2134}
2135
2136/**
2137 * @copydoc FNPDMDEVRELOCATE
2138 */
2139static DECLCALLBACK(void) apicRelocate(PPDMDEVINS pDevIns, RTGCINTPTR offDelta)
2140{
2141 APICDeviceInfo *dev = PDMINS_2_DATA(pDevIns, APICDeviceInfo *);
2142#ifdef VBOX_WITH_SMP_GUESTS
2143 LogRel(("[SMP]: relocate apic on %llx\n", offDelta));
2144#endif
2145 dev->pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
2146 dev->pApicHlpRC = dev->pApicHlpR3->pfnGetRCHelpers(pDevIns);
2147 dev->pLapicsRC = MMHyperR3ToRC(PDMDevHlpGetVM(pDevIns), dev->pLapicsR3);
2148 foreach_apic(dev, 0xffffffff,
2149 apic->pTimerRC = TMTimerRCPtr(apic->CTX_SUFF(pTimer)));
2150}
2151
2152DECLINLINE(void) initApicData(APICState* apic, uint8_t id)
2153{
2154 int i;
2155 memset(apic, 0, sizeof(*apic));
2156 apic->apicbase = UINT32_C(0xfee00000) | MSR_IA32_APICBASE_ENABLE;
2157 /* Mark first CPU as BSP */
2158 if (id == 0)
2159 apic->apicbase |= MSR_IA32_APICBASE_BSP;
2160 for (i = 0; i < APIC_LVT_NB; i++)
2161 apic->lvt[i] = 1 << 16; /* mask LVT */
2162 apic->spurious_vec = 0xff;
2163 apic->phys_id = apic->id = id;
2164}
2165
2166/**
2167 * @copydoc FNPDMDEVCONSTRUCT
2168 */
2169static DECLCALLBACK(int) apicConstruct(PPDMDEVINS pDevIns, int iInstance, PCFGMNODE pCfgHandle)
2170{
2171 PDMAPICREG ApicReg;
2172 int rc;
2173 uint32_t i;
2174 bool fIOAPIC;
2175 bool fGCEnabled;
2176 bool fR0Enabled;
2177 APICDeviceInfo *pThis = PDMINS_2_DATA(pDevIns, APICDeviceInfo *);
2178 uint32_t cCpus;
2179 APICState *apic;
2180
2181 /*
2182 * Only single device instance.
2183 */
2184 Assert(iInstance == 0);
2185
2186 /*
2187 * Validate configuration.
2188 */
2189 if (!CFGMR3AreValuesValid(pCfgHandle,
2190 "IOAPIC\0"
2191 "GCEnabled\0"
2192 "R0Enabled\0"
2193 "NumCPUs\0"))
2194 return VERR_PDM_DEVINS_UNKNOWN_CFG_VALUES;
2195
2196 rc = CFGMR3QueryBoolDef(pCfgHandle, "IOAPIC", &fIOAPIC, true);
2197 if (RT_FAILURE(rc))
2198 return PDMDEV_SET_ERROR(pDevIns, rc,
2199 N_("Configuration error: Failed to read \"IOAPIC\""));
2200
2201 rc = CFGMR3QueryBoolDef(pCfgHandle, "GCEnabled", &fGCEnabled, true);
2202 if (RT_FAILURE(rc))
2203 return PDMDEV_SET_ERROR(pDevIns, rc,
2204 N_("Configuration error: Failed to query boolean value \"GCEnabled\""));
2205
2206 rc = CFGMR3QueryBoolDef(pCfgHandle, "R0Enabled", &fR0Enabled, true);
2207 if (RT_FAILURE(rc))
2208 return PDMDEV_SET_ERROR(pDevIns, rc,
2209 N_("Configuration error: Failed to query boolean value \"R0Enabled\""));
2210
2211 rc = CFGMR3QueryU32Def(pCfgHandle, "NumCPUs", &cCpus, 1);
2212 if (RT_FAILURE(rc))
2213 return PDMDEV_SET_ERROR(pDevIns, rc,
2214 N_("Configuration error: Failed to query integer value \"NumCPUs\""));
2215
2216 Log(("APIC: cCpus=%d fR0Enabled=%RTbool fGCEnabled=%RTbool fIOAPIC=%RTbool\n", cCpus, fR0Enabled, fGCEnabled, fIOAPIC));
2217
2218 /*
2219 * Init the data.
2220 */
2221 pThis->pDevInsR3 = pDevIns;
2222 pThis->pDevInsR0 = PDMDEVINS_2_R0PTR(pDevIns);
2223 pThis->pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
2224 pThis->cCpus = cCpus;
2225 /* Use PDMAPICVERSION_X2APIC to activate x2APIC mode */
2226 pThis->enmVersion = PDMAPICVERSION_APIC;
2227
2228 PVM pVM = PDMDevHlpGetVM(pDevIns);
2229 /*
2230 * We are not freeing this memory, as it's automatically released when guest exits.
2231 */
2232 rc = MMHyperAlloc(pVM, cCpus*sizeof(APICState), 1, MM_TAG_PDM_DEVICE_USER, (void **)&pThis->pLapicsR3);
2233 if (RT_FAILURE(rc))
2234 return VERR_NO_MEMORY;
2235 pThis->pLapicsR0 = MMHyperR3ToR0(pVM, pThis->pLapicsR3);
2236 pThis->pLapicsRC = MMHyperR3ToRC(pVM, pThis->pLapicsR3);
2237
2238 for (i = 0, apic = LAPIC_BASE(pThis); i < cCpus; i++)
2239 {
2240 initApicData(apic, i);
2241 apic++;
2242 }
2243
2244 /*
2245 * Register the APIC.
2246 */
2247 ApicReg.u32Version = PDM_APICREG_VERSION;
2248 ApicReg.pfnGetInterruptR3 = apicGetInterrupt;
2249 ApicReg.pfnHasPendingIrqR3 = apicHasPendingIrq;
2250 ApicReg.pfnSetBaseR3 = apicSetBase;
2251 ApicReg.pfnGetBaseR3 = apicGetBase;
2252 ApicReg.pfnSetTPRR3 = apicSetTPR;
2253 ApicReg.pfnGetTPRR3 = apicGetTPR;
2254 ApicReg.pfnWriteMSRR3 = apicWriteMSR;
2255 ApicReg.pfnReadMSRR3 = apicReadMSR;
2256 ApicReg.pfnBusDeliverR3 = apicBusDeliverCallback;
2257 if (fGCEnabled) {
2258 ApicReg.pszGetInterruptRC = "apicGetInterrupt";
2259 ApicReg.pszHasPendingIrqRC = "apicHasPendingIrq";
2260 ApicReg.pszSetBaseRC = "apicSetBase";
2261 ApicReg.pszGetBaseRC = "apicGetBase";
2262 ApicReg.pszSetTPRRC = "apicSetTPR";
2263 ApicReg.pszGetTPRRC = "apicGetTPR";
2264 ApicReg.pszWriteMSRRC = "apicWriteMSR";
2265 ApicReg.pszReadMSRRC = "apicReadMSR";
2266 ApicReg.pszBusDeliverRC = "apicBusDeliverCallback";
2267 } else {
2268 ApicReg.pszGetInterruptRC = NULL;
2269 ApicReg.pszHasPendingIrqRC = NULL;
2270 ApicReg.pszSetBaseRC = NULL;
2271 ApicReg.pszGetBaseRC = NULL;
2272 ApicReg.pszSetTPRRC = NULL;
2273 ApicReg.pszGetTPRRC = NULL;
2274 ApicReg.pszWriteMSRRC = NULL;
2275 ApicReg.pszReadMSRRC = NULL;
2276 ApicReg.pszBusDeliverRC = NULL;
2277 }
2278 if (fR0Enabled) {
2279 ApicReg.pszGetInterruptR0 = "apicGetInterrupt";
2280 ApicReg.pszHasPendingIrqR0 = "apicHasPendingIrq";
2281 ApicReg.pszSetBaseR0 = "apicSetBase";
2282 ApicReg.pszGetBaseR0 = "apicGetBase";
2283 ApicReg.pszSetTPRR0 = "apicSetTPR";
2284 ApicReg.pszGetTPRR0 = "apicGetTPR";
2285 ApicReg.pszWriteMSRR0 = "apicWriteMSR";
2286 ApicReg.pszReadMSRR0 = "apicReadMSR";
2287 ApicReg.pszBusDeliverR0 = "apicBusDeliverCallback";
2288 } else {
2289 ApicReg.pszGetInterruptR0 = NULL;
2290 ApicReg.pszHasPendingIrqR0 = NULL;
2291 ApicReg.pszSetBaseR0 = NULL;
2292 ApicReg.pszGetBaseR0 = NULL;
2293 ApicReg.pszSetTPRR0 = NULL;
2294 ApicReg.pszGetTPRR0 = NULL;
2295 ApicReg.pszWriteMSRR0 = NULL;
2296 ApicReg.pszReadMSRR0 = NULL;
2297 ApicReg.pszBusDeliverR0 = NULL;
2298 }
2299
2300 Assert(pDevIns->pDevHlpR3->pfnAPICRegister);
2301 rc = pDevIns->pDevHlpR3->pfnAPICRegister(pDevIns, &ApicReg, &pThis->pApicHlpR3);
2302 if (RT_FAILURE(rc))
2303 {
2304 AssertLogRelMsgFailed(("APICRegister -> %Rrc\n", rc));
2305 return rc;
2306 }
2307
2308 /*
2309 * The the CPUID feature bit.
2310 */
2311 uint32_t u32Eax, u32Ebx, u32Ecx, u32Edx;
2312 PDMDevHlpGetCpuId(pDevIns, 0, &u32Eax, &u32Ebx, &u32Ecx, &u32Edx);
2313 if (u32Eax >= 1)
2314 {
2315 if ( fIOAPIC /* If IOAPIC is enabled, enable Local APIC in any case */
2316 || ( u32Ebx == X86_CPUID_VENDOR_INTEL_EBX
2317 && u32Ecx == X86_CPUID_VENDOR_INTEL_ECX
2318 && u32Edx == X86_CPUID_VENDOR_INTEL_EDX /* GenuineIntel */)
2319 || ( u32Ebx == X86_CPUID_VENDOR_AMD_EBX
2320 && u32Ecx == X86_CPUID_VENDOR_AMD_ECX
2321 && u32Edx == X86_CPUID_VENDOR_AMD_EDX /* AuthenticAMD */))
2322 {
2323 LogRel(("Activating Local APIC\n"));
2324 pThis->pApicHlpR3->pfnChangeFeature(pDevIns, pThis->enmVersion);
2325 }
2326 }
2327
2328 /*
2329 * Register the MMIO range.
2330 * @todo: may need to rethink for cases when different LAPICs mapped to different address
2331 * (see IA32_APIC_BASE_MSR)
2332 */
2333 rc = PDMDevHlpMMIORegister(pDevIns, LAPIC_BASE(pThis)->apicbase & ~0xfff, 0x1000, pThis,
2334 apicMMIOWrite, apicMMIORead, NULL, "APIC Memory");
2335 if (RT_FAILURE(rc))
2336 return rc;
2337
2338 if (fGCEnabled) {
2339 pThis->pApicHlpRC = pThis->pApicHlpR3->pfnGetRCHelpers(pDevIns);
2340
2341 rc = PDMDevHlpMMIORegisterGC(pDevIns, LAPIC_BASE(pThis)->apicbase & ~0xfff, 0x1000, 0,
2342 "apicMMIOWrite", "apicMMIORead", NULL);
2343 if (RT_FAILURE(rc))
2344 return rc;
2345 }
2346
2347 if (fR0Enabled) {
2348 pThis->pApicHlpR0 = pThis->pApicHlpR3->pfnGetR0Helpers(pDevIns);
2349
2350 rc = PDMDevHlpMMIORegisterR0(pDevIns, LAPIC_BASE(pThis)->apicbase & ~0xfff, 0x1000, 0,
2351 "apicMMIOWrite", "apicMMIORead", NULL);
2352 if (RT_FAILURE(rc))
2353 return rc;
2354 }
2355
2356 /*
2357 * Create the APIC timers.
2358 */
2359 for (i = 0, apic = LAPIC_BASE(pThis); i < cCpus; i++)
2360 {
2361 rc = PDMDevHlpTMTimerCreate(pDevIns, TMCLOCK_VIRTUAL_SYNC, apicTimer,
2362 "APIC Timer", &apic->pTimerR3);
2363 if (RT_FAILURE(rc))
2364 return rc;
2365 apic->pTimerR0 = TMTimerR0Ptr(apic->pTimerR3);
2366 apic->pTimerRC = TMTimerRCPtr(apic->pTimerR3);
2367 apic++;
2368 }
2369
2370 /*
2371 * Saved state.
2372 */
2373 rc = PDMDevHlpSSMRegister(pDevIns, pDevIns->pDevReg->szDeviceName, iInstance, 2 /* version */,
2374 sizeof(*pThis), NULL, apicSaveExec, NULL, NULL, apicLoadExec, NULL);
2375 if (RT_FAILURE(rc))
2376 return rc;
2377
2378#ifdef VBOX_WITH_STATISTICS
2379 /*
2380 * Statistics.
2381 */
2382 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMMIOReadGC, STAMTYPE_COUNTER, "/PDM/APIC/MMIOReadGC", STAMUNIT_OCCURENCES, "Number of APIC MMIO reads in GC.");
2383 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMMIOReadHC, STAMTYPE_COUNTER, "/PDM/APIC/MMIOReadHC", STAMUNIT_OCCURENCES, "Number of APIC MMIO reads in HC.");
2384 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMMIOWriteGC, STAMTYPE_COUNTER, "/PDM/APIC/MMIOWriteGC", STAMUNIT_OCCURENCES, "Number of APIC MMIO writes in GC.");
2385 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMMIOWriteHC, STAMTYPE_COUNTER, "/PDM/APIC/MMIOWriteHC", STAMUNIT_OCCURENCES, "Number of APIC MMIO writes in HC.");
2386 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatClearedActiveIrq, STAMTYPE_COUNTER, "/PDM/APIC/Masked/ActiveIRQ", STAMUNIT_OCCURENCES, "Number of cleared irqs.");
2387#endif
2388
2389 return VINF_SUCCESS;
2390}
2391
2392
2393/**
2394 * APIC device registration structure.
2395 */
2396const PDMDEVREG g_DeviceAPIC =
2397{
2398 /* u32Version */
2399 PDM_DEVREG_VERSION,
2400 /* szDeviceName */
2401 "apic",
2402 /* szRCMod */
2403 "VBoxDD2GC.gc",
2404 /* szR0Mod */
2405 "VBoxDD2R0.r0",
2406 /* pszDescription */
2407 "Advanced Programmable Interrupt Controller (APIC) Device",
2408 /* fFlags */
2409 PDM_DEVREG_FLAGS_HOST_BITS_DEFAULT | PDM_DEVREG_FLAGS_GUEST_BITS_32_64 | PDM_DEVREG_FLAGS_PAE36 | PDM_DEVREG_FLAGS_RC | PDM_DEVREG_FLAGS_R0,
2410 /* fClass */
2411 PDM_DEVREG_CLASS_PIC,
2412 /* cMaxInstances */
2413 1,
2414 /* cbInstance */
2415 sizeof(APICState),
2416 /* pfnConstruct */
2417 apicConstruct,
2418 /* pfnDestruct */
2419 NULL,
2420 /* pfnRelocate */
2421 apicRelocate,
2422 /* pfnIOCtl */
2423 NULL,
2424 /* pfnPowerOn */
2425 NULL,
2426 /* pfnReset */
2427 apicReset,
2428 /* pfnSuspend */
2429 NULL,
2430 /* pfnResume */
2431 NULL,
2432 /* pfnAttach */
2433 NULL,
2434 /* pfnDetach */
2435 NULL,
2436 /* pfnQueryInterface. */
2437 NULL,
2438 /* pfnInitComplete */
2439 NULL,
2440 /* pfnPowerOff */
2441 NULL,
2442 /* pfnSoftReset */
2443 NULL,
2444 /* u32VersionEnd */
2445 PDM_DEVREG_VERSION
2446};
2447
2448#endif /* IN_RING3 */
2449
2450
2451/* IOAPIC */
2452
2453PDMBOTHCBDECL(int) ioapicMMIORead(PPDMDEVINS pDevIns, void *pvUser, RTGCPHYS GCPhysAddr, void *pv, unsigned cb)
2454{
2455 IOAPICState *s = PDMINS_2_DATA(pDevIns, IOAPICState *);
2456 IOAPIC_LOCK(s, VINF_IOM_HC_MMIO_READ);
2457
2458 STAM_COUNTER_INC(&CTXSUFF(s->StatMMIORead));
2459 switch (cb)
2460 {
2461 case 1:
2462 *(uint8_t *)pv = ioapic_mem_readl(s, GCPhysAddr);
2463 break;
2464
2465 case 2:
2466 *(uint16_t *)pv = ioapic_mem_readl(s, GCPhysAddr);
2467 break;
2468
2469 case 4:
2470 *(uint32_t *)pv = ioapic_mem_readl(s, GCPhysAddr);
2471 break;
2472
2473 default:
2474 AssertReleaseMsgFailed(("cb=%d\n", cb)); /* for now we assume simple accesses. */
2475 IOAPIC_UNLOCK(s);
2476 return VERR_INTERNAL_ERROR;
2477 }
2478 IOAPIC_UNLOCK(s);
2479 return VINF_SUCCESS;
2480}
2481
2482PDMBOTHCBDECL(int) ioapicMMIOWrite(PPDMDEVINS pDevIns, void *pvUser, RTGCPHYS GCPhysAddr, void *pv, unsigned cb)
2483{
2484 IOAPICState *s = PDMINS_2_DATA(pDevIns, IOAPICState *);
2485
2486 STAM_COUNTER_INC(&CTXSUFF(s->StatMMIOWrite));
2487 switch (cb)
2488 {
2489 case 1:
2490 case 2:
2491 case 4:
2492 IOAPIC_LOCK(s, VINF_IOM_HC_MMIO_WRITE);
2493 ioapic_mem_writel(s, GCPhysAddr, *(uint32_t *)pv);
2494 IOAPIC_UNLOCK(s);
2495 break;
2496
2497 default:
2498 AssertReleaseMsgFailed(("cb=%d\n", cb)); /* for now we assume simple accesses. */
2499 return VERR_INTERNAL_ERROR;
2500 }
2501 return VINF_SUCCESS;
2502}
2503
2504PDMBOTHCBDECL(void) ioapicSetIrq(PPDMDEVINS pDevIns, int iIrq, int iLevel)
2505{
2506 IOAPICState *pThis = PDMINS_2_DATA(pDevIns, IOAPICState *);
2507 STAM_COUNTER_INC(&pThis->CTXSUFF(StatSetIrq));
2508 LogFlow(("ioapicSetIrq: iIrq=%d iLevel=%d\n", iIrq, iLevel));
2509 ioapic_set_irq(pThis, iIrq, iLevel);
2510}
2511
2512
2513#ifdef IN_RING3
2514
2515/**
2516 * @copydoc FNSSMDEVSAVEEXEC
2517 */
2518static DECLCALLBACK(int) ioapicSaveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSMHandle)
2519{
2520 IOAPICState *s = PDMINS_2_DATA(pDevIns, IOAPICState *);
2521 ioapic_save(pSSMHandle, s);
2522 return VINF_SUCCESS;
2523}
2524
2525/**
2526 * @copydoc FNSSMDEVLOADEXEC
2527 */
2528static DECLCALLBACK(int) ioapicLoadExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSMHandle, uint32_t u32Version)
2529{
2530 IOAPICState *s = PDMINS_2_DATA(pDevIns, IOAPICState *);
2531
2532 if (ioapic_load(pSSMHandle, s, u32Version)) {
2533 AssertFailed();
2534 return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
2535 }
2536
2537 return VINF_SUCCESS;
2538}
2539
2540/**
2541 * @copydoc FNPDMDEVRESET
2542 */
2543static DECLCALLBACK(void) ioapicReset(PPDMDEVINS pDevIns)
2544{
2545 IOAPICState *s = PDMINS_2_DATA(pDevIns, IOAPICState *);
2546 s->pIoApicHlpR3->pfnLock(pDevIns, VERR_INTERNAL_ERROR);
2547 ioapic_reset(s);
2548 IOAPIC_UNLOCK(s);
2549}
2550
2551/**
2552 * @copydoc FNPDMDEVRELOCATE
2553 */
2554static DECLCALLBACK(void) ioapicRelocate(PPDMDEVINS pDevIns, RTGCINTPTR offDelta)
2555{
2556 IOAPICState *s = PDMINS_2_DATA(pDevIns, IOAPICState *);
2557 s->pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
2558 s->pIoApicHlpRC = s->pIoApicHlpR3->pfnGetRCHelpers(pDevIns);
2559}
2560
2561/**
2562 * @copydoc FNPDMDEVCONSTRUCT
2563 */
2564static DECLCALLBACK(int) ioapicConstruct(PPDMDEVINS pDevIns, int iInstance, PCFGMNODE pCfgHandle)
2565{
2566 IOAPICState *s = PDMINS_2_DATA(pDevIns, IOAPICState *);
2567 PDMIOAPICREG IoApicReg;
2568 bool fGCEnabled;
2569 bool fR0Enabled;
2570 int rc;
2571
2572 Assert(iInstance == 0);
2573
2574 /*
2575 * Validate and read the configuration.
2576 */
2577 if (!CFGMR3AreValuesValid(pCfgHandle, "GCEnabled\0" "R0Enabled\0"))
2578 return VERR_PDM_DEVINS_UNKNOWN_CFG_VALUES;
2579
2580 rc = CFGMR3QueryBoolDef(pCfgHandle, "GCEnabled", &fGCEnabled, true);
2581 if (RT_FAILURE(rc))
2582 return PDMDEV_SET_ERROR(pDevIns, rc,
2583 N_("Configuration error: Failed to query boolean value \"GCEnabled\""));
2584
2585 rc = CFGMR3QueryBoolDef(pCfgHandle, "R0Enabled", &fR0Enabled, true);
2586 if (RT_FAILURE(rc))
2587 return PDMDEV_SET_ERROR(pDevIns, rc,
2588 N_("Configuration error: Failed to query boolean value \"R0Enabled\""));
2589 Log(("IOAPIC: fR0Enabled=%RTbool fGCEnabled=%RTbool\n", fR0Enabled, fGCEnabled));
2590
2591 /*
2592 * Initialize the state data.
2593 */
2594 s->pDevInsR3 = pDevIns;
2595 s->pDevInsR0 = PDMDEVINS_2_R0PTR(pDevIns);
2596 s->pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
2597 ioapic_reset(s);
2598 s->id = 0;
2599
2600 /*
2601 * Register the IOAPIC and get helpers.
2602 */
2603 IoApicReg.u32Version = PDM_IOAPICREG_VERSION;
2604 IoApicReg.pfnSetIrqR3 = ioapicSetIrq;
2605 IoApicReg.pszSetIrqRC = fGCEnabled ? "ioapicSetIrq" : NULL;
2606 IoApicReg.pszSetIrqR0 = fR0Enabled ? "ioapicSetIrq" : NULL;
2607 rc = pDevIns->pDevHlpR3->pfnIOAPICRegister(pDevIns, &IoApicReg, &s->pIoApicHlpR3);
2608 if (RT_FAILURE(rc))
2609 {
2610 AssertMsgFailed(("IOAPICRegister -> %Rrc\n", rc));
2611 return rc;
2612 }
2613
2614 /*
2615 * Register MMIO callbacks and saved state.
2616 */
2617 rc = PDMDevHlpMMIORegister(pDevIns, 0xfec00000, 0x1000, s,
2618 ioapicMMIOWrite, ioapicMMIORead, NULL, "I/O APIC Memory");
2619 if (RT_FAILURE(rc))
2620 return rc;
2621
2622 if (fGCEnabled) {
2623 s->pIoApicHlpRC = s->pIoApicHlpR3->pfnGetRCHelpers(pDevIns);
2624
2625 rc = PDMDevHlpMMIORegisterGC(pDevIns, 0xfec00000, 0x1000, 0,
2626 "ioapicMMIOWrite", "ioapicMMIORead", NULL);
2627 if (RT_FAILURE(rc))
2628 return rc;
2629 }
2630
2631 if (fR0Enabled) {
2632 s->pIoApicHlpR0 = s->pIoApicHlpR3->pfnGetR0Helpers(pDevIns);
2633
2634 rc = PDMDevHlpMMIORegisterR0(pDevIns, 0xfec00000, 0x1000, 0,
2635 "ioapicMMIOWrite", "ioapicMMIORead", NULL);
2636 if (RT_FAILURE(rc))
2637 return rc;
2638 }
2639
2640 rc = PDMDevHlpSSMRegister(pDevIns, pDevIns->pDevReg->szDeviceName, iInstance, 1 /* version */,
2641 sizeof(*s), NULL, ioapicSaveExec, NULL, NULL, ioapicLoadExec, NULL);
2642 if (RT_FAILURE(rc))
2643 return rc;
2644
2645#ifdef VBOX_WITH_STATISTICS
2646 /*
2647 * Statistics.
2648 */
2649 PDMDevHlpSTAMRegister(pDevIns, &s->StatMMIOReadGC, STAMTYPE_COUNTER, "/PDM/IOAPIC/MMIOReadGC", STAMUNIT_OCCURENCES, "Number of IOAPIC MMIO reads in GC.");
2650 PDMDevHlpSTAMRegister(pDevIns, &s->StatMMIOReadHC, STAMTYPE_COUNTER, "/PDM/IOAPIC/MMIOReadHC", STAMUNIT_OCCURENCES, "Number of IOAPIC MMIO reads in HC.");
2651 PDMDevHlpSTAMRegister(pDevIns, &s->StatMMIOWriteGC, STAMTYPE_COUNTER, "/PDM/IOAPIC/MMIOWriteGC", STAMUNIT_OCCURENCES, "Number of IOAPIC MMIO writes in GC.");
2652 PDMDevHlpSTAMRegister(pDevIns, &s->StatMMIOWriteHC, STAMTYPE_COUNTER, "/PDM/IOAPIC/MMIOWriteHC", STAMUNIT_OCCURENCES, "Number of IOAPIC MMIO writes in HC.");
2653 PDMDevHlpSTAMRegister(pDevIns, &s->StatSetIrqGC, STAMTYPE_COUNTER, "/PDM/IOAPIC/SetIrqGC", STAMUNIT_OCCURENCES, "Number of IOAPIC SetIrq calls in GC.");
2654 PDMDevHlpSTAMRegister(pDevIns, &s->StatSetIrqHC, STAMTYPE_COUNTER, "/PDM/IOAPIC/SetIrqHC", STAMUNIT_OCCURENCES, "Number of IOAPIC SetIrq calls in HC.");
2655#endif
2656
2657 return VINF_SUCCESS;
2658}
2659
2660/**
2661 * IO APIC device registration structure.
2662 */
2663const PDMDEVREG g_DeviceIOAPIC =
2664{
2665 /* u32Version */
2666 PDM_DEVREG_VERSION,
2667 /* szDeviceName */
2668 "ioapic",
2669 /* szRCMod */
2670 "VBoxDD2GC.gc",
2671 /* szR0Mod */
2672 "VBoxDD2R0.r0",
2673 /* pszDescription */
2674 "I/O Advanced Programmable Interrupt Controller (IO-APIC) Device",
2675 /* fFlags */
2676 PDM_DEVREG_FLAGS_HOST_BITS_DEFAULT | PDM_DEVREG_FLAGS_GUEST_BITS_32_64 | PDM_DEVREG_FLAGS_PAE36 | PDM_DEVREG_FLAGS_RC | PDM_DEVREG_FLAGS_R0,
2677 /* fClass */
2678 PDM_DEVREG_CLASS_PIC,
2679 /* cMaxInstances */
2680 1,
2681 /* cbInstance */
2682 sizeof(IOAPICState),
2683 /* pfnConstruct */
2684 ioapicConstruct,
2685 /* pfnDestruct */
2686 NULL,
2687 /* pfnRelocate */
2688 ioapicRelocate,
2689 /* pfnIOCtl */
2690 NULL,
2691 /* pfnPowerOn */
2692 NULL,
2693 /* pfnReset */
2694 ioapicReset,
2695 /* pfnSuspend */
2696 NULL,
2697 /* pfnResume */
2698 NULL,
2699 /* pfnAttach */
2700 NULL,
2701 /* pfnDetach */
2702 NULL,
2703 /* pfnQueryInterface. */
2704 NULL,
2705 /* pfnInitComplete */
2706 NULL,
2707 /* pfnPowerOff */
2708 NULL,
2709 /* pfnSoftReset */
2710 NULL,
2711 /* u32VersionEnd */
2712 PDM_DEVREG_VERSION
2713};
2714
2715#endif /* IN_RING3 */
2716#endif /* !VBOX_DEVICE_STRUCT_TESTCASE */
2717
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