VirtualBox

source: vbox/trunk/src/VBox/Devices/PC/DevACPI.cpp@ 96407

Last change on this file since 96407 was 96407, checked in by vboxsync, 2 years ago

scm copyright and license note update
  • Property svn:eol-style set to native
  • Property svn:keywords set to Id Revision
File size: 189.0 KB
Line 
1/* $Id: DevACPI.cpp 96407 2022-08-22 17:43:14Z vboxsync $ */
2/** @file
3 * DevACPI - Advanced Configuration and Power Interface (ACPI) Device.
4 */
5
6/*
7 * Copyright (C) 2006-2022 Oracle and/or its affiliates.
8 *
9 * This file is part of VirtualBox base platform packages, as
10 * available from https://www.virtualbox.org.
11 *
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License
14 * as published by the Free Software Foundation, in version 3 of the
15 * License.
16 *
17 * This program is distributed in the hope that it will be useful, but
18 * WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
20 * General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, see <https://www.gnu.org/licenses>.
24 *
25 * SPDX-License-Identifier: GPL-3.0-only
26 */
27
28
29/*********************************************************************************************************************************
30* Header Files *
31*********************************************************************************************************************************/
32#define LOG_GROUP LOG_GROUP_DEV_ACPI
33#include <VBox/vmm/pdmdev.h>
34#include <VBox/vmm/pgm.h>
35#include <VBox/vmm/dbgftrace.h>
36#include <VBox/vmm/vmcpuset.h>
37#include <VBox/AssertGuest.h>
38#include <VBox/log.h>
39#include <VBox/param.h>
40#include <VBox/pci.h>
41#include <iprt/assert.h>
42#include <iprt/asm.h>
43#include <iprt/asm-math.h>
44#include <iprt/file.h>
45#ifdef IN_RING3
46# include <iprt/alloc.h>
47# include <iprt/string.h>
48# include <iprt/uuid.h>
49#endif /* IN_RING3 */
50#ifdef VBOX_WITH_IOMMU_AMD
51# include <VBox/iommu-amd.h>
52#endif
53#ifdef VBOX_WITH_IOMMU_INTEL
54# include <VBox/iommu-intel.h>
55#endif
56
57#include "VBoxDD.h"
58#ifdef VBOX_WITH_IOMMU_AMD
59# include "../Bus/DevIommuAmd.h"
60#endif
61#ifdef VBOX_WITH_IOMMU_INTEL
62# include "../Bus/DevIommuIntel.h"
63#endif
64
65#ifdef LOG_ENABLED
66# define DEBUG_ACPI
67#endif
68
69
70/*********************************************************************************************************************************
71* Defined Constants And Macros *
72*********************************************************************************************************************************/
73#ifdef IN_RING3
74/** Locks the device state, ring-3 only. */
75# define DEVACPI_LOCK_R3(a_pDevIns, a_pThis) \
76 do { \
77 int rcLock = PDMDevHlpCritSectEnter((a_pDevIns), &(a_pThis)->CritSect, VERR_IGNORED); \
78 PDM_CRITSECT_RELEASE_ASSERT_RC_DEV((a_pDevIns), &(a_pThis)->CritSect, rcLock); \
79 } while (0)
80#endif
81/** Unlocks the device state (all contexts). */
82#define DEVACPI_UNLOCK(a_pDevIns, a_pThis) \
83 do { PDMDevHlpCritSectLeave((a_pDevIns), &(a_pThis)->CritSect); } while (0)
84
85
86#define DEBUG_HEX 0x3000
87#define DEBUG_CHR 0x3001
88
89/** PM Base Address PCI config space offset */
90#define PMBA 0x40
91/** PM Miscellaneous Power Management PCI config space offset */
92#define PMREGMISC 0x80
93
94#define PM_TMR_FREQ 3579545
95/** Default base for PM PIIX4 device */
96#define PM_PORT_BASE 0x4000
97/* Port offsets in PM device */
98enum
99{
100 PM1a_EVT_OFFSET = 0x00,
101 PM1b_EVT_OFFSET = -1, /**< not supported */
102 PM1a_CTL_OFFSET = 0x04,
103 PM1b_CTL_OFFSET = -1, /**< not supported */
104 PM2_CTL_OFFSET = -1, /**< not supported */
105 PM_TMR_OFFSET = 0x08,
106 GPE0_OFFSET = 0x20,
107 GPE1_OFFSET = -1 /**< not supported */
108};
109
110/* Maximum supported number of custom ACPI tables */
111#define MAX_CUST_TABLES 4
112
113/* Undef this to enable 24 bit PM timer (mostly for debugging purposes) */
114#define PM_TMR_32BIT
115
116#define BAT_INDEX 0x00004040
117#define BAT_DATA 0x00004044
118#define SYSI_INDEX 0x00004048
119#define SYSI_DATA 0x0000404c
120#define ACPI_RESET_BLK 0x00004050
121
122/* PM1x status register bits */
123#define TMR_STS RT_BIT(0)
124#define RSR1_STS (RT_BIT(1) | RT_BIT(2) | RT_BIT(3))
125#define BM_STS RT_BIT(4)
126#define GBL_STS RT_BIT(5)
127#define RSR2_STS (RT_BIT(6) | RT_BIT(7))
128#define PWRBTN_STS RT_BIT(8)
129#define SLPBTN_STS RT_BIT(9)
130#define RTC_STS RT_BIT(10)
131#define IGN_STS RT_BIT(11)
132#define RSR3_STS (RT_BIT(12) | RT_BIT(13) | RT_BIT(14))
133#define WAK_STS RT_BIT(15)
134#define RSR_STS (RSR1_STS | RSR2_STS | RSR3_STS)
135
136/* PM1x enable register bits */
137#define TMR_EN RT_BIT(0)
138#define RSR1_EN (RT_BIT(1) | RT_BIT(2) | RT_BIT(3) | RT_BIT(4))
139#define GBL_EN RT_BIT(5)
140#define RSR2_EN (RT_BIT(6) | RT_BIT(7))
141#define PWRBTN_EN RT_BIT(8)
142#define SLPBTN_EN RT_BIT(9)
143#define RTC_EN RT_BIT(10)
144#define RSR3_EN (RT_BIT(11) | RT_BIT(12) | RT_BIT(13) | RT_BIT(14) | RT_BIT(15))
145#define RSR_EN (RSR1_EN | RSR2_EN | RSR3_EN)
146#define IGN_EN 0
147
148/* PM1x control register bits */
149#define SCI_EN RT_BIT(0)
150#define BM_RLD RT_BIT(1)
151#define GBL_RLS RT_BIT(2)
152#define RSR1_CNT (RT_BIT(3) | RT_BIT(4) | RT_BIT(5) | RT_BIT(6) | RT_BIT(7) | RT_BIT(8))
153#define IGN_CNT RT_BIT(9)
154#define SLP_TYPx_SHIFT 10
155#define SLP_TYPx_MASK 7
156#define SLP_EN RT_BIT(13)
157#define RSR2_CNT (RT_BIT(14) | RT_BIT(15))
158#define RSR_CNT (RSR1_CNT | RSR2_CNT)
159
160#define GPE0_BATTERY_INFO_CHANGED RT_BIT(0)
161
162enum
163{
164 BAT_STATUS_STATE = 0x00, /**< BST battery state */
165 BAT_STATUS_PRESENT_RATE = 0x01, /**< BST battery present rate */
166 BAT_STATUS_REMAINING_CAPACITY = 0x02, /**< BST battery remaining capacity */
167 BAT_STATUS_PRESENT_VOLTAGE = 0x03, /**< BST battery present voltage */
168 BAT_INFO_UNITS = 0x04, /**< BIF power unit */
169 BAT_INFO_DESIGN_CAPACITY = 0x05, /**< BIF design capacity */
170 BAT_INFO_LAST_FULL_CHARGE_CAPACITY = 0x06, /**< BIF last full charge capacity */
171 BAT_INFO_TECHNOLOGY = 0x07, /**< BIF battery technology */
172 BAT_INFO_DESIGN_VOLTAGE = 0x08, /**< BIF design voltage */
173 BAT_INFO_DESIGN_CAPACITY_OF_WARNING = 0x09, /**< BIF design capacity of warning */
174 BAT_INFO_DESIGN_CAPACITY_OF_LOW = 0x0A, /**< BIF design capacity of low */
175 BAT_INFO_CAPACITY_GRANULARITY_1 = 0x0B, /**< BIF battery capacity granularity 1 */
176 BAT_INFO_CAPACITY_GRANULARITY_2 = 0x0C, /**< BIF battery capacity granularity 2 */
177 BAT_DEVICE_STATUS = 0x0D, /**< STA device status */
178 BAT_POWER_SOURCE = 0x0E, /**< PSR power source */
179 BAT_INDEX_LAST
180};
181
182enum
183{
184 CPU_EVENT_TYPE_ADD = 0x01, /**< Event type add */
185 CPU_EVENT_TYPE_REMOVE = 0x03 /**< Event type remove */
186};
187
188enum
189{
190 SYSTEM_INFO_INDEX_LOW_MEMORY_LENGTH = 0,
191 SYSTEM_INFO_INDEX_USE_IOAPIC = 1,
192 SYSTEM_INFO_INDEX_HPET_STATUS = 2,
193 SYSTEM_INFO_INDEX_SMC_STATUS = 3,
194 SYSTEM_INFO_INDEX_FDC_STATUS = 4,
195 SYSTEM_INFO_INDEX_SERIAL2_IOBASE = 5,
196 SYSTEM_INFO_INDEX_SERIAL2_IRQ = 6,
197 SYSTEM_INFO_INDEX_SERIAL3_IOBASE = 7,
198 SYSTEM_INFO_INDEX_SERIAL3_IRQ = 8,
199 SYSTEM_INFO_INDEX_PREF64_MEMORY_MIN = 9,
200 SYSTEM_INFO_INDEX_RTC_STATUS = 10,
201 SYSTEM_INFO_INDEX_CPU_LOCKED = 11, /**< Contains a flag indicating whether the CPU is locked or not */
202 SYSTEM_INFO_INDEX_CPU_LOCK_CHECK = 12, /**< For which CPU the lock status should be checked */
203 SYSTEM_INFO_INDEX_CPU_EVENT_TYPE = 13, /**< Type of the CPU hot-plug event */
204 SYSTEM_INFO_INDEX_CPU_EVENT = 14, /**< The CPU id the event is for */
205 SYSTEM_INFO_INDEX_NIC_ADDRESS = 15, /**< NIC PCI address, or 0 */
206 SYSTEM_INFO_INDEX_AUDIO_ADDRESS = 16, /**< Audio card PCI address, or 0 */
207 SYSTEM_INFO_INDEX_POWER_STATES = 17,
208 SYSTEM_INFO_INDEX_IOC_ADDRESS = 18, /**< IO controller PCI address */
209 SYSTEM_INFO_INDEX_HBC_ADDRESS = 19, /**< host bus controller PCI address */
210 SYSTEM_INFO_INDEX_PCI_BASE = 20, /**< PCI bus MCFG MMIO range base */
211 SYSTEM_INFO_INDEX_PCI_LENGTH = 21, /**< PCI bus MCFG MMIO range length */
212 SYSTEM_INFO_INDEX_SERIAL0_IOBASE = 22,
213 SYSTEM_INFO_INDEX_SERIAL0_IRQ = 23,
214 SYSTEM_INFO_INDEX_SERIAL1_IOBASE = 24,
215 SYSTEM_INFO_INDEX_SERIAL1_IRQ = 25,
216 SYSTEM_INFO_INDEX_PARALLEL0_IOBASE = 26,
217 SYSTEM_INFO_INDEX_PARALLEL0_IRQ = 27,
218 SYSTEM_INFO_INDEX_PARALLEL1_IOBASE = 28,
219 SYSTEM_INFO_INDEX_PARALLEL1_IRQ = 29,
220 SYSTEM_INFO_INDEX_PREF64_MEMORY_MAX = 30,
221 SYSTEM_INFO_INDEX_NVME_ADDRESS = 31, /**< First NVMe controller PCI address, or 0 */
222 SYSTEM_INFO_INDEX_IOMMU_ADDRESS = 32, /**< IOMMU PCI address, or 0 */
223 SYSTEM_INFO_INDEX_SB_IOAPIC_ADDRESS = 33, /**< Southbridge I/O APIC (needed by AMD IOMMU) PCI address, or 0 */
224 SYSTEM_INFO_INDEX_END = 34,
225 SYSTEM_INFO_INDEX_INVALID = 0x80,
226 SYSTEM_INFO_INDEX_VALID = 0x200
227};
228
229#define AC_OFFLINE 0
230#define AC_ONLINE 1
231
232#define BAT_TECH_PRIMARY 1
233#define BAT_TECH_SECONDARY 2
234
235#define STA_DEVICE_PRESENT_MASK RT_BIT(0) /**< present */
236#define STA_DEVICE_ENABLED_MASK RT_BIT(1) /**< enabled and decodes its resources */
237#define STA_DEVICE_SHOW_IN_UI_MASK RT_BIT(2) /**< should be shown in UI */
238#define STA_DEVICE_FUNCTIONING_PROPERLY_MASK RT_BIT(3) /**< functioning properly */
239#define STA_BATTERY_PRESENT_MASK RT_BIT(4) /**< the battery is present */
240
241/** SMBus Base Address PCI config space offset */
242#define SMBBA 0x90
243/** SMBus Host Configuration PCI config space offset */
244#define SMBHSTCFG 0xd2
245/** SMBus Slave Command PCI config space offset */
246#define SMBSLVC 0xd3
247/** SMBus Slave Shadow Port 1 PCI config space offset */
248#define SMBSHDW1 0xd4
249/** SMBus Slave Shadow Port 2 PCI config space offset */
250#define SMBSHDW2 0xd5
251/** SMBus Revision Identification PCI config space offset */
252#define SMBREV 0xd6
253
254#define SMBHSTCFG_SMB_HST_EN RT_BIT(0)
255#define SMBHSTCFG_INTRSEL (RT_BIT(1) | RT_BIT(2) | RT_BIT(3))
256#define SMBHSTCFG_INTRSEL_SMI 0
257#define SMBHSTCFG_INTRSEL_IRQ9 4
258#define SMBHSTCFG_INTRSEL_SHIFT 1
259
260/** Default base for SMBus PIIX4 device */
261#define SMB_PORT_BASE 0x4100
262
263/** SMBus Host Status Register I/O offset */
264#define SMBHSTSTS_OFF 0x0000
265/** SMBus Slave Status Register I/O offset */
266#define SMBSLVSTS_OFF 0x0001
267/** SMBus Host Count Register I/O offset */
268#define SMBHSTCNT_OFF 0x0002
269/** SMBus Host Command Register I/O offset */
270#define SMBHSTCMD_OFF 0x0003
271/** SMBus Host Address Register I/O offset */
272#define SMBHSTADD_OFF 0x0004
273/** SMBus Host Data 0 Register I/O offset */
274#define SMBHSTDAT0_OFF 0x0005
275/** SMBus Host Data 1 Register I/O offset */
276#define SMBHSTDAT1_OFF 0x0006
277/** SMBus Block Data Register I/O offset */
278#define SMBBLKDAT_OFF 0x0007
279/** SMBus Slave Control Register I/O offset */
280#define SMBSLVCNT_OFF 0x0008
281/** SMBus Shadow Command Register I/O offset */
282#define SMBSHDWCMD_OFF 0x0009
283/** SMBus Slave Event Register I/O offset */
284#define SMBSLVEVT_OFF 0x000a
285/** SMBus Slave Data Register I/O offset */
286#define SMBSLVDAT_OFF 0x000c
287
288#define SMBHSTSTS_HOST_BUSY RT_BIT(0)
289#define SMBHSTSTS_INTER RT_BIT(1)
290#define SMBHSTSTS_DEV_ERR RT_BIT(2)
291#define SMBHSTSTS_BUS_ERR RT_BIT(3)
292#define SMBHSTSTS_FAILED RT_BIT(4)
293#define SMBHSTSTS_INT_MASK (SMBHSTSTS_INTER | SMBHSTSTS_DEV_ERR | SMBHSTSTS_BUS_ERR | SMBHSTSTS_FAILED)
294
295#define SMBSLVSTS_WRITE_MASK 0x3c
296
297#define SMBHSTCNT_INTEREN RT_BIT(0)
298#define SMBHSTCNT_KILL RT_BIT(1)
299#define SMBHSTCNT_CMD_PROT (RT_BIT(2) | RT_BIT(3) | RT_BIT(4))
300#define SMBHSTCNT_START RT_BIT(6)
301#define SMBHSTCNT_WRITE_MASK (SMBHSTCNT_INTEREN | SMBHSTCNT_KILL | SMBHSTCNT_CMD_PROT)
302
303#define SMBSLVCNT_WRITE_MASK (RT_BIT(0) | RT_BIT(1) | RT_BIT(2) | RT_BIT(3))
304
305
306/*********************************************************************************************************************************
307* Structures and Typedefs *
308*********************************************************************************************************************************/
309/**
310 * The TPM mode configured.
311 */
312typedef enum ACPITPMMODE
313{
314 ACPITPMMODE_INVALID = 0,
315 ACPITPMMODE_DISABLED,
316 ACPITPMMODE_TIS_1_2,
317 ACPITPMMODE_CRB_2_0,
318 ACPITPMMODE_FIFO_2_0,
319 ACPITPMMODE_32BIT_HACK = 0x7fffffff
320} ACPITPMMODE;
321
322
323/**
324 * The shared ACPI device state.
325 */
326typedef struct ACPISTATE
327{
328 /** Critical section protecting the ACPI state. */
329 PDMCRITSECT CritSect;
330
331 uint16_t pm1a_en;
332 uint16_t pm1a_sts;
333 uint16_t pm1a_ctl;
334 /** Number of logical CPUs in guest */
335 uint16_t cCpus;
336
337 uint64_t u64PmTimerInitial;
338 /** The PM timer. */
339 TMTIMERHANDLE hPmTimer;
340 /* PM Timer last calculated value */
341 uint32_t uPmTimerVal;
342 uint32_t Alignment0;
343
344 uint32_t gpe0_en;
345 uint32_t gpe0_sts;
346
347 uint32_t uBatteryIndex;
348 uint32_t au8BatteryInfo[13];
349
350 uint32_t uSystemInfoIndex;
351 uint32_t u32Alignment0;
352 uint64_t u64RamSize;
353 /** Offset of the 64-bit prefetchable memory window. */
354 uint64_t u64PciPref64Min;
355 /** Limit of the 64-bit prefetchable memory window. */
356 uint64_t u64PciPref64Max;
357 /** The number of bytes below 4GB. */
358 uint32_t cbRamLow;
359
360 /** Current ACPI S* state. We support S0 and S5. */
361 uint32_t uSleepState;
362 uint8_t au8RSDPPage[0x1000];
363 /** This is a workaround for incorrect index field handling by Intels ACPICA.
364 * The system info _INI method writes to offset 0x200. We either observe a
365 * write request to index 0x80 (in that case we don't change the index) or a
366 * write request to offset 0x200 (in that case we divide the index value by
367 * 4. Note that the _STA method is sometimes called prior to the _INI method
368 * (ACPI spec 6.3.7, _STA). See the special case for BAT_DEVICE_STATUS in
369 * acpiR3BatIndexWrite() for handling this. */
370 uint8_t u8IndexShift;
371 /** provide an I/O-APIC */
372 uint8_t u8UseIOApic;
373 /** provide a floppy controller */
374 bool fUseFdc;
375 /** If High Precision Event Timer device should be supported */
376 bool fUseHpet;
377 /** If System Management Controller device should be supported */
378 bool fUseSmc;
379 /** the guest handled the last power button event */
380 bool fPowerButtonHandled;
381 /** If ACPI CPU device should be shown */
382 bool fShowCpu;
383 /** If Real Time Clock ACPI object to be shown */
384 bool fShowRtc;
385 /** I/O port address of PM device. */
386 RTIOPORT uPmIoPortBase;
387 /** I/O port address of SMBus device. */
388 RTIOPORT uSMBusIoPortBase;
389 /** Which CPU to check for the locked status. */
390 uint32_t idCpuLockCheck;
391 /** Array of flags of attached CPUs */
392 VMCPUSET CpuSetAttached;
393 /** Mask of locked CPUs (used by the guest). */
394 VMCPUSET CpuSetLocked;
395 /** The CPU event type. */
396 uint32_t u32CpuEventType;
397 /** The CPU id affected. */
398 uint32_t u32CpuEvent;
399 /** Flag whether CPU hot plugging is enabled. */
400 bool fCpuHotPlug;
401 /** If MCFG ACPI table shown to the guest */
402 bool fUseMcfg;
403 /** if the 64-bit prefetchable memory window is shown to the guest */
404 bool fPciPref64Enabled;
405 /** If the IOMMU (AMD) device should be enabled */
406 bool fUseIommuAmd;
407 /** If the IOMMU (Intel) device should be enabled */
408 bool fUseIommuIntel;
409 /** Padding. */
410 bool afPadding0[3];
411 /** Primary NIC PCI address. */
412 uint32_t u32NicPciAddress;
413 /** HD Audio PCI address. */
414 uint32_t u32AudioPciAddress;
415 /** Primary NVMe controller PCI address. */
416 uint32_t u32NvmePciAddress;
417 /** Flag whether S1 power state is enabled. */
418 bool fS1Enabled;
419 /** Flag whether S4 power state is enabled. */
420 bool fS4Enabled;
421 /** Flag whether S1 triggers a state save. */
422 bool fSuspendToSavedState;
423 /** Flag whether to set WAK_STS on resume (restore included). */
424 bool fSetWakeupOnResume;
425 /** PCI address of the IO controller device. */
426 uint32_t u32IocPciAddress;
427 /** PCI address of the host bus controller device. */
428 uint32_t u32HbcPciAddress;
429 /** PCI address of the IOMMU device. */
430 uint32_t u32IommuPciAddress;
431 /** PCI address of the southbridge I/O APIC device. */
432 uint32_t u32SbIoApicPciAddress;
433
434 /** Physical address of PCI config space MMIO region */
435 uint64_t u64PciConfigMMioAddress;
436 /** Length of PCI config space MMIO region */
437 uint64_t u64PciConfigMMioLength;
438 /** Serial 0 IRQ number */
439 uint8_t uSerial0Irq;
440 /** Serial 1 IRQ number */
441 uint8_t uSerial1Irq;
442 /** Serial 2 IRQ number */
443 uint8_t uSerial2Irq;
444 /** Serial 3 IRQ number */
445 uint8_t uSerial3Irq;
446 /** Serial 0 IO port base */
447 RTIOPORT uSerial0IoPortBase;
448 /** Serial 1 IO port base */
449 RTIOPORT uSerial1IoPortBase;
450 /** Serial 2 IO port base */
451 RTIOPORT uSerial2IoPortBase;
452 /** Serial 3 IO port base */
453 RTIOPORT uSerial3IoPortBase;
454
455 /** @name Parallel port config bits
456 * @{ */
457 /** Parallel 0 IO port base */
458 RTIOPORT uParallel0IoPortBase;
459 /** Parallel 1 IO port base */
460 RTIOPORT uParallel1IoPortBase;
461 /** Parallel 0 IRQ number */
462 uint8_t uParallel0Irq;
463 /** Parallel 1 IRQ number */
464 uint8_t uParallel1Irq;
465 /** @} */
466
467#ifdef VBOX_WITH_TPM
468 /** @name TPM config bits
469 * @{ */
470 /** The ACPI TPM mode configured. */
471 ACPITPMMODE enmTpmMode;
472 /** The MMIO register area base address. */
473 RTGCPHYS GCPhysTpmMmio;
474 /** @} */
475#endif
476
477 /** Number of custom ACPI tables */
478 uint8_t cCustTbls;
479 /** ACPI OEM ID */
480 uint8_t au8OemId[6];
481 /** ACPI Crator ID */
482 uint8_t au8CreatorId[4];
483 uint8_t abAlignment2[3];
484 /** ACPI Crator Rev */
485 uint32_t u32CreatorRev;
486 /** ACPI custom OEM Tab ID */
487 uint8_t au8OemTabId[8];
488 /** ACPI custom OEM Rev */
489 uint32_t u32OemRevision;
490
491 /** SMBus Host Status Register */
492 uint8_t u8SMBusHstSts;
493 /** SMBus Slave Status Register */
494 uint8_t u8SMBusSlvSts;
495 /** SMBus Host Control Register */
496 uint8_t u8SMBusHstCnt;
497 /** SMBus Host Command Register */
498 uint8_t u8SMBusHstCmd;
499 /** SMBus Host Address Register */
500 uint8_t u8SMBusHstAdd;
501 /** SMBus Host Data 0 Register */
502 uint8_t u8SMBusHstDat0;
503 /** SMBus Host Data 1 Register */
504 uint8_t u8SMBusHstDat1;
505 /** SMBus Slave Control Register */
506 uint8_t u8SMBusSlvCnt;
507 /** SMBus Slave Event Register */
508 uint16_t u16SMBusSlvEvt;
509 /** SMBus Slave Data Register */
510 uint16_t u16SMBusSlvDat;
511 /** SMBus Shadow Command Register */
512 uint8_t u8SMBusShdwCmd;
513 /** SMBus Host Block Index */
514 uint8_t u8SMBusBlkIdx;
515 uint8_t abAlignment3[2];
516 /** SMBus Host Block Data Buffer */
517 uint8_t au8SMBusBlkDat[32];
518
519 /** @todo DEBUGGING */
520 uint32_t uPmTimeOld;
521 uint32_t uPmTimeA;
522 uint32_t uPmTimeB;
523 uint32_t Alignment5;
524
525 /** @name PM1a, PM timer and GPE0 I/O ports - mapped/unmapped as a group.
526 * @{ */
527 IOMIOPORTHANDLE hIoPortPm1aEn;
528 IOMIOPORTHANDLE hIoPortPm1aSts;
529 IOMIOPORTHANDLE hIoPortPm1aCtl;
530 IOMIOPORTHANDLE hIoPortPmTimer;
531 IOMIOPORTHANDLE hIoPortGpe0En;
532 IOMIOPORTHANDLE hIoPortGpe0Sts;
533 /** @} */
534
535 /** SMBus I/O ports (mapped/unmapped). */
536 IOMIOPORTHANDLE hIoPortSMBus;
537
538 /** @name Fixed I/O ports
539 * @{ */
540 /** ACPI SMI I/O port. */
541 IOMIOPORTHANDLE hIoPortSmi;
542 /** ACPI Debug hex I/O port. */
543 IOMIOPORTHANDLE hIoPortDebugHex;
544 /** ACPI Debug char I/O port. */
545 IOMIOPORTHANDLE hIoPortDebugChar;
546 /** ACPI Battery status index I/O port. */
547 IOMIOPORTHANDLE hIoPortBatteryIndex;
548 /** ACPI Battery status data I/O port. */
549 IOMIOPORTHANDLE hIoPortBatteryData;
550 /** ACPI system info index I/O port. */
551 IOMIOPORTHANDLE hIoPortSysInfoIndex;
552 /** ACPI system info data I/O port. */
553 IOMIOPORTHANDLE hIoPortSysInfoData;
554 /** ACPI Reset I/O port. */
555 IOMIOPORTHANDLE hIoPortReset;
556 /** @} */
557
558} ACPISTATE;
559/** Pointer to the shared ACPI device state. */
560typedef ACPISTATE *PACPISTATE;
561
562
563
564/**
565 * The ring-3 ACPI device state.
566 */
567typedef struct ACPISTATER3
568{
569 /** ACPI port base interface. */
570 PDMIBASE IBase;
571 /** ACPI port interface. */
572 PDMIACPIPORT IACPIPort;
573 /** Pointer to the device instance so we can get our bearings from
574 * interface functions. */
575 PPDMDEVINSR3 pDevIns;
576
577 /** Pointer to the driver base interface. */
578 R3PTRTYPE(PPDMIBASE) pDrvBase;
579 /** Pointer to the driver connector interface. */
580 R3PTRTYPE(PPDMIACPICONNECTOR) pDrv;
581
582 /** Custom ACPI tables binary data. */
583 R3PTRTYPE(uint8_t *) apu8CustBin[MAX_CUST_TABLES];
584 /** The size of the custom table binary. */
585 uint64_t acbCustBin[MAX_CUST_TABLES];
586} ACPISTATER3;
587/** Pointer to the ring-3 ACPI device state. */
588typedef ACPISTATER3 *PACPISTATER3;
589
590
591#pragma pack(1)
592
593/** Generic Address Structure (see ACPIspec 3.0, 5.2.3.1) */
594struct ACPIGENADDR
595{
596 uint8_t u8AddressSpaceId; /**< 0=sys, 1=IO, 2=PCICfg, 3=emb, 4=SMBus */
597 uint8_t u8RegisterBitWidth; /**< size in bits of the given register */
598 uint8_t u8RegisterBitOffset; /**< bit offset of register */
599 uint8_t u8AccessSize; /**< 1=byte, 2=word, 3=dword, 4=qword */
600 uint64_t u64Address; /**< 64-bit address of register */
601};
602AssertCompileSize(ACPIGENADDR, 12);
603
604/** Root System Description Pointer */
605struct ACPITBLRSDP
606{
607 uint8_t au8Signature[8]; /**< 'RSD PTR ' */
608 uint8_t u8Checksum; /**< checksum for the first 20 bytes */
609 uint8_t au8OemId[6]; /**< OEM-supplied identifier */
610 uint8_t u8Revision; /**< revision number, currently 2 */
611#define ACPI_REVISION 2 /**< ACPI 3.0 */
612 uint32_t u32RSDT; /**< phys addr of RSDT */
613 uint32_t u32Length; /**< bytes of this table */
614 uint64_t u64XSDT; /**< 64-bit phys addr of XSDT */
615 uint8_t u8ExtChecksum; /**< checksum of entire table */
616 uint8_t u8Reserved[3]; /**< reserved */
617};
618AssertCompileSize(ACPITBLRSDP, 36);
619
620/** System Description Table Header */
621struct ACPITBLHEADER
622{
623 uint8_t au8Signature[4]; /**< table identifier */
624 uint32_t u32Length; /**< length of the table including header */
625 uint8_t u8Revision; /**< revision number */
626 uint8_t u8Checksum; /**< all fields inclusive this add to zero */
627 uint8_t au8OemId[6]; /**< OEM-supplied string */
628 uint8_t au8OemTabId[8]; /**< to identify the particular data table */
629 uint32_t u32OemRevision; /**< OEM-supplied revision number */
630 uint8_t au8CreatorId[4]; /**< ID for the ASL compiler */
631 uint32_t u32CreatorRev; /**< revision for the ASL compiler */
632};
633AssertCompileSize(ACPITBLHEADER, 36);
634
635/** Root System Description Table */
636struct ACPITBLRSDT
637{
638 ACPITBLHEADER header;
639 uint32_t u32Entry[1]; /**< array of phys. addresses to other tables */
640};
641AssertCompileSize(ACPITBLRSDT, 40);
642
643/** Extended System Description Table */
644struct ACPITBLXSDT
645{
646 ACPITBLHEADER header;
647 uint64_t u64Entry[1]; /**< array of phys. addresses to other tables */
648};
649AssertCompileSize(ACPITBLXSDT, 44);
650
651/** Fixed ACPI Description Table */
652struct ACPITBLFADT
653{
654 ACPITBLHEADER header;
655 uint32_t u32FACS; /**< phys. address of FACS */
656 uint32_t u32DSDT; /**< phys. address of DSDT */
657 uint8_t u8IntModel; /**< was eleminated in ACPI 2.0 */
658#define INT_MODEL_DUAL_PIC 1 /**< for ACPI 2+ */
659#define INT_MODEL_MULTIPLE_APIC 2
660 uint8_t u8PreferredPMProfile; /**< preferred power management profile */
661 uint16_t u16SCIInt; /**< system vector the SCI is wired in 8259 mode */
662#define SCI_INT 9
663 uint32_t u32SMICmd; /**< system port address of SMI command port */
664#define SMI_CMD 0x0000442e
665 uint8_t u8AcpiEnable; /**< SMICmd val to disable ownership of ACPIregs */
666#define ACPI_ENABLE 0xa1
667 uint8_t u8AcpiDisable; /**< SMICmd val to re-enable ownership of ACPIregs */
668#define ACPI_DISABLE 0xa0
669 uint8_t u8S4BIOSReq; /**< SMICmd val to enter S4BIOS state */
670 uint8_t u8PStateCnt; /**< SMICmd val to assume processor performance
671 state control responsibility */
672 uint32_t u32PM1aEVTBLK; /**< port addr of PM1a event regs block */
673 uint32_t u32PM1bEVTBLK; /**< port addr of PM1b event regs block */
674 uint32_t u32PM1aCTLBLK; /**< port addr of PM1a control regs block */
675 uint32_t u32PM1bCTLBLK; /**< port addr of PM1b control regs block */
676 uint32_t u32PM2CTLBLK; /**< port addr of PM2 control regs block */
677 uint32_t u32PMTMRBLK; /**< port addr of PMTMR regs block */
678 uint32_t u32GPE0BLK; /**< port addr of gen-purp event 0 regs block */
679 uint32_t u32GPE1BLK; /**< port addr of gen-purp event 1 regs block */
680 uint8_t u8PM1EVTLEN; /**< bytes decoded by PM1a_EVT_BLK. >= 4 */
681 uint8_t u8PM1CTLLEN; /**< bytes decoded by PM1b_CNT_BLK. >= 2 */
682 uint8_t u8PM2CTLLEN; /**< bytes decoded by PM2_CNT_BLK. >= 1 or 0 */
683 uint8_t u8PMTMLEN; /**< bytes decoded by PM_TMR_BLK. ==4 */
684 uint8_t u8GPE0BLKLEN; /**< bytes decoded by GPE0_BLK. %2==0 */
685#define GPE0_BLK_LEN 2
686 uint8_t u8GPE1BLKLEN; /**< bytes decoded by GPE1_BLK. %2==0 */
687#define GPE1_BLK_LEN 0
688 uint8_t u8GPE1BASE; /**< offset of GPE1 based events */
689#define GPE1_BASE 0
690 uint8_t u8CSTCNT; /**< SMICmd val to indicate OS supp for C states */
691 uint16_t u16PLVL2LAT; /**< us to enter/exit C2. >100 => unsupported */
692#define P_LVL2_LAT 101 /**< C2 state not supported */
693 uint16_t u16PLVL3LAT; /**< us to enter/exit C3. >1000 => unsupported */
694#define P_LVL3_LAT 1001 /**< C3 state not supported */
695 uint16_t u16FlushSize; /**< # of flush strides to read to flush dirty
696 lines from any processors memory caches */
697#define FLUSH_SIZE 0 /**< Ignored if WBVIND set in FADT_FLAGS */
698 uint16_t u16FlushStride; /**< cache line width */
699#define FLUSH_STRIDE 0 /**< Ignored if WBVIND set in FADT_FLAGS */
700 uint8_t u8DutyOffset;
701 uint8_t u8DutyWidth;
702 uint8_t u8DayAlarm; /**< RTC CMOS RAM index of day-of-month alarm */
703 uint8_t u8MonAlarm; /**< RTC CMOS RAM index of month-of-year alarm */
704 uint8_t u8Century; /**< RTC CMOS RAM index of century */
705 uint16_t u16IAPCBOOTARCH; /**< IA-PC boot architecture flags */
706#define IAPC_BOOT_ARCH_LEGACY_DEV RT_BIT(0) /**< legacy devices present such as LPT
707 (COM too?) */
708#define IAPC_BOOT_ARCH_8042 RT_BIT(1) /**< legacy keyboard device present */
709#define IAPC_BOOT_ARCH_NO_VGA RT_BIT(2) /**< VGA not present */
710#define IAPC_BOOT_ARCH_NO_MSI RT_BIT(3) /**< OSPM must not enable MSIs on this platform */
711#define IAPC_BOOT_ARCH_NO_ASPM RT_BIT(4) /**< OSPM must not enable ASPM on this platform */
712 uint8_t u8Must0_0; /**< must be 0 */
713 uint32_t u32Flags; /**< fixed feature flags */
714#define FADT_FL_WBINVD RT_BIT(0) /**< emulation of WBINVD available */
715#define FADT_FL_WBINVD_FLUSH RT_BIT(1)
716#define FADT_FL_PROC_C1 RT_BIT(2) /**< 1=C1 supported on all processors */
717#define FADT_FL_P_LVL2_UP RT_BIT(3) /**< 1=C2 works on SMP and UNI systems */
718#define FADT_FL_PWR_BUTTON RT_BIT(4) /**< 1=power button handled as ctrl method dev */
719#define FADT_FL_SLP_BUTTON RT_BIT(5) /**< 1=sleep button handled as ctrl method dev */
720#define FADT_FL_FIX_RTC RT_BIT(6) /**< 0=RTC wake status in fixed register */
721#define FADT_FL_RTC_S4 RT_BIT(7) /**< 1=RTC can wake system from S4 */
722#define FADT_FL_TMR_VAL_EXT RT_BIT(8) /**< 1=TMR_VAL implemented as 32 bit */
723#define FADT_FL_DCK_CAP RT_BIT(9) /**< 0=system cannot support docking */
724#define FADT_FL_RESET_REG_SUP RT_BIT(10) /**< 1=system supports system resets */
725#define FADT_FL_SEALED_CASE RT_BIT(11) /**< 1=case is sealed */
726#define FADT_FL_HEADLESS RT_BIT(12) /**< 1=system cannot detect moni/keyb/mouse */
727#define FADT_FL_CPU_SW_SLP RT_BIT(13)
728#define FADT_FL_PCI_EXT_WAK RT_BIT(14) /**< 1=system supports PCIEXP_WAKE_STS */
729#define FADT_FL_USE_PLATFORM_CLOCK RT_BIT(15) /**< 1=system has ACPI PM timer */
730#define FADT_FL_S4_RTC_STS_VALID RT_BIT(16) /**< 1=RTC_STS flag is valid when waking from S4 */
731#define FADT_FL_REMOVE_POWER_ON_CAPABLE RT_BIT(17) /**< 1=platform can remote power on */
732#define FADT_FL_FORCE_APIC_CLUSTER_MODEL RT_BIT(18)
733#define FADT_FL_FORCE_APIC_PHYS_DEST_MODE RT_BIT(19)
734
735/* PM Timer mask and msb */
736#ifndef PM_TMR_32BIT
737#define TMR_VAL_MSB 0x800000
738#define TMR_VAL_MASK 0xffffff
739#undef FADT_FL_TMR_VAL_EXT
740#define FADT_FL_TMR_VAL_EXT 0
741#else
742#define TMR_VAL_MSB 0x80000000
743#define TMR_VAL_MASK 0xffffffff
744#endif
745
746 /** Start of the ACPI 2.0 extension. */
747 ACPIGENADDR ResetReg; /**< ext addr of reset register */
748 uint8_t u8ResetVal; /**< ResetReg value to reset the system */
749#define ACPI_RESET_REG_VAL 0x10
750 uint8_t au8Must0_1[3]; /**< must be 0 */
751 uint64_t u64XFACS; /**< 64-bit phys address of FACS */
752 uint64_t u64XDSDT; /**< 64-bit phys address of DSDT */
753 ACPIGENADDR X_PM1aEVTBLK; /**< ext addr of PM1a event regs block */
754 ACPIGENADDR X_PM1bEVTBLK; /**< ext addr of PM1b event regs block */
755 ACPIGENADDR X_PM1aCTLBLK; /**< ext addr of PM1a control regs block */
756 ACPIGENADDR X_PM1bCTLBLK; /**< ext addr of PM1b control regs block */
757 ACPIGENADDR X_PM2CTLBLK; /**< ext addr of PM2 control regs block */
758 ACPIGENADDR X_PMTMRBLK; /**< ext addr of PMTMR control regs block */
759 ACPIGENADDR X_GPE0BLK; /**< ext addr of GPE1 regs block */
760 ACPIGENADDR X_GPE1BLK; /**< ext addr of GPE1 regs block */
761};
762AssertCompileSize(ACPITBLFADT, 244);
763#define ACPITBLFADT_VERSION1_SIZE RT_OFFSETOF(ACPITBLFADT, ResetReg)
764
765/** Firmware ACPI Control Structure */
766struct ACPITBLFACS
767{
768 uint8_t au8Signature[4]; /**< 'FACS' */
769 uint32_t u32Length; /**< bytes of entire FACS structure >= 64 */
770 uint32_t u32HWSignature; /**< systems HW signature at last boot */
771 uint32_t u32FWVector; /**< address of waking vector */
772 uint32_t u32GlobalLock; /**< global lock to sync HW/SW */
773 uint32_t u32Flags; /**< FACS flags */
774 uint64_t u64X_FWVector; /**< 64-bit waking vector */
775 uint8_t u8Version; /**< version of this table */
776 uint8_t au8Reserved[31]; /**< zero */
777};
778AssertCompileSize(ACPITBLFACS, 64);
779
780/** Processor Local APIC Structure */
781struct ACPITBLLAPIC
782{
783 uint8_t u8Type; /**< 0 = LAPIC */
784 uint8_t u8Length; /**< 8 */
785 uint8_t u8ProcId; /**< processor ID */
786 uint8_t u8ApicId; /**< local APIC ID */
787 uint32_t u32Flags; /**< Flags */
788#define LAPIC_ENABLED 0x1
789};
790AssertCompileSize(ACPITBLLAPIC, 8);
791
792/** I/O APIC Structure */
793struct ACPITBLIOAPIC
794{
795 uint8_t u8Type; /**< 1 == I/O APIC */
796 uint8_t u8Length; /**< 12 */
797 uint8_t u8IOApicId; /**< I/O APIC ID */
798 uint8_t u8Reserved; /**< 0 */
799 uint32_t u32Address; /**< phys address to access I/O APIC */
800 uint32_t u32GSIB; /**< global system interrupt number to start */
801};
802AssertCompileSize(ACPITBLIOAPIC, 12);
803
804/** Interrupt Source Override Structure */
805struct ACPITBLISO
806{
807 uint8_t u8Type; /**< 2 == Interrupt Source Override*/
808 uint8_t u8Length; /**< 10 */
809 uint8_t u8Bus; /**< Bus */
810 uint8_t u8Source; /**< Bus-relative interrupt source (IRQ) */
811 uint32_t u32GSI; /**< Global System Interrupt */
812 uint16_t u16Flags; /**< MPS INTI flags Global */
813};
814AssertCompileSize(ACPITBLISO, 10);
815#define NUMBER_OF_IRQ_SOURCE_OVERRIDES 2
816
817/** HPET Descriptor Structure */
818struct ACPITBLHPET
819{
820 ACPITBLHEADER aHeader;
821 uint32_t u32Id; /**< hardware ID of event timer block
822 [31:16] PCI vendor ID of first timer block
823 [15] legacy replacement IRQ routing capable
824 [14] reserved
825 [13] COUNT_SIZE_CAP counter size
826 [12:8] number of comparators in first timer block
827 [7:0] hardware rev ID */
828 ACPIGENADDR HpetAddr; /**< lower 32-bit base address */
829 uint8_t u32Number; /**< sequence number starting at 0 */
830 uint16_t u32MinTick; /**< minimum clock ticks which can be set without
831 lost interrupts while the counter is programmed
832 to operate in periodic mode. Unit: clock tick. */
833 uint8_t u8Attributes; /**< page protection and OEM attribute. */
834};
835AssertCompileSize(ACPITBLHPET, 56);
836
837#ifdef VBOX_WITH_IOMMU_AMD
838/** AMD IOMMU: IVRS (I/O Virtualization Reporting Structure).
839 * In accordance with the AMD spec. */
840typedef struct ACPIIVRS
841{
842 ACPITBLHEADER header;
843 uint32_t u32IvInfo; /**< IVInfo: I/O virtualization info. common to all IOMMUs in the system. */
844 uint64_t u64Rsvd; /**< Reserved (MBZ). */
845 /* IVHD type block follows. */
846} ACPIIVRS;
847AssertCompileSize(ACPIIVRS, 48);
848AssertCompileMemberOffset(ACPIIVRS, u32IvInfo, 36);
849
850/**
851 * AMD IOMMU: The ACPI table.
852 */
853typedef struct ACPITBLIOMMU
854{
855 ACPIIVRS Hdr;
856 ACPIIVHDTYPE10 IvhdType10;
857 ACPIIVHDDEVENTRY4 IvhdType10Start;
858 ACPIIVHDDEVENTRY4 IvhdType10End;
859 ACPIIVHDDEVENTRY4 IvhdType10Rsvd0;
860 ACPIIVHDDEVENTRY4 IvhdType10Rsvd1;
861 ACPIIVHDDEVENTRY8 IvhdType10IoApic;
862 ACPIIVHDDEVENTRY8 IvhdType10Hpet;
863
864 ACPIIVHDTYPE11 IvhdType11;
865 ACPIIVHDDEVENTRY4 IvhdType11Start;
866 ACPIIVHDDEVENTRY4 IvhdType11End;
867 ACPIIVHDDEVENTRY4 IvhdType11Rsvd0;
868 ACPIIVHDDEVENTRY4 IvhdType11Rsvd1;
869 ACPIIVHDDEVENTRY8 IvhdType11IoApic;
870 ACPIIVHDDEVENTRY8 IvhdType11Hpet;
871} ACPITBLIOMMU;
872AssertCompileMemberAlignment(ACPITBLIOMMU, IvhdType10Start, 4);
873AssertCompileMemberAlignment(ACPITBLIOMMU, IvhdType10End, 4);
874AssertCompileMemberAlignment(ACPITBLIOMMU, IvhdType11Start, 4);
875AssertCompileMemberAlignment(ACPITBLIOMMU, IvhdType11End, 4);
876#endif /* VBOX_WITH_IOMMU_AMD */
877
878#ifdef VBOX_WITH_IOMMU_INTEL
879/** Intel IOMMU: DMAR (DMA Remapping) Reporting Structure.
880 * In accordance with the AMD spec. */
881typedef struct ACPIDMAR
882{
883 ACPITBLHEADER Hdr;
884 /** Host-address Width (N+1 physical bits addressable). */
885 uint8_t uHostAddrWidth;
886 /** Flags, see ACPI_DMAR_F_XXX. */
887 uint8_t fFlags;
888 /** Reserved. */
889 uint8_t abRsvd[10];
890 /* Remapping Structures[] follows. */
891} ACPIDMAR;
892AssertCompileSize(ACPIDMAR, 48);
893AssertCompileMemberOffset(ACPIDMAR, uHostAddrWidth, 36);
894AssertCompileMemberOffset(ACPIDMAR, fFlags, 37);
895
896/**
897 * Intel VT-d: The ACPI table.
898 */
899typedef struct ACPITBLVTD
900{
901 ACPIDMAR Dmar;
902 ACPIDRHD Drhd;
903 ACPIDMARDEVSCOPE DevScopeIoApic;
904} ACPITBLVTD;
905#endif /* VBOX_WITH_IOMMU_INTEL */
906
907/** MCFG Descriptor Structure */
908typedef struct ACPITBLMCFG
909{
910 ACPITBLHEADER aHeader;
911 uint64_t u64Reserved;
912} ACPITBLMCFG;
913AssertCompileSize(ACPITBLMCFG, 44);
914
915/** Number of such entries can be computed from the whole table length in header */
916typedef struct ACPITBLMCFGENTRY
917{
918 uint64_t u64BaseAddress;
919 uint16_t u16PciSegmentGroup;
920 uint8_t u8StartBus;
921 uint8_t u8EndBus;
922 uint32_t u32Reserved;
923} ACPITBLMCFGENTRY;
924AssertCompileSize(ACPITBLMCFGENTRY, 16);
925
926#define PCAT_COMPAT 0x1 /**< system has also a dual-8259 setup */
927
928/** Custom Description Table */
929struct ACPITBLCUST
930{
931 ACPITBLHEADER header;
932 uint8_t au8Data[476];
933};
934AssertCompileSize(ACPITBLCUST, 512);
935
936
937#ifdef VBOX_WITH_TPM
938/**
939 * TPM: The ACPI table for a TPM 2.0 device
940 * (from: https://trustedcomputinggroup.org/wp-content/uploads/TCG_ACPIGeneralSpec_v1p3_r8_pub.pdf).
941 */
942typedef struct ACPITBLTPM20
943{
944 /** The common ACPI table header. */
945 ACPITBLHEADER Hdr;
946 /** The platform class. */
947 uint16_t u16PlatCls;
948 /** Reserved. */
949 uint16_t u16Rsvd0;
950 /** Address of the CRB control area or FIFO base address. */
951 uint64_t u64BaseAddrCrbOrFifo;
952 /** The start method selector. */
953 uint32_t u32StartMethod;
954 /** Following are start method specific parameters and optional LAML and LASA fields we don't implement right now. */
955 /** @todo */
956} ACPITBLTPM20;
957AssertCompileSize(ACPITBLTPM20, 52);
958
959/** Revision of the TPM2.0 ACPI table. */
960#define ACPI_TPM20_REVISION 4
961/** The default MMIO base address of the TPM. */
962#define ACPI_TPM_MMIO_BASE_DEFAULT 0xfed40000
963
964
965/** @name Possible values for the ACPITBLTPM20::u16PlatCls member.
966 * @{ */
967/** Client platform. */
968#define ACPITBL_TPM20_PLAT_CLS_CLIENT UINT16_C(0)
969/** Server platform. */
970#define ACPITBL_TPM20_PLAT_CLS_SERVER UINT16_C(1)
971/** @} */
972
973
974/** @name Possible values for the ACPITBLTPM20::u32StartMethod member.
975 * @{ */
976/** MMIO interface (TIS1.2+Cancel). */
977#define ACPITBL_TPM20_START_METHOD_TIS12 UINT16_C(6)
978/** CRB interface. */
979#define ACPITBL_TPM20_START_METHOD_CRB UINT16_C(7)
980/** @} */
981
982
983/**
984 * TPM: The ACPI table for a TPM 1.2 device
985 * (from: https://trustedcomputinggroup.org/wp-content/uploads/TCG_ACPIGeneralSpecification_v1.20_r8.pdf).
986 */
987typedef struct ACPITBLTCPA
988{
989 /** The common ACPI table header. */
990 ACPITBLHEADER Hdr;
991 /** The platform class. */
992 uint16_t u16PlatCls;
993 /** Log Area Minimum Length. */
994 uint32_t u32Laml;
995 /** Log Area Start Address. */
996 uint64_t u64Lasa;
997} ACPITBLTCPA;
998AssertCompileSize(ACPITBLTCPA, 50);
999
1000/** Revision of the TPM1.2 ACPI table. */
1001#define ACPI_TCPA_REVISION 2
1002/** LAML region size. */
1003#define ACPI_TCPA_LAML_SZ _16K
1004
1005
1006/** @name Possible values for the ACPITBLTCPA::u16PlatCls member.
1007 * @{ */
1008/** Client platform. */
1009#define ACPI_TCPA_PLAT_CLS_CLIENT UINT16_C(0)
1010/** @} */
1011#endif
1012
1013
1014#pragma pack()
1015
1016
1017#ifndef VBOX_DEVICE_STRUCT_TESTCASE /* exclude the rest of the file */
1018
1019
1020/*********************************************************************************************************************************
1021* Internal Functions *
1022*********************************************************************************************************************************/
1023#ifdef IN_RING3
1024static int acpiR3PlantTables(PPDMDEVINS pDevIns, PACPISTATE pThis, PACPISTATER3 pThisCC);
1025#endif
1026
1027/* SCI, usually IRQ9 */
1028DECLINLINE(void) acpiSetIrq(PPDMDEVINS pDevIns, int level)
1029{
1030 PDMDevHlpPCISetIrq(pDevIns, 0, level);
1031}
1032
1033DECLINLINE(bool) pm1a_level(PACPISTATE pThis)
1034{
1035 return (pThis->pm1a_ctl & SCI_EN)
1036 && (pThis->pm1a_en & pThis->pm1a_sts & ~(RSR_EN | IGN_EN));
1037}
1038
1039DECLINLINE(bool) gpe0_level(PACPISTATE pThis)
1040{
1041 return !!(pThis->gpe0_en & pThis->gpe0_sts);
1042}
1043
1044DECLINLINE(bool) smbus_level(PPDMDEVINS pDevIns, PACPISTATE pThis)
1045{
1046 PPDMPCIDEV pPciDev = pDevIns->apPciDevs[0];
1047 return (pThis->u8SMBusHstCnt & SMBHSTCNT_INTEREN)
1048 && (pPciDev->abConfig[SMBHSTCFG] & SMBHSTCFG_SMB_HST_EN)
1049 && (pPciDev->abConfig[SMBHSTCFG] & SMBHSTCFG_INTRSEL) == SMBHSTCFG_INTRSEL_IRQ9 << SMBHSTCFG_INTRSEL_SHIFT
1050 && (pThis->u8SMBusHstSts & SMBHSTSTS_INT_MASK);
1051}
1052
1053DECLINLINE(bool) acpiSCILevel(PPDMDEVINS pDevIns, PACPISTATE pThis)
1054{
1055 return pm1a_level(pThis) || gpe0_level(pThis) || smbus_level(pDevIns, pThis);
1056}
1057
1058/**
1059 * Used by acpiR3PM1aStsWrite, acpiR3PM1aEnWrite, acpiR3PmTimer,
1060 * acpiR3Port_PowerBuffonPress, acpiR3Port_SleepButtonPress
1061 * and acpiPmTmrRead to update the PM1a.STS and PM1a.EN
1062 * registers and trigger IRQs.
1063 *
1064 * Caller must hold the state lock.
1065 *
1066 * @param pDevIns The PDM device instance.
1067 * @param pThis The ACPI shared instance data.
1068 * @param sts The new PM1a.STS value.
1069 * @param en The new PM1a.EN value.
1070 */
1071static void acpiUpdatePm1a(PPDMDEVINS pDevIns, PACPISTATE pThis, uint32_t sts, uint32_t en)
1072{
1073 Assert(PDMDevHlpCritSectIsOwner(pDevIns, &pThis->CritSect));
1074
1075 const bool old_level = acpiSCILevel(pDevIns, pThis);
1076 pThis->pm1a_en = en;
1077 pThis->pm1a_sts = sts;
1078 const bool new_level = acpiSCILevel(pDevIns, pThis);
1079
1080 LogFunc(("old=%x new=%x\n", old_level, new_level));
1081
1082 if (new_level != old_level)
1083 acpiSetIrq(pDevIns, new_level);
1084}
1085
1086#ifdef IN_RING3
1087
1088/**
1089 * Used by acpiR3Gpe0StsWrite, acpiR3Gpe0EnWrite, acpiAttach and acpiDetach to
1090 * update the GPE0.STS and GPE0.EN registers and trigger IRQs.
1091 *
1092 * Caller must hold the state lock.
1093 *
1094 * @param pDevIns The PDM device instance.
1095 * @param pThis The ACPI shared instance data.
1096 * @param sts The new GPE0.STS value.
1097 * @param en The new GPE0.EN value.
1098 */
1099static void apicR3UpdateGpe0(PPDMDEVINS pDevIns, PACPISTATE pThis, uint32_t sts, uint32_t en)
1100{
1101 Assert(PDMDevHlpCritSectIsOwner(pDevIns, &pThis->CritSect));
1102
1103 const bool old_level = acpiSCILevel(pDevIns, pThis);
1104 pThis->gpe0_en = en;
1105 pThis->gpe0_sts = sts;
1106 const bool new_level = acpiSCILevel(pDevIns, pThis);
1107
1108 LogFunc(("old=%x new=%x\n", old_level, new_level));
1109
1110 if (new_level != old_level)
1111 acpiSetIrq(pDevIns, new_level);
1112}
1113
1114/**
1115 * Used by acpiR3PM1aCtlWrite to power off the VM.
1116 *
1117 * @param pDevIns The device instance.
1118 * @returns Strict VBox status code.
1119 */
1120static VBOXSTRICTRC acpiR3DoPowerOff(PPDMDEVINS pDevIns)
1121{
1122 VBOXSTRICTRC rc = PDMDevHlpVMPowerOff(pDevIns);
1123 AssertRC(VBOXSTRICTRC_VAL(rc));
1124 return rc;
1125}
1126
1127/**
1128 * Used by acpiR3PM1aCtlWrite to put the VM to sleep.
1129 *
1130 * @param pDevIns The device instance.
1131 * @param pThis The ACPI shared instance data.
1132 * @returns Strict VBox status code.
1133 */
1134static VBOXSTRICTRC acpiR3DoSleep(PPDMDEVINS pDevIns, PACPISTATE pThis)
1135{
1136 /* We must set WAK_STS on resume (includes restore) so the guest knows that
1137 we've woken up and can continue executing code. The guest is probably
1138 reading the PMSTS register in a loop to check this. */
1139 VBOXSTRICTRC rc;
1140 pThis->fSetWakeupOnResume = true;
1141 if (pThis->fSuspendToSavedState)
1142 {
1143 rc = PDMDevHlpVMSuspendSaveAndPowerOff(pDevIns);
1144 if (rc != VERR_NOT_SUPPORTED)
1145 AssertRC(VBOXSTRICTRC_VAL(rc));
1146 else
1147 {
1148 LogRel(("ACPI: PDMDevHlpVMSuspendSaveAndPowerOff is not supported, falling back to suspend-only\n"));
1149 rc = PDMDevHlpVMSuspend(pDevIns);
1150 AssertRC(VBOXSTRICTRC_VAL(rc));
1151 }
1152 }
1153 else
1154 {
1155 rc = PDMDevHlpVMSuspend(pDevIns);
1156 AssertRC(VBOXSTRICTRC_VAL(rc));
1157 }
1158 return rc;
1159}
1160
1161
1162/**
1163 * @interface_method_impl{PDMIACPIPORT,pfnPowerButtonPress}
1164 */
1165static DECLCALLBACK(int) acpiR3Port_PowerButtonPress(PPDMIACPIPORT pInterface)
1166{
1167 PACPISTATER3 pThisCC = RT_FROM_MEMBER(pInterface, ACPISTATER3, IACPIPort);
1168 PPDMDEVINS pDevIns = pThisCC->pDevIns;
1169 PACPISTATE pThis = PDMDEVINS_2_DATA(pDevIns, PACPISTATE);
1170 DEVACPI_LOCK_R3(pDevIns, pThis);
1171
1172 Log(("acpiR3Port_PowerButtonPress: handled=%d status=%x\n", pThis->fPowerButtonHandled, pThis->pm1a_sts));
1173 pThis->fPowerButtonHandled = false;
1174 acpiUpdatePm1a(pDevIns, pThis, pThis->pm1a_sts | PWRBTN_STS, pThis->pm1a_en);
1175
1176 DEVACPI_UNLOCK(pDevIns, pThis);
1177 return VINF_SUCCESS;
1178}
1179
1180/**
1181 * @interface_method_impl{PDMIACPIPORT,pfnGetPowerButtonHandled}
1182 */
1183static DECLCALLBACK(int) acpiR3Port_GetPowerButtonHandled(PPDMIACPIPORT pInterface, bool *pfHandled)
1184{
1185 PACPISTATER3 pThisCC = RT_FROM_MEMBER(pInterface, ACPISTATER3, IACPIPort);
1186 PPDMDEVINS pDevIns = pThisCC->pDevIns;
1187 PACPISTATE pThis = PDMDEVINS_2_DATA(pDevIns, PACPISTATE);
1188 DEVACPI_LOCK_R3(pDevIns, pThis);
1189
1190 *pfHandled = pThis->fPowerButtonHandled;
1191
1192 DEVACPI_UNLOCK(pDevIns, pThis);
1193 return VINF_SUCCESS;
1194}
1195
1196/**
1197 * @interface_method_impl{PDMIACPIPORT,pfnGetGuestEnteredACPIMode, Check if the
1198 * Guest entered into G0 (working) or G1 (sleeping)}
1199 */
1200static DECLCALLBACK(int) acpiR3Port_GetGuestEnteredACPIMode(PPDMIACPIPORT pInterface, bool *pfEntered)
1201{
1202 PACPISTATER3 pThisCC = RT_FROM_MEMBER(pInterface, ACPISTATER3, IACPIPort);
1203 PPDMDEVINS pDevIns = pThisCC->pDevIns;
1204 PACPISTATE pThis = PDMDEVINS_2_DATA(pDevIns, PACPISTATE);
1205 DEVACPI_LOCK_R3(pDevIns, pThis);
1206
1207 *pfEntered = (pThis->pm1a_ctl & SCI_EN) != 0;
1208
1209 DEVACPI_UNLOCK(pDevIns, pThis);
1210 return VINF_SUCCESS;
1211}
1212
1213/**
1214 * @interface_method_impl{PDMIACPIPORT,pfnGetCpuStatus}
1215 */
1216static DECLCALLBACK(int) acpiR3Port_GetCpuStatus(PPDMIACPIPORT pInterface, unsigned uCpu, bool *pfLocked)
1217{
1218 PACPISTATER3 pThisCC = RT_FROM_MEMBER(pInterface, ACPISTATER3, IACPIPort);
1219 PPDMDEVINS pDevIns = pThisCC->pDevIns;
1220 PACPISTATE pThis = PDMDEVINS_2_DATA(pDevIns, PACPISTATE);
1221 DEVACPI_LOCK_R3(pDevIns, pThis);
1222
1223 *pfLocked = VMCPUSET_IS_PRESENT(&pThis->CpuSetLocked, uCpu);
1224
1225 DEVACPI_UNLOCK(pDevIns, pThis);
1226 return VINF_SUCCESS;
1227}
1228
1229/**
1230 * Send an ACPI sleep button event.
1231 *
1232 * @returns VBox status code
1233 * @param pInterface Pointer to the interface structure containing the called function pointer.
1234 */
1235static DECLCALLBACK(int) acpiR3Port_SleepButtonPress(PPDMIACPIPORT pInterface)
1236{
1237 PACPISTATER3 pThisCC = RT_FROM_MEMBER(pInterface, ACPISTATER3, IACPIPort);
1238 PPDMDEVINS pDevIns = pThisCC->pDevIns;
1239 PACPISTATE pThis = PDMDEVINS_2_DATA(pDevIns, PACPISTATE);
1240 DEVACPI_LOCK_R3(pDevIns, pThis);
1241
1242 acpiUpdatePm1a(pDevIns, pThis, pThis->pm1a_sts | SLPBTN_STS, pThis->pm1a_en);
1243
1244 DEVACPI_UNLOCK(pDevIns, pThis);
1245 return VINF_SUCCESS;
1246}
1247
1248/**
1249 * Send an ACPI monitor hot-plug event.
1250 *
1251 * @returns VBox status code
1252 * @param pInterface Pointer to the interface structure containing the
1253 * called function pointer.
1254 */
1255static DECLCALLBACK(int) acpiR3Port_MonitorHotPlugEvent(PPDMIACPIPORT pInterface)
1256{
1257 PACPISTATER3 pThisCC = RT_FROM_MEMBER(pInterface, ACPISTATER3, IACPIPort);
1258 PPDMDEVINS pDevIns = pThisCC->pDevIns;
1259 PACPISTATE pThis = PDMDEVINS_2_DATA(pDevIns, PACPISTATE);
1260 DEVACPI_LOCK_R3(pDevIns, pThis);
1261
1262 apicR3UpdateGpe0(pDevIns, pThis, pThis->gpe0_sts | 0x4, pThis->gpe0_en);
1263
1264 DEVACPI_UNLOCK(pDevIns, pThis);
1265 return VINF_SUCCESS;
1266}
1267
1268/**
1269 * Send an ACPI battery status change event.
1270 *
1271 * @returns VBox status code
1272 * @param pInterface Pointer to the interface structure containing the
1273 * called function pointer.
1274 */
1275static DECLCALLBACK(int) acpiR3Port_BatteryStatusChangeEvent(PPDMIACPIPORT pInterface)
1276{
1277 PACPISTATER3 pThisCC = RT_FROM_MEMBER(pInterface, ACPISTATER3, IACPIPort);
1278 PPDMDEVINS pDevIns = pThisCC->pDevIns;
1279 PACPISTATE pThis = PDMDEVINS_2_DATA(pDevIns, PACPISTATE);
1280 DEVACPI_LOCK_R3(pDevIns, pThis);
1281
1282 apicR3UpdateGpe0(pDevIns, pThis, pThis->gpe0_sts | 0x1, pThis->gpe0_en);
1283
1284 DEVACPI_UNLOCK(pDevIns, pThis);
1285 return VINF_SUCCESS;
1286}
1287
1288/**
1289 * Used by acpiR3PmTimer to re-arm the PM timer.
1290 *
1291 * The caller is expected to either hold the clock lock or to have made sure
1292 * the VM is resetting or loading state.
1293 *
1294 * @param pDevIns The device instance.
1295 * @param pThis The ACPI shared instance data.
1296 * @param uNow The current time.
1297 */
1298static void acpiR3PmTimerReset(PPDMDEVINS pDevIns, PACPISTATE pThis, uint64_t uNow)
1299{
1300 uint64_t uTimerFreq = PDMDevHlpTimerGetFreq(pDevIns, pThis->hPmTimer);
1301 uint32_t uPmTmrCyclesToRollover = TMR_VAL_MSB - (pThis->uPmTimerVal & (TMR_VAL_MSB - 1));
1302 uint64_t uInterval = ASMMultU64ByU32DivByU32(uPmTmrCyclesToRollover, uTimerFreq, PM_TMR_FREQ);
1303 PDMDevHlpTimerSet(pDevIns, pThis->hPmTimer, uNow + uInterval + 1);
1304 Log(("acpi: uInterval = %RU64\n", uInterval));
1305}
1306
1307#endif /* IN_RING3 */
1308
1309/**
1310 * Used by acpiR3PMTimer & acpiPmTmrRead to update TMR_VAL and update TMR_STS
1311 *
1312 * The caller is expected to either hold the clock lock or to have made sure
1313 * the VM is resetting or loading state.
1314 *
1315 * @param pDevIns The PDM device instance.
1316 * @param pThis The ACPI instance
1317 * @param u64Now The current time
1318 */
1319static void acpiPmTimerUpdate(PPDMDEVINS pDevIns, PACPISTATE pThis, uint64_t u64Now)
1320{
1321 uint32_t msb = pThis->uPmTimerVal & TMR_VAL_MSB;
1322 uint64_t u64Elapsed = u64Now - pThis->u64PmTimerInitial;
1323 Assert(PDMDevHlpTimerIsLockOwner(pDevIns, pThis->hPmTimer));
1324
1325 pThis->uPmTimerVal = ASMMultU64ByU32DivByU32(u64Elapsed, PM_TMR_FREQ, PDMDevHlpTimerGetFreq(pDevIns, pThis->hPmTimer))
1326 & TMR_VAL_MASK;
1327
1328 if ((pThis->uPmTimerVal & TMR_VAL_MSB) != msb)
1329 acpiUpdatePm1a(pDevIns, pThis, pThis->pm1a_sts | TMR_STS, pThis->pm1a_en);
1330}
1331
1332#ifdef IN_RING3
1333
1334/**
1335 * @callback_method_impl{FNTMTIMERDEV, PM Timer callback}
1336 */
1337static DECLCALLBACK(void) acpiR3PmTimer(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, void *pvUser)
1338{
1339 PACPISTATE pThis = PDMDEVINS_2_DATA(pDevIns, PACPISTATE);
1340 Assert(pThis->hPmTimer == hTimer);
1341 Assert(PDMDevHlpTimerIsLockOwner(pDevIns, hTimer));
1342 RT_NOREF(pvUser);
1343
1344 DEVACPI_LOCK_R3(pDevIns, pThis);
1345 Log(("acpi: pm timer sts %#x (%d), en %#x (%d)\n",
1346 pThis->pm1a_sts, (pThis->pm1a_sts & TMR_STS) != 0,
1347 pThis->pm1a_en, (pThis->pm1a_en & TMR_EN) != 0));
1348 uint64_t tsNow = PDMDevHlpTimerGet(pDevIns, hTimer);
1349 acpiPmTimerUpdate(pDevIns, pThis, tsNow);
1350 DEVACPI_UNLOCK(pDevIns, pThis);
1351
1352 acpiR3PmTimerReset(pDevIns, pThis, tsNow);
1353}
1354
1355/**
1356 * _BST method - used by acpiR3BatDataRead to implement BAT_STATUS_STATE and
1357 * acpiR3LoadState.
1358 *
1359 * @returns VINF_SUCCESS.
1360 * @param pThis The ACPI shared instance data.
1361 * @param pThisCC The ACPI instance data for ring-3.
1362 */
1363static int acpiR3FetchBatteryStatus(PACPISTATE pThis, PACPISTATER3 pThisCC)
1364{
1365 uint32_t *p = pThis->au8BatteryInfo;
1366 bool fPresent; /* battery present? */
1367 PDMACPIBATCAPACITY hostRemainingCapacity; /* 0..100 */
1368 PDMACPIBATSTATE hostBatteryState; /* bitfield */
1369 uint32_t hostPresentRate; /* 0..1000 */
1370 int rc;
1371
1372 if (!pThisCC->pDrv)
1373 return VINF_SUCCESS;
1374 rc = pThisCC->pDrv->pfnQueryBatteryStatus(pThisCC->pDrv, &fPresent, &hostRemainingCapacity,
1375 &hostBatteryState, &hostPresentRate);
1376 AssertRC(rc);
1377
1378 /* default values */
1379 p[BAT_STATUS_STATE] = hostBatteryState;
1380 p[BAT_STATUS_PRESENT_RATE] = hostPresentRate == ~0U ? 0xFFFFFFFF
1381 : hostPresentRate * 50; /* mW */
1382 p[BAT_STATUS_REMAINING_CAPACITY] = 50000; /* mWh */
1383 p[BAT_STATUS_PRESENT_VOLTAGE] = 10000; /* mV */
1384
1385 /* did we get a valid battery state? */
1386 if (hostRemainingCapacity != PDM_ACPI_BAT_CAPACITY_UNKNOWN)
1387 p[BAT_STATUS_REMAINING_CAPACITY] = hostRemainingCapacity * 500; /* mWh */
1388 if (hostBatteryState == PDM_ACPI_BAT_STATE_CHARGED)
1389 p[BAT_STATUS_PRESENT_RATE] = 0; /* mV */
1390
1391 return VINF_SUCCESS;
1392}
1393
1394/**
1395 * _BIF method - used by acpiR3BatDataRead to implement BAT_INFO_UNITS and
1396 * acpiR3LoadState.
1397 *
1398 * @returns VINF_SUCCESS.
1399 * @param pThis The ACPI shared instance data.
1400 */
1401static int acpiR3FetchBatteryInfo(PACPISTATE pThis)
1402{
1403 uint32_t *p = pThis->au8BatteryInfo;
1404
1405 p[BAT_INFO_UNITS] = 0; /* mWh */
1406 p[BAT_INFO_DESIGN_CAPACITY] = 50000; /* mWh */
1407 p[BAT_INFO_LAST_FULL_CHARGE_CAPACITY] = 50000; /* mWh */
1408 p[BAT_INFO_TECHNOLOGY] = BAT_TECH_PRIMARY;
1409 p[BAT_INFO_DESIGN_VOLTAGE] = 10000; /* mV */
1410 p[BAT_INFO_DESIGN_CAPACITY_OF_WARNING] = 100; /* mWh */
1411 p[BAT_INFO_DESIGN_CAPACITY_OF_LOW] = 50; /* mWh */
1412 p[BAT_INFO_CAPACITY_GRANULARITY_1] = 1; /* mWh */
1413 p[BAT_INFO_CAPACITY_GRANULARITY_2] = 1; /* mWh */
1414
1415 return VINF_SUCCESS;
1416}
1417
1418/**
1419 * The _STA method - used by acpiR3BatDataRead to implement BAT_DEVICE_STATUS.
1420 *
1421 * @returns status mask or 0.
1422 * @param pThisCC The ACPI instance data for ring-3.
1423 */
1424static uint32_t acpiR3GetBatteryDeviceStatus(PACPISTATER3 pThisCC)
1425{
1426 bool fPresent; /* battery present? */
1427 PDMACPIBATCAPACITY hostRemainingCapacity; /* 0..100 */
1428 PDMACPIBATSTATE hostBatteryState; /* bitfield */
1429 uint32_t hostPresentRate; /* 0..1000 */
1430 int rc;
1431
1432 if (!pThisCC->pDrv)
1433 return 0;
1434 rc = pThisCC->pDrv->pfnQueryBatteryStatus(pThisCC->pDrv, &fPresent, &hostRemainingCapacity,
1435 &hostBatteryState, &hostPresentRate);
1436 AssertRC(rc);
1437
1438 return fPresent
1439 ? STA_DEVICE_PRESENT_MASK /* present */
1440 | STA_DEVICE_ENABLED_MASK /* enabled and decodes its resources */
1441 | STA_DEVICE_SHOW_IN_UI_MASK /* should be shown in UI */
1442 | STA_DEVICE_FUNCTIONING_PROPERLY_MASK /* functioning properly */
1443 | STA_BATTERY_PRESENT_MASK /* battery is present */
1444 : 0; /* device not present */
1445}
1446
1447/**
1448 * Used by acpiR3BatDataRead to implement BAT_POWER_SOURCE.
1449 *
1450 * @returns status.
1451 * @param pThisCC The ACPI instance data for ring-3.
1452 */
1453static uint32_t acpiR3GetPowerSource(PACPISTATER3 pThisCC)
1454{
1455 /* query the current power source from the host driver */
1456 if (!pThisCC->pDrv)
1457 return AC_ONLINE;
1458
1459 PDMACPIPOWERSOURCE ps;
1460 int rc = pThisCC->pDrv->pfnQueryPowerSource(pThisCC->pDrv, &ps);
1461 AssertRC(rc);
1462 return ps == PDM_ACPI_POWER_SOURCE_BATTERY ? AC_OFFLINE : AC_ONLINE;
1463}
1464
1465/**
1466 * @callback_method_impl{FNIOMIOPORTNEWOUT, Battery status index}
1467 */
1468static DECLCALLBACK(VBOXSTRICTRC) acpiR3BatIndexWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT offPort, uint32_t u32, unsigned cb)
1469{
1470 RT_NOREF(pvUser, offPort);
1471 Log(("acpiR3BatIndexWrite: %#x (%#x)\n", u32, u32 >> 2));
1472 if (cb != 4)
1473 return PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "cb=%d offPort=%u u32=%#x\n", cb, offPort, u32);
1474
1475 PACPISTATE pThis = PDMDEVINS_2_DATA(pDevIns, PACPISTATE);
1476 DEVACPI_LOCK_R3(pDevIns, pThis);
1477
1478 u32 >>= pThis->u8IndexShift;
1479 /* see comment at the declaration of u8IndexShift */
1480 if (pThis->u8IndexShift == 0 && u32 == (BAT_DEVICE_STATUS << 2))
1481 {
1482 pThis->u8IndexShift = 2;
1483 u32 >>= 2;
1484 }
1485 ASSERT_GUEST_MSG(u32 < BAT_INDEX_LAST, ("%#x\n", u32));
1486 pThis->uBatteryIndex = u32;
1487
1488 DEVACPI_UNLOCK(pDevIns, pThis);
1489 return VINF_SUCCESS;
1490}
1491
1492/**
1493 * @callback_method_impl{FNIOMIOPORTNEWIN, Battery status data}
1494 */
1495static DECLCALLBACK(VBOXSTRICTRC) acpiR3BatDataRead(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT offPort, uint32_t *pu32, unsigned cb)
1496{
1497 RT_NOREF(pvUser, offPort);
1498 if (cb != 4)
1499 return VERR_IOM_IOPORT_UNUSED;
1500
1501 PACPISTATE pThis = PDMDEVINS_2_DATA(pDevIns, PACPISTATE);
1502 PACPISTATER3 pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PACPISTATER3);
1503 DEVACPI_LOCK_R3(pDevIns, pThis);
1504
1505 VBOXSTRICTRC rc = VINF_SUCCESS;
1506 switch (pThis->uBatteryIndex)
1507 {
1508 case BAT_STATUS_STATE:
1509 acpiR3FetchBatteryStatus(pThis, pThisCC);
1510 RT_FALL_THRU();
1511 case BAT_STATUS_PRESENT_RATE:
1512 case BAT_STATUS_REMAINING_CAPACITY:
1513 case BAT_STATUS_PRESENT_VOLTAGE:
1514 *pu32 = pThis->au8BatteryInfo[pThis->uBatteryIndex];
1515 break;
1516
1517 case BAT_INFO_UNITS:
1518 acpiR3FetchBatteryInfo(pThis);
1519 RT_FALL_THRU();
1520 case BAT_INFO_DESIGN_CAPACITY:
1521 case BAT_INFO_LAST_FULL_CHARGE_CAPACITY:
1522 case BAT_INFO_TECHNOLOGY:
1523 case BAT_INFO_DESIGN_VOLTAGE:
1524 case BAT_INFO_DESIGN_CAPACITY_OF_WARNING:
1525 case BAT_INFO_DESIGN_CAPACITY_OF_LOW:
1526 case BAT_INFO_CAPACITY_GRANULARITY_1:
1527 case BAT_INFO_CAPACITY_GRANULARITY_2:
1528 *pu32 = pThis->au8BatteryInfo[pThis->uBatteryIndex];
1529 break;
1530
1531 case BAT_DEVICE_STATUS:
1532 *pu32 = acpiR3GetBatteryDeviceStatus(pThisCC);
1533 break;
1534
1535 case BAT_POWER_SOURCE:
1536 *pu32 = acpiR3GetPowerSource(pThisCC);
1537 break;
1538
1539 default:
1540 rc = PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "cb=%d offPort=%u idx=%u\n", cb, offPort, pThis->uBatteryIndex);
1541 *pu32 = UINT32_MAX;
1542 break;
1543 }
1544
1545 DEVACPI_UNLOCK(pDevIns, pThis);
1546 return rc;
1547}
1548
1549/**
1550 * @callback_method_impl{FNIOMIOPORTNEWOUT, System info index}
1551 */
1552static DECLCALLBACK(VBOXSTRICTRC) acpiR3SysInfoIndexWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT offPort, uint32_t u32, unsigned cb)
1553{
1554 RT_NOREF(pvUser, offPort);
1555 Log(("acpiR3SysInfoIndexWrite: %#x (%#x)\n", u32, u32 >> 2));
1556 if (cb != 4)
1557 return PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "cb=%d offPort=%u u32=%#x\n", cb, offPort, u32);
1558
1559 PACPISTATE pThis = PDMDEVINS_2_DATA(pDevIns, PACPISTATE);
1560 DEVACPI_LOCK_R3(pDevIns, pThis);
1561
1562 if (u32 == SYSTEM_INFO_INDEX_VALID || u32 == SYSTEM_INFO_INDEX_INVALID)
1563 pThis->uSystemInfoIndex = u32;
1564 else
1565 {
1566 /* see comment at the declaration of u8IndexShift */
1567 if (u32 > SYSTEM_INFO_INDEX_END && pThis->u8IndexShift == 0)
1568 {
1569 if ((u32 >> 2) < SYSTEM_INFO_INDEX_END && (u32 & 0x3) == 0)
1570 pThis->u8IndexShift = 2;
1571 }
1572
1573 u32 >>= pThis->u8IndexShift;
1574
1575 /* If the index exceeds 31 (which is all we can fit within offset 0x80), we need to divide the index again
1576 for indices > 31 and < SYSTEM_INFO_INDEX_END. */
1577 if (u32 > SYSTEM_INFO_INDEX_END && pThis->u8IndexShift == 2 && (u32 >> 2) < SYSTEM_INFO_INDEX_END)
1578 u32 >>= 2;
1579
1580 ASSERT_GUEST_MSG(u32 < SYSTEM_INFO_INDEX_END, ("%u - Max=%u. IndexShift=%u\n", u32, SYSTEM_INFO_INDEX_END, pThis->u8IndexShift));
1581 pThis->uSystemInfoIndex = u32;
1582 }
1583
1584 DEVACPI_UNLOCK(pDevIns, pThis);
1585 return VINF_SUCCESS;
1586}
1587
1588/**
1589 * @callback_method_impl{FNIOMIOPORTNEWIN, System info data}
1590 */
1591static DECLCALLBACK(VBOXSTRICTRC) acpiR3SysInfoDataRead(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT offPort, uint32_t *pu32, unsigned cb)
1592{
1593 RT_NOREF(pvUser, offPort);
1594 if (cb != 4)
1595 return VERR_IOM_IOPORT_UNUSED;
1596
1597 PACPISTATE pThis = PDMDEVINS_2_DATA(pDevIns, PACPISTATE);
1598 DEVACPI_LOCK_R3(pDevIns, pThis);
1599
1600 VBOXSTRICTRC rc = VINF_SUCCESS;
1601 uint32_t const uSystemInfoIndex = pThis->uSystemInfoIndex;
1602 switch (uSystemInfoIndex)
1603 {
1604 case SYSTEM_INFO_INDEX_LOW_MEMORY_LENGTH:
1605 *pu32 = pThis->cbRamLow;
1606 break;
1607
1608 case SYSTEM_INFO_INDEX_PREF64_MEMORY_MIN:
1609 *pu32 = pThis->u64PciPref64Min >> 16; /* 64KB units */
1610 Assert(((uint64_t)*pu32 << 16) == pThis->u64PciPref64Min);
1611 break;
1612
1613 case SYSTEM_INFO_INDEX_PREF64_MEMORY_MAX:
1614 *pu32 = pThis->u64PciPref64Max >> 16; /* 64KB units */
1615 Assert(((uint64_t)*pu32 << 16) == pThis->u64PciPref64Max);
1616 break;
1617
1618 case SYSTEM_INFO_INDEX_USE_IOAPIC:
1619 *pu32 = pThis->u8UseIOApic;
1620 break;
1621
1622 case SYSTEM_INFO_INDEX_HPET_STATUS:
1623 *pu32 = pThis->fUseHpet
1624 ? ( STA_DEVICE_PRESENT_MASK
1625 | STA_DEVICE_ENABLED_MASK
1626 | STA_DEVICE_SHOW_IN_UI_MASK
1627 | STA_DEVICE_FUNCTIONING_PROPERLY_MASK)
1628 : 0;
1629 break;
1630
1631 case SYSTEM_INFO_INDEX_SMC_STATUS:
1632 *pu32 = pThis->fUseSmc
1633 ? ( STA_DEVICE_PRESENT_MASK
1634 | STA_DEVICE_ENABLED_MASK
1635 /* no need to show this device in the UI */
1636 | STA_DEVICE_FUNCTIONING_PROPERLY_MASK)
1637 : 0;
1638 break;
1639
1640 case SYSTEM_INFO_INDEX_FDC_STATUS:
1641 *pu32 = pThis->fUseFdc
1642 ? ( STA_DEVICE_PRESENT_MASK
1643 | STA_DEVICE_ENABLED_MASK
1644 | STA_DEVICE_SHOW_IN_UI_MASK
1645 | STA_DEVICE_FUNCTIONING_PROPERLY_MASK)
1646 : 0;
1647 break;
1648
1649 case SYSTEM_INFO_INDEX_NIC_ADDRESS:
1650 *pu32 = pThis->u32NicPciAddress;
1651 break;
1652
1653 case SYSTEM_INFO_INDEX_AUDIO_ADDRESS:
1654 *pu32 = pThis->u32AudioPciAddress;
1655 break;
1656
1657 case SYSTEM_INFO_INDEX_NVME_ADDRESS:
1658 *pu32 = pThis->u32NvmePciAddress;
1659 break;
1660
1661 case SYSTEM_INFO_INDEX_POWER_STATES:
1662 *pu32 = RT_BIT(0) | RT_BIT(5); /* S1 and S5 always exposed */
1663 if (pThis->fS1Enabled) /* Optionally expose S1 and S4 */
1664 *pu32 |= RT_BIT(1);
1665 if (pThis->fS4Enabled)
1666 *pu32 |= RT_BIT(4);
1667 break;
1668
1669 case SYSTEM_INFO_INDEX_IOC_ADDRESS:
1670 *pu32 = pThis->u32IocPciAddress;
1671 break;
1672
1673 case SYSTEM_INFO_INDEX_HBC_ADDRESS:
1674 *pu32 = pThis->u32HbcPciAddress;
1675 break;
1676
1677 case SYSTEM_INFO_INDEX_PCI_BASE:
1678 /** @todo couldn't MCFG be in 64-bit range? */
1679 Assert(pThis->u64PciConfigMMioAddress < 0xffffffff);
1680 *pu32 = (uint32_t)pThis->u64PciConfigMMioAddress;
1681 break;
1682
1683 case SYSTEM_INFO_INDEX_PCI_LENGTH:
1684 /** @todo couldn't MCFG be in 64-bit range? */
1685 Assert(pThis->u64PciConfigMMioLength < 0xffffffff);
1686 *pu32 = (uint32_t)pThis->u64PciConfigMMioLength;
1687 break;
1688
1689 case SYSTEM_INFO_INDEX_RTC_STATUS:
1690 *pu32 = pThis->fShowRtc
1691 ? ( STA_DEVICE_PRESENT_MASK
1692 | STA_DEVICE_ENABLED_MASK
1693 | STA_DEVICE_SHOW_IN_UI_MASK
1694 | STA_DEVICE_FUNCTIONING_PROPERLY_MASK)
1695 : 0;
1696 break;
1697
1698 case SYSTEM_INFO_INDEX_CPU_LOCKED:
1699 if (pThis->idCpuLockCheck < VMM_MAX_CPU_COUNT)
1700 {
1701 *pu32 = VMCPUSET_IS_PRESENT(&pThis->CpuSetLocked, pThis->idCpuLockCheck);
1702 pThis->idCpuLockCheck = UINT32_C(0xffffffff); /* Make the entry invalid */
1703 }
1704 else
1705 {
1706 rc = PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "CPU lock check protocol violation (idCpuLockCheck=%#x)\n",
1707 pThis->idCpuLockCheck);
1708 /* Always return locked status just to be safe */
1709 *pu32 = 1;
1710 }
1711 break;
1712
1713 case SYSTEM_INFO_INDEX_CPU_EVENT_TYPE:
1714 *pu32 = pThis->u32CpuEventType;
1715 break;
1716
1717 case SYSTEM_INFO_INDEX_CPU_EVENT:
1718 *pu32 = pThis->u32CpuEvent;
1719 break;
1720
1721 case SYSTEM_INFO_INDEX_SERIAL0_IOBASE:
1722 *pu32 = pThis->uSerial0IoPortBase;
1723 break;
1724
1725 case SYSTEM_INFO_INDEX_SERIAL0_IRQ:
1726 *pu32 = pThis->uSerial0Irq;
1727 break;
1728
1729 case SYSTEM_INFO_INDEX_SERIAL1_IOBASE:
1730 *pu32 = pThis->uSerial1IoPortBase;
1731 break;
1732
1733 case SYSTEM_INFO_INDEX_SERIAL1_IRQ:
1734 *pu32 = pThis->uSerial1Irq;
1735 break;
1736
1737 case SYSTEM_INFO_INDEX_SERIAL2_IOBASE:
1738 *pu32 = pThis->uSerial2IoPortBase;
1739 break;
1740
1741 case SYSTEM_INFO_INDEX_SERIAL2_IRQ:
1742 *pu32 = pThis->uSerial2Irq;
1743 break;
1744
1745 case SYSTEM_INFO_INDEX_SERIAL3_IOBASE:
1746 *pu32 = pThis->uSerial3IoPortBase;
1747 break;
1748
1749 case SYSTEM_INFO_INDEX_SERIAL3_IRQ:
1750 *pu32 = pThis->uSerial3Irq;
1751 break;
1752
1753 case SYSTEM_INFO_INDEX_PARALLEL0_IOBASE:
1754 *pu32 = pThis->uParallel0IoPortBase;
1755 break;
1756
1757 case SYSTEM_INFO_INDEX_PARALLEL0_IRQ:
1758 *pu32 = pThis->uParallel0Irq;
1759 break;
1760
1761 case SYSTEM_INFO_INDEX_PARALLEL1_IOBASE:
1762 *pu32 = pThis->uParallel1IoPortBase;
1763 break;
1764
1765 case SYSTEM_INFO_INDEX_PARALLEL1_IRQ:
1766 *pu32 = pThis->uParallel1Irq;
1767 break;
1768
1769 case SYSTEM_INFO_INDEX_IOMMU_ADDRESS:
1770 *pu32 = pThis->u32IommuPciAddress;
1771 break;
1772
1773 case SYSTEM_INFO_INDEX_SB_IOAPIC_ADDRESS:
1774 *pu32 = pThis->u32SbIoApicPciAddress;
1775 break;
1776
1777 case SYSTEM_INFO_INDEX_END:
1778 /** @todo why isn't this setting any output value? */
1779 break;
1780
1781 /* Solaris 9 tries to read from this index */
1782 case SYSTEM_INFO_INDEX_INVALID:
1783 *pu32 = 0;
1784 break;
1785
1786 default:
1787 *pu32 = UINT32_MAX;
1788 rc = PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "cb=%d offPort=%u idx=%u\n", cb, offPort, uSystemInfoIndex);
1789 break;
1790 }
1791
1792 DEVACPI_UNLOCK(pDevIns, pThis);
1793 Log(("acpiR3SysInfoDataRead: idx=%d val=%#x (%u) rc=%Rrc\n", uSystemInfoIndex, *pu32, *pu32, VBOXSTRICTRC_VAL(rc)));
1794 return rc;
1795}
1796
1797/**
1798 * @callback_method_impl{FNIOMIOPORTNEWOUT, System info data}
1799 */
1800static DECLCALLBACK(VBOXSTRICTRC) acpiR3SysInfoDataWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT offPort, uint32_t u32, unsigned cb)
1801{
1802 RT_NOREF(pvUser, offPort);
1803 PACPISTATE pThis = PDMDEVINS_2_DATA(pDevIns, PACPISTATE);
1804 if (cb != 4)
1805 return PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "cb=%d offPort=%u u32=%#x idx=%u\n", cb, offPort, u32, pThis->uSystemInfoIndex);
1806
1807 DEVACPI_LOCK_R3(pDevIns, pThis);
1808 Log(("addr=%#x cb=%d u32=%#x si=%#x\n", offPort, cb, u32, pThis->uSystemInfoIndex));
1809
1810 VBOXSTRICTRC rc = VINF_SUCCESS;
1811 switch (pThis->uSystemInfoIndex)
1812 {
1813 case SYSTEM_INFO_INDEX_INVALID:
1814 AssertMsg(u32 == 0xbadc0de, ("u32=%u\n", u32));
1815 pThis->u8IndexShift = 0;
1816 break;
1817
1818 case SYSTEM_INFO_INDEX_VALID:
1819 AssertMsg(u32 == 0xbadc0de, ("u32=%u\n", u32));
1820 pThis->u8IndexShift = 2;
1821 break;
1822
1823 case SYSTEM_INFO_INDEX_CPU_LOCK_CHECK:
1824 pThis->idCpuLockCheck = u32;
1825 break;
1826
1827 case SYSTEM_INFO_INDEX_CPU_LOCKED:
1828 if (u32 < pThis->cCpus)
1829 VMCPUSET_DEL(&pThis->CpuSetLocked, u32); /* Unlock the CPU */
1830 else
1831 LogRel(("ACPI: CPU %u does not exist\n", u32));
1832 break;
1833
1834 default:
1835 rc = PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "cb=%d offPort=%u u32=%#x idx=%u\n", cb, offPort, u32, pThis->uSystemInfoIndex);
1836 break;
1837 }
1838
1839 DEVACPI_UNLOCK(pDevIns, pThis);
1840 return rc;
1841}
1842
1843/**
1844 * @callback_method_impl{FNIOMIOPORTNEWIN, PM1a Enable}
1845 */
1846static DECLCALLBACK(VBOXSTRICTRC) acpiR3Pm1aEnRead(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT offPort, uint32_t *pu32, unsigned cb)
1847{
1848 RT_NOREF(offPort, pvUser);
1849 if (cb != 2)
1850 return VERR_IOM_IOPORT_UNUSED;
1851
1852 PACPISTATE pThis = PDMDEVINS_2_DATA(pDevIns, PACPISTATE);
1853 DEVACPI_LOCK_R3(pDevIns, pThis);
1854
1855 *pu32 = pThis->pm1a_en;
1856
1857 DEVACPI_UNLOCK(pDevIns, pThis);
1858 Log(("acpiR3Pm1aEnRead -> %#x\n", *pu32));
1859 return VINF_SUCCESS;
1860}
1861
1862/**
1863 * @callback_method_impl{FNIOMIOPORTNEWOUT, PM1a Enable}
1864 */
1865static DECLCALLBACK(VBOXSTRICTRC) acpiR3PM1aEnWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT offPort, uint32_t u32, unsigned cb)
1866{
1867 RT_NOREF(offPort, pvUser);
1868 if (cb != 2 && cb != 4)
1869 return PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "cb=%d offPort=%u u32=%#x\n", cb, offPort, u32);
1870
1871 PACPISTATE pThis = PDMDEVINS_2_DATA(pDevIns, PACPISTATE);
1872 DEVACPI_LOCK_R3(pDevIns, pThis);
1873
1874 Log(("acpiR3PM1aEnWrite: %#x (%#x)\n", u32, u32 & ~(RSR_EN | IGN_EN) & 0xffff));
1875 u32 &= ~(RSR_EN | IGN_EN);
1876 u32 &= 0xffff;
1877 acpiUpdatePm1a(pDevIns, pThis, pThis->pm1a_sts, u32);
1878
1879 DEVACPI_UNLOCK(pDevIns, pThis);
1880 return VINF_SUCCESS;
1881}
1882
1883/**
1884 * @callback_method_impl{FNIOMIOPORTNEWIN, PM1a Status}
1885 */
1886static DECLCALLBACK(VBOXSTRICTRC) acpiR3Pm1aStsRead(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT offPort, uint32_t *pu32, unsigned cb)
1887{
1888 RT_NOREF(offPort, pvUser);
1889 if (cb != 2)
1890 {
1891 int rc = PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "cb=%d offPort=%u\n", cb, offPort);
1892 return rc == VINF_SUCCESS ? VERR_IOM_IOPORT_UNUSED : rc;
1893 }
1894
1895 PACPISTATE pThis = PDMDEVINS_2_DATA(pDevIns, PACPISTATE);
1896 DEVACPI_LOCK_R3(pDevIns, pThis);
1897
1898 *pu32 = pThis->pm1a_sts;
1899
1900 DEVACPI_UNLOCK(pDevIns, pThis);
1901 Log(("acpiR3Pm1aStsRead: %#x\n", *pu32));
1902 return VINF_SUCCESS;
1903}
1904
1905/**
1906 * @callback_method_impl{FNIOMIOPORTNEWOUT, PM1a Status}
1907 */
1908static DECLCALLBACK(VBOXSTRICTRC) acpiR3PM1aStsWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT offPort, uint32_t u32, unsigned cb)
1909{
1910 RT_NOREF(offPort, pvUser);
1911 if (cb != 2 && cb != 4)
1912 return PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "cb=%d offPort=%u u32=%#x\n", cb, offPort, u32);
1913
1914 PACPISTATE pThis = PDMDEVINS_2_DATA(pDevIns, PACPISTATE);
1915 DEVACPI_LOCK_R3(pDevIns, pThis);
1916
1917 Log(("acpiR3PM1aStsWrite: %#x (%#x)\n", u32, u32 & ~(RSR_STS | IGN_STS) & 0xffff));
1918 u32 &= 0xffff;
1919 if (u32 & PWRBTN_STS)
1920 pThis->fPowerButtonHandled = true; /* Remember that the guest handled the last power button event */
1921 u32 = pThis->pm1a_sts & ~(u32 & ~(RSR_STS | IGN_STS));
1922 acpiUpdatePm1a(pDevIns, pThis, u32, pThis->pm1a_en);
1923
1924 DEVACPI_UNLOCK(pDevIns, pThis);
1925 return VINF_SUCCESS;
1926}
1927
1928/**
1929 * @callback_method_impl{FNIOMIOPORTNEWIN, PM1a Control}
1930 */
1931static DECLCALLBACK(VBOXSTRICTRC) acpiR3Pm1aCtlRead(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT offPort, uint32_t *pu32, unsigned cb)
1932{
1933 RT_NOREF(offPort, pvUser);
1934 if (cb != 2)
1935 {
1936 int rc = PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "cb=%d offPort=%u\n", cb, offPort);
1937 return rc == VINF_SUCCESS ? VERR_IOM_IOPORT_UNUSED : rc;
1938 }
1939
1940 PACPISTATE pThis = PDMDEVINS_2_DATA(pDevIns, PACPISTATE);
1941 DEVACPI_LOCK_R3(pDevIns, pThis);
1942
1943 *pu32 = pThis->pm1a_ctl;
1944
1945 DEVACPI_UNLOCK(pDevIns, pThis);
1946 Log(("acpiR3Pm1aCtlRead: %#x\n", *pu32));
1947 return VINF_SUCCESS;
1948}
1949
1950/**
1951 * @callback_method_impl{FNIOMIOPORTNEWOUT, PM1a Control}
1952 */
1953static DECLCALLBACK(VBOXSTRICTRC) acpiR3PM1aCtlWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT offPort, uint32_t u32, unsigned cb)
1954{
1955 RT_NOREF(offPort, pvUser);
1956 if (cb != 2 && cb != 4)
1957 return PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "cb=%d offPort=%u u32=%#x\n", cb, offPort, u32);
1958
1959 PACPISTATE pThis = PDMDEVINS_2_DATA(pDevIns, PACPISTATE);
1960 DEVACPI_LOCK_R3(pDevIns, pThis);
1961
1962 Log(("acpiR3PM1aCtlWrite: %#x (%#x)\n", u32, u32 & ~(RSR_CNT | IGN_CNT) & 0xffff));
1963 u32 &= 0xffff;
1964 pThis->pm1a_ctl = u32 & ~(RSR_CNT | IGN_CNT);
1965
1966 VBOXSTRICTRC rc = VINF_SUCCESS;
1967 uint32_t const uSleepState = (pThis->pm1a_ctl >> SLP_TYPx_SHIFT) & SLP_TYPx_MASK;
1968 if (uSleepState != pThis->uSleepState)
1969 {
1970 pThis->uSleepState = uSleepState;
1971 switch (uSleepState)
1972 {
1973 case 0x00: /* S0 */
1974 break;
1975
1976 case 0x01: /* S1 */
1977 if (pThis->fS1Enabled)
1978 {
1979 LogRel(("ACPI: Entering S1 power state (powered-on suspend)\n"));
1980 rc = acpiR3DoSleep(pDevIns, pThis);
1981 break;
1982 }
1983 LogRel(("ACPI: Ignoring guest attempt to enter S1 power state (powered-on suspend)!\n"));
1984 RT_FALL_THRU();
1985
1986 case 0x04: /* S4 */
1987 if (pThis->fS4Enabled)
1988 {
1989 LogRel(("ACPI: Entering S4 power state (suspend to disk)\n"));
1990 rc = acpiR3DoPowerOff(pDevIns);/* Same behavior as S5 */
1991 break;
1992 }
1993 LogRel(("ACPI: Ignoring guest attempt to enter S4 power state (suspend to disk)!\n"));
1994 RT_FALL_THRU();
1995
1996 case 0x05: /* S5 */
1997 LogRel(("ACPI: Entering S5 power state (power down)\n"));
1998 rc = acpiR3DoPowerOff(pDevIns);
1999 break;
2000
2001 default:
2002 rc = PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "Unknown sleep state %#x (u32=%#x)\n", uSleepState, u32);
2003 break;
2004 }
2005 }
2006
2007 DEVACPI_UNLOCK(pDevIns, pThis);
2008 Log(("acpiR3PM1aCtlWrite: rc=%Rrc\n", VBOXSTRICTRC_VAL(rc)));
2009 return rc;
2010}
2011
2012#endif /* IN_RING3 */
2013
2014/**
2015 * @callback_method_impl{FNIOMIOPORTNEWIN, PMTMR}
2016 *
2017 * @remarks The only I/O port currently implemented in all contexts.
2018 */
2019static DECLCALLBACK(VBOXSTRICTRC) acpiPMTmrRead(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT offPort, uint32_t *pu32, unsigned cb)
2020{
2021 RT_NOREF(offPort, pvUser);
2022 if (cb != 4)
2023 return VERR_IOM_IOPORT_UNUSED;
2024
2025 /*
2026 * We use the clock lock to serialize access to u64PmTimerInitial and to
2027 * make sure we get a reliable time from the clock
2028 * as well as and to prevent uPmTimerVal from being updated during read.
2029 */
2030 PACPISTATE pThis = PDMDEVINS_2_DATA(pDevIns, PACPISTATE);
2031 VBOXSTRICTRC rc = PDMDevHlpTimerLockClock2(pDevIns, pThis->hPmTimer, &pThis->CritSect, VINF_IOM_R3_IOPORT_READ);
2032 if (rc == VINF_SUCCESS)
2033 {
2034 uint64_t u64Now = PDMDevHlpTimerGet(pDevIns, pThis->hPmTimer);
2035 acpiPmTimerUpdate(pDevIns, pThis, u64Now);
2036 *pu32 = pThis->uPmTimerVal;
2037
2038 PDMDevHlpTimerUnlockClock2(pDevIns, pThis->hPmTimer, &pThis->CritSect);
2039
2040 DBGFTRACE_PDM_U64_TAG(pDevIns, u64Now, "acpi");
2041 Log(("acpi: acpiPMTmrRead -> %#x\n", *pu32));
2042
2043#if 0
2044 /** @todo temporary: sanity check against running backwards */
2045 uint32_t uOld = ASMAtomicXchgU32(&pThis->uPmTimeOld, *pu32);
2046 if (*pu32 - uOld >= 0x10000000)
2047 {
2048# if defined(IN_RING0)
2049 pThis->uPmTimeA = uOld;
2050 pThis->uPmTimeB = *pu32;
2051 return VERR_TM_TIMER_BAD_CLOCK;
2052# elif defined(IN_RING3)
2053 AssertReleaseMsgFailed(("acpiPMTmrRead: old=%08RX32, current=%08RX32\n", uOld, *pu32));
2054# endif
2055 }
2056#endif
2057 }
2058 return rc;
2059}
2060
2061#ifdef IN_RING3
2062
2063/**
2064 * @callback_method_impl{FNIOMIOPORTNEWIN, GPE0 Status}
2065 */
2066static DECLCALLBACK(VBOXSTRICTRC) acpiR3Gpe0StsRead(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT offPort, uint32_t *pu32, unsigned cb)
2067{
2068 RT_NOREF(offPort, pvUser);
2069 if (cb != 1)
2070 {
2071 int rc = PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "cb=%d offPort=%u\n", cb, offPort);
2072 return rc == VINF_SUCCESS ? VERR_IOM_IOPORT_UNUSED : rc;
2073 }
2074
2075 PACPISTATE pThis = PDMDEVINS_2_DATA(pDevIns, PACPISTATE);
2076 DEVACPI_LOCK_R3(pDevIns, pThis);
2077
2078 *pu32 = pThis->gpe0_sts & 0xff;
2079
2080 DEVACPI_UNLOCK(pDevIns, pThis);
2081 Log(("acpiR3Gpe0StsRead: %#x\n", *pu32));
2082 return VINF_SUCCESS;
2083}
2084
2085/**
2086 * @callback_method_impl{FNIOMIOPORTNEWOUT, GPE0 Status}
2087 */
2088static DECLCALLBACK(VBOXSTRICTRC) acpiR3Gpe0StsWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT offPort, uint32_t u32, unsigned cb)
2089{
2090 RT_NOREF(offPort, pvUser);
2091 if (cb != 1)
2092 return PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "cb=%d offPort=%u u32=%#x\n", cb, offPort, u32);
2093
2094 PACPISTATE pThis = PDMDEVINS_2_DATA(pDevIns, PACPISTATE);
2095 DEVACPI_LOCK_R3(pDevIns, pThis);
2096
2097 Log(("acpiR3Gpe0StsWrite: %#x (%#x)\n", u32, pThis->gpe0_sts & ~u32));
2098 u32 = pThis->gpe0_sts & ~u32;
2099 apicR3UpdateGpe0(pDevIns, pThis, u32, pThis->gpe0_en);
2100
2101 DEVACPI_UNLOCK(pDevIns, pThis);
2102 return VINF_SUCCESS;
2103}
2104
2105/**
2106 * @callback_method_impl{FNIOMIOPORTNEWIN, GPE0 Enable}
2107 */
2108static DECLCALLBACK(VBOXSTRICTRC) acpiR3Gpe0EnRead(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT offPort, uint32_t *pu32, unsigned cb)
2109{
2110 RT_NOREF(offPort, pvUser);
2111 if (cb != 1)
2112 {
2113 int rc = PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "cb=%d offPort=%u\n", cb, offPort);
2114 return rc == VINF_SUCCESS ? VERR_IOM_IOPORT_UNUSED : rc;
2115 }
2116
2117 PACPISTATE pThis = PDMDEVINS_2_DATA(pDevIns, PACPISTATE);
2118 DEVACPI_LOCK_R3(pDevIns, pThis);
2119
2120 *pu32 = pThis->gpe0_en & 0xff;
2121
2122 DEVACPI_UNLOCK(pDevIns, pThis);
2123 Log(("acpiR3Gpe0EnRead: %#x\n", *pu32));
2124 return VINF_SUCCESS;
2125}
2126
2127/**
2128 * @callback_method_impl{FNIOMIOPORTNEWOUT, GPE0 Enable}
2129 */
2130static DECLCALLBACK(VBOXSTRICTRC) acpiR3Gpe0EnWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT offPort, uint32_t u32, unsigned cb)
2131{
2132 RT_NOREF(offPort, pvUser);
2133 if (cb != 1)
2134 return PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "cb=%d offPort=%u u32=%#x\n", cb, offPort, u32);
2135
2136 PACPISTATE pThis = PDMDEVINS_2_DATA(pDevIns, PACPISTATE);
2137 DEVACPI_LOCK_R3(pDevIns, pThis);
2138
2139 Log(("acpiR3Gpe0EnWrite: %#x\n", u32));
2140 apicR3UpdateGpe0(pDevIns, pThis, pThis->gpe0_sts, u32);
2141
2142 DEVACPI_UNLOCK(pDevIns, pThis);
2143 return VINF_SUCCESS;
2144}
2145
2146/**
2147 * @callback_method_impl{FNIOMIOPORTNEWOUT, SMI_CMD}
2148 */
2149static DECLCALLBACK(VBOXSTRICTRC) acpiR3SmiWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT offPort, uint32_t u32, unsigned cb)
2150{
2151 RT_NOREF(offPort, pvUser);
2152 Log(("acpiR3SmiWrite %#x\n", u32));
2153 if (cb != 1)
2154 return PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "cb=%d offPort=%u u32=%#x\n", cb, offPort, u32);
2155
2156 PACPISTATE pThis = PDMDEVINS_2_DATA(pDevIns, PACPISTATE);
2157 DEVACPI_LOCK_R3(pDevIns, pThis);
2158
2159 if (u32 == ACPI_ENABLE)
2160 pThis->pm1a_ctl |= SCI_EN;
2161 else if (u32 == ACPI_DISABLE)
2162 pThis->pm1a_ctl &= ~SCI_EN;
2163 else
2164 Log(("acpiR3SmiWrite: %#x <- unknown value\n", u32));
2165
2166 DEVACPI_UNLOCK(pDevIns, pThis);
2167 return VINF_SUCCESS;
2168}
2169
2170/**
2171 * @callback_method_impl{FNIOMIOPORTNEWOUT, ACPI_RESET_BLK}
2172 */
2173static DECLCALLBACK(VBOXSTRICTRC) acpiR3ResetWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT offPort, uint32_t u32, unsigned cb)
2174{
2175 RT_NOREF(offPort, pvUser);
2176 Log(("acpiR3ResetWrite: %#x\n", u32));
2177 NOREF(pvUser);
2178 if (cb != 1)
2179 return PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "cb=%d offPort=%u u32=%#x\n", cb, offPort, u32);
2180
2181 /* No state locking required. */
2182 VBOXSTRICTRC rc;
2183 if (u32 == ACPI_RESET_REG_VAL)
2184 {
2185 LogRel(("ACPI: Reset initiated by ACPI\n"));
2186 rc = PDMDevHlpVMReset(pDevIns, PDMVMRESET_F_ACPI);
2187 }
2188 else
2189 {
2190 Log(("acpiR3ResetWrite: %#x <- unknown value\n", u32));
2191 rc = VINF_SUCCESS;
2192 }
2193
2194 return rc;
2195}
2196
2197# ifdef DEBUG_ACPI
2198
2199/**
2200 * @callback_method_impl{FNIOMIOPORTNEWOUT, Debug hex value logger}
2201 */
2202static DECLCALLBACK(VBOXSTRICTRC) acpiR3DebugHexWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT offPort, uint32_t u32, unsigned cb)
2203{
2204 NOREF(pvUser);
2205 switch (cb)
2206 {
2207 case 1:
2208 Log(("%#x\n", u32 & 0xff));
2209 break;
2210 case 2:
2211 Log(("%#6x\n", u32 & 0xffff));
2212 break;
2213 case 4:
2214 Log(("%#10x\n", u32));
2215 break;
2216 default:
2217 return PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "cb=%d offPort=%u u32=%#x\n", cb, offPort, u32);
2218 }
2219 return VINF_SUCCESS;
2220}
2221
2222/**
2223 * @callback_method_impl{FNIOMIOPORTNEWOUT, Debug char logger}
2224 */
2225static DECLCALLBACK(VBOXSTRICTRC) acpiR3DebugCharWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT offPort, uint32_t u32, unsigned cb)
2226{
2227 NOREF(pvUser);
2228 switch (cb)
2229 {
2230 case 1:
2231 Log(("%c", u32 & 0xff));
2232 break;
2233 default:
2234 return PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "cb=%d offPort=%u u32=%#x\n", cb, offPort, u32);
2235 }
2236 return VINF_SUCCESS;
2237}
2238
2239# endif /* DEBUG_ACPI */
2240
2241/**
2242 * @callback_method_impl{FNDBGFHANDLERDEV}
2243 */
2244static DECLCALLBACK(void) acpiR3Info(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
2245{
2246 RT_NOREF(pszArgs);
2247 PACPISTATE pThis = PDMDEVINS_2_DATA(pDevIns, PACPISTATE);
2248 pHlp->pfnPrintf(pHlp,
2249 "timer: old=%08RX32, current=%08RX32\n", pThis->uPmTimeA, pThis->uPmTimeB);
2250}
2251
2252/**
2253 * Called by acpiR3Reset and acpiR3Construct to set up the PM PCI config space.
2254 *
2255 * @param pDevIns The PDM device instance.
2256 * @param pThis The ACPI shared instance data.
2257 */
2258static void acpiR3PmPCIBIOSFake(PPDMDEVINS pDevIns, PACPISTATE pThis)
2259{
2260 PPDMPCIDEV pPciDev = pDevIns->apPciDevs[0];
2261 pPciDev->abConfig[PMBA ] = pThis->uPmIoPortBase | 1; /* PMBA, PM base address, bit 0 marks it as IO range */
2262 pPciDev->abConfig[PMBA + 1] = pThis->uPmIoPortBase >> 8;
2263 pPciDev->abConfig[PMBA + 2] = 0x00;
2264 pPciDev->abConfig[PMBA + 3] = 0x00;
2265}
2266
2267/**
2268 * Used to calculate the value of a PM I/O port.
2269 *
2270 * @returns The actual I/O port value.
2271 * @param pThis The ACPI shared instance data.
2272 * @param offset The offset into the I/O space, or -1 if invalid.
2273 */
2274static RTIOPORT acpiR3CalcPmPort(PACPISTATE pThis, int32_t offset)
2275{
2276 Assert(pThis->uPmIoPortBase != 0);
2277
2278 if (offset == -1)
2279 return 0;
2280
2281 return (RTIOPORT)(pThis->uPmIoPortBase + offset);
2282}
2283
2284/**
2285 * Called by acpiR3LoadState and acpiR3UpdatePmHandlers to map the PM1a, PM
2286 * timer and GPE0 I/O ports.
2287 *
2288 * @returns VBox status code.
2289 * @param pDevIns The device instance.
2290 * @param pThis The ACPI shared instance data.
2291 */
2292static int acpiR3MapPmIoPorts(PPDMDEVINS pDevIns, PACPISTATE pThis)
2293{
2294 if (pThis->uPmIoPortBase == 0)
2295 return VINF_SUCCESS;
2296
2297 int rc;
2298 rc = PDMDevHlpIoPortMap(pDevIns, pThis->hIoPortPm1aSts, acpiR3CalcPmPort(pThis, PM1a_EVT_OFFSET));
2299 AssertRCReturn(rc, rc);
2300 rc = PDMDevHlpIoPortMap(pDevIns, pThis->hIoPortPm1aEn, acpiR3CalcPmPort(pThis, PM1a_EVT_OFFSET + 2));
2301 AssertRCReturn(rc, rc);
2302 rc = PDMDevHlpIoPortMap(pDevIns, pThis->hIoPortPm1aCtl, acpiR3CalcPmPort(pThis, PM1a_CTL_OFFSET));
2303 AssertRCReturn(rc, rc);
2304 rc = PDMDevHlpIoPortMap(pDevIns, pThis->hIoPortPmTimer, acpiR3CalcPmPort(pThis, PM_TMR_OFFSET));
2305 AssertRCReturn(rc, rc);
2306 rc = PDMDevHlpIoPortMap(pDevIns, pThis->hIoPortGpe0Sts, acpiR3CalcPmPort(pThis, GPE0_OFFSET));
2307 AssertRCReturn(rc, rc);
2308 rc = PDMDevHlpIoPortMap(pDevIns, pThis->hIoPortGpe0En, acpiR3CalcPmPort(pThis, GPE0_OFFSET + GPE0_BLK_LEN / 2));
2309
2310 return VINF_SUCCESS;
2311}
2312
2313/**
2314 * Called by acpiR3LoadState and acpiR3UpdatePmHandlers to unmap the PM1a, PM
2315 * timer and GPE0 I/O ports.
2316 *
2317 * @returns VBox status code.
2318 * @param pDevIns The device instance.
2319 * @param pThis The ACPI shared instance data.
2320 */
2321static int acpiR3UnmapPmIoPorts(PPDMDEVINS pDevIns, PACPISTATE pThis)
2322{
2323 if (pThis->uPmIoPortBase != 0)
2324 {
2325 int rc;
2326 rc = PDMDevHlpIoPortUnmap(pDevIns, pThis->hIoPortPm1aSts);
2327 AssertRCReturn(rc, rc);
2328 rc = PDMDevHlpIoPortUnmap(pDevIns, pThis->hIoPortPm1aEn);
2329 AssertRCReturn(rc, rc);
2330 rc = PDMDevHlpIoPortUnmap(pDevIns, pThis->hIoPortPm1aCtl);
2331 AssertRCReturn(rc, rc);
2332 rc = PDMDevHlpIoPortUnmap(pDevIns, pThis->hIoPortPmTimer);
2333 AssertRCReturn(rc, rc);
2334 rc = PDMDevHlpIoPortUnmap(pDevIns, pThis->hIoPortGpe0Sts);
2335 AssertRCReturn(rc, rc);
2336 rc = PDMDevHlpIoPortUnmap(pDevIns, pThis->hIoPortGpe0En);
2337 AssertRCReturn(rc, rc);
2338 }
2339 return VINF_SUCCESS;
2340}
2341
2342/**
2343 * Called by acpiR3PciConfigWrite and acpiReset to change the location of the
2344 * PM1a, PM timer and GPE0 ports.
2345 *
2346 * @returns VBox status code.
2347 *
2348 * @param pDevIns The device instance.
2349 * @param pThis The ACPI shared instance data.
2350 * @param pThisCC The ACPI instance data for ring-3.
2351 * @param NewIoPortBase The new base address of the I/O ports.
2352 */
2353static int acpiR3UpdatePmHandlers(PPDMDEVINS pDevIns, PACPISTATE pThis, PACPISTATER3 pThisCC, RTIOPORT NewIoPortBase)
2354{
2355 Log(("acpi: rebasing PM 0x%x -> 0x%x\n", pThis->uPmIoPortBase, NewIoPortBase));
2356 if (NewIoPortBase != pThis->uPmIoPortBase)
2357 {
2358 int rc = acpiR3UnmapPmIoPorts(pDevIns, pThis);
2359 if (RT_FAILURE(rc))
2360 return rc;
2361
2362 pThis->uPmIoPortBase = NewIoPortBase;
2363
2364 rc = acpiR3MapPmIoPorts(pDevIns, pThis);
2365 if (RT_FAILURE(rc))
2366 return rc;
2367
2368 /* We have to update FADT table acccording to the new base */
2369 rc = acpiR3PlantTables(pDevIns, pThis, pThisCC);
2370 AssertRC(rc);
2371 if (RT_FAILURE(rc))
2372 return rc;
2373 }
2374
2375 return VINF_SUCCESS;
2376}
2377
2378/**
2379 * @callback_method_impl{FNIOMIOPORTNEWOUT, SMBus}
2380 */
2381static DECLCALLBACK(VBOXSTRICTRC) acpiR3SMBusWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT offPort, uint32_t u32, unsigned cb)
2382{
2383 RT_NOREF(pvUser);
2384 PACPISTATE pThis = PDMDEVINS_2_DATA(pDevIns, PACPISTATE);
2385
2386 LogFunc(("offPort=%#x u32=%#x cb=%u\n", offPort, u32, cb));
2387 uint8_t off = offPort & 0x000f;
2388 if ( (cb != 1 && off <= SMBSHDWCMD_OFF)
2389 || (cb != 2 && (off == SMBSLVEVT_OFF || off == SMBSLVDAT_OFF)))
2390 return PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "cb=%d offPort=%u u32=%#x\n", cb, offPort, u32);
2391
2392 DEVACPI_LOCK_R3(pDevIns, pThis);
2393 switch (off)
2394 {
2395 case SMBHSTSTS_OFF:
2396 /* Bit 0 is readonly, bits 1..4 are write clear, bits 5..7 are reserved */
2397 pThis->u8SMBusHstSts &= ~(u32 & SMBHSTSTS_INT_MASK);
2398 break;
2399 case SMBSLVSTS_OFF:
2400 /* Bit 0 is readonly, bit 1 is reserved, bits 2..5 are write clear, bits 6..7 are reserved */
2401 pThis->u8SMBusSlvSts &= ~(u32 & SMBSLVSTS_WRITE_MASK);
2402 break;
2403 case SMBHSTCNT_OFF:
2404 {
2405 Assert(PDMDevHlpCritSectIsOwner(pDevIns, &pThis->CritSect));
2406
2407 const bool old_level = acpiSCILevel(pDevIns, pThis);
2408 pThis->u8SMBusHstCnt = u32 & SMBHSTCNT_WRITE_MASK;
2409 if (u32 & SMBHSTCNT_START)
2410 {
2411 /* Start, trigger error as this is a dummy implementation */
2412 pThis->u8SMBusHstSts |= SMBHSTSTS_DEV_ERR | SMBHSTSTS_INTER;
2413 }
2414 if (u32 & SMBHSTCNT_KILL)
2415 {
2416 /* Kill */
2417 pThis->u8SMBusHstSts |= SMBHSTSTS_FAILED | SMBHSTSTS_INTER;
2418 }
2419 const bool new_level = acpiSCILevel(pDevIns, pThis);
2420
2421 LogFunc(("old=%x new=%x\n", old_level, new_level));
2422
2423 /* This handles only SCI/IRQ9. SMI# makes not much sense today and
2424 * needs to be implemented later if it ever becomes relevant. */
2425 if (new_level != old_level)
2426 acpiSetIrq(pDevIns, new_level);
2427 break;
2428 }
2429 case SMBHSTCMD_OFF:
2430 pThis->u8SMBusHstCmd = u32;
2431 break;
2432 case SMBHSTADD_OFF:
2433 pThis->u8SMBusHstAdd = u32;
2434 break;
2435 case SMBHSTDAT0_OFF:
2436 pThis->u8SMBusHstDat0 = u32;
2437 break;
2438 case SMBHSTDAT1_OFF:
2439 pThis->u8SMBusHstDat1 = u32;
2440 break;
2441 case SMBBLKDAT_OFF:
2442 pThis->au8SMBusBlkDat[pThis->u8SMBusBlkIdx] = u32;
2443 pThis->u8SMBusBlkIdx++;
2444 pThis->u8SMBusBlkIdx &= sizeof(pThis->au8SMBusBlkDat) - 1;
2445 break;
2446 case SMBSLVCNT_OFF:
2447 pThis->u8SMBusSlvCnt = u32 & SMBSLVCNT_WRITE_MASK;
2448 break;
2449 case SMBSHDWCMD_OFF:
2450 /* readonly register */
2451 break;
2452 case SMBSLVEVT_OFF:
2453 pThis->u16SMBusSlvEvt = u32;
2454 break;
2455 case SMBSLVDAT_OFF:
2456 /* readonly register */
2457 break;
2458 default:
2459 /* caught by the sanity check above */
2460 ;
2461 }
2462
2463 DEVACPI_UNLOCK(pDevIns, pThis);
2464 return VINF_SUCCESS;
2465}
2466
2467/**
2468 * @callback_method_impl{FNIOMIOPORTNEWIN, SMBus}
2469 */
2470static DECLCALLBACK(VBOXSTRICTRC) acpiR3SMBusRead(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT offPort, uint32_t *pu32, unsigned cb)
2471{
2472 RT_NOREF(pvUser);
2473 PACPISTATE pThis = PDMDEVINS_2_DATA(pDevIns, PACPISTATE);
2474
2475 VBOXSTRICTRC rc = VINF_SUCCESS;
2476 LogFunc(("offPort=%#x cb=%u\n", offPort, cb));
2477 uint8_t const off = offPort & 0x000f;
2478 if ( (cb != 1 && off <= SMBSHDWCMD_OFF)
2479 || (cb != 2 && (off == SMBSLVEVT_OFF || off == SMBSLVDAT_OFF)))
2480 return VERR_IOM_IOPORT_UNUSED;
2481
2482 DEVACPI_LOCK_R3(pDevIns, pThis);
2483 switch (off)
2484 {
2485 case SMBHSTSTS_OFF:
2486 *pu32 = pThis->u8SMBusHstSts;
2487 break;
2488 case SMBSLVSTS_OFF:
2489 *pu32 = pThis->u8SMBusSlvSts;
2490 break;
2491 case SMBHSTCNT_OFF:
2492 pThis->u8SMBusBlkIdx = 0;
2493 *pu32 = pThis->u8SMBusHstCnt;
2494 break;
2495 case SMBHSTCMD_OFF:
2496 *pu32 = pThis->u8SMBusHstCmd;
2497 break;
2498 case SMBHSTADD_OFF:
2499 *pu32 = pThis->u8SMBusHstAdd;
2500 break;
2501 case SMBHSTDAT0_OFF:
2502 *pu32 = pThis->u8SMBusHstDat0;
2503 break;
2504 case SMBHSTDAT1_OFF:
2505 *pu32 = pThis->u8SMBusHstDat1;
2506 break;
2507 case SMBBLKDAT_OFF:
2508 *pu32 = pThis->au8SMBusBlkDat[pThis->u8SMBusBlkIdx];
2509 pThis->u8SMBusBlkIdx++;
2510 pThis->u8SMBusBlkIdx &= sizeof(pThis->au8SMBusBlkDat) - 1;
2511 break;
2512 case SMBSLVCNT_OFF:
2513 *pu32 = pThis->u8SMBusSlvCnt;
2514 break;
2515 case SMBSHDWCMD_OFF:
2516 *pu32 = pThis->u8SMBusShdwCmd;
2517 break;
2518 case SMBSLVEVT_OFF:
2519 *pu32 = pThis->u16SMBusSlvEvt;
2520 break;
2521 case SMBSLVDAT_OFF:
2522 *pu32 = pThis->u16SMBusSlvDat;
2523 break;
2524 default:
2525 /* caught by the sanity check above */
2526 rc = VERR_IOM_IOPORT_UNUSED;
2527 }
2528 DEVACPI_UNLOCK(pDevIns, pThis);
2529
2530 LogFunc(("offPort=%#x u32=%#x cb=%u rc=%Rrc\n", offPort, *pu32, cb, VBOXSTRICTRC_VAL(rc)));
2531 return rc;
2532}
2533
2534/**
2535 * Called by acpiR3Reset and acpiR3Construct to set up the SMBus PCI config space.
2536 *
2537 * @param pDevIns The PDM device instance.
2538 * @param pThis The ACPI shared instance data.
2539 */
2540static void acpiR3SMBusPCIBIOSFake(PPDMDEVINS pDevIns, PACPISTATE pThis)
2541{
2542 PPDMPCIDEV pPciDev = pDevIns->apPciDevs[0];
2543 pPciDev->abConfig[SMBBA ] = pThis->uSMBusIoPortBase | 1; /* SMBBA, SMBus base address, bit 0 marks it as IO range */
2544 pPciDev->abConfig[SMBBA+1] = pThis->uSMBusIoPortBase >> 8;
2545 pPciDev->abConfig[SMBBA+2] = 0x00;
2546 pPciDev->abConfig[SMBBA+3] = 0x00;
2547 pPciDev->abConfig[SMBHSTCFG] = SMBHSTCFG_INTRSEL_IRQ9 << SMBHSTCFG_INTRSEL_SHIFT | SMBHSTCFG_SMB_HST_EN; /* SMBHSTCFG */
2548 pPciDev->abConfig[SMBSLVC] = 0x00; /* SMBSLVC */
2549 pPciDev->abConfig[SMBSHDW1] = 0x00; /* SMBSHDW1 */
2550 pPciDev->abConfig[SMBSHDW2] = 0x00; /* SMBSHDW2 */
2551 pPciDev->abConfig[SMBREV] = 0x00; /* SMBREV */
2552}
2553
2554/**
2555 * Called by acpiR3LoadState, acpiR3Reset and acpiR3Construct to reset the SMBus device register state.
2556 *
2557 * @param pThis The ACPI shared instance data.
2558 */
2559static void acpiR3SMBusResetDevice(PACPISTATE pThis)
2560{
2561 pThis->u8SMBusHstSts = 0x00;
2562 pThis->u8SMBusSlvSts = 0x00;
2563 pThis->u8SMBusHstCnt = 0x00;
2564 pThis->u8SMBusHstCmd = 0x00;
2565 pThis->u8SMBusHstAdd = 0x00;
2566 pThis->u8SMBusHstDat0 = 0x00;
2567 pThis->u8SMBusHstDat1 = 0x00;
2568 pThis->u8SMBusSlvCnt = 0x00;
2569 pThis->u8SMBusShdwCmd = 0x00;
2570 pThis->u16SMBusSlvEvt = 0x0000;
2571 pThis->u16SMBusSlvDat = 0x0000;
2572 memset(pThis->au8SMBusBlkDat, 0x00, sizeof(pThis->au8SMBusBlkDat));
2573 pThis->u8SMBusBlkIdx = 0;
2574}
2575
2576/**
2577 * Called by acpiR3LoadState and acpiR3UpdateSMBusHandlers to map the SMBus ports.
2578 *
2579 * @returns VBox status code.
2580 * @param pDevIns The device instance.
2581 * @param pThis The ACPI shared instance data.
2582 */
2583static int acpiR3MapSMBusIoPorts(PPDMDEVINS pDevIns, PACPISTATE pThis)
2584{
2585 if (pThis->uSMBusIoPortBase != 0)
2586 {
2587 int rc = PDMDevHlpIoPortMap(pDevIns, pThis->hIoPortSMBus, pThis->uSMBusIoPortBase);
2588 AssertRCReturn(rc, rc);
2589 }
2590 return VINF_SUCCESS;
2591}
2592
2593/**
2594 * Called by acpiR3LoadState and acpiR3UpdateSMBusHandlers to unmap the SMBus ports.
2595 *
2596 * @returns VBox status code.
2597 * @param pDevIns The device instance.
2598 * @param pThis The ACPI shared instance data.
2599 */
2600static int acpiR3UnmapSMBusPorts(PPDMDEVINS pDevIns, PACPISTATE pThis)
2601{
2602 if (pThis->uSMBusIoPortBase != 0)
2603 {
2604 int rc = PDMDevHlpIoPortUnmap(pDevIns, pThis->hIoPortSMBus);
2605 AssertRCReturn(rc, rc);
2606 }
2607 return VINF_SUCCESS;
2608}
2609
2610/**
2611 * Called by acpiR3PciConfigWrite and acpiReset to change the location of the
2612 * SMBus ports.
2613 *
2614 * @returns VBox status code.
2615 *
2616 * @param pDevIns The device instance.
2617 * @param pThis The ACPI shared instance data.
2618 * @param NewIoPortBase The new base address of the I/O ports.
2619 */
2620static int acpiR3UpdateSMBusHandlers(PPDMDEVINS pDevIns, PACPISTATE pThis, RTIOPORT NewIoPortBase)
2621{
2622 Log(("acpi: rebasing SMBus 0x%x -> 0x%x\n", pThis->uSMBusIoPortBase, NewIoPortBase));
2623 if (NewIoPortBase != pThis->uSMBusIoPortBase)
2624 {
2625 int rc = acpiR3UnmapSMBusPorts(pDevIns, pThis);
2626 AssertRCReturn(rc, rc);
2627
2628 pThis->uSMBusIoPortBase = NewIoPortBase;
2629
2630 rc = acpiR3MapSMBusIoPorts(pDevIns, pThis);
2631 AssertRCReturn(rc, rc);
2632
2633#if 0 /* is there an FADT table entry for the SMBus base? */
2634 /* We have to update FADT table acccording to the new base */
2635 rc = acpiR3PlantTables(pThis);
2636 AssertRC(rc);
2637 if (RT_FAILURE(rc))
2638 return rc;
2639#endif
2640 }
2641
2642 return VINF_SUCCESS;
2643}
2644
2645
2646/**
2647 * Saved state structure description, version 4.
2648 */
2649static const SSMFIELD g_AcpiSavedStateFields4[] =
2650{
2651 SSMFIELD_ENTRY(ACPISTATE, pm1a_en),
2652 SSMFIELD_ENTRY(ACPISTATE, pm1a_sts),
2653 SSMFIELD_ENTRY(ACPISTATE, pm1a_ctl),
2654 SSMFIELD_ENTRY(ACPISTATE, u64PmTimerInitial),
2655 SSMFIELD_ENTRY(ACPISTATE, gpe0_en),
2656 SSMFIELD_ENTRY(ACPISTATE, gpe0_sts),
2657 SSMFIELD_ENTRY(ACPISTATE, uBatteryIndex),
2658 SSMFIELD_ENTRY(ACPISTATE, uSystemInfoIndex),
2659 SSMFIELD_ENTRY(ACPISTATE, u64RamSize),
2660 SSMFIELD_ENTRY(ACPISTATE, u8IndexShift),
2661 SSMFIELD_ENTRY(ACPISTATE, u8UseIOApic),
2662 SSMFIELD_ENTRY(ACPISTATE, uSleepState),
2663 SSMFIELD_ENTRY_TERM()
2664};
2665
2666/**
2667 * Saved state structure description, version 5.
2668 */
2669static const SSMFIELD g_AcpiSavedStateFields5[] =
2670{
2671 SSMFIELD_ENTRY(ACPISTATE, pm1a_en),
2672 SSMFIELD_ENTRY(ACPISTATE, pm1a_sts),
2673 SSMFIELD_ENTRY(ACPISTATE, pm1a_ctl),
2674 SSMFIELD_ENTRY(ACPISTATE, u64PmTimerInitial),
2675 SSMFIELD_ENTRY(ACPISTATE, gpe0_en),
2676 SSMFIELD_ENTRY(ACPISTATE, gpe0_sts),
2677 SSMFIELD_ENTRY(ACPISTATE, uBatteryIndex),
2678 SSMFIELD_ENTRY(ACPISTATE, uSystemInfoIndex),
2679 SSMFIELD_ENTRY(ACPISTATE, uSleepState),
2680 SSMFIELD_ENTRY(ACPISTATE, u8IndexShift),
2681 SSMFIELD_ENTRY(ACPISTATE, uPmIoPortBase),
2682 SSMFIELD_ENTRY_TERM()
2683};
2684
2685/**
2686 * Saved state structure description, version 6.
2687 */
2688static const SSMFIELD g_AcpiSavedStateFields6[] =
2689{
2690 SSMFIELD_ENTRY(ACPISTATE, pm1a_en),
2691 SSMFIELD_ENTRY(ACPISTATE, pm1a_sts),
2692 SSMFIELD_ENTRY(ACPISTATE, pm1a_ctl),
2693 SSMFIELD_ENTRY(ACPISTATE, u64PmTimerInitial),
2694 SSMFIELD_ENTRY(ACPISTATE, gpe0_en),
2695 SSMFIELD_ENTRY(ACPISTATE, gpe0_sts),
2696 SSMFIELD_ENTRY(ACPISTATE, uBatteryIndex),
2697 SSMFIELD_ENTRY(ACPISTATE, uSystemInfoIndex),
2698 SSMFIELD_ENTRY(ACPISTATE, uSleepState),
2699 SSMFIELD_ENTRY(ACPISTATE, u8IndexShift),
2700 SSMFIELD_ENTRY(ACPISTATE, uPmIoPortBase),
2701 SSMFIELD_ENTRY(ACPISTATE, fSuspendToSavedState),
2702 SSMFIELD_ENTRY_TERM()
2703};
2704
2705/**
2706 * Saved state structure description, version 7.
2707 */
2708static const SSMFIELD g_AcpiSavedStateFields7[] =
2709{
2710 SSMFIELD_ENTRY(ACPISTATE, pm1a_en),
2711 SSMFIELD_ENTRY(ACPISTATE, pm1a_sts),
2712 SSMFIELD_ENTRY(ACPISTATE, pm1a_ctl),
2713 SSMFIELD_ENTRY(ACPISTATE, u64PmTimerInitial),
2714 SSMFIELD_ENTRY(ACPISTATE, uPmTimerVal),
2715 SSMFIELD_ENTRY(ACPISTATE, gpe0_en),
2716 SSMFIELD_ENTRY(ACPISTATE, gpe0_sts),
2717 SSMFIELD_ENTRY(ACPISTATE, uBatteryIndex),
2718 SSMFIELD_ENTRY(ACPISTATE, uSystemInfoIndex),
2719 SSMFIELD_ENTRY(ACPISTATE, uSleepState),
2720 SSMFIELD_ENTRY(ACPISTATE, u8IndexShift),
2721 SSMFIELD_ENTRY(ACPISTATE, uPmIoPortBase),
2722 SSMFIELD_ENTRY(ACPISTATE, fSuspendToSavedState),
2723 SSMFIELD_ENTRY_TERM()
2724};
2725
2726/**
2727 * Saved state structure description, version 8.
2728 */
2729static const SSMFIELD g_AcpiSavedStateFields8[] =
2730{
2731 SSMFIELD_ENTRY(ACPISTATE, pm1a_en),
2732 SSMFIELD_ENTRY(ACPISTATE, pm1a_sts),
2733 SSMFIELD_ENTRY(ACPISTATE, pm1a_ctl),
2734 SSMFIELD_ENTRY(ACPISTATE, u64PmTimerInitial),
2735 SSMFIELD_ENTRY(ACPISTATE, uPmTimerVal),
2736 SSMFIELD_ENTRY(ACPISTATE, gpe0_en),
2737 SSMFIELD_ENTRY(ACPISTATE, gpe0_sts),
2738 SSMFIELD_ENTRY(ACPISTATE, uBatteryIndex),
2739 SSMFIELD_ENTRY(ACPISTATE, uSystemInfoIndex),
2740 SSMFIELD_ENTRY(ACPISTATE, uSleepState),
2741 SSMFIELD_ENTRY(ACPISTATE, u8IndexShift),
2742 SSMFIELD_ENTRY(ACPISTATE, uPmIoPortBase),
2743 SSMFIELD_ENTRY(ACPISTATE, fSuspendToSavedState),
2744 SSMFIELD_ENTRY(ACPISTATE, uSMBusIoPortBase),
2745 SSMFIELD_ENTRY(ACPISTATE, u8SMBusHstSts),
2746 SSMFIELD_ENTRY(ACPISTATE, u8SMBusSlvSts),
2747 SSMFIELD_ENTRY(ACPISTATE, u8SMBusHstCnt),
2748 SSMFIELD_ENTRY(ACPISTATE, u8SMBusHstCmd),
2749 SSMFIELD_ENTRY(ACPISTATE, u8SMBusHstAdd),
2750 SSMFIELD_ENTRY(ACPISTATE, u8SMBusHstDat0),
2751 SSMFIELD_ENTRY(ACPISTATE, u8SMBusHstDat1),
2752 SSMFIELD_ENTRY(ACPISTATE, u8SMBusSlvCnt),
2753 SSMFIELD_ENTRY(ACPISTATE, u8SMBusShdwCmd),
2754 SSMFIELD_ENTRY(ACPISTATE, u16SMBusSlvEvt),
2755 SSMFIELD_ENTRY(ACPISTATE, u16SMBusSlvDat),
2756 SSMFIELD_ENTRY(ACPISTATE, au8SMBusBlkDat),
2757 SSMFIELD_ENTRY(ACPISTATE, u8SMBusBlkIdx),
2758 SSMFIELD_ENTRY_TERM()
2759};
2760
2761/**
2762 * @callback_method_impl{FNSSMDEVSAVEEXEC}
2763 */
2764static DECLCALLBACK(int) acpiR3SaveState(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
2765{
2766 PACPISTATE pThis = PDMDEVINS_2_DATA(pDevIns, PACPISTATE);
2767 PCPDMDEVHLPR3 pHlp = pDevIns->pHlpR3;
2768 return pHlp->pfnSSMPutStruct(pSSM, pThis, &g_AcpiSavedStateFields8[0]);
2769}
2770
2771/**
2772 * @callback_method_impl{FNSSMDEVLOADEXEC}
2773 */
2774static DECLCALLBACK(int) acpiR3LoadState(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
2775{
2776 PACPISTATE pThis = PDMDEVINS_2_DATA(pDevIns, PACPISTATE);
2777 PACPISTATER3 pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PACPISTATER3);
2778 PCPDMDEVHLPR3 pHlp = pDevIns->pHlpR3;
2779 Assert(uPass == SSM_PASS_FINAL); NOREF(uPass);
2780
2781 /*
2782 * Unmap PM I/O ports, will remap it with the actual base after state
2783 * successfully loaded.
2784 */
2785 int rc = acpiR3UnmapPmIoPorts(pDevIns, pThis);
2786 AssertRCReturn(rc, rc);
2787
2788 /*
2789 * Unregister SMBus handlers, will register with actual base after state
2790 * successfully loaded.
2791 */
2792 rc = acpiR3UnmapSMBusPorts(pDevIns, pThis);
2793 AssertRCReturn(rc, rc);
2794 acpiR3SMBusResetDevice(pThis);
2795
2796 switch (uVersion)
2797 {
2798 case 4:
2799 rc = pHlp->pfnSSMGetStruct(pSSM, pThis, &g_AcpiSavedStateFields4[0]);
2800 break;
2801 case 5:
2802 rc = pHlp->pfnSSMGetStruct(pSSM, pThis, &g_AcpiSavedStateFields5[0]);
2803 break;
2804 case 6:
2805 rc = pHlp->pfnSSMGetStruct(pSSM, pThis, &g_AcpiSavedStateFields6[0]);
2806 break;
2807 case 7:
2808 rc = pHlp->pfnSSMGetStruct(pSSM, pThis, &g_AcpiSavedStateFields7[0]);
2809 break;
2810 case 8:
2811 rc = pHlp->pfnSSMGetStruct(pSSM, pThis, &g_AcpiSavedStateFields8[0]);
2812 break;
2813 default:
2814 rc = VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
2815 break;
2816 }
2817 if (RT_SUCCESS(rc))
2818 {
2819 AssertLogRelMsgReturn(pThis->u8SMBusBlkIdx < RT_ELEMENTS(pThis->au8SMBusBlkDat),
2820 ("%#x\n", pThis->u8SMBusBlkIdx), VERR_SSM_LOAD_CONFIG_MISMATCH);
2821 rc = acpiR3MapPmIoPorts(pDevIns, pThis);
2822 AssertRCReturn(rc, rc);
2823 rc = acpiR3MapSMBusIoPorts(pDevIns, pThis);
2824 AssertRCReturn(rc, rc);
2825 rc = acpiR3FetchBatteryStatus(pThis, pThisCC);
2826 AssertRCReturn(rc, rc);
2827 rc = acpiR3FetchBatteryInfo(pThis);
2828 AssertRCReturn(rc, rc);
2829
2830 PDMDevHlpTimerLockClock(pDevIns, pThis->hPmTimer, VERR_IGNORED);
2831 DEVACPI_LOCK_R3(pDevIns, pThis);
2832 uint64_t u64Now = PDMDevHlpTimerGet(pDevIns, pThis->hPmTimer);
2833 /* The interrupt may be incorrectly re-generated if the state is restored from versions < 7. */
2834 acpiPmTimerUpdate(pDevIns, pThis, u64Now);
2835 acpiR3PmTimerReset(pDevIns, pThis, u64Now);
2836 DEVACPI_UNLOCK(pDevIns, pThis);
2837 PDMDevHlpTimerUnlockClock(pDevIns, pThis->hPmTimer);
2838 }
2839 return rc;
2840}
2841
2842/**
2843 * @interface_method_impl{PDMIBASE,pfnQueryInterface}
2844 */
2845static DECLCALLBACK(void *) acpiR3QueryInterface(PPDMIBASE pInterface, const char *pszIID)
2846{
2847 PACPISTATER3 pThisCC = RT_FROM_MEMBER(pInterface, ACPISTATER3, IBase);
2848 PDMIBASE_RETURN_INTERFACE(pszIID, PDMIBASE, &pThisCC->IBase);
2849 PDMIBASE_RETURN_INTERFACE(pszIID, PDMIACPIPORT, &pThisCC->IACPIPort);
2850 return NULL;
2851}
2852
2853/**
2854 * Calculate the check sum for some ACPI data before planting it.
2855 *
2856 * All the bytes must add up to 0.
2857 *
2858 * @returns check sum.
2859 * @param pvSrc What to check sum.
2860 * @param cbData The amount of data to checksum.
2861 */
2862static uint8_t acpiR3Checksum(const void * const pvSrc, size_t cbData)
2863{
2864 uint8_t const *pbSrc = (uint8_t const *)pvSrc;
2865 uint8_t uSum = 0;
2866 for (size_t i = 0; i < cbData; ++i)
2867 uSum += pbSrc[i];
2868 return -uSum;
2869}
2870
2871/**
2872 * Prepare a ACPI table header.
2873 */
2874static void acpiR3PrepareHeader(PACPISTATE pThis, ACPITBLHEADER *header,
2875 const char au8Signature[4],
2876 uint32_t u32Length, uint8_t u8Revision)
2877{
2878 memcpy(header->au8Signature, au8Signature, 4);
2879 header->u32Length = RT_H2LE_U32(u32Length);
2880 header->u8Revision = u8Revision;
2881 memcpy(header->au8OemId, pThis->au8OemId, 6);
2882 memcpy(header->au8OemTabId, "VBOX", 4);
2883 memcpy(header->au8OemTabId+4, au8Signature, 4);
2884 header->u32OemRevision = RT_H2LE_U32(1);
2885 memcpy(header->au8CreatorId, pThis->au8CreatorId, 4);
2886 header->u32CreatorRev = pThis->u32CreatorRev;
2887}
2888
2889/**
2890 * Initialize a generic address structure (ACPIGENADDR).
2891 */
2892static void acpiR3WriteGenericAddr(ACPIGENADDR *g, uint8_t u8AddressSpaceId,
2893 uint8_t u8RegisterBitWidth, uint8_t u8RegisterBitOffset,
2894 uint8_t u8AccessSize, uint64_t u64Address)
2895{
2896 g->u8AddressSpaceId = u8AddressSpaceId;
2897 g->u8RegisterBitWidth = u8RegisterBitWidth;
2898 g->u8RegisterBitOffset = u8RegisterBitOffset;
2899 g->u8AccessSize = u8AccessSize;
2900 g->u64Address = RT_H2LE_U64(u64Address);
2901}
2902
2903/**
2904 * Wrapper around PDMDevHlpPhysWrite used when planting ACPI tables.
2905 */
2906DECLINLINE(void) acpiR3PhysCopy(PPDMDEVINS pDevIns, RTGCPHYS32 GCPhys32Dst, const void *pvSrc, size_t cbToCopy)
2907{
2908 PDMDevHlpPhysWrite(pDevIns, GCPhys32Dst, pvSrc, cbToCopy);
2909}
2910
2911/**
2912 * Plant the Differentiated System Description Table (DSDT).
2913 */
2914static void acpiR3SetupDsdt(PPDMDEVINS pDevIns, RTGCPHYS32 GCPhys32, void const *pvSrc, size_t cbDsdt)
2915{
2916 acpiR3PhysCopy(pDevIns, GCPhys32, pvSrc, cbDsdt);
2917}
2918
2919/**
2920 * Plant the Secondary System Description Table (SSDT).
2921 */
2922static void acpiR3SetupSsdt(PPDMDEVINS pDevIns, RTGCPHYS32 addr, void const *pvSrc, size_t uSsdtLen)
2923{
2924 acpiR3PhysCopy(pDevIns, addr, pvSrc, uSsdtLen);
2925}
2926
2927#ifdef VBOX_WITH_TPM
2928/**
2929 * Plant the Secondary System Description Table (SSDT).
2930 */
2931static void acpiR3SetupTpmSsdt(PPDMDEVINS pDevIns, RTGCPHYS32 addr, void const *pvSrc, size_t uSsdtLen)
2932{
2933 acpiR3PhysCopy(pDevIns, addr, pvSrc, uSsdtLen);
2934}
2935#endif
2936
2937/**
2938 * Plant the Firmware ACPI Control Structure (FACS).
2939 */
2940static void acpiR3SetupFacs(PPDMDEVINS pDevIns, RTGCPHYS32 addr)
2941{
2942 ACPITBLFACS facs;
2943
2944 memset(&facs, 0, sizeof(facs));
2945 memcpy(facs.au8Signature, "FACS", 4);
2946 facs.u32Length = RT_H2LE_U32(sizeof(ACPITBLFACS));
2947 facs.u32HWSignature = RT_H2LE_U32(0);
2948 facs.u32FWVector = RT_H2LE_U32(0);
2949 facs.u32GlobalLock = RT_H2LE_U32(0);
2950 facs.u32Flags = RT_H2LE_U32(0);
2951 facs.u64X_FWVector = RT_H2LE_U64(0);
2952 facs.u8Version = 1;
2953
2954 acpiR3PhysCopy(pDevIns, addr, (const uint8_t *)&facs, sizeof(facs));
2955}
2956
2957/**
2958 * Plant the Fixed ACPI Description Table (FADT aka FACP).
2959 */
2960static void acpiR3SetupFadt(PPDMDEVINS pDevIns, PACPISTATE pThis, RTGCPHYS32 GCPhysAcpi1, RTGCPHYS32 GCPhysAcpi2,
2961 RTGCPHYS32 GCPhysFacs, RTGCPHYS GCPhysDsdt)
2962{
2963 ACPITBLFADT fadt;
2964
2965 /* First the ACPI version 2+ version of the structure. */
2966 memset(&fadt, 0, sizeof(fadt));
2967 acpiR3PrepareHeader(pThis, &fadt.header, "FACP", sizeof(fadt), 4);
2968 fadt.u32FACS = RT_H2LE_U32(GCPhysFacs);
2969 fadt.u32DSDT = RT_H2LE_U32(GCPhysDsdt);
2970 fadt.u8IntModel = 0; /* dropped from the ACPI 2.0 spec. */
2971 fadt.u8PreferredPMProfile = 0; /* unspecified */
2972 fadt.u16SCIInt = RT_H2LE_U16(SCI_INT);
2973 fadt.u32SMICmd = RT_H2LE_U32(SMI_CMD);
2974 fadt.u8AcpiEnable = ACPI_ENABLE;
2975 fadt.u8AcpiDisable = ACPI_DISABLE;
2976 fadt.u8S4BIOSReq = 0;
2977 fadt.u8PStateCnt = 0;
2978 fadt.u32PM1aEVTBLK = RT_H2LE_U32(acpiR3CalcPmPort(pThis, PM1a_EVT_OFFSET));
2979 fadt.u32PM1bEVTBLK = RT_H2LE_U32(acpiR3CalcPmPort(pThis, PM1b_EVT_OFFSET));
2980 fadt.u32PM1aCTLBLK = RT_H2LE_U32(acpiR3CalcPmPort(pThis, PM1a_CTL_OFFSET));
2981 fadt.u32PM1bCTLBLK = RT_H2LE_U32(acpiR3CalcPmPort(pThis, PM1b_CTL_OFFSET));
2982 fadt.u32PM2CTLBLK = RT_H2LE_U32(acpiR3CalcPmPort(pThis, PM2_CTL_OFFSET));
2983 fadt.u32PMTMRBLK = RT_H2LE_U32(acpiR3CalcPmPort(pThis, PM_TMR_OFFSET));
2984 fadt.u32GPE0BLK = RT_H2LE_U32(acpiR3CalcPmPort(pThis, GPE0_OFFSET));
2985 fadt.u32GPE1BLK = RT_H2LE_U32(acpiR3CalcPmPort(pThis, GPE1_OFFSET));
2986 fadt.u8PM1EVTLEN = 4;
2987 fadt.u8PM1CTLLEN = 2;
2988 fadt.u8PM2CTLLEN = 0;
2989 fadt.u8PMTMLEN = 4;
2990 fadt.u8GPE0BLKLEN = GPE0_BLK_LEN;
2991 fadt.u8GPE1BLKLEN = GPE1_BLK_LEN;
2992 fadt.u8GPE1BASE = GPE1_BASE;
2993 fadt.u8CSTCNT = 0;
2994 fadt.u16PLVL2LAT = RT_H2LE_U16(P_LVL2_LAT);
2995 fadt.u16PLVL3LAT = RT_H2LE_U16(P_LVL3_LAT);
2996 fadt.u16FlushSize = RT_H2LE_U16(FLUSH_SIZE);
2997 fadt.u16FlushStride = RT_H2LE_U16(FLUSH_STRIDE);
2998 fadt.u8DutyOffset = 0;
2999 fadt.u8DutyWidth = 0;
3000 fadt.u8DayAlarm = 0;
3001 fadt.u8MonAlarm = 0;
3002 fadt.u8Century = 0;
3003 fadt.u16IAPCBOOTARCH = RT_H2LE_U16(IAPC_BOOT_ARCH_LEGACY_DEV | IAPC_BOOT_ARCH_8042);
3004 /** @note WBINVD is required for ACPI versions newer than 1.0 */
3005 fadt.u32Flags = RT_H2LE_U32( FADT_FL_WBINVD
3006 | FADT_FL_FIX_RTC
3007 | FADT_FL_TMR_VAL_EXT
3008 | FADT_FL_RESET_REG_SUP);
3009
3010 /* We have to force physical APIC mode or Linux can't use more than 8 CPUs */
3011 if (pThis->fCpuHotPlug)
3012 fadt.u32Flags |= RT_H2LE_U32(FADT_FL_FORCE_APIC_PHYS_DEST_MODE);
3013
3014 acpiR3WriteGenericAddr(&fadt.ResetReg, 1, 8, 0, 1, ACPI_RESET_BLK);
3015 fadt.u8ResetVal = ACPI_RESET_REG_VAL;
3016 fadt.u64XFACS = RT_H2LE_U64((uint64_t)GCPhysFacs);
3017 fadt.u64XDSDT = RT_H2LE_U64((uint64_t)GCPhysDsdt);
3018 acpiR3WriteGenericAddr(&fadt.X_PM1aEVTBLK, 1, 32, 0, 2, acpiR3CalcPmPort(pThis, PM1a_EVT_OFFSET));
3019 acpiR3WriteGenericAddr(&fadt.X_PM1bEVTBLK, 0, 0, 0, 0, acpiR3CalcPmPort(pThis, PM1b_EVT_OFFSET));
3020 acpiR3WriteGenericAddr(&fadt.X_PM1aCTLBLK, 1, 16, 0, 2, acpiR3CalcPmPort(pThis, PM1a_CTL_OFFSET));
3021 acpiR3WriteGenericAddr(&fadt.X_PM1bCTLBLK, 0, 0, 0, 0, acpiR3CalcPmPort(pThis, PM1b_CTL_OFFSET));
3022 acpiR3WriteGenericAddr(&fadt.X_PM2CTLBLK, 0, 0, 0, 0, acpiR3CalcPmPort(pThis, PM2_CTL_OFFSET));
3023 acpiR3WriteGenericAddr(&fadt.X_PMTMRBLK, 1, 32, 0, 3, acpiR3CalcPmPort(pThis, PM_TMR_OFFSET));
3024 acpiR3WriteGenericAddr(&fadt.X_GPE0BLK, 1, 16, 0, 1, acpiR3CalcPmPort(pThis, GPE0_OFFSET));
3025 acpiR3WriteGenericAddr(&fadt.X_GPE1BLK, 0, 0, 0, 0, acpiR3CalcPmPort(pThis, GPE1_OFFSET));
3026 fadt.header.u8Checksum = acpiR3Checksum(&fadt, sizeof(fadt));
3027 acpiR3PhysCopy(pDevIns, GCPhysAcpi2, &fadt, sizeof(fadt));
3028
3029 /* Now the ACPI 1.0 version. */
3030 fadt.header.u32Length = ACPITBLFADT_VERSION1_SIZE;
3031 fadt.u8IntModel = INT_MODEL_DUAL_PIC;
3032 fadt.header.u8Checksum = 0; /* Must be zeroed before recalculating checksum! */
3033 fadt.header.u8Checksum = acpiR3Checksum(&fadt, ACPITBLFADT_VERSION1_SIZE);
3034 acpiR3PhysCopy(pDevIns, GCPhysAcpi1, &fadt, ACPITBLFADT_VERSION1_SIZE);
3035}
3036
3037/**
3038 * Plant the root System Description Table.
3039 *
3040 * The RSDT and XSDT tables are basically identical. The only difference is 32
3041 * vs 64 bits addresses for description headers. RSDT is for ACPI 1.0. XSDT for
3042 * ACPI 2.0 and up.
3043 */
3044static int acpiR3SetupRsdt(PPDMDEVINS pDevIns, PACPISTATE pThis, RTGCPHYS32 addr, unsigned int nb_entries, uint32_t *addrs)
3045{
3046 ACPITBLRSDT *rsdt;
3047 const size_t size = sizeof(ACPITBLHEADER) + nb_entries * sizeof(rsdt->u32Entry[0]);
3048
3049 rsdt = (ACPITBLRSDT*)RTMemAllocZ(size);
3050 if (!rsdt)
3051 return PDMDEV_SET_ERROR(pDevIns, VERR_NO_TMP_MEMORY, N_("Cannot allocate RSDT"));
3052
3053 acpiR3PrepareHeader(pThis, &rsdt->header, "RSDT", (uint32_t)size, 1);
3054 for (unsigned int i = 0; i < nb_entries; ++i)
3055 {
3056 rsdt->u32Entry[i] = RT_H2LE_U32(addrs[i]);
3057 Log(("Setup RSDT: [%d] = %x\n", i, rsdt->u32Entry[i]));
3058 }
3059 rsdt->header.u8Checksum = acpiR3Checksum(rsdt, size);
3060 acpiR3PhysCopy(pDevIns, addr, rsdt, size);
3061 RTMemFree(rsdt);
3062 return VINF_SUCCESS;
3063}
3064
3065/**
3066 * Plant the Extended System Description Table.
3067 */
3068static int acpiR3SetupXsdt(PPDMDEVINS pDevIns, PACPISTATE pThis, RTGCPHYS32 addr, unsigned int nb_entries, uint32_t *addrs)
3069{
3070 ACPITBLXSDT *xsdt;
3071 const size_t cbXsdt = sizeof(ACPITBLHEADER) + nb_entries * sizeof(xsdt->u64Entry[0]);
3072 xsdt = (ACPITBLXSDT *)RTMemAllocZ(cbXsdt);
3073 if (!xsdt)
3074 return VERR_NO_TMP_MEMORY;
3075
3076 acpiR3PrepareHeader(pThis, &xsdt->header, "XSDT", (uint32_t)cbXsdt, 1 /* according to ACPI 3.0 specs */);
3077
3078 if (pThis->cCustTbls > 0)
3079 memcpy(xsdt->header.au8OemTabId, pThis->au8OemTabId, 8);
3080
3081 for (unsigned int i = 0; i < nb_entries; ++i)
3082 {
3083 xsdt->u64Entry[i] = RT_H2LE_U64((uint64_t)addrs[i]);
3084 Log(("Setup XSDT: [%d] = %RX64\n", i, xsdt->u64Entry[i]));
3085 }
3086 xsdt->header.u8Checksum = acpiR3Checksum(xsdt, cbXsdt);
3087 acpiR3PhysCopy(pDevIns, addr, xsdt, cbXsdt);
3088
3089 RTMemFree(xsdt);
3090 return VINF_SUCCESS;
3091}
3092
3093/**
3094 * Plant the Root System Description Pointer (RSDP).
3095 */
3096static void acpiR3SetupRsdp(PACPISTATE pThis, ACPITBLRSDP *rsdp, RTGCPHYS32 GCPhysRsdt, RTGCPHYS GCPhysXsdt)
3097{
3098 memset(rsdp, 0, sizeof(*rsdp));
3099
3100 /* ACPI 1.0 part (RSDT) */
3101 memcpy(rsdp->au8Signature, "RSD PTR ", 8);
3102 memcpy(rsdp->au8OemId, pThis->au8OemId, 6);
3103 rsdp->u8Revision = ACPI_REVISION;
3104 rsdp->u32RSDT = RT_H2LE_U32(GCPhysRsdt);
3105 rsdp->u8Checksum = acpiR3Checksum(rsdp, RT_OFFSETOF(ACPITBLRSDP, u32Length));
3106
3107 /* ACPI 2.0 part (XSDT) */
3108 rsdp->u32Length = RT_H2LE_U32(sizeof(ACPITBLRSDP));
3109 rsdp->u64XSDT = RT_H2LE_U64(GCPhysXsdt);
3110 rsdp->u8ExtChecksum = acpiR3Checksum(rsdp, sizeof(ACPITBLRSDP));
3111}
3112
3113/**
3114 * Multiple APIC Description Table.
3115 *
3116 * This structure looks somewhat convoluted due layout of MADT table in MP case.
3117 * There extpected to be multiple LAPIC records for each CPU, thus we cannot
3118 * use regular C structure and proxy to raw memory instead.
3119 */
3120class AcpiTableMadt
3121{
3122 /**
3123 * All actual data stored in dynamically allocated memory pointed by this field.
3124 */
3125 uint8_t *m_pbData;
3126 /**
3127 * Number of CPU entries in this MADT.
3128 */
3129 uint32_t m_cCpus;
3130
3131 /**
3132 * Number of interrupt overrides.
3133 */
3134 uint32_t m_cIsos;
3135
3136public:
3137 /**
3138 * Address of ACPI header
3139 */
3140 inline ACPITBLHEADER *header_addr(void) const
3141 {
3142 return (ACPITBLHEADER *)m_pbData;
3143 }
3144
3145 /**
3146 * Address of local APIC for each CPU. Note that different CPUs address different LAPICs,
3147 * although address is the same for all of them.
3148 */
3149 inline uint32_t *u32LAPIC_addr(void) const
3150 {
3151 return (uint32_t *)(header_addr() + 1);
3152 }
3153
3154 /**
3155 * Address of APIC flags
3156 */
3157 inline uint32_t *u32Flags_addr(void) const
3158 {
3159 return (uint32_t *)(u32LAPIC_addr() + 1);
3160 }
3161
3162 /**
3163 * Address of ISO description
3164 */
3165 inline ACPITBLISO *ISO_addr(void) const
3166 {
3167 return (ACPITBLISO *)(u32Flags_addr() + 1);
3168 }
3169
3170 /**
3171 * Address of per-CPU LAPIC descriptions
3172 */
3173 inline ACPITBLLAPIC *LApics_addr(void) const
3174 {
3175 return (ACPITBLLAPIC *)(ISO_addr() + m_cIsos);
3176 }
3177
3178 /**
3179 * Address of IO APIC description
3180 */
3181 inline ACPITBLIOAPIC *IOApic_addr(void) const
3182 {
3183 return (ACPITBLIOAPIC *)(LApics_addr() + m_cCpus);
3184 }
3185
3186 /**
3187 * Size of MADT.
3188 * Note that this function assumes IOApic to be the last field in structure.
3189 */
3190 inline uint32_t size(void) const
3191 {
3192 return (uint8_t *)(IOApic_addr() + 1) - (uint8_t *)header_addr();
3193 }
3194
3195 /**
3196 * Raw data of MADT.
3197 */
3198 inline const uint8_t *data(void) const
3199 {
3200 return m_pbData;
3201 }
3202
3203 /**
3204 * Size of MADT for given ACPI config, useful to compute layout.
3205 */
3206 static uint32_t sizeFor(PACPISTATE pThis, uint32_t cIsos)
3207 {
3208 return AcpiTableMadt(pThis->cCpus, cIsos).size();
3209 }
3210
3211 /*
3212 * Constructor, only works in Ring 3, doesn't look like a big deal.
3213 */
3214 AcpiTableMadt(uint32_t cCpus, uint32_t cIsos)
3215 {
3216 m_cCpus = cCpus;
3217 m_cIsos = cIsos;
3218 m_pbData = NULL; /* size() uses this and gcc will complain if not initialized. */
3219 uint32_t cb = size();
3220 m_pbData = (uint8_t *)RTMemAllocZ(cb);
3221 }
3222
3223 ~AcpiTableMadt()
3224 {
3225 RTMemFree(m_pbData);
3226 }
3227};
3228
3229
3230/**
3231 * Plant the Multiple APIC Description Table (MADT).
3232 *
3233 * @note APIC without IO-APIC hangs Windows Vista therefore we setup both.
3234 *
3235 * @todo All hardcoded, should set this up based on the actual VM config!!!!!
3236 */
3237static void acpiR3SetupMadt(PPDMDEVINS pDevIns, PACPISTATE pThis, RTGCPHYS32 addr)
3238{
3239 uint16_t cpus = pThis->cCpus;
3240 AcpiTableMadt madt(cpus, NUMBER_OF_IRQ_SOURCE_OVERRIDES);
3241
3242 acpiR3PrepareHeader(pThis, madt.header_addr(), "APIC", madt.size(), 2);
3243
3244 *madt.u32LAPIC_addr() = RT_H2LE_U32(0xfee00000);
3245 *madt.u32Flags_addr() = RT_H2LE_U32(PCAT_COMPAT);
3246
3247 /* LAPICs records */
3248 ACPITBLLAPIC* lapic = madt.LApics_addr();
3249 for (uint16_t i = 0; i < cpus; i++)
3250 {
3251 lapic->u8Type = 0;
3252 lapic->u8Length = sizeof(ACPITBLLAPIC);
3253 lapic->u8ProcId = i;
3254 /** Must match numbering convention in MPTABLES */
3255 lapic->u8ApicId = i;
3256 lapic->u32Flags = VMCPUSET_IS_PRESENT(&pThis->CpuSetAttached, i) ? RT_H2LE_U32(LAPIC_ENABLED) : 0;
3257 lapic++;
3258 }
3259
3260 /* IO-APIC record */
3261 ACPITBLIOAPIC* ioapic = madt.IOApic_addr();
3262 ioapic->u8Type = 1;
3263 ioapic->u8Length = sizeof(ACPITBLIOAPIC);
3264 /** Must match MP tables ID */
3265 ioapic->u8IOApicId = cpus;
3266 ioapic->u8Reserved = 0;
3267 ioapic->u32Address = RT_H2LE_U32(0xfec00000);
3268 ioapic->u32GSIB = RT_H2LE_U32(0);
3269
3270 /* Interrupt Source Overrides */
3271 /* Flags:
3272 bits[3:2]:
3273 00 conforms to the bus
3274 01 edge-triggered
3275 10 reserved
3276 11 level-triggered
3277 bits[1:0]
3278 00 conforms to the bus
3279 01 active-high
3280 10 reserved
3281 11 active-low */
3282 /* If changing, also update PDMIsaSetIrq() and MPS */
3283 ACPITBLISO* isos = madt.ISO_addr();
3284 /* Timer interrupt rule IRQ0 to GSI2 */
3285 isos[0].u8Type = 2;
3286 isos[0].u8Length = sizeof(ACPITBLISO);
3287 isos[0].u8Bus = 0; /* Must be 0 */
3288 isos[0].u8Source = 0; /* IRQ0 */
3289 isos[0].u32GSI = 2; /* connected to pin 2 */
3290 isos[0].u16Flags = 0; /* conform to the bus */
3291
3292 /* ACPI interrupt rule - IRQ9 to GSI9 */
3293 isos[1].u8Type = 2;
3294 isos[1].u8Length = sizeof(ACPITBLISO);
3295 isos[1].u8Bus = 0; /* Must be 0 */
3296 isos[1].u8Source = 9; /* IRQ9 */
3297 isos[1].u32GSI = 9; /* connected to pin 9 */
3298 isos[1].u16Flags = 0xf; /* active low, level triggered */
3299 Assert(NUMBER_OF_IRQ_SOURCE_OVERRIDES == 2);
3300
3301 madt.header_addr()->u8Checksum = acpiR3Checksum(madt.data(), madt.size());
3302 acpiR3PhysCopy(pDevIns, addr, madt.data(), madt.size());
3303}
3304
3305/**
3306 * Plant the High Performance Event Timer (HPET) descriptor.
3307 */
3308static void acpiR3SetupHpet(PPDMDEVINS pDevIns, PACPISTATE pThis, RTGCPHYS32 addr)
3309{
3310 ACPITBLHPET hpet;
3311
3312 memset(&hpet, 0, sizeof(hpet));
3313
3314 acpiR3PrepareHeader(pThis, &hpet.aHeader, "HPET", sizeof(hpet), 1);
3315 /* Keep base address consistent with appropriate DSDT entry (vbox.dsl) */
3316 acpiR3WriteGenericAddr(&hpet.HpetAddr,
3317 0 /* Memory address space */,
3318 64 /* Register bit width */,
3319 0 /* Bit offset */,
3320 0, /* Register access size, is it correct? */
3321 0xfed00000 /* Address */);
3322
3323 hpet.u32Id = 0x8086a201; /* must match what HPET ID returns, is it correct ? */
3324 hpet.u32Number = 0;
3325 hpet.u32MinTick = 4096;
3326 hpet.u8Attributes = 0;
3327
3328 hpet.aHeader.u8Checksum = acpiR3Checksum(&hpet, sizeof(hpet));
3329
3330 acpiR3PhysCopy(pDevIns, addr, (const uint8_t *)&hpet, sizeof(hpet));
3331}
3332
3333
3334#ifdef VBOX_WITH_IOMMU_AMD
3335/**
3336 * Plant the AMD IOMMU descriptor.
3337 */
3338static void acpiR3SetupIommuAmd(PPDMDEVINS pDevIns, PACPISTATE pThis, RTGCPHYS32 addr)
3339{
3340 ACPITBLIOMMU Ivrs;
3341 RT_ZERO(Ivrs);
3342
3343 uint16_t const uIommuBus = 0;
3344 uint16_t const uIommuDev = RT_HI_U16(pThis->u32IommuPciAddress);
3345 uint16_t const uIommuFn = RT_LO_U16(pThis->u32IommuPciAddress);
3346
3347 /* IVRS header. */
3348 acpiR3PrepareHeader(pThis, &Ivrs.Hdr.header, "IVRS", sizeof(Ivrs), ACPI_IVRS_FMT_REV_FIXED);
3349 /* NOTE! The values here must match what we expose via MMIO/PCI config. space in the IOMMU device code. */
3350 Ivrs.Hdr.u32IvInfo = RT_BF_MAKE(ACPI_IVINFO_BF_EFR_SUP, 1)
3351 | RT_BF_MAKE(ACPI_IVINFO_BF_DMA_REMAP_SUP, 0) /* Pre-boot DMA remap support not supported. */
3352 | RT_BF_MAKE(ACPI_IVINFO_BF_GVA_SIZE, 2) /* Guest Virt. Addr size (2=48 bits) */
3353 | RT_BF_MAKE(ACPI_IVINFO_BF_PA_SIZE, 48) /* Physical Addr size (48 bits) */
3354 | RT_BF_MAKE(ACPI_IVINFO_BF_VA_SIZE, 64) /* Virt. Addr size (64 bits) */
3355 | RT_BF_MAKE(ACPI_IVINFO_BF_HT_ATS_RESV, 0); /* ATS response range reserved (only applicable for HT) */
3356
3357 /* IVHD type 10 definition block. */
3358 Ivrs.IvhdType10.u8Type = 0x10;
3359 Ivrs.IvhdType10.u16Length = sizeof(Ivrs.IvhdType10)
3360 + sizeof(Ivrs.IvhdType10Start)
3361 + sizeof(Ivrs.IvhdType10End)
3362 + sizeof(Ivrs.IvhdType10Rsvd0)
3363 + sizeof(Ivrs.IvhdType10Rsvd1)
3364 + sizeof(Ivrs.IvhdType10IoApic)
3365 + sizeof(Ivrs.IvhdType10Hpet);
3366 Ivrs.IvhdType10.u16DeviceId = PCIBDF_MAKE(uIommuBus, VBOX_PCI_DEVFN_MAKE(uIommuDev, uIommuFn));
3367 Ivrs.IvhdType10.u16CapOffset = IOMMU_PCI_OFF_CAP_HDR;
3368 Ivrs.IvhdType10.u64BaseAddress = IOMMU_MMIO_BASE_ADDR;
3369 Ivrs.IvhdType10.u16PciSegmentGroup = 0;
3370 /* NOTE! Subfields in the following fields must match any corresponding field in PCI/MMIO registers of the IOMMU device. */
3371 Ivrs.IvhdType10.u8Flags = ACPI_IVHD_10H_F_COHERENT; /* Remote IOTLB etc. not supported. */
3372 Ivrs.IvhdType10.u16IommuInfo = RT_BF_MAKE(ACPI_IOMMU_INFO_BF_MSI_NUM, 0)
3373 | RT_BF_MAKE(ACPI_IOMMU_INFO_BF_UNIT_ID, 0);
3374 Ivrs.IvhdType10.u32Features = RT_BF_MAKE(ACPI_IOMMU_FEAT_BF_XT_SUP, 0)
3375 | RT_BF_MAKE(ACPI_IOMMU_FEAT_BF_NX_SUP, 0)
3376 | RT_BF_MAKE(ACPI_IOMMU_FEAT_BF_GT_SUP, 0)
3377 | RT_BF_MAKE(ACPI_IOMMU_FEAT_BF_GLX_SUP, 0)
3378 | RT_BF_MAKE(ACPI_IOMMU_FEAT_BF_IA_SUP, 1)
3379 | RT_BF_MAKE(ACPI_IOMMU_FEAT_BF_GA_SUP, 0)
3380 | RT_BF_MAKE(ACPI_IOMMU_FEAT_BF_HE_SUP, 1)
3381 | RT_BF_MAKE(ACPI_IOMMU_FEAT_BF_PAS_MAX, 0)
3382 | RT_BF_MAKE(ACPI_IOMMU_FEAT_BF_PN_COUNTERS, 0)
3383 | RT_BF_MAKE(ACPI_IOMMU_FEAT_BF_PN_BANKS, 0)
3384 | RT_BF_MAKE(ACPI_IOMMU_FEAT_BF_PN_COUNTERS, 0)
3385 | RT_BF_MAKE(ACPI_IOMMU_FEAT_BF_MSI_NUM_PPR, 0)
3386 | RT_BF_MAKE(ACPI_IOMMU_FEAT_BF_GATS, 0)
3387 | RT_BF_MAKE(ACPI_IOMMU_FEAT_BF_HATS, IOMMU_MAX_HOST_PT_LEVEL & 3);
3388 /* Start range from BDF (00:01:00). */
3389 Ivrs.IvhdType10Start.u8DevEntryType = ACPI_IVHD_DEVENTRY_TYPE_START_RANGE;
3390 Ivrs.IvhdType10Start.u16DevId = PCIBDF_MAKE(0, VBOX_PCI_DEVFN_MAKE(1, 0));
3391 Ivrs.IvhdType10Start.u8DteSetting = 0;
3392 /* End range at BDF (ff:1f:7). */
3393 Ivrs.IvhdType10End.u8DevEntryType = ACPI_IVHD_DEVENTRY_TYPE_END_RANGE;
3394 Ivrs.IvhdType10End.u16DevId = PCIBDF_MAKE(0xff, VBOX_PCI_DEVFN_MAKE(0x1f, 7U));
3395 Ivrs.IvhdType10End.u8DteSetting = 0;
3396
3397 /* Southbridge I/O APIC special device entry. */
3398 Ivrs.IvhdType10IoApic.u8DevEntryType = 0x48;
3399 Ivrs.IvhdType10IoApic.u.special.u16Rsvd0 = 0;
3400 Ivrs.IvhdType10IoApic.u.special.u8DteSetting = RT_BF_MAKE(ACPI_IVHD_DTE_INIT_PASS, 1)
3401 | RT_BF_MAKE(ACPI_IVHD_DTE_EXTINT_PASS, 1)
3402 | RT_BF_MAKE(ACPI_IVHD_DTE_NMI_PASS, 1)
3403 | RT_BF_MAKE(ACPI_IVHD_DTE_LINT0_PASS, 1)
3404 | RT_BF_MAKE(ACPI_IVHD_DTE_LINT1_PASS, 1);
3405 Ivrs.IvhdType10IoApic.u.special.u8Handle = pThis->cCpus; /* The I/O APIC ID, see u8IOApicId in acpiR3SetupMadt(). */
3406 Ivrs.IvhdType10IoApic.u.special.u16DevIdB = VBOX_PCI_BDF_SB_IOAPIC;
3407 Ivrs.IvhdType10IoApic.u.special.u8Variety = ACPI_IVHD_VARIETY_IOAPIC;
3408
3409 /* HPET special device entry. */
3410 Ivrs.IvhdType10Hpet.u8DevEntryType = 0x48;
3411 Ivrs.IvhdType10Hpet.u.special.u16Rsvd0 = 0;
3412 Ivrs.IvhdType10Hpet.u.special.u8DteSetting = 0;
3413 Ivrs.IvhdType10Hpet.u.special.u8Handle = 0; /* HPET number. ASSUMING it's identical to u32Number in acpiR3SetupHpet(). */
3414 Ivrs.IvhdType10Hpet.u.special.u16DevIdB = VBOX_PCI_BDF_SB_IOAPIC; /* HPET goes through the I/O APIC. */
3415 Ivrs.IvhdType10Hpet.u.special.u8Variety = ACPI_IVHD_VARIETY_HPET;
3416
3417 /* IVHD type 11 definition block. */
3418 Ivrs.IvhdType11.u8Type = 0x11;
3419 Ivrs.IvhdType11.u16Length = sizeof(Ivrs.IvhdType11)
3420 + sizeof(Ivrs.IvhdType11Start)
3421 + sizeof(Ivrs.IvhdType11End)
3422 + sizeof(Ivrs.IvhdType11Rsvd0)
3423 + sizeof(Ivrs.IvhdType11Rsvd1)
3424 + sizeof(Ivrs.IvhdType11IoApic)
3425 + sizeof(Ivrs.IvhdType11Hpet);
3426 Ivrs.IvhdType11.u16DeviceId = Ivrs.IvhdType10.u16DeviceId;
3427 Ivrs.IvhdType11.u16CapOffset = Ivrs.IvhdType10.u16CapOffset;
3428 Ivrs.IvhdType11.u64BaseAddress = Ivrs.IvhdType10.u64BaseAddress;
3429 Ivrs.IvhdType11.u16PciSegmentGroup = Ivrs.IvhdType10.u16PciSegmentGroup;
3430 Ivrs.IvhdType11.u8Flags = ACPI_IVHD_11H_F_COHERENT;
3431 Ivrs.IvhdType11.u16IommuInfo = Ivrs.IvhdType10.u16IommuInfo;
3432 Ivrs.IvhdType11.u32IommuAttr = RT_BF_MAKE(ACPI_IOMMU_ATTR_BF_PN_COUNTERS, 0)
3433 | RT_BF_MAKE(ACPI_IOMMU_ATTR_BF_PN_BANKS, 0)
3434 | RT_BF_MAKE(ACPI_IOMMU_ATTR_BF_MSI_NUM_PPR, 0);
3435 /* NOTE! The feature bits below must match the IOMMU device code (MMIO/PCI access of the EFR register). */
3436 Ivrs.IvhdType11.u64EfrRegister = RT_BF_MAKE(IOMMU_EXT_FEAT_BF_PREF_SUP, 0)
3437 | RT_BF_MAKE(IOMMU_EXT_FEAT_BF_PPR_SUP, 0)
3438 | RT_BF_MAKE(IOMMU_EXT_FEAT_BF_X2APIC_SUP, 0)
3439 | RT_BF_MAKE(IOMMU_EXT_FEAT_BF_NO_EXEC_SUP, 0)
3440 | RT_BF_MAKE(IOMMU_EXT_FEAT_BF_GT_SUP, 0)
3441 | RT_BF_MAKE(IOMMU_EXT_FEAT_BF_IA_SUP, 1)
3442 | RT_BF_MAKE(IOMMU_EXT_FEAT_BF_GA_SUP, 0)
3443 | RT_BF_MAKE(IOMMU_EXT_FEAT_BF_HE_SUP, 1)
3444 | RT_BF_MAKE(IOMMU_EXT_FEAT_BF_PC_SUP, 0)
3445 | RT_BF_MAKE(IOMMU_EXT_FEAT_BF_HATS, IOMMU_MAX_HOST_PT_LEVEL & 3)
3446 | RT_BF_MAKE(IOMMU_EXT_FEAT_BF_GATS, 0)
3447 | RT_BF_MAKE(IOMMU_EXT_FEAT_BF_GLX_SUP, 0)
3448 | RT_BF_MAKE(IOMMU_EXT_FEAT_BF_SMI_FLT_SUP, 0)
3449 | RT_BF_MAKE(IOMMU_EXT_FEAT_BF_SMI_FLT_REG_CNT, 0)
3450 | RT_BF_MAKE(IOMMU_EXT_FEAT_BF_GAM_SUP, 0)
3451 | RT_BF_MAKE(IOMMU_EXT_FEAT_BF_DUAL_PPR_LOG_SUP, 0)
3452 | RT_BF_MAKE(IOMMU_EXT_FEAT_BF_DUAL_EVT_LOG_SUP, 0)
3453 | RT_BF_MAKE(IOMMU_EXT_FEAT_BF_PASID_MAX, 0)
3454 | RT_BF_MAKE(IOMMU_EXT_FEAT_BF_US_SUP, 0)
3455 | RT_BF_MAKE(IOMMU_EXT_FEAT_BF_DEV_TBL_SEG_SUP, IOMMU_MAX_DEV_TAB_SEGMENTS)
3456 | RT_BF_MAKE(IOMMU_EXT_FEAT_BF_PPR_OVERFLOW_EARLY, 0)
3457 | RT_BF_MAKE(IOMMU_EXT_FEAT_BF_PPR_AUTO_RES_SUP, 0)
3458 | RT_BF_MAKE(IOMMU_EXT_FEAT_BF_MARC_SUP, 0)
3459 | RT_BF_MAKE(IOMMU_EXT_FEAT_BF_BLKSTOP_MARK_SUP, 0)
3460 | RT_BF_MAKE(IOMMU_EXT_FEAT_BF_PERF_OPT_SUP, 0)
3461 | RT_BF_MAKE(IOMMU_EXT_FEAT_BF_MSI_CAP_MMIO_SUP, 1)
3462 | RT_BF_MAKE(IOMMU_EXT_FEAT_BF_GST_IO_PROT_SUP, 0)
3463 | RT_BF_MAKE(IOMMU_EXT_FEAT_BF_HST_ACCESS_SUP, 0)
3464 | RT_BF_MAKE(IOMMU_EXT_FEAT_BF_ENHANCED_PPR_SUP, 0)
3465 | RT_BF_MAKE(IOMMU_EXT_FEAT_BF_ATTR_FW_SUP, 0)
3466 | RT_BF_MAKE(IOMMU_EXT_FEAT_BF_HST_DIRTY_SUP, 0)
3467 | RT_BF_MAKE(IOMMU_EXT_FEAT_BF_INV_IOTLB_TYPE_SUP, 0)
3468 | RT_BF_MAKE(IOMMU_EXT_FEAT_BF_GA_UPDATE_DIS_SUP, 0)
3469 | RT_BF_MAKE(IOMMU_EXT_FEAT_BF_FORCE_PHYS_DST_SUP, 0);
3470
3471 /* The IVHD type 11 entries can be copied from their type 10 counterparts. */
3472 Ivrs.IvhdType11Start = Ivrs.IvhdType10Start;
3473 Ivrs.IvhdType11End = Ivrs.IvhdType10End;
3474 Ivrs.IvhdType11Rsvd0 = Ivrs.IvhdType10Rsvd0;
3475 Ivrs.IvhdType11Rsvd1 = Ivrs.IvhdType10Rsvd1;
3476 Ivrs.IvhdType11IoApic = Ivrs.IvhdType10IoApic;
3477 Ivrs.IvhdType11Hpet = Ivrs.IvhdType10Hpet;
3478
3479 /* Finally, compute checksum. */
3480 Ivrs.Hdr.header.u8Checksum = acpiR3Checksum(&Ivrs, sizeof(Ivrs));
3481
3482 /* Plant the ACPI table. */
3483 acpiR3PhysCopy(pDevIns, addr, (const uint8_t *)&Ivrs, sizeof(Ivrs));
3484}
3485#endif /* VBOX_WITH_IOMMU_AMD */
3486
3487
3488#ifdef VBOX_WITH_IOMMU_INTEL
3489/**
3490 * Plant the Intel IOMMU (VT-d) descriptor.
3491 */
3492static void acpiR3SetupIommuIntel(PPDMDEVINS pDevIns, PACPISTATE pThis, RTGCPHYS32 addr)
3493{
3494 ACPITBLVTD VtdTable;
3495 RT_ZERO(VtdTable);
3496
3497 /* VT-d Table. */
3498 acpiR3PrepareHeader(pThis, &VtdTable.Dmar.Hdr, "DMAR", sizeof(ACPITBLVTD), ACPI_DMAR_REVISION);
3499
3500 /* DMAR. */
3501 uint8_t cPhysAddrBits;
3502 uint8_t cLinearAddrBits;
3503 PDMDevHlpCpuGetGuestAddrWidths(pDevIns, &cPhysAddrBits, &cLinearAddrBits);
3504 Assert(cPhysAddrBits > 0); NOREF(cLinearAddrBits);
3505 VtdTable.Dmar.uHostAddrWidth = cPhysAddrBits - 1;
3506 VtdTable.Dmar.fFlags = DMAR_ACPI_DMAR_FLAGS;
3507
3508 /* DRHD. */
3509 VtdTable.Drhd.cbLength = sizeof(ACPIDRHD);
3510 VtdTable.Drhd.fFlags = ACPI_DRHD_F_INCLUDE_PCI_ALL;
3511 VtdTable.Drhd.uRegBaseAddr = DMAR_MMIO_BASE_PHYSADDR;
3512
3513 /* Device Scopes: I/O APIC. */
3514 if (pThis->u8UseIOApic)
3515 {
3516 uint8_t const uIoApicBus = 0;
3517 uint8_t const uIoApicDev = RT_HI_U16(pThis->u32SbIoApicPciAddress);
3518 uint8_t const uIoApicFn = RT_LO_U16(pThis->u32SbIoApicPciAddress);
3519
3520 VtdTable.DevScopeIoApic.uType = ACPIDMARDEVSCOPE_TYPE_IOAPIC;
3521 VtdTable.DevScopeIoApic.cbLength = sizeof(ACPIDMARDEVSCOPE);
3522 VtdTable.DevScopeIoApic.idEnum = pThis->cCpus; /* The I/O APIC ID, see u8IOApicId in acpiR3SetupMadt(). */
3523 VtdTable.DevScopeIoApic.uStartBusNum = uIoApicBus;
3524 VtdTable.DevScopeIoApic.Path.uDevice = uIoApicDev;
3525 VtdTable.DevScopeIoApic.Path.uFunction = uIoApicFn;
3526
3527 VtdTable.Drhd.cbLength += sizeof(VtdTable.DevScopeIoApic);
3528 }
3529
3530 /* Finally, compute checksum. */
3531 VtdTable.Dmar.Hdr.u8Checksum = acpiR3Checksum(&VtdTable, sizeof(VtdTable));
3532
3533 /* Plant the ACPI table. */
3534 acpiR3PhysCopy(pDevIns, addr, (const uint8_t *)&VtdTable, sizeof(VtdTable));
3535}
3536#endif /* VBOX_WITH_IOMMU_INTEL */
3537
3538
3539#ifdef VBOX_WITH_TPM
3540/**
3541 * Plant the TPM 2.0 ACPI descriptor.
3542 */
3543static void acpiR3SetupTpm(PPDMDEVINS pDevIns, PACPISTATE pThis, RTGCPHYS32 addr)
3544{
3545 if (pThis->enmTpmMode == ACPITPMMODE_TIS_1_2)
3546 {
3547 ACPITBLTCPA TcpaTbl;
3548 RT_ZERO(TcpaTbl);
3549
3550 acpiR3PrepareHeader(pThis, &TcpaTbl.Hdr, "TCPA", sizeof(TcpaTbl), ACPI_TCPA_REVISION);
3551
3552 TcpaTbl.u16PlatCls = ACPI_TCPA_PLAT_CLS_CLIENT;
3553 TcpaTbl.u32Laml = ACPI_TCPA_LAML_SZ;
3554 TcpaTbl.u64Lasa = addr + sizeof(TcpaTbl);
3555
3556 /* Finally, compute checksum. */
3557 TcpaTbl.Hdr.u8Checksum = acpiR3Checksum(&TcpaTbl, sizeof(TcpaTbl));
3558
3559 /* Plant the ACPI table. */
3560 acpiR3PhysCopy(pDevIns, addr, (const uint8_t *)&TcpaTbl, sizeof(TcpaTbl));
3561 }
3562 else
3563 {
3564 ACPITBLTPM20 Tpm2Tbl;
3565 RT_ZERO(Tpm2Tbl);
3566
3567 acpiR3PrepareHeader(pThis, &Tpm2Tbl.Hdr, "TPM2", sizeof(ACPITBLTPM20), ACPI_TPM20_REVISION);
3568
3569 switch (pThis->enmTpmMode)
3570 {
3571 case ACPITPMMODE_CRB_2_0:
3572 Tpm2Tbl.u32StartMethod = ACPITBL_TPM20_START_METHOD_CRB;
3573 Tpm2Tbl.u64BaseAddrCrbOrFifo = pThis->GCPhysTpmMmio;
3574 break;
3575 case ACPITPMMODE_FIFO_2_0:
3576 Tpm2Tbl.u32StartMethod = ACPITBL_TPM20_START_METHOD_TIS12;
3577 break;
3578 case ACPITPMMODE_TIS_1_2: /* Handled above. */
3579 case ACPITPMMODE_DISABLED: /* Should never be called with the TPM disabled. */
3580 default:
3581 AssertFailed();
3582 }
3583
3584 Tpm2Tbl.u16PlatCls = ACPITBL_TPM20_PLAT_CLS_CLIENT;
3585
3586 /* Finally, compute checksum. */
3587 Tpm2Tbl.Hdr.u8Checksum = acpiR3Checksum(&Tpm2Tbl, sizeof(Tpm2Tbl));
3588
3589 /* Plant the ACPI table. */
3590 acpiR3PhysCopy(pDevIns, addr, (const uint8_t *)&Tpm2Tbl, sizeof(Tpm2Tbl));
3591 }
3592}
3593#endif
3594
3595
3596/**
3597 * Used by acpiR3PlantTables to plant a MMCONFIG PCI config space access (MCFG)
3598 * descriptor.
3599 *
3600 * @param pDevIns The device instance.
3601 * @param pThis The ACPI shared instance data.
3602 * @param GCPhysDst Where to plant it.
3603 */
3604static void acpiR3SetupMcfg(PPDMDEVINS pDevIns, PACPISTATE pThis, RTGCPHYS32 GCPhysDst)
3605{
3606 struct
3607 {
3608 ACPITBLMCFG hdr;
3609 ACPITBLMCFGENTRY entry;
3610 } tbl;
3611 uint8_t u8StartBus = 0;
3612 uint8_t u8EndBus = (pThis->u64PciConfigMMioLength >> 20) - 1;
3613
3614 RT_ZERO(tbl);
3615
3616 acpiR3PrepareHeader(pThis, &tbl.hdr.aHeader, "MCFG", sizeof(tbl), 1);
3617 tbl.entry.u64BaseAddress = pThis->u64PciConfigMMioAddress;
3618 tbl.entry.u8StartBus = u8StartBus;
3619 tbl.entry.u8EndBus = u8EndBus;
3620 // u16PciSegmentGroup must match _SEG in ACPI table
3621
3622 tbl.hdr.aHeader.u8Checksum = acpiR3Checksum(&tbl, sizeof(tbl));
3623
3624 acpiR3PhysCopy(pDevIns, GCPhysDst, (const uint8_t *)&tbl, sizeof(tbl));
3625}
3626
3627/**
3628 * Used by acpiR3PlantTables and acpiConstruct.
3629 *
3630 * @returns Guest memory address.
3631 */
3632static uint32_t apicR3FindRsdpSpace(void)
3633{
3634 return 0xe0000;
3635}
3636
3637/**
3638 * Called by acpiR3Construct to read and allocate a custom ACPI table
3639 *
3640 * @param pDevIns The device instance.
3641 * @param ppu8CustBin Address to receive the address of the table
3642 * @param pcbCustBin Address to receive the size of the the table.
3643 * @param pszCustBinFile
3644 * @param cbBufAvail Maximum space in bytes available for the custom
3645 * table (including header).
3646 */
3647static int acpiR3ReadCustomTable(PPDMDEVINS pDevIns, uint8_t **ppu8CustBin, uint64_t *pcbCustBin,
3648 char *pszCustBinFile, uint32_t cbBufAvail)
3649{
3650 RTFILE FileCUSTBin;
3651 int rc = RTFileOpen(&FileCUSTBin, pszCustBinFile,
3652 RTFILE_O_READ | RTFILE_O_OPEN | RTFILE_O_DENY_WRITE);
3653 if (RT_SUCCESS(rc))
3654 {
3655 rc = RTFileQuerySize(FileCUSTBin, pcbCustBin);
3656 if (RT_SUCCESS(rc))
3657 {
3658 /* The following checks should be in sync the AssertReleaseMsg's below. */
3659 if ( *pcbCustBin > cbBufAvail
3660 || *pcbCustBin < sizeof(ACPITBLHEADER))
3661 rc = VERR_TOO_MUCH_DATA;
3662
3663 /*
3664 * Allocate buffer for the custom table binary data.
3665 */
3666 *ppu8CustBin = (uint8_t *)PDMDevHlpMMHeapAlloc(pDevIns, *pcbCustBin);
3667 if (*ppu8CustBin)
3668 {
3669 rc = RTFileRead(FileCUSTBin, *ppu8CustBin, *pcbCustBin, NULL);
3670 if (RT_FAILURE(rc))
3671 {
3672 AssertMsgFailed(("RTFileRead(,,%d,NULL) -> %Rrc\n", *pcbCustBin, rc));
3673 PDMDevHlpMMHeapFree(pDevIns, *ppu8CustBin);
3674 *ppu8CustBin = NULL;
3675 }
3676 }
3677 else
3678 {
3679 rc = VERR_NO_MEMORY;
3680 }
3681 RTFileClose(FileCUSTBin);
3682 }
3683 }
3684 return rc;
3685}
3686
3687/**
3688 * Create the ACPI tables in guest memory.
3689 */
3690static int acpiR3PlantTables(PPDMDEVINS pDevIns, PACPISTATE pThis, PACPISTATER3 pThisCC)
3691{
3692 int rc;
3693 RTGCPHYS32 GCPhysCur, GCPhysRsdt, GCPhysXsdt, GCPhysFadtAcpi1, GCPhysFadtAcpi2, GCPhysFacs, GCPhysDsdt;
3694 RTGCPHYS32 GCPhysHpet = 0;
3695#if defined(VBOX_WITH_IOMMU_AMD) || defined(VBOX_WITH_IOMMU_INTEL)
3696 RTGCPHYS32 GCPhysIommu = 0;
3697#endif
3698#ifdef VBOX_WITH_TPM
3699 RTGCPHYS32 GCPhysTpm = 0;
3700 RTGCPHYS32 GCPhysSsdtTpm = 0;
3701#endif
3702 RTGCPHYS32 GCPhysApic = 0;
3703 RTGCPHYS32 GCPhysSsdt = 0;
3704 RTGCPHYS32 GCPhysMcfg = 0;
3705 RTGCPHYS32 aGCPhysCust[MAX_CUST_TABLES] = {0};
3706 uint32_t addend = 0;
3707#if defined(VBOX_WITH_IOMMU_AMD) || defined(VBOX_WITH_IOMMU_INTEL)
3708# ifdef VBOX_WITH_TPM
3709 RTGCPHYS32 aGCPhysRsdt[10 + MAX_CUST_TABLES];
3710 RTGCPHYS32 aGCPhysXsdt[10 + MAX_CUST_TABLES];
3711# else
3712 RTGCPHYS32 aGCPhysRsdt[8 + MAX_CUST_TABLES];
3713 RTGCPHYS32 aGCPhysXsdt[8 + MAX_CUST_TABLES];
3714# endif
3715#else
3716# ifdef VBOX_WITH_TPM
3717 RTGCPHYS32 aGCPhysRsdt[9 + MAX_CUST_TABLES];
3718 RTGCPHYS32 aGCPhysXsdt[9 + MAX_CUST_TABLES];
3719# else
3720 RTGCPHYS32 aGCPhysRsdt[7 + MAX_CUST_TABLES];
3721 RTGCPHYS32 aGCPhysXsdt[7 + MAX_CUST_TABLES];
3722# endif
3723#endif
3724 uint32_t cAddr;
3725 uint32_t iMadt = 0;
3726 uint32_t iHpet = 0;
3727#if defined(VBOX_WITH_IOMMU_AMD) || defined(VBOX_WITH_IOMMU_INTEL)
3728 uint32_t iIommu = 0;
3729#endif
3730#ifdef VBOX_WITH_TPM
3731 uint32_t iTpm = 0;
3732 uint32_t iSsdtTpm = 0;
3733#endif
3734 uint32_t iSsdt = 0;
3735 uint32_t iMcfg = 0;
3736 uint32_t iCust = 0;
3737 size_t cbRsdt = sizeof(ACPITBLHEADER);
3738 size_t cbXsdt = sizeof(ACPITBLHEADER);
3739
3740 cAddr = 1; /* FADT */
3741 if (pThis->u8UseIOApic)
3742 iMadt = cAddr++; /* MADT */
3743
3744 if (pThis->fUseHpet)
3745 iHpet = cAddr++; /* HPET */
3746
3747#ifdef VBOX_WITH_IOMMU_AMD
3748 if (pThis->fUseIommuAmd)
3749 iIommu = cAddr++; /* IOMMU (AMD) */
3750#endif
3751
3752#ifdef VBOX_WITH_IOMMU_INTEL
3753 if (pThis->fUseIommuIntel)
3754 iIommu = cAddr++; /* IOMMU (Intel) */
3755#endif
3756
3757#ifdef VBOX_WITH_TPM
3758 if (pThis->enmTpmMode != ACPITPMMODE_DISABLED)
3759 {
3760 iTpm = cAddr++; /* TPM device */
3761 iSsdtTpm = cAddr++;
3762 }
3763#endif
3764
3765 if (pThis->fUseMcfg)
3766 iMcfg = cAddr++; /* MCFG */
3767
3768 if (pThis->cCustTbls > 0)
3769 {
3770 iCust = cAddr; /* CUST */
3771 cAddr += pThis->cCustTbls;
3772 }
3773
3774 iSsdt = cAddr++; /* SSDT */
3775
3776 Assert(cAddr < RT_ELEMENTS(aGCPhysRsdt));
3777 Assert(cAddr < RT_ELEMENTS(aGCPhysXsdt));
3778
3779 cbRsdt += cAddr * sizeof(uint32_t); /* each entry: 32 bits phys. address. */
3780 cbXsdt += cAddr * sizeof(uint64_t); /* each entry: 64 bits phys. address. */
3781
3782 /*
3783 * Calculate the sizes for the low region and for the 64-bit prefetchable memory.
3784 * The latter starts never below 4G.
3785 */
3786 uint32_t cbBelow4GB = PDMDevHlpMMPhysGetRamSizeBelow4GB(pDevIns);
3787 uint64_t const cbAbove4GB = PDMDevHlpMMPhysGetRamSizeAbove4GB(pDevIns);
3788
3789 pThis->u64RamSize = PDMDevHlpMMPhysGetRamSize(pDevIns);
3790 if (pThis->fPciPref64Enabled)
3791 {
3792 uint64_t const u64PciPref64Min = _4G + cbAbove4GB;
3793 if (pThis->u64PciPref64Max > u64PciPref64Min)
3794 {
3795 /* Activate MEM4. See also DevPciIch9.cpp / ich9pciFakePCIBIOS() / uPciBiosMmio64 */
3796 pThis->u64PciPref64Min = u64PciPref64Min;
3797 LogRel(("ACPI: Enabling 64-bit prefetch root bus resource %#018RX64..%#018RX64\n",
3798 u64PciPref64Min, pThis->u64PciPref64Max-1));
3799 }
3800 else
3801 LogRel(("ACPI: NOT enabling 64-bit prefetch root bus resource (min/%#018RX64 >= max/%#018RX64)\n",
3802 u64PciPref64Min, pThis->u64PciPref64Max-1));
3803 }
3804 if (cbBelow4GB > UINT32_C(0xfe000000)) /* See MEM3. */
3805 {
3806 /* Note: This is also enforced by DevPcBios.cpp. */
3807 LogRel(("ACPI: Clipping cbRamLow=%#RX64 down to 0xfe000000.\n", cbBelow4GB));
3808 cbBelow4GB = UINT32_C(0xfe000000);
3809 }
3810 pThis->cbRamLow = cbBelow4GB;
3811
3812 GCPhysCur = 0;
3813 GCPhysRsdt = GCPhysCur;
3814
3815 GCPhysCur = RT_ALIGN_32(GCPhysCur + cbRsdt, 16);
3816 GCPhysXsdt = GCPhysCur;
3817
3818 GCPhysCur = RT_ALIGN_32(GCPhysCur + cbXsdt, 16);
3819 GCPhysFadtAcpi1 = GCPhysCur;
3820
3821 GCPhysCur = RT_ALIGN_32(GCPhysCur + ACPITBLFADT_VERSION1_SIZE, 16);
3822 GCPhysFadtAcpi2 = GCPhysCur;
3823
3824 GCPhysCur = RT_ALIGN_32(GCPhysCur + sizeof(ACPITBLFADT), 64);
3825 GCPhysFacs = GCPhysCur;
3826
3827 GCPhysCur = RT_ALIGN_32(GCPhysCur + sizeof(ACPITBLFACS), 16);
3828 if (pThis->u8UseIOApic)
3829 {
3830 GCPhysApic = GCPhysCur;
3831 GCPhysCur = RT_ALIGN_32(GCPhysCur + AcpiTableMadt::sizeFor(pThis, NUMBER_OF_IRQ_SOURCE_OVERRIDES), 16);
3832 }
3833 if (pThis->fUseHpet)
3834 {
3835 GCPhysHpet = GCPhysCur;
3836 GCPhysCur = RT_ALIGN_32(GCPhysCur + sizeof(ACPITBLHPET), 16);
3837 }
3838#ifdef VBOX_WITH_IOMMU_AMD
3839 if (pThis->fUseIommuAmd)
3840 {
3841 GCPhysIommu = GCPhysCur;
3842 GCPhysCur = RT_ALIGN_32(GCPhysCur + sizeof(ACPITBLIOMMU), 16);
3843 }
3844#endif
3845#ifdef VBOX_WITH_IOMMU_INTEL
3846 if (pThis->fUseIommuIntel)
3847 {
3848 GCPhysIommu = GCPhysCur;
3849 GCPhysCur = RT_ALIGN_32(GCPhysCur + sizeof(ACPITBLVTD), 16);
3850 }
3851#endif
3852#ifdef VBOX_WITH_TPM
3853 void *pvSsdtTpmCode = NULL;
3854 size_t cbSsdtTpm = 0;
3855
3856 if (pThis->enmTpmMode != ACPITPMMODE_DISABLED)
3857 {
3858 GCPhysTpm = GCPhysCur;
3859
3860 if (pThis->enmTpmMode == ACPITPMMODE_TIS_1_2)
3861 GCPhysCur = RT_ALIGN_32(GCPhysCur + sizeof(ACPITBLTCPA) + ACPI_TCPA_LAML_SZ, 16);
3862 else
3863 GCPhysCur = RT_ALIGN_32(GCPhysCur + sizeof(ACPITBLTPM20), 16);
3864
3865 rc = acpiPrepareTpmSsdt(pDevIns, &pvSsdtTpmCode, &cbSsdtTpm);
3866 if (RT_FAILURE(rc))
3867 return rc;
3868
3869 GCPhysSsdtTpm = GCPhysCur;
3870 GCPhysCur = RT_ALIGN_32(GCPhysCur + cbSsdtTpm, 16);
3871 }
3872#endif
3873
3874 if (pThis->fUseMcfg)
3875 {
3876 GCPhysMcfg = GCPhysCur;
3877 /* Assume one entry */
3878 GCPhysCur = RT_ALIGN_32(GCPhysCur + sizeof(ACPITBLMCFG) + sizeof(ACPITBLMCFGENTRY), 16);
3879 }
3880
3881 for (uint8_t i = 0; i < pThis->cCustTbls; i++)
3882 {
3883 aGCPhysCust[i] = GCPhysCur;
3884 GCPhysCur = RT_ALIGN_32(GCPhysCur + pThisCC->acbCustBin[i], 16);
3885 }
3886
3887 void *pvSsdtCode = NULL;
3888 size_t cbSsdt = 0;
3889 rc = acpiPrepareSsdt(pDevIns, &pvSsdtCode, &cbSsdt);
3890 if (RT_FAILURE(rc))
3891 return rc;
3892
3893 GCPhysSsdt = GCPhysCur;
3894 GCPhysCur = RT_ALIGN_32(GCPhysCur + cbSsdt, 16);
3895
3896 GCPhysDsdt = GCPhysCur;
3897
3898 void *pvDsdtCode = NULL;
3899 size_t cbDsdt = 0;
3900 rc = acpiPrepareDsdt(pDevIns, &pvDsdtCode, &cbDsdt);
3901 if (RT_FAILURE(rc))
3902 return rc;
3903
3904 GCPhysCur = RT_ALIGN_32(GCPhysCur + cbDsdt, 16);
3905
3906 if (GCPhysCur > 0x10000)
3907 return PDMDEV_SET_ERROR(pDevIns, VERR_TOO_MUCH_DATA,
3908 N_("Error: ACPI tables bigger than 64KB"));
3909
3910 Log(("RSDP 0x%08X\n", apicR3FindRsdpSpace()));
3911 addend = pThis->cbRamLow - 0x10000;
3912 Log(("RSDT 0x%08X XSDT 0x%08X\n", GCPhysRsdt + addend, GCPhysXsdt + addend));
3913 Log(("FACS 0x%08X FADT (1.0) 0x%08X, FADT (2+) 0x%08X\n", GCPhysFacs + addend, GCPhysFadtAcpi1 + addend, GCPhysFadtAcpi2 + addend));
3914 Log(("DSDT 0x%08X", GCPhysDsdt + addend));
3915 if (pThis->u8UseIOApic)
3916 Log((" MADT 0x%08X", GCPhysApic + addend));
3917 if (pThis->fUseHpet)
3918 Log((" HPET 0x%08X", GCPhysHpet + addend));
3919 if (pThis->fUseMcfg)
3920 Log((" MCFG 0x%08X", GCPhysMcfg + addend));
3921 for (uint8_t i = 0; i < pThis->cCustTbls; i++)
3922 Log((" CUST(%d) 0x%08X", i, aGCPhysCust[i] + addend));
3923 Log((" SSDT 0x%08X", GCPhysSsdt + addend));
3924 Log(("\n"));
3925
3926 acpiR3SetupRsdp(pThis, (ACPITBLRSDP *)pThis->au8RSDPPage, GCPhysRsdt + addend, GCPhysXsdt + addend);
3927 acpiR3SetupDsdt(pDevIns, GCPhysDsdt + addend, pvDsdtCode, cbDsdt);
3928 acpiCleanupDsdt(pDevIns, pvDsdtCode);
3929 acpiR3SetupFacs(pDevIns, GCPhysFacs + addend);
3930 acpiR3SetupFadt(pDevIns, pThis, GCPhysFadtAcpi1 + addend, GCPhysFadtAcpi2 + addend, GCPhysFacs + addend, GCPhysDsdt + addend);
3931
3932 aGCPhysRsdt[0] = GCPhysFadtAcpi1 + addend;
3933 aGCPhysXsdt[0] = GCPhysFadtAcpi2 + addend;
3934 if (pThis->u8UseIOApic)
3935 {
3936 acpiR3SetupMadt(pDevIns, pThis, GCPhysApic + addend);
3937 aGCPhysRsdt[iMadt] = GCPhysApic + addend;
3938 aGCPhysXsdt[iMadt] = GCPhysApic + addend;
3939 }
3940 if (pThis->fUseHpet)
3941 {
3942 acpiR3SetupHpet(pDevIns, pThis, GCPhysHpet + addend);
3943 aGCPhysRsdt[iHpet] = GCPhysHpet + addend;
3944 aGCPhysXsdt[iHpet] = GCPhysHpet + addend;
3945 }
3946#ifdef VBOX_WITH_IOMMU_AMD
3947 if (pThis->fUseIommuAmd)
3948 {
3949 acpiR3SetupIommuAmd(pDevIns, pThis, GCPhysIommu + addend);
3950 aGCPhysRsdt[iIommu] = GCPhysIommu + addend;
3951 aGCPhysXsdt[iIommu] = GCPhysIommu + addend;
3952 }
3953#endif
3954#ifdef VBOX_WITH_IOMMU_INTEL
3955 if (pThis->fUseIommuIntel)
3956 {
3957 acpiR3SetupIommuIntel(pDevIns, pThis, GCPhysIommu + addend);
3958 aGCPhysRsdt[iIommu] = GCPhysIommu + addend;
3959 aGCPhysXsdt[iIommu] = GCPhysIommu + addend;
3960 }
3961#endif
3962#ifdef VBOX_WITH_TPM
3963 if (pThis->enmTpmMode != ACPITPMMODE_DISABLED)
3964 {
3965 acpiR3SetupTpm(pDevIns, pThis, GCPhysTpm + addend);
3966 aGCPhysRsdt[iTpm] = GCPhysTpm + addend;
3967 aGCPhysXsdt[iTpm] = GCPhysTpm + addend;
3968
3969 acpiR3SetupTpmSsdt(pDevIns, GCPhysSsdtTpm + addend, pvSsdtTpmCode, cbSsdtTpm);
3970 acpiCleanupTpmSsdt(pDevIns, pvSsdtTpmCode);
3971 aGCPhysRsdt[iSsdtTpm] = GCPhysSsdtTpm + addend;
3972 aGCPhysXsdt[iSsdtTpm] = GCPhysSsdtTpm + addend;
3973 }
3974#endif
3975
3976 if (pThis->fUseMcfg)
3977 {
3978 acpiR3SetupMcfg(pDevIns, pThis, GCPhysMcfg + addend);
3979 aGCPhysRsdt[iMcfg] = GCPhysMcfg + addend;
3980 aGCPhysXsdt[iMcfg] = GCPhysMcfg + addend;
3981 }
3982 for (uint8_t i = 0; i < pThis->cCustTbls; i++)
3983 {
3984 AssertBreak(i < MAX_CUST_TABLES);
3985 acpiR3PhysCopy(pDevIns, aGCPhysCust[i] + addend, pThisCC->apu8CustBin[i], pThisCC->acbCustBin[i]);
3986 aGCPhysRsdt[iCust + i] = aGCPhysCust[i] + addend;
3987 aGCPhysXsdt[iCust + i] = aGCPhysCust[i] + addend;
3988 uint8_t* pSig = pThisCC->apu8CustBin[i];
3989 LogRel(("ACPI: Planted custom table '%c%c%c%c' at 0x%08X\n",
3990 pSig[0], pSig[1], pSig[2], pSig[3], aGCPhysCust[i] + addend));
3991 }
3992
3993 acpiR3SetupSsdt(pDevIns, GCPhysSsdt + addend, pvSsdtCode, cbSsdt);
3994 acpiCleanupSsdt(pDevIns, pvSsdtCode);
3995 aGCPhysRsdt[iSsdt] = GCPhysSsdt + addend;
3996 aGCPhysXsdt[iSsdt] = GCPhysSsdt + addend;
3997
3998 rc = acpiR3SetupRsdt(pDevIns, pThis, GCPhysRsdt + addend, cAddr, aGCPhysRsdt);
3999 if (RT_FAILURE(rc))
4000 return rc;
4001 return acpiR3SetupXsdt(pDevIns, pThis, GCPhysXsdt + addend, cAddr, aGCPhysXsdt);
4002}
4003
4004/**
4005 * @callback_method_impl{FNPCICONFIGREAD}
4006 */
4007static DECLCALLBACK(VBOXSTRICTRC) acpiR3PciConfigRead(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev,
4008 uint32_t uAddress, unsigned cb, uint32_t *pu32Value)
4009{
4010 VBOXSTRICTRC rcStrict = PDMDevHlpPCIConfigRead(pDevIns, pPciDev, uAddress, cb, pu32Value);
4011 Log2(("acpi: PCI config read: %#x (%d) -> %#x %Rrc\n", uAddress, cb, *pu32Value, VBOXSTRICTRC_VAL(rcStrict)));
4012 return rcStrict;
4013}
4014
4015/**
4016 * @callback_method_impl{FNPCICONFIGWRITE}
4017 */
4018static DECLCALLBACK(VBOXSTRICTRC) acpiR3PciConfigWrite(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev,
4019 uint32_t uAddress, unsigned cb, uint32_t u32Value)
4020{
4021 PACPISTATE pThis = PDMDEVINS_2_DATA(pDevIns, PACPISTATE);
4022 PACPISTATER3 pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PACPISTATER3);
4023
4024 Log2(("acpi: PCI config write: 0x%x -> 0x%x (%d)\n", u32Value, uAddress, cb));
4025 DEVACPI_LOCK_R3(pDevIns, pThis);
4026
4027 if (uAddress == VBOX_PCI_INTERRUPT_LINE)
4028 {
4029 Log(("acpi: ignore interrupt line settings: %d, we'll use hardcoded value %d\n", u32Value, SCI_INT));
4030 u32Value = SCI_INT;
4031 }
4032
4033 VBOXSTRICTRC rcStrict = PDMDevHlpPCIConfigWrite(pDevIns, pPciDev, uAddress, cb, u32Value);
4034
4035 /* Assume that the base address is only changed when the corresponding
4036 * hardware functionality is disabled. The IO region is mapped when the
4037 * functionality is enabled by the guest. */
4038
4039 if (uAddress == PMREGMISC)
4040 {
4041 RTIOPORT NewIoPortBase = 0;
4042 /* Check Power Management IO Space Enable (PMIOSE) bit */
4043 if (pPciDev->abConfig[PMREGMISC] & 0x01)
4044 {
4045 NewIoPortBase = (RTIOPORT)PDMPciDevGetDWord(pPciDev, PMBA);
4046 NewIoPortBase &= 0xffc0;
4047 }
4048
4049 int rc = acpiR3UpdatePmHandlers(pDevIns, pThis, pThisCC, NewIoPortBase);
4050 AssertRC(rc);
4051 }
4052
4053 if (uAddress == SMBHSTCFG)
4054 {
4055 RTIOPORT NewIoPortBase = 0;
4056 /* Check SMBus Controller Host Interface Enable (SMB_HST_EN) bit */
4057 if (pPciDev->abConfig[SMBHSTCFG] & SMBHSTCFG_SMB_HST_EN)
4058 {
4059 NewIoPortBase = (RTIOPORT)PDMPciDevGetDWord(pPciDev, SMBBA);
4060 NewIoPortBase &= 0xfff0;
4061 }
4062
4063 int rc = acpiR3UpdateSMBusHandlers(pDevIns, pThis, NewIoPortBase);
4064 AssertRC(rc);
4065 }
4066
4067 DEVACPI_UNLOCK(pDevIns, pThis);
4068 return rcStrict;
4069}
4070
4071/**
4072 * Attach a new CPU.
4073 *
4074 * @returns VBox status code.
4075 * @param pDevIns The device instance.
4076 * @param iLUN The logical unit which is being attached.
4077 * @param fFlags Flags, combination of the PDMDEVATT_FLAGS_* \#defines.
4078 *
4079 * @remarks This code path is not used during construction.
4080 */
4081static DECLCALLBACK(int) acpiR3Attach(PPDMDEVINS pDevIns, unsigned iLUN, uint32_t fFlags)
4082{
4083 PACPISTATE pThis = PDMDEVINS_2_DATA(pDevIns, PACPISTATE);
4084 PACPISTATER3 pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PACPISTATER3);
4085 LogFlow(("acpiAttach: pDevIns=%p iLUN=%u fFlags=%#x\n", pDevIns, iLUN, fFlags));
4086
4087 AssertMsgReturn(!(fFlags & PDM_TACH_FLAGS_NOT_HOT_PLUG),
4088 ("Hot-plug flag is not set\n"),
4089 VERR_NOT_SUPPORTED);
4090 AssertReturn(iLUN < VMM_MAX_CPU_COUNT, VERR_PDM_NO_SUCH_LUN);
4091
4092 /* Check if it was already attached */
4093 int rc = VINF_SUCCESS;
4094 DEVACPI_LOCK_R3(pDevIns, pThis);
4095 if (!VMCPUSET_IS_PRESENT(&pThis->CpuSetAttached, iLUN))
4096 {
4097 PPDMIBASE IBaseTmp;
4098 rc = PDMDevHlpDriverAttach(pDevIns, iLUN, &pThisCC->IBase, &IBaseTmp, "ACPI CPU");
4099 if (RT_SUCCESS(rc))
4100 {
4101 /* Enable the CPU */
4102 VMCPUSET_ADD(&pThis->CpuSetAttached, iLUN);
4103
4104 /*
4105 * Lock the CPU because we don't know if the guest will use it or not.
4106 * Prevents ejection while the CPU is still used
4107 */
4108 VMCPUSET_ADD(&pThis->CpuSetLocked, iLUN);
4109 pThis->u32CpuEventType = CPU_EVENT_TYPE_ADD;
4110 pThis->u32CpuEvent = iLUN;
4111
4112 /* Notify the guest */
4113 apicR3UpdateGpe0(pDevIns, pThis, pThis->gpe0_sts | 0x2, pThis->gpe0_en);
4114 }
4115 }
4116 DEVACPI_UNLOCK(pDevIns, pThis);
4117 return rc;
4118}
4119
4120/**
4121 * Detach notification.
4122 *
4123 * @param pDevIns The device instance.
4124 * @param iLUN The logical unit which is being detached.
4125 * @param fFlags Flags, combination of the PDMDEVATT_FLAGS_* \#defines.
4126 */
4127static DECLCALLBACK(void) acpiR3Detach(PPDMDEVINS pDevIns, unsigned iLUN, uint32_t fFlags)
4128{
4129 PACPISTATE pThis = PDMDEVINS_2_DATA(pDevIns, PACPISTATE);
4130
4131 LogFlow(("acpiDetach: pDevIns=%p iLUN=%u fFlags=%#x\n", pDevIns, iLUN, fFlags));
4132
4133 AssertMsgReturnVoid(!(fFlags & PDM_TACH_FLAGS_NOT_HOT_PLUG),
4134 ("Hot-plug flag is not set\n"));
4135
4136 /* Check if it was already detached */
4137 DEVACPI_LOCK_R3(pDevIns, pThis);
4138 if (VMCPUSET_IS_PRESENT(&pThis->CpuSetAttached, iLUN))
4139 {
4140 if (!VMCPUSET_IS_PRESENT(&pThis->CpuSetLocked, iLUN))
4141 {
4142 /* Disable the CPU */
4143 VMCPUSET_DEL(&pThis->CpuSetAttached, iLUN);
4144 pThis->u32CpuEventType = CPU_EVENT_TYPE_REMOVE;
4145 pThis->u32CpuEvent = iLUN;
4146
4147 /* Notify the guest */
4148 apicR3UpdateGpe0(pDevIns, pThis, pThis->gpe0_sts | 0x2, pThis->gpe0_en);
4149 }
4150 else
4151 AssertMsgFailed(("CPU is still locked by the guest\n"));
4152 }
4153 DEVACPI_UNLOCK(pDevIns, pThis);
4154}
4155
4156/**
4157 * @interface_method_impl{PDMDEVREG,pfnResume}
4158 */
4159static DECLCALLBACK(void) acpiR3Resume(PPDMDEVINS pDevIns)
4160{
4161 PACPISTATE pThis = PDMDEVINS_2_DATA(pDevIns, PACPISTATE);
4162 if (pThis->fSetWakeupOnResume)
4163 {
4164 Log(("acpiResume: setting WAK_STS\n"));
4165 pThis->fSetWakeupOnResume = false;
4166 pThis->pm1a_sts |= WAK_STS;
4167 }
4168}
4169
4170/**
4171 * @interface_method_impl{PDMDEVREG,pfnMemSetup}
4172 */
4173static DECLCALLBACK(void) acpiR3MemSetup(PPDMDEVINS pDevIns, PDMDEVMEMSETUPCTX enmCtx)
4174{
4175 RT_NOREF(enmCtx);
4176 PACPISTATE pThis = PDMDEVINS_2_DATA(pDevIns, PACPISTATE);
4177 PACPISTATER3 pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PACPISTATER3);
4178 acpiR3PlantTables(pDevIns, pThis, pThisCC);
4179}
4180
4181/**
4182 * @interface_method_impl{PDMDEVREG,pfnReset}
4183 */
4184static DECLCALLBACK(void) acpiR3Reset(PPDMDEVINS pDevIns)
4185{
4186 PACPISTATE pThis = PDMDEVINS_2_DATA(pDevIns, PACPISTATE);
4187 PACPISTATER3 pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PACPISTATER3);
4188
4189 /* Play safe: make sure that the IRQ isn't stuck after a reset. */
4190 acpiSetIrq(pDevIns, 0);
4191
4192 PDMDevHlpTimerLockClock(pDevIns, pThis->hPmTimer, VERR_IGNORED);
4193 pThis->pm1a_en = 0;
4194 pThis->pm1a_sts = 0;
4195 pThis->pm1a_ctl = 0;
4196 pThis->u64PmTimerInitial = PDMDevHlpTimerGet(pDevIns, pThis->hPmTimer);
4197 pThis->uPmTimerVal = 0;
4198 acpiR3PmTimerReset(pDevIns, pThis, pThis->u64PmTimerInitial);
4199 pThis->uPmTimeOld = pThis->uPmTimerVal;
4200 pThis->uBatteryIndex = 0;
4201 pThis->uSystemInfoIndex = 0;
4202 pThis->gpe0_en = 0;
4203 pThis->gpe0_sts = 0;
4204 pThis->uSleepState = 0;
4205 PDMDevHlpTimerUnlockClock(pDevIns, pThis->hPmTimer);
4206
4207 /* Real device behavior is resetting only the PM controller state,
4208 * but we're additionally doing the job of the BIOS. */
4209 acpiR3UpdatePmHandlers(pDevIns, pThis, pThisCC, PM_PORT_BASE);
4210 acpiR3PmPCIBIOSFake(pDevIns, pThis);
4211
4212 /* Reset SMBus base and PCI config space in addition to the SMBus controller
4213 * state. Real device behavior is only the SMBus controller state reset,
4214 * but we're additionally doing the job of the BIOS. */
4215 acpiR3UpdateSMBusHandlers(pDevIns, pThis, SMB_PORT_BASE);
4216 acpiR3SMBusPCIBIOSFake(pDevIns, pThis);
4217 acpiR3SMBusResetDevice(pThis);
4218}
4219
4220/**
4221 * @interface_method_impl{PDMDEVREG,pfnDestruct}
4222 */
4223static DECLCALLBACK(int) acpiR3Destruct(PPDMDEVINS pDevIns)
4224{
4225 PDMDEV_CHECK_VERSIONS_RETURN(pDevIns);
4226 PACPISTATE pThis = PDMDEVINS_2_DATA(pDevIns, PACPISTATE);
4227 PACPISTATER3 pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PACPISTATER3);
4228
4229 for (uint8_t i = 0; i < pThis->cCustTbls; i++)
4230 {
4231 if (pThisCC->apu8CustBin[i])
4232 {
4233 PDMDevHlpMMHeapFree(pDevIns, pThisCC->apu8CustBin[i]);
4234 pThisCC->apu8CustBin[i] = NULL;
4235 }
4236 }
4237 return VINF_SUCCESS;
4238}
4239
4240/**
4241 * @interface_method_impl{PDMDEVREG,pfnConstruct}
4242 */
4243static DECLCALLBACK(int) acpiR3Construct(PPDMDEVINS pDevIns, int iInstance, PCFGMNODE pCfg)
4244{
4245 PDMDEV_CHECK_VERSIONS_RETURN(pDevIns);
4246 PACPISTATE pThis = PDMDEVINS_2_DATA(pDevIns, PACPISTATE);
4247 PACPISTATER3 pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PACPISTATER3);
4248 PCPDMDEVHLPR3 pHlp = pDevIns->pHlpR3;
4249
4250 /*
4251 * Init data and set defaults.
4252 */
4253 /** @todo move more of the code up! */
4254
4255 pThisCC->pDevIns = pDevIns;
4256 VMCPUSET_EMPTY(&pThis->CpuSetAttached);
4257 VMCPUSET_EMPTY(&pThis->CpuSetLocked);
4258 pThis->idCpuLockCheck = UINT32_C(0xffffffff);
4259 pThis->u32CpuEventType = 0;
4260 pThis->u32CpuEvent = UINT32_C(0xffffffff);
4261
4262 /* The first CPU can't be attached/detached */
4263 VMCPUSET_ADD(&pThis->CpuSetAttached, 0);
4264 VMCPUSET_ADD(&pThis->CpuSetLocked, 0);
4265
4266 /* IBase */
4267 pThisCC->IBase.pfnQueryInterface = acpiR3QueryInterface;
4268 /* IACPIPort */
4269 pThisCC->IACPIPort.pfnSleepButtonPress = acpiR3Port_SleepButtonPress;
4270 pThisCC->IACPIPort.pfnPowerButtonPress = acpiR3Port_PowerButtonPress;
4271 pThisCC->IACPIPort.pfnGetPowerButtonHandled = acpiR3Port_GetPowerButtonHandled;
4272 pThisCC->IACPIPort.pfnGetGuestEnteredACPIMode = acpiR3Port_GetGuestEnteredACPIMode;
4273 pThisCC->IACPIPort.pfnGetCpuStatus = acpiR3Port_GetCpuStatus;
4274 pThisCC->IACPIPort.pfnMonitorHotPlugEvent = acpiR3Port_MonitorHotPlugEvent;
4275 pThisCC->IACPIPort.pfnBatteryStatusChangeEvent = acpiR3Port_BatteryStatusChangeEvent;
4276
4277 /*
4278 * Set the default critical section to NOP (related to the PM timer).
4279 */
4280 int rc = PDMDevHlpSetDeviceCritSect(pDevIns, PDMDevHlpCritSectGetNop(pDevIns));
4281 AssertRCReturn(rc, rc);
4282
4283 rc = PDMDevHlpCritSectInit(pDevIns, &pThis->CritSect, RT_SRC_POS, "acpi#%u", iInstance);
4284 AssertRCReturn(rc, rc);
4285
4286 /*
4287 * Validate and read the configuration.
4288 */
4289 PDMDEV_VALIDATE_CONFIG_RETURN(pDevIns,
4290 "IOAPIC"
4291 "|NumCPUs"
4292 "|HpetEnabled"
4293 "|McfgEnabled"
4294 "|McfgBase"
4295 "|McfgLength"
4296 "|PciPref64Enabled"
4297 "|PciPref64LimitGB"
4298 "|SmcEnabled"
4299 "|FdcEnabled"
4300 "|ShowRtc"
4301 "|ShowCpu"
4302 "|NicPciAddress"
4303 "|AudioPciAddress"
4304 "|NvmePciAddress"
4305 "|IocPciAddress"
4306 "|HostBusPciAddress"
4307 "|EnableSuspendToDisk"
4308 "|PowerS1Enabled"
4309 "|PowerS4Enabled"
4310 "|CpuHotPlug"
4311 "|AmlFilePath"
4312 "|Serial0IoPortBase"
4313 "|Serial1IoPortBase"
4314 "|Serial2IoPortBase"
4315 "|Serial3IoPortBase"
4316 "|Serial0Irq"
4317 "|Serial1Irq"
4318 "|Serial2Irq"
4319 "|Serial3Irq"
4320 "|AcpiOemId"
4321 "|AcpiCreatorId"
4322 "|AcpiCreatorRev"
4323 "|CustomTable"
4324 "|CustomTable0"
4325 "|CustomTable1"
4326 "|CustomTable2"
4327 "|CustomTable3"
4328 "|Parallel0IoPortBase"
4329 "|Parallel1IoPortBase"
4330 "|Parallel0Irq"
4331 "|Parallel1Irq"
4332 "|IommuIntelEnabled"
4333 "|IommuAmdEnabled"
4334 "|IommuPciAddress"
4335 "|SbIoApicPciAddress"
4336 "|TpmMode"
4337 "|TpmMmioAddress"
4338 "|SsdtTpmFilePath"
4339 , "");
4340
4341 /* query whether we are supposed to present an IOAPIC */
4342 rc = pHlp->pfnCFGMQueryU8Def(pCfg, "IOAPIC", &pThis->u8UseIOApic, 1);
4343 if (RT_FAILURE(rc))
4344 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to read \"IOAPIC\""));
4345
4346 rc = pHlp->pfnCFGMQueryU16Def(pCfg, "NumCPUs", &pThis->cCpus, 1);
4347 if (RT_FAILURE(rc))
4348 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Querying \"NumCPUs\" as integer failed"));
4349
4350 /* query whether we are supposed to present an FDC controller */
4351 rc = pHlp->pfnCFGMQueryBoolDef(pCfg, "FdcEnabled", &pThis->fUseFdc, true);
4352 if (RT_FAILURE(rc))
4353 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to read \"FdcEnabled\""));
4354
4355 /* query whether we are supposed to present HPET */
4356 rc = pHlp->pfnCFGMQueryBoolDef(pCfg, "HpetEnabled", &pThis->fUseHpet, false);
4357 if (RT_FAILURE(rc))
4358 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to read \"HpetEnabled\""));
4359 /* query MCFG configuration */
4360 rc = pHlp->pfnCFGMQueryU64Def(pCfg, "McfgBase", &pThis->u64PciConfigMMioAddress, 0);
4361 if (RT_FAILURE(rc))
4362 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to read \"McfgBase\""));
4363 rc = pHlp->pfnCFGMQueryU64Def(pCfg, "McfgLength", &pThis->u64PciConfigMMioLength, 0);
4364 if (RT_FAILURE(rc))
4365 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to read \"McfgLength\""));
4366 pThis->fUseMcfg = (pThis->u64PciConfigMMioAddress != 0) && (pThis->u64PciConfigMMioLength != 0);
4367
4368 /* query whether we are supposed to set up the 64-bit prefetchable memory window */
4369 rc = pHlp->pfnCFGMQueryBoolDef(pCfg, "PciPref64Enabled", &pThis->fPciPref64Enabled, false);
4370 if (RT_FAILURE(rc))
4371 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to read \"PciPref64Enabled\""));
4372
4373 /* query the limit of the the 64-bit prefetchable memory window */
4374 uint64_t u64PciPref64MaxGB;
4375 rc = pHlp->pfnCFGMQueryU64Def(pCfg, "PciPref64LimitGB", &u64PciPref64MaxGB, 64);
4376 if (RT_FAILURE(rc))
4377 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to read \"PciPref64LimitGB\""));
4378 pThis->u64PciPref64Max = _1G64 * u64PciPref64MaxGB;
4379
4380 /* query whether we are supposed to present SMC */
4381 rc = pHlp->pfnCFGMQueryBoolDef(pCfg, "SmcEnabled", &pThis->fUseSmc, false);
4382 if (RT_FAILURE(rc))
4383 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to read \"SmcEnabled\""));
4384
4385 /* query whether we are supposed to present RTC object */
4386 rc = pHlp->pfnCFGMQueryBoolDef(pCfg, "ShowRtc", &pThis->fShowRtc, false);
4387 if (RT_FAILURE(rc))
4388 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to read \"ShowRtc\""));
4389
4390 /* query whether we are supposed to present CPU objects */
4391 rc = pHlp->pfnCFGMQueryBoolDef(pCfg, "ShowCpu", &pThis->fShowCpu, false);
4392 if (RT_FAILURE(rc))
4393 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to read \"ShowCpu\""));
4394
4395 /* query primary NIC PCI address (GIGE) */
4396 rc = pHlp->pfnCFGMQueryU32Def(pCfg, "NicPciAddress", &pThis->u32NicPciAddress, 0);
4397 if (RT_FAILURE(rc))
4398 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to read \"NicPciAddress\""));
4399
4400 /* query HD Audio PCI address (HDAA) */
4401 rc = pHlp->pfnCFGMQueryU32Def(pCfg, "AudioPciAddress", &pThis->u32AudioPciAddress, 0);
4402 if (RT_FAILURE(rc))
4403 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to read \"AudioPciAddress\""));
4404
4405 /* query NVMe PCI address (NVMA) */
4406 rc = pHlp->pfnCFGMQueryU32Def(pCfg, "NvmePciAddress", &pThis->u32NvmePciAddress, 0);
4407 if (RT_FAILURE(rc))
4408 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to read \"NvmePciAddress\""));
4409
4410 /* query IO controller (southbridge) PCI address */
4411 rc = pHlp->pfnCFGMQueryU32Def(pCfg, "IocPciAddress", &pThis->u32IocPciAddress, 0);
4412 if (RT_FAILURE(rc))
4413 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to read \"IocPciAddress\""));
4414
4415 /* query host bus controller PCI address */
4416 rc = pHlp->pfnCFGMQueryU32Def(pCfg, "HostBusPciAddress", &pThis->u32HbcPciAddress, 0);
4417 if (RT_FAILURE(rc))
4418 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to read \"HostBusPciAddress\""));
4419
4420 /* query whether S1 power state should be exposed */
4421 rc = pHlp->pfnCFGMQueryBoolDef(pCfg, "PowerS1Enabled", &pThis->fS1Enabled, false);
4422 if (RT_FAILURE(rc))
4423 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to read \"PowerS1Enabled\""));
4424
4425 /* query whether S4 power state should be exposed */
4426 rc = pHlp->pfnCFGMQueryBoolDef(pCfg, "PowerS4Enabled", &pThis->fS4Enabled, false);
4427 if (RT_FAILURE(rc))
4428 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to read \"PowerS4Enabled\""));
4429
4430 /* query whether S1 power state should save the VM state */
4431 rc = pHlp->pfnCFGMQueryBoolDef(pCfg, "EnableSuspendToDisk", &pThis->fSuspendToSavedState, false);
4432 if (RT_FAILURE(rc))
4433 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to read \"EnableSuspendToDisk\""));
4434
4435 /* query whether we are allow CPU hot plugging */
4436 rc = pHlp->pfnCFGMQueryBoolDef(pCfg, "CpuHotPlug", &pThis->fCpuHotPlug, false);
4437 if (RT_FAILURE(rc))
4438 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to read \"CpuHotPlug\""));
4439
4440 /* query serial info */
4441 rc = pHlp->pfnCFGMQueryU8Def(pCfg, "Serial0Irq", &pThis->uSerial0Irq, 4);
4442 if (RT_FAILURE(rc))
4443 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to read \"Serial0Irq\""));
4444
4445 rc = pHlp->pfnCFGMQueryU16Def(pCfg, "Serial0IoPortBase", &pThis->uSerial0IoPortBase, 0x3f8);
4446 if (RT_FAILURE(rc))
4447 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to read \"Serial0IoPortBase\""));
4448
4449 /* Serial 1 is enabled, get config data */
4450 rc = pHlp->pfnCFGMQueryU8Def(pCfg, "Serial1Irq", &pThis->uSerial1Irq, 3);
4451 if (RT_FAILURE(rc))
4452 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to read \"Serial1Irq\""));
4453
4454 rc = pHlp->pfnCFGMQueryU16Def(pCfg, "Serial1IoPortBase", &pThis->uSerial1IoPortBase, 0x2f8);
4455 if (RT_FAILURE(rc))
4456 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to read \"Serial1IoPortBase\""));
4457
4458 /* Read serial port 2 settings; disabled if CFGM keys do not exist. */
4459 rc = pHlp->pfnCFGMQueryU8Def(pCfg, "Serial2Irq", &pThis->uSerial2Irq, 0);
4460 if (RT_FAILURE(rc))
4461 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to read \"Serial2Irq\""));
4462
4463 rc = pHlp->pfnCFGMQueryU16Def(pCfg, "Serial2IoPortBase", &pThis->uSerial2IoPortBase, 0);
4464 if (RT_FAILURE(rc))
4465 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to read \"Serial2IoPortBase\""));
4466
4467 /* Read serial port 3 settings; disabled if CFGM keys do not exist. */
4468 rc = pHlp->pfnCFGMQueryU8Def(pCfg, "Serial3Irq", &pThis->uSerial3Irq, 0);
4469 if (RT_FAILURE(rc))
4470 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to read \"Serial3Irq\""));
4471
4472 rc = pHlp->pfnCFGMQueryU16Def(pCfg, "Serial3IoPortBase", &pThis->uSerial3IoPortBase, 0);
4473 if (RT_FAILURE(rc))
4474 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to read \"Serial3IoPortBase\""));
4475 /*
4476 * Query settings for both parallel ports, if the CFGM keys don't exist pretend that
4477 * the corresponding parallel port is not enabled.
4478 */
4479 rc = pHlp->pfnCFGMQueryU8Def(pCfg, "Parallel0Irq", &pThis->uParallel0Irq, 0);
4480 if (RT_FAILURE(rc))
4481 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to read \"Parallel0Irq\""));
4482
4483 rc = pHlp->pfnCFGMQueryU16Def(pCfg, "Parallel0IoPortBase", &pThis->uParallel0IoPortBase, 0);
4484 if (RT_FAILURE(rc))
4485 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to read \"Parallel0IoPortBase\""));
4486
4487 rc = pHlp->pfnCFGMQueryU8Def(pCfg, "Parallel1Irq", &pThis->uParallel1Irq, 0);
4488 if (RT_FAILURE(rc))
4489 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to read \"Parallel1Irq\""));
4490
4491 rc = pHlp->pfnCFGMQueryU16Def(pCfg, "Parallel1IoPortBase", &pThis->uParallel1IoPortBase, 0);
4492 if (RT_FAILURE(rc))
4493 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to read \"Parallel1IoPortBase\""));
4494
4495#ifdef VBOX_WITH_IOMMU_AMD
4496 /* Query whether an IOMMU (AMD) is enabled. */
4497 rc = pHlp->pfnCFGMQueryBoolDef(pCfg, "IommuAmdEnabled", &pThis->fUseIommuAmd, false);
4498 if (RT_FAILURE(rc))
4499 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to read \"IommuAmdEnabled\""));
4500
4501 if (pThis->fUseIommuAmd)
4502 {
4503 /* Query IOMMU AMD address (IOMA). */
4504 rc = pHlp->pfnCFGMQueryU32(pCfg, "IommuPciAddress", &pThis->u32IommuPciAddress);
4505 if (RT_FAILURE(rc))
4506 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to read \"IommuPciAddress\""));
4507
4508 /* Query southbridge I/O APIC address (required when an AMD IOMMU is configured). */
4509 rc = pHlp->pfnCFGMQueryU32(pCfg, "SbIoApicPciAddress", &pThis->u32SbIoApicPciAddress);
4510 if (RT_FAILURE(rc))
4511 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to read \"SbIoApicAddress\""));
4512
4513 /* Warn if the IOMMU Address is at the PCI host-bridge address. */
4514 /** @todo We should eventually not assign the IOMMU at this address, see
4515 * @bugref{9654#c53}. */
4516 if (!pThis->u32IommuPciAddress)
4517 LogRel(("ACPI: Warning! AMD IOMMU assigned the PCI host bridge address.\n"));
4518
4519 /* Warn if the IOAPIC is not at the expected address. */
4520 if (pThis->u32SbIoApicPciAddress != RT_MAKE_U32(VBOX_PCI_FN_SB_IOAPIC, VBOX_PCI_DEV_SB_IOAPIC))
4521 {
4522 LogRel(("ACPI: Southbridge I/O APIC not at %#x:%#x:%#x when an AMD IOMMU is present.\n",
4523 VBOX_PCI_BUS_SB_IOAPIC, VBOX_PCI_DEV_SB_IOAPIC, VBOX_PCI_FN_SB_IOAPIC));
4524 return PDMDEV_SET_ERROR(pDevIns, VERR_MISMATCH, N_("Configuration error: \"SbIoApicAddress\" mismatch"));
4525 }
4526 }
4527#endif
4528
4529#ifdef VBOX_WITH_IOMMU_INTEL
4530 /* Query whether an IOMMU (Intel) is enabled. */
4531 rc = pHlp->pfnCFGMQueryBoolDef(pCfg, "IommuIntelEnabled", &pThis->fUseIommuIntel, false);
4532 if (RT_FAILURE(rc))
4533 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to read \"IommuIntelEnabled\""));
4534
4535 if (pThis->fUseIommuIntel)
4536 {
4537 /* Query IOMMU Intel address. */
4538 rc = pHlp->pfnCFGMQueryU32(pCfg, "IommuPciAddress", &pThis->u32IommuPciAddress);
4539 if (RT_FAILURE(rc))
4540 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to read \"IommuPciAddress\""));
4541
4542 /* Get the reserved I/O APIC PCI address (required when an Intel IOMMU is configured). */
4543 rc = pHlp->pfnCFGMQueryU32(pCfg, "SbIoApicPciAddress", &pThis->u32SbIoApicPciAddress);
4544 if (RT_FAILURE(rc))
4545 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to read \"SbIoApicAddress\""));
4546
4547 /* Warn if the IOAPIC is not at the expected address. */
4548 if (pThis->u32SbIoApicPciAddress != RT_MAKE_U32(VBOX_PCI_FN_SB_IOAPIC, VBOX_PCI_DEV_SB_IOAPIC))
4549 {
4550 LogRel(("ACPI: Southbridge I/O APIC not at %#x:%#x:%#x when an Intel IOMMU is present.\n",
4551 VBOX_PCI_BUS_SB_IOAPIC, VBOX_PCI_DEV_SB_IOAPIC, VBOX_PCI_FN_SB_IOAPIC));
4552 return PDMDEV_SET_ERROR(pDevIns, VERR_MISMATCH, N_("Configuration error: \"SbIoApicAddress\" mismatch"));
4553 }
4554 }
4555#endif
4556
4557 /* Don't even think about enabling an Intel and an AMD IOMMU at the same time! */
4558 if ( pThis->fUseIommuAmd
4559 && pThis->fUseIommuIntel)
4560 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Cannot enable Intel and AMD IOMMU simultaneously!"));
4561
4562#ifdef VBOX_WITH_TPM
4563 char szTpmMode[64]; RT_ZERO(szTpmMode);
4564
4565 rc = pHlp->pfnCFGMQueryStringDef(pCfg, "TpmMode", &szTpmMode[0], RT_ELEMENTS(szTpmMode) - 1, "disabled");
4566 if (RT_FAILURE(rc))
4567 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to read \"TpmMode\""));
4568
4569 if (!RTStrICmp(szTpmMode, "disabled"))
4570 pThis->enmTpmMode = ACPITPMMODE_DISABLED;
4571 else if (!RTStrICmp(szTpmMode, "tis1.2"))
4572 pThis->enmTpmMode = ACPITPMMODE_TIS_1_2;
4573 else if (!RTStrICmp(szTpmMode, "crb2.0"))
4574 pThis->enmTpmMode = ACPITPMMODE_CRB_2_0;
4575 else if (!RTStrICmp(szTpmMode, "fifo2.0"))
4576 pThis->enmTpmMode = ACPITPMMODE_FIFO_2_0;
4577 else
4578 return PDMDEV_SET_ERROR(pDevIns, VERR_INVALID_PARAMETER, N_("Configuration error: Value of \"TpmMode\" is not known"));
4579
4580 rc = pHlp->pfnCFGMQueryU64Def(pCfg, "TpmMmioAddress", (uint64_t *)&pThis->GCPhysTpmMmio, ACPI_TPM_MMIO_BASE_DEFAULT);
4581 if (RT_FAILURE(rc))
4582 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to read \"TpmMmioAddress\""));
4583#endif
4584
4585 /* Try to attach the other CPUs */
4586 for (unsigned i = 1; i < pThis->cCpus; i++)
4587 {
4588 if (pThis->fCpuHotPlug)
4589 {
4590 PPDMIBASE IBaseTmp;
4591 rc = PDMDevHlpDriverAttach(pDevIns, i, &pThisCC->IBase, &IBaseTmp, "ACPI CPU");
4592
4593 if (RT_SUCCESS(rc))
4594 {
4595 VMCPUSET_ADD(&pThis->CpuSetAttached, i);
4596 VMCPUSET_ADD(&pThis->CpuSetLocked, i);
4597 Log(("acpi: Attached CPU %u\n", i));
4598 }
4599 else if (rc == VERR_PDM_NO_ATTACHED_DRIVER)
4600 Log(("acpi: CPU %u not attached yet\n", i));
4601 else
4602 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Failed to attach CPU object\n"));
4603 }
4604 else
4605 {
4606 /* CPU is always attached if hot-plug is not enabled. */
4607 VMCPUSET_ADD(&pThis->CpuSetAttached, i);
4608 VMCPUSET_ADD(&pThis->CpuSetLocked, i);
4609 }
4610 }
4611
4612 char szOemId[16];
4613 rc = pHlp->pfnCFGMQueryStringDef(pCfg, "AcpiOemId", szOemId, sizeof(szOemId), "VBOX ");
4614 if (RT_FAILURE(rc))
4615 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Querying \"AcpiOemId\" as string failed"));
4616 size_t cchOemId = strlen(szOemId);
4617 if (cchOemId > 6)
4618 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: \"AcpiOemId\" must contain not more than 6 characters"));
4619 memset(pThis->au8OemId, ' ', sizeof(pThis->au8OemId));
4620 memcpy(pThis->au8OemId, szOemId, cchOemId);
4621
4622 char szCreatorId[16];
4623 rc = pHlp->pfnCFGMQueryStringDef(pCfg, "AcpiCreatorId", szCreatorId, sizeof(szCreatorId), "ASL ");
4624 if (RT_FAILURE(rc))
4625 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Querying \"AcpiCreatorId\" as string failed"));
4626 size_t cchCreatorId = strlen(szCreatorId);
4627 if (cchCreatorId > 4)
4628 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: \"AcpiCreatorId\" must contain not more than 4 characters"));
4629 memset(pThis->au8CreatorId, ' ', sizeof(pThis->au8CreatorId));
4630 memcpy(pThis->au8CreatorId, szCreatorId, cchCreatorId);
4631
4632 rc = pHlp->pfnCFGMQueryU32Def(pCfg, "AcpiCreatorRev", &pThis->u32CreatorRev, RT_H2LE_U32(0x61));
4633 if (RT_FAILURE(rc))
4634 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Querying \"AcpiCreatorRev\" as integer failed"));
4635
4636 pThis->u32OemRevision = RT_H2LE_U32(0x1);
4637
4638 /*
4639 * Load custom ACPI tables.
4640 */
4641 /* Total space available for custom ACPI tables */
4642 /** @todo define as appropriate, remove as a magic number, and document
4643 * limitation in product manual */
4644 uint32_t cbBufAvail = 3072;
4645 pThis->cCustTbls = 0;
4646
4647 static const char *s_apszCustTblConfigKeys[] = {"CustomTable0", "CustomTable1", "CustomTable2", "CustomTable3"};
4648 AssertCompile(RT_ELEMENTS(s_apszCustTblConfigKeys) <= RT_ELEMENTS(pThisCC->apu8CustBin));
4649 for (unsigned i = 0; i < RT_ELEMENTS(s_apszCustTblConfigKeys); ++i)
4650 {
4651 const char *pszConfigKey = s_apszCustTblConfigKeys[i];
4652
4653 /*
4654 * Get the custom table binary file name.
4655 */
4656 char *pszCustBinFile = NULL;
4657 rc = pHlp->pfnCFGMQueryStringAlloc(pCfg, pszConfigKey, &pszCustBinFile);
4658 if (rc == VERR_CFGM_VALUE_NOT_FOUND && i == 0)
4659 rc = pHlp->pfnCFGMQueryStringAlloc(pCfg, "CustomTable", &pszCustBinFile); /* legacy */
4660 if (rc == VERR_CFGM_VALUE_NOT_FOUND)
4661 {
4662 rc = VINF_SUCCESS;
4663 pszCustBinFile = NULL;
4664 }
4665 else if (RT_FAILURE(rc))
4666 return PDMDEV_SET_ERROR(pDevIns, rc,
4667 N_("Configuration error: Querying \"CustomTableN\" as a string failed"));
4668 else if (!*pszCustBinFile)
4669 {
4670 PDMDevHlpMMHeapFree(pDevIns, pszCustBinFile);
4671 pszCustBinFile = NULL;
4672 }
4673
4674 /*
4675 * Determine the custom table binary size, open specified file in the process.
4676 */
4677 if (pszCustBinFile)
4678 {
4679 uint32_t idxCust = pThis->cCustTbls;
4680 rc = acpiR3ReadCustomTable(pDevIns, &pThisCC->apu8CustBin[idxCust],
4681 &pThisCC->acbCustBin[idxCust], pszCustBinFile, cbBufAvail);
4682 LogRel(("ACPI: Reading custom ACPI table(%u) from file '%s' (%d bytes)\n",
4683 idxCust, pszCustBinFile, pThisCC->acbCustBin[idxCust]));
4684 PDMDevHlpMMHeapFree(pDevIns, pszCustBinFile);
4685 if (RT_FAILURE(rc))
4686 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Error reading custom ACPI table."));
4687 cbBufAvail -= pThisCC->acbCustBin[idxCust];
4688
4689 /* Update custom OEM attributes based on custom table */
4690 /** @todo is it intended for custom tables to overwrite user provided values above? */
4691 ACPITBLHEADER *pTblHdr = (ACPITBLHEADER*)pThisCC->apu8CustBin[idxCust];
4692 memcpy(&pThis->au8OemId[0], &pTblHdr->au8OemId[0], 6);
4693 memcpy(&pThis->au8OemTabId[0], &pTblHdr->au8OemTabId[0], 8);
4694 pThis->u32OemRevision = pTblHdr->u32OemRevision;
4695 memcpy(&pThis->au8CreatorId[0], &pTblHdr->au8CreatorId[0], 4);
4696 pThis->u32CreatorRev = pTblHdr->u32CreatorRev;
4697
4698 pThis->cCustTbls++;
4699 AssertBreak(pThis->cCustTbls <= MAX_CUST_TABLES);
4700 }
4701 }
4702
4703 /* Set default PM port base */
4704 pThis->uPmIoPortBase = PM_PORT_BASE;
4705
4706 /* Set default SMBus port base */
4707 pThis->uSMBusIoPortBase = SMB_PORT_BASE;
4708
4709 /*
4710 * FDC and SMC try to use the same non-shareable interrupt (6),
4711 * enable only one device.
4712 */
4713 if (pThis->fUseSmc)
4714 pThis->fUseFdc = false;
4715
4716 /*
4717 * Plant ACPI tables.
4718 */
4719 /** @todo Part of this is redone by acpiR3MemSetup, we only need to init the
4720 * au8RSDPPage here. However, there should be no harm in doing it
4721 * twice, so the lazy bird is taking the quick way out for now. */
4722 RTGCPHYS32 GCPhysRsdp = apicR3FindRsdpSpace();
4723 if (!GCPhysRsdp)
4724 return PDMDEV_SET_ERROR(pDevIns, VERR_NO_MEMORY, N_("Can not find space for RSDP. ACPI is disabled"));
4725
4726 rc = acpiR3PlantTables(pDevIns, pThis, pThisCC);
4727 AssertRCReturn(rc, rc);
4728
4729 rc = PDMDevHlpROMRegister(pDevIns, GCPhysRsdp, 0x1000, pThis->au8RSDPPage, 0x1000,
4730 PGMPHYS_ROM_FLAGS_PERMANENT_BINARY, "ACPI RSDP");
4731 AssertRCReturn(rc, rc);
4732
4733 /*
4734 * Create the PM I/O ports. These can be unmapped and remapped.
4735 */
4736 rc = PDMDevHlpIoPortCreateIsa(pDevIns, 1 /*cPorts*/, acpiR3PM1aStsWrite, acpiR3Pm1aStsRead, NULL /*pvUser*/,
4737 "ACPI PM1a Status", NULL /*paExtDesc*/, &pThis->hIoPortPm1aSts);
4738 AssertRCReturn(rc, rc);
4739 rc = PDMDevHlpIoPortCreateIsa(pDevIns, 1 /*cPorts*/, acpiR3PM1aEnWrite, acpiR3Pm1aEnRead, NULL /*pvUser*/,
4740 "ACPI PM1a Enable", NULL /*paExtDesc*/, &pThis->hIoPortPm1aEn);
4741 AssertRCReturn(rc, rc);
4742 rc = PDMDevHlpIoPortCreateIsa(pDevIns, 1 /*cPorts*/, acpiR3PM1aCtlWrite, acpiR3Pm1aCtlRead, NULL /*pvUser*/,
4743 "ACPI PM1a Control", NULL /*paExtDesc*/, &pThis->hIoPortPm1aCtl);
4744 AssertRCReturn(rc, rc);
4745 rc = PDMDevHlpIoPortCreateIsa(pDevIns, 1 /*cPorts*/, NULL, acpiPMTmrRead, NULL /*pvUser*/,
4746 "ACPI PM Timer", NULL /*paExtDesc*/, &pThis->hIoPortPmTimer);
4747 AssertRCReturn(rc, rc);
4748 rc = PDMDevHlpIoPortCreateIsa(pDevIns, GPE0_BLK_LEN / 2 /*cPorts*/, acpiR3Gpe0StsWrite, acpiR3Gpe0StsRead, NULL /*pvUser*/,
4749 "ACPI GPE0 Status", NULL /*paExtDesc*/, &pThis->hIoPortGpe0Sts);
4750 AssertRCReturn(rc, rc);
4751 rc = PDMDevHlpIoPortCreateIsa(pDevIns, GPE0_BLK_LEN / 2 /*cPorts*/, acpiR3Gpe0EnWrite, acpiR3Gpe0EnRead, NULL /*pvUser*/,
4752 "ACPI GPE0 Enable", NULL /*paExtDesc*/, &pThis->hIoPortGpe0En);
4753 AssertRCReturn(rc, rc);
4754 rc = acpiR3MapPmIoPorts(pDevIns, pThis);
4755 AssertRCReturn(rc, rc);
4756
4757 /*
4758 * Create the System Management Bus I/O ports. These can be unmapped and remapped.
4759 */
4760 rc = PDMDevHlpIoPortCreateIsa(pDevIns, 16, acpiR3SMBusWrite, acpiR3SMBusRead, NULL /*pvUser*/,
4761 "SMBus", NULL /*paExtDesc*/, &pThis->hIoPortSMBus);
4762 AssertRCReturn(rc, rc);
4763 rc = acpiR3MapSMBusIoPorts(pDevIns, pThis);
4764 AssertRCReturn(rc, rc);
4765
4766 /*
4767 * Create and map the fixed I/O ports.
4768 */
4769 rc = PDMDevHlpIoPortCreateAndMap(pDevIns, SMI_CMD, 1, acpiR3SmiWrite, NULL,
4770 "ACPI SMI", NULL /*paExtDesc*/, &pThis->hIoPortSmi);
4771 AssertRCReturn(rc, rc);
4772#ifdef DEBUG_ACPI
4773 rc = PDMDevHlpIoPortCreateAndMap(pDevIns, DEBUG_HEX, 1, acpiR3DebugHexWrite, NULL,
4774 "ACPI Debug hex", NULL /*paExtDesc*/, &pThis->hIoPortDebugHex);
4775 AssertRCReturn(rc, rc);
4776 rc = PDMDevHlpIoPortCreateAndMap(pDevIns, DEBUG_CHR, 1, acpiR3DebugCharWrite, NULL,
4777 "ACPI Debug char", NULL /*paExtDesc*/, &pThis->hIoPortDebugChar);
4778 AssertRCReturn(rc, rc);
4779#endif
4780 rc = PDMDevHlpIoPortCreateAndMap(pDevIns, BAT_INDEX, 1, acpiR3BatIndexWrite, NULL,
4781 "ACPI Battery status index", NULL /*paExtDesc*/, &pThis->hIoPortBatteryIndex);
4782 AssertRCReturn(rc, rc);
4783 rc = PDMDevHlpIoPortCreateAndMap(pDevIns, BAT_DATA, 1, NULL, acpiR3BatDataRead,
4784 "ACPI Battery status data", NULL /*paExtDesc*/, &pThis->hIoPortBatteryData);
4785 AssertRCReturn(rc, rc);
4786 rc = PDMDevHlpIoPortCreateAndMap(pDevIns, SYSI_INDEX, 1, acpiR3SysInfoIndexWrite, NULL,
4787 "ACPI system info index", NULL /*paExtDesc*/, &pThis->hIoPortSysInfoIndex);
4788 AssertRCReturn(rc, rc);
4789 rc = PDMDevHlpIoPortCreateAndMap(pDevIns, SYSI_DATA, 1, acpiR3SysInfoDataWrite, acpiR3SysInfoDataRead,
4790 "ACPI system info data", NULL /*paExtDesc*/, &pThis->hIoPortSysInfoData);
4791 AssertRCReturn(rc, rc);
4792 rc = PDMDevHlpIoPortCreateAndMap(pDevIns, ACPI_RESET_BLK, 1, acpiR3ResetWrite, NULL,
4793 "ACPI Reset", NULL /*paExtDesc*/, &pThis->hIoPortReset);
4794 AssertRCReturn(rc, rc);
4795
4796 /*
4797 * Create the PM timer.
4798 */
4799 rc = PDMDevHlpTimerCreate(pDevIns, TMCLOCK_VIRTUAL_SYNC, acpiR3PmTimer, NULL /*pvUser*/,
4800 TMTIMER_FLAGS_NO_CRIT_SECT | TMTIMER_FLAGS_RING0, "ACPI PM", &pThis->hPmTimer);
4801 AssertRCReturn(rc, rc);
4802
4803 PDMDevHlpTimerLockClock(pDevIns, pThis->hPmTimer, VERR_IGNORED);
4804 pThis->u64PmTimerInitial = PDMDevHlpTimerGet(pDevIns, pThis->hPmTimer);
4805 acpiR3PmTimerReset(pDevIns, pThis, pThis->u64PmTimerInitial);
4806 PDMDevHlpTimerUnlockClock(pDevIns, pThis->hPmTimer);
4807
4808 /*
4809 * Set up the PCI device.
4810 */
4811 PPDMPCIDEV pPciDev = pDevIns->apPciDevs[0];
4812 PDMPCIDEV_ASSERT_VALID(pDevIns, pPciDev);
4813
4814 PDMPciDevSetVendorId(pPciDev, 0x8086); /* Intel */
4815 PDMPciDevSetDeviceId(pPciDev, 0x7113); /* 82371AB */
4816
4817 /* See p. 50 of PIIX4 manual */
4818 PDMPciDevSetCommand(pPciDev, PCI_COMMAND_IOACCESS);
4819 PDMPciDevSetStatus(pPciDev, 0x0280);
4820
4821 PDMPciDevSetRevisionId(pPciDev, 0x08);
4822
4823 PDMPciDevSetClassProg(pPciDev, 0x00);
4824 PDMPciDevSetClassSub(pPciDev, 0x80);
4825 PDMPciDevSetClassBase(pPciDev, 0x06);
4826
4827 PDMPciDevSetHeaderType(pPciDev, 0x80);
4828
4829 PDMPciDevSetBIST(pPciDev, 0x00);
4830
4831 PDMPciDevSetInterruptLine(pPciDev, SCI_INT);
4832 PDMPciDevSetInterruptPin(pPciDev, 0x01);
4833
4834 Assert((pThis->uPmIoPortBase & 0x003f) == 0);
4835 acpiR3PmPCIBIOSFake(pDevIns, pThis);
4836
4837 Assert((pThis->uSMBusIoPortBase & 0x000f) == 0);
4838 acpiR3SMBusPCIBIOSFake(pDevIns, pThis);
4839 acpiR3SMBusResetDevice(pThis);
4840
4841 rc = PDMDevHlpPCIRegister(pDevIns, pPciDev);
4842 AssertRCReturn(rc, rc);
4843
4844 rc = PDMDevHlpPCIInterceptConfigAccesses(pDevIns, pPciDev, acpiR3PciConfigRead, acpiR3PciConfigWrite);
4845 AssertRCReturn(rc, rc);
4846
4847 /*
4848 * Register the saved state.
4849 */
4850 rc = PDMDevHlpSSMRegister(pDevIns, 8, sizeof(*pThis), acpiR3SaveState, acpiR3LoadState);
4851 AssertRCReturn(rc, rc);
4852
4853 /*
4854 * Get the corresponding connector interface
4855 */
4856 rc = PDMDevHlpDriverAttach(pDevIns, 0, &pThisCC->IBase, &pThisCC->pDrvBase, "ACPI Driver Port");
4857 if (RT_SUCCESS(rc))
4858 {
4859 pThisCC->pDrv = PDMIBASE_QUERY_INTERFACE(pThisCC->pDrvBase, PDMIACPICONNECTOR);
4860 if (!pThisCC->pDrv)
4861 return PDMDEV_SET_ERROR(pDevIns, VERR_PDM_MISSING_INTERFACE, N_("LUN #0 doesn't have an ACPI connector interface"));
4862 }
4863 else if (rc == VERR_PDM_NO_ATTACHED_DRIVER)
4864 {
4865 Log(("acpi: %s/%d: warning: no driver attached to LUN #0!\n", pDevIns->pReg->szName, pDevIns->iInstance));
4866 rc = VINF_SUCCESS;
4867 }
4868 else
4869 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Failed to attach LUN #0"));
4870
4871 PDMDevHlpDBGFInfoRegister(pDevIns, "acpi", "ACPI info", acpiR3Info);
4872
4873 return rc;
4874}
4875
4876#else /* !IN_RING3 */
4877
4878/**
4879 * @callback_method_impl{PDMDEVREGR0,pfnConstruct}
4880 */
4881static DECLCALLBACK(int) acpiRZConstruct(PPDMDEVINS pDevIns)
4882{
4883 PDMDEV_CHECK_VERSIONS_RETURN(pDevIns);
4884 PACPISTATE pThis = PDMDEVINS_2_DATA(pDevIns, PACPISTATE);
4885
4886 int rc = PDMDevHlpSetDeviceCritSect(pDevIns, PDMDevHlpCritSectGetNop(pDevIns));
4887 AssertRCReturn(rc, rc);
4888
4889 /* Only the PM timer read port is handled directly in ring-0/raw-mode. */
4890 rc = PDMDevHlpIoPortSetUpContext(pDevIns, pThis->hIoPortPmTimer, NULL, acpiPMTmrRead, NULL);
4891 AssertRCReturn(rc, rc);
4892
4893 return VINF_SUCCESS;
4894}
4895
4896#endif /* !IN_RING3 */
4897
4898/**
4899 * The device registration structure.
4900 */
4901const PDMDEVREG g_DeviceACPI =
4902{
4903 /* .u32Version = */ PDM_DEVREG_VERSION,
4904 /* .uReserved0 = */ 0,
4905 /* .szName = */ "acpi",
4906 /* .fFlags = */ PDM_DEVREG_FLAGS_DEFAULT_BITS | PDM_DEVREG_FLAGS_RZ | PDM_DEVREG_FLAGS_NEW_STYLE,
4907 /* .fClass = */ PDM_DEVREG_CLASS_ACPI,
4908 /* .cMaxInstances = */ ~0U,
4909 /* .uSharedVersion = */ 42,
4910 /* .cbInstanceShared = */ sizeof(ACPISTATE),
4911 /* .cbInstanceCC = */ CTX_EXPR(sizeof(ACPISTATER3), 0, 0),
4912 /* .cbInstanceRC = */ 0,
4913 /* .cMaxPciDevices = */ 1,
4914 /* .cMaxMsixVectors = */ 0,
4915 /* .pszDescription = */ "Advanced Configuration and Power Interface",
4916#if defined(IN_RING3)
4917 /* .pszRCMod = */ "VBoxDDRC.rc",
4918 /* .pszR0Mod = */ "VBoxDDR0.r0",
4919 /* .pfnConstruct = */ acpiR3Construct,
4920 /* .pfnDestruct = */ acpiR3Destruct,
4921 /* .pfnRelocate = */ NULL,
4922 /* .pfnMemSetup = */ acpiR3MemSetup,
4923 /* .pfnPowerOn = */ NULL,
4924 /* .pfnReset = */ acpiR3Reset,
4925 /* .pfnSuspend = */ NULL,
4926 /* .pfnResume = */ acpiR3Resume,
4927 /* .pfnAttach = */ acpiR3Attach,
4928 /* .pfnDetach = */ acpiR3Detach,
4929 /* .pfnQueryInterface = */ NULL,
4930 /* .pfnInitComplete = */ NULL,
4931 /* .pfnPowerOff = */ NULL,
4932 /* .pfnSoftReset = */ NULL,
4933 /* .pfnReserved0 = */ NULL,
4934 /* .pfnReserved1 = */ NULL,
4935 /* .pfnReserved2 = */ NULL,
4936 /* .pfnReserved3 = */ NULL,
4937 /* .pfnReserved4 = */ NULL,
4938 /* .pfnReserved5 = */ NULL,
4939 /* .pfnReserved6 = */ NULL,
4940 /* .pfnReserved7 = */ NULL,
4941#elif defined(IN_RING0)
4942 /* .pfnEarlyConstruct = */ NULL,
4943 /* .pfnConstruct = */ acpiRZConstruct,
4944 /* .pfnDestruct = */ NULL,
4945 /* .pfnFinalDestruct = */ NULL,
4946 /* .pfnRequest = */ NULL,
4947 /* .pfnReserved0 = */ NULL,
4948 /* .pfnReserved1 = */ NULL,
4949 /* .pfnReserved2 = */ NULL,
4950 /* .pfnReserved3 = */ NULL,
4951 /* .pfnReserved4 = */ NULL,
4952 /* .pfnReserved5 = */ NULL,
4953 /* .pfnReserved6 = */ NULL,
4954 /* .pfnReserved7 = */ NULL,
4955#elif defined(IN_RC)
4956 /* .pfnConstruct = */ acpiRZConstruct,
4957 /* .pfnReserved0 = */ NULL,
4958 /* .pfnReserved1 = */ NULL,
4959 /* .pfnReserved2 = */ NULL,
4960 /* .pfnReserved3 = */ NULL,
4961 /* .pfnReserved4 = */ NULL,
4962 /* .pfnReserved5 = */ NULL,
4963 /* .pfnReserved6 = */ NULL,
4964 /* .pfnReserved7 = */ NULL,
4965#else
4966# error "Not in IN_RING3, IN_RING0 or IN_RC!"
4967#endif
4968 /* .u32VersionEnd = */ PDM_DEVREG_VERSION
4969};
4970
4971#endif /* !VBOX_DEVICE_STRUCT_TESTCASE */
Note: See TracBrowser for help on using the repository browser.

© 2024 Oracle Support Privacy / Do Not Sell My Info Terms of Use Trademark Policy Automated Access Etiquette