VirtualBox

source: vbox/trunk/src/VBox/Devices/PC/DevACPI.cpp@ 46845

Last change on this file since 46845 was 46491, checked in by vboxsync, 12 years ago

DevACPI: added more boot architecture flags
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1/* $Id: DevACPI.cpp 46491 2013-06-11 13:02:32Z vboxsync $ */
2/** @file
3 * DevACPI - Advanced Configuration and Power Interface (ACPI) Device.
4 */
5
6/*
7 * Copyright (C) 2006-2013 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18/*******************************************************************************
19* Header Files *
20*******************************************************************************/
21#define LOG_GROUP LOG_GROUP_DEV_ACPI
22#include <VBox/vmm/pdmdev.h>
23#include <VBox/vmm/pgm.h>
24#include <VBox/vmm/dbgftrace.h>
25#include <VBox/vmm/vmcpuset.h>
26#include <VBox/log.h>
27#include <VBox/param.h>
28#include <iprt/assert.h>
29#include <iprt/asm.h>
30#include <iprt/asm-math.h>
31#include <iprt/file.h>
32#ifdef IN_RING3
33# include <iprt/alloc.h>
34# include <iprt/string.h>
35# include <iprt/uuid.h>
36#endif /* IN_RING3 */
37
38#include "VBoxDD.h"
39
40#ifdef LOG_ENABLED
41# define DEBUG_ACPI
42#endif
43
44
45
46/*******************************************************************************
47* Defined Constants And Macros *
48*******************************************************************************/
49#ifdef IN_RING3
50/** Locks the device state, ring-3 only. */
51# define DEVACPI_LOCK_R3(a_pThis) \
52 do { \
53 int rcLock = PDMCritSectEnter(&(a_pThis)->CritSect, VERR_IGNORED); \
54 AssertRC(rcLock); \
55 } while (0)
56#endif
57/** Unlocks the device state (all contexts). */
58#define DEVACPI_UNLOCK(a_pThis) \
59 do { PDMCritSectLeave(&(a_pThis)->CritSect); } while (0)
60
61
62#define DEBUG_HEX 0x3000
63#define DEBUG_CHR 0x3001
64
65#define PM_TMR_FREQ 3579545
66/* Default base for PM PIIX4 device */
67#define PM_PORT_BASE 0x4000
68/* Port offsets in PM device */
69enum
70{
71 PM1a_EVT_OFFSET = 0x00,
72 PM1b_EVT_OFFSET = -1, /**< not supported */
73 PM1a_CTL_OFFSET = 0x04,
74 PM1b_CTL_OFFSET = -1, /**< not supported */
75 PM2_CTL_OFFSET = -1, /**< not supported */
76 PM_TMR_OFFSET = 0x08,
77 GPE0_OFFSET = 0x20,
78 GPE1_OFFSET = -1 /**< not supported */
79};
80
81#define BAT_INDEX 0x00004040
82#define BAT_DATA 0x00004044
83#define SYSI_INDEX 0x00004048
84#define SYSI_DATA 0x0000404c
85#define ACPI_RESET_BLK 0x00004050
86
87/* PM1x status register bits */
88#define TMR_STS RT_BIT(0)
89#define RSR1_STS (RT_BIT(1) | RT_BIT(2) | RT_BIT(3))
90#define BM_STS RT_BIT(4)
91#define GBL_STS RT_BIT(5)
92#define RSR2_STS (RT_BIT(6) | RT_BIT(7))
93#define PWRBTN_STS RT_BIT(8)
94#define SLPBTN_STS RT_BIT(9)
95#define RTC_STS RT_BIT(10)
96#define IGN_STS RT_BIT(11)
97#define RSR3_STS (RT_BIT(12) | RT_BIT(13) | RT_BIT(14))
98#define WAK_STS RT_BIT(15)
99#define RSR_STS (RSR1_STS | RSR2_STS | RSR3_STS)
100
101/* PM1x enable register bits */
102#define TMR_EN RT_BIT(0)
103#define RSR1_EN (RT_BIT(1) | RT_BIT(2) | RT_BIT(3) | RT_BIT(4))
104#define GBL_EN RT_BIT(5)
105#define RSR2_EN (RT_BIT(6) | RT_BIT(7))
106#define PWRBTN_EN RT_BIT(8)
107#define SLPBTN_EN RT_BIT(9)
108#define RTC_EN RT_BIT(10)
109#define RSR3_EN (RT_BIT(11) | RT_BIT(12) | RT_BIT(13) | RT_BIT(14) | RT_BIT(15))
110#define RSR_EN (RSR1_EN | RSR2_EN | RSR3_EN)
111#define IGN_EN 0
112
113/* PM1x control register bits */
114#define SCI_EN RT_BIT(0)
115#define BM_RLD RT_BIT(1)
116#define GBL_RLS RT_BIT(2)
117#define RSR1_CNT (RT_BIT(3) | RT_BIT(4) | RT_BIT(5) | RT_BIT(6) | RT_BIT(7) | RT_BIT(8))
118#define IGN_CNT RT_BIT(9)
119#define SLP_TYPx_SHIFT 10
120#define SLP_TYPx_MASK 7
121#define SLP_EN RT_BIT(13)
122#define RSR2_CNT (RT_BIT(14) | RT_BIT(15))
123#define RSR_CNT (RSR1_CNT | RSR2_CNT)
124
125#define GPE0_BATTERY_INFO_CHANGED RT_BIT(0)
126
127enum
128{
129 BAT_STATUS_STATE = 0x00, /**< BST battery state */
130 BAT_STATUS_PRESENT_RATE = 0x01, /**< BST battery present rate */
131 BAT_STATUS_REMAINING_CAPACITY = 0x02, /**< BST battery remaining capacity */
132 BAT_STATUS_PRESENT_VOLTAGE = 0x03, /**< BST battery present voltage */
133 BAT_INFO_UNITS = 0x04, /**< BIF power unit */
134 BAT_INFO_DESIGN_CAPACITY = 0x05, /**< BIF design capacity */
135 BAT_INFO_LAST_FULL_CHARGE_CAPACITY = 0x06, /**< BIF last full charge capacity */
136 BAT_INFO_TECHNOLOGY = 0x07, /**< BIF battery technology */
137 BAT_INFO_DESIGN_VOLTAGE = 0x08, /**< BIF design voltage */
138 BAT_INFO_DESIGN_CAPACITY_OF_WARNING = 0x09, /**< BIF design capacity of warning */
139 BAT_INFO_DESIGN_CAPACITY_OF_LOW = 0x0A, /**< BIF design capacity of low */
140 BAT_INFO_CAPACITY_GRANULARITY_1 = 0x0B, /**< BIF battery capacity granularity 1 */
141 BAT_INFO_CAPACITY_GRANULARITY_2 = 0x0C, /**< BIF battery capacity granularity 2 */
142 BAT_DEVICE_STATUS = 0x0D, /**< STA device status */
143 BAT_POWER_SOURCE = 0x0E, /**< PSR power source */
144 BAT_INDEX_LAST
145};
146
147enum
148{
149 CPU_EVENT_TYPE_ADD = 0x01, /**< Event type add */
150 CPU_EVENT_TYPE_REMOVE = 0x03 /**< Event type remove */
151};
152
153enum
154{
155 SYSTEM_INFO_INDEX_LOW_MEMORY_LENGTH = 0,
156 SYSTEM_INFO_INDEX_USE_IOAPIC = 1,
157 SYSTEM_INFO_INDEX_HPET_STATUS = 2,
158 SYSTEM_INFO_INDEX_SMC_STATUS = 3,
159 SYSTEM_INFO_INDEX_FDC_STATUS = 4,
160 SYSTEM_INFO_INDEX_CPU0_STATUS = 5, /**< For compatibility with older saved states. */
161 SYSTEM_INFO_INDEX_CPU1_STATUS = 6, /**< For compatibility with older saved states. */
162 SYSTEM_INFO_INDEX_CPU2_STATUS = 7, /**< For compatibility with older saved states. */
163 SYSTEM_INFO_INDEX_CPU3_STATUS = 8, /**< For compatibility with older saved states. */
164 SYSTEM_INFO_INDEX_HIGH_MEMORY_LENGTH= 9,
165 SYSTEM_INFO_INDEX_RTC_STATUS = 10,
166 SYSTEM_INFO_INDEX_CPU_LOCKED = 11, /**< Contains a flag indicating whether the CPU is locked or not */
167 SYSTEM_INFO_INDEX_CPU_LOCK_CHECK = 12, /**< For which CPU the lock status should be checked */
168 SYSTEM_INFO_INDEX_CPU_EVENT_TYPE = 13, /**< Type of the CPU hot-plug event */
169 SYSTEM_INFO_INDEX_CPU_EVENT = 14, /**< The CPU id the event is for */
170 SYSTEM_INFO_INDEX_NIC_ADDRESS = 15, /**< NIC PCI address, or 0 */
171 SYSTEM_INFO_INDEX_AUDIO_ADDRESS = 16, /**< Audio card PCI address, or 0 */
172 SYSTEM_INFO_INDEX_POWER_STATES = 17,
173 SYSTEM_INFO_INDEX_IOC_ADDRESS = 18, /**< IO controller PCI address */
174 SYSTEM_INFO_INDEX_HBC_ADDRESS = 19, /**< host bus controller PCI address */
175 SYSTEM_INFO_INDEX_PCI_BASE = 20, /**< PCI bus MCFG MMIO range base */
176 SYSTEM_INFO_INDEX_PCI_LENGTH = 21, /**< PCI bus MCFG MMIO range length */
177 SYSTEM_INFO_INDEX_SERIAL0_IOBASE = 22,
178 SYSTEM_INFO_INDEX_SERIAL0_IRQ = 23,
179 SYSTEM_INFO_INDEX_SERIAL1_IOBASE = 24,
180 SYSTEM_INFO_INDEX_SERIAL1_IRQ = 25,
181 SYSTEM_INFO_INDEX_END = 26,
182 SYSTEM_INFO_INDEX_INVALID = 0x80,
183 SYSTEM_INFO_INDEX_VALID = 0x200
184};
185
186#define AC_OFFLINE 0
187#define AC_ONLINE 1
188
189#define BAT_TECH_PRIMARY 1
190#define BAT_TECH_SECONDARY 2
191
192#define STA_DEVICE_PRESENT_MASK RT_BIT(0) /**< present */
193#define STA_DEVICE_ENABLED_MASK RT_BIT(1) /**< enabled and decodes its resources */
194#define STA_DEVICE_SHOW_IN_UI_MASK RT_BIT(2) /**< should be shown in UI */
195#define STA_DEVICE_FUNCTIONING_PROPERLY_MASK RT_BIT(3) /**< functioning properly */
196#define STA_BATTERY_PRESENT_MASK RT_BIT(4) /**< the battery is present */
197
198
199/*******************************************************************************
200* Structures and Typedefs *
201*******************************************************************************/
202/**
203 * The ACPI device state.
204 */
205typedef struct ACPIState
206{
207 PCIDevice dev;
208 /** Critical section protecting the ACPI state. */
209 PDMCRITSECT CritSect;
210
211 uint16_t pm1a_en;
212 uint16_t pm1a_sts;
213 uint16_t pm1a_ctl;
214 /** Number of logical CPUs in guest */
215 uint16_t cCpus;
216 uint64_t u64PmTimerInitial;
217 PTMTIMERR3 pPmTimerR3;
218 PTMTIMERR0 pPmTimerR0;
219 PTMTIMERRC pPmTimerRC;
220
221 uint32_t gpe0_en;
222 uint32_t gpe0_sts;
223
224 uint32_t uBatteryIndex;
225 uint32_t au8BatteryInfo[13];
226
227 uint32_t uSystemInfoIndex;
228 uint64_t u64RamSize;
229 /** The number of bytes above 4GB. */
230 uint64_t cbRamHigh;
231 /** The number of bytes below 4GB. */
232 uint32_t cbRamLow;
233
234 /** Current ACPI S* state. We support S0 and S5. */
235 uint32_t uSleepState;
236 uint8_t au8RSDPPage[0x1000];
237 /** This is a workaround for incorrect index field handling by Intels ACPICA.
238 * The system info _INI method writes to offset 0x200. We either observe a
239 * write request to index 0x80 (in that case we don't change the index) or a
240 * write request to offset 0x200 (in that case we divide the index value by
241 * 4. Note that the _STA method is sometimes called prior to the _INI method
242 * (ACPI spec 6.3.7, _STA). See the special case for BAT_DEVICE_STATUS in
243 * acpiR3BatIndexWrite() for handling this. */
244 uint8_t u8IndexShift;
245 /** provide an I/O-APIC */
246 uint8_t u8UseIOApic;
247 /** provide a floppy controller */
248 bool fUseFdc;
249 /** If High Precision Event Timer device should be supported */
250 bool fUseHpet;
251 /** If System Management Controller device should be supported */
252 bool fUseSmc;
253 /** the guest handled the last power button event */
254 bool fPowerButtonHandled;
255 /** If ACPI CPU device should be shown */
256 bool fShowCpu;
257 /** If Real Time Clock ACPI object to be shown */
258 bool fShowRtc;
259 /** I/O port address of PM device. */
260 RTIOPORT uPmIoPortBase;
261 /** Flag whether the GC part of the device is enabled. */
262 bool fGCEnabled;
263 /** Flag whether the R0 part of the device is enabled. */
264 bool fR0Enabled;
265 /** Array of flags of attached CPUs */
266 VMCPUSET CpuSetAttached;
267 /** Which CPU to check for the locked status. */
268 uint32_t idCpuLockCheck;
269 /** Mask of locked CPUs (used by the guest). */
270 VMCPUSET CpuSetLocked;
271 /** The CPU event type. */
272 uint32_t u32CpuEventType;
273 /** The CPU id affected. */
274 uint32_t u32CpuEvent;
275 /** Flag whether CPU hot plugging is enabled. */
276 bool fCpuHotPlug;
277 /** If MCFG ACPI table shown to the guest */
278 bool fUseMcfg;
279 /** Primary NIC PCI address. */
280 uint32_t u32NicPciAddress;
281 /** Primary audio card PCI address. */
282 uint32_t u32AudioPciAddress;
283 /** Flag whether S1 power state is enabled. */
284 bool fS1Enabled;
285 /** Flag whether S4 power state is enabled. */
286 bool fS4Enabled;
287 /** Flag whether S1 triggers a state save. */
288 bool fSuspendToSavedState;
289 /** Flag whether to set WAK_STS on resume (restore included). */
290 bool fSetWakeupOnResume;
291 /** PCI address of the IO controller device. */
292 uint32_t u32IocPciAddress;
293 /** PCI address of the host bus controller device. */
294 uint32_t u32HbcPciAddress;
295 /* Physical address of PCI config space MMIO region */
296 uint64_t u64PciConfigMMioAddress;
297 /* Length of PCI config space MMIO region */
298 uint64_t u64PciConfigMMioLength;
299 /** Serial 0 IRQ number */
300 uint8_t uSerial0Irq;
301 /** Serial 1 IRQ number */
302 uint8_t uSerial1Irq;
303 /** Serial 0 IO port base */
304 RTIOPORT uSerial0IoPortBase;
305 /** Serial 1 IO port base */
306 RTIOPORT uSerial1IoPortBase;
307 /** ACPI port base interface. */
308 PDMIBASE IBase;
309 /** ACPI port interface. */
310 PDMIACPIPORT IACPIPort;
311 /** Pointer to the device instance. */
312 PPDMDEVINSR3 pDevIns;
313 /** Pointer to the driver base interface. */
314 R3PTRTYPE(PPDMIBASE) pDrvBase;
315 /** Pointer to the driver connector interface. */
316 R3PTRTYPE(PPDMIACPICONNECTOR) pDrv;
317
318 /** Pointer to default PCI config read function. */
319 R3PTRTYPE(PFNPCICONFIGREAD) pfnAcpiPciConfigRead;
320 /** Pointer to default PCI config write function. */
321 R3PTRTYPE(PFNPCICONFIGWRITE) pfnAcpiPciConfigWrite;
322
323 /** If custom table should be supported */
324 bool fUseCust;
325 /** ACPI OEM ID */
326 uint8_t au8OemId[6];
327 /** ACPI Crator ID */
328 uint8_t au8CreatorId[4];
329 /** ACPI Crator Rev */
330 uint32_t u32CreatorRev;
331 /** ACPI custom OEM Tab ID */
332 uint8_t au8OemTabId[8];
333 /** ACPI custom OEM Rev */
334 uint32_t u32OemRevision;
335 uint32_t Alignment0;
336
337 /** The custom table binary data. */
338 R3PTRTYPE(uint8_t *) pu8CustBin;
339 /** The size of the custom table binary. */
340 uint64_t cbCustBin;
341} ACPIState;
342
343#pragma pack(1)
344
345/** Generic Address Structure (see ACPIspec 3.0, 5.2.3.1) */
346struct ACPIGENADDR
347{
348 uint8_t u8AddressSpaceId; /**< 0=sys, 1=IO, 2=PCICfg, 3=emb, 4=SMBus */
349 uint8_t u8RegisterBitWidth; /**< size in bits of the given register */
350 uint8_t u8RegisterBitOffset; /**< bit offset of register */
351 uint8_t u8AccessSize; /**< 1=byte, 2=word, 3=dword, 4=qword */
352 uint64_t u64Address; /**< 64-bit address of register */
353};
354AssertCompileSize(ACPIGENADDR, 12);
355
356/** Root System Description Pointer */
357struct ACPITBLRSDP
358{
359 uint8_t au8Signature[8]; /**< 'RSD PTR ' */
360 uint8_t u8Checksum; /**< checksum for the first 20 bytes */
361 uint8_t au8OemId[6]; /**< OEM-supplied identifier */
362 uint8_t u8Revision; /**< revision number, currently 2 */
363#define ACPI_REVISION 2 /**< ACPI 3.0 */
364 uint32_t u32RSDT; /**< phys addr of RSDT */
365 uint32_t u32Length; /**< bytes of this table */
366 uint64_t u64XSDT; /**< 64-bit phys addr of XSDT */
367 uint8_t u8ExtChecksum; /**< checksum of entire table */
368 uint8_t u8Reserved[3]; /**< reserved */
369};
370AssertCompileSize(ACPITBLRSDP, 36);
371
372/** System Description Table Header */
373struct ACPITBLHEADER
374{
375 uint8_t au8Signature[4]; /**< table identifier */
376 uint32_t u32Length; /**< length of the table including header */
377 uint8_t u8Revision; /**< revision number */
378 uint8_t u8Checksum; /**< all fields inclusive this add to zero */
379 uint8_t au8OemId[6]; /**< OEM-supplied string */
380 uint8_t au8OemTabId[8]; /**< to identify the particular data table */
381 uint32_t u32OemRevision; /**< OEM-supplied revision number */
382 uint8_t au8CreatorId[4]; /**< ID for the ASL compiler */
383 uint32_t u32CreatorRev; /**< revision for the ASL compiler */
384};
385AssertCompileSize(ACPITBLHEADER, 36);
386
387/** Root System Description Table */
388struct ACPITBLRSDT
389{
390 ACPITBLHEADER header;
391 uint32_t u32Entry[1]; /**< array of phys. addresses to other tables */
392};
393AssertCompileSize(ACPITBLRSDT, 40);
394
395/** Extended System Description Table */
396struct ACPITBLXSDT
397{
398 ACPITBLHEADER header;
399 uint64_t u64Entry[1]; /**< array of phys. addresses to other tables */
400};
401AssertCompileSize(ACPITBLXSDT, 44);
402
403/** Fixed ACPI Description Table */
404struct ACPITBLFADT
405{
406 ACPITBLHEADER header;
407 uint32_t u32FACS; /**< phys. address of FACS */
408 uint32_t u32DSDT; /**< phys. address of DSDT */
409 uint8_t u8IntModel; /**< was eleminated in ACPI 2.0 */
410#define INT_MODEL_DUAL_PIC 1 /**< for ACPI 2+ */
411#define INT_MODEL_MULTIPLE_APIC 2
412 uint8_t u8PreferredPMProfile; /**< preferred power management profile */
413 uint16_t u16SCIInt; /**< system vector the SCI is wired in 8259 mode */
414#define SCI_INT 9
415 uint32_t u32SMICmd; /**< system port address of SMI command port */
416#define SMI_CMD 0x0000442e
417 uint8_t u8AcpiEnable; /**< SMICmd val to disable ownership of ACPIregs */
418#define ACPI_ENABLE 0xa1
419 uint8_t u8AcpiDisable; /**< SMICmd val to re-enable ownership of ACPIregs */
420#define ACPI_DISABLE 0xa0
421 uint8_t u8S4BIOSReq; /**< SMICmd val to enter S4BIOS state */
422 uint8_t u8PStateCnt; /**< SMICmd val to assume processor performance
423 state control responsibility */
424 uint32_t u32PM1aEVTBLK; /**< port addr of PM1a event regs block */
425 uint32_t u32PM1bEVTBLK; /**< port addr of PM1b event regs block */
426 uint32_t u32PM1aCTLBLK; /**< port addr of PM1a control regs block */
427 uint32_t u32PM1bCTLBLK; /**< port addr of PM1b control regs block */
428 uint32_t u32PM2CTLBLK; /**< port addr of PM2 control regs block */
429 uint32_t u32PMTMRBLK; /**< port addr of PMTMR regs block */
430 uint32_t u32GPE0BLK; /**< port addr of gen-purp event 0 regs block */
431 uint32_t u32GPE1BLK; /**< port addr of gen-purp event 1 regs block */
432 uint8_t u8PM1EVTLEN; /**< bytes decoded by PM1a_EVT_BLK. >= 4 */
433 uint8_t u8PM1CTLLEN; /**< bytes decoded by PM1b_CNT_BLK. >= 2 */
434 uint8_t u8PM2CTLLEN; /**< bytes decoded by PM2_CNT_BLK. >= 1 or 0 */
435 uint8_t u8PMTMLEN; /**< bytes decoded by PM_TMR_BLK. ==4 */
436 uint8_t u8GPE0BLKLEN; /**< bytes decoded by GPE0_BLK. %2==0 */
437#define GPE0_BLK_LEN 2
438 uint8_t u8GPE1BLKLEN; /**< bytes decoded by GPE1_BLK. %2==0 */
439#define GPE1_BLK_LEN 0
440 uint8_t u8GPE1BASE; /**< offset of GPE1 based events */
441#define GPE1_BASE 0
442 uint8_t u8CSTCNT; /**< SMICmd val to indicate OS supp for C states */
443 uint16_t u16PLVL2LAT; /**< us to enter/exit C2. >100 => unsupported */
444#define P_LVL2_LAT 101 /**< C2 state not supported */
445 uint16_t u16PLVL3LAT; /**< us to enter/exit C3. >1000 => unsupported */
446#define P_LVL3_LAT 1001 /**< C3 state not supported */
447 uint16_t u16FlushSize; /**< # of flush strides to read to flush dirty
448 lines from any processors memory caches */
449#define FLUSH_SIZE 0 /**< Ignored if WBVIND set in FADT_FLAGS */
450 uint16_t u16FlushStride; /**< cache line width */
451#define FLUSH_STRIDE 0 /**< Ignored if WBVIND set in FADT_FLAGS */
452 uint8_t u8DutyOffset;
453 uint8_t u8DutyWidth;
454 uint8_t u8DayAlarm; /**< RTC CMOS RAM index of day-of-month alarm */
455 uint8_t u8MonAlarm; /**< RTC CMOS RAM index of month-of-year alarm */
456 uint8_t u8Century; /**< RTC CMOS RAM index of century */
457 uint16_t u16IAPCBOOTARCH; /**< IA-PC boot architecture flags */
458#define IAPC_BOOT_ARCH_LEGACY_DEV RT_BIT(0) /**< legacy devices present such as LPT
459 (COM too?) */
460#define IAPC_BOOT_ARCH_8042 RT_BIT(1) /**< legacy keyboard device present */
461#define IAPC_BOOT_ARCH_NO_VGA RT_BIT(2) /**< VGA not present */
462#define IAPC_BOOT_ARCH_NO_MSI RT_BIT(3) /**< OSPM must not enable MSIs on this platform */
463#define IAPC_BOOT_ARCH_NO_ASPM RT_BIT(4) /**< OSPM must not enable ASPM on this platform */
464 uint8_t u8Must0_0; /**< must be 0 */
465 uint32_t u32Flags; /**< fixed feature flags */
466#define FADT_FL_WBINVD RT_BIT(0) /**< emulation of WBINVD available */
467#define FADT_FL_WBINVD_FLUSH RT_BIT(1)
468#define FADT_FL_PROC_C1 RT_BIT(2) /**< 1=C1 supported on all processors */
469#define FADT_FL_P_LVL2_UP RT_BIT(3) /**< 1=C2 works on SMP and UNI systems */
470#define FADT_FL_PWR_BUTTON RT_BIT(4) /**< 1=power button handled as ctrl method dev */
471#define FADT_FL_SLP_BUTTON RT_BIT(5) /**< 1=sleep button handled as ctrl method dev */
472#define FADT_FL_FIX_RTC RT_BIT(6) /**< 0=RTC wake status in fixed register */
473#define FADT_FL_RTC_S4 RT_BIT(7) /**< 1=RTC can wake system from S4 */
474#define FADT_FL_TMR_VAL_EXT RT_BIT(8) /**< 1=TMR_VAL implemented as 32 bit */
475#define FADT_FL_DCK_CAP RT_BIT(9) /**< 0=system cannot support docking */
476#define FADT_FL_RESET_REG_SUP RT_BIT(10) /**< 1=system supports system resets */
477#define FADT_FL_SEALED_CASE RT_BIT(11) /**< 1=case is sealed */
478#define FADT_FL_HEADLESS RT_BIT(12) /**< 1=system cannot detect moni/keyb/mouse */
479#define FADT_FL_CPU_SW_SLP RT_BIT(13)
480#define FADT_FL_PCI_EXT_WAK RT_BIT(14) /**< 1=system supports PCIEXP_WAKE_STS */
481#define FADT_FL_USE_PLATFORM_CLOCK RT_BIT(15) /**< 1=system has ACPI PM timer */
482#define FADT_FL_S4_RTC_STS_VALID RT_BIT(16) /**< 1=RTC_STS flag is valid when waking from S4 */
483#define FADT_FL_REMOVE_POWER_ON_CAPABLE RT_BIT(17) /**< 1=platform can remote power on */
484#define FADT_FL_FORCE_APIC_CLUSTER_MODEL RT_BIT(18)
485#define FADT_FL_FORCE_APIC_PHYS_DEST_MODE RT_BIT(19)
486
487 /** Start of the ACPI 2.0 extension. */
488 ACPIGENADDR ResetReg; /**< ext addr of reset register */
489 uint8_t u8ResetVal; /**< ResetReg value to reset the system */
490#define ACPI_RESET_REG_VAL 0x10
491 uint8_t au8Must0_1[3]; /**< must be 0 */
492 uint64_t u64XFACS; /**< 64-bit phys address of FACS */
493 uint64_t u64XDSDT; /**< 64-bit phys address of DSDT */
494 ACPIGENADDR X_PM1aEVTBLK; /**< ext addr of PM1a event regs block */
495 ACPIGENADDR X_PM1bEVTBLK; /**< ext addr of PM1b event regs block */
496 ACPIGENADDR X_PM1aCTLBLK; /**< ext addr of PM1a control regs block */
497 ACPIGENADDR X_PM1bCTLBLK; /**< ext addr of PM1b control regs block */
498 ACPIGENADDR X_PM2CTLBLK; /**< ext addr of PM2 control regs block */
499 ACPIGENADDR X_PMTMRBLK; /**< ext addr of PMTMR control regs block */
500 ACPIGENADDR X_GPE0BLK; /**< ext addr of GPE1 regs block */
501 ACPIGENADDR X_GPE1BLK; /**< ext addr of GPE1 regs block */
502};
503AssertCompileSize(ACPITBLFADT, 244);
504#define ACPITBLFADT_VERSION1_SIZE RT_OFFSETOF(ACPITBLFADT, ResetReg)
505
506/** Firmware ACPI Control Structure */
507struct ACPITBLFACS
508{
509 uint8_t au8Signature[4]; /**< 'FACS' */
510 uint32_t u32Length; /**< bytes of entire FACS structure >= 64 */
511 uint32_t u32HWSignature; /**< systems HW signature at last boot */
512 uint32_t u32FWVector; /**< address of waking vector */
513 uint32_t u32GlobalLock; /**< global lock to sync HW/SW */
514 uint32_t u32Flags; /**< FACS flags */
515 uint64_t u64X_FWVector; /**< 64-bit waking vector */
516 uint8_t u8Version; /**< version of this table */
517 uint8_t au8Reserved[31]; /**< zero */
518};
519AssertCompileSize(ACPITBLFACS, 64);
520
521/** Processor Local APIC Structure */
522struct ACPITBLLAPIC
523{
524 uint8_t u8Type; /**< 0 = LAPIC */
525 uint8_t u8Length; /**< 8 */
526 uint8_t u8ProcId; /**< processor ID */
527 uint8_t u8ApicId; /**< local APIC ID */
528 uint32_t u32Flags; /**< Flags */
529#define LAPIC_ENABLED 0x1
530};
531AssertCompileSize(ACPITBLLAPIC, 8);
532
533/** I/O APIC Structure */
534struct ACPITBLIOAPIC
535{
536 uint8_t u8Type; /**< 1 == I/O APIC */
537 uint8_t u8Length; /**< 12 */
538 uint8_t u8IOApicId; /**< I/O APIC ID */
539 uint8_t u8Reserved; /**< 0 */
540 uint32_t u32Address; /**< phys address to access I/O APIC */
541 uint32_t u32GSIB; /**< global system interrupt number to start */
542};
543AssertCompileSize(ACPITBLIOAPIC, 12);
544
545/** Interrupt Source Override Structure */
546struct ACPITBLISO
547{
548 uint8_t u8Type; /**< 2 == Interrupt Source Override*/
549 uint8_t u8Length; /**< 10 */
550 uint8_t u8Bus; /**< Bus */
551 uint8_t u8Source; /**< Bus-relative interrupt source (IRQ) */
552 uint32_t u32GSI; /**< Global System Interrupt */
553 uint16_t u16Flags; /**< MPS INTI flags Global */
554};
555AssertCompileSize(ACPITBLISO, 10);
556#define NUMBER_OF_IRQ_SOURCE_OVERRIDES 2
557
558/** HPET Descriptor Structure */
559struct ACPITBLHPET
560{
561 ACPITBLHEADER aHeader;
562 uint32_t u32Id; /**< hardware ID of event timer block
563 [31:16] PCI vendor ID of first timer block
564 [15] legacy replacement IRQ routing capable
565 [14] reserved
566 [13] COUNT_SIZE_CAP counter size
567 [12:8] number of comparators in first timer block
568 [7:0] hardware rev ID */
569 ACPIGENADDR HpetAddr; /**< lower 32-bit base address */
570 uint8_t u32Number; /**< sequence number starting at 0 */
571 uint16_t u32MinTick; /**< minimum clock ticks which can be set without
572 lost interrupts while the counter is programmed
573 to operate in periodic mode. Unit: clock tick. */
574 uint8_t u8Attributes; /**< page protection and OEM attribute. */
575};
576AssertCompileSize(ACPITBLHPET, 56);
577
578/** MCFG Descriptor Structure */
579typedef struct ACPITBLMCFG
580{
581 ACPITBLHEADER aHeader;
582 uint64_t u64Reserved;
583} ACPITBLMCFG;
584AssertCompileSize(ACPITBLMCFG, 44);
585
586/** Number of such entries can be computed from the whole table length in header */
587typedef struct ACPITBLMCFGENTRY
588{
589 uint64_t u64BaseAddress;
590 uint16_t u16PciSegmentGroup;
591 uint8_t u8StartBus;
592 uint8_t u8EndBus;
593 uint32_t u32Reserved;
594} ACPITBLMCFGENTRY;
595AssertCompileSize(ACPITBLMCFGENTRY, 16);
596
597#define PCAT_COMPAT 0x1 /**< system has also a dual-8259 setup */
598
599/** Custom Description Table */
600struct ACPITBLCUST
601{
602 ACPITBLHEADER header;
603 uint8_t au8Data[476];
604};
605AssertCompileSize(ACPITBLCUST, 512);
606
607
608#pragma pack()
609
610
611#ifndef VBOX_DEVICE_STRUCT_TESTCASE /* exclude the rest of the file */
612/*******************************************************************************
613* Internal Functions *
614*******************************************************************************/
615RT_C_DECLS_BEGIN
616PDMBOTHCBDECL(int) acpiPMTmrRead(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t *pu32, unsigned cb);
617RT_C_DECLS_END
618#ifdef IN_RING3
619static int acpiR3PlantTables(ACPIState *pThis);
620#endif
621
622#ifdef IN_RING3
623
624/* SCI IRQ */
625DECLINLINE(void) acpiR3SetIrq(ACPIState *pThis, int level)
626{
627 if (pThis->pm1a_ctl & SCI_EN)
628 PDMDevHlpPCISetIrq(pThis->pDevIns, 0, level);
629}
630
631DECLINLINE(uint32_t) pm1a_pure_en(uint32_t en)
632{
633 return en & ~(RSR_EN | IGN_EN);
634}
635
636DECLINLINE(uint32_t) pm1a_pure_sts(uint32_t sts)
637{
638 return sts & ~(RSR_STS | IGN_STS);
639}
640
641DECLINLINE(int) pm1a_level(ACPIState *pThis)
642{
643 return (pm1a_pure_en(pThis->pm1a_en) & pm1a_pure_sts(pThis->pm1a_sts)) != 0;
644}
645
646DECLINLINE(bool) gpe0_level(ACPIState *pThis)
647{
648 return (pThis->gpe0_en & pThis->gpe0_sts) != 0;
649}
650
651/**
652 * Used by acpiR3PM1aStsWrite, acpiR3PM1aEnWrite, acpiR3PmTimer,
653 * acpiR3Port_PowerBuffonPress and acpiR3Port_SleepButtonPress to
654 * update the GPE0.STS and GPE0.EN registers and trigger IRQs.
655 *
656 * Caller must hold the state lock.
657 *
658 * @param pThis The ACPI instance.
659 * @param sts The new GPE0.STS value.
660 * @param en The new GPE0.EN value.
661 */
662static void apicR3UpdatePm1a(ACPIState *pThis, uint32_t sts, uint32_t en)
663{
664 Assert(PDMCritSectIsOwner(&pThis->CritSect));
665
666 if (gpe0_level(pThis))
667 return;
668
669 int const old_level = pm1a_level(pThis);
670 int const new_level = (pm1a_pure_en(en) & pm1a_pure_sts(sts)) != 0;
671
672 Log(("apicR3UpdatePm1a() old=%x new=%x\n", old_level, new_level));
673
674 pThis->pm1a_en = en;
675 pThis->pm1a_sts = sts;
676
677 if (new_level != old_level)
678 acpiR3SetIrq(pThis, new_level);
679}
680
681/**
682 * Used by acpiR3Gpe0StsWrite, acpiR3Gpe0EnWrite, acpiAttach and acpiDetach to
683 * update the GPE0.STS and GPE0.EN registers and trigger IRQs.
684 *
685 * Caller must hold the state lock.
686 *
687 * @param pThis The ACPI instance.
688 * @param sts The new GPE0.STS value.
689 * @param en The new GPE0.EN value.
690 */
691static void apicR3UpdateGpe0(ACPIState *pThis, uint32_t sts, uint32_t en)
692{
693 Assert(PDMCritSectIsOwner(&pThis->CritSect));
694
695 if (pm1a_level(pThis))
696 return;
697
698 int const old_level = (pThis->gpe0_en & pThis->gpe0_sts) != 0;
699 int const new_level = (en & sts) != 0;
700
701 pThis->gpe0_en = en;
702 pThis->gpe0_sts = sts;
703
704 if (new_level != old_level)
705 acpiR3SetIrq(pThis, new_level);
706}
707
708/**
709 * Used by acpiR3PM1aCtlWrite to power off the VM.
710 *
711 * @param pThis The ACPI instance.
712 * @returns Strict VBox status code.
713 */
714static int acpiR3DoPowerOff(ACPIState *pThis)
715{
716 int rc = PDMDevHlpVMPowerOff(pThis->pDevIns);
717 if (RT_FAILURE(rc))
718 AssertMsgFailed(("Could not power down the VM. rc = %Rrc\n", rc));
719 return rc;
720}
721
722/**
723 * Used by acpiR3PM1aCtlWrite to put the VM to sleep.
724 *
725 * @param pThis The ACPI instance.
726 * @returns Strict VBox status code.
727 */
728static int acpiR3DoSleep(ACPIState *pThis)
729{
730 /* We must set WAK_STS on resume (includes restore) so the guest knows that
731 we've woken up and can continue executing code. The guest is probably
732 reading the PMSTS register in a loop to check this. */
733 int rc;
734 pThis->fSetWakeupOnResume = true;
735 if (pThis->fSuspendToSavedState)
736 {
737 rc = PDMDevHlpVMSuspendSaveAndPowerOff(pThis->pDevIns);
738 if (rc != VERR_NOT_SUPPORTED)
739 AssertRC(rc);
740 else
741 {
742 LogRel(("ACPI: PDMDevHlpVMSuspendSaveAndPowerOff is not supported, falling back to suspend-only\n"));
743 rc = PDMDevHlpVMSuspend(pThis->pDevIns);
744 AssertRC(rc);
745 }
746 }
747 else
748 {
749 rc = PDMDevHlpVMSuspend(pThis->pDevIns);
750 AssertRC(rc);
751 }
752 return rc;
753}
754
755
756/**
757 * @interface_method_impl{PDMIACPIPORT,pfnPowerButtonPress}
758 */
759static DECLCALLBACK(int) acpiR3Port_PowerButtonPress(PPDMIACPIPORT pInterface)
760{
761 ACPIState *pThis = RT_FROM_MEMBER(pInterface, ACPIState, IACPIPort);
762 DEVACPI_LOCK_R3(pThis);
763
764 Log(("acpiR3Port_PowerButtonPress: handled=%d status=%x\n", pThis->fPowerButtonHandled, pThis->pm1a_sts));
765 pThis->fPowerButtonHandled = false;
766 apicR3UpdatePm1a(pThis, pThis->pm1a_sts | PWRBTN_STS, pThis->pm1a_en);
767
768 DEVACPI_UNLOCK(pThis);
769 return VINF_SUCCESS;
770}
771
772/**
773 * @interface_method_impl{PDMIACPIPORT,pfnGetPowerButtonHandled}
774 */
775static DECLCALLBACK(int) acpiR3Port_GetPowerButtonHandled(PPDMIACPIPORT pInterface, bool *pfHandled)
776{
777 ACPIState *pThis = RT_FROM_MEMBER(pInterface, ACPIState, IACPIPort);
778 DEVACPI_LOCK_R3(pThis);
779
780 *pfHandled = pThis->fPowerButtonHandled;
781
782 DEVACPI_UNLOCK(pThis);
783 return VINF_SUCCESS;
784}
785
786/**
787 * @interface_method_impl{PDMIACPIPORT,pfnGetGuestEnteredACPIMode, Check if the
788 * Guest entered into G0 (working) or G1 (sleeping)}
789 */
790static DECLCALLBACK(int) acpiR3Port_GetGuestEnteredACPIMode(PPDMIACPIPORT pInterface, bool *pfEntered)
791{
792 ACPIState *pThis = RT_FROM_MEMBER(pInterface, ACPIState, IACPIPort);
793 DEVACPI_LOCK_R3(pThis);
794
795 *pfEntered = (pThis->pm1a_ctl & SCI_EN) != 0;
796
797 DEVACPI_UNLOCK(pThis);
798 return VINF_SUCCESS;
799}
800
801/**
802 * @interface_method_impl{PDMIACPIPORT,pfnGetCpuStatus}
803 */
804static DECLCALLBACK(int) acpiR3Port_GetCpuStatus(PPDMIACPIPORT pInterface, unsigned uCpu, bool *pfLocked)
805{
806 ACPIState *pThis = RT_FROM_MEMBER(pInterface, ACPIState, IACPIPort);
807 DEVACPI_LOCK_R3(pThis);
808
809 *pfLocked = VMCPUSET_IS_PRESENT(&pThis->CpuSetLocked, uCpu);
810
811 DEVACPI_UNLOCK(pThis);
812 return VINF_SUCCESS;
813}
814
815/**
816 * Send an ACPI sleep button event.
817 *
818 * @returns VBox status code
819 * @param pInterface Pointer to the interface structure containing the called function pointer.
820 */
821static DECLCALLBACK(int) acpiR3Port_SleepButtonPress(PPDMIACPIPORT pInterface)
822{
823 ACPIState *pThis = RT_FROM_MEMBER(pInterface, ACPIState, IACPIPort);
824 DEVACPI_LOCK_R3(pThis);
825
826 apicR3UpdatePm1a(pThis, pThis->pm1a_sts | SLPBTN_STS, pThis->pm1a_en);
827
828 DEVACPI_UNLOCK(pThis);
829 return VINF_SUCCESS;
830}
831
832/**
833 * Used by acpiR3PmTimer to re-arm the PM timer.
834 *
835 * The caller is expected to either hold the clock lock or to have made sure
836 * the VM is resetting or loading state.
837 *
838 * @param pThis The ACPI instance.
839 * @param uNow The current time.
840 */
841static void acpiR3PmTimerReset(ACPIState *pThis, uint64_t uNow)
842{
843 uint64_t uTimerFreq = TMTimerGetFreq(pThis->CTX_SUFF(pPmTimer));
844 uint64_t uInterval = ASMMultU64ByU32DivByU32(0xffffffff, uTimerFreq, PM_TMR_FREQ);
845 TMTimerSet(pThis->pPmTimerR3, uNow + uInterval);
846 Log(("acpi: uInterval = %RU64\n", uInterval));
847}
848
849/**
850 * @callback_method_impl{FNTMTIMERDEV, PM Timer callback}
851 */
852static DECLCALLBACK(void) acpiR3PmTimer(PPDMDEVINS pDevIns, PTMTIMER pTimer, void *pvUser)
853{
854 ACPIState *pThis = (ACPIState *)pvUser;
855 Assert(TMTimerIsLockOwner(pTimer));
856 NOREF(pDevIns);
857
858 DEVACPI_LOCK_R3(pThis);
859 Log(("acpi: pm timer sts %#x (%d), en %#x (%d)\n",
860 pThis->pm1a_sts, (pThis->pm1a_sts & TMR_STS) != 0,
861 pThis->pm1a_en, (pThis->pm1a_en & TMR_EN) != 0));
862 apicR3UpdatePm1a(pThis, pThis->pm1a_sts | TMR_STS, pThis->pm1a_en);
863 DEVACPI_UNLOCK(pThis);
864
865 acpiR3PmTimerReset(pThis, TMTimerGet(pTimer));
866}
867
868/**
869 * _BST method - used by acpiR3BatDataRead to implement BAT_STATUS_STATE and
870 * acpiR3LoadState.
871 *
872 * @returns VINF_SUCCESS.
873 * @param pThis The ACPI instance.
874 */
875static int acpiR3FetchBatteryStatus(ACPIState *pThis)
876{
877 uint32_t *p = pThis->au8BatteryInfo;
878 bool fPresent; /* battery present? */
879 PDMACPIBATCAPACITY hostRemainingCapacity; /* 0..100 */
880 PDMACPIBATSTATE hostBatteryState; /* bitfield */
881 uint32_t hostPresentRate; /* 0..1000 */
882 int rc;
883
884 if (!pThis->pDrv)
885 return VINF_SUCCESS;
886 rc = pThis->pDrv->pfnQueryBatteryStatus(pThis->pDrv, &fPresent, &hostRemainingCapacity,
887 &hostBatteryState, &hostPresentRate);
888 AssertRC(rc);
889
890 /* default values */
891 p[BAT_STATUS_STATE] = hostBatteryState;
892 p[BAT_STATUS_PRESENT_RATE] = hostPresentRate == ~0U ? 0xFFFFFFFF
893 : hostPresentRate * 50; /* mW */
894 p[BAT_STATUS_REMAINING_CAPACITY] = 50000; /* mWh */
895 p[BAT_STATUS_PRESENT_VOLTAGE] = 10000; /* mV */
896
897 /* did we get a valid battery state? */
898 if (hostRemainingCapacity != PDM_ACPI_BAT_CAPACITY_UNKNOWN)
899 p[BAT_STATUS_REMAINING_CAPACITY] = hostRemainingCapacity * 500; /* mWh */
900 if (hostBatteryState == PDM_ACPI_BAT_STATE_CHARGED)
901 p[BAT_STATUS_PRESENT_RATE] = 0; /* mV */
902
903 return VINF_SUCCESS;
904}
905
906/**
907 * _BIF method - used by acpiR3BatDataRead to implement BAT_INFO_UNITS and
908 * acpiR3LoadState.
909 *
910 * @returns VINF_SUCCESS.
911 * @param pThis The ACPI instance.
912 */
913static int acpiR3FetchBatteryInfo(ACPIState *pThis)
914{
915 uint32_t *p = pThis->au8BatteryInfo;
916
917 p[BAT_INFO_UNITS] = 0; /* mWh */
918 p[BAT_INFO_DESIGN_CAPACITY] = 50000; /* mWh */
919 p[BAT_INFO_LAST_FULL_CHARGE_CAPACITY] = 50000; /* mWh */
920 p[BAT_INFO_TECHNOLOGY] = BAT_TECH_PRIMARY;
921 p[BAT_INFO_DESIGN_VOLTAGE] = 10000; /* mV */
922 p[BAT_INFO_DESIGN_CAPACITY_OF_WARNING] = 100; /* mWh */
923 p[BAT_INFO_DESIGN_CAPACITY_OF_LOW] = 50; /* mWh */
924 p[BAT_INFO_CAPACITY_GRANULARITY_1] = 1; /* mWh */
925 p[BAT_INFO_CAPACITY_GRANULARITY_2] = 1; /* mWh */
926
927 return VINF_SUCCESS;
928}
929
930/**
931 * The _STA method - used by acpiR3BatDataRead to implement BAT_DEVICE_STATUS.
932 *
933 * @returns status mask or 0.
934 * @param pThis The ACPI instance.
935 */
936static uint32_t acpiR3GetBatteryDeviceStatus(ACPIState *pThis)
937{
938 bool fPresent; /* battery present? */
939 PDMACPIBATCAPACITY hostRemainingCapacity; /* 0..100 */
940 PDMACPIBATSTATE hostBatteryState; /* bitfield */
941 uint32_t hostPresentRate; /* 0..1000 */
942 int rc;
943
944 if (!pThis->pDrv)
945 return 0;
946 rc = pThis->pDrv->pfnQueryBatteryStatus(pThis->pDrv, &fPresent, &hostRemainingCapacity,
947 &hostBatteryState, &hostPresentRate);
948 AssertRC(rc);
949
950 return fPresent
951 ? STA_DEVICE_PRESENT_MASK /* present */
952 | STA_DEVICE_ENABLED_MASK /* enabled and decodes its resources */
953 | STA_DEVICE_SHOW_IN_UI_MASK /* should be shown in UI */
954 | STA_DEVICE_FUNCTIONING_PROPERLY_MASK /* functioning properly */
955 | STA_BATTERY_PRESENT_MASK /* battery is present */
956 : 0; /* device not present */
957}
958
959/**
960 * Used by acpiR3BatDataRead to implement BAT_POWER_SOURCE.
961 *
962 * @returns status.
963 * @param pThis The ACPI instance.
964 */
965static uint32_t acpiR3GetPowerSource(ACPIState *pThis)
966{
967 /* query the current power source from the host driver */
968 if (!pThis->pDrv)
969 return AC_ONLINE;
970
971 PDMACPIPOWERSOURCE ps;
972 int rc = pThis->pDrv->pfnQueryPowerSource(pThis->pDrv, &ps);
973 AssertRC(rc);
974 return ps == PDM_ACPI_POWER_SOURCE_BATTERY ? AC_OFFLINE : AC_ONLINE;
975}
976
977/**
978 * @callback_method_impl{FNIOMIOPORTOUT, Battery status index}
979 */
980PDMBOTHCBDECL(int) acpiR3BatIndexWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb)
981{
982 Log(("acpiR3BatIndexWrite: %#x (%#x)\n", u32, u32 >> 2));
983 if (cb != 4)
984 return PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "cb=%d Port=%u u32=%#x\n", cb, Port, u32);
985
986 ACPIState *pThis = (ACPIState *)pvUser;
987 DEVACPI_LOCK_R3(pThis);
988
989 u32 >>= pThis->u8IndexShift;
990 /* see comment at the declaration of u8IndexShift */
991 if (pThis->u8IndexShift == 0 && u32 == (BAT_DEVICE_STATUS << 2))
992 {
993 pThis->u8IndexShift = 2;
994 u32 >>= 2;
995 }
996 Assert(u32 < BAT_INDEX_LAST);
997 pThis->uBatteryIndex = u32;
998
999 DEVACPI_UNLOCK(pThis);
1000 return VINF_SUCCESS;
1001}
1002
1003/**
1004 * @callback_method_impl{FNIOMIOPORTIN, Battery status data}
1005 */
1006PDMBOTHCBDECL(int) acpiR3BatDataRead(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t *pu32, unsigned cb)
1007{
1008 if (cb != 4)
1009 return VERR_IOM_IOPORT_UNUSED;
1010
1011 ACPIState *pThis = (ACPIState *)pvUser;
1012 DEVACPI_LOCK_R3(pThis);
1013
1014 int rc = VINF_SUCCESS;
1015 switch (pThis->uBatteryIndex)
1016 {
1017 case BAT_STATUS_STATE:
1018 acpiR3FetchBatteryStatus(pThis);
1019 /* fall thru */
1020 case BAT_STATUS_PRESENT_RATE:
1021 case BAT_STATUS_REMAINING_CAPACITY:
1022 case BAT_STATUS_PRESENT_VOLTAGE:
1023 *pu32 = pThis->au8BatteryInfo[pThis->uBatteryIndex];
1024 break;
1025
1026 case BAT_INFO_UNITS:
1027 acpiR3FetchBatteryInfo(pThis);
1028 /* fall thru */
1029 case BAT_INFO_DESIGN_CAPACITY:
1030 case BAT_INFO_LAST_FULL_CHARGE_CAPACITY:
1031 case BAT_INFO_TECHNOLOGY:
1032 case BAT_INFO_DESIGN_VOLTAGE:
1033 case BAT_INFO_DESIGN_CAPACITY_OF_WARNING:
1034 case BAT_INFO_DESIGN_CAPACITY_OF_LOW:
1035 case BAT_INFO_CAPACITY_GRANULARITY_1:
1036 case BAT_INFO_CAPACITY_GRANULARITY_2:
1037 *pu32 = pThis->au8BatteryInfo[pThis->uBatteryIndex];
1038 break;
1039
1040 case BAT_DEVICE_STATUS:
1041 *pu32 = acpiR3GetBatteryDeviceStatus(pThis);
1042 break;
1043
1044 case BAT_POWER_SOURCE:
1045 *pu32 = acpiR3GetPowerSource(pThis);
1046 break;
1047
1048 default:
1049 rc = PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "cb=%d Port=%u idx=%u\n", cb, Port, pThis->uBatteryIndex);
1050 *pu32 = UINT32_MAX;
1051 break;
1052 }
1053
1054 DEVACPI_UNLOCK(pThis);
1055 return rc;
1056}
1057
1058/**
1059 * @callback_method_impl{FNIOMIOPORTOUT, System info index}
1060 */
1061PDMBOTHCBDECL(int) acpiR3SysInfoIndexWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb)
1062{
1063 Log(("acpiR3SysInfoIndexWrite: %#x (%#x)\n", u32, u32 >> 2));
1064 if (cb != 4)
1065 return PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "cb=%d Port=%u u32=%#x\n", cb, Port, u32);
1066
1067 ACPIState *pThis = (ACPIState *)pvUser;
1068 DEVACPI_LOCK_R3(pThis);
1069
1070 if (u32 == SYSTEM_INFO_INDEX_VALID || u32 == SYSTEM_INFO_INDEX_INVALID)
1071 pThis->uSystemInfoIndex = u32;
1072 else
1073 {
1074 /* see comment at the declaration of u8IndexShift */
1075 if (u32 > SYSTEM_INFO_INDEX_END && pThis->u8IndexShift == 0)
1076 {
1077 if ((u32 >> 2) < SYSTEM_INFO_INDEX_END && (u32 & 0x3) == 0)
1078 pThis->u8IndexShift = 2;
1079 }
1080
1081 u32 >>= pThis->u8IndexShift;
1082 Assert(u32 < SYSTEM_INFO_INDEX_END);
1083 pThis->uSystemInfoIndex = u32;
1084 }
1085
1086 DEVACPI_UNLOCK(pThis);
1087 return VINF_SUCCESS;
1088}
1089
1090/**
1091 * @callback_method_impl{FNIOMIOPORTIN, System info data}
1092 */
1093PDMBOTHCBDECL(int) acpiR3SysInfoDataRead(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t *pu32, unsigned cb)
1094{
1095 if (cb != 4)
1096 return VERR_IOM_IOPORT_UNUSED;
1097
1098 ACPIState *pThis = (ACPIState *)pvUser;
1099 DEVACPI_LOCK_R3(pThis);
1100
1101 int rc = VINF_SUCCESS;
1102 uint32_t const uSystemInfoIndex = pThis->uSystemInfoIndex;
1103 switch (uSystemInfoIndex)
1104 {
1105 case SYSTEM_INFO_INDEX_LOW_MEMORY_LENGTH:
1106 *pu32 = pThis->cbRamLow;
1107 break;
1108
1109 case SYSTEM_INFO_INDEX_HIGH_MEMORY_LENGTH:
1110 *pu32 = pThis->cbRamHigh >> 16; /* 64KB units */
1111 Assert(((uint64_t)*pu32 << 16) == pThis->cbRamHigh);
1112 break;
1113
1114 case SYSTEM_INFO_INDEX_USE_IOAPIC:
1115 *pu32 = pThis->u8UseIOApic;
1116 break;
1117
1118 case SYSTEM_INFO_INDEX_HPET_STATUS:
1119 *pu32 = pThis->fUseHpet
1120 ? ( STA_DEVICE_PRESENT_MASK
1121 | STA_DEVICE_ENABLED_MASK
1122 | STA_DEVICE_SHOW_IN_UI_MASK
1123 | STA_DEVICE_FUNCTIONING_PROPERLY_MASK)
1124 : 0;
1125 break;
1126
1127 case SYSTEM_INFO_INDEX_SMC_STATUS:
1128 *pu32 = pThis->fUseSmc
1129 ? ( STA_DEVICE_PRESENT_MASK
1130 | STA_DEVICE_ENABLED_MASK
1131 /* no need to show this device in the UI */
1132 | STA_DEVICE_FUNCTIONING_PROPERLY_MASK)
1133 : 0;
1134 break;
1135
1136 case SYSTEM_INFO_INDEX_FDC_STATUS:
1137 *pu32 = pThis->fUseFdc
1138 ? ( STA_DEVICE_PRESENT_MASK
1139 | STA_DEVICE_ENABLED_MASK
1140 | STA_DEVICE_SHOW_IN_UI_MASK
1141 | STA_DEVICE_FUNCTIONING_PROPERLY_MASK)
1142 : 0;
1143 break;
1144
1145 case SYSTEM_INFO_INDEX_NIC_ADDRESS:
1146 *pu32 = pThis->u32NicPciAddress;
1147 break;
1148
1149 case SYSTEM_INFO_INDEX_AUDIO_ADDRESS:
1150 *pu32 = pThis->u32AudioPciAddress;
1151 break;
1152
1153 case SYSTEM_INFO_INDEX_POWER_STATES:
1154 *pu32 = RT_BIT(0) | RT_BIT(5); /* S1 and S5 always exposed */
1155 if (pThis->fS1Enabled) /* Optionally expose S1 and S4 */
1156 *pu32 |= RT_BIT(1);
1157 if (pThis->fS4Enabled)
1158 *pu32 |= RT_BIT(4);
1159 break;
1160
1161 case SYSTEM_INFO_INDEX_IOC_ADDRESS:
1162 *pu32 = pThis->u32IocPciAddress;
1163 break;
1164
1165 case SYSTEM_INFO_INDEX_HBC_ADDRESS:
1166 *pu32 = pThis->u32HbcPciAddress;
1167 break;
1168
1169 case SYSTEM_INFO_INDEX_PCI_BASE:
1170 /** @todo couldn't MCFG be in 64-bit range? */
1171 Assert(pThis->u64PciConfigMMioAddress < 0xffffffff);
1172 *pu32 = (uint32_t)pThis->u64PciConfigMMioAddress;
1173 break;
1174
1175 case SYSTEM_INFO_INDEX_PCI_LENGTH:
1176 /** @todo couldn't MCFG be in 64-bit range? */
1177 Assert(pThis->u64PciConfigMMioLength< 0xffffffff);
1178 *pu32 = (uint32_t)pThis->u64PciConfigMMioLength;
1179 break;
1180
1181 /* This is only for compatibility with older saved states that
1182 may include ACPI code that read these values. Legacy is
1183 a wonderful thing, isn't it? :-) */
1184 case SYSTEM_INFO_INDEX_CPU0_STATUS:
1185 case SYSTEM_INFO_INDEX_CPU1_STATUS:
1186 case SYSTEM_INFO_INDEX_CPU2_STATUS:
1187 case SYSTEM_INFO_INDEX_CPU3_STATUS:
1188 *pu32 = ( pThis->fShowCpu
1189 && pThis->uSystemInfoIndex - SYSTEM_INFO_INDEX_CPU0_STATUS < pThis->cCpus
1190 && VMCPUSET_IS_PRESENT(&pThis->CpuSetAttached,
1191 pThis->uSystemInfoIndex - SYSTEM_INFO_INDEX_CPU0_STATUS) )
1192 ? ( STA_DEVICE_PRESENT_MASK
1193 | STA_DEVICE_ENABLED_MASK
1194 | STA_DEVICE_SHOW_IN_UI_MASK
1195 | STA_DEVICE_FUNCTIONING_PROPERLY_MASK)
1196 : 0;
1197 break;
1198
1199 case SYSTEM_INFO_INDEX_RTC_STATUS:
1200 *pu32 = pThis->fShowRtc
1201 ? ( STA_DEVICE_PRESENT_MASK
1202 | STA_DEVICE_ENABLED_MASK
1203 | STA_DEVICE_SHOW_IN_UI_MASK
1204 | STA_DEVICE_FUNCTIONING_PROPERLY_MASK)
1205 : 0;
1206 break;
1207
1208 case SYSTEM_INFO_INDEX_CPU_LOCKED:
1209 if (pThis->idCpuLockCheck < VMM_MAX_CPU_COUNT)
1210 {
1211 *pu32 = VMCPUSET_IS_PRESENT(&pThis->CpuSetLocked, pThis->idCpuLockCheck);
1212 pThis->idCpuLockCheck = UINT32_C(0xffffffff); /* Make the entry invalid */
1213 }
1214 else
1215 {
1216 rc = PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "CPU lock check protocol violation (idCpuLockCheck=%#x)\n",
1217 pThis->idCpuLockCheck);
1218 /* Always return locked status just to be safe */
1219 *pu32 = 1;
1220 }
1221 break;
1222
1223 case SYSTEM_INFO_INDEX_CPU_EVENT_TYPE:
1224 *pu32 = pThis->u32CpuEventType;
1225 break;
1226
1227 case SYSTEM_INFO_INDEX_CPU_EVENT:
1228 *pu32 = pThis->u32CpuEvent;
1229 break;
1230
1231 case SYSTEM_INFO_INDEX_SERIAL0_IOBASE:
1232 *pu32 = pThis->uSerial0IoPortBase;
1233 break;
1234
1235 case SYSTEM_INFO_INDEX_SERIAL0_IRQ:
1236 *pu32 = pThis->uSerial0Irq;
1237 break;
1238
1239 case SYSTEM_INFO_INDEX_SERIAL1_IOBASE:
1240 *pu32 = pThis->uSerial1IoPortBase;
1241 break;
1242
1243 case SYSTEM_INFO_INDEX_SERIAL1_IRQ:
1244 *pu32 = pThis->uSerial1Irq;
1245 break;
1246
1247 case SYSTEM_INFO_INDEX_END:
1248 /** @todo why isn't this setting any output value? */
1249 break;
1250
1251 /* Solaris 9 tries to read from this index */
1252 case SYSTEM_INFO_INDEX_INVALID:
1253 *pu32 = 0;
1254 break;
1255
1256 default:
1257 *pu32 = UINT32_MAX;
1258 rc = PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "cb=%d Port=%u idx=%u\n", cb, Port, pThis->uBatteryIndex);
1259 break;
1260 }
1261
1262 DEVACPI_UNLOCK(pThis);
1263 Log(("acpiR3SysInfoDataRead: idx=%d val=%#x (%d) rc=%Rrc\n", uSystemInfoIndex, *pu32, *pu32, rc));
1264 return rc;
1265}
1266
1267/**
1268 * @callback_method_impl{FNIOMIOPORTOUT, System info data}
1269 */
1270PDMBOTHCBDECL(int) acpiR3SysInfoDataWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb)
1271{
1272 ACPIState *pThis = (ACPIState *)pvUser;
1273 if (cb != 4)
1274 return PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "cb=%d Port=%u u32=%#x idx=%u\n", cb, Port, u32, pThis->uSystemInfoIndex);
1275
1276 DEVACPI_LOCK_R3(pThis);
1277 Log(("addr=%#x cb=%d u32=%#x si=%#x\n", Port, cb, u32, pThis->uSystemInfoIndex));
1278
1279 int rc = VINF_SUCCESS;
1280 switch (pThis->uSystemInfoIndex)
1281 {
1282 case SYSTEM_INFO_INDEX_INVALID:
1283 AssertMsg(u32 == 0xbadc0de, ("u32=%u\n", u32));
1284 pThis->u8IndexShift = 0;
1285 break;
1286
1287 case SYSTEM_INFO_INDEX_VALID:
1288 AssertMsg(u32 == 0xbadc0de, ("u32=%u\n", u32));
1289 pThis->u8IndexShift = 2;
1290 break;
1291
1292 case SYSTEM_INFO_INDEX_CPU_LOCK_CHECK:
1293 pThis->idCpuLockCheck = u32;
1294 break;
1295
1296 case SYSTEM_INFO_INDEX_CPU_LOCKED:
1297 if (u32 < pThis->cCpus)
1298 VMCPUSET_DEL(&pThis->CpuSetLocked, u32); /* Unlock the CPU */
1299 else
1300 LogRel(("ACPI: CPU %u does not exist\n", u32));
1301 break;
1302
1303 default:
1304 rc = PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "cb=%d Port=%u u32=%#x idx=%u\n", cb, Port, u32, pThis->uSystemInfoIndex);
1305 break;
1306 }
1307
1308 DEVACPI_UNLOCK(pThis);
1309 return rc;
1310}
1311
1312/**
1313 * @callback_method_impl{FNIOMIOPORTIN, PM1a Enable}
1314 */
1315PDMBOTHCBDECL(int) acpiR3Pm1aEnRead(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t *pu32, unsigned cb)
1316{
1317 NOREF(pDevIns); NOREF(Port);
1318 if (cb != 2)
1319 return VERR_IOM_IOPORT_UNUSED;
1320
1321 ACPIState *pThis = (ACPIState *)pvUser;
1322 DEVACPI_LOCK_R3(pThis);
1323
1324 *pu32 = pThis->pm1a_en;
1325
1326 DEVACPI_UNLOCK(pThis);
1327 Log(("acpiR3Pm1aEnRead -> %#x\n", *pu32));
1328 return VINF_SUCCESS;
1329}
1330
1331/**
1332 * @callback_method_impl{FNIOMIOPORTOUT, PM1a Enable}
1333 */
1334PDMBOTHCBDECL(int) acpiR3PM1aEnWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb)
1335{
1336 if (cb != 2 && cb != 4)
1337 return PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "cb=%d Port=%u u32=%#x\n", cb, Port, u32);
1338
1339 ACPIState *pThis = (ACPIState *)pvUser;
1340 DEVACPI_LOCK_R3(pThis);
1341
1342 Log(("acpiR3PM1aEnWrite: %#x (%#x)\n", u32, u32 & ~(RSR_EN | IGN_EN) & 0xffff));
1343 u32 &= ~(RSR_EN | IGN_EN);
1344 u32 &= 0xffff;
1345 apicR3UpdatePm1a(pThis, pThis->pm1a_sts, u32);
1346
1347 DEVACPI_UNLOCK(pThis);
1348 return VINF_SUCCESS;
1349}
1350
1351/**
1352 * @callback_method_impl{FNIOMIOPORTIN, PM1a Status}
1353 */
1354PDMBOTHCBDECL(int) acpiR3Pm1aStsRead(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t *pu32, unsigned cb)
1355{
1356 if (cb != 2)
1357 {
1358 int rc = PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "cb=%d Port=%u\n", cb, Port);
1359 return rc == VINF_SUCCESS ? VERR_IOM_IOPORT_UNUSED : rc;
1360 }
1361
1362 ACPIState *pThis = (ACPIState *)pvUser;
1363 DEVACPI_LOCK_R3(pThis);
1364
1365 *pu32 = pThis->pm1a_sts;
1366
1367 DEVACPI_UNLOCK(pThis);
1368 Log(("acpiR3Pm1aStsRead: %#x\n", *pu32));
1369 return VINF_SUCCESS;
1370}
1371
1372/**
1373 * @callback_method_impl{FNIOMIOPORTOUT, PM1a Status}
1374 */
1375PDMBOTHCBDECL(int) acpiR3PM1aStsWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb)
1376{
1377 if (cb != 2 && cb != 4)
1378 return PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "cb=%d Port=%u u32=%#x\n", cb, Port, u32);
1379
1380 ACPIState *pThis = (ACPIState *)pvUser;
1381 DEVACPI_LOCK_R3(pThis);
1382
1383 Log(("acpiR3PM1aStsWrite: %#x (%#x)\n", u32, u32 & ~(RSR_STS | IGN_STS) & 0xffff));
1384 u32 &= 0xffff;
1385 if (u32 & PWRBTN_STS)
1386 pThis->fPowerButtonHandled = true; /* Remember that the guest handled the last power button event */
1387 u32 = pThis->pm1a_sts & ~(u32 & ~(RSR_STS | IGN_STS));
1388 apicR3UpdatePm1a(pThis, u32, pThis->pm1a_en);
1389
1390 DEVACPI_UNLOCK(pThis);
1391 return VINF_SUCCESS;
1392}
1393
1394/**
1395 * @callback_method_impl{FNIOMIOPORTIN, PM1a Control}
1396 */
1397PDMBOTHCBDECL(int) acpiR3Pm1aCtlRead(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t *pu32, unsigned cb)
1398{
1399 if (cb != 2)
1400 {
1401 int rc = PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "cb=%d Port=%u\n", cb, Port);
1402 return rc == VINF_SUCCESS ? VERR_IOM_IOPORT_UNUSED : rc;
1403 }
1404
1405 ACPIState *pThis = (ACPIState *)pvUser;
1406 DEVACPI_LOCK_R3(pThis);
1407
1408 *pu32 = pThis->pm1a_ctl;
1409
1410 DEVACPI_UNLOCK(pThis);
1411 Log(("acpiR3Pm1aCtlRead: %#x\n", *pu32));
1412 return VINF_SUCCESS;
1413}
1414
1415/**
1416 * @callback_method_impl{FNIOMIOPORTOUT, PM1a Control}
1417 */
1418PDMBOTHCBDECL(int) acpiR3PM1aCtlWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb)
1419{
1420 if (cb != 2 && cb != 4)
1421 return PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "cb=%d Port=%u u32=%#x\n", cb, Port, u32);
1422
1423 ACPIState *pThis = (ACPIState *)pvUser;
1424 DEVACPI_LOCK_R3(pThis);
1425
1426 Log(("acpiR3PM1aCtlWrite: %#x (%#x)\n", u32, u32 & ~(RSR_CNT | IGN_CNT) & 0xffff));
1427 u32 &= 0xffff;
1428 pThis->pm1a_ctl = u32 & ~(RSR_CNT | IGN_CNT);
1429
1430 int rc = VINF_SUCCESS;
1431 uint32_t const uSleepState = (pThis->pm1a_ctl >> SLP_TYPx_SHIFT) & SLP_TYPx_MASK;
1432 if (uSleepState != pThis->uSleepState)
1433 {
1434 pThis->uSleepState = uSleepState;
1435 switch (uSleepState)
1436 {
1437 case 0x00: /* S0 */
1438 break;
1439
1440 case 0x01: /* S1 */
1441 if (pThis->fS1Enabled)
1442 {
1443 LogRel(("Entering S1 power state (powered-on suspend)\n"));
1444 rc = acpiR3DoSleep(pThis);
1445 break;
1446 }
1447 LogRel(("Ignoring guest attempt to enter S1 power state (powered-on suspend)!\n"));
1448 /* fall thru */
1449
1450 case 0x04: /* S4 */
1451 if (pThis->fS4Enabled)
1452 {
1453 LogRel(("Entering S4 power state (suspend to disk)\n"));
1454 rc = acpiR3DoPowerOff(pThis);/* Same behavior as S5 */
1455 break;
1456 }
1457 LogRel(("Ignoring guest attempt to enter S4 power state (suspend to disk)!\n"));
1458 /* fall thru */
1459
1460 case 0x05: /* S5 */
1461 LogRel(("Entering S5 power state (power down)\n"));
1462 rc = acpiR3DoPowerOff(pThis);
1463 break;
1464
1465 default:
1466 rc = PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "Unknown sleep state %#x (u32=%#x)\n", uSleepState, u32);
1467 break;
1468 }
1469 }
1470
1471 DEVACPI_UNLOCK(pThis);
1472 Log(("acpiR3PM1aCtlWrite: rc=%Rrc\n", rc));
1473 return rc;
1474}
1475
1476#endif /* IN_RING3 */
1477
1478/**
1479 * @callback_method_impl{FNIOMIOPORTIN, PMTMR}
1480 *
1481 * @remarks Only I/O port currently implemented in all contexts.
1482 */
1483PDMBOTHCBDECL(int) acpiPMTmrRead(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t *pu32, unsigned cb)
1484{
1485 if (cb != 4)
1486 return VERR_IOM_IOPORT_UNUSED;
1487
1488 ACPIState *pThis = PDMINS_2_DATA(pDevIns, ACPIState *);
1489
1490 /*
1491 * We use the clock lock to serialize access to u64PmTimerInitial and to
1492 * make sure we get a reliable time from the clock.
1493 */
1494 int rc = TMTimerLock(pThis->CTX_SUFF(pPmTimer), VINF_IOM_R3_IOPORT_READ);
1495 if (rc == VINF_SUCCESS)
1496 {
1497 uint64_t const u64PmTimerInitial = pThis->u64PmTimerInitial;
1498 uint64_t u64Now = TMTimerGet(pThis->CTX_SUFF(pPmTimer));
1499 TMTimerUnlock(pThis->CTX_SUFF(pPmTimer));
1500
1501 /*
1502 * Calculate the return value.
1503 */
1504 DBGFTRACE_PDM_U64_TAG(pDevIns, u64Now, "acpi");
1505 uint64_t u64Elapsed = u64Now - u64PmTimerInitial;
1506 *pu32 = ASMMultU64ByU32DivByU32(u64Elapsed, PM_TMR_FREQ, TMTimerGetFreq(pThis->CTX_SUFF(pPmTimer)));
1507 Log(("acpi: acpiPMTmrRead -> %#x\n", *pu32));
1508 }
1509
1510 NOREF(pvUser); NOREF(Port);
1511 return rc;
1512}
1513
1514#ifdef IN_RING3
1515
1516/**
1517 * @callback_method_impl{FNIOMIOPORTIN, GPE0 Status}
1518 */
1519PDMBOTHCBDECL(int) acpiR3Gpe0StsRead(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t *pu32, unsigned cb)
1520{
1521 if (cb != 1)
1522 {
1523 int rc = PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "cb=%d Port=%u\n", cb, Port);
1524 return rc == VINF_SUCCESS ? VERR_IOM_IOPORT_UNUSED : rc;
1525 }
1526
1527 ACPIState *pThis = (ACPIState *)pvUser;
1528 DEVACPI_LOCK_R3(pThis);
1529
1530 *pu32 = pThis->gpe0_sts & 0xff;
1531
1532 DEVACPI_UNLOCK(pThis);
1533 Log(("acpiR3Gpe0StsRead: %#x\n", *pu32));
1534 return VINF_SUCCESS;
1535}
1536
1537/**
1538 * @callback_method_impl{FNIOMIOPORTOUT, GPE0 Status}
1539 */
1540PDMBOTHCBDECL(int) acpiR3Gpe0StsWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb)
1541{
1542 if (cb != 1)
1543 return PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "cb=%d Port=%u u32=%#x\n", cb, Port, u32);
1544
1545 ACPIState *pThis = (ACPIState *)pvUser;
1546 DEVACPI_LOCK_R3(pThis);
1547
1548 Log(("acpiR3Gpe0StsWrite: %#x (%#x)\n", u32, pThis->gpe0_sts & ~u32));
1549 u32 = pThis->gpe0_sts & ~u32;
1550 apicR3UpdateGpe0(pThis, u32, pThis->gpe0_en);
1551
1552 DEVACPI_UNLOCK(pThis);
1553 return VINF_SUCCESS;
1554}
1555
1556/**
1557 * @callback_method_impl{FNIOMIOPORTIN, GPE0 Enable}
1558 */
1559PDMBOTHCBDECL(int) acpiR3Gpe0EnRead(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t *pu32, unsigned cb)
1560{
1561 if (cb != 1)
1562 {
1563 int rc = PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "cb=%d Port=%u\n", cb, Port);
1564 return rc == VINF_SUCCESS ? VERR_IOM_IOPORT_UNUSED : rc;
1565 }
1566
1567 ACPIState *pThis = (ACPIState *)pvUser;
1568 DEVACPI_LOCK_R3(pThis);
1569
1570 *pu32 = pThis->gpe0_en & 0xff;
1571
1572 DEVACPI_UNLOCK(pThis);
1573 Log(("acpiR3Gpe0EnRead: %#x\n", *pu32));
1574 return VINF_SUCCESS;
1575}
1576
1577/**
1578 * @callback_method_impl{FNIOMIOPORTOUT, GPE0 Enable}
1579 */
1580PDMBOTHCBDECL(int) acpiR3Gpe0EnWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb)
1581{
1582 if (cb != 1)
1583 return PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "cb=%d Port=%u u32=%#x\n", cb, Port, u32);
1584
1585 ACPIState *pThis = (ACPIState *)pvUser;
1586 DEVACPI_LOCK_R3(pThis);
1587
1588 Log(("acpiR3Gpe0EnWrite: %#x\n", u32));
1589 apicR3UpdateGpe0(pThis, pThis->gpe0_sts, u32);
1590
1591 DEVACPI_UNLOCK(pThis);
1592 return VINF_SUCCESS;
1593}
1594
1595/**
1596 * @callback_method_impl{FNIOMIOPORTOUT, SMI_CMD}
1597 */
1598PDMBOTHCBDECL(int) acpiR3SmiWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb)
1599{
1600 Log(("acpiR3SmiWrite %#x\n", u32));
1601 if (cb != 1)
1602 return PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "cb=%d Port=%u u32=%#x\n", cb, Port, u32);
1603
1604 ACPIState *pThis = (ACPIState *)pvUser;
1605 DEVACPI_LOCK_R3(pThis);
1606
1607 if (u32 == ACPI_ENABLE)
1608 pThis->pm1a_ctl |= SCI_EN;
1609 else if (u32 == ACPI_DISABLE)
1610 pThis->pm1a_ctl &= ~SCI_EN;
1611 else
1612 Log(("acpiR3SmiWrite: %#x <- unknown value\n", u32));
1613
1614 DEVACPI_UNLOCK(pThis);
1615 return VINF_SUCCESS;
1616}
1617
1618/**
1619 * @{FNIOMIOPORTOUT, ACPI_RESET_BLK}
1620 */
1621PDMBOTHCBDECL(int) acpiR3ResetWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb)
1622{
1623 Log(("acpiR3ResetWrite: %#x\n", u32));
1624 NOREF(pvUser);
1625 if (cb != 1)
1626 return PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "cb=%d Port=%u u32=%#x\n", cb, Port, u32);
1627
1628 /* No state locking required. */
1629 int rc = VINF_SUCCESS;
1630 if (u32 == ACPI_RESET_REG_VAL)
1631 {
1632 LogRel(("Reset initiated by ACPI\n"));
1633 rc = PDMDevHlpVMReset(pDevIns);
1634 }
1635 else
1636 Log(("acpiR3ResetWrite: %#x <- unknown value\n", u32));
1637
1638 return rc;
1639}
1640
1641# ifdef DEBUG_ACPI
1642
1643/**
1644 * @callback_method_impl{FNIOMIOPORTOUT, Debug hex value logger}
1645 */
1646PDMBOTHCBDECL(int) acpiR3DhexWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb)
1647{
1648 NOREF(pvUser);
1649 switch (cb)
1650 {
1651 case 1:
1652 Log(("%#x\n", u32 & 0xff));
1653 break;
1654 case 2:
1655 Log(("%#6x\n", u32 & 0xffff));
1656 case 4:
1657 Log(("%#10x\n", u32));
1658 break;
1659 default:
1660 return PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "cb=%d Port=%u u32=%#x\n", cb, Port, u32);
1661 }
1662 return VINF_SUCCESS;
1663}
1664
1665/**
1666 * @callback_method_impl{FNIOMIOPORTOUT, Debug char logger}
1667 */
1668PDMBOTHCBDECL(int) acpiR3DchrWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb)
1669{
1670 NOREF(pvUser);
1671 switch (cb)
1672 {
1673 case 1:
1674 Log(("%c", u32 & 0xff));
1675 break;
1676 default:
1677 return PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "cb=%d Port=%u u32=%#x\n", cb, Port, u32);
1678 }
1679 return VINF_SUCCESS;
1680}
1681
1682# endif /* DEBUG_ACPI */
1683
1684/**
1685 * Used to calculate the value of a PM I/O port.
1686 *
1687 * @returns The actual I/O port value.
1688 * @param pThis The ACPI instance.
1689 * @param offset The offset into the I/O space, or -1 if invalid.
1690 */
1691static RTIOPORT acpiR3CalcPmPort(ACPIState *pThis, int32_t offset)
1692{
1693 Assert(pThis->uPmIoPortBase != 0);
1694
1695 if (offset == -1)
1696 return 0;
1697
1698 return (RTIOPORT)(pThis->uPmIoPortBase + offset);
1699}
1700
1701/**
1702 * Called by acpiR3LoadState and acpiR3UpdatePmHandlers to register the PM1a, PM
1703 * timer and GPE0 I/O ports.
1704 *
1705 * @returns VBox status code.
1706 * @param pThis The ACPI instance.
1707 */
1708static int acpiR3RegisterPmHandlers(ACPIState *pThis)
1709{
1710 int rc = VINF_SUCCESS;
1711
1712#define R(offset, cnt, writer, reader, description) \
1713 do { \
1714 rc = PDMDevHlpIOPortRegister(pThis->pDevIns, acpiR3CalcPmPort(pThis, offset), cnt, pThis, writer, reader, \
1715 NULL, NULL, description); \
1716 if (RT_FAILURE(rc)) \
1717 return rc; \
1718 } while (0)
1719#define L (GPE0_BLK_LEN / 2)
1720
1721 R(PM1a_EVT_OFFSET+2, 1, acpiR3PM1aEnWrite, acpiR3Pm1aEnRead, "ACPI PM1a Enable");
1722 R(PM1a_EVT_OFFSET, 1, acpiR3PM1aStsWrite, acpiR3Pm1aStsRead, "ACPI PM1a Status");
1723 R(PM1a_CTL_OFFSET, 1, acpiR3PM1aCtlWrite, acpiR3Pm1aCtlRead, "ACPI PM1a Control");
1724 R(PM_TMR_OFFSET, 1, NULL, acpiPMTmrRead, "ACPI PM Timer");
1725 R(GPE0_OFFSET + L, L, acpiR3Gpe0EnWrite, acpiR3Gpe0EnRead, "ACPI GPE0 Enable");
1726 R(GPE0_OFFSET, L, acpiR3Gpe0StsWrite, acpiR3Gpe0StsRead, "ACPI GPE0 Status");
1727#undef L
1728#undef R
1729
1730 /* register RC stuff */
1731 if (pThis->fGCEnabled)
1732 {
1733 rc = PDMDevHlpIOPortRegisterRC(pThis->pDevIns, acpiR3CalcPmPort(pThis, PM_TMR_OFFSET),
1734 1, 0, NULL, "acpiPMTmrRead",
1735 NULL, NULL, "ACPI PM Timer");
1736 AssertRCReturn(rc, rc);
1737 }
1738
1739 /* register R0 stuff */
1740 if (pThis->fR0Enabled)
1741 {
1742 rc = PDMDevHlpIOPortRegisterR0(pThis->pDevIns, acpiR3CalcPmPort(pThis, PM_TMR_OFFSET),
1743 1, 0, NULL, "acpiPMTmrRead",
1744 NULL, NULL, "ACPI PM Timer");
1745 AssertRCReturn(rc, rc);
1746 }
1747
1748 return rc;
1749}
1750
1751/**
1752 * Called by acpiR3LoadState and acpiR3UpdatePmHandlers to unregister the PM1a, PM
1753 * timer and GPE0 I/O ports.
1754 *
1755 * @returns VBox status code.
1756 * @param pThis The ACPI instance.
1757 */
1758static int acpiR3UnregisterPmHandlers(ACPIState *pThis)
1759{
1760#define U(offset, cnt) \
1761 do { \
1762 int rc = PDMDevHlpIOPortDeregister(pThis->pDevIns, acpiR3CalcPmPort(pThis, offset), cnt); \
1763 AssertRCReturn(rc, rc); \
1764 } while (0)
1765#define L (GPE0_BLK_LEN / 2)
1766
1767 U(PM1a_EVT_OFFSET+2, 1);
1768 U(PM1a_EVT_OFFSET, 1);
1769 U(PM1a_CTL_OFFSET, 1);
1770 U(PM_TMR_OFFSET, 1);
1771 U(GPE0_OFFSET + L, L);
1772 U(GPE0_OFFSET, L);
1773#undef L
1774#undef U
1775
1776 return VINF_SUCCESS;
1777}
1778
1779/**
1780 * Called by acpiR3PciConfigWrite and acpiReset to change the location of the
1781 * PM1a, PM timer and GPE0 ports.
1782 *
1783 * @returns VBox status code.
1784 *
1785 * @param pThis The ACPI instance.
1786 * @param NewIoPortBase The new base address of the I/O ports.
1787 */
1788static int acpiR3UpdatePmHandlers(ACPIState *pThis, RTIOPORT NewIoPortBase)
1789{
1790 Log(("acpi: rebasing PM 0x%x -> 0x%x\n", pThis->uPmIoPortBase, NewIoPortBase));
1791 if (NewIoPortBase != pThis->uPmIoPortBase)
1792 {
1793 int rc = acpiR3UnregisterPmHandlers(pThis);
1794 if (RT_FAILURE(rc))
1795 return rc;
1796
1797 pThis->uPmIoPortBase = NewIoPortBase;
1798
1799 rc = acpiR3RegisterPmHandlers(pThis);
1800 if (RT_FAILURE(rc))
1801 return rc;
1802
1803 /* We have to update FADT table acccording to the new base */
1804 rc = acpiR3PlantTables(pThis);
1805 AssertRC(rc);
1806 if (RT_FAILURE(rc))
1807 return rc;
1808 }
1809
1810 return VINF_SUCCESS;
1811}
1812
1813
1814/**
1815 * Saved state structure description, version 4.
1816 */
1817static const SSMFIELD g_AcpiSavedStateFields4[] =
1818{
1819 SSMFIELD_ENTRY(ACPIState, pm1a_en),
1820 SSMFIELD_ENTRY(ACPIState, pm1a_sts),
1821 SSMFIELD_ENTRY(ACPIState, pm1a_ctl),
1822 SSMFIELD_ENTRY(ACPIState, u64PmTimerInitial),
1823 SSMFIELD_ENTRY(ACPIState, gpe0_en),
1824 SSMFIELD_ENTRY(ACPIState, gpe0_sts),
1825 SSMFIELD_ENTRY(ACPIState, uBatteryIndex),
1826 SSMFIELD_ENTRY(ACPIState, uSystemInfoIndex),
1827 SSMFIELD_ENTRY(ACPIState, u64RamSize),
1828 SSMFIELD_ENTRY(ACPIState, u8IndexShift),
1829 SSMFIELD_ENTRY(ACPIState, u8UseIOApic),
1830 SSMFIELD_ENTRY(ACPIState, uSleepState),
1831 SSMFIELD_ENTRY_TERM()
1832};
1833
1834/**
1835 * Saved state structure description, version 5.
1836 */
1837static const SSMFIELD g_AcpiSavedStateFields5[] =
1838{
1839 SSMFIELD_ENTRY(ACPIState, pm1a_en),
1840 SSMFIELD_ENTRY(ACPIState, pm1a_sts),
1841 SSMFIELD_ENTRY(ACPIState, pm1a_ctl),
1842 SSMFIELD_ENTRY(ACPIState, u64PmTimerInitial),
1843 SSMFIELD_ENTRY(ACPIState, gpe0_en),
1844 SSMFIELD_ENTRY(ACPIState, gpe0_sts),
1845 SSMFIELD_ENTRY(ACPIState, uBatteryIndex),
1846 SSMFIELD_ENTRY(ACPIState, uSystemInfoIndex),
1847 SSMFIELD_ENTRY(ACPIState, uSleepState),
1848 SSMFIELD_ENTRY(ACPIState, u8IndexShift),
1849 SSMFIELD_ENTRY(ACPIState, uPmIoPortBase),
1850 SSMFIELD_ENTRY_TERM()
1851};
1852
1853/**
1854 * Saved state structure description, version 6.
1855 */
1856static const SSMFIELD g_AcpiSavedStateFields6[] =
1857{
1858 SSMFIELD_ENTRY(ACPIState, pm1a_en),
1859 SSMFIELD_ENTRY(ACPIState, pm1a_sts),
1860 SSMFIELD_ENTRY(ACPIState, pm1a_ctl),
1861 SSMFIELD_ENTRY(ACPIState, u64PmTimerInitial),
1862 SSMFIELD_ENTRY(ACPIState, gpe0_en),
1863 SSMFIELD_ENTRY(ACPIState, gpe0_sts),
1864 SSMFIELD_ENTRY(ACPIState, uBatteryIndex),
1865 SSMFIELD_ENTRY(ACPIState, uSystemInfoIndex),
1866 SSMFIELD_ENTRY(ACPIState, uSleepState),
1867 SSMFIELD_ENTRY(ACPIState, u8IndexShift),
1868 SSMFIELD_ENTRY(ACPIState, uPmIoPortBase),
1869 SSMFIELD_ENTRY(ACPIState, fSuspendToSavedState),
1870 SSMFIELD_ENTRY_TERM()
1871};
1872
1873
1874/**
1875 * @callback_method_impl{FNSSMDEVSAVEEXEC}
1876 */
1877static DECLCALLBACK(int) acpiR3SaveState(PPDMDEVINS pDevIns, PSSMHANDLE pSSMHandle)
1878{
1879 ACPIState *pThis = PDMINS_2_DATA(pDevIns, ACPIState *);
1880 return SSMR3PutStruct(pSSMHandle, pThis, &g_AcpiSavedStateFields6[0]);
1881}
1882
1883/**
1884 * @callback_method_impl{FNSSMDEVLOADEXEC}
1885 */
1886static DECLCALLBACK(int) acpiR3LoadState(PPDMDEVINS pDevIns, PSSMHANDLE pSSMHandle, uint32_t uVersion, uint32_t uPass)
1887{
1888 ACPIState *pThis = PDMINS_2_DATA(pDevIns, ACPIState *);
1889 Assert(uPass == SSM_PASS_FINAL); NOREF(uPass);
1890
1891 /*
1892 * Unregister PM handlers, will register with actual base after state
1893 * successfully loaded.
1894 */
1895 int rc = acpiR3UnregisterPmHandlers(pThis);
1896 if (RT_FAILURE(rc))
1897 return rc;
1898
1899 switch (uVersion)
1900 {
1901 case 4:
1902 rc = SSMR3GetStruct(pSSMHandle, pThis, &g_AcpiSavedStateFields4[0]);
1903 break;
1904 case 5:
1905 rc = SSMR3GetStruct(pSSMHandle, pThis, &g_AcpiSavedStateFields5[0]);
1906 break;
1907 case 6:
1908 rc = SSMR3GetStruct(pSSMHandle, pThis, &g_AcpiSavedStateFields6[0]);
1909 break;
1910 default:
1911 rc = VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
1912 break;
1913 }
1914 if (RT_SUCCESS(rc))
1915 {
1916 rc = acpiR3RegisterPmHandlers(pThis);
1917 if (RT_FAILURE(rc))
1918 return rc;
1919 rc = acpiR3FetchBatteryStatus(pThis);
1920 if (RT_FAILURE(rc))
1921 return rc;
1922 rc = acpiR3FetchBatteryInfo(pThis);
1923 if (RT_FAILURE(rc))
1924 return rc;
1925 TMTimerLock(pThis->pPmTimerR3, VERR_IGNORED);
1926 acpiR3PmTimerReset(pThis, TMTimerGet(pThis->pPmTimerR3));
1927 TMTimerUnlock(pThis->pPmTimerR3);
1928 }
1929 return rc;
1930}
1931
1932/**
1933 * @interface_method_impl{PDMIBASE,pfnQueryInterface}
1934 */
1935static DECLCALLBACK(void *) acpiR3QueryInterface(PPDMIBASE pInterface, const char *pszIID)
1936{
1937 ACPIState *pThis = RT_FROM_MEMBER(pInterface, ACPIState, IBase);
1938 PDMIBASE_RETURN_INTERFACE(pszIID, PDMIBASE, &pThis->IBase);
1939 PDMIBASE_RETURN_INTERFACE(pszIID, PDMIACPIPORT, &pThis->IACPIPort);
1940 return NULL;
1941}
1942
1943/**
1944 * Calculate the check sum for some ACPI data before planting it.
1945 *
1946 * All the bytes must add up to 0.
1947 *
1948 * @returns check sum.
1949 * @param pvSrc What to check sum.
1950 * @param cbData The amount of data to checksum.
1951 */
1952static uint8_t acpiR3Checksum(const void * const pvSrc, size_t cbData)
1953{
1954 uint8_t const *pbSrc = (uint8_t const *)pvSrc;
1955 uint8_t uSum = 0;
1956 for (size_t i = 0; i < cbData; ++i)
1957 uSum += pbSrc[i];
1958 return -uSum;
1959}
1960
1961/**
1962 * Prepare a ACPI table header.
1963 */
1964static void acpiR3PrepareHeader(ACPIState *pThis, ACPITBLHEADER *header,
1965 const char au8Signature[4],
1966 uint32_t u32Length, uint8_t u8Revision)
1967{
1968 memcpy(header->au8Signature, au8Signature, 4);
1969 header->u32Length = RT_H2LE_U32(u32Length);
1970 header->u8Revision = u8Revision;
1971 memcpy(header->au8OemId, pThis->au8OemId, 6);
1972 memcpy(header->au8OemTabId, "VBOX", 4);
1973 memcpy(header->au8OemTabId+4, au8Signature, 4);
1974 header->u32OemRevision = RT_H2LE_U32(1);
1975 memcpy(header->au8CreatorId, pThis->au8CreatorId, 4);
1976 header->u32CreatorRev = pThis->u32CreatorRev;
1977}
1978
1979/**
1980 * Initialize a generic address structure (ACPIGENADDR).
1981 */
1982static void acpiR3WriteGenericAddr(ACPIGENADDR *g, uint8_t u8AddressSpaceId,
1983 uint8_t u8RegisterBitWidth, uint8_t u8RegisterBitOffset,
1984 uint8_t u8AccessSize, uint64_t u64Address)
1985{
1986 g->u8AddressSpaceId = u8AddressSpaceId;
1987 g->u8RegisterBitWidth = u8RegisterBitWidth;
1988 g->u8RegisterBitOffset = u8RegisterBitOffset;
1989 g->u8AccessSize = u8AccessSize;
1990 g->u64Address = RT_H2LE_U64(u64Address);
1991}
1992
1993/**
1994 * Wrapper around PDMDevHlpPhysWrite used when planting ACPI tables.
1995 */
1996DECLINLINE(void) acpiR3PhysCopy(ACPIState *pThis, RTGCPHYS32 GCPhys32Dst, const void *pvSrc, size_t cbToCopy)
1997{
1998 PDMDevHlpPhysWrite(pThis->pDevIns, GCPhys32Dst, pvSrc, cbToCopy);
1999}
2000
2001/**
2002 * Plant the Differentiated System Description Table (DSDT).
2003 */
2004static void acpiR3SetupDsdt(ACPIState *pThis, RTGCPHYS32 GCPhys32, void *pvPtr, size_t cbDsdt)
2005{
2006 acpiR3PhysCopy(pThis, GCPhys32, pvPtr, cbDsdt);
2007}
2008
2009/**
2010 * Plan the Secondary System Description Table (SSDT).
2011 */
2012static void acpiR3SetupSsdt(ACPIState *pThis, RTGCPHYS32 addr,
2013 void* pPtr, size_t uSsdtLen)
2014{
2015 acpiR3PhysCopy(pThis, addr, pPtr, uSsdtLen);
2016}
2017
2018/**
2019 * Plant the Firmware ACPI Control Structure (FACS).
2020 */
2021static void acpiR3SetupFacs(ACPIState *pThis, RTGCPHYS32 addr)
2022{
2023 ACPITBLFACS facs;
2024
2025 memset(&facs, 0, sizeof(facs));
2026 memcpy(facs.au8Signature, "FACS", 4);
2027 facs.u32Length = RT_H2LE_U32(sizeof(ACPITBLFACS));
2028 facs.u32HWSignature = RT_H2LE_U32(0);
2029 facs.u32FWVector = RT_H2LE_U32(0);
2030 facs.u32GlobalLock = RT_H2LE_U32(0);
2031 facs.u32Flags = RT_H2LE_U32(0);
2032 facs.u64X_FWVector = RT_H2LE_U64(0);
2033 facs.u8Version = 1;
2034
2035 acpiR3PhysCopy(pThis, addr, (const uint8_t *)&facs, sizeof(facs));
2036}
2037
2038/**
2039 * Plant the Fixed ACPI Description Table (FADT aka FACP).
2040 */
2041static void acpiR3SetupFadt(ACPIState *pThis, RTGCPHYS32 GCPhysAcpi1, RTGCPHYS32 GCPhysAcpi2,
2042 RTGCPHYS32 GCPhysFacs, RTGCPHYS GCPhysDsdt)
2043{
2044 ACPITBLFADT fadt;
2045
2046 /* First the ACPI version 2+ version of the structure. */
2047 memset(&fadt, 0, sizeof(fadt));
2048 acpiR3PrepareHeader(pThis, &fadt.header, "FACP", sizeof(fadt), 4);
2049 fadt.u32FACS = RT_H2LE_U32(GCPhysFacs);
2050 fadt.u32DSDT = RT_H2LE_U32(GCPhysDsdt);
2051 fadt.u8IntModel = 0; /* dropped from the ACPI 2.0 spec. */
2052 fadt.u8PreferredPMProfile = 0; /* unspecified */
2053 fadt.u16SCIInt = RT_H2LE_U16(SCI_INT);
2054 fadt.u32SMICmd = RT_H2LE_U32(SMI_CMD);
2055 fadt.u8AcpiEnable = ACPI_ENABLE;
2056 fadt.u8AcpiDisable = ACPI_DISABLE;
2057 fadt.u8S4BIOSReq = 0;
2058 fadt.u8PStateCnt = 0;
2059 fadt.u32PM1aEVTBLK = RT_H2LE_U32(acpiR3CalcPmPort(pThis, PM1a_EVT_OFFSET));
2060 fadt.u32PM1bEVTBLK = RT_H2LE_U32(acpiR3CalcPmPort(pThis, PM1b_EVT_OFFSET));
2061 fadt.u32PM1aCTLBLK = RT_H2LE_U32(acpiR3CalcPmPort(pThis, PM1a_CTL_OFFSET));
2062 fadt.u32PM1bCTLBLK = RT_H2LE_U32(acpiR3CalcPmPort(pThis, PM1b_CTL_OFFSET));
2063 fadt.u32PM2CTLBLK = RT_H2LE_U32(acpiR3CalcPmPort(pThis, PM2_CTL_OFFSET));
2064 fadt.u32PMTMRBLK = RT_H2LE_U32(acpiR3CalcPmPort(pThis, PM_TMR_OFFSET));
2065 fadt.u32GPE0BLK = RT_H2LE_U32(acpiR3CalcPmPort(pThis, GPE0_OFFSET));
2066 fadt.u32GPE1BLK = RT_H2LE_U32(acpiR3CalcPmPort(pThis, GPE1_OFFSET));
2067 fadt.u8PM1EVTLEN = 4;
2068 fadt.u8PM1CTLLEN = 2;
2069 fadt.u8PM2CTLLEN = 0;
2070 fadt.u8PMTMLEN = 4;
2071 fadt.u8GPE0BLKLEN = GPE0_BLK_LEN;
2072 fadt.u8GPE1BLKLEN = GPE1_BLK_LEN;
2073 fadt.u8GPE1BASE = GPE1_BASE;
2074 fadt.u8CSTCNT = 0;
2075 fadt.u16PLVL2LAT = RT_H2LE_U16(P_LVL2_LAT);
2076 fadt.u16PLVL3LAT = RT_H2LE_U16(P_LVL3_LAT);
2077 fadt.u16FlushSize = RT_H2LE_U16(FLUSH_SIZE);
2078 fadt.u16FlushStride = RT_H2LE_U16(FLUSH_STRIDE);
2079 fadt.u8DutyOffset = 0;
2080 fadt.u8DutyWidth = 0;
2081 fadt.u8DayAlarm = 0;
2082 fadt.u8MonAlarm = 0;
2083 fadt.u8Century = 0;
2084 fadt.u16IAPCBOOTARCH = RT_H2LE_U16(IAPC_BOOT_ARCH_LEGACY_DEV | IAPC_BOOT_ARCH_8042);
2085 /** @note WBINVD is required for ACPI versions newer than 1.0 */
2086 fadt.u32Flags = RT_H2LE_U32( FADT_FL_WBINVD
2087 | FADT_FL_FIX_RTC
2088 | FADT_FL_TMR_VAL_EXT
2089 | FADT_FL_RESET_REG_SUP);
2090
2091 /* We have to force physical APIC mode or Linux can't use more than 8 CPUs */
2092 if (pThis->fCpuHotPlug)
2093 fadt.u32Flags |= RT_H2LE_U32(FADT_FL_FORCE_APIC_PHYS_DEST_MODE);
2094
2095 acpiR3WriteGenericAddr(&fadt.ResetReg, 1, 8, 0, 1, ACPI_RESET_BLK);
2096 fadt.u8ResetVal = ACPI_RESET_REG_VAL;
2097 fadt.u64XFACS = RT_H2LE_U64((uint64_t)GCPhysFacs);
2098 fadt.u64XDSDT = RT_H2LE_U64((uint64_t)GCPhysDsdt);
2099 acpiR3WriteGenericAddr(&fadt.X_PM1aEVTBLK, 1, 32, 0, 2, acpiR3CalcPmPort(pThis, PM1a_EVT_OFFSET));
2100 acpiR3WriteGenericAddr(&fadt.X_PM1bEVTBLK, 0, 0, 0, 0, acpiR3CalcPmPort(pThis, PM1b_EVT_OFFSET));
2101 acpiR3WriteGenericAddr(&fadt.X_PM1aCTLBLK, 1, 16, 0, 2, acpiR3CalcPmPort(pThis, PM1a_CTL_OFFSET));
2102 acpiR3WriteGenericAddr(&fadt.X_PM1bCTLBLK, 0, 0, 0, 0, acpiR3CalcPmPort(pThis, PM1b_CTL_OFFSET));
2103 acpiR3WriteGenericAddr(&fadt.X_PM2CTLBLK, 0, 0, 0, 0, acpiR3CalcPmPort(pThis, PM2_CTL_OFFSET));
2104 acpiR3WriteGenericAddr(&fadt.X_PMTMRBLK, 1, 32, 0, 3, acpiR3CalcPmPort(pThis, PM_TMR_OFFSET));
2105 acpiR3WriteGenericAddr(&fadt.X_GPE0BLK, 1, 16, 0, 1, acpiR3CalcPmPort(pThis, GPE0_OFFSET));
2106 acpiR3WriteGenericAddr(&fadt.X_GPE1BLK, 0, 0, 0, 0, acpiR3CalcPmPort(pThis, GPE1_OFFSET));
2107 fadt.header.u8Checksum = acpiR3Checksum(&fadt, sizeof(fadt));
2108 acpiR3PhysCopy(pThis, GCPhysAcpi2, &fadt, sizeof(fadt));
2109
2110 /* Now the ACPI 1.0 version. */
2111 fadt.header.u32Length = ACPITBLFADT_VERSION1_SIZE;
2112 fadt.u8IntModel = INT_MODEL_DUAL_PIC;
2113 fadt.header.u8Checksum = 0; /* Must be zeroed before recalculating checksum! */
2114 fadt.header.u8Checksum = acpiR3Checksum(&fadt, ACPITBLFADT_VERSION1_SIZE);
2115 acpiR3PhysCopy(pThis, GCPhysAcpi1, &fadt, ACPITBLFADT_VERSION1_SIZE);
2116}
2117
2118/**
2119 * Plant the root System Description Table.
2120 *
2121 * The RSDT and XSDT tables are basically identical. The only difference is 32
2122 * vs 64 bits addresses for description headers. RSDT is for ACPI 1.0. XSDT for
2123 * ACPI 2.0 and up.
2124 */
2125static int acpiR3SetupRsdt(ACPIState *pThis, RTGCPHYS32 addr, unsigned int nb_entries, uint32_t *addrs)
2126{
2127 ACPITBLRSDT *rsdt;
2128 const size_t size = sizeof(ACPITBLHEADER) + nb_entries * sizeof(rsdt->u32Entry[0]);
2129
2130 rsdt = (ACPITBLRSDT*)RTMemAllocZ(size);
2131 if (!rsdt)
2132 return PDMDEV_SET_ERROR(pThis->pDevIns, VERR_NO_TMP_MEMORY, N_("Cannot allocate RSDT"));
2133
2134 acpiR3PrepareHeader(pThis, &rsdt->header, "RSDT", (uint32_t)size, 1);
2135 for (unsigned int i = 0; i < nb_entries; ++i)
2136 {
2137 rsdt->u32Entry[i] = RT_H2LE_U32(addrs[i]);
2138 Log(("Setup RSDT: [%d] = %x\n", i, rsdt->u32Entry[i]));
2139 }
2140 rsdt->header.u8Checksum = acpiR3Checksum(rsdt, size);
2141 acpiR3PhysCopy(pThis, addr, rsdt, size);
2142 RTMemFree(rsdt);
2143 return VINF_SUCCESS;
2144}
2145
2146/**
2147 * Plant the Extended System Description Table.
2148 */
2149static int acpiR3SetupXsdt(ACPIState *pThis, RTGCPHYS32 addr, unsigned int nb_entries, uint32_t *addrs)
2150{
2151 ACPITBLXSDT *xsdt;
2152 const size_t size = sizeof(ACPITBLHEADER) + nb_entries * sizeof(xsdt->u64Entry[0]);
2153
2154 xsdt = (ACPITBLXSDT*)RTMemAllocZ(size);
2155 if (!xsdt)
2156 return VERR_NO_TMP_MEMORY;
2157
2158 acpiR3PrepareHeader(pThis, &xsdt->header, "XSDT", (uint32_t)size, 1 /* according to ACPI 3.0 specs */);
2159
2160 if (pThis->fUseCust)
2161 memcpy(xsdt->header.au8OemTabId, pThis->au8OemTabId, 8);
2162
2163 for (unsigned int i = 0; i < nb_entries; ++i)
2164 {
2165 xsdt->u64Entry[i] = RT_H2LE_U64((uint64_t)addrs[i]);
2166 Log(("Setup XSDT: [%d] = %RX64\n", i, xsdt->u64Entry[i]));
2167 }
2168 xsdt->header.u8Checksum = acpiR3Checksum(xsdt, size);
2169 acpiR3PhysCopy(pThis, addr, xsdt, size);
2170 RTMemFree(xsdt);
2171 return VINF_SUCCESS;
2172}
2173
2174/**
2175 * Plant the Root System Description Pointer (RSDP).
2176 */
2177static void acpiR3SetupRsdp(ACPIState *pThis, ACPITBLRSDP *rsdp, RTGCPHYS32 GCPhysRsdt, RTGCPHYS GCPhysXsdt)
2178{
2179 memset(rsdp, 0, sizeof(*rsdp));
2180
2181 /* ACPI 1.0 part (RSDT) */
2182 memcpy(rsdp->au8Signature, "RSD PTR ", 8);
2183 memcpy(rsdp->au8OemId, pThis->au8OemId, 6);
2184 rsdp->u8Revision = ACPI_REVISION;
2185 rsdp->u32RSDT = RT_H2LE_U32(GCPhysRsdt);
2186 rsdp->u8Checksum = acpiR3Checksum(rsdp, RT_OFFSETOF(ACPITBLRSDP, u32Length));
2187
2188 /* ACPI 2.0 part (XSDT) */
2189 rsdp->u32Length = RT_H2LE_U32(sizeof(ACPITBLRSDP));
2190 rsdp->u64XSDT = RT_H2LE_U64(GCPhysXsdt);
2191 rsdp->u8ExtChecksum = acpiR3Checksum(rsdp, sizeof(ACPITBLRSDP));
2192}
2193
2194/**
2195 * Multiple APIC Description Table.
2196 *
2197 * This structure looks somewhat convoluted due layout of MADT table in MP case.
2198 * There extpected to be multiple LAPIC records for each CPU, thus we cannot
2199 * use regular C structure and proxy to raw memory instead.
2200 */
2201class AcpiTableMadt
2202{
2203 /**
2204 * All actual data stored in dynamically allocated memory pointed by this field.
2205 */
2206 uint8_t *m_pbData;
2207 /**
2208 * Number of CPU entries in this MADT.
2209 */
2210 uint32_t m_cCpus;
2211
2212 /**
2213 * Number of interrupt overrides.
2214 */
2215 uint32_t m_cIsos;
2216
2217public:
2218 /**
2219 * Address of ACPI header
2220 */
2221 inline ACPITBLHEADER *header_addr(void) const
2222 {
2223 return (ACPITBLHEADER *)m_pbData;
2224 }
2225
2226 /**
2227 * Address of local APIC for each CPU. Note that different CPUs address different LAPICs,
2228 * although address is the same for all of them.
2229 */
2230 inline uint32_t *u32LAPIC_addr(void) const
2231 {
2232 return (uint32_t *)(header_addr() + 1);
2233 }
2234
2235 /**
2236 * Address of APIC flags
2237 */
2238 inline uint32_t *u32Flags_addr(void) const
2239 {
2240 return (uint32_t *)(u32LAPIC_addr() + 1);
2241 }
2242
2243 /**
2244 * Address of ISO description
2245 */
2246 inline ACPITBLISO *ISO_addr(void) const
2247 {
2248 return (ACPITBLISO *)(u32Flags_addr() + 1);
2249 }
2250
2251 /**
2252 * Address of per-CPU LAPIC descriptions
2253 */
2254 inline ACPITBLLAPIC *LApics_addr(void) const
2255 {
2256 return (ACPITBLLAPIC *)(ISO_addr() + m_cIsos);
2257 }
2258
2259 /**
2260 * Address of IO APIC description
2261 */
2262 inline ACPITBLIOAPIC *IOApic_addr(void) const
2263 {
2264 return (ACPITBLIOAPIC *)(LApics_addr() + m_cCpus);
2265 }
2266
2267 /**
2268 * Size of MADT.
2269 * Note that this function assumes IOApic to be the last field in structure.
2270 */
2271 inline uint32_t size(void) const
2272 {
2273 return (uint8_t *)(IOApic_addr() + 1) - (uint8_t *)header_addr();
2274 }
2275
2276 /**
2277 * Raw data of MADT.
2278 */
2279 inline const uint8_t *data(void) const
2280 {
2281 return m_pbData;
2282 }
2283
2284 /**
2285 * Size of MADT for given ACPI config, useful to compute layout.
2286 */
2287 static uint32_t sizeFor(ACPIState *pThis, uint32_t cIsos)
2288 {
2289 return AcpiTableMadt(pThis->cCpus, cIsos).size();
2290 }
2291
2292 /*
2293 * Constructor, only works in Ring 3, doesn't look like a big deal.
2294 */
2295 AcpiTableMadt(uint32_t cCpus, uint32_t cIsos)
2296 {
2297 m_cCpus = cCpus;
2298 m_cIsos = cIsos;
2299 m_pbData = NULL; /* size() uses this and gcc will complain if not initialized. */
2300 uint32_t cb = size();
2301 m_pbData = (uint8_t *)RTMemAllocZ(cb);
2302 }
2303
2304 ~AcpiTableMadt()
2305 {
2306 RTMemFree(m_pbData);
2307 }
2308};
2309
2310
2311/**
2312 * Plant the Multiple APIC Description Table (MADT).
2313 *
2314 * @note APIC without IO-APIC hangs Windows Vista therefore we setup both.
2315 *
2316 * @todo All hardcoded, should set this up based on the actual VM config!!!!!
2317 */
2318static void acpiR3SetupMadt(ACPIState *pThis, RTGCPHYS32 addr)
2319{
2320 uint16_t cpus = pThis->cCpus;
2321 AcpiTableMadt madt(cpus, NUMBER_OF_IRQ_SOURCE_OVERRIDES);
2322
2323 acpiR3PrepareHeader(pThis, madt.header_addr(), "APIC", madt.size(), 2);
2324
2325 *madt.u32LAPIC_addr() = RT_H2LE_U32(0xfee00000);
2326 *madt.u32Flags_addr() = RT_H2LE_U32(PCAT_COMPAT);
2327
2328 /* LAPICs records */
2329 ACPITBLLAPIC* lapic = madt.LApics_addr();
2330 for (uint16_t i = 0; i < cpus; i++)
2331 {
2332 lapic->u8Type = 0;
2333 lapic->u8Length = sizeof(ACPITBLLAPIC);
2334 lapic->u8ProcId = i;
2335 /** Must match numbering convention in MPTABLES */
2336 lapic->u8ApicId = i;
2337 lapic->u32Flags = VMCPUSET_IS_PRESENT(&pThis->CpuSetAttached, i) ? RT_H2LE_U32(LAPIC_ENABLED) : 0;
2338 lapic++;
2339 }
2340
2341 /* IO-APIC record */
2342 ACPITBLIOAPIC* ioapic = madt.IOApic_addr();
2343 ioapic->u8Type = 1;
2344 ioapic->u8Length = sizeof(ACPITBLIOAPIC);
2345 /** Must match MP tables ID */
2346 ioapic->u8IOApicId = cpus;
2347 ioapic->u8Reserved = 0;
2348 ioapic->u32Address = RT_H2LE_U32(0xfec00000);
2349 ioapic->u32GSIB = RT_H2LE_U32(0);
2350
2351 /* Interrupt Source Overrides */
2352 /* Flags:
2353 bits[3:2]:
2354 00 conforms to the bus
2355 01 edge-triggered
2356 10 reserved
2357 11 level-triggered
2358 bits[1:0]
2359 00 conforms to the bus
2360 01 active-high
2361 10 reserved
2362 11 active-low */
2363 /* If changing, also update PDMIsaSetIrq() and MPS */
2364 ACPITBLISO* isos = madt.ISO_addr();
2365 /* Timer interrupt rule IRQ0 to GSI2 */
2366 isos[0].u8Type = 2;
2367 isos[0].u8Length = sizeof(ACPITBLISO);
2368 isos[0].u8Bus = 0; /* Must be 0 */
2369 isos[0].u8Source = 0; /* IRQ0 */
2370 isos[0].u32GSI = 2; /* connected to pin 2 */
2371 isos[0].u16Flags = 0; /* conform to the bus */
2372
2373 /* ACPI interrupt rule - IRQ9 to GSI9 */
2374 isos[1].u8Type = 2;
2375 isos[1].u8Length = sizeof(ACPITBLISO);
2376 isos[1].u8Bus = 0; /* Must be 0 */
2377 isos[1].u8Source = 9; /* IRQ9 */
2378 isos[1].u32GSI = 9; /* connected to pin 9 */
2379 isos[1].u16Flags = 0xd; /* active high, level triggered */
2380 Assert(NUMBER_OF_IRQ_SOURCE_OVERRIDES == 2);
2381
2382 madt.header_addr()->u8Checksum = acpiR3Checksum(madt.data(), madt.size());
2383 acpiR3PhysCopy(pThis, addr, madt.data(), madt.size());
2384}
2385
2386/**
2387 * Plant the High Performance Event Timer (HPET) descriptor.
2388 */
2389static void acpiR3SetupHpet(ACPIState *pThis, RTGCPHYS32 addr)
2390{
2391 ACPITBLHPET hpet;
2392
2393 memset(&hpet, 0, sizeof(hpet));
2394
2395 acpiR3PrepareHeader(pThis, &hpet.aHeader, "HPET", sizeof(hpet), 1);
2396 /* Keep base address consistent with appropriate DSDT entry (vbox.dsl) */
2397 acpiR3WriteGenericAddr(&hpet.HpetAddr,
2398 0 /* Memory address space */,
2399 64 /* Register bit width */,
2400 0 /* Bit offset */,
2401 0, /* Register access size, is it correct? */
2402 0xfed00000 /* Address */);
2403
2404 hpet.u32Id = 0x8086a201; /* must match what HPET ID returns, is it correct ? */
2405 hpet.u32Number = 0;
2406 hpet.u32MinTick = 4096;
2407 hpet.u8Attributes = 0;
2408
2409 hpet.aHeader.u8Checksum = acpiR3Checksum(&hpet, sizeof(hpet));
2410
2411 acpiR3PhysCopy(pThis, addr, (const uint8_t *)&hpet, sizeof(hpet));
2412}
2413
2414
2415/** Custom Description Table */
2416static void acpiR3SetupCust(ACPIState *pThis, RTGCPHYS32 addr)
2417{
2418 ACPITBLCUST cust;
2419
2420 /* First the ACPI version 1 version of the structure. */
2421 memset(&cust, 0, sizeof(cust));
2422 acpiR3PrepareHeader(pThis, &cust.header, "CUST", sizeof(cust), 1);
2423
2424 memcpy(cust.header.au8OemTabId, pThis->au8OemTabId, 8);
2425 cust.header.u32OemRevision = RT_H2LE_U32(pThis->u32OemRevision);
2426 cust.header.u8Checksum = acpiR3Checksum((uint8_t *)&cust, sizeof(cust));
2427
2428 acpiR3PhysCopy(pThis, addr, pThis->pu8CustBin, pThis->cbCustBin);
2429}
2430
2431/**
2432 * Used by acpiR3PlantTables to plant a MMCONFIG PCI config space access (MCFG)
2433 * descriptor.
2434 *
2435 * @param pThis The ACPI instance.
2436 * @param GCPhysDst Where to plant it.
2437 */
2438static void acpiR3SetupMcfg(ACPIState *pThis, RTGCPHYS32 GCPhysDst)
2439{
2440 struct
2441 {
2442 ACPITBLMCFG hdr;
2443 ACPITBLMCFGENTRY entry;
2444 } tbl;
2445 uint8_t u8StartBus = 0;
2446 uint8_t u8EndBus = (pThis->u64PciConfigMMioLength >> 20) - 1;
2447
2448 RT_ZERO(tbl);
2449
2450 acpiR3PrepareHeader(pThis, &tbl.hdr.aHeader, "MCFG", sizeof(tbl), 1);
2451 tbl.entry.u64BaseAddress = pThis->u64PciConfigMMioAddress;
2452 tbl.entry.u8StartBus = u8StartBus;
2453 tbl.entry.u8EndBus = u8EndBus;
2454 // u16PciSegmentGroup must match _SEG in ACPI table
2455
2456 tbl.hdr.aHeader.u8Checksum = acpiR3Checksum(&tbl, sizeof(tbl));
2457
2458 acpiR3PhysCopy(pThis, GCPhysDst, (const uint8_t *)&tbl, sizeof(tbl));
2459}
2460
2461/**
2462 * Used by acpiR3PlantTables and acpiConstruct.
2463 *
2464 * @returns Guest memory address.
2465 */
2466static uint32_t apicR3FindRsdpSpace(void)
2467{
2468 return 0xe0000;
2469}
2470
2471/**
2472 * Create the ACPI tables in guest memory.
2473 */
2474static int acpiR3PlantTables(ACPIState *pThis)
2475{
2476 int rc;
2477 RTGCPHYS32 GCPhysCur, GCPhysRsdt, GCPhysXsdt, GCPhysFadtAcpi1, GCPhysFadtAcpi2, GCPhysFacs, GCPhysDsdt;
2478 RTGCPHYS32 GCPhysHpet = 0;
2479 RTGCPHYS32 GCPhysApic = 0;
2480 RTGCPHYS32 GCPhysSsdt = 0;
2481 RTGCPHYS32 GCPhysMcfg = 0;
2482 RTGCPHYS32 GCPhysCust = 0;
2483 uint32_t addend = 0;
2484 RTGCPHYS32 aGCPhysRsdt[8];
2485 RTGCPHYS32 aGCPhysXsdt[8];
2486 uint32_t cAddr;
2487 uint32_t iMadt = 0;
2488 uint32_t iHpet = 0;
2489 uint32_t iSsdt = 0;
2490 uint32_t iMcfg = 0;
2491 uint32_t iCust = 0;
2492 size_t cbRsdt = sizeof(ACPITBLHEADER);
2493 size_t cbXsdt = sizeof(ACPITBLHEADER);
2494
2495 cAddr = 1; /* FADT */
2496 if (pThis->u8UseIOApic)
2497 iMadt = cAddr++; /* MADT */
2498
2499 if (pThis->fUseHpet)
2500 iHpet = cAddr++; /* HPET */
2501
2502 if (pThis->fUseMcfg)
2503 iMcfg = cAddr++; /* MCFG */
2504
2505 if (pThis->fUseCust)
2506 iCust = cAddr++; /* CUST */
2507
2508 iSsdt = cAddr++; /* SSDT */
2509
2510 Assert(cAddr < RT_ELEMENTS(aGCPhysRsdt));
2511 Assert(cAddr < RT_ELEMENTS(aGCPhysXsdt));
2512
2513 cbRsdt += cAddr*sizeof(uint32_t); /* each entry: 32 bits phys. address. */
2514 cbXsdt += cAddr*sizeof(uint64_t); /* each entry: 64 bits phys. address. */
2515
2516 rc = CFGMR3QueryU64(pThis->pDevIns->pCfg, "RamSize", &pThis->u64RamSize);
2517 if (RT_FAILURE(rc))
2518 return PDMDEV_SET_ERROR(pThis->pDevIns, rc,
2519 N_("Configuration error: Querying \"RamSize\" as integer failed"));
2520
2521 uint32_t cbRamHole;
2522 rc = CFGMR3QueryU32Def(pThis->pDevIns->pCfg, "RamHoleSize", &cbRamHole, MM_RAM_HOLE_SIZE_DEFAULT);
2523 if (RT_FAILURE(rc))
2524 return PDMDEV_SET_ERROR(pThis->pDevIns, rc,
2525 N_("Configuration error: Querying \"RamHoleSize\" as integer failed"));
2526
2527 /*
2528 * Calculate the sizes for the high and low regions.
2529 */
2530 const uint64_t offRamHole = _4G - cbRamHole;
2531 pThis->cbRamHigh = offRamHole < pThis->u64RamSize ? pThis->u64RamSize - offRamHole : 0;
2532 uint64_t cbRamLow = offRamHole < pThis->u64RamSize ? offRamHole : pThis->u64RamSize;
2533 if (cbRamLow > UINT32_C(0xffe00000)) /* See MEM3. */
2534 {
2535 /* Note: This is also enforced by DevPcBios.cpp. */
2536 LogRel(("DevACPI: Clipping cbRamLow=%#RX64 down to 0xffe00000.\n", cbRamLow));
2537 cbRamLow = UINT32_C(0xffe00000);
2538 }
2539 pThis->cbRamLow = (uint32_t)cbRamLow;
2540
2541 GCPhysCur = 0;
2542 GCPhysRsdt = GCPhysCur;
2543
2544 GCPhysCur = RT_ALIGN_32(GCPhysCur + cbRsdt, 16);
2545 GCPhysXsdt = GCPhysCur;
2546
2547 GCPhysCur = RT_ALIGN_32(GCPhysCur + cbXsdt, 16);
2548 GCPhysFadtAcpi1 = GCPhysCur;
2549
2550 GCPhysCur = RT_ALIGN_32(GCPhysCur + ACPITBLFADT_VERSION1_SIZE, 16);
2551 GCPhysFadtAcpi2 = GCPhysCur;
2552
2553 GCPhysCur = RT_ALIGN_32(GCPhysCur + sizeof(ACPITBLFADT), 64);
2554 GCPhysFacs = GCPhysCur;
2555
2556 GCPhysCur = RT_ALIGN_32(GCPhysCur + sizeof(ACPITBLFACS), 16);
2557 if (pThis->u8UseIOApic)
2558 {
2559 GCPhysApic = GCPhysCur;
2560 GCPhysCur = RT_ALIGN_32(GCPhysCur + AcpiTableMadt::sizeFor(pThis, NUMBER_OF_IRQ_SOURCE_OVERRIDES), 16);
2561 }
2562 if (pThis->fUseHpet)
2563 {
2564 GCPhysHpet = GCPhysCur;
2565 GCPhysCur = RT_ALIGN_32(GCPhysCur + sizeof(ACPITBLHPET), 16);
2566 }
2567 if (pThis->fUseMcfg)
2568 {
2569 GCPhysMcfg = GCPhysCur;
2570 /* Assume one entry */
2571 GCPhysCur = RT_ALIGN_32(GCPhysCur + sizeof(ACPITBLMCFG) + sizeof(ACPITBLMCFGENTRY), 16);
2572 }
2573 if (pThis->fUseCust)
2574 {
2575 GCPhysCust = GCPhysCur;
2576 GCPhysCur = RT_ALIGN_32(GCPhysCur + pThis->cbCustBin, 16);
2577 }
2578
2579 void *pvSsdtCode = NULL;
2580 size_t cbSsdt = 0;
2581 rc = acpiPrepareSsdt(pThis->pDevIns, &pvSsdtCode, &cbSsdt);
2582 if (RT_FAILURE(rc))
2583 return rc;
2584
2585 GCPhysSsdt = GCPhysCur;
2586 GCPhysCur = RT_ALIGN_32(GCPhysCur + cbSsdt, 16);
2587
2588 GCPhysDsdt = GCPhysCur;
2589
2590 void *pvDsdtCode = NULL;
2591 size_t cbDsdt = 0;
2592 rc = acpiPrepareDsdt(pThis->pDevIns, &pvDsdtCode, &cbDsdt);
2593 if (RT_FAILURE(rc))
2594 return rc;
2595
2596 GCPhysCur = RT_ALIGN_32(GCPhysCur + cbDsdt, 16);
2597
2598 if (GCPhysCur > 0x10000)
2599 return PDMDEV_SET_ERROR(pThis->pDevIns, VERR_TOO_MUCH_DATA,
2600 N_("Error: ACPI tables bigger than 64KB"));
2601
2602 Log(("RSDP 0x%08X\n", apicR3FindRsdpSpace()));
2603 addend = pThis->cbRamLow - 0x10000;
2604 Log(("RSDT 0x%08X XSDT 0x%08X\n", GCPhysRsdt + addend, GCPhysXsdt + addend));
2605 Log(("FACS 0x%08X FADT (1.0) 0x%08X, FADT (2+) 0x%08X\n", GCPhysFacs + addend, GCPhysFadtAcpi1 + addend, GCPhysFadtAcpi2 + addend));
2606 Log(("DSDT 0x%08X", GCPhysDsdt + addend));
2607 if (pThis->u8UseIOApic)
2608 Log((" MADT 0x%08X", GCPhysApic + addend));
2609 if (pThis->fUseHpet)
2610 Log((" HPET 0x%08X", GCPhysHpet + addend));
2611 if (pThis->fUseMcfg)
2612 Log((" MCFG 0x%08X", GCPhysMcfg + addend));
2613 if (pThis->fUseCust)
2614 Log((" CUST 0x%08X", GCPhysCust + addend));
2615 Log((" SSDT 0x%08X", GCPhysSsdt + addend));
2616 Log(("\n"));
2617
2618 acpiR3SetupRsdp(pThis, (ACPITBLRSDP *)pThis->au8RSDPPage, GCPhysRsdt + addend, GCPhysXsdt + addend);
2619 acpiR3SetupDsdt(pThis, GCPhysDsdt + addend, pvDsdtCode, cbDsdt);
2620 acpiCleanupDsdt(pThis->pDevIns, pvDsdtCode);
2621 acpiR3SetupFacs(pThis, GCPhysFacs + addend);
2622 acpiR3SetupFadt(pThis, GCPhysFadtAcpi1 + addend, GCPhysFadtAcpi2 + addend, GCPhysFacs + addend, GCPhysDsdt + addend);
2623
2624 aGCPhysRsdt[0] = GCPhysFadtAcpi1 + addend;
2625 aGCPhysXsdt[0] = GCPhysFadtAcpi2 + addend;
2626 if (pThis->u8UseIOApic)
2627 {
2628 acpiR3SetupMadt(pThis, GCPhysApic + addend);
2629 aGCPhysRsdt[iMadt] = GCPhysApic + addend;
2630 aGCPhysXsdt[iMadt] = GCPhysApic + addend;
2631 }
2632 if (pThis->fUseHpet)
2633 {
2634 acpiR3SetupHpet(pThis, GCPhysHpet + addend);
2635 aGCPhysRsdt[iHpet] = GCPhysHpet + addend;
2636 aGCPhysXsdt[iHpet] = GCPhysHpet + addend;
2637 }
2638 if (pThis->fUseMcfg)
2639 {
2640 acpiR3SetupMcfg(pThis, GCPhysMcfg + addend);
2641 aGCPhysRsdt[iMcfg] = GCPhysMcfg + addend;
2642 aGCPhysXsdt[iMcfg] = GCPhysMcfg + addend;
2643 }
2644 if (pThis->fUseCust)
2645 {
2646 acpiR3SetupCust(pThis, GCPhysCust + addend);
2647 aGCPhysRsdt[iCust] = GCPhysCust + addend;
2648 aGCPhysXsdt[iCust] = GCPhysCust + addend;
2649 }
2650
2651 acpiR3SetupSsdt(pThis, GCPhysSsdt + addend, pvSsdtCode, cbSsdt);
2652 acpiCleanupSsdt(pThis->pDevIns, pvSsdtCode);
2653 aGCPhysRsdt[iSsdt] = GCPhysSsdt + addend;
2654 aGCPhysXsdt[iSsdt] = GCPhysSsdt + addend;
2655
2656 rc = acpiR3SetupRsdt(pThis, GCPhysRsdt + addend, cAddr, aGCPhysRsdt);
2657 if (RT_FAILURE(rc))
2658 return rc;
2659 return acpiR3SetupXsdt(pThis, GCPhysXsdt + addend, cAddr, aGCPhysXsdt);
2660}
2661
2662/**
2663 * @callback_method_impl{FNPCICONFIGREAD}
2664 */
2665static DECLCALLBACK(uint32_t) acpiR3PciConfigRead(PPCIDEVICE pPciDev, uint32_t Address, unsigned cb)
2666{
2667 PPDMDEVINS pDevIns = pPciDev->pDevIns;
2668 ACPIState *pThis = PDMINS_2_DATA(pDevIns, ACPIState *);
2669
2670 Log2(("acpi: PCI config read: 0x%x (%d)\n", Address, cb));
2671 return pThis->pfnAcpiPciConfigRead(pPciDev, Address, cb);
2672}
2673
2674/**
2675 * @callback_method_impl{FNPCICONFIGWRITE}
2676 */
2677static DECLCALLBACK(void) acpiR3PciConfigWrite(PPCIDEVICE pPciDev, uint32_t Address, uint32_t u32Value, unsigned cb)
2678{
2679 PPDMDEVINS pDevIns = pPciDev->pDevIns;
2680 ACPIState *pThis = PDMINS_2_DATA(pDevIns, ACPIState *);
2681
2682 Log2(("acpi: PCI config write: 0x%x -> 0x%x (%d)\n", u32Value, Address, cb));
2683 DEVACPI_LOCK_R3(pThis);
2684
2685 if (Address == VBOX_PCI_INTERRUPT_LINE)
2686 {
2687 Log(("acpi: ignore interrupt line settings: %d, we'll use hardcoded value %d\n", u32Value, SCI_INT));
2688 u32Value = SCI_INT;
2689 }
2690
2691 pThis->pfnAcpiPciConfigWrite(pPciDev, Address, u32Value, cb);
2692
2693 /* PMREGMISC written */
2694 if (Address == 0x80)
2695 {
2696 /* Check Power Management IO Space Enable (PMIOSE) bit */
2697 if (pPciDev->config[0x80] & 0x1)
2698 {
2699 RTIOPORT NewIoPortBase = (RTIOPORT)PCIDevGetDWord(pPciDev, 0x40);
2700 NewIoPortBase &= 0xffc0;
2701
2702 int rc = acpiR3UpdatePmHandlers(pThis, NewIoPortBase);
2703 AssertRC(rc);
2704 }
2705 }
2706
2707 DEVACPI_UNLOCK(pThis);
2708}
2709
2710/**
2711 * Attach a new CPU.
2712 *
2713 * @returns VBox status code.
2714 * @param pDevIns The device instance.
2715 * @param iLUN The logical unit which is being attached.
2716 * @param fFlags Flags, combination of the PDMDEVATT_FLAGS_* \#defines.
2717 *
2718 * @remarks This code path is not used during construction.
2719 */
2720static DECLCALLBACK(int) acpiR3Attach(PPDMDEVINS pDevIns, unsigned iLUN, uint32_t fFlags)
2721{
2722 ACPIState *pThis = PDMINS_2_DATA(pDevIns, ACPIState *);
2723 LogFlow(("acpiAttach: pDevIns=%p iLUN=%u fFlags=%#x\n", pDevIns, iLUN, fFlags));
2724
2725 AssertMsgReturn(!(fFlags & PDM_TACH_FLAGS_NOT_HOT_PLUG),
2726 ("Hot-plug flag is not set\n"),
2727 VERR_NOT_SUPPORTED);
2728 AssertReturn(iLUN < VMM_MAX_CPU_COUNT, VERR_PDM_NO_SUCH_LUN);
2729
2730 /* Check if it was already attached */
2731 int rc = VINF_SUCCESS;
2732 DEVACPI_LOCK_R3(pThis);
2733 if (!VMCPUSET_IS_PRESENT(&pThis->CpuSetAttached, iLUN))
2734 {
2735 PPDMIBASE IBaseTmp;
2736 rc = PDMDevHlpDriverAttach(pDevIns, iLUN, &pThis->IBase, &IBaseTmp, "ACPI CPU");
2737 if (RT_SUCCESS(rc))
2738 {
2739 /* Enable the CPU */
2740 VMCPUSET_ADD(&pThis->CpuSetAttached, iLUN);
2741
2742 /*
2743 * Lock the CPU because we don't know if the guest will use it or not.
2744 * Prevents ejection while the CPU is still used
2745 */
2746 VMCPUSET_ADD(&pThis->CpuSetLocked, iLUN);
2747 pThis->u32CpuEventType = CPU_EVENT_TYPE_ADD;
2748 pThis->u32CpuEvent = iLUN;
2749
2750 /* Notify the guest */
2751 apicR3UpdateGpe0(pThis, pThis->gpe0_sts | 0x2, pThis->gpe0_en);
2752 }
2753 }
2754 DEVACPI_UNLOCK(pThis);
2755 return rc;
2756}
2757
2758/**
2759 * Detach notification.
2760 *
2761 * @param pDevIns The device instance.
2762 * @param iLUN The logical unit which is being detached.
2763 * @param fFlags Flags, combination of the PDMDEVATT_FLAGS_* \#defines.
2764 */
2765static DECLCALLBACK(void) acpiR3Detach(PPDMDEVINS pDevIns, unsigned iLUN, uint32_t fFlags)
2766{
2767 ACPIState *pThis = PDMINS_2_DATA(pDevIns, ACPIState *);
2768
2769 LogFlow(("acpiDetach: pDevIns=%p iLUN=%u fFlags=%#x\n", pDevIns, iLUN, fFlags));
2770
2771 AssertMsgReturnVoid(!(fFlags & PDM_TACH_FLAGS_NOT_HOT_PLUG),
2772 ("Hot-plug flag is not set\n"));
2773
2774 /* Check if it was already detached */
2775 DEVACPI_LOCK_R3(pThis);
2776 if (VMCPUSET_IS_PRESENT(&pThis->CpuSetAttached, iLUN))
2777 {
2778 if (!VMCPUSET_IS_PRESENT(&pThis->CpuSetLocked, iLUN))
2779 {
2780 /* Disable the CPU */
2781 VMCPUSET_DEL(&pThis->CpuSetAttached, iLUN);
2782 pThis->u32CpuEventType = CPU_EVENT_TYPE_REMOVE;
2783 pThis->u32CpuEvent = iLUN;
2784
2785 /* Notify the guest */
2786 apicR3UpdateGpe0(pThis, pThis->gpe0_sts | 0x2, pThis->gpe0_en);
2787 }
2788 else
2789 AssertMsgFailed(("CPU is still locked by the guest\n"));
2790 }
2791 DEVACPI_UNLOCK(pThis);
2792}
2793
2794/**
2795 * @interface_method_impl{PDMDEVREG,pfnResume}
2796 */
2797static DECLCALLBACK(void) acpiR3Resume(PPDMDEVINS pDevIns)
2798{
2799 ACPIState *pThis = PDMINS_2_DATA(pDevIns, ACPIState *);
2800 if (pThis->fSetWakeupOnResume)
2801 {
2802 Log(("acpiResume: setting WAK_STS\n"));
2803 pThis->fSetWakeupOnResume = false;
2804 pThis->pm1a_sts |= WAK_STS;
2805 }
2806}
2807
2808/**
2809 * @interface_method_impl{PDMDEVREG,pfnMemSetup}
2810 */
2811static DECLCALLBACK(void) acpiR3MemSetup(PPDMDEVINS pDevIns, PDMDEVMEMSETUPCTX enmCtx)
2812{
2813 ACPIState *pThis = PDMINS_2_DATA(pDevIns, ACPIState *);
2814 acpiR3PlantTables(pThis);
2815}
2816
2817/**
2818 * @interface_method_impl{PDMDEVREG,pfnReset}
2819 */
2820static DECLCALLBACK(void) acpiR3Reset(PPDMDEVINS pDevIns)
2821{
2822 ACPIState *pThis = PDMINS_2_DATA(pDevIns, ACPIState *);
2823
2824 TMTimerLock(pThis->pPmTimerR3, VERR_IGNORED);
2825 pThis->pm1a_en = 0;
2826 pThis->pm1a_sts = 0;
2827 pThis->pm1a_ctl = 0;
2828 pThis->u64PmTimerInitial = TMTimerGet(pThis->pPmTimerR3);
2829 acpiR3PmTimerReset(pThis, pThis->u64PmTimerInitial);
2830 pThis->uBatteryIndex = 0;
2831 pThis->uSystemInfoIndex = 0;
2832 pThis->gpe0_en = 0;
2833 pThis->gpe0_sts = 0;
2834 pThis->uSleepState = 0;
2835 TMTimerUnlock(pThis->pPmTimerR3);
2836
2837 /** @todo Should we really reset PM base? */
2838 acpiR3UpdatePmHandlers(pThis, PM_PORT_BASE);
2839}
2840
2841/**
2842 * @interface_method_impl{PDMDEVREG,pfnRelocate}
2843 */
2844static DECLCALLBACK(void) acpiR3Relocate(PPDMDEVINS pDevIns, RTGCINTPTR offDelta)
2845{
2846 ACPIState *pThis = PDMINS_2_DATA(pDevIns, ACPIState *);
2847 pThis->pPmTimerRC = TMTimerRCPtr(pThis->pPmTimerR3);
2848 NOREF(offDelta);
2849}
2850
2851/**
2852 * @interface_methid_impl{PDMDEVREG,pfnDestruct}
2853 */
2854static DECLCALLBACK(int) acpiR3Destruct(PPDMDEVINS pDevIns)
2855{
2856 ACPIState *pThis = PDMINS_2_DATA(pDevIns, ACPIState *);
2857 if (pThis->pu8CustBin)
2858 {
2859 MMR3HeapFree(pThis->pu8CustBin);
2860 pThis->pu8CustBin = NULL;
2861 }
2862 return VINF_SUCCESS;
2863}
2864
2865/**
2866 * @interface_method_impl{PDMDEVREG,pfnConstruct}
2867 */
2868static DECLCALLBACK(int) acpiR3Construct(PPDMDEVINS pDevIns, int iInstance, PCFGMNODE pCfg)
2869{
2870 ACPIState *pThis = PDMINS_2_DATA(pDevIns, ACPIState *);
2871 PDMDEV_CHECK_VERSIONS_RETURN(pDevIns);
2872
2873 /*
2874 * Init data and set defaults.
2875 */
2876 /** @todo move more of the code up! */
2877
2878 pThis->pDevIns = pDevIns;
2879 VMCPUSET_EMPTY(&pThis->CpuSetAttached);
2880 VMCPUSET_EMPTY(&pThis->CpuSetLocked);
2881 pThis->idCpuLockCheck = UINT32_C(0xffffffff);
2882 pThis->u32CpuEventType = 0;
2883 pThis->u32CpuEvent = UINT32_C(0xffffffff);
2884
2885 /* The first CPU can't be attached/detached */
2886 VMCPUSET_ADD(&pThis->CpuSetAttached, 0);
2887 VMCPUSET_ADD(&pThis->CpuSetLocked, 0);
2888
2889 /* IBase */
2890 pThis->IBase.pfnQueryInterface = acpiR3QueryInterface;
2891 /* IACPIPort */
2892 pThis->IACPIPort.pfnSleepButtonPress = acpiR3Port_SleepButtonPress;
2893 pThis->IACPIPort.pfnPowerButtonPress = acpiR3Port_PowerButtonPress;
2894 pThis->IACPIPort.pfnGetPowerButtonHandled = acpiR3Port_GetPowerButtonHandled;
2895 pThis->IACPIPort.pfnGetGuestEnteredACPIMode = acpiR3Port_GetGuestEnteredACPIMode;
2896 pThis->IACPIPort.pfnGetCpuStatus = acpiR3Port_GetCpuStatus;
2897
2898 /*
2899 * Set the default critical section to NOP (related to the PM timer).
2900 */
2901 int rc = PDMDevHlpSetDeviceCritSect(pDevIns, PDMDevHlpCritSectGetNop(pDevIns));
2902 AssertRCReturn(rc, rc);
2903
2904 rc = PDMDevHlpCritSectInit(pDevIns, &pThis->CritSect, RT_SRC_POS, "acpi#%u", iInstance);
2905 AssertRCReturn(rc, rc);
2906
2907 /*
2908 * Validate and read the configuration.
2909 */
2910 if (!CFGMR3AreValuesValid(pCfg,
2911 "RamSize\0"
2912 "RamHoleSize\0"
2913 "IOAPIC\0"
2914 "NumCPUs\0"
2915 "GCEnabled\0"
2916 "R0Enabled\0"
2917 "HpetEnabled\0"
2918 "McfgEnabled\0"
2919 "McfgBase\0"
2920 "McfgLength\0"
2921 "SmcEnabled\0"
2922 "FdcEnabled\0"
2923 "ShowRtc\0"
2924 "ShowCpu\0"
2925 "NicPciAddress\0"
2926 "AudioPciAddress\0"
2927 "IocPciAddress\0"
2928 "HostBusPciAddress\0"
2929 "EnableSuspendToDisk\0"
2930 "PowerS1Enabled\0"
2931 "PowerS4Enabled\0"
2932 "CpuHotPlug\0"
2933 "AmlFilePath\0"
2934 "Serial0IoPortBase\0"
2935 "Serial1IoPortBase\0"
2936 "Serial0Irq\0"
2937 "Serial1Irq\0"
2938 "AcpiOemId\0"
2939 "AcpiCreatorId\0"
2940 "AcpiCreatorRev\0"
2941 "CustomTable\0"
2942 "SLICTable\0"
2943 ))
2944 return PDMDEV_SET_ERROR(pDevIns, VERR_PDM_DEVINS_UNKNOWN_CFG_VALUES,
2945 N_("Configuration error: Invalid config key for ACPI device"));
2946
2947 /* query whether we are supposed to present an IOAPIC */
2948 rc = CFGMR3QueryU8Def(pCfg, "IOAPIC", &pThis->u8UseIOApic, 1);
2949 if (RT_FAILURE(rc))
2950 return PDMDEV_SET_ERROR(pDevIns, rc,
2951 N_("Configuration error: Failed to read \"IOAPIC\""));
2952
2953 rc = CFGMR3QueryU16Def(pCfg, "NumCPUs", &pThis->cCpus, 1);
2954 if (RT_FAILURE(rc))
2955 return PDMDEV_SET_ERROR(pDevIns, rc,
2956 N_("Configuration error: Querying \"NumCPUs\" as integer failed"));
2957
2958 /* query whether we are supposed to present an FDC controller */
2959 rc = CFGMR3QueryBoolDef(pCfg, "FdcEnabled", &pThis->fUseFdc, true);
2960 if (RT_FAILURE(rc))
2961 return PDMDEV_SET_ERROR(pDevIns, rc,
2962 N_("Configuration error: Failed to read \"FdcEnabled\""));
2963
2964 /* query whether we are supposed to present HPET */
2965 rc = CFGMR3QueryBoolDef(pCfg, "HpetEnabled", &pThis->fUseHpet, false);
2966 if (RT_FAILURE(rc))
2967 return PDMDEV_SET_ERROR(pDevIns, rc,
2968 N_("Configuration error: Failed to read \"HpetEnabled\""));
2969 /* query MCFG configuration */
2970 rc = CFGMR3QueryU64Def(pCfg, "McfgBase", &pThis->u64PciConfigMMioAddress, 0);
2971 if (RT_FAILURE(rc))
2972 return PDMDEV_SET_ERROR(pDevIns, rc,
2973 N_("Configuration error: Failed to read \"McfgBase\""));
2974 rc = CFGMR3QueryU64Def(pCfg, "McfgLength", &pThis->u64PciConfigMMioLength, 0);
2975 if (RT_FAILURE(rc))
2976 return PDMDEV_SET_ERROR(pDevIns, rc,
2977 N_("Configuration error: Failed to read \"McfgLength\""));
2978 pThis->fUseMcfg = (pThis->u64PciConfigMMioAddress != 0) && (pThis->u64PciConfigMMioLength != 0);
2979
2980 /* query whether we are supposed to present custom table */
2981 pThis->fUseCust = false;
2982
2983 /* query whether we are supposed to present SMC */
2984 rc = CFGMR3QueryBoolDef(pCfg, "SmcEnabled", &pThis->fUseSmc, false);
2985 if (RT_FAILURE(rc))
2986 return PDMDEV_SET_ERROR(pDevIns, rc,
2987 N_("Configuration error: Failed to read \"SmcEnabled\""));
2988
2989 /* query whether we are supposed to present RTC object */
2990 rc = CFGMR3QueryBoolDef(pCfg, "ShowRtc", &pThis->fShowRtc, false);
2991 if (RT_FAILURE(rc))
2992 return PDMDEV_SET_ERROR(pDevIns, rc,
2993 N_("Configuration error: Failed to read \"ShowRtc\""));
2994
2995 /* query whether we are supposed to present CPU objects */
2996 rc = CFGMR3QueryBoolDef(pCfg, "ShowCpu", &pThis->fShowCpu, false);
2997 if (RT_FAILURE(rc))
2998 return PDMDEV_SET_ERROR(pDevIns, rc,
2999 N_("Configuration error: Failed to read \"ShowCpu\""));
3000
3001 /* query primary NIC PCI address */
3002 rc = CFGMR3QueryU32Def(pCfg, "NicPciAddress", &pThis->u32NicPciAddress, 0);
3003 if (RT_FAILURE(rc))
3004 return PDMDEV_SET_ERROR(pDevIns, rc,
3005 N_("Configuration error: Failed to read \"NicPciAddress\""));
3006
3007 /* query primary NIC PCI address */
3008 rc = CFGMR3QueryU32Def(pCfg, "AudioPciAddress", &pThis->u32AudioPciAddress, 0);
3009 if (RT_FAILURE(rc))
3010 return PDMDEV_SET_ERROR(pDevIns, rc,
3011 N_("Configuration error: Failed to read \"AudioPciAddress\""));
3012
3013 /* query IO controller (southbridge) PCI address */
3014 rc = CFGMR3QueryU32Def(pCfg, "IocPciAddress", &pThis->u32IocPciAddress, 0);
3015 if (RT_FAILURE(rc))
3016 return PDMDEV_SET_ERROR(pDevIns, rc,
3017 N_("Configuration error: Failed to read \"IocPciAddress\""));
3018
3019 /* query host bus controller PCI address */
3020 rc = CFGMR3QueryU32Def(pCfg, "HostBusPciAddress", &pThis->u32HbcPciAddress, 0);
3021 if (RT_FAILURE(rc))
3022 return PDMDEV_SET_ERROR(pDevIns, rc,
3023 N_("Configuration error: Failed to read \"HostBusPciAddress\""));
3024
3025 /* query whether S1 power state should be exposed */
3026 rc = CFGMR3QueryBoolDef(pCfg, "PowerS1Enabled", &pThis->fS1Enabled, false);
3027 if (RT_FAILURE(rc))
3028 return PDMDEV_SET_ERROR(pDevIns, rc,
3029 N_("Configuration error: Failed to read \"PowerS1Enabled\""));
3030
3031 /* query whether S4 power state should be exposed */
3032 rc = CFGMR3QueryBoolDef(pCfg, "PowerS4Enabled", &pThis->fS4Enabled, false);
3033 if (RT_FAILURE(rc))
3034 return PDMDEV_SET_ERROR(pDevIns, rc,
3035 N_("Configuration error: Failed to read \"PowerS4Enabled\""));
3036
3037 /* query whether S1 power state should save the VM state */
3038 rc = CFGMR3QueryBoolDef(pCfg, "EnableSuspendToDisk", &pThis->fSuspendToSavedState, false);
3039 if (RT_FAILURE(rc))
3040 return PDMDEV_SET_ERROR(pDevIns, rc,
3041 N_("Configuration error: Failed to read \"EnableSuspendToDisk\""));
3042
3043 /* query whether we are allow CPU hot plugging */
3044 rc = CFGMR3QueryBoolDef(pCfg, "CpuHotPlug", &pThis->fCpuHotPlug, false);
3045 if (RT_FAILURE(rc))
3046 return PDMDEV_SET_ERROR(pDevIns, rc,
3047 N_("Configuration error: Failed to read \"CpuHotPlug\""));
3048
3049 rc = CFGMR3QueryBoolDef(pCfg, "GCEnabled", &pThis->fGCEnabled, true);
3050 if (RT_FAILURE(rc))
3051 return PDMDEV_SET_ERROR(pDevIns, rc,
3052 N_("Configuration error: Failed to read \"GCEnabled\""));
3053
3054 rc = CFGMR3QueryBoolDef(pCfg, "R0Enabled", &pThis->fR0Enabled, true);
3055 if (RT_FAILURE(rc))
3056 return PDMDEV_SET_ERROR(pDevIns, rc,
3057 N_("configuration error: failed to read \"R0Enabled\""));
3058
3059 /* query serial info */
3060 rc = CFGMR3QueryU8Def(pCfg, "Serial0Irq", &pThis->uSerial0Irq, 4);
3061 if (RT_FAILURE(rc))
3062 return PDMDEV_SET_ERROR(pDevIns, rc,
3063 N_("Configuration error: Failed to read \"Serial0Irq\""));
3064
3065 rc = CFGMR3QueryU16Def(pCfg, "Serial0IoPortBase", &pThis->uSerial0IoPortBase, 0x3f8);
3066 if (RT_FAILURE(rc))
3067 return PDMDEV_SET_ERROR(pDevIns, rc,
3068 N_("Configuration error: Failed to read \"Serial0IoPortBase\""));
3069
3070 /* Serial 1 is enabled, get config data */
3071 rc = CFGMR3QueryU8Def(pCfg, "Serial1Irq", &pThis->uSerial1Irq, 3);
3072 if (RT_FAILURE(rc))
3073 return PDMDEV_SET_ERROR(pDevIns, rc,
3074 N_("Configuration error: Failed to read \"Serial1Irq\""));
3075
3076 rc = CFGMR3QueryU16Def(pCfg, "Serial1IoPortBase", &pThis->uSerial1IoPortBase, 0x2f8);
3077 if (RT_FAILURE(rc))
3078 return PDMDEV_SET_ERROR(pDevIns, rc,
3079 N_("Configuration error: Failed to read \"Serial1IoPortBase\""));
3080
3081 /* Try to attach the other CPUs */
3082 for (unsigned i = 1; i < pThis->cCpus; i++)
3083 {
3084 if (pThis->fCpuHotPlug)
3085 {
3086 PPDMIBASE IBaseTmp;
3087 rc = PDMDevHlpDriverAttach(pDevIns, i, &pThis->IBase, &IBaseTmp, "ACPI CPU");
3088
3089 if (RT_SUCCESS(rc))
3090 {
3091 VMCPUSET_ADD(&pThis->CpuSetAttached, i);
3092 VMCPUSET_ADD(&pThis->CpuSetLocked, i);
3093 Log(("acpi: Attached CPU %u\n", i));
3094 }
3095 else if (rc == VERR_PDM_NO_ATTACHED_DRIVER)
3096 Log(("acpi: CPU %u not attached yet\n", i));
3097 else
3098 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Failed to attach CPU object\n"));
3099 }
3100 else
3101 {
3102 /* CPU is always attached if hot-plug is not enabled. */
3103 VMCPUSET_ADD(&pThis->CpuSetAttached, i);
3104 VMCPUSET_ADD(&pThis->CpuSetLocked, i);
3105 }
3106 }
3107
3108 char *pszOemId = NULL;
3109 rc = CFGMR3QueryStringAllocDef(pThis->pDevIns->pCfg, "AcpiOemId", &pszOemId, "VBOX ");
3110 if (RT_FAILURE(rc))
3111 return PDMDEV_SET_ERROR(pThis->pDevIns, rc,
3112 N_("Configuration error: Querying \"AcpiOemId\" as string failed"));
3113 size_t cbOemId = strlen(pszOemId);
3114 if (cbOemId > 6)
3115 return PDMDEV_SET_ERROR(pThis->pDevIns, rc,
3116 N_("Configuration error: \"AcpiOemId\" must contain not more than 6 characters"));
3117 memset(pThis->au8OemId, ' ', sizeof(pThis->au8OemId));
3118 memcpy(pThis->au8OemId, pszOemId, cbOemId);
3119 MMR3HeapFree(pszOemId);
3120
3121 char *pszCreatorId = NULL;
3122 rc = CFGMR3QueryStringAllocDef(pThis->pDevIns->pCfg, "AcpiCreatorId", &pszCreatorId, "ASL ");
3123 if (RT_FAILURE(rc))
3124 return PDMDEV_SET_ERROR(pThis->pDevIns, rc,
3125 N_("Configuration error: Querying \"AcpiCreatorId\" as string failed"));
3126 size_t cbCreatorId = strlen(pszCreatorId);
3127 if (cbCreatorId > 4)
3128 return PDMDEV_SET_ERROR(pThis->pDevIns, rc,
3129 N_("Configuration error: \"AcpiCreatorId\" must contain not more than 4 characters"));
3130 memset(pThis->au8CreatorId, ' ', sizeof(pThis->au8CreatorId));
3131 memcpy(pThis->au8CreatorId, pszCreatorId, cbCreatorId);
3132 MMR3HeapFree(pszCreatorId);
3133
3134 rc = CFGMR3QueryU32Def(pThis->pDevIns->pCfg, "AcpiCreatorRev", &pThis->u32CreatorRev, RT_H2LE_U32(0x61));
3135 if (RT_FAILURE(rc))
3136 return PDMDEV_SET_ERROR(pThis->pDevIns, rc,
3137 N_("Configuration error: Querying \"AcpiCreatorRev\" as integer failed"));
3138 pThis->u32OemRevision = RT_H2LE_U32(0x1);
3139
3140 /*
3141 * Get the custom table binary file name.
3142 */
3143 char *pszCustBinFile;
3144 rc = CFGMR3QueryStringAlloc(pThis->pDevIns->pCfg, "CustomTable", &pszCustBinFile);
3145 if (rc == VERR_CFGM_VALUE_NOT_FOUND)
3146 rc = CFGMR3QueryStringAlloc(pThis->pDevIns->pCfg, "SLICTable", &pszCustBinFile);
3147 if (rc == VERR_CFGM_VALUE_NOT_FOUND)
3148 {
3149 pszCustBinFile = NULL;
3150 rc = VINF_SUCCESS;
3151 }
3152 else if (RT_FAILURE(rc))
3153 return PDMDEV_SET_ERROR(pThis->pDevIns, rc,
3154 N_("Configuration error: Querying \"CustomTable\" as a string failed"));
3155 else if (!*pszCustBinFile)
3156 {
3157 MMR3HeapFree(pszCustBinFile);
3158 pszCustBinFile = NULL;
3159 }
3160
3161 /*
3162 * Determine the custom table binary size, open specified ROM file in the process.
3163 */
3164 if (pszCustBinFile)
3165 {
3166 RTFILE FileCUSTBin;
3167 rc = RTFileOpen(&FileCUSTBin, pszCustBinFile,
3168 RTFILE_O_READ | RTFILE_O_OPEN | RTFILE_O_DENY_WRITE);
3169 if (RT_SUCCESS(rc))
3170 {
3171 rc = RTFileGetSize(FileCUSTBin, &pThis->cbCustBin);
3172 if (RT_SUCCESS(rc))
3173 {
3174 /* The following checks should be in sync the AssertReleaseMsg's below. */
3175 if ( pThis->cbCustBin > 3072
3176 || pThis->cbCustBin < sizeof(ACPITBLHEADER))
3177 rc = VERR_TOO_MUCH_DATA;
3178
3179 /*
3180 * Allocate buffer for the custom table binary data.
3181 */
3182 pThis->pu8CustBin = (uint8_t *)PDMDevHlpMMHeapAlloc(pThis->pDevIns, pThis->cbCustBin);
3183 if (pThis->pu8CustBin)
3184 {
3185 rc = RTFileRead(FileCUSTBin, pThis->pu8CustBin, pThis->cbCustBin, NULL);
3186 if (RT_FAILURE(rc))
3187 {
3188 AssertMsgFailed(("RTFileRead(,,%d,NULL) -> %Rrc\n", pThis->cbCustBin, rc));
3189 MMR3HeapFree(pThis->pu8CustBin);
3190 pThis->pu8CustBin = NULL;
3191 }
3192 else
3193 {
3194 pThis->fUseCust = true;
3195 memcpy(&pThis->au8OemId[0], &pThis->pu8CustBin[10], 6);
3196 memcpy(&pThis->au8OemTabId[0], &pThis->pu8CustBin[16], 8);
3197 memcpy(&pThis->u32OemRevision, &pThis->pu8CustBin[24], 4);
3198 memcpy(&pThis->au8CreatorId[0], &pThis->pu8CustBin[28], 4);
3199 memcpy(&pThis->u32CreatorRev, &pThis->pu8CustBin[32], 4);
3200 LogRel(("Reading custom ACPI table from file '%s' (%d bytes)\n", pszCustBinFile, pThis->cbCustBin));
3201 }
3202 }
3203 else
3204 rc = VERR_NO_MEMORY;
3205
3206 RTFileClose(FileCUSTBin);
3207 }
3208 }
3209 MMR3HeapFree(pszCustBinFile);
3210 if (RT_FAILURE(rc))
3211 return PDMDEV_SET_ERROR(pDevIns, rc,
3212 N_("Error reading custom ACPI table"));
3213 }
3214
3215 /* Set default port base */
3216 pThis->uPmIoPortBase = PM_PORT_BASE;
3217
3218 /*
3219 * FDC and SMC try to use the same non-shareable interrupt (6),
3220 * enable only one device.
3221 */
3222 if (pThis->fUseSmc)
3223 pThis->fUseFdc = false;
3224
3225 /*
3226 * Plant ACPI tables.
3227 */
3228 /** @todo Part of this is redone by acpiR3MemSetup, we only need to init the
3229 * au8RSDPPage here. However, there should be no harm in doing it
3230 * twice, so the lazy bird is taking the quick way out for now. */
3231 RTGCPHYS32 GCPhysRsdp = apicR3FindRsdpSpace();
3232 if (!GCPhysRsdp)
3233 return PDMDEV_SET_ERROR(pDevIns, VERR_NO_MEMORY,
3234 N_("Can not find space for RSDP. ACPI is disabled"));
3235
3236 rc = acpiR3PlantTables(pThis);
3237 if (RT_FAILURE(rc))
3238 return rc;
3239
3240 rc = PDMDevHlpROMRegister(pDevIns, GCPhysRsdp, 0x1000, pThis->au8RSDPPage, 0x1000,
3241 PGMPHYS_ROM_FLAGS_PERMANENT_BINARY, "ACPI RSDP");
3242 if (RT_FAILURE(rc))
3243 return rc;
3244
3245 /*
3246 * Register I/O ports.
3247 */
3248 rc = acpiR3RegisterPmHandlers(pThis);
3249 if (RT_FAILURE(rc))
3250 return rc;
3251
3252#define R(addr, cnt, writer, reader, description) \
3253 do { \
3254 rc = PDMDevHlpIOPortRegister(pDevIns, addr, cnt, pThis, writer, reader, \
3255 NULL, NULL, description); \
3256 if (RT_FAILURE(rc)) \
3257 return rc; \
3258 } while (0)
3259 R(SMI_CMD, 1, acpiR3SmiWrite, NULL, "ACPI SMI");
3260#ifdef DEBUG_ACPI
3261 R(DEBUG_HEX, 1, acpiR3DhexWrite, NULL, "ACPI Debug hex");
3262 R(DEBUG_CHR, 1, acpiR3DchrWrite, NULL, "ACPI Debug char");
3263#endif
3264 R(BAT_INDEX, 1, acpiR3BatIndexWrite, NULL, "ACPI Battery status index");
3265 R(BAT_DATA, 1, NULL, acpiR3BatDataRead, "ACPI Battery status data");
3266 R(SYSI_INDEX, 1, acpiR3SysInfoIndexWrite, NULL, "ACPI system info index");
3267 R(SYSI_DATA, 1, acpiR3SysInfoDataWrite, acpiR3SysInfoDataRead, "ACPI system info data");
3268 R(ACPI_RESET_BLK, 1, acpiR3ResetWrite, NULL, "ACPI Reset");
3269#undef R
3270
3271 /*
3272 * Create the PM timer.
3273 */
3274 PTMTIMER pTimer;
3275 rc = PDMDevHlpTMTimerCreate(pDevIns, TMCLOCK_VIRTUAL_SYNC, acpiR3PmTimer, &pThis->dev,
3276 TMTIMER_FLAGS_NO_CRIT_SECT, "ACPI PM Timer", &pTimer);
3277 AssertRCReturn(rc, rc);
3278 pThis->pPmTimerR3 = pTimer;
3279 pThis->pPmTimerR0 = TMTimerR0Ptr(pTimer);
3280 pThis->pPmTimerRC = TMTimerRCPtr(pTimer);
3281
3282 rc = TMTimerLock(pTimer, VERR_IGNORED);
3283 AssertRCReturn(rc, rc);
3284 pThis->u64PmTimerInitial = TMTimerGet(pTimer);
3285 acpiR3PmTimerReset(pThis, pThis->u64PmTimerInitial);
3286 TMTimerUnlock(pTimer);
3287
3288 /*
3289 * Set up the PCI device.
3290 */
3291 PCIDevSetVendorId(&pThis->dev, 0x8086); /* Intel */
3292 PCIDevSetDeviceId(&pThis->dev, 0x7113); /* 82371AB */
3293
3294 /* See p. 50 of PIIX4 manual */
3295 PCIDevSetCommand(&pThis->dev, 0x01);
3296 PCIDevSetStatus(&pThis->dev, 0x0280);
3297
3298 PCIDevSetRevisionId(&pThis->dev, 0x08);
3299
3300 PCIDevSetClassProg(&pThis->dev, 0x00);
3301 PCIDevSetClassSub(&pThis->dev, 0x80);
3302 PCIDevSetClassBase(&pThis->dev, 0x06);
3303
3304 PCIDevSetHeaderType(&pThis->dev, 0x80);
3305
3306 PCIDevSetBIST(&pThis->dev, 0x00);
3307
3308 PCIDevSetInterruptLine(&pThis->dev, SCI_INT);
3309 PCIDevSetInterruptPin (&pThis->dev, 0x01);
3310
3311 pThis->dev.config[0x40] = 0x01; /* PM base address, this bit marks it as IO range, not PA */
3312
3313#if 0
3314 int smb_io_base = 0xb100;
3315 dev->config[0x90] = smb_io_base | 1; /* SMBus base address */
3316 dev->config[0x90] = smb_io_base >> 8;
3317#endif
3318
3319 rc = PDMDevHlpPCIRegister(pDevIns, &pThis->dev);
3320 if (RT_FAILURE(rc))
3321 return rc;
3322
3323 PDMDevHlpPCISetConfigCallbacks(pDevIns, &pThis->dev,
3324 acpiR3PciConfigRead, &pThis->pfnAcpiPciConfigRead,
3325 acpiR3PciConfigWrite, &pThis->pfnAcpiPciConfigWrite);
3326
3327 /*
3328 * Register the saved state.
3329 */
3330 rc = PDMDevHlpSSMRegister(pDevIns, 6, sizeof(*pThis), acpiR3SaveState, acpiR3LoadState);
3331 if (RT_FAILURE(rc))
3332 return rc;
3333
3334 /*
3335 * Get the corresponding connector interface
3336 */
3337 rc = PDMDevHlpDriverAttach(pDevIns, 0, &pThis->IBase, &pThis->pDrvBase, "ACPI Driver Port");
3338 if (RT_SUCCESS(rc))
3339 {
3340 pThis->pDrv = PDMIBASE_QUERY_INTERFACE(pThis->pDrvBase, PDMIACPICONNECTOR);
3341 if (!pThis->pDrv)
3342 return PDMDEV_SET_ERROR(pDevIns, VERR_PDM_MISSING_INTERFACE,
3343 N_("LUN #0 doesn't have an ACPI connector interface"));
3344 }
3345 else if (rc == VERR_PDM_NO_ATTACHED_DRIVER)
3346 {
3347 Log(("acpi: %s/%d: warning: no driver attached to LUN #0!\n",
3348 pDevIns->pReg->szName, pDevIns->iInstance));
3349 rc = VINF_SUCCESS;
3350 }
3351 else
3352 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Failed to attach LUN #0"));
3353
3354 return rc;
3355}
3356
3357/**
3358 * The device registration structure.
3359 */
3360const PDMDEVREG g_DeviceACPI =
3361{
3362 /* u32Version */
3363 PDM_DEVREG_VERSION,
3364 /* szName */
3365 "acpi",
3366 /* szRCMod */
3367 "VBoxDDGC.gc",
3368 /* szR0Mod */
3369 "VBoxDDR0.r0",
3370 /* pszDescription */
3371 "Advanced Configuration and Power Interface",
3372 /* fFlags */
3373 PDM_DEVREG_FLAGS_DEFAULT_BITS | PDM_DEVREG_FLAGS_RC | PDM_DEVREG_FLAGS_R0,
3374 /* fClass */
3375 PDM_DEVREG_CLASS_ACPI,
3376 /* cMaxInstances */
3377 ~0U,
3378 /* cbInstance */
3379 sizeof(ACPIState),
3380 /* pfnConstruct */
3381 acpiR3Construct,
3382 /* pfnDestruct */
3383 acpiR3Destruct,
3384 /* pfnRelocate */
3385 acpiR3Relocate,
3386 /* pfnMemSetup */
3387 acpiR3MemSetup,
3388 /* pfnPowerOn */
3389 NULL,
3390 /* pfnReset */
3391 acpiR3Reset,
3392 /* pfnSuspend */
3393 NULL,
3394 /* pfnResume */
3395 acpiR3Resume,
3396 /* pfnAttach */
3397 acpiR3Attach,
3398 /* pfnDetach */
3399 acpiR3Detach,
3400 /* pfnQueryInterface. */
3401 NULL,
3402 /* pfnInitComplete */
3403 NULL,
3404 /* pfnPowerOff */
3405 NULL,
3406 /* pfnSoftReset */
3407 NULL,
3408 /* u32VersionEnd */
3409 PDM_DEVREG_VERSION
3410};
3411
3412#endif /* IN_RING3 */
3413#endif /* !VBOX_DEVICE_STRUCT_TESTCASE */
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