VirtualBox

source: vbox/trunk/src/VBox/Devices/PC/DevACPI.cpp@ 400

Last change on this file since 400 was 1, checked in by vboxsync, 55 years ago

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1/** @file
2 *
3 * VBox basic PC devices:
4 * Advanced Configuration and Power Interface (ACPI) device
5 */
6
7/*
8 * Copyright (C) 2006 InnoTek Systemberatung GmbH
9 *
10 * This file is part of VirtualBox Open Source Edition (OSE), as
11 * available from http://www.virtualbox.org. This file is free software;
12 * you can redistribute it and/or modify it under the terms of the GNU
13 * General Public License as published by the Free Software Foundation,
14 * in version 2 as it comes in the "COPYING" file of the VirtualBox OSE
15 * distribution. VirtualBox OSE is distributed in the hope that it will
16 * be useful, but WITHOUT ANY WARRANTY of any kind.
17 *
18 * If you received this file as part of a commercial VirtualBox
19 * distribution, then only the terms of your commercial VirtualBox
20 * license agreement apply instead of the previous paragraph.
21 */
22
23#define LOG_GROUP LOG_GROUP_DEV_ACPI
24
25#include <VBox/pdm.h>
26#include <VBox/log.h>
27#include <iprt/assert.h>
28#ifdef IN_RING3
29#include <iprt/alloc.h>
30#endif /* IN_RING3 */
31
32#include "Builtins.h"
33#include "vl_vbox.h"
34
35#ifdef LOG_ENABLED
36#define DEBUG_ACPI
37#endif
38
39/* the compiled DSL */
40#ifdef IN_RING3
41#include <vboxaml.hex>
42#endif /* !IN_RING3 */
43
44#define IO_READ_PROTO(name) \
45 PDMBOTHCBDECL(int) name (PPDMDEVINS pDevIns, void *pvUser, \
46 RTIOPORT Port, uint32_t *pu32, unsigned cb)
47
48#define IO_WRITE_PROTO(name) \
49 PDMBOTHCBDECL(int) name (PPDMDEVINS pDevIns, void *pvUser, \
50 RTIOPORT Port, uint32_t u32, unsigned cb)
51
52#define DEBUG_HEX 0x3000
53#define DEBUG_CHR 0x3001
54
55#define PM_TMR_FREQ 3579545
56#define PM1a_EVT_BLK 0x00004000
57#define PM1b_EVT_BLK 0x00000000 /**< not supported */
58#define PM1a_CTL_BLK 0x00004004
59#define PM1b_CTL_BLK 0x00000000 /**< not supported */
60#define PM2_CTL_BLK 0x00000000 /**< not supported */
61#define PM_TMR_BLK 0x00004008
62#define GPE0_BLK 0x00004020
63#define GPE1_BLK 0x00000000 /**< not supported */
64#define BAT_INDEX 0x00004040
65#define BAT_DATA 0x00004044
66#define SYSI_INDEX 0x00004048
67#define SYSI_DATA 0x0000404c
68#define ACPI_RESET_BLK 0x00004050
69
70/* PM1x status register bits */
71#define TMR_STS BIT(0)
72#define RSR1_STS (BIT(1) | BIT(2) | BIT(3))
73#define BM_STS BIT(4)
74#define GBL_STS BIT(5)
75#define RSR2_STS (BIT(6) | BIT(7))
76#define PWRBTN_STS BIT(8)
77#define SLPBTN_STS BIT(9)
78#define RTC_STS BIT(10)
79#define IGN_STS BIT(11)
80#define RSR3_STS (BIT(12) | BIT(13) | BIT(14))
81#define WAK_STS BIT(15)
82#define RSR_STS (RSR1_STS | RSR2_STS | RSR3_STS)
83
84/* PM1x enable register bits */
85#define TMR_EN BIT(0)
86#define RSR1_EN (BIT(1) | BIT(2) | BIT(3) | BIT(4))
87#define GBL_EN BIT(5)
88#define RSR2_EN (BIT(6) | BIT(7))
89#define PWRBTN_EN BIT(8)
90#define SLPBTN_EN BIT(9)
91#define RTC_EN BIT(10)
92#define RSR3_EN (BIT(11) | BIT(12) | BIT(13) | BIT(14) | BIT(15))
93#define RSR_EN (RSR1_EN | RSR2_EN | RSR3_EN)
94#define IGN_EN 0
95
96/* PM1x control register bits */
97#define SCI_EN BIT(0)
98#define BM_RLD BIT(1)
99#define GBL_RLS BIT(2)
100#define RSR1_CNT (BIT(3) | BIT(4) | BIT(5) | BIT(6) | BIT(7) | BIT(8))
101#define IGN_CNT BIT(9)
102#define SLP_TYPx_SHIFT 10
103#define SLP_TYPx_MASK 7
104#define SLP_EN BIT(13)
105#define RSR2_CNT (BIT(14) | BIT(15))
106#define RSR_CNT (RSR1_CNT | RSR2_CNT)
107
108#define GPE0_BATTERY_INFO_CHANGED BIT (0)
109
110enum
111{
112 BAT_STATUS_STATE = 0x00, /**< BST battery state */
113 BAT_STATUS_PRESENT_RATE = 0x01, /**< BST battery present rate */
114 BAT_STATUS_REMAINING_CAPACITY = 0x02, /**< BST battery remaining capacity */
115 BAT_STATUS_PRESENT_VOLTAGE = 0x03, /**< BST battery present voltage */
116 BAT_INFO_UNITS = 0x04, /**< BIF power unit */
117 BAT_INFO_DESIGN_CAPACITY = 0x05, /**< BIF design capacity */
118 BAT_INFO_LAST_FULL_CHARGE_CAPACITY = 0x06, /**< BIF last full charge capacity */
119 BAT_INFO_TECHNOLOGY = 0x07, /**< BIF battery technology */
120 BAT_INFO_DESIGN_VOLTAGE = 0x08, /**< BIF design voltage */
121 BAT_INFO_DESIGN_CAPACITY_OF_WARNING = 0x09, /**< BIF design capacity of warning */
122 BAT_INFO_DESIGN_CAPACITY_OF_LOW = 0x0A, /**< BIF design capacity of low */
123 BAT_INFO_CAPACITY_GRANULARITY_1 = 0x0B, /**< BIF battery capacity granularity 1 */
124 BAT_INFO_CAPACITY_GRANULARITY_2 = 0x0C, /**< BIF battery capacity granularity 2 */
125 BAT_DEVICE_STATUS = 0x0D, /**< STA device status */
126 BAT_POWER_SOURCE = 0x0E, /**< PSR power source */
127 BAT_INDEX_LAST
128};
129
130enum
131{
132 SYSTEM_INFO_INDEX_MEMORY_LENGTH = 0,
133 SYSTEM_INFO_INDEX_USE_IOAPIC = 1,
134 SYSTEM_INFO_INDEX_LAST = 2,
135 SYSTEM_INFO_INDEX_INVALID = 0x80,
136 SYSTEM_INFO_INDEX_VALID = 0x200
137};
138
139#define AC_OFFLINE 0
140#define AC_ONLINE 1
141
142#define BAT_TECH_PRIMARY 1
143#define BAT_TECH_SECONDARY 2
144
145#define BAT_STATUS_DISCHARGING_MASK BIT (0)
146#define BAT_STATUS_CHARGING_MASK BIT (1)
147#define BAT_STATUS_CRITICAL_MASK BIT (2)
148
149#define STA_DEVICE_PRESENT_MASK BIT (0)
150#define STA_DEVICE_ENABLED_MASK BIT (1)
151#define STA_DEVICE_SHOW_IN_UI_MASK BIT (2)
152#define STA_DEVICE_FUNCTIONING_PROPERLY_MASK BIT (3)
153#define STA_BATTERY_PRESENT_MASK BIT (4)
154
155struct ACPIState
156{
157 PCIDevice dev;
158 uint16_t pm1a_en;
159 uint16_t pm1a_sts;
160 uint16_t pm1a_ctl;
161 int64_t pm_timer_initial;
162 PTMTIMERHC tsHC;
163 PTMTIMERGC tsGC;
164
165 uint32_t gpe0_en;
166 uint32_t gpe0_sts;
167
168 unsigned int uBatteryIndex;
169 uint32_t au8BatteryInfo[13];
170
171 unsigned int uSystemInfoIndex;
172 uint64_t u64RamSize;
173
174 /** Current ACPI S* state. We support S0 and S5 */
175 uint32_t uSleepState;
176 uint8_t au8RSDPPage[0x1000];
177 uint8_t u8IndexShift;
178 uint8_t u8UseIOApic;
179
180 /** ACPI port base interface. */
181 PDMIBASE IBase;
182 /** ACPI port interface. */
183 PDMIACPIPORT IACPIPort;
184 /** Pointer to the device instance. */
185 PPDMDEVINS pDevIns;
186 /** Pointer to the driver base interface */
187 PPDMIBASE pDrvBase;
188 /** Pointer to the driver connector interface */
189 PPDMIACPICONNECTOR pDrv;
190};
191
192#pragma pack(1)
193
194/** Generic Address Structure (see ACPIspec 3.0, 5.2.3.1) */
195struct ACPIGENADDR
196{
197 uint8_t u8AddressSpaceId; /**< 0=sys, 1=IO, 2=PCICfg, 3=emb, 4=SMBus */
198 uint8_t u8RegisterBitWidth; /**< size in bits of the given register */
199 uint8_t u8RegisterBitOffset; /**< bit offset of register */
200 uint8_t u8AccessSize; /**< 1=byte, 2=word, 3=dword, 4=qword */
201 uint64_t u64Address; /**< 64-bit address of register */
202};
203AssertCompileSize(ACPIGENADDR, 12);
204
205/** Root System Description Pointer */
206struct ACPITBLRSDP
207{
208 uint8_t au8Signature[8]; /**< 'RSD PTR ' */
209 uint8_t u8Checksum; /**< checksum for the first 20 bytes */
210 uint8_t au8OemId[6]; /**< OEM-supplied identifier */
211 uint8_t u8Revision; /**< revision number, currently 2 */
212#define ACPI_REVISION 2 /**< ACPI 3.0 */
213 uint32_t u32RSDT; /**< phys addr of RSDT */
214 uint32_t u32Length; /**< bytes of this table */
215 uint64_t u64XSDT; /**< 64-bit phys addr of XSDT */
216 uint8_t u8ExtChecksum; /**< checksum of entire table */
217 uint8_t u8Reserved[3]; /**< reserved */
218};
219AssertCompileSize(ACPITBLRSDP, 36);
220
221/** System Description Table Header */
222struct ACPITBLHEADER
223{
224 uint8_t au8Signature[4]; /**< table identifier */
225 uint32_t u32Length; /**< length of the table including header */
226 uint8_t u8Revision; /**< revision number */
227 uint8_t u8Checksum; /**< all fields inclusive this add to zero */
228 uint8_t au8OemId[6]; /**< OEM-supplied string */
229 uint8_t au8OemTabId[8]; /**< to identify the particular data table */
230 uint32_t u32OemRevision; /**< OEM-supplied revision number */
231 uint8_t au8CreatorId[4]; /**< ID for the ASL compiler */
232 uint32_t u32CreatorRev; /**< revision for the ASL compiler */
233};
234AssertCompileSize(ACPITBLHEADER, 36);
235
236/** Root System Description Table */
237struct ACPITBLRSDT
238{
239 ACPITBLHEADER header;
240 uint32_t u32Entry[1]; /**< array of phys. addresses to other tables */
241};
242AssertCompileSize(ACPITBLRSDT, 40);
243
244/** Extended System Description Table */
245struct ACPITBLXSDT
246{
247 ACPITBLHEADER header;
248 uint64_t u64Entry[1]; /**< array of phys. addresses to other tables */
249};
250AssertCompileSize(ACPITBLXSDT, 44);
251
252/** Fixed ACPI Description Table */
253struct ACPITBLFADT
254{
255 ACPITBLHEADER header;
256 uint32_t u32FACS; /**< phys. address of FACS */
257 uint32_t u32DSDT; /**< phys. address of DSDT */
258 uint8_t u8IntModel; /**< was eleminated in ACPI 2.0 */
259#define INT_MODEL_DUAL_PIC 1 /**< for ACPI 2+ */
260#define INT_MODEL_MULTIPLE_APIC 2
261 uint8_t u8PreferredPMProfile; /**< preferred power management profile */
262 uint16_t u16SCIInt; /**< system vector the SCI is wired in 8259 mode */
263#define SCI_INT 9
264 uint32_t u32SMICmd; /**< system port address of SMI command port */
265#define SMI_CMD 0x0000442e
266 uint8_t u8AcpiEnable; /**< SMICmd val to disable ownship of ACPIregs */
267#define ACPI_ENABLE 0xa1
268 uint8_t u8AcpiDisable; /**< SMICmd val to re-enable ownship of ACPIregs */
269#define ACPI_DISABLE 0xa0
270 uint8_t u8S4BIOSReq; /**< SMICmd val to enter S4BIOS state */
271 uint8_t u8PStateCnt; /**< SMICmd val to assume processor performance
272 state control responsibility */
273 uint32_t u32PM1aEVTBLK; /**< port addr of PM1a event regs block */
274 uint32_t u32PM1bEVTBLK; /**< port addr of PM1b event regs block */
275 uint32_t u32PM1aCTLBLK; /**< port addr of PM1a control regs block */
276 uint32_t u32PM1bCTLBLK; /**< port addr of PM1b control regs block */
277 uint32_t u32PM2CTLBLK; /**< port addr of PM2 control regs block */
278 uint32_t u32PMTMRBLK; /**< port addr of PMTMR regs block */
279 uint32_t u32GPE0BLK; /**< port addr of gen-purp event 0 regs block */
280 uint32_t u32GPE1BLK; /**< port addr of gen-purp event 1 regs block */
281 uint8_t u8PM1EVTLEN; /**< bytes decoded by PM1a_EVT_BLK. >= 4 */
282 uint8_t u8PM1CTLLEN; /**< bytes decoded by PM1b_CNT_BLK. >= 2 */
283 uint8_t u8PM2CTLLEN; /**< bytes decoded by PM2_CNT_BLK. >= 1 or 0 */
284 uint8_t u8PMTMLEN; /**< bytes decoded by PM_TMR_BLK. ==4 */
285 uint8_t u8GPE0BLKLEN; /**< bytes decoded by GPE0_BLK. %2==0 */
286#define GPE0_BLK_LEN 2
287 uint8_t u8GPE1BLKLEN; /**< bytes decoded by GPE1_BLK. %2==0 */
288#define GPE1_BLK_LEN 0
289 uint8_t u8GPE1BASE; /**< offset of GPE1 based events */
290#define GPE1_BASE 0
291 uint8_t u8CSTCNT; /**< SMICmd val to indicate OS supp for C states */
292 uint16_t u16PLVL2LAT; /**< us to enter/exit C2. >100 => unsupported */
293#define P_LVL2_LAT 101 /**< C2 state not supported */
294 uint16_t u16PLVL3LAT; /**< us to enter/exit C3. >1000 => unsupported */
295#define P_LVL3_LAT 1001 /**< C3 state not supported */
296 uint16_t u16FlushSize; /**< # of flush strides to read to flush dirty
297 lines from any processors memory caches */
298#define FLUSH_SIZE 0 /**< Ignored if WBVIND set in FADT_FLAGS */
299 uint16_t u16FlushStride; /**< cache line width */
300#define FLUSH_STRIDE 0 /**< Ignored if WBVIND set in FADT_FLAGS */
301 uint8_t u8DutyOffset;
302 uint8_t u8DutyWidth;
303 uint8_t u8DayAlarm; /**< RTC CMOS RAM index of day-of-month alarm */
304 uint8_t u8MonAlarm; /**< RTC CMOS RAM index of month-of-year alarm */
305 uint8_t u8Century; /**< RTC CMOS RAM index of century */
306 uint16_t u16IAPCBOOTARCH; /**< IA-PC boot architecture flags */
307#define IAPC_BOOT_ARCH_LEGACY_DEV BIT(0) /**< legacy devices present such as LPT
308 (COM too?) */
309#define IAPC_BOOT_ARCH_8042 BIT(1) /**< legacy keyboard device present */
310#define IAPC_BOOT_ARCH_NO_VGA BIT(2) /**< VGA not present */
311 uint8_t u8Must0_0; /**< must be 0 */
312 uint32_t u32Flags; /**< fixed feature flags */
313#define FADT_FL_WBINVD BIT(0) /**< emulation of WBINVD available */
314#define FADT_FL_WBINVD_FLUSH BIT(1)
315#define FADT_FL_PROC_C1 BIT(2) /**< 1=C1 supported on all processors */
316#define FADT_FL_P_LVL2_UP BIT(3) /**< 1=C2 works on SMP and UNI systems */
317#define FADT_FL_PWR_BUTTON BIT(4) /**< 1=power button handled as ctrl method dev */
318#define FADT_FL_SLP_BUTTON BIT(5) /**< 1=sleep button handled as ctrl method dev */
319#define FADT_FL_FIX_RTC BIT(6) /**< 0=RTC wake status in fixed register */
320#define FADT_FL_RTC_S4 BIT(7) /**< 1=RTC can wake system from S4 */
321#define FADT_FL_TMR_VAL_EXT BIT(8) /**< 1=TMR_VAL implemented as 32 bit */
322#define FADT_FL_DCK_CAP BIT(9) /**< 0=system cannot support docking */
323#define FADT_FL_RESET_REG_SUP BIT(10) /**< 1=system supports system resets */
324#define FADT_FL_SEALED_CASE BIT(11) /**< 1=case is sealed */
325#define FADT_FL_HEADLESS BIT(12) /**< 1=system cannot detect moni/keyb/mouse */
326#define FADT_FL_CPU_SW_SLP BIT(13)
327#define FADT_FL_PCI_EXT_WAK BIT(14) /**< 1=system supports PCIEXP_WAKE_STS */
328#define FADT_FL_USE_PLATFORM_CLOCK BIT(15) /**< 1=system has ACPI PM timer */
329#define FADT_FL_S4_RTC_STS_VALID BIT(16) /**< 1=RTC_STS flag is valid when waking from S4 */
330#define FADT_FL_REMOVE_POWER_ON_CAPABLE BIT(17) /**< 1=platform can remote power on */
331#define FADT_FL_FORCE_APIC_CLUSTER_MODEL BIT(18)
332#define FADT_FL_FORCE_APIC_PHYS_DEST_MODE BIT(19)
333 ACPIGENADDR ResetReg; /**< ext addr of reset register */
334 uint8_t u8ResetVal; /**< ResetReg value to reset the system */
335#define ACPI_RESET_REG_VAL 0x10
336 uint8_t au8Must0_1[3]; /**< must be 0 */
337 uint64_t u64XFACS; /**< 64-bit phys address of FACS */
338 uint64_t u64XDSDT; /**< 64-bit phys address of DSDT */
339 ACPIGENADDR X_PM1aEVTBLK; /**< ext addr of PM1a event regs block */
340 ACPIGENADDR X_PM1bEVTBLK; /**< ext addr of PM1b event regs block */
341 ACPIGENADDR X_PM1aCTLBLK; /**< ext addr of PM1a control regs block */
342 ACPIGENADDR X_PM1bCTLBLK; /**< ext addr of PM1b control regs block */
343 ACPIGENADDR X_PM2CTLBLK; /**< ext addr of PM2 control regs block */
344 ACPIGENADDR X_PMTMRBLK; /**< ext addr of PMTMR control regs block */
345 ACPIGENADDR X_GPE0BLK; /**< ext addr of GPE1 regs block */
346 ACPIGENADDR X_GPE1BLK; /**< ext addr of GPE1 regs block */
347};
348AssertCompileSize(ACPITBLFADT, 244);
349
350/** Firmware ACPI Control Structure */
351struct ACPITBLFACS
352{
353 uint8_t au8Signature[4]; /**< 'FACS' */
354 uint32_t u32Length; /**< bytes of entire FACS structure >= 64 */
355 uint32_t u32HWSignature; /**< systems HW signature at last boot */
356 uint32_t u32FWVector; /**< address of waking vector */
357 uint32_t u32GlobalLock; /**< global lock to sync HW/SW */
358 uint32_t u32Flags; /**< FACS flags */
359 uint64_t u64X_FWVector; /**< 64-bit waking vector */
360 uint8_t u8Version; /**< version of this table */
361 uint8_t au8Reserved[31]; /**< zero */
362};
363AssertCompileSize(ACPITBLFACS, 64);
364
365/** Processor Local APIC Structure */
366struct ACPITBLLAPIC
367{
368 uint8_t u8Type; /**< 0 = LAPIC */
369 uint8_t u8Length; /**< 8 */
370 uint8_t u8ProcId; /**< processor ID */
371 uint8_t u8ApicId; /**< local APIC ID */
372 uint32_t u32Flags; /**< Flags */
373#define LAPIC_ENABLED 0x1
374};
375AssertCompileSize(ACPITBLLAPIC, 8);
376
377/** I/O APIC Structure */
378struct ACPITBLIOAPIC
379{
380 uint8_t u8Type; /**< 1 == I/O APIC */
381 uint8_t u8Length; /**< 12 */
382 uint8_t u8IOApicId; /**< I/O APIC ID */
383 uint8_t u8Reserved; /**< 0 */
384 uint32_t u32Address; /**< phys address to access I/O APIC */
385 uint32_t u32GSIB; /**< global system interrupt number to start */
386};
387AssertCompileSize(ACPITBLIOAPIC, 12);
388
389/** Multiple APIC Description Table */
390struct ACPITBLMADT
391{
392 ACPITBLHEADER header;
393 uint32_t u32LAPIC; /**< local APIC address */
394 uint32_t u32Flags; /**< Flags */
395#define PCAT_COMPAT 0x1 /**< system has also a dual-8259 setup */
396 ACPITBLLAPIC LApic;
397 ACPITBLIOAPIC IOApic;
398};
399AssertCompileSize(ACPITBLMADT, 64);
400
401#pragma pack()
402
403__BEGIN_DECLS
404IO_READ_PROTO (acpiPMTmrRead);
405#ifdef IN_RING3
406IO_READ_PROTO (acpiPm1aEnRead);
407IO_WRITE_PROTO (acpiPM1aEnWrite);
408IO_READ_PROTO (acpiPm1aStsRead);
409IO_WRITE_PROTO (acpiPM1aStsWrite);
410IO_READ_PROTO (acpiPm1aCtlRead);
411IO_WRITE_PROTO (acpiPM1aCtlWrite);
412IO_WRITE_PROTO (acpiSmiWrite);
413IO_WRITE_PROTO (acpiBatIndexWrite);
414IO_READ_PROTO (acpiBatDataRead);
415IO_READ_PROTO (acpiSysInfoDataRead);
416IO_WRITE_PROTO (acpiSysInfoDataWrite);
417IO_READ_PROTO (acpiGpe0EnRead);
418IO_WRITE_PROTO (acpiGpe0EnWrite);
419IO_READ_PROTO (acpiGpe0StsRead);
420IO_WRITE_PROTO (acpiGpe0StsWrite);
421IO_WRITE_PROTO (acpiResetWrite);
422# ifdef DEBUG_ACPI
423IO_WRITE_PROTO (acpiDhexWrite);
424IO_WRITE_PROTO (acpiDchrWrite);
425# endif
426#endif
427__END_DECLS
428
429#ifdef IN_RING3
430
431/* Simple acpiChecksum: all the bytes must add up to 0. */
432static uint8_t acpiChecksum (const uint8_t * const data, uint32_t len)
433{
434 uint8_t sum = 0;
435 for (size_t i = 0; i < len; ++i)
436 sum += data[i];
437 return -sum;
438}
439
440static void acpiPrepareHeader (ACPITBLHEADER *header, const char au8Signature[4],
441 uint32_t u32Length, uint8_t u8Revision)
442{
443 memcpy(header->au8Signature, au8Signature, 4);
444 header->u32Length = cpu_to_le32(u32Length);
445 header->u8Revision = u8Revision;
446 memcpy(header->au8OemId, "VBOX ", 6);
447 memcpy(header->au8OemTabId, "VBOX", 4);
448 memcpy(header->au8OemTabId+4, au8Signature, 4);
449 header->u32OemRevision = cpu_to_le32(1);
450 memcpy(header->au8CreatorId, "ASL ", 4);
451 header->u32CreatorRev = cpu_to_le32(0x61);
452}
453
454static void acpiWriteGenericAddr(ACPIGENADDR *g, uint8_t u8AddressSpaceId,
455 uint8_t u8RegisterBitWidth, uint8_t u8RegisterBitOffset,
456 uint8_t u8AccessSize, uint64_t u64Address)
457{
458 g->u8AddressSpaceId = u8AddressSpaceId;
459 g->u8RegisterBitWidth = u8RegisterBitWidth;
460 g->u8RegisterBitOffset = u8RegisterBitOffset;
461 g->u8AccessSize = u8AccessSize;
462 g->u64Address = cpu_to_le64(u64Address);
463}
464
465static void acpiPhyscpy (ACPIState *s, RTGCPHYS dst, const void * const src, size_t size)
466{
467 PDMDevHlpPhysWrite (s->pDevIns, dst, src, size);
468}
469
470/* Differentiated System Description Table (DSDT) */
471static void acpiSetupDSDT (ACPIState *s, RTGCPHYS addr)
472{
473 acpiPhyscpy (s, addr, AmlCode, sizeof(AmlCode));
474}
475
476/* Firmware ACPI Control Structure (FACS) */
477static void acpiSetupFACS (ACPIState *s, RTGCPHYS addr)
478{
479 ACPITBLFACS facs;
480
481 memset (&facs, 0, sizeof(facs));
482 memcpy (facs.au8Signature, "FACS", 4);
483 facs.u32Length = cpu_to_le32(sizeof(ACPITBLFACS));
484 facs.u32HWSignature = cpu_to_le32(0);
485 facs.u32FWVector = cpu_to_le32(0);
486 facs.u32GlobalLock = cpu_to_le32(0);
487 facs.u32Flags = cpu_to_le32(0);
488 facs.u64X_FWVector = cpu_to_le64(0);
489 facs.u8Version = 1;
490
491 acpiPhyscpy (s, addr, (const uint8_t*)&facs, sizeof(facs));
492}
493
494/* Fixed ACPI Description Table (FADT aka FACP) */
495static void acpiSetupFADT (ACPIState *s, RTGCPHYS addr, uint32_t facs_addr, uint32_t dsdt_addr)
496{
497 ACPITBLFADT fadt;
498
499 memset (&fadt, 0, sizeof(fadt));
500 acpiPrepareHeader (&fadt.header, "FACP", sizeof(fadt), 4);
501 fadt.u32FACS = cpu_to_le32(facs_addr);
502 fadt.u32DSDT = cpu_to_le32(dsdt_addr);
503 fadt.u8IntModel = INT_MODEL_DUAL_PIC;
504 fadt.u8PreferredPMProfile = 0; /* unspecified */
505 fadt.u16SCIInt = cpu_to_le16(SCI_INT);
506 fadt.u32SMICmd = cpu_to_le32(SMI_CMD);
507 fadt.u8AcpiEnable = ACPI_ENABLE;
508 fadt.u8AcpiDisable = ACPI_DISABLE;
509 fadt.u8S4BIOSReq = 0;
510 fadt.u8PStateCnt = 0;
511 fadt.u32PM1aEVTBLK = cpu_to_le32(PM1a_EVT_BLK);
512 fadt.u32PM1bEVTBLK = cpu_to_le32(PM1b_EVT_BLK);
513 fadt.u32PM1aCTLBLK = cpu_to_le32(PM1a_CTL_BLK);
514 fadt.u32PM1bCTLBLK = cpu_to_le32(PM1b_CTL_BLK);
515 fadt.u32PM2CTLBLK = cpu_to_le32(PM2_CTL_BLK);
516 fadt.u32PMTMRBLK = cpu_to_le32(PM_TMR_BLK);
517 fadt.u32GPE0BLK = cpu_to_le32(GPE0_BLK);
518 fadt.u32GPE1BLK = cpu_to_le32(GPE1_BLK);
519 fadt.u8PM1EVTLEN = 4;
520 fadt.u8PM1CTLLEN = 2;
521 fadt.u8PM2CTLLEN = 0;
522 fadt.u8PMTMLEN = 4;
523 fadt.u8GPE0BLKLEN = GPE0_BLK_LEN;
524 fadt.u8GPE1BLKLEN = GPE1_BLK_LEN;
525 fadt.u8GPE1BASE = GPE1_BASE;
526 fadt.u8CSTCNT = 0;
527 fadt.u16PLVL2LAT = cpu_to_le16(P_LVL2_LAT);
528 fadt.u16PLVL3LAT = cpu_to_le16(P_LVL3_LAT);
529 fadt.u16FlushSize = cpu_to_le16(FLUSH_SIZE);
530 fadt.u16FlushStride = cpu_to_le16(FLUSH_STRIDE);
531 fadt.u8DutyOffset = 0;
532 fadt.u8DutyWidth = 0;
533 fadt.u8DayAlarm = 0;
534 fadt.u8MonAlarm = 0;
535 fadt.u8Century = 0;
536 fadt.u16IAPCBOOTARCH = cpu_to_le16(IAPC_BOOT_ARCH_LEGACY_DEV | IAPC_BOOT_ARCH_8042);
537 /** @note WBINVD is required for ACPI versions newer than 1.0 */
538 fadt.u32Flags = cpu_to_le32( FADT_FL_WBINVD | FADT_FL_SLP_BUTTON
539 | FADT_FL_FIX_RTC | FADT_FL_TMR_VAL_EXT);
540 acpiWriteGenericAddr(&fadt.ResetReg, 1, 8, 0, 1, ACPI_RESET_BLK);
541 fadt.u8ResetVal = ACPI_RESET_REG_VAL;
542 fadt.u64XFACS = cpu_to_le64((uint64_t)facs_addr);
543 fadt.u64XDSDT = cpu_to_le64((uint64_t)dsdt_addr);
544 acpiWriteGenericAddr(&fadt.X_PM1aEVTBLK, 1, 32, 0, 2, PM1a_EVT_BLK);
545 acpiWriteGenericAddr(&fadt.X_PM1bEVTBLK, 0, 0, 0, 0, PM1b_EVT_BLK);
546 acpiWriteGenericAddr(&fadt.X_PM1aCTLBLK, 1, 16, 0, 2, PM1a_CTL_BLK);
547 acpiWriteGenericAddr(&fadt.X_PM1bCTLBLK, 0, 0, 0, 0, PM1b_CTL_BLK);
548 acpiWriteGenericAddr(&fadt.X_PM2CTLBLK, 0, 0, 0, 0, PM2_CTL_BLK);
549 acpiWriteGenericAddr(&fadt.X_PMTMRBLK, 1, 32, 0, 3, PM_TMR_BLK);
550 acpiWriteGenericAddr(&fadt.X_GPE0BLK, 1, 16, 0, 1, GPE0_BLK);
551 acpiWriteGenericAddr(&fadt.X_GPE1BLK, 0, 0, 0, 0, GPE1_BLK);
552 fadt.header.u8Checksum = acpiChecksum ((uint8_t*)&fadt, sizeof(fadt));
553 acpiPhyscpy (s, addr, &fadt, sizeof(fadt));
554}
555
556/*
557 * Root System Description Table.
558 * The RSDT and XSDT tables are basically identical. The only difference is 32 vs 64 bits
559 * addresses for description headers. RSDT is for ACPI 1.0. XSDT for ACPI 2.0 and up.
560 */
561static int acpiSetupRSDT (ACPIState *s, RTGCPHYS addr, unsigned int nb_entries, uint32_t *addrs)
562{
563 ACPITBLRSDT *rsdt;
564 const size_t size = sizeof(ACPITBLHEADER) + nb_entries * sizeof(rsdt->u32Entry[0]);
565
566 rsdt = (ACPITBLRSDT*)RTMemAllocZ (size);
567 if (!rsdt)
568 return PDMDEV_SET_ERROR(s->pDevIns, VERR_NO_TMP_MEMORY, N_("Cannot allocate RSDT"));
569
570 acpiPrepareHeader (&rsdt->header, "RSDT", size, 1);
571 for (unsigned int i = 0; i < nb_entries; ++i)
572 {
573 rsdt->u32Entry[i] = cpu_to_le32(addrs[i]);
574 Log(("Setup RSDT: [%d] = %x\n", i, rsdt->u32Entry[i]));
575 }
576 rsdt->header.u8Checksum = acpiChecksum ((uint8_t*)rsdt, size);
577 acpiPhyscpy (s, addr, rsdt, size);
578 RTMemFree (rsdt);
579 return VINF_SUCCESS;
580}
581
582/* Extended System Description Table. */
583static int acpiSetupXSDT (ACPIState *s, RTGCPHYS addr, unsigned int nb_entries, uint32_t *addrs)
584{
585 ACPITBLXSDT *xsdt;
586 const size_t size = sizeof(ACPITBLHEADER) + nb_entries * sizeof(xsdt->u64Entry[0]);
587
588 xsdt = (ACPITBLXSDT*)RTMemAllocZ (size);
589 if (!xsdt)
590 return VERR_NO_TMP_MEMORY;
591
592 acpiPrepareHeader (&xsdt->header, "XSDT", size, 1 /* according to ACPI 3.0 specs */);
593 for (unsigned int i = 0; i < nb_entries; ++i)
594 {
595 xsdt->u64Entry[i] = cpu_to_le64((uint64_t)addrs[i]);
596 Log(("Setup XSDT: [%d] = %VX64\n", i, xsdt->u64Entry[i]));
597 }
598 xsdt->header.u8Checksum = acpiChecksum ((uint8_t*)xsdt, size);
599 acpiPhyscpy (s, addr, xsdt, size);
600 RTMemFree (xsdt);
601 return VINF_SUCCESS;
602}
603
604/* Root System Description Pointer (RSDP) */
605static void acpiSetupRSDP (ACPITBLRSDP *rsdp, uint32_t rsdt_addr, uint64_t xsdt_addr)
606{
607 memset(rsdp, 0, sizeof(*rsdp));
608
609 /* ACPI 1.0 part (RSDT */
610 memcpy(rsdp->au8Signature, "RSD PTR ", 8);
611 memcpy(rsdp->au8OemId, "VBox ", 6);
612 rsdp->u8Revision = ACPI_REVISION;
613 rsdp->u32RSDT = cpu_to_le32(rsdt_addr);
614 rsdp->u8Checksum = acpiChecksum((uint8_t*)rsdp, RT_OFFSETOF(ACPITBLRSDP, u32Length));
615
616 /* ACPI 2.0 part (XSDT) */
617 rsdp->u32Length = cpu_to_le32(sizeof(ACPITBLRSDP));
618 rsdp->u64XSDT = cpu_to_le64(xsdt_addr);
619 rsdp->u8ExtChecksum = acpiChecksum ((uint8_t*)rsdp, sizeof(ACPITBLRSDP));
620}
621
622/* Multiple APIC Description Table. */
623/** @todo All hardcoded, should set this up based on the actual VM config!!!!! */
624/** @note APIC without IO-APIC hangs Windows Vista therefore we setup both */
625static void acpiSetupMADT (ACPIState *s, RTGCPHYS addr)
626{
627 ACPITBLMADT madt;
628
629 /* Don't call this function if u8UseIOApic==false! */
630 Assert(s->u8UseIOApic);
631
632 memset(&madt, 0, sizeof(madt));
633 acpiPrepareHeader(&madt.header, "APIC", sizeof(madt), 2);
634
635 madt.u32LAPIC = cpu_to_le32(0xfee00000);
636 madt.u32Flags = cpu_to_le32(PCAT_COMPAT);
637
638 madt.LApic.u8Type = 0;
639 madt.LApic.u8Length = sizeof(ACPITBLLAPIC);
640 madt.LApic.u8ProcId = 0;
641 madt.LApic.u8ApicId = 0;
642 madt.LApic.u32Flags = cpu_to_le32(LAPIC_ENABLED);
643
644 madt.IOApic.u8Type = 1;
645 madt.IOApic.u8Length = sizeof(ACPITBLIOAPIC);
646 madt.IOApic.u8IOApicId = 0;
647 madt.IOApic.u8Reserved = 0;
648 madt.IOApic.u32Address = cpu_to_le32(0xfec00000);
649 madt.IOApic.u32GSIB = cpu_to_le32(0);
650
651 madt.header.u8Checksum = acpiChecksum ((uint8_t*)&madt, sizeof(madt));
652 acpiPhyscpy (s, addr, &madt, sizeof(madt));
653}
654
655/* SCI IRQ */
656DECLINLINE(void) acpiSetIrq (ACPIState *s, int level)
657{
658 if (s->pm1a_ctl & SCI_EN)
659 PDMDevHlpPCISetIrq (s->pDevIns, -1, level);
660}
661
662DECLINLINE(uint32_t) pm1a_pure_en (uint32_t en)
663{
664 return en & ~(RSR_EN | IGN_EN);
665}
666
667DECLINLINE(uint32_t) pm1a_pure_sts (uint32_t sts)
668{
669 return sts & ~(RSR_STS | IGN_STS);
670}
671
672DECLINLINE(int) pm1a_level (ACPIState *s)
673{
674 return (pm1a_pure_en (s->pm1a_en) & pm1a_pure_sts (s->pm1a_sts)) != 0;
675}
676
677DECLINLINE(int) gpe0_level (ACPIState *s)
678{
679 return (s->gpe0_en & s->gpe0_sts) != 0;
680}
681
682static void update_pm1a (ACPIState *s, uint32_t sts, uint32_t en)
683{
684 int old_level, new_level;
685
686 if (gpe0_level (s))
687 return;
688
689 old_level = pm1a_level (s);
690 new_level = (pm1a_pure_en (en) & pm1a_pure_sts (sts)) != 0;
691
692 s->pm1a_en = en;
693 s->pm1a_sts = sts;
694
695 if (new_level != old_level)
696 acpiSetIrq (s, new_level);
697}
698
699static void update_gpe0 (ACPIState *s, uint32_t sts, uint32_t en)
700{
701 int old_level, new_level;
702
703 if (pm1a_level (s))
704 return;
705
706 old_level = (s->gpe0_en & s->gpe0_sts) != 0;
707 new_level = (en & sts) != 0;
708
709 s->gpe0_en = en;
710 s->gpe0_sts = sts;
711
712 if (new_level != old_level)
713 acpiSetIrq (s, new_level);
714}
715
716static int acpiPowerDown (ACPIState *s)
717{
718 int rc = PDMDevHlpVMPowerOff(s->pDevIns);
719 if (VBOX_FAILURE (rc))
720 AssertMsgFailed (("Could not power down the VM. rc = %Vrc\n", rc));
721 return rc;
722}
723
724/** Converts a ACPI port interface pointer to an ACPI state pointer. */
725#define IACPIPORT_2_ACPISTATE(pInterface) ( (ACPIState*)((uintptr_t)pInterface - RT_OFFSETOF(ACPIState, IACPIPort)) )
726
727/**
728 * Send an ACPI power off event.
729 *
730 * @returns VBox status code
731 * @param pInterface Pointer to the interface structure containing the called function pointer.
732 */
733static DECLCALLBACK(int) acpiPowerButtonPress(PPDMIACPIPORT pInterface)
734{
735 ACPIState *s = IACPIPORT_2_ACPISTATE(pInterface);
736 update_pm1a (s, s->pm1a_sts | PWRBTN_STS, s->pm1a_en);
737 return VINF_SUCCESS;
738}
739
740/* PM1a_EVT_BLK enable */
741static uint32_t acpiPm1aEnReadw (ACPIState *s, uint32_t addr)
742{
743 uint16_t val = s->pm1a_en;
744 Log (("acpi: acpiPm1aEnReadw -> %#x\n", val));
745 return val;
746}
747
748static void acpiPM1aEnWritew (ACPIState *s, uint32_t addr, uint32_t val)
749{
750 Log (("acpi: acpiPM1aEnWritew <- %#x (%#x)\n", val, val & ~(RSR_EN | IGN_EN)));
751 val &= ~(RSR_EN | IGN_EN);
752 update_pm1a (s, s->pm1a_sts, val);
753}
754
755/* PM1a_EVT_BLK status */
756static uint32_t acpiPm1aStsReadw (ACPIState *s, uint32_t addr)
757{
758 uint16_t val = s->pm1a_sts;
759 Log (("acpi: acpiPm1aStsReadw -> %#x\n", val));
760 return val;
761}
762
763static void acpiPM1aStsWritew (ACPIState *s, uint32_t addr, uint32_t val)
764{
765 Log (("acpi: acpiPM1aStsWritew <- %#x (%#x)\n", val, val & ~(RSR_STS | IGN_STS)));
766 val = s->pm1a_sts & ~(val & ~(RSR_STS | IGN_STS));
767 update_pm1a (s, val, s->pm1a_en);
768}
769
770/* PM1a_CTL_BLK */
771static uint32_t acpiPm1aCtlReadw (ACPIState *s, uint32_t addr)
772{
773 uint16_t val = s->pm1a_ctl;
774 Log (("acpi: acpiPm1aCtlReadw -> %#x\n", val));
775 return val;
776}
777
778static int acpiPM1aCtlWritew (ACPIState *s, uint32_t addr, uint32_t val)
779{
780 uint32_t uSleepState;
781
782 Log (("acpi: acpiPM1aCtlWritew <- %#x (%#x)\n", val, val & ~(RSR_CNT | IGN_CNT)));
783 s->pm1a_ctl = val & ~(RSR_CNT | IGN_CNT);
784
785 uSleepState = (s->pm1a_ctl >> SLP_TYPx_SHIFT) & SLP_TYPx_MASK;
786 if (uSleepState != s->uSleepState)
787 {
788 s->uSleepState = uSleepState;
789 switch (uSleepState)
790 {
791 case 0x00: /* S0 */
792 break;
793 case 0x05: /* S5 */
794 LogRel (("Entering S5 (power down)\n"));
795 return acpiPowerDown (s);
796 default:
797 AssertMsgFailed (("Unknown sleep state %#x\n", uSleepState));
798 break;
799 }
800 }
801 return VINF_SUCCESS;
802}
803
804/* GPE0_BLK */
805static uint32_t acpiGpe0EnReadb (ACPIState *s, uint32_t addr)
806{
807 uint8_t val = s->gpe0_en;
808 Log (("acpi: acpiGpe0EnReadl -> %#x\n", val));
809 return val;
810}
811
812static void acpiGpe0EnWriteb (ACPIState *s, uint32_t addr, uint32_t val)
813{
814 Log (("acpi: acpiGpe0EnWritel <- %#x\n", val));
815 update_gpe0 (s, s->gpe0_sts, val);
816}
817
818static uint32_t acpiGpe0StsReadb (ACPIState *s, uint32_t addr)
819{
820 uint8_t val = s->gpe0_sts;
821 Log (("acpi: acpiGpe0StsReadl -> %#x\n", val));
822 return val;
823}
824
825static void acpiGpe0StsWriteb (ACPIState *s, uint32_t addr, uint32_t val)
826{
827 val = s->gpe0_sts & ~val;
828 update_gpe0 (s, val, s->gpe0_en);
829 Log (("acpi: acpiGpe0StsWritel <- %#x\n", val));
830}
831
832static int acpiResetWriteU8(ACPIState *s, uint32_t addr, uint32_t val)
833{
834 int rc = VINF_SUCCESS;
835
836 Log(("ACPI: acpiResetWriteU8: %x %x\n", addr, val));
837 if (val == ACPI_RESET_REG_VAL)
838 {
839# ifndef IN_RING3
840 rc = VINF_IOM_HC_IOPORT_WRITE;
841# else /* IN_RING3 */
842 rc = PDMDevHlpVMReset(s->pDevIns);
843# endif /* !IN_RING3 */
844 }
845 return rc;
846}
847
848/* SMI */
849static void acpiSmiWriteU8 (ACPIState *s, uint32_t addr, uint32_t val)
850{
851 Log (("acpi: acpiSmiWriteU8 %#x\n", val));
852 if (val == ACPI_ENABLE)
853 s->pm1a_ctl |= SCI_EN;
854 else if (val == ACPI_DISABLE)
855 s->pm1a_ctl &= ~SCI_EN;
856 else
857 Log (("acpi: acpiSmiWriteU8 %#x <- unknown value\n", val));
858}
859
860static uint32_t find_rsdp_space (void)
861{
862 return 0xe0000;
863}
864
865static void acpiPMTimerReset (ACPIState *s)
866{
867 uint64_t interval, freq;
868
869 freq = TMTimerGetFreq (s->CTXSUFF(ts));
870 interval = muldiv64 (0xffffffff, freq, PM_TMR_FREQ);
871 Log (("interval = %RU64\n", interval));
872 TMTimerSet (s->CTXSUFF(ts), TMTimerGet (s->CTXSUFF(ts)) + interval);
873}
874
875static DECLCALLBACK(void) acpiTimer (PPDMDEVINS pDevIns, PTMTIMER pTimer)
876{
877 ACPIState *s = PDMINS2DATA (pDevIns, ACPIState *);
878
879 Log (("acpi: pm timer sts %#x (%d), en %#x (%d)\n",
880 s->pm1a_sts, (s->pm1a_sts & TMR_STS) != 0,
881 s->pm1a_en, (s->pm1a_en & TMR_EN) != 0));
882
883 update_pm1a (s, s->pm1a_sts | TMR_STS, s->pm1a_en);
884 acpiPMTimerReset (s);
885}
886
887/**
888 * _BST method.
889 */
890static void acpiFetchBatteryStatus (ACPIState *s)
891{
892 uint32_t *p = s->au8BatteryInfo;
893 bool fPresent; /* battery present? */
894 PDMACPIBATCAPACITY hostRemainingCapacity; /* 0..100 */
895 PDMACPIBATSTATE hostBatteryState; /* bitfield */
896 uint32_t hostPresentRate; /* 0..1000 */
897 int rc;
898
899 rc = s->pDrv->pfnQueryBatteryStatus (s->pDrv, &fPresent, &hostRemainingCapacity,
900 &hostBatteryState, &hostPresentRate);
901 AssertRC (rc);
902
903 /* default values */
904 p[BAT_STATUS_STATE] = hostBatteryState;
905 p[BAT_STATUS_PRESENT_RATE] = hostPresentRate == ~0U ? 0xFFFFFFFF
906 : hostPresentRate * 50; /* mW */
907 p[BAT_STATUS_REMAINING_CAPACITY] = 50000; /* mWh */
908 p[BAT_STATUS_PRESENT_VOLTAGE] = 10000; /* mV */
909
910 /* did we get a valid battery state? */
911 if (hostRemainingCapacity != PDM_ACPI_BAT_CAPACITY_UNKNOWN)
912 p[BAT_STATUS_REMAINING_CAPACITY] = hostRemainingCapacity * 500; /* mWh */
913 if (hostBatteryState == PDM_ACPI_BAT_STATE_CHARGED)
914 p[BAT_STATUS_PRESENT_RATE] = 0; /* mV */
915}
916
917/**
918 * _BIF method.
919 */
920static void acpiFetchBatteryInfo (ACPIState *s)
921{
922 uint32_t *p = s->au8BatteryInfo;
923
924 p[BAT_INFO_UNITS] = 0; /* mWh */
925 p[BAT_INFO_DESIGN_CAPACITY] = 50000; /* mWh */
926 p[BAT_INFO_LAST_FULL_CHARGE_CAPACITY] = 50000; /* mWh */
927 p[BAT_INFO_TECHNOLOGY] = BAT_TECH_PRIMARY;
928 p[BAT_INFO_DESIGN_VOLTAGE] = 10000; /* mV */
929 p[BAT_INFO_DESIGN_CAPACITY_OF_WARNING] = 100; /* mWh */
930 p[BAT_INFO_DESIGN_CAPACITY_OF_LOW] = 50; /* mWh */
931 p[BAT_INFO_CAPACITY_GRANULARITY_1] = 1; /* mWh */
932 p[BAT_INFO_CAPACITY_GRANULARITY_2] = 1; /* mWh */
933}
934
935/**
936 * _STA method.
937 */
938static uint32_t acpiGetBatteryDeviceStatus (ACPIState *s)
939{
940 bool fPresent; /* battery present? */
941 PDMACPIBATCAPACITY hostRemainingCapacity; /* 0..100 */
942 PDMACPIBATSTATE hostBatteryState; /* bitfield */
943 uint32_t hostPresentRate; /* 0..1000 */
944 int rc;
945
946 rc = s->pDrv->pfnQueryBatteryStatus (s->pDrv, &fPresent, &hostRemainingCapacity,
947 &hostBatteryState, &hostPresentRate);
948 AssertRC (rc);
949
950 return fPresent
951 ? STA_DEVICE_PRESENT_MASK /* present */
952 | STA_DEVICE_ENABLED_MASK /* enabled and decodes its resources */
953 | STA_DEVICE_SHOW_IN_UI_MASK /* should be shown in UI */
954 | STA_DEVICE_FUNCTIONING_PROPERLY_MASK /* functioning properly */
955 | STA_BATTERY_PRESENT_MASK /* battery is present */
956 : 0; /* device not present */
957}
958
959static uint32_t acpiGetPowerSource (ACPIState *s)
960{
961 PDMACPIPOWERSOURCE ps;
962
963 /* query the current power source from the host driver */
964 int rc = s->pDrv->pfnQueryPowerSource (s->pDrv, &ps);
965 AssertRC (rc);
966 return ps == PDM_ACPI_POWER_SOURCE_BATTERY ? AC_OFFLINE : AC_ONLINE;
967}
968
969IO_WRITE_PROTO (acpiBatIndexWrite)
970{
971 ACPIState *s = (ACPIState *)pvUser;
972
973 switch (cb)
974 {
975 case 4:
976 u32 >>= s->u8IndexShift;
977 Assert (u32 < BAT_INDEX_LAST);
978 s->uBatteryIndex = u32;
979 break;
980 default:
981 AssertMsgFailed(("Port=%#x cb=%d u32=%#x\n", Port, cb, u32));
982 break;
983 }
984 return VINF_SUCCESS;
985}
986
987IO_READ_PROTO (acpiBatDataRead)
988{
989 ACPIState *s = (ACPIState *)pvUser;
990
991 switch (cb)
992 {
993 case 4:
994 switch (s->uBatteryIndex)
995 {
996 case BAT_STATUS_STATE:
997 acpiFetchBatteryStatus(s);
998 case BAT_STATUS_PRESENT_RATE:
999 case BAT_STATUS_REMAINING_CAPACITY:
1000 case BAT_STATUS_PRESENT_VOLTAGE:
1001 *pu32 = s->au8BatteryInfo[s->uBatteryIndex];
1002 break;
1003
1004 case BAT_INFO_UNITS:
1005 acpiFetchBatteryInfo(s);
1006 case BAT_INFO_DESIGN_CAPACITY:
1007 case BAT_INFO_LAST_FULL_CHARGE_CAPACITY:
1008 case BAT_INFO_TECHNOLOGY:
1009 case BAT_INFO_DESIGN_VOLTAGE:
1010 case BAT_INFO_DESIGN_CAPACITY_OF_WARNING:
1011 case BAT_INFO_DESIGN_CAPACITY_OF_LOW:
1012 case BAT_INFO_CAPACITY_GRANULARITY_1:
1013 case BAT_INFO_CAPACITY_GRANULARITY_2:
1014 *pu32 = s->au8BatteryInfo[s->uBatteryIndex];
1015 break;
1016
1017 case BAT_DEVICE_STATUS:
1018 *pu32 = acpiGetBatteryDeviceStatus(s);
1019 break;
1020
1021 case BAT_POWER_SOURCE:
1022 *pu32 = acpiGetPowerSource(s);
1023 break;
1024
1025 default:
1026 AssertMsgFailed (("Invalid battery index %d\n", s->uBatteryIndex));
1027 break;
1028 }
1029 break;
1030 default:
1031 return VERR_IOM_IOPORT_UNUSED;
1032 }
1033// LogRel(("Query %04x => %08x\n", s->uBatteryIndex, *pu32));
1034 return VINF_SUCCESS;
1035}
1036
1037IO_WRITE_PROTO (acpiSysInfoIndexWrite)
1038{
1039 ACPIState *s = (ACPIState *)pvUser;
1040
1041 Log(("system_index = %d, %d\n", u32, u32 >> 2));
1042 switch (cb) {
1043 case 4:
1044 if (u32 == SYSTEM_INFO_INDEX_VALID || u32 == SYSTEM_INFO_INDEX_INVALID)
1045 s->uSystemInfoIndex = u32;
1046 else
1047 {
1048 u32 >>= s->u8IndexShift;
1049 Assert (u32 < SYSTEM_INFO_INDEX_LAST);
1050 s->uSystemInfoIndex = u32;
1051 }
1052 break;
1053
1054 default:
1055 AssertMsgFailed(("Port=%#x cb=%d u32=%#x\n", Port, cb, u32));
1056 break;
1057 }
1058 return VINF_SUCCESS;
1059}
1060
1061IO_READ_PROTO (acpiSysInfoDataRead)
1062{
1063 ACPIState *s = (ACPIState *)pvUser;
1064
1065 switch (cb)
1066 {
1067 case 4:
1068 switch (s->uSystemInfoIndex)
1069 {
1070 case SYSTEM_INFO_INDEX_MEMORY_LENGTH:
1071 *pu32 = s->u64RamSize;
1072 break;
1073
1074 case SYSTEM_INFO_INDEX_USE_IOAPIC:
1075 *pu32 = s->u8UseIOApic;
1076 break;
1077
1078 default:
1079 AssertMsgFailed (("Invalid system info index %d\n", s->uSystemInfoIndex));
1080 break;
1081 }
1082 break;
1083
1084 default:
1085 return VERR_IOM_IOPORT_UNUSED;
1086 }
1087
1088 Log(("index %d val %d\n", s->uSystemInfoIndex, *pu32));
1089 return VINF_SUCCESS;
1090}
1091
1092IO_WRITE_PROTO (acpiSysInfoDataWrite)
1093{
1094 ACPIState *s = (ACPIState *)pvUser;
1095
1096 Log(("addr=%#x cb=%d u32=%#x si=%#x\n", Port, cb, u32, s->uSystemInfoIndex));
1097
1098 if (cb == 4 && u32 == 0xbadc0de)
1099 {
1100 switch (s->uSystemInfoIndex)
1101 {
1102 case SYSTEM_INFO_INDEX_INVALID:
1103 s->u8IndexShift = 0;
1104 break;
1105
1106 case SYSTEM_INFO_INDEX_VALID:
1107 s->u8IndexShift = 2;
1108 break;
1109
1110 default:
1111 AssertMsgFailed(("Port=%#x cb=%d u32=%#x system_index=%#x\n",
1112 Port, cb, u32, s->uSystemInfoIndex));
1113 break;
1114 }
1115 }
1116 else
1117 AssertMsgFailed(("Port=%#x cb=%d u32=%#x\n", Port, cb, u32));
1118 return VINF_SUCCESS;
1119}
1120
1121/* IO Helpers */
1122IO_READ_PROTO (acpiPm1aEnRead)
1123{
1124 switch (cb)
1125 {
1126 case 2:
1127 *pu32 = acpiPm1aEnReadw ((ACPIState*)pvUser, Port);
1128 break;
1129 default:
1130 return VERR_IOM_IOPORT_UNUSED;
1131 }
1132 return VINF_SUCCESS;
1133}
1134
1135IO_READ_PROTO (acpiPm1aStsRead)
1136{
1137 switch (cb)
1138 {
1139 case 2:
1140 *pu32 = acpiPm1aStsReadw ((ACPIState*)pvUser, Port);
1141 break;
1142 default:
1143 return VERR_IOM_IOPORT_UNUSED;
1144 }
1145 return VINF_SUCCESS;
1146}
1147
1148IO_READ_PROTO (acpiPm1aCtlRead)
1149{
1150 switch (cb)
1151 {
1152 case 2:
1153 *pu32 = acpiPm1aCtlReadw ((ACPIState*)pvUser, Port);
1154 break;
1155 default:
1156 return VERR_IOM_IOPORT_UNUSED;
1157 }
1158 return VINF_SUCCESS;
1159}
1160
1161IO_WRITE_PROTO (acpiPM1aEnWrite)
1162{
1163 switch (cb)
1164 {
1165 case 2:
1166 acpiPM1aEnWritew ((ACPIState*)pvUser, Port, u32);
1167 break;
1168 default:
1169 AssertMsgFailed(("Port=%#x cb=%d u32=%#x\n", Port, cb, u32));
1170 break;
1171 }
1172 return VINF_SUCCESS;
1173}
1174
1175IO_WRITE_PROTO (acpiPM1aStsWrite)
1176{
1177 switch (cb)
1178 {
1179 case 2:
1180 acpiPM1aStsWritew ((ACPIState*)pvUser, Port, u32);
1181 break;
1182 default:
1183 AssertMsgFailed(("Port=%#x cb=%d u32=%#x\n", Port, cb, u32));
1184 break;
1185 }
1186 return VINF_SUCCESS;
1187}
1188
1189IO_WRITE_PROTO (acpiPM1aCtlWrite)
1190{
1191 switch (cb)
1192 {
1193 case 2:
1194 return acpiPM1aCtlWritew ((ACPIState*)pvUser, Port, u32);
1195 default:
1196 AssertMsgFailed(("Port=%#x cb=%d u32=%#x\n", Port, cb, u32));
1197 break;
1198 }
1199 return VINF_SUCCESS;
1200}
1201
1202#endif /* IN_RING3 */
1203
1204/**
1205 * PMTMR readable from host/guest.
1206 */
1207IO_READ_PROTO (acpiPMTmrRead)
1208{
1209 if (cb == 4)
1210 {
1211 ACPIState *s = PDMINS2DATA (pDevIns, ACPIState *);
1212 int64_t now = TMTimerGet (s->CTXSUFF(ts));
1213 int64_t elapsed = now - s->pm_timer_initial;
1214
1215 *pu32 = muldiv64 (elapsed, PM_TMR_FREQ, TMTimerGetFreq (s->CTXSUFF(ts)));
1216 Log (("acpi: acpiPMTmrRead -> %#x\n", *pu32));
1217 return VINF_SUCCESS;
1218 }
1219 return VERR_IOM_IOPORT_UNUSED;
1220}
1221
1222#ifdef IN_RING3
1223
1224IO_READ_PROTO (acpiGpe0StsRead)
1225{
1226 switch (cb)
1227 {
1228 case 1:
1229 *pu32 = acpiGpe0StsReadb ((ACPIState*)pvUser, Port);
1230 break;
1231 default:
1232 return VERR_IOM_IOPORT_UNUSED;
1233 }
1234 return VINF_SUCCESS;
1235}
1236
1237IO_READ_PROTO (acpiGpe0EnRead)
1238{
1239 switch (cb)
1240 {
1241 case 1:
1242 *pu32 = acpiGpe0EnReadb ((ACPIState*)pvUser, Port);
1243 break;
1244 default:
1245 return VERR_IOM_IOPORT_UNUSED;
1246 }
1247 return VINF_SUCCESS;
1248}
1249
1250IO_WRITE_PROTO (acpiGpe0StsWrite)
1251{
1252 switch (cb)
1253 {
1254 case 1:
1255 acpiGpe0StsWriteb ((ACPIState*)pvUser, Port, u32);
1256 break;
1257 default:
1258 AssertMsgFailed(("Port=%#x cb=%d u32=%#x\n", Port, cb, u32));
1259 break;
1260 }
1261 return VINF_SUCCESS;
1262}
1263
1264IO_WRITE_PROTO (acpiGpe0EnWrite)
1265{
1266 switch (cb)
1267 {
1268 case 1:
1269 acpiGpe0EnWriteb ((ACPIState*)pvUser, Port, u32);
1270 break;
1271 default:
1272 AssertMsgFailed(("Port=%#x cb=%d u32=%#x\n", Port, cb, u32));
1273 break;
1274 }
1275 return VINF_SUCCESS;
1276}
1277
1278IO_WRITE_PROTO (acpiSmiWrite)
1279{
1280 switch (cb)
1281 {
1282 case 1:
1283 acpiSmiWriteU8 ((ACPIState*)pvUser, Port, u32);
1284 break;
1285 default:
1286 AssertMsgFailed(("Port=%#x cb=%d u32=%#x\n", Port, cb, u32));
1287 break;
1288 }
1289 return VINF_SUCCESS;
1290}
1291
1292IO_WRITE_PROTO (acpiResetWrite)
1293{
1294 switch (cb)
1295 {
1296 case 1:
1297 return acpiResetWriteU8 ((ACPIState*)pvUser, Port, u32);
1298 default:
1299 AssertMsgFailed(("Port=%#x cb=%d u32=%#x\n", Port, cb, u32));
1300 break;
1301 }
1302 return VINF_SUCCESS;
1303}
1304
1305#ifdef DEBUG_ACPI
1306
1307IO_WRITE_PROTO (acpiDhexWrite)
1308{
1309 switch (cb)
1310 {
1311 case 1:
1312 Log (("%#x\n", u32 & 0xff));
1313 break;
1314 case 2:
1315 Log (("%#6x\n", u32 & 0xffff));
1316 case 4:
1317 Log (("%#10x\n", u32));
1318 break;
1319 default:
1320 AssertMsgFailed(("Port=%#x cb=%d u32=%#x\n", Port, cb, u32));
1321 break;
1322 }
1323 return VINF_SUCCESS;
1324}
1325
1326IO_WRITE_PROTO (acpiDchrWrite)
1327{
1328 switch (cb)
1329 {
1330 case 1:
1331 Log (("%c", u32 & 0xff));
1332 break;
1333 default:
1334 AssertMsgFailed(("Port=%#x cb=%d u32=%#x\n", Port, cb, u32));
1335 break;
1336 }
1337 return VINF_SUCCESS;
1338}
1339
1340#endif /* DEBUG_ACPI */
1341
1342
1343/**
1344 * Saved state structure description.
1345 */
1346static const SSMFIELD g_AcpiSavedStateFields[] =
1347{
1348 SSMFIELD_ENTRY (ACPIState, pm1a_en),
1349 SSMFIELD_ENTRY (ACPIState, pm1a_sts),
1350 SSMFIELD_ENTRY (ACPIState, pm1a_ctl),
1351 SSMFIELD_ENTRY (ACPIState, pm_timer_initial),
1352 SSMFIELD_ENTRY (ACPIState, gpe0_en),
1353 SSMFIELD_ENTRY (ACPIState, gpe0_sts),
1354 SSMFIELD_ENTRY (ACPIState, uBatteryIndex),
1355 SSMFIELD_ENTRY (ACPIState, uSystemInfoIndex),
1356 SSMFIELD_ENTRY (ACPIState, u64RamSize),
1357 SSMFIELD_ENTRY (ACPIState, u8IndexShift),
1358 SSMFIELD_ENTRY (ACPIState, u8UseIOApic),
1359 SSMFIELD_ENTRY (ACPIState, uSleepState),
1360 SSMFIELD_ENTRY_TERM ()
1361};
1362
1363static DECLCALLBACK(int) acpi_save_state (PPDMDEVINS pDevIns, PSSMHANDLE pSSMHandle)
1364{
1365 ACPIState *s = PDMINS2DATA (pDevIns, ACPIState *);
1366 return SSMR3PutStruct (pSSMHandle, s, &g_AcpiSavedStateFields[0]);
1367}
1368
1369static DECLCALLBACK(int) acpi_load_state (PPDMDEVINS pDevIns, PSSMHANDLE pSSMHandle,
1370 uint32_t u32Version)
1371{
1372 ACPIState *s = PDMINS2DATA (pDevIns, ACPIState *);
1373 int rc;
1374
1375 if (u32Version != 4)
1376 return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
1377
1378 rc = SSMR3GetStruct (pSSMHandle, s, &g_AcpiSavedStateFields[0]);
1379 if (VBOX_SUCCESS (rc))
1380 {
1381 acpiFetchBatteryStatus (s);
1382 acpiFetchBatteryInfo (s);
1383 acpiPMTimerReset (s);
1384 }
1385 return rc;
1386}
1387
1388/**
1389 * Queries an interface to the driver.
1390 *
1391 * @returns Pointer to interface.
1392 * @returns NULL if the interface was not supported by the driver.
1393 * @param pInterface Pointer to this interface structure.
1394 * @param enmInterface The requested interface identification.
1395 * @thread Any thread.
1396 */
1397static DECLCALLBACK(void *) acpiQueryInterface(PPDMIBASE pInterface, PDMINTERFACE enmInterface)
1398{
1399 ACPIState *pData = (ACPIState*)((uintptr_t)pInterface - RT_OFFSETOF(ACPIState, IBase));
1400 switch (enmInterface)
1401 {
1402 case PDMINTERFACE_BASE:
1403 return &pData->IBase;
1404 case PDMINTERFACE_ACPI_PORT:
1405 return &pData->IACPIPort;
1406 default:
1407 return NULL;
1408 }
1409}
1410
1411/**
1412 * Create the ACPI tables.
1413 */
1414static int acpiPlantTables (ACPIState *s)
1415{
1416 int rc;
1417 uint32_t rsdt_addr, xsdt_addr, fadt_addr, facs_addr, dsdt_addr, last_addr, apic_addr = 0;
1418 uint32_t addend = 0;
1419 uint32_t rsdt_addrs[4];
1420 uint32_t cAddr;
1421 size_t rsdt_tbl_len = sizeof(ACPITBLHEADER);
1422 size_t xsdt_tbl_len = sizeof(ACPITBLHEADER);
1423
1424 cAddr = 1; /* FADT */
1425 if (s->u8UseIOApic)
1426 cAddr++; /* MADT */
1427
1428 rsdt_tbl_len += cAddr*4; /* each entry: 32 bits phys. address. */
1429 xsdt_tbl_len += cAddr*8; /* each entry: 64 bits phys. address. */
1430
1431 rc = CFGMR3QueryU64 (s->pDevIns->pCfgHandle, "RamSize", &s->u64RamSize);
1432 if (VBOX_FAILURE (rc))
1433 return PDMDEV_SET_ERROR(s->pDevIns, rc,
1434 N_("Configuration error: Querying "
1435 "\"RamSize\" as integer failed"));
1436
1437 if (s->u64RamSize > (0xffffffff - 0x10000))
1438 return PDMDEV_SET_ERROR(s->pDevIns, VERR_OUT_OF_RANGE,
1439 N_("Configuration error: Invalid \"RamSize\", maximum allowed "
1440 "value is 4095MB"));
1441
1442 rsdt_addr = 0;
1443 xsdt_addr = RT_ALIGN_32 (rsdt_addr + rsdt_tbl_len, 16);
1444 fadt_addr = RT_ALIGN_32 (xsdt_addr + xsdt_tbl_len, 16);
1445 facs_addr = RT_ALIGN_32 (fadt_addr + sizeof(ACPITBLFADT), 16);
1446 if (s->u8UseIOApic)
1447 {
1448 apic_addr = RT_ALIGN_32 (facs_addr + sizeof(ACPITBLFACS), 16);
1449 dsdt_addr = RT_ALIGN_32 (apic_addr + sizeof(ACPITBLMADT), 16);
1450 }
1451 else
1452 {
1453 dsdt_addr = RT_ALIGN_32 (facs_addr + sizeof(ACPITBLFACS), 16);
1454 }
1455
1456 last_addr = RT_ALIGN_32 (dsdt_addr + sizeof(AmlCode), 16);
1457 if (last_addr > 0x10000)
1458 return PDMDEV_SET_ERROR(s->pDevIns, VERR_TOO_MUCH_DATA,
1459 N_("Error: ACPI tables > 64KB!"));
1460
1461 Log(("RSDP 0x%08X\n", find_rsdp_space()));
1462 addend = (uint32_t) s->u64RamSize - 0x10000;
1463 Log(("RSDT 0x%08X XSDT 0x%08X\n", rsdt_addr + addend, xsdt_addr + addend));
1464 Log(("FACS 0x%08X FADT 0x%08X\n", facs_addr + addend, fadt_addr + addend));
1465 Log(("DSDT 0x%08X\n", dsdt_addr + addend));
1466 acpiSetupRSDP ((ACPITBLRSDP*)s->au8RSDPPage, rsdt_addr + addend, xsdt_addr + addend);
1467 acpiSetupDSDT (s, dsdt_addr + addend);
1468 acpiSetupFACS (s, facs_addr + addend);
1469 acpiSetupFADT (s, fadt_addr + addend, facs_addr + addend, dsdt_addr + addend);
1470
1471 rsdt_addrs[0] = fadt_addr + addend;
1472 if (s->u8UseIOApic)
1473 {
1474 acpiSetupMADT (s, apic_addr + addend);
1475 rsdt_addrs[1] = apic_addr + addend;
1476 }
1477
1478 rc = acpiSetupRSDT (s, rsdt_addr + addend, cAddr, rsdt_addrs);
1479 if (VBOX_FAILURE(rc))
1480 return rc;
1481 return acpiSetupXSDT (s, xsdt_addr + addend, cAddr, rsdt_addrs);
1482}
1483
1484/**
1485 * Construct a device instance for a VM.
1486 *
1487 * @returns VBox status.
1488 * @param pDevIns The device instance data.
1489 * If the registration structure is needed, pDevIns->pDevReg points to it.
1490 * @param iInstance Instance number. Use this to figure out which registers and such to use.
1491 * The device number is also found in pDevIns->iInstance, but since it's
1492 * likely to be freqently used PDM passes it as parameter.
1493 * @param pCfgHandle Configuration node handle for the device. Use this to obtain the configuration
1494 * of the device instance. It's also found in pDevIns->pCfgHandle, but like
1495 * iInstance it's expected to be used a bit in this function.
1496 */
1497static DECLCALLBACK(int) acpiConstruct (PPDMDEVINS pDevIns, int iInstance, PCFGMNODE pCfgHandle)
1498{
1499 int rc;
1500 ACPIState *s = PDMINS2DATA (pDevIns, ACPIState *);
1501 uint32_t rsdp_addr;
1502 PCIDevice *dev;
1503 bool fGCEnabled;
1504 bool fR0Enabled;
1505
1506 /* Validate and read the configuration. */
1507 if (!CFGMR3AreValuesValid (pCfgHandle, "RamSize\0IOAPIC\0GCEnabled\0R0Enabled\0"))
1508 return PDMDEV_SET_ERROR(pDevIns, VERR_PDM_DEVINS_UNKNOWN_CFG_VALUES,
1509 N_("Configuration error: Invalid config key for ACPI device"));
1510
1511 s->pDevIns = pDevIns;
1512
1513 /* query whether we are supposed to present an IOAPIC */
1514 rc = CFGMR3QueryU8 (pCfgHandle, "IOAPIC", &s->u8UseIOApic);
1515 if (rc == VERR_CFGM_VALUE_NOT_FOUND)
1516 s->u8UseIOApic = 1;
1517 else if (VBOX_FAILURE (rc))
1518 return PDMDEV_SET_ERROR(pDevIns, rc,
1519 N_("Configuration error: Failed to read \"IOAPIC\"."));
1520
1521 rc = CFGMR3QueryBool (pCfgHandle, "GCEnabled", &fGCEnabled);
1522 if (rc == VERR_CFGM_VALUE_NOT_FOUND)
1523 fGCEnabled = true;
1524 else if (VBOX_FAILURE (rc))
1525 return PDMDEV_SET_ERROR(pDevIns, rc,
1526 N_("Configuration error: Failed to read \"GCEnabled\"."));
1527
1528 rc = CFGMR3QueryBool(pCfgHandle, "R0Enabled", &fR0Enabled);
1529 if (rc == VERR_CFGM_VALUE_NOT_FOUND)
1530 fR0Enabled = true;
1531 else if (VBOX_FAILURE(rc))
1532 return PDMDEV_SET_ERROR(pDevIns, rc,
1533 N_("configuration error: failed to read R0Enabled as boolean."));
1534
1535 /* */
1536 rsdp_addr = find_rsdp_space ();
1537 if (!rsdp_addr)
1538 return PDMDEV_SET_ERROR(pDevIns, VERR_NO_MEMORY,
1539 N_("Can not find space for RSDP. ACPI is disabled."));
1540
1541 rc = acpiPlantTables (s);
1542 if (VBOX_FAILURE (rc))
1543 return rc;
1544
1545 rc = PDMDevHlpROMRegister (pDevIns, rsdp_addr, 0x1000, s->au8RSDPPage, "ACPI RSDP");
1546 if (VBOX_FAILURE (rc))
1547 return rc;
1548
1549#define R(addr, cnt, writer, reader, description) \
1550 do { \
1551 rc = PDMDevHlpIOPortRegister (pDevIns, addr, cnt, s, writer, reader, \
1552 NULL, NULL, description); \
1553 if (VBOX_FAILURE (rc)) \
1554 return rc; \
1555 } while (0)
1556#define L (GPE0_BLK_LEN / 2)
1557
1558 R (PM1a_EVT_BLK+2, 1, acpiPM1aEnWrite, acpiPm1aEnRead, "ACPI PM1a Enable");
1559 R (PM1a_EVT_BLK, 1, acpiPM1aStsWrite, acpiPm1aStsRead, "ACPI PM1a Status");
1560 R (PM1a_CTL_BLK, 1, acpiPM1aCtlWrite, acpiPm1aCtlRead, "ACPI PM1a Control");
1561 R (PM_TMR_BLK, 1, NULL, acpiPMTmrRead, "ACPI PM Timer");
1562 R (SMI_CMD, 1, acpiSmiWrite, NULL, "ACPI SMI");
1563#ifdef DEBUG_ACPI
1564 R (DEBUG_HEX, 1, acpiDhexWrite, NULL, "ACPI Debug hex");
1565 R (DEBUG_CHR, 1, acpiDchrWrite, NULL, "ACPI Debug char");
1566#endif
1567 R (BAT_INDEX, 1, acpiBatIndexWrite, NULL, "ACPI Battery status index");
1568 R (BAT_DATA, 1, NULL, acpiBatDataRead, "ACPI Battery status data");
1569 R (SYSI_INDEX, 1, acpiSysInfoIndexWrite, NULL, "ACPI system info index");
1570 R (SYSI_DATA, 1, acpiSysInfoDataWrite, acpiSysInfoDataRead, "ACPI system info data");
1571 R (GPE0_BLK + L, L, acpiGpe0EnWrite, acpiGpe0EnRead, "ACPI GPE0 Enable");
1572 R (GPE0_BLK, L, acpiGpe0StsWrite, acpiGpe0StsRead, "ACPI GPE0 Status");
1573 R (ACPI_RESET_BLK, 1, acpiResetWrite, NULL, "ACPI Reset");
1574#undef L
1575#undef R
1576
1577 /* register GC stuff */
1578 if (fGCEnabled)
1579 {
1580 rc = PDMDevHlpIOPortRegisterGC (pDevIns, PM_TMR_BLK, 1, 0, NULL, "acpiPMTmrRead",
1581 NULL, NULL, "ACPI PM Timer");
1582 AssertRCReturn(rc, rc);
1583 }
1584
1585 /* register R0 stuff */
1586 if (fR0Enabled)
1587 {
1588 rc = PDMDevHlpIOPortRegisterR0 (pDevIns, PM_TMR_BLK, 1, 0, NULL, "acpiPMTmrRead",
1589 NULL, NULL, "ACPI PM Timer");
1590 AssertRCReturn(rc, rc);
1591 }
1592
1593 rc = PDMDevHlpTMTimerCreate (pDevIns, TMCLOCK_VIRTUAL, acpiTimer, "ACPI Timer", &s->tsHC);
1594 if (VBOX_FAILURE(rc))
1595 {
1596 AssertMsgFailed(("pfnTMTimerCreate -> %Vrc\n", rc));
1597 return rc;
1598 }
1599
1600 s->tsGC = TMTimerGCPtr (s->tsHC);
1601 s->pm_timer_initial = TMTimerGet (s->tsHC);
1602 acpiPMTimerReset (s);
1603
1604 dev = &s->dev;
1605 dev->config[0x00] = 0x86;
1606 dev->config[0x01] = 0x80;
1607
1608 dev->config[0x02] = 0x13;
1609 dev->config[0x03] = 0x71;
1610
1611 dev->config[0x04] = 0x01;
1612 dev->config[0x05] = 0x00;
1613
1614 dev->config[0x06] = 0x80;
1615 dev->config[0x07] = 0x02;
1616 dev->config[0x08] = 0x08;
1617 dev->config[0x09] = 0x00;
1618
1619 dev->config[0x0a] = 0x80;
1620 dev->config[0x0b] = 0x06;
1621
1622 dev->config[0x0e] = 0x80;
1623 dev->config[0x0f] = 0x00;
1624
1625#if 0 /* The ACPI controller usually has no subsystem ID. */
1626 dev->config[0x2c] = 0x86;
1627 dev->config[0x2d] = 0x80;
1628 dev->config[0x2e] = 0x00;
1629 dev->config[0x2f] = 0x00;
1630#endif
1631 dev->config[0x3c] = SCI_INT;
1632
1633 rc = PDMDevHlpPCIRegister (pDevIns, dev);
1634 if (VBOX_FAILURE (rc))
1635 return rc;
1636
1637 rc = PDMDevHlpSSMRegister (pDevIns, pDevIns->pDevReg->szDeviceName, iInstance, 4, sizeof(*s),
1638 NULL, acpi_save_state, NULL, NULL, acpi_load_state, NULL);
1639 if (VBOX_FAILURE(rc))
1640 return rc;
1641
1642 /*
1643 * Interfaces
1644 */
1645 /* IBase */
1646 s->IBase.pfnQueryInterface = acpiQueryInterface;
1647 /* IACPIPort */
1648 s->IACPIPort.pfnPowerButtonPress = acpiPowerButtonPress;
1649
1650 /*
1651 * Get the corresponding connector interface
1652 */
1653 rc = PDMDevHlpDriverAttach (pDevIns, 0, &s->IBase, &s->pDrvBase, "ACPI Driver Port");
1654 if (VBOX_SUCCESS (rc))
1655 {
1656 s->pDrv = (PPDMIACPICONNECTOR)s->pDrvBase->pfnQueryInterface (s->pDrvBase,
1657 PDMINTERFACE_ACPI_CONNECTOR);
1658 if (!s->pDrv)
1659 return PDMDEV_SET_ERROR(pDevIns, VERR_PDM_MISSING_INTERFACE,
1660 N_("LUN #0 doesn't have an ACPI connector interface!\n"));
1661 }
1662 else if (rc == VERR_PDM_NO_ATTACHED_DRIVER)
1663 {
1664 Log (("acpi: %s/%d: warning: no driver attached to LUN #0!\n",
1665 pDevIns->pDevReg->szDeviceName, pDevIns->iInstance));
1666 rc = VINF_SUCCESS;
1667 }
1668 else
1669 return PDMDEV_SET_ERROR(pDevIns, rc,
1670 N_("Failed to attach LUN #0!"));
1671
1672 return rc;
1673}
1674
1675/**
1676 * Relocates the GC pointer members.
1677 */
1678static DECLCALLBACK(void) acpiRelocate (PPDMDEVINS pDevIns, RTGCINTPTR offDelta)
1679{
1680 ACPIState *s = PDMINS2DATA (pDevIns, ACPIState *);
1681 s->tsGC = TMTimerGCPtr (s->tsHC);
1682}
1683
1684static DECLCALLBACK(void) acpiReset (PPDMDEVINS pDevIns)
1685{
1686 ACPIState *s = PDMINS2DATA (pDevIns, ACPIState *);
1687
1688 s->pm1a_en = 0;
1689 s->pm1a_sts = 0;
1690 s->pm1a_ctl = 0;
1691 s->pm_timer_initial = TMTimerGet (s->CTXSUFF(ts));
1692 acpiPMTimerReset(s);
1693 s->uBatteryIndex = 0;
1694 s->uSystemInfoIndex = 0;
1695 s->gpe0_en = 0;
1696 s->gpe0_sts = 0;
1697 s->uSleepState = 0;
1698
1699 acpiPlantTables(s);
1700}
1701
1702/**
1703 * The device registration structure.
1704 */
1705const PDMDEVREG g_DeviceACPI =
1706{
1707 /* u32Version */
1708 PDM_DEVREG_VERSION,
1709 /* szDeviceName */
1710 "acpi",
1711 /* szGCMod */
1712 "VBoxDDGC.gc",
1713 /* szR0Mod */
1714 "VBoxDDR0.r0",
1715 /* pszDescription */
1716 "Advanced Configuration and Power Interface",
1717 /* fFlags */
1718 PDM_DEVREG_FLAGS_HOST_BITS_DEFAULT | PDM_DEVREG_FLAGS_GUEST_BITS_DEFAULT | PDM_DEVREG_FLAGS_GC | PDM_DEVREG_FLAGS_R0,
1719 /* fClass */
1720 PDM_DEVREG_CLASS_ACPI,
1721 /* cMaxInstances */
1722 ~0,
1723 /* cbInstance */
1724 sizeof(ACPIState),
1725 /* pfnConstruct */
1726 acpiConstruct,
1727 /* pfnDestruct */
1728 NULL,
1729 /* pfnRelocate */
1730 acpiRelocate,
1731 /* pfnIOCtl */
1732 NULL,
1733 /* pfnPowerOn */
1734 NULL,
1735 /* pfnReset */
1736 acpiReset,
1737 /* pfnSuspend */
1738 NULL,
1739 /* pfnResume */
1740 NULL,
1741 /* pfnAttach */
1742 NULL,
1743 /* pfnDetach */
1744 NULL,
1745 /* pfnQueryInterface. */
1746 NULL
1747};
1748
1749#endif /* IN_RING3 */
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