VirtualBox

source: vbox/trunk/src/VBox/Devices/PC/DevACPI.cpp@ 25776

Last change on this file since 25776 was 25226, checked in by vboxsync, 15 years ago

*: Assert(RT_SUCCESS(rc)) -> AssertRC(rc)
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1/* $Id: DevACPI.cpp 25226 2009-12-08 10:55:32Z vboxsync $ */
2/** @file
3 * DevACPI - Advanced Configuration and Power Interface (ACPI) Device.
4 */
5
6/*
7 * Copyright (C) 2006-2009 Sun Microsystems, Inc.
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 *
17 * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
18 * Clara, CA 95054 USA or visit http://www.sun.com if you need
19 * additional information or have any questions.
20 */
21
22/*******************************************************************************
23* Header Files *
24*******************************************************************************/
25#define LOG_GROUP LOG_GROUP_DEV_ACPI
26#include <VBox/pdmdev.h>
27#include <VBox/pgm.h>
28#include <VBox/log.h>
29#include <VBox/param.h>
30#include <iprt/assert.h>
31#include <iprt/asm.h>
32#ifdef IN_RING3
33# include <iprt/alloc.h>
34# include <iprt/string.h>
35#endif /* IN_RING3 */
36
37#include "../Builtins.h"
38
39#ifdef LOG_ENABLED
40# define DEBUG_ACPI
41#endif
42
43#if defined(IN_RING3) && !defined(VBOX_DEVICE_STRUCT_TESTCASE)
44int acpiPrepareDsdt(PPDMDEVINS pDevIns, void* *ppPtr, size_t *puDsdtLen);
45int acpiCleanupDsdt(PPDMDEVINS pDevIns, void* pPtr);
46#endif /* !IN_RING3 */
47
48
49
50/*******************************************************************************
51* Defined Constants And Macros *
52*******************************************************************************/
53#define DEBUG_HEX 0x3000
54#define DEBUG_CHR 0x3001
55
56#define PM_TMR_FREQ 3579545
57/* Default base for PM PIIX4 device */
58#define PM_PORT_BASE 0x4000
59/* Port offsets in PM device */
60enum
61{
62 PM1a_EVT_OFFSET = 0x00,
63 PM1b_EVT_OFFSET = -1, /**< not supported */
64 PM1a_CTL_OFFSET = 0x04,
65 PM1b_CTL_OFFSET = -1, /**< not supported */
66 PM2_CTL_OFFSET = -1, /**< not supported */
67 PM_TMR_OFFSET = 0x08,
68 GPE0_OFFSET = 0x20,
69 GPE1_OFFSET = -1 /**< not supported */
70};
71
72#define BAT_INDEX 0x00004040
73#define BAT_DATA 0x00004044
74#define SYSI_INDEX 0x00004048
75#define SYSI_DATA 0x0000404c
76#define ACPI_RESET_BLK 0x00004050
77
78/* PM1x status register bits */
79#define TMR_STS RT_BIT(0)
80#define RSR1_STS (RT_BIT(1) | RT_BIT(2) | RT_BIT(3))
81#define BM_STS RT_BIT(4)
82#define GBL_STS RT_BIT(5)
83#define RSR2_STS (RT_BIT(6) | RT_BIT(7))
84#define PWRBTN_STS RT_BIT(8)
85#define SLPBTN_STS RT_BIT(9)
86#define RTC_STS RT_BIT(10)
87#define IGN_STS RT_BIT(11)
88#define RSR3_STS (RT_BIT(12) | RT_BIT(13) | RT_BIT(14))
89#define WAK_STS RT_BIT(15)
90#define RSR_STS (RSR1_STS | RSR2_STS | RSR3_STS)
91
92/* PM1x enable register bits */
93#define TMR_EN RT_BIT(0)
94#define RSR1_EN (RT_BIT(1) | RT_BIT(2) | RT_BIT(3) | RT_BIT(4))
95#define GBL_EN RT_BIT(5)
96#define RSR2_EN (RT_BIT(6) | RT_BIT(7))
97#define PWRBTN_EN RT_BIT(8)
98#define SLPBTN_EN RT_BIT(9)
99#define RTC_EN RT_BIT(10)
100#define RSR3_EN (RT_BIT(11) | RT_BIT(12) | RT_BIT(13) | RT_BIT(14) | RT_BIT(15))
101#define RSR_EN (RSR1_EN | RSR2_EN | RSR3_EN)
102#define IGN_EN 0
103
104/* PM1x control register bits */
105#define SCI_EN RT_BIT(0)
106#define BM_RLD RT_BIT(1)
107#define GBL_RLS RT_BIT(2)
108#define RSR1_CNT (RT_BIT(3) | RT_BIT(4) | RT_BIT(5) | RT_BIT(6) | RT_BIT(7) | RT_BIT(8))
109#define IGN_CNT RT_BIT(9)
110#define SLP_TYPx_SHIFT 10
111#define SLP_TYPx_MASK 7
112#define SLP_EN RT_BIT(13)
113#define RSR2_CNT (RT_BIT(14) | RT_BIT(15))
114#define RSR_CNT (RSR1_CNT | RSR2_CNT)
115
116#define GPE0_BATTERY_INFO_CHANGED RT_BIT(0)
117
118enum
119{
120 BAT_STATUS_STATE = 0x00, /**< BST battery state */
121 BAT_STATUS_PRESENT_RATE = 0x01, /**< BST battery present rate */
122 BAT_STATUS_REMAINING_CAPACITY = 0x02, /**< BST battery remaining capacity */
123 BAT_STATUS_PRESENT_VOLTAGE = 0x03, /**< BST battery present voltage */
124 BAT_INFO_UNITS = 0x04, /**< BIF power unit */
125 BAT_INFO_DESIGN_CAPACITY = 0x05, /**< BIF design capacity */
126 BAT_INFO_LAST_FULL_CHARGE_CAPACITY = 0x06, /**< BIF last full charge capacity */
127 BAT_INFO_TECHNOLOGY = 0x07, /**< BIF battery technology */
128 BAT_INFO_DESIGN_VOLTAGE = 0x08, /**< BIF design voltage */
129 BAT_INFO_DESIGN_CAPACITY_OF_WARNING = 0x09, /**< BIF design capacity of warning */
130 BAT_INFO_DESIGN_CAPACITY_OF_LOW = 0x0A, /**< BIF design capacity of low */
131 BAT_INFO_CAPACITY_GRANULARITY_1 = 0x0B, /**< BIF battery capacity granularity 1 */
132 BAT_INFO_CAPACITY_GRANULARITY_2 = 0x0C, /**< BIF battery capacity granularity 2 */
133 BAT_DEVICE_STATUS = 0x0D, /**< STA device status */
134 BAT_POWER_SOURCE = 0x0E, /**< PSR power source */
135 BAT_INDEX_LAST
136};
137
138enum
139{
140 SYSTEM_INFO_INDEX_LOW_MEMORY_LENGTH = 0,
141 SYSTEM_INFO_INDEX_USE_IOAPIC = 1,
142 SYSTEM_INFO_INDEX_HPET_STATUS = 2,
143 SYSTEM_INFO_INDEX_SMC_STATUS = 3,
144 SYSTEM_INFO_INDEX_FDC_STATUS = 4,
145 SYSTEM_INFO_INDEX_CPU0_STATUS = 5,
146 SYSTEM_INFO_INDEX_CPU1_STATUS = 6,
147 SYSTEM_INFO_INDEX_CPU2_STATUS = 7,
148 SYSTEM_INFO_INDEX_CPU3_STATUS = 8,
149 SYSTEM_INFO_INDEX_HIGH_MEMORY_LENGTH= 9,
150 SYSTEM_INFO_INDEX_RTC_STATUS = 10,
151 SYSTEM_INFO_INDEX_END = 11,
152 SYSTEM_INFO_INDEX_INVALID = 0x80,
153 SYSTEM_INFO_INDEX_VALID = 0x200
154};
155
156#define AC_OFFLINE 0
157#define AC_ONLINE 1
158
159#define BAT_TECH_PRIMARY 1
160#define BAT_TECH_SECONDARY 2
161
162#define STA_DEVICE_PRESENT_MASK RT_BIT(0) /**< present */
163#define STA_DEVICE_ENABLED_MASK RT_BIT(1) /**< enabled and decodes its resources */
164#define STA_DEVICE_SHOW_IN_UI_MASK RT_BIT(2) /**< should be shown in UI */
165#define STA_DEVICE_FUNCTIONING_PROPERLY_MASK RT_BIT(3) /**< functioning properly */
166#define STA_BATTERY_PRESENT_MASK RT_BIT(4) /**< the battery is present */
167
168
169/*******************************************************************************
170* Structures and Typedefs *
171*******************************************************************************/
172/**
173 * The ACPI device state.
174 */
175typedef struct ACPIState
176{
177 PCIDevice dev;
178 uint16_t pm1a_en;
179 uint16_t pm1a_sts;
180 uint16_t pm1a_ctl;
181 /** Number of logical CPUs in guest */
182 uint16_t cCpus;
183 int64_t pm_timer_initial;
184 PTMTIMERR3 tsR3;
185 PTMTIMERR0 tsR0;
186 PTMTIMERRC tsRC;
187
188 uint32_t gpe0_en;
189 uint32_t gpe0_sts;
190
191 unsigned int uBatteryIndex;
192 uint32_t au8BatteryInfo[13];
193
194 unsigned int uSystemInfoIndex;
195 uint64_t u64RamSize;
196 /** The number of bytes above 4GB. */
197 uint64_t cbRamHigh;
198 /** The number of bytes below 4GB. */
199 uint32_t cbRamLow;
200
201 /** Current ACPI S* state. We support S0 and S5 */
202 uint32_t uSleepState;
203 uint8_t au8RSDPPage[0x1000];
204 /** This is a workaround for incorrect index field handling by Intels ACPICA.
205 * The system info _INI method writes to offset 0x200. We either observe a
206 * write request to index 0x80 (in that case we don't change the index) or a
207 * write request to offset 0x200 (in that case we divide the index value by
208 * 4. Note that the _STA method is sometimes called prior to the _INI method
209 * (ACPI spec 6.3.7, _STA). See the special case for BAT_DEVICE_STATUS in
210 * acpiBatIndexWrite() for handling this. */
211 uint8_t u8IndexShift;
212 /** provide an I/O-APIC */
213 uint8_t u8UseIOApic;
214 /** provide a floppy controller */
215 bool fUseFdc;
216 /** If High Precision Event Timer device should be supported */
217 bool fUseHpet;
218 /** If System Management Controller device should be supported */
219 bool fUseSmc;
220 /** the guest handled the last power button event */
221 bool fPowerButtonHandled;
222 /** If ACPI CPU device should be shown */
223 bool fShowCpu;
224 /** If Real Time Clock ACPI object to be shown */
225 bool fShowRtc;
226 /** I/O port address of PM device. */
227 RTIOPORT uPmIoPortBase;
228 /** Flag whether the GC part of the device is enabled. */
229 bool fGCEnabled;
230 /** Flag whether the R0 part of the device is enabled. */
231 bool fR0Enabled;
232 /** Aligning IBase. */
233 bool afAlignment[4];
234
235 /** ACPI port base interface. */
236 PDMIBASE IBase;
237 /** ACPI port interface. */
238 PDMIACPIPORT IACPIPort;
239 /** Pointer to the device instance. */
240 PPDMDEVINSR3 pDevIns;
241 /** Pointer to the driver base interface */
242 R3PTRTYPE(PPDMIBASE) pDrvBase;
243 /** Pointer to the driver connector interface */
244 R3PTRTYPE(PPDMIACPICONNECTOR) pDrv;
245
246 /* Pointer to default PCI config read function */
247 R3PTRTYPE(PFNPCICONFIGREAD) pfnAcpiPciConfigRead;
248 /* Pointer to default PCI config write function */
249 R3PTRTYPE(PFNPCICONFIGWRITE) pfnAcpiPciConfigWrite;
250} ACPIState;
251
252#pragma pack(1)
253
254/** Generic Address Structure (see ACPIspec 3.0, 5.2.3.1) */
255struct ACPIGENADDR
256{
257 uint8_t u8AddressSpaceId; /**< 0=sys, 1=IO, 2=PCICfg, 3=emb, 4=SMBus */
258 uint8_t u8RegisterBitWidth; /**< size in bits of the given register */
259 uint8_t u8RegisterBitOffset; /**< bit offset of register */
260 uint8_t u8AccessSize; /**< 1=byte, 2=word, 3=dword, 4=qword */
261 uint64_t u64Address; /**< 64-bit address of register */
262};
263AssertCompileSize(ACPIGENADDR, 12);
264
265/** Root System Description Pointer */
266struct ACPITBLRSDP
267{
268 uint8_t au8Signature[8]; /**< 'RSD PTR ' */
269 uint8_t u8Checksum; /**< checksum for the first 20 bytes */
270 uint8_t au8OemId[6]; /**< OEM-supplied identifier */
271 uint8_t u8Revision; /**< revision number, currently 2 */
272#define ACPI_REVISION 2 /**< ACPI 3.0 */
273 uint32_t u32RSDT; /**< phys addr of RSDT */
274 uint32_t u32Length; /**< bytes of this table */
275 uint64_t u64XSDT; /**< 64-bit phys addr of XSDT */
276 uint8_t u8ExtChecksum; /**< checksum of entire table */
277 uint8_t u8Reserved[3]; /**< reserved */
278};
279AssertCompileSize(ACPITBLRSDP, 36);
280
281/** System Description Table Header */
282struct ACPITBLHEADER
283{
284 uint8_t au8Signature[4]; /**< table identifier */
285 uint32_t u32Length; /**< length of the table including header */
286 uint8_t u8Revision; /**< revision number */
287 uint8_t u8Checksum; /**< all fields inclusive this add to zero */
288 uint8_t au8OemId[6]; /**< OEM-supplied string */
289 uint8_t au8OemTabId[8]; /**< to identify the particular data table */
290 uint32_t u32OemRevision; /**< OEM-supplied revision number */
291 uint8_t au8CreatorId[4]; /**< ID for the ASL compiler */
292 uint32_t u32CreatorRev; /**< revision for the ASL compiler */
293};
294AssertCompileSize(ACPITBLHEADER, 36);
295
296/** Root System Description Table */
297struct ACPITBLRSDT
298{
299 ACPITBLHEADER header;
300 uint32_t u32Entry[1]; /**< array of phys. addresses to other tables */
301};
302AssertCompileSize(ACPITBLRSDT, 40);
303
304/** Extended System Description Table */
305struct ACPITBLXSDT
306{
307 ACPITBLHEADER header;
308 uint64_t u64Entry[1]; /**< array of phys. addresses to other tables */
309};
310AssertCompileSize(ACPITBLXSDT, 44);
311
312/** Fixed ACPI Description Table */
313struct ACPITBLFADT
314{
315 ACPITBLHEADER header;
316 uint32_t u32FACS; /**< phys. address of FACS */
317 uint32_t u32DSDT; /**< phys. address of DSDT */
318 uint8_t u8IntModel; /**< was eleminated in ACPI 2.0 */
319#define INT_MODEL_DUAL_PIC 1 /**< for ACPI 2+ */
320#define INT_MODEL_MULTIPLE_APIC 2
321 uint8_t u8PreferredPMProfile; /**< preferred power management profile */
322 uint16_t u16SCIInt; /**< system vector the SCI is wired in 8259 mode */
323#define SCI_INT 9
324 uint32_t u32SMICmd; /**< system port address of SMI command port */
325#define SMI_CMD 0x0000442e
326 uint8_t u8AcpiEnable; /**< SMICmd val to disable ownship of ACPIregs */
327#define ACPI_ENABLE 0xa1
328 uint8_t u8AcpiDisable; /**< SMICmd val to re-enable ownship of ACPIregs */
329#define ACPI_DISABLE 0xa0
330 uint8_t u8S4BIOSReq; /**< SMICmd val to enter S4BIOS state */
331 uint8_t u8PStateCnt; /**< SMICmd val to assume processor performance
332 state control responsibility */
333 uint32_t u32PM1aEVTBLK; /**< port addr of PM1a event regs block */
334 uint32_t u32PM1bEVTBLK; /**< port addr of PM1b event regs block */
335 uint32_t u32PM1aCTLBLK; /**< port addr of PM1a control regs block */
336 uint32_t u32PM1bCTLBLK; /**< port addr of PM1b control regs block */
337 uint32_t u32PM2CTLBLK; /**< port addr of PM2 control regs block */
338 uint32_t u32PMTMRBLK; /**< port addr of PMTMR regs block */
339 uint32_t u32GPE0BLK; /**< port addr of gen-purp event 0 regs block */
340 uint32_t u32GPE1BLK; /**< port addr of gen-purp event 1 regs block */
341 uint8_t u8PM1EVTLEN; /**< bytes decoded by PM1a_EVT_BLK. >= 4 */
342 uint8_t u8PM1CTLLEN; /**< bytes decoded by PM1b_CNT_BLK. >= 2 */
343 uint8_t u8PM2CTLLEN; /**< bytes decoded by PM2_CNT_BLK. >= 1 or 0 */
344 uint8_t u8PMTMLEN; /**< bytes decoded by PM_TMR_BLK. ==4 */
345 uint8_t u8GPE0BLKLEN; /**< bytes decoded by GPE0_BLK. %2==0 */
346#define GPE0_BLK_LEN 2
347 uint8_t u8GPE1BLKLEN; /**< bytes decoded by GPE1_BLK. %2==0 */
348#define GPE1_BLK_LEN 0
349 uint8_t u8GPE1BASE; /**< offset of GPE1 based events */
350#define GPE1_BASE 0
351 uint8_t u8CSTCNT; /**< SMICmd val to indicate OS supp for C states */
352 uint16_t u16PLVL2LAT; /**< us to enter/exit C2. >100 => unsupported */
353#define P_LVL2_LAT 101 /**< C2 state not supported */
354 uint16_t u16PLVL3LAT; /**< us to enter/exit C3. >1000 => unsupported */
355#define P_LVL3_LAT 1001 /**< C3 state not supported */
356 uint16_t u16FlushSize; /**< # of flush strides to read to flush dirty
357 lines from any processors memory caches */
358#define FLUSH_SIZE 0 /**< Ignored if WBVIND set in FADT_FLAGS */
359 uint16_t u16FlushStride; /**< cache line width */
360#define FLUSH_STRIDE 0 /**< Ignored if WBVIND set in FADT_FLAGS */
361 uint8_t u8DutyOffset;
362 uint8_t u8DutyWidth;
363 uint8_t u8DayAlarm; /**< RTC CMOS RAM index of day-of-month alarm */
364 uint8_t u8MonAlarm; /**< RTC CMOS RAM index of month-of-year alarm */
365 uint8_t u8Century; /**< RTC CMOS RAM index of century */
366 uint16_t u16IAPCBOOTARCH; /**< IA-PC boot architecture flags */
367#define IAPC_BOOT_ARCH_LEGACY_DEV RT_BIT(0) /**< legacy devices present such as LPT
368 (COM too?) */
369#define IAPC_BOOT_ARCH_8042 RT_BIT(1) /**< legacy keyboard device present */
370#define IAPC_BOOT_ARCH_NO_VGA RT_BIT(2) /**< VGA not present */
371 uint8_t u8Must0_0; /**< must be 0 */
372 uint32_t u32Flags; /**< fixed feature flags */
373#define FADT_FL_WBINVD RT_BIT(0) /**< emulation of WBINVD available */
374#define FADT_FL_WBINVD_FLUSH RT_BIT(1)
375#define FADT_FL_PROC_C1 RT_BIT(2) /**< 1=C1 supported on all processors */
376#define FADT_FL_P_LVL2_UP RT_BIT(3) /**< 1=C2 works on SMP and UNI systems */
377#define FADT_FL_PWR_BUTTON RT_BIT(4) /**< 1=power button handled as ctrl method dev */
378#define FADT_FL_SLP_BUTTON RT_BIT(5) /**< 1=sleep button handled as ctrl method dev */
379#define FADT_FL_FIX_RTC RT_BIT(6) /**< 0=RTC wake status in fixed register */
380#define FADT_FL_RTC_S4 RT_BIT(7) /**< 1=RTC can wake system from S4 */
381#define FADT_FL_TMR_VAL_EXT RT_BIT(8) /**< 1=TMR_VAL implemented as 32 bit */
382#define FADT_FL_DCK_CAP RT_BIT(9) /**< 0=system cannot support docking */
383#define FADT_FL_RESET_REG_SUP RT_BIT(10) /**< 1=system supports system resets */
384#define FADT_FL_SEALED_CASE RT_BIT(11) /**< 1=case is sealed */
385#define FADT_FL_HEADLESS RT_BIT(12) /**< 1=system cannot detect moni/keyb/mouse */
386#define FADT_FL_CPU_SW_SLP RT_BIT(13)
387#define FADT_FL_PCI_EXT_WAK RT_BIT(14) /**< 1=system supports PCIEXP_WAKE_STS */
388#define FADT_FL_USE_PLATFORM_CLOCK RT_BIT(15) /**< 1=system has ACPI PM timer */
389#define FADT_FL_S4_RTC_STS_VALID RT_BIT(16) /**< 1=RTC_STS flag is valid when waking from S4 */
390#define FADT_FL_REMOVE_POWER_ON_CAPABLE RT_BIT(17) /**< 1=platform can remote power on */
391#define FADT_FL_FORCE_APIC_CLUSTER_MODEL RT_BIT(18)
392#define FADT_FL_FORCE_APIC_PHYS_DEST_MODE RT_BIT(19)
393
394 /** Start of the ACPI 2.0 extension. */
395 ACPIGENADDR ResetReg; /**< ext addr of reset register */
396 uint8_t u8ResetVal; /**< ResetReg value to reset the system */
397#define ACPI_RESET_REG_VAL 0x10
398 uint8_t au8Must0_1[3]; /**< must be 0 */
399 uint64_t u64XFACS; /**< 64-bit phys address of FACS */
400 uint64_t u64XDSDT; /**< 64-bit phys address of DSDT */
401 ACPIGENADDR X_PM1aEVTBLK; /**< ext addr of PM1a event regs block */
402 ACPIGENADDR X_PM1bEVTBLK; /**< ext addr of PM1b event regs block */
403 ACPIGENADDR X_PM1aCTLBLK; /**< ext addr of PM1a control regs block */
404 ACPIGENADDR X_PM1bCTLBLK; /**< ext addr of PM1b control regs block */
405 ACPIGENADDR X_PM2CTLBLK; /**< ext addr of PM2 control regs block */
406 ACPIGENADDR X_PMTMRBLK; /**< ext addr of PMTMR control regs block */
407 ACPIGENADDR X_GPE0BLK; /**< ext addr of GPE1 regs block */
408 ACPIGENADDR X_GPE1BLK; /**< ext addr of GPE1 regs block */
409};
410AssertCompileSize(ACPITBLFADT, 244);
411#define ACPITBLFADT_VERSION1_SIZE RT_OFFSETOF(ACPITBLFADT, ResetReg)
412
413/** Firmware ACPI Control Structure */
414struct ACPITBLFACS
415{
416 uint8_t au8Signature[4]; /**< 'FACS' */
417 uint32_t u32Length; /**< bytes of entire FACS structure >= 64 */
418 uint32_t u32HWSignature; /**< systems HW signature at last boot */
419 uint32_t u32FWVector; /**< address of waking vector */
420 uint32_t u32GlobalLock; /**< global lock to sync HW/SW */
421 uint32_t u32Flags; /**< FACS flags */
422 uint64_t u64X_FWVector; /**< 64-bit waking vector */
423 uint8_t u8Version; /**< version of this table */
424 uint8_t au8Reserved[31]; /**< zero */
425};
426AssertCompileSize(ACPITBLFACS, 64);
427
428/** Processor Local APIC Structure */
429struct ACPITBLLAPIC
430{
431 uint8_t u8Type; /**< 0 = LAPIC */
432 uint8_t u8Length; /**< 8 */
433 uint8_t u8ProcId; /**< processor ID */
434 uint8_t u8ApicId; /**< local APIC ID */
435 uint32_t u32Flags; /**< Flags */
436#define LAPIC_ENABLED 0x1
437};
438AssertCompileSize(ACPITBLLAPIC, 8);
439
440/** I/O APIC Structure */
441struct ACPITBLIOAPIC
442{
443 uint8_t u8Type; /**< 1 == I/O APIC */
444 uint8_t u8Length; /**< 12 */
445 uint8_t u8IOApicId; /**< I/O APIC ID */
446 uint8_t u8Reserved; /**< 0 */
447 uint32_t u32Address; /**< phys address to access I/O APIC */
448 uint32_t u32GSIB; /**< global system interrupt number to start */
449};
450AssertCompileSize(ACPITBLIOAPIC, 12);
451
452# ifdef IN_RING3 /** @todo r=bird: Move this down to where it's used. */
453
454# define PCAT_COMPAT 0x1 /**< system has also a dual-8259 setup */
455
456/**
457 * Multiple APIC Description Table.
458 *
459 * This structure looks somewhat convoluted due layout of MADT table in MP case.
460 * There extpected to be multiple LAPIC records for each CPU, thus we cannot
461 * use regular C structure and proxy to raw memory instead.
462 */
463class AcpiTableMADT
464{
465 /**
466 * All actual data stored in dynamically allocated memory pointed by this field.
467 */
468 uint8_t *m_pbData;
469 /**
470 * Number of CPU entries in this MADT.
471 */
472 uint32_t m_cCpus;
473
474public:
475 /**
476 * Address of ACPI header
477 */
478 inline ACPITBLHEADER *header_addr(void) const
479 {
480 return (ACPITBLHEADER *)m_pbData;
481 }
482
483 /**
484 * Address of local APIC for each CPU. Note that different CPUs address different LAPICs,
485 * although address is the same for all of them.
486 */
487 inline uint32_t *u32LAPIC_addr(void) const
488 {
489 return (uint32_t *)(header_addr() + 1);
490 }
491
492 /**
493 * Address of APIC flags
494 */
495 inline uint32_t *u32Flags_addr(void) const
496 {
497 return (uint32_t *)(u32LAPIC_addr() + 1);
498 }
499
500 /**
501 * Address of per-CPU LAPIC descriptions
502 */
503 inline ACPITBLLAPIC *LApics_addr(void) const
504 {
505 return (ACPITBLLAPIC *)(u32Flags_addr() + 1);
506 }
507
508 /**
509 * Address of IO APIC description
510 */
511 inline ACPITBLIOAPIC *IOApic_addr(void) const
512 {
513 return (ACPITBLIOAPIC *)(LApics_addr() + m_cCpus);
514 }
515
516 /**
517 * Size of MADT.
518 * Note that this function assumes IOApic to be the last field in structure.
519 */
520 inline uint32_t size(void) const
521 {
522 return (uint8_t *)(IOApic_addr() + 1) - (uint8_t *)header_addr();
523 }
524
525 /**
526 * Raw data of MADT.
527 */
528 inline const uint8_t *data(void) const
529 {
530 return m_pbData;
531 }
532
533 /**
534 * Size of MADT for given ACPI config, useful to compute layout.
535 */
536 static uint32_t sizeFor(ACPIState *s)
537 {
538 return AcpiTableMADT(s->cCpus).size();
539 }
540
541 /*
542 * Constructor, only works in Ring 3, doesn't look like a big deal.
543 */
544 AcpiTableMADT(uint32_t cCpus)
545 {
546 m_cCpus = cCpus;
547 m_pbData = NULL; /* size() uses this and gcc will complain if not initilized. */
548 uint32_t cb = size();
549 m_pbData = (uint8_t *)RTMemAllocZ(cb);
550 }
551
552 ~AcpiTableMADT()
553 {
554 RTMemFree(m_pbData);
555 }
556};
557# endif /* IN_RING3 */
558
559#pragma pack()
560
561
562#ifndef VBOX_DEVICE_STRUCT_TESTCASE /* exclude the rest of the file */
563/*******************************************************************************
564* Internal Functions *
565*******************************************************************************/
566RT_C_DECLS_BEGIN
567PDMBOTHCBDECL(int) acpiPMTmrRead( PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t *pu32, unsigned cb);
568#ifdef IN_RING3
569PDMBOTHCBDECL(int) acpiPm1aEnRead( PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t *pu32, unsigned cb);
570PDMBOTHCBDECL(int) acpiPM1aEnWrite( PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb);
571PDMBOTHCBDECL(int) acpiPm1aStsRead( PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t *pu32, unsigned cb);
572PDMBOTHCBDECL(int) acpiPM1aStsWrite( PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb);
573PDMBOTHCBDECL(int) acpiPm1aCtlRead( PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t *pu32, unsigned cb);
574PDMBOTHCBDECL(int) acpiPM1aCtlWrite( PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb);
575PDMBOTHCBDECL(int) acpiSmiWrite( PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb);
576PDMBOTHCBDECL(int) acpiBatIndexWrite( PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb);
577PDMBOTHCBDECL(int) acpiBatDataRead( PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t *pu32, unsigned cb);
578PDMBOTHCBDECL(int) acpiSysInfoDataRead( PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t *pu32, unsigned cb);
579PDMBOTHCBDECL(int) acpiSysInfoDataWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb);
580PDMBOTHCBDECL(int) acpiGpe0EnRead( PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t *pu32, unsigned cb);
581PDMBOTHCBDECL(int) acpiGpe0EnWrite( PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb);
582PDMBOTHCBDECL(int) acpiGpe0StsRead( PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t *pu32, unsigned cb);
583PDMBOTHCBDECL(int) acpiGpe0StsWrite( PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb);
584PDMBOTHCBDECL(int) acpiResetWrite( PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb);
585# ifdef DEBUG_ACPI
586PDMBOTHCBDECL(int) acpiDhexWrite( PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb);
587PDMBOTHCBDECL(int) acpiDchrWrite( PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb);
588# endif
589#endif /* IN_RING3 */
590RT_C_DECLS_END
591
592
593#ifdef IN_RING3
594
595static RTIOPORT acpiPmPort(ACPIState* pAcpi, int32_t offset)
596{
597 Assert(pAcpi->uPmIoPortBase != 0);
598
599 if (offset == -1)
600 return 0;
601
602 return RTIOPORT(pAcpi->uPmIoPortBase + offset);
603}
604
605/* Simple acpiChecksum: all the bytes must add up to 0. */
606static uint8_t acpiChecksum(const uint8_t * const data, size_t len)
607{
608 uint8_t sum = 0;
609 for (size_t i = 0; i < len; ++i)
610 sum += data[i];
611 return -sum;
612}
613
614static void acpiPrepareHeader(ACPITBLHEADER *header, const char au8Signature[4],
615 uint32_t u32Length, uint8_t u8Revision)
616{
617 memcpy(header->au8Signature, au8Signature, 4);
618 header->u32Length = RT_H2LE_U32(u32Length);
619 header->u8Revision = u8Revision;
620 memcpy(header->au8OemId, "VBOX ", 6);
621 memcpy(header->au8OemTabId, "VBOX", 4);
622 memcpy(header->au8OemTabId+4, au8Signature, 4);
623 header->u32OemRevision = RT_H2LE_U32(1);
624 memcpy(header->au8CreatorId, "ASL ", 4);
625 header->u32CreatorRev = RT_H2LE_U32(0x61);
626}
627
628static void acpiWriteGenericAddr(ACPIGENADDR *g, uint8_t u8AddressSpaceId,
629 uint8_t u8RegisterBitWidth, uint8_t u8RegisterBitOffset,
630 uint8_t u8AccessSize, uint64_t u64Address)
631{
632 g->u8AddressSpaceId = u8AddressSpaceId;
633 g->u8RegisterBitWidth = u8RegisterBitWidth;
634 g->u8RegisterBitOffset = u8RegisterBitOffset;
635 g->u8AccessSize = u8AccessSize;
636 g->u64Address = RT_H2LE_U64(u64Address);
637}
638
639static void acpiPhyscpy(ACPIState *s, RTGCPHYS32 dst, const void * const src, size_t size)
640{
641 PDMDevHlpPhysWrite(s->pDevIns, dst, src, size);
642}
643
644/** Differentiated System Description Table (DSDT) */
645
646static void acpiSetupDSDT(ACPIState *s, RTGCPHYS32 addr,
647 void* pPtr, size_t uDsdtLen)
648{
649 acpiPhyscpy(s, addr, pPtr, uDsdtLen);
650}
651
652/** Firmware ACPI Control Structure (FACS) */
653static void acpiSetupFACS(ACPIState *s, RTGCPHYS32 addr)
654{
655 ACPITBLFACS facs;
656
657 memset(&facs, 0, sizeof(facs));
658 memcpy(facs.au8Signature, "FACS", 4);
659 facs.u32Length = RT_H2LE_U32(sizeof(ACPITBLFACS));
660 facs.u32HWSignature = RT_H2LE_U32(0);
661 facs.u32FWVector = RT_H2LE_U32(0);
662 facs.u32GlobalLock = RT_H2LE_U32(0);
663 facs.u32Flags = RT_H2LE_U32(0);
664 facs.u64X_FWVector = RT_H2LE_U64(0);
665 facs.u8Version = 1;
666
667 acpiPhyscpy(s, addr, (const uint8_t *)&facs, sizeof(facs));
668}
669
670/** Fixed ACPI Description Table (FADT aka FACP) */
671static void acpiSetupFADT(ACPIState *s, RTGCPHYS32 addr_acpi1, RTGCPHYS32 addr_acpi2, uint32_t facs_addr, uint32_t dsdt_addr)
672{
673 ACPITBLFADT fadt;
674
675 /* First the ACPI version 2+ version of the structure. */
676 memset(&fadt, 0, sizeof(fadt));
677 acpiPrepareHeader(&fadt.header, "FACP", sizeof(fadt), 4);
678 fadt.u32FACS = RT_H2LE_U32(facs_addr);
679 fadt.u32DSDT = RT_H2LE_U32(dsdt_addr);
680 fadt.u8IntModel = 0; /* dropped from the ACPI 2.0 spec. */
681 fadt.u8PreferredPMProfile = 0; /* unspecified */
682 fadt.u16SCIInt = RT_H2LE_U16(SCI_INT);
683 fadt.u32SMICmd = RT_H2LE_U32(SMI_CMD);
684 fadt.u8AcpiEnable = ACPI_ENABLE;
685 fadt.u8AcpiDisable = ACPI_DISABLE;
686 fadt.u8S4BIOSReq = 0;
687 fadt.u8PStateCnt = 0;
688 fadt.u32PM1aEVTBLK = RT_H2LE_U32(acpiPmPort(s, PM1a_EVT_OFFSET));
689 fadt.u32PM1bEVTBLK = RT_H2LE_U32(acpiPmPort(s, PM1b_EVT_OFFSET));
690 fadt.u32PM1aCTLBLK = RT_H2LE_U32(acpiPmPort(s, PM1a_CTL_OFFSET));
691 fadt.u32PM1bCTLBLK = RT_H2LE_U32(acpiPmPort(s, PM1b_CTL_OFFSET));
692 fadt.u32PM2CTLBLK = RT_H2LE_U32(acpiPmPort(s, PM2_CTL_OFFSET));
693 fadt.u32PMTMRBLK = RT_H2LE_U32(acpiPmPort(s, PM_TMR_OFFSET));
694 fadt.u32GPE0BLK = RT_H2LE_U32(acpiPmPort(s, GPE0_OFFSET));
695 fadt.u32GPE1BLK = RT_H2LE_U32(acpiPmPort(s, GPE1_OFFSET));
696 fadt.u8PM1EVTLEN = 4;
697 fadt.u8PM1CTLLEN = 2;
698 fadt.u8PM2CTLLEN = 0;
699 fadt.u8PMTMLEN = 4;
700 fadt.u8GPE0BLKLEN = GPE0_BLK_LEN;
701 fadt.u8GPE1BLKLEN = GPE1_BLK_LEN;
702 fadt.u8GPE1BASE = GPE1_BASE;
703 fadt.u8CSTCNT = 0;
704 fadt.u16PLVL2LAT = RT_H2LE_U16(P_LVL2_LAT);
705 fadt.u16PLVL3LAT = RT_H2LE_U16(P_LVL3_LAT);
706 fadt.u16FlushSize = RT_H2LE_U16(FLUSH_SIZE);
707 fadt.u16FlushStride = RT_H2LE_U16(FLUSH_STRIDE);
708 fadt.u8DutyOffset = 0;
709 fadt.u8DutyWidth = 0;
710 fadt.u8DayAlarm = 0;
711 fadt.u8MonAlarm = 0;
712 fadt.u8Century = 0;
713 fadt.u16IAPCBOOTARCH = RT_H2LE_U16(IAPC_BOOT_ARCH_LEGACY_DEV | IAPC_BOOT_ARCH_8042);
714 /** @note WBINVD is required for ACPI versions newer than 1.0 */
715 fadt.u32Flags = RT_H2LE_U32( FADT_FL_WBINVD
716 | FADT_FL_FIX_RTC
717 | FADT_FL_TMR_VAL_EXT);
718 acpiWriteGenericAddr(&fadt.ResetReg, 1, 8, 0, 1, ACPI_RESET_BLK);
719 fadt.u8ResetVal = ACPI_RESET_REG_VAL;
720 fadt.u64XFACS = RT_H2LE_U64((uint64_t)facs_addr);
721 fadt.u64XDSDT = RT_H2LE_U64((uint64_t)dsdt_addr);
722 acpiWriteGenericAddr(&fadt.X_PM1aEVTBLK, 1, 32, 0, 2, acpiPmPort(s, PM1a_EVT_OFFSET));
723 acpiWriteGenericAddr(&fadt.X_PM1bEVTBLK, 0, 0, 0, 0, acpiPmPort(s, PM1b_EVT_OFFSET));
724 acpiWriteGenericAddr(&fadt.X_PM1aCTLBLK, 1, 16, 0, 2, acpiPmPort(s, PM1a_CTL_OFFSET));
725 acpiWriteGenericAddr(&fadt.X_PM1bCTLBLK, 0, 0, 0, 0, acpiPmPort(s, PM1b_CTL_OFFSET));
726 acpiWriteGenericAddr(&fadt.X_PM2CTLBLK, 0, 0, 0, 0, acpiPmPort(s, PM2_CTL_OFFSET));
727 acpiWriteGenericAddr(&fadt.X_PMTMRBLK, 1, 32, 0, 3, acpiPmPort(s, PM_TMR_OFFSET));
728 acpiWriteGenericAddr(&fadt.X_GPE0BLK, 1, 16, 0, 1, acpiPmPort(s, GPE0_OFFSET));
729 acpiWriteGenericAddr(&fadt.X_GPE1BLK, 0, 0, 0, 0, acpiPmPort(s, GPE1_OFFSET));
730 fadt.header.u8Checksum = acpiChecksum((uint8_t *)&fadt, sizeof(fadt));
731 acpiPhyscpy(s, addr_acpi2, &fadt, sizeof(fadt));
732
733 /* Now the ACPI 1.0 version. */
734 fadt.header.u32Length = ACPITBLFADT_VERSION1_SIZE;
735 fadt.u8IntModel = INT_MODEL_DUAL_PIC;
736 fadt.header.u8Checksum = 0; /* Must be zeroed before recalculating checksum! */
737 fadt.header.u8Checksum = acpiChecksum((uint8_t *)&fadt, ACPITBLFADT_VERSION1_SIZE);
738 acpiPhyscpy(s, addr_acpi1, &fadt, ACPITBLFADT_VERSION1_SIZE);
739}
740
741/**
742 * Root System Description Table.
743 * The RSDT and XSDT tables are basically identical. The only difference is 32 vs 64 bits
744 * addresses for description headers. RSDT is for ACPI 1.0. XSDT for ACPI 2.0 and up.
745 */
746static int acpiSetupRSDT(ACPIState *s, RTGCPHYS32 addr, unsigned int nb_entries, uint32_t *addrs)
747{
748 ACPITBLRSDT *rsdt;
749 const size_t size = sizeof(ACPITBLHEADER) + nb_entries * sizeof(rsdt->u32Entry[0]);
750
751 rsdt = (ACPITBLRSDT*)RTMemAllocZ(size);
752 if (!rsdt)
753 return PDMDEV_SET_ERROR(s->pDevIns, VERR_NO_TMP_MEMORY, N_("Cannot allocate RSDT"));
754
755 acpiPrepareHeader(&rsdt->header, "RSDT", (uint32_t)size, 1);
756 for (unsigned int i = 0; i < nb_entries; ++i)
757 {
758 rsdt->u32Entry[i] = RT_H2LE_U32(addrs[i]);
759 Log(("Setup RSDT: [%d] = %x\n", i, rsdt->u32Entry[i]));
760 }
761 rsdt->header.u8Checksum = acpiChecksum((uint8_t*)rsdt, size);
762 acpiPhyscpy(s, addr, rsdt, size);
763 RTMemFree(rsdt);
764 return VINF_SUCCESS;
765}
766
767/** Extended System Description Table. */
768static int acpiSetupXSDT(ACPIState *s, RTGCPHYS32 addr, unsigned int nb_entries, uint32_t *addrs)
769{
770 ACPITBLXSDT *xsdt;
771 const size_t size = sizeof(ACPITBLHEADER) + nb_entries * sizeof(xsdt->u64Entry[0]);
772
773 xsdt = (ACPITBLXSDT*)RTMemAllocZ(size);
774 if (!xsdt)
775 return VERR_NO_TMP_MEMORY;
776
777 acpiPrepareHeader(&xsdt->header, "XSDT", (uint32_t)size, 1 /* according to ACPI 3.0 specs */);
778 for (unsigned int i = 0; i < nb_entries; ++i)
779 {
780 xsdt->u64Entry[i] = RT_H2LE_U64((uint64_t)addrs[i]);
781 Log(("Setup XSDT: [%d] = %RX64\n", i, xsdt->u64Entry[i]));
782 }
783 xsdt->header.u8Checksum = acpiChecksum((uint8_t*)xsdt, size);
784 acpiPhyscpy(s, addr, xsdt, size);
785 RTMemFree(xsdt);
786 return VINF_SUCCESS;
787}
788
789/** Root System Description Pointer (RSDP) */
790static void acpiSetupRSDP(ACPITBLRSDP *rsdp, uint32_t rsdt_addr, uint64_t xsdt_addr)
791{
792 memset(rsdp, 0, sizeof(*rsdp));
793
794 /* ACPI 1.0 part (RSDT */
795 memcpy(rsdp->au8Signature, "RSD PTR ", 8);
796 memcpy(rsdp->au8OemId, "VBOX ", 6);
797 rsdp->u8Revision = ACPI_REVISION;
798 rsdp->u32RSDT = RT_H2LE_U32(rsdt_addr);
799 rsdp->u8Checksum = acpiChecksum((uint8_t*)rsdp, RT_OFFSETOF(ACPITBLRSDP, u32Length));
800
801 /* ACPI 2.0 part (XSDT) */
802 rsdp->u32Length = RT_H2LE_U32(sizeof(ACPITBLRSDP));
803 rsdp->u64XSDT = RT_H2LE_U64(xsdt_addr);
804 rsdp->u8ExtChecksum = acpiChecksum((uint8_t*)rsdp, sizeof(ACPITBLRSDP));
805}
806
807/**
808 * Multiple APIC Description Table.
809 *
810 * @note APIC without IO-APIC hangs Windows Vista therefore we setup both
811 *
812 * @todo All hardcoded, should set this up based on the actual VM config!!!!!
813 */
814static void acpiSetupMADT(ACPIState *s, RTGCPHYS32 addr)
815{
816 uint16_t cpus = s->cCpus;
817 AcpiTableMADT madt(cpus);
818
819 acpiPrepareHeader(madt.header_addr(), "APIC", madt.size(), 2);
820
821 *madt.u32LAPIC_addr() = RT_H2LE_U32(0xfee00000);
822 *madt.u32Flags_addr() = RT_H2LE_U32(PCAT_COMPAT);
823
824 ACPITBLLAPIC* lapic = madt.LApics_addr();
825 for (uint16_t i = 0; i < cpus; i++)
826 {
827 lapic->u8Type = 0;
828 lapic->u8Length = sizeof(ACPITBLLAPIC);
829 lapic->u8ProcId = i;
830 lapic->u8ApicId = i;
831 lapic->u32Flags = RT_H2LE_U32(LAPIC_ENABLED);
832 lapic++;
833 }
834
835 ACPITBLIOAPIC* ioapic = madt.IOApic_addr();
836
837 ioapic->u8Type = 1;
838 ioapic->u8Length = sizeof(ACPITBLIOAPIC);
839 /** @todo is this the right id? */
840 ioapic->u8IOApicId = cpus;
841 ioapic->u8Reserved = 0;
842 ioapic->u32Address = RT_H2LE_U32(0xfec00000);
843 ioapic->u32GSIB = RT_H2LE_U32(0);
844
845 madt.header_addr()->u8Checksum = acpiChecksum(madt.data(), madt.size());
846 acpiPhyscpy(s, addr, madt.data(), madt.size());
847}
848
849/* SCI IRQ */
850DECLINLINE(void) acpiSetIrq(ACPIState *s, int level)
851{
852 if (s->pm1a_ctl & SCI_EN)
853 PDMDevHlpPCISetIrq(s->pDevIns, -1, level);
854}
855
856DECLINLINE(uint32_t) pm1a_pure_en(uint32_t en)
857{
858 return en & ~(RSR_EN | IGN_EN);
859}
860
861DECLINLINE(uint32_t) pm1a_pure_sts(uint32_t sts)
862{
863 return sts & ~(RSR_STS | IGN_STS);
864}
865
866DECLINLINE(int) pm1a_level(ACPIState *s)
867{
868 return (pm1a_pure_en(s->pm1a_en) & pm1a_pure_sts(s->pm1a_sts)) != 0;
869}
870
871DECLINLINE(int) gpe0_level(ACPIState *s)
872{
873 return (s->gpe0_en & s->gpe0_sts) != 0;
874}
875
876static void update_pm1a(ACPIState *s, uint32_t sts, uint32_t en)
877{
878 int old_level, new_level;
879
880 if (gpe0_level(s))
881 return;
882
883 old_level = pm1a_level(s);
884 new_level = (pm1a_pure_en(en) & pm1a_pure_sts(sts)) != 0;
885
886 s->pm1a_en = en;
887 s->pm1a_sts = sts;
888
889 if (new_level != old_level)
890 acpiSetIrq(s, new_level);
891}
892
893static void update_gpe0(ACPIState *s, uint32_t sts, uint32_t en)
894{
895 int old_level, new_level;
896
897 if (pm1a_level(s))
898 return;
899
900 old_level = (s->gpe0_en & s->gpe0_sts) != 0;
901 new_level = (en & sts) != 0;
902
903 s->gpe0_en = en;
904 s->gpe0_sts = sts;
905
906 if (new_level != old_level)
907 acpiSetIrq(s, new_level);
908}
909
910static int acpiPowerDown(ACPIState *s)
911{
912 int rc = PDMDevHlpVMPowerOff(s->pDevIns);
913 if (RT_FAILURE(rc))
914 AssertMsgFailed(("Could not power down the VM. rc = %Rrc\n", rc));
915 return rc;
916}
917
918/** Converts a ACPI port interface pointer to an ACPI state pointer. */
919#define IACPIPORT_2_ACPISTATE(pInterface) ( (ACPIState*)((uintptr_t)pInterface - RT_OFFSETOF(ACPIState, IACPIPort)) )
920
921/**
922 * Send an ACPI power off event.
923 *
924 * @returns VBox status code
925 * @param pInterface Pointer to the interface structure containing the called function pointer.
926 */
927static DECLCALLBACK(int) acpiPowerButtonPress(PPDMIACPIPORT pInterface)
928{
929 ACPIState *s = IACPIPORT_2_ACPISTATE(pInterface);
930 s->fPowerButtonHandled = false;
931 update_pm1a(s, s->pm1a_sts | PWRBTN_STS, s->pm1a_en);
932 return VINF_SUCCESS;
933}
934
935/**
936 * Check if the ACPI power button event was handled.
937 *
938 * @returns VBox status code
939 * @param pInterface Pointer to the interface structure containing the called function pointer.
940 * @param pfHandled Return true if the power button event was handled by the guest.
941 */
942static DECLCALLBACK(int) acpiGetPowerButtonHandled(PPDMIACPIPORT pInterface, bool *pfHandled)
943{
944 ACPIState *s = IACPIPORT_2_ACPISTATE(pInterface);
945 *pfHandled = s->fPowerButtonHandled;
946 return VINF_SUCCESS;
947}
948
949/**
950 * Check if the Guest entered into G0 (working) or G1 (sleeping).
951 *
952 * @returns VBox status code
953 * @param pInterface Pointer to the interface structure containing the called function pointer.
954 * @param pfEntered Return true if the guest entered the ACPI mode.
955 */
956static DECLCALLBACK(int) acpiGetGuestEnteredACPIMode(PPDMIACPIPORT pInterface, bool *pfEntered)
957{
958 ACPIState *s = IACPIPORT_2_ACPISTATE(pInterface);
959 *pfEntered = (s->pm1a_ctl & SCI_EN) != 0;
960 return VINF_SUCCESS;
961}
962
963/**
964 * Send an ACPI sleep button event.
965 *
966 * @returns VBox status code
967 * @param pInterface Pointer to the interface structure containing the called function pointer.
968 */
969static DECLCALLBACK(int) acpiSleepButtonPress(PPDMIACPIPORT pInterface)
970{
971 ACPIState *s = IACPIPORT_2_ACPISTATE(pInterface);
972 update_pm1a(s, s->pm1a_sts | SLPBTN_STS, s->pm1a_en);
973 return VINF_SUCCESS;
974}
975
976/* PM1a_EVT_BLK enable */
977static uint32_t acpiPm1aEnReadw(ACPIState *s, uint32_t addr)
978{
979 uint16_t val = s->pm1a_en;
980 Log(("acpi: acpiPm1aEnReadw -> %#x\n", val));
981 return val;
982}
983
984static void acpiPM1aEnWritew(ACPIState *s, uint32_t addr, uint32_t val)
985{
986 Log(("acpi: acpiPM1aEnWritew <- %#x (%#x)\n", val, val & ~(RSR_EN | IGN_EN)));
987 val &= ~(RSR_EN | IGN_EN);
988 update_pm1a(s, s->pm1a_sts, val);
989}
990
991/* PM1a_EVT_BLK status */
992static uint32_t acpiPm1aStsReadw(ACPIState *s, uint32_t addr)
993{
994 uint16_t val = s->pm1a_sts;
995 Log(("acpi: acpiPm1aStsReadw -> %#x\n", val));
996 return val;
997}
998
999static void acpiPM1aStsWritew(ACPIState *s, uint32_t addr, uint32_t val)
1000{
1001 Log(("acpi: acpiPM1aStsWritew <- %#x (%#x)\n", val, val & ~(RSR_STS | IGN_STS)));
1002 if (val & PWRBTN_STS)
1003 s->fPowerButtonHandled = true; /* Remember that the guest handled the last power button event */
1004 val = s->pm1a_sts & ~(val & ~(RSR_STS | IGN_STS));
1005 update_pm1a(s, val, s->pm1a_en);
1006}
1007
1008/* PM1a_CTL_BLK */
1009static uint32_t acpiPm1aCtlReadw(ACPIState *s, uint32_t addr)
1010{
1011 uint16_t val = s->pm1a_ctl;
1012 Log(("acpi: acpiPm1aCtlReadw -> %#x\n", val));
1013 return val;
1014}
1015
1016static int acpiPM1aCtlWritew(ACPIState *s, uint32_t addr, uint32_t val)
1017{
1018 uint32_t uSleepState;
1019
1020 Log(("acpi: acpiPM1aCtlWritew <- %#x (%#x)\n", val, val & ~(RSR_CNT | IGN_CNT)));
1021 s->pm1a_ctl = val & ~(RSR_CNT | IGN_CNT);
1022
1023 uSleepState = (s->pm1a_ctl >> SLP_TYPx_SHIFT) & SLP_TYPx_MASK;
1024 if (uSleepState != s->uSleepState)
1025 {
1026 s->uSleepState = uSleepState;
1027 switch (uSleepState)
1028 {
1029 case 0x00: /* S0 */
1030 break;
1031 case 0x05: /* S5 */
1032 LogRel(("Entering S5 (power down)\n"));
1033 return acpiPowerDown(s);
1034 default:
1035 AssertMsgFailed(("Unknown sleep state %#x\n", uSleepState));
1036 break;
1037 }
1038 }
1039 return VINF_SUCCESS;
1040}
1041
1042/* GPE0_BLK */
1043static uint32_t acpiGpe0EnReadb(ACPIState *s, uint32_t addr)
1044{
1045 uint8_t val = s->gpe0_en;
1046 Log(("acpi: acpiGpe0EnReadl -> %#x\n", val));
1047 return val;
1048}
1049
1050static void acpiGpe0EnWriteb(ACPIState *s, uint32_t addr, uint32_t val)
1051{
1052 Log(("acpi: acpiGpe0EnWritel <- %#x\n", val));
1053 update_gpe0(s, s->gpe0_sts, val);
1054}
1055
1056static uint32_t acpiGpe0StsReadb(ACPIState *s, uint32_t addr)
1057{
1058 uint8_t val = s->gpe0_sts;
1059 Log(("acpi: acpiGpe0StsReadl -> %#x\n", val));
1060 return val;
1061}
1062
1063static void acpiGpe0StsWriteb(ACPIState *s, uint32_t addr, uint32_t val)
1064{
1065 val = s->gpe0_sts & ~val;
1066 update_gpe0(s, val, s->gpe0_en);
1067 Log(("acpi: acpiGpe0StsWritel <- %#x\n", val));
1068}
1069
1070static int acpiResetWriteU8(ACPIState *s, uint32_t addr, uint32_t val)
1071{
1072 int rc = VINF_SUCCESS;
1073
1074 Log(("ACPI: acpiResetWriteU8: %x %x\n", addr, val));
1075 if (val == ACPI_RESET_REG_VAL)
1076 {
1077# ifndef IN_RING3
1078 rc = VINF_IOM_HC_IOPORT_WRITE;
1079# else /* IN_RING3 */
1080 rc = PDMDevHlpVMReset(s->pDevIns);
1081# endif /* !IN_RING3 */
1082 }
1083 return rc;
1084}
1085
1086/* SMI */
1087static void acpiSmiWriteU8(ACPIState *s, uint32_t addr, uint32_t val)
1088{
1089 Log(("acpi: acpiSmiWriteU8 %#x\n", val));
1090 if (val == ACPI_ENABLE)
1091 s->pm1a_ctl |= SCI_EN;
1092 else if (val == ACPI_DISABLE)
1093 s->pm1a_ctl &= ~SCI_EN;
1094 else
1095 Log(("acpi: acpiSmiWriteU8 %#x <- unknown value\n", val));
1096}
1097
1098static uint32_t find_rsdp_space(void)
1099{
1100 return 0xe0000;
1101}
1102
1103static int acpiPMTimerReset(ACPIState *s)
1104{
1105 uint64_t interval, freq;
1106
1107 freq = TMTimerGetFreq(s->CTX_SUFF(ts));
1108 interval = ASMMultU64ByU32DivByU32(0xffffffff, freq, PM_TMR_FREQ);
1109 Log(("interval = %RU64\n", interval));
1110 TMTimerSet(s->CTX_SUFF(ts), TMTimerGet(s->CTX_SUFF(ts)) + interval);
1111
1112 return VINF_SUCCESS;
1113}
1114
1115static DECLCALLBACK(void) acpiTimer(PPDMDEVINS pDevIns, PTMTIMER pTimer, void *pvUser)
1116{
1117 ACPIState *s = (ACPIState *)pvUser;
1118
1119 Log(("acpi: pm timer sts %#x (%d), en %#x (%d)\n",
1120 s->pm1a_sts, (s->pm1a_sts & TMR_STS) != 0,
1121 s->pm1a_en, (s->pm1a_en & TMR_EN) != 0));
1122
1123 update_pm1a(s, s->pm1a_sts | TMR_STS, s->pm1a_en);
1124 acpiPMTimerReset(s);
1125}
1126
1127/**
1128 * _BST method.
1129 */
1130static int acpiFetchBatteryStatus(ACPIState *s)
1131{
1132 uint32_t *p = s->au8BatteryInfo;
1133 bool fPresent; /* battery present? */
1134 PDMACPIBATCAPACITY hostRemainingCapacity; /* 0..100 */
1135 PDMACPIBATSTATE hostBatteryState; /* bitfield */
1136 uint32_t hostPresentRate; /* 0..1000 */
1137 int rc;
1138
1139 if (!s->pDrv)
1140 return VINF_SUCCESS;
1141 rc = s->pDrv->pfnQueryBatteryStatus(s->pDrv, &fPresent, &hostRemainingCapacity,
1142 &hostBatteryState, &hostPresentRate);
1143 AssertRC(rc);
1144
1145 /* default values */
1146 p[BAT_STATUS_STATE] = hostBatteryState;
1147 p[BAT_STATUS_PRESENT_RATE] = hostPresentRate == ~0U ? 0xFFFFFFFF
1148 : hostPresentRate * 50; /* mW */
1149 p[BAT_STATUS_REMAINING_CAPACITY] = 50000; /* mWh */
1150 p[BAT_STATUS_PRESENT_VOLTAGE] = 10000; /* mV */
1151
1152 /* did we get a valid battery state? */
1153 if (hostRemainingCapacity != PDM_ACPI_BAT_CAPACITY_UNKNOWN)
1154 p[BAT_STATUS_REMAINING_CAPACITY] = hostRemainingCapacity * 500; /* mWh */
1155 if (hostBatteryState == PDM_ACPI_BAT_STATE_CHARGED)
1156 p[BAT_STATUS_PRESENT_RATE] = 0; /* mV */
1157
1158 return VINF_SUCCESS;
1159}
1160
1161/**
1162 * _BIF method.
1163 */
1164static int acpiFetchBatteryInfo(ACPIState *s)
1165{
1166 uint32_t *p = s->au8BatteryInfo;
1167
1168 p[BAT_INFO_UNITS] = 0; /* mWh */
1169 p[BAT_INFO_DESIGN_CAPACITY] = 50000; /* mWh */
1170 p[BAT_INFO_LAST_FULL_CHARGE_CAPACITY] = 50000; /* mWh */
1171 p[BAT_INFO_TECHNOLOGY] = BAT_TECH_PRIMARY;
1172 p[BAT_INFO_DESIGN_VOLTAGE] = 10000; /* mV */
1173 p[BAT_INFO_DESIGN_CAPACITY_OF_WARNING] = 100; /* mWh */
1174 p[BAT_INFO_DESIGN_CAPACITY_OF_LOW] = 50; /* mWh */
1175 p[BAT_INFO_CAPACITY_GRANULARITY_1] = 1; /* mWh */
1176 p[BAT_INFO_CAPACITY_GRANULARITY_2] = 1; /* mWh */
1177
1178 return VINF_SUCCESS;
1179}
1180
1181/**
1182 * _STA method.
1183 */
1184static uint32_t acpiGetBatteryDeviceStatus(ACPIState *s)
1185{
1186 bool fPresent; /* battery present? */
1187 PDMACPIBATCAPACITY hostRemainingCapacity; /* 0..100 */
1188 PDMACPIBATSTATE hostBatteryState; /* bitfield */
1189 uint32_t hostPresentRate; /* 0..1000 */
1190 int rc;
1191
1192 if (!s->pDrv)
1193 return 0;
1194 rc = s->pDrv->pfnQueryBatteryStatus(s->pDrv, &fPresent, &hostRemainingCapacity,
1195 &hostBatteryState, &hostPresentRate);
1196 AssertRC(rc);
1197
1198 return fPresent
1199 ? STA_DEVICE_PRESENT_MASK /* present */
1200 | STA_DEVICE_ENABLED_MASK /* enabled and decodes its resources */
1201 | STA_DEVICE_SHOW_IN_UI_MASK /* should be shown in UI */
1202 | STA_DEVICE_FUNCTIONING_PROPERLY_MASK /* functioning properly */
1203 | STA_BATTERY_PRESENT_MASK /* battery is present */
1204 : 0; /* device not present */
1205}
1206
1207static uint32_t acpiGetPowerSource(ACPIState *s)
1208{
1209 PDMACPIPOWERSOURCE ps;
1210
1211 /* query the current power source from the host driver */
1212 if (!s->pDrv)
1213 return AC_ONLINE;
1214 int rc = s->pDrv->pfnQueryPowerSource(s->pDrv, &ps);
1215 AssertRC(rc);
1216 return ps == PDM_ACPI_POWER_SOURCE_BATTERY ? AC_OFFLINE : AC_ONLINE;
1217}
1218
1219PDMBOTHCBDECL(int) acpiBatIndexWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb)
1220{
1221 ACPIState *s = (ACPIState *)pvUser;
1222
1223 switch (cb)
1224 {
1225 case 4:
1226 u32 >>= s->u8IndexShift;
1227 /* see comment at the declaration of u8IndexShift */
1228 if (s->u8IndexShift == 0 && u32 == (BAT_DEVICE_STATUS << 2))
1229 {
1230 s->u8IndexShift = 2;
1231 u32 >>= 2;
1232 }
1233 Assert(u32 < BAT_INDEX_LAST);
1234 s->uBatteryIndex = u32;
1235 break;
1236 default:
1237 AssertMsgFailed(("Port=%#x cb=%d u32=%#x\n", Port, cb, u32));
1238 break;
1239 }
1240 return VINF_SUCCESS;
1241}
1242
1243PDMBOTHCBDECL(int) acpiBatDataRead(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t *pu32, unsigned cb)
1244{
1245 ACPIState *s = (ACPIState *)pvUser;
1246
1247 switch (cb)
1248 {
1249 case 4:
1250 switch (s->uBatteryIndex)
1251 {
1252 case BAT_STATUS_STATE:
1253 acpiFetchBatteryStatus(s);
1254 case BAT_STATUS_PRESENT_RATE:
1255 case BAT_STATUS_REMAINING_CAPACITY:
1256 case BAT_STATUS_PRESENT_VOLTAGE:
1257 *pu32 = s->au8BatteryInfo[s->uBatteryIndex];
1258 break;
1259
1260 case BAT_INFO_UNITS:
1261 acpiFetchBatteryInfo(s);
1262 case BAT_INFO_DESIGN_CAPACITY:
1263 case BAT_INFO_LAST_FULL_CHARGE_CAPACITY:
1264 case BAT_INFO_TECHNOLOGY:
1265 case BAT_INFO_DESIGN_VOLTAGE:
1266 case BAT_INFO_DESIGN_CAPACITY_OF_WARNING:
1267 case BAT_INFO_DESIGN_CAPACITY_OF_LOW:
1268 case BAT_INFO_CAPACITY_GRANULARITY_1:
1269 case BAT_INFO_CAPACITY_GRANULARITY_2:
1270 *pu32 = s->au8BatteryInfo[s->uBatteryIndex];
1271 break;
1272
1273 case BAT_DEVICE_STATUS:
1274 *pu32 = acpiGetBatteryDeviceStatus(s);
1275 break;
1276
1277 case BAT_POWER_SOURCE:
1278 *pu32 = acpiGetPowerSource(s);
1279 break;
1280
1281 default:
1282 AssertMsgFailed(("Invalid battery index %d\n", s->uBatteryIndex));
1283 break;
1284 }
1285 break;
1286 default:
1287 return VERR_IOM_IOPORT_UNUSED;
1288 }
1289 return VINF_SUCCESS;
1290}
1291
1292PDMBOTHCBDECL(int) acpiSysInfoIndexWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb)
1293{
1294 ACPIState *s = (ACPIState *)pvUser;
1295
1296 Log(("system_index = %d, %d\n", u32, u32 >> 2));
1297 switch (cb)
1298 {
1299 case 4:
1300 if (u32 == SYSTEM_INFO_INDEX_VALID || u32 == SYSTEM_INFO_INDEX_INVALID)
1301 s->uSystemInfoIndex = u32;
1302 else
1303 {
1304 /* see comment at the declaration of u8IndexShift */
1305 if (s->u8IndexShift == 0)
1306 {
1307 if (((u32 >> 2) < SYSTEM_INFO_INDEX_END) && ((u32 & 0x3)) == 0)
1308 {
1309 s->u8IndexShift = 2;
1310 }
1311 }
1312
1313 u32 >>= s->u8IndexShift;
1314 Assert(u32 < SYSTEM_INFO_INDEX_END);
1315 s->uSystemInfoIndex = u32;
1316 }
1317 break;
1318
1319 default:
1320 AssertMsgFailed(("Port=%#x cb=%d u32=%#x\n", Port, cb, u32));
1321 break;
1322 }
1323 return VINF_SUCCESS;
1324}
1325
1326PDMBOTHCBDECL(int) acpiSysInfoDataRead(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t *pu32, unsigned cb)
1327{
1328 ACPIState *s = (ACPIState *)pvUser;
1329
1330 switch (cb)
1331 {
1332 case 4:
1333 switch (s->uSystemInfoIndex)
1334 {
1335 case SYSTEM_INFO_INDEX_LOW_MEMORY_LENGTH:
1336 *pu32 = s->cbRamLow;
1337 break;
1338
1339 case SYSTEM_INFO_INDEX_HIGH_MEMORY_LENGTH:
1340 *pu32 = s->cbRamHigh >> 16; /* 64KB units */
1341 Assert(((uint64_t)*pu32 << 16) == s->cbRamHigh);
1342 break;
1343
1344 case SYSTEM_INFO_INDEX_USE_IOAPIC:
1345 *pu32 = s->u8UseIOApic;
1346 break;
1347
1348 case SYSTEM_INFO_INDEX_HPET_STATUS:
1349 *pu32 = s->fUseHpet ? ( STA_DEVICE_PRESENT_MASK
1350 | STA_DEVICE_ENABLED_MASK
1351 | STA_DEVICE_SHOW_IN_UI_MASK
1352 | STA_DEVICE_FUNCTIONING_PROPERLY_MASK)
1353 : 0;
1354 break;
1355
1356 case SYSTEM_INFO_INDEX_SMC_STATUS:
1357 *pu32 = s->fUseSmc ? ( STA_DEVICE_PRESENT_MASK
1358 | STA_DEVICE_ENABLED_MASK
1359 /* no need to show this device in the UI */
1360 | STA_DEVICE_FUNCTIONING_PROPERLY_MASK)
1361 : 0;
1362 break;
1363
1364 case SYSTEM_INFO_INDEX_FDC_STATUS:
1365 *pu32 = s->fUseFdc ? ( STA_DEVICE_PRESENT_MASK
1366 | STA_DEVICE_ENABLED_MASK
1367 | STA_DEVICE_SHOW_IN_UI_MASK
1368 | STA_DEVICE_FUNCTIONING_PROPERLY_MASK)
1369 : 0;
1370 break;
1371
1372
1373 case SYSTEM_INFO_INDEX_CPU0_STATUS:
1374 case SYSTEM_INFO_INDEX_CPU1_STATUS:
1375 case SYSTEM_INFO_INDEX_CPU2_STATUS:
1376 case SYSTEM_INFO_INDEX_CPU3_STATUS:
1377 *pu32 = s->fShowCpu
1378 && s->uSystemInfoIndex - SYSTEM_INFO_INDEX_CPU0_STATUS < s->cCpus
1379 ?
1380 STA_DEVICE_PRESENT_MASK
1381 | STA_DEVICE_ENABLED_MASK
1382 | STA_DEVICE_SHOW_IN_UI_MASK
1383 | STA_DEVICE_FUNCTIONING_PROPERLY_MASK
1384 : 0;
1385
1386 case SYSTEM_INFO_INDEX_RTC_STATUS:
1387 *pu32 = s->fShowRtc ? ( STA_DEVICE_PRESENT_MASK
1388 | STA_DEVICE_ENABLED_MASK
1389 | STA_DEVICE_SHOW_IN_UI_MASK
1390 | STA_DEVICE_FUNCTIONING_PROPERLY_MASK)
1391 : 0;
1392 break;
1393
1394 /* Solaris 9 tries to read from this index */
1395 case SYSTEM_INFO_INDEX_INVALID:
1396 *pu32 = 0;
1397 break;
1398
1399 default:
1400 AssertMsgFailed(("Invalid system info index %d\n", s->uSystemInfoIndex));
1401 break;
1402 }
1403 break;
1404
1405 default:
1406 return VERR_IOM_IOPORT_UNUSED;
1407 }
1408
1409 Log(("index %d val %d\n", s->uSystemInfoIndex, *pu32));
1410 return VINF_SUCCESS;
1411}
1412
1413PDMBOTHCBDECL(int) acpiSysInfoDataWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb)
1414{
1415 ACPIState *s = (ACPIState *)pvUser;
1416
1417 Log(("addr=%#x cb=%d u32=%#x si=%#x\n", Port, cb, u32, s->uSystemInfoIndex));
1418
1419 if (cb == 4 && u32 == 0xbadc0de)
1420 {
1421 switch (s->uSystemInfoIndex)
1422 {
1423 case SYSTEM_INFO_INDEX_INVALID:
1424 s->u8IndexShift = 0;
1425 break;
1426
1427 case SYSTEM_INFO_INDEX_VALID:
1428 s->u8IndexShift = 2;
1429 break;
1430
1431 default:
1432 AssertMsgFailed(("Port=%#x cb=%d u32=%#x system_index=%#x\n",
1433 Port, cb, u32, s->uSystemInfoIndex));
1434 break;
1435 }
1436 }
1437 else
1438 AssertMsgFailed(("Port=%#x cb=%d u32=%#x\n", Port, cb, u32));
1439 return VINF_SUCCESS;
1440}
1441
1442/** @todo Don't call functions, but do the job in the read/write handlers
1443 * here! */
1444
1445/* IO Helpers */
1446PDMBOTHCBDECL(int) acpiPm1aEnRead(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t *pu32, unsigned cb)
1447{
1448 switch (cb)
1449 {
1450 case 2:
1451 *pu32 = acpiPm1aEnReadw((ACPIState*)pvUser, Port);
1452 break;
1453 default:
1454 return VERR_IOM_IOPORT_UNUSED;
1455 }
1456 return VINF_SUCCESS;
1457}
1458
1459PDMBOTHCBDECL(int) acpiPm1aStsRead(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t *pu32, unsigned cb)
1460{
1461 switch (cb)
1462 {
1463 case 2:
1464 *pu32 = acpiPm1aStsReadw((ACPIState*)pvUser, Port);
1465 break;
1466 default:
1467 return VERR_IOM_IOPORT_UNUSED;
1468 }
1469 return VINF_SUCCESS;
1470}
1471
1472PDMBOTHCBDECL(int) acpiPm1aCtlRead(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t *pu32, unsigned cb)
1473{
1474 switch (cb)
1475 {
1476 case 2:
1477 *pu32 = acpiPm1aCtlReadw((ACPIState*)pvUser, Port);
1478 break;
1479 default:
1480 return VERR_IOM_IOPORT_UNUSED;
1481 }
1482 return VINF_SUCCESS;
1483}
1484
1485PDMBOTHCBDECL(int) acpiPM1aEnWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb)
1486{
1487 switch (cb)
1488 {
1489 case 2:
1490 acpiPM1aEnWritew((ACPIState*)pvUser, Port, u32);
1491 break;
1492 default:
1493 AssertMsgFailed(("Port=%#x cb=%d u32=%#x\n", Port, cb, u32));
1494 break;
1495 }
1496 return VINF_SUCCESS;
1497}
1498
1499PDMBOTHCBDECL(int) acpiPM1aStsWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb)
1500{
1501 switch (cb)
1502 {
1503 case 2:
1504 acpiPM1aStsWritew((ACPIState*)pvUser, Port, u32);
1505 break;
1506 default:
1507 AssertMsgFailed(("Port=%#x cb=%d u32=%#x\n", Port, cb, u32));
1508 break;
1509 }
1510 return VINF_SUCCESS;
1511}
1512
1513PDMBOTHCBDECL(int) acpiPM1aCtlWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb)
1514{
1515 switch (cb)
1516 {
1517 case 2:
1518 return acpiPM1aCtlWritew((ACPIState*)pvUser, Port, u32);
1519 default:
1520 AssertMsgFailed(("Port=%#x cb=%d u32=%#x\n", Port, cb, u32));
1521 break;
1522 }
1523 return VINF_SUCCESS;
1524}
1525
1526#endif /* IN_RING3 */
1527
1528/**
1529 * PMTMR readable from host/guest.
1530 */
1531PDMBOTHCBDECL(int) acpiPMTmrRead(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t *pu32, unsigned cb)
1532{
1533 if (cb == 4)
1534 {
1535 ACPIState *s = PDMINS_2_DATA(pDevIns, ACPIState *);
1536 int64_t now = TMTimerGet(s->CTX_SUFF(ts));
1537 int64_t elapsed = now - s->pm_timer_initial;
1538
1539 *pu32 = ASMMultU64ByU32DivByU32(elapsed, PM_TMR_FREQ, TMTimerGetFreq(s->CTX_SUFF(ts)));
1540 Log(("acpi: acpiPMTmrRead -> %#x\n", *pu32));
1541 return VINF_SUCCESS;
1542 }
1543 return VERR_IOM_IOPORT_UNUSED;
1544}
1545
1546#ifdef IN_RING3
1547
1548PDMBOTHCBDECL(int) acpiGpe0StsRead(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t *pu32, unsigned cb)
1549{
1550 switch (cb)
1551 {
1552 case 1:
1553 *pu32 = acpiGpe0StsReadb((ACPIState*)pvUser, Port);
1554 break;
1555 default:
1556 return VERR_IOM_IOPORT_UNUSED;
1557 }
1558 return VINF_SUCCESS;
1559}
1560
1561PDMBOTHCBDECL(int) acpiGpe0EnRead(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t *pu32, unsigned cb)
1562{
1563 switch (cb)
1564 {
1565 case 1:
1566 *pu32 = acpiGpe0EnReadb((ACPIState*)pvUser, Port);
1567 break;
1568 default:
1569 return VERR_IOM_IOPORT_UNUSED;
1570 }
1571 return VINF_SUCCESS;
1572}
1573
1574PDMBOTHCBDECL(int) acpiGpe0StsWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb)
1575{
1576 switch (cb)
1577 {
1578 case 1:
1579 acpiGpe0StsWriteb((ACPIState*)pvUser, Port, u32);
1580 break;
1581 default:
1582 AssertMsgFailed(("Port=%#x cb=%d u32=%#x\n", Port, cb, u32));
1583 break;
1584 }
1585 return VINF_SUCCESS;
1586}
1587
1588PDMBOTHCBDECL(int) acpiGpe0EnWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb)
1589{
1590 switch (cb)
1591 {
1592 case 1:
1593 acpiGpe0EnWriteb((ACPIState*)pvUser, Port, u32);
1594 break;
1595 default:
1596 AssertMsgFailed(("Port=%#x cb=%d u32=%#x\n", Port, cb, u32));
1597 break;
1598 }
1599 return VINF_SUCCESS;
1600}
1601
1602PDMBOTHCBDECL(int) acpiSmiWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb)
1603{
1604 switch (cb)
1605 {
1606 case 1:
1607 acpiSmiWriteU8((ACPIState*)pvUser, Port, u32);
1608 break;
1609 default:
1610 AssertMsgFailed(("Port=%#x cb=%d u32=%#x\n", Port, cb, u32));
1611 break;
1612 }
1613 return VINF_SUCCESS;
1614}
1615
1616PDMBOTHCBDECL(int) acpiResetWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb)
1617{
1618 switch (cb)
1619 {
1620 case 1:
1621 return acpiResetWriteU8((ACPIState*)pvUser, Port, u32);
1622 default:
1623 AssertMsgFailed(("Port=%#x cb=%d u32=%#x\n", Port, cb, u32));
1624 break;
1625 }
1626 return VINF_SUCCESS;
1627}
1628
1629#ifdef DEBUG_ACPI
1630
1631PDMBOTHCBDECL(int) acpiDhexWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb)
1632{
1633 switch (cb)
1634 {
1635 case 1:
1636 Log(("%#x\n", u32 & 0xff));
1637 break;
1638 case 2:
1639 Log(("%#6x\n", u32 & 0xffff));
1640 case 4:
1641 Log(("%#10x\n", u32));
1642 break;
1643 default:
1644 AssertMsgFailed(("Port=%#x cb=%d u32=%#x\n", Port, cb, u32));
1645 break;
1646 }
1647 return VINF_SUCCESS;
1648}
1649
1650PDMBOTHCBDECL(int) acpiDchrWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb)
1651{
1652 switch (cb)
1653 {
1654 case 1:
1655 Log(("%c", u32 & 0xff));
1656 break;
1657 default:
1658 AssertMsgFailed(("Port=%#x cb=%d u32=%#x\n", Port, cb, u32));
1659 break;
1660 }
1661 return VINF_SUCCESS;
1662}
1663
1664#endif /* DEBUG_ACPI */
1665
1666static int acpiRegisterPmHandlers(ACPIState* pThis)
1667{
1668 int rc = VINF_SUCCESS;
1669
1670#define R(offset, cnt, writer, reader, description) \
1671 do { \
1672 rc = PDMDevHlpIOPortRegister(pThis->pDevIns, acpiPmPort(pThis, offset), cnt, pThis, writer, reader, \
1673 NULL, NULL, description); \
1674 if (RT_FAILURE(rc)) \
1675 return rc; \
1676 } while (0)
1677#define L (GPE0_BLK_LEN / 2)
1678
1679 R(PM1a_EVT_OFFSET+2, 1, acpiPM1aEnWrite, acpiPm1aEnRead, "ACPI PM1a Enable");
1680 R(PM1a_EVT_OFFSET, 1, acpiPM1aStsWrite, acpiPm1aStsRead, "ACPI PM1a Status");
1681 R(PM1a_CTL_OFFSET, 1, acpiPM1aCtlWrite, acpiPm1aCtlRead, "ACPI PM1a Control");
1682 R(PM_TMR_OFFSET, 1, NULL, acpiPMTmrRead, "ACPI PM Timer");
1683 R(GPE0_OFFSET + L, L, acpiGpe0EnWrite, acpiGpe0EnRead, "ACPI GPE0 Enable");
1684 R(GPE0_OFFSET, L, acpiGpe0StsWrite, acpiGpe0StsRead, "ACPI GPE0 Status");
1685#undef L
1686#undef R
1687
1688 /* register GC stuff */
1689 if (pThis->fGCEnabled)
1690 {
1691 rc = PDMDevHlpIOPortRegisterGC(pThis->pDevIns, acpiPmPort(pThis, PM_TMR_OFFSET),
1692 1, 0, NULL, "acpiPMTmrRead",
1693 NULL, NULL, "ACPI PM Timer");
1694 AssertRCReturn(rc, rc);
1695 }
1696
1697 /* register R0 stuff */
1698 if (pThis->fR0Enabled)
1699 {
1700 rc = PDMDevHlpIOPortRegisterR0(pThis->pDevIns, acpiPmPort(pThis, PM_TMR_OFFSET),
1701 1, 0, NULL, "acpiPMTmrRead",
1702 NULL, NULL, "ACPI PM Timer");
1703 AssertRCReturn(rc, rc);
1704 }
1705
1706 return rc;
1707}
1708
1709static int acpiUnregisterPmHandlers(ACPIState *pThis)
1710{
1711#define U(offset, cnt) \
1712 do { \
1713 int rc = PDMDevHlpIOPortDeregister(pThis->pDevIns, acpiPmPort(pThis, offset), cnt); \
1714 AssertRCReturn(rc, rc); \
1715 } while (0)
1716#define L (GPE0_BLK_LEN / 2)
1717
1718 U(PM1a_EVT_OFFSET+2, 1);
1719 U(PM1a_EVT_OFFSET, 1);
1720 U(PM1a_CTL_OFFSET, 1);
1721 U(PM_TMR_OFFSET, 1);
1722 U(GPE0_OFFSET + L, L);
1723 U(GPE0_OFFSET, L);
1724#undef L
1725#undef U
1726
1727 return VINF_SUCCESS;
1728}
1729
1730/**
1731 * Saved state structure description, version 4.
1732 */
1733static const SSMFIELD g_AcpiSavedStateFields4[] =
1734{
1735 SSMFIELD_ENTRY(ACPIState, pm1a_en),
1736 SSMFIELD_ENTRY(ACPIState, pm1a_sts),
1737 SSMFIELD_ENTRY(ACPIState, pm1a_ctl),
1738 SSMFIELD_ENTRY(ACPIState, pm_timer_initial),
1739 SSMFIELD_ENTRY(ACPIState, gpe0_en),
1740 SSMFIELD_ENTRY(ACPIState, gpe0_sts),
1741 SSMFIELD_ENTRY(ACPIState, uBatteryIndex),
1742 SSMFIELD_ENTRY(ACPIState, uSystemInfoIndex),
1743 SSMFIELD_ENTRY(ACPIState, u64RamSize),
1744 SSMFIELD_ENTRY(ACPIState, u8IndexShift),
1745 SSMFIELD_ENTRY(ACPIState, u8UseIOApic),
1746 SSMFIELD_ENTRY(ACPIState, uSleepState),
1747 SSMFIELD_ENTRY_TERM()
1748};
1749
1750/**
1751 * Saved state structure description, version 5.
1752 */
1753static const SSMFIELD g_AcpiSavedStateFields5[] =
1754{
1755 SSMFIELD_ENTRY(ACPIState, pm1a_en),
1756 SSMFIELD_ENTRY(ACPIState, pm1a_sts),
1757 SSMFIELD_ENTRY(ACPIState, pm1a_ctl),
1758 SSMFIELD_ENTRY(ACPIState, pm_timer_initial),
1759 SSMFIELD_ENTRY(ACPIState, gpe0_en),
1760 SSMFIELD_ENTRY(ACPIState, gpe0_sts),
1761 SSMFIELD_ENTRY(ACPIState, uBatteryIndex),
1762 SSMFIELD_ENTRY(ACPIState, uSystemInfoIndex),
1763 SSMFIELD_ENTRY(ACPIState, uSleepState),
1764 SSMFIELD_ENTRY(ACPIState, u8IndexShift),
1765 SSMFIELD_ENTRY(ACPIState, uPmIoPortBase),
1766 SSMFIELD_ENTRY_TERM()
1767};
1768
1769
1770static DECLCALLBACK(int) acpi_save_state(PPDMDEVINS pDevIns, PSSMHANDLE pSSMHandle)
1771{
1772 ACPIState *s = PDMINS_2_DATA(pDevIns, ACPIState *);
1773 return SSMR3PutStruct(pSSMHandle, s, &g_AcpiSavedStateFields5[0]);
1774}
1775
1776static DECLCALLBACK(int) acpi_load_state(PPDMDEVINS pDevIns, PSSMHANDLE pSSMHandle,
1777 uint32_t uVersion, uint32_t uPass)
1778{
1779 ACPIState *s = PDMINS_2_DATA(pDevIns, ACPIState *);
1780
1781
1782 Assert(uPass == SSM_PASS_FINAL); NOREF(uPass);
1783 /*
1784 * Unregister PM handlers, will register with actual base
1785 * after state successfully loaded.
1786 */
1787 int rc = acpiUnregisterPmHandlers(s);
1788 if (RT_FAILURE(rc))
1789 return rc;
1790
1791 switch (uVersion)
1792 {
1793 case 4:
1794 rc = SSMR3GetStruct(pSSMHandle, s, &g_AcpiSavedStateFields4[0]);
1795 /** @todo Provide saner defaults for fields not found in saved state. */
1796 break;
1797 case 5:
1798 rc = SSMR3GetStruct(pSSMHandle, s, &g_AcpiSavedStateFields5[0]);
1799 break;
1800 default:
1801 return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
1802 }
1803 if (RT_SUCCESS(rc))
1804 {
1805 rc = acpiRegisterPmHandlers(s);
1806 if (RT_FAILURE(rc))
1807 return rc;
1808 rc = acpiFetchBatteryStatus(s);
1809 if (RT_FAILURE(rc))
1810 return rc;
1811 rc = acpiFetchBatteryInfo(s);
1812 if (RT_FAILURE(rc))
1813 return rc;
1814 rc = acpiPMTimerReset(s);
1815 if (RT_FAILURE(rc))
1816 return rc;
1817 }
1818 return rc;
1819}
1820
1821/**
1822 * Queries an interface to the driver.
1823 *
1824 * @returns Pointer to interface.
1825 * @returns NULL if the interface was not supported by the driver.
1826 * @param pInterface Pointer to this interface structure.
1827 * @param enmInterface The requested interface identification.
1828 * @thread Any thread.
1829 */
1830static DECLCALLBACK(void *) acpiQueryInterface(PPDMIBASE pInterface, PDMINTERFACE enmInterface)
1831{
1832 ACPIState *pThis = (ACPIState*)((uintptr_t)pInterface - RT_OFFSETOF(ACPIState, IBase));
1833 switch (enmInterface)
1834 {
1835 case PDMINTERFACE_BASE:
1836 return &pThis->IBase;
1837 case PDMINTERFACE_ACPI_PORT:
1838 return &pThis->IACPIPort;
1839 default:
1840 return NULL;
1841 }
1842}
1843
1844/**
1845 * Create the ACPI tables.
1846 */
1847static int acpiPlantTables(ACPIState *s)
1848{
1849 int rc;
1850 RTGCPHYS32 rsdt_addr, xsdt_addr, fadt_acpi1_addr, fadt_acpi2_addr, facs_addr, dsdt_addr, last_addr, apic_addr = 0;
1851 uint32_t addend = 0;
1852 RTGCPHYS32 rsdt_addrs[4];
1853 RTGCPHYS32 xsdt_addrs[4];
1854 uint32_t cAddr;
1855 size_t rsdt_tbl_len = sizeof(ACPITBLHEADER);
1856 size_t xsdt_tbl_len = sizeof(ACPITBLHEADER);
1857
1858 cAddr = 1; /* FADT */
1859 if (s->u8UseIOApic)
1860 cAddr++; /* MADT */
1861
1862 rsdt_tbl_len += cAddr*4; /* each entry: 32 bits phys. address. */
1863 xsdt_tbl_len += cAddr*8; /* each entry: 64 bits phys. address. */
1864
1865 rc = CFGMR3QueryU64(s->pDevIns->pCfgHandle, "RamSize", &s->u64RamSize);
1866 if (RT_FAILURE(rc))
1867 return PDMDEV_SET_ERROR(s->pDevIns, rc,
1868 N_("Configuration error: Querying "
1869 "\"RamSize\" as integer failed"));
1870
1871 uint32_t cbRamHole;
1872 rc = CFGMR3QueryU32Def(s->pDevIns->pCfgHandle, "RamHoleSize", &cbRamHole, MM_RAM_HOLE_SIZE_DEFAULT);
1873 if (RT_FAILURE(rc))
1874 return PDMDEV_SET_ERROR(s->pDevIns, rc,
1875 N_("Configuration error: Querying \"RamHoleSize\" as integer failed"));
1876
1877 /*
1878 * Calc the sizes for the high and low regions.
1879 */
1880 const uint64_t offRamHole = _4G - cbRamHole;
1881 s->cbRamHigh = offRamHole < s->u64RamSize ? s->u64RamSize - offRamHole : 0;
1882 uint64_t cbRamLow = offRamHole < s->u64RamSize ? offRamHole : s->u64RamSize;
1883 if (cbRamLow > UINT32_C(0xffe00000)) /* See MEM3. */
1884 {
1885 /* Note: This is also enforced by DevPcBios.cpp. */
1886 LogRel(("DevACPI: Clipping cbRamLow=%#RX64 down to 0xffe00000.\n", cbRamLow));
1887 cbRamLow = UINT32_C(0xffe00000);
1888 }
1889 s->cbRamLow = (uint32_t)cbRamLow;
1890
1891 rsdt_addr = 0;
1892 xsdt_addr = RT_ALIGN_32(rsdt_addr + rsdt_tbl_len, 16);
1893 fadt_acpi1_addr = RT_ALIGN_32(xsdt_addr + xsdt_tbl_len, 16);
1894 fadt_acpi2_addr = RT_ALIGN_32(fadt_acpi1_addr + ACPITBLFADT_VERSION1_SIZE, 16);
1895 /** @todo ACPI 3.0 doc says it needs to be aligned on a 64 byte boundary. */
1896 facs_addr = RT_ALIGN_32(fadt_acpi2_addr + sizeof(ACPITBLFADT), 16);
1897 if (s->u8UseIOApic)
1898 {
1899 apic_addr = RT_ALIGN_32(facs_addr + sizeof(ACPITBLFACS), 16);
1900 /**
1901 * @todo nike: maybe some refactoring needed to compute tables layout,
1902 * but as this code is executed only once it doesn't make sense to optimize much
1903 */
1904 dsdt_addr = RT_ALIGN_32(apic_addr + AcpiTableMADT::sizeFor(s), 16);
1905 }
1906 else
1907 {
1908 dsdt_addr = RT_ALIGN_32(facs_addr + sizeof(ACPITBLFACS), 16);
1909 }
1910
1911 void* pDsdtCode = NULL;
1912 size_t uDsdtSize = 0;
1913 rc = acpiPrepareDsdt(s->pDevIns, &pDsdtCode, &uDsdtSize);
1914 if (RT_FAILURE(rc))
1915 return rc;
1916
1917 last_addr = RT_ALIGN_32(dsdt_addr + uDsdtSize, 16);
1918 if (last_addr > 0x10000)
1919 return PDMDEV_SET_ERROR(s->pDevIns, VERR_TOO_MUCH_DATA,
1920 N_("Error: ACPI tables > 64KB"));
1921
1922 Log(("RSDP 0x%08X\n", find_rsdp_space()));
1923 addend = s->cbRamLow - 0x10000;
1924 Log(("RSDT 0x%08X XSDT 0x%08X\n", rsdt_addr + addend, xsdt_addr + addend));
1925 Log(("FACS 0x%08X FADT (1.0) 0x%08X, FADT (2+) 0x%08X\n", facs_addr + addend, fadt_acpi1_addr + addend, fadt_acpi2_addr + addend));
1926 Log(("DSDT 0x%08X\n", dsdt_addr + addend));
1927 acpiSetupRSDP((ACPITBLRSDP*)s->au8RSDPPage, rsdt_addr + addend, xsdt_addr + addend);
1928 acpiSetupDSDT(s, dsdt_addr + addend, pDsdtCode, uDsdtSize);
1929 acpiCleanupDsdt(s->pDevIns, pDsdtCode);
1930 acpiSetupFACS(s, facs_addr + addend);
1931 acpiSetupFADT(s, fadt_acpi1_addr + addend, fadt_acpi2_addr + addend, facs_addr + addend, dsdt_addr + addend);
1932
1933 rsdt_addrs[0] = fadt_acpi1_addr + addend;
1934 xsdt_addrs[0] = fadt_acpi2_addr + addend;
1935 if (s->u8UseIOApic)
1936 {
1937 acpiSetupMADT(s, apic_addr + addend);
1938 rsdt_addrs[1] = apic_addr + addend;
1939 xsdt_addrs[1] = apic_addr + addend;
1940 }
1941
1942 rc = acpiSetupRSDT(s, rsdt_addr + addend, cAddr, rsdt_addrs);
1943 if (RT_FAILURE(rc))
1944 return rc;
1945 return acpiSetupXSDT(s, xsdt_addr + addend, cAddr, xsdt_addrs);
1946}
1947
1948static int acpiUpdatePmHandlers(ACPIState *pThis, RTIOPORT uNewBase)
1949{
1950 Log(("acpi: rebasing PM 0x%x -> 0x%x\n", pThis->uPmIoPortBase, uNewBase));
1951 if (uNewBase != pThis->uPmIoPortBase)
1952 {
1953 int rc;
1954
1955 rc = acpiUnregisterPmHandlers(pThis);
1956 if (RT_FAILURE(rc))
1957 return rc;
1958
1959 pThis->uPmIoPortBase = uNewBase;
1960
1961 rc = acpiRegisterPmHandlers(pThis);
1962 if (RT_FAILURE(rc))
1963 return rc;
1964
1965 /* We have to update FADT table acccording to the new base */
1966 rc = acpiPlantTables(pThis);
1967 AssertRC(rc);
1968 if (RT_FAILURE(rc))
1969 return rc;
1970 }
1971
1972 return VINF_SUCCESS;
1973}
1974
1975static uint32_t acpiPciConfigRead(PPCIDEVICE pPciDev, uint32_t Address, unsigned cb)
1976{
1977 PPDMDEVINS pDevIns = pPciDev->pDevIns;
1978 ACPIState* pThis = PDMINS_2_DATA(pDevIns, ACPIState *);
1979
1980 Log2(("acpi: PCI config read: 0x%x (%d)\n", Address, cb));
1981
1982 return pThis->pfnAcpiPciConfigRead(pPciDev, Address, cb);
1983}
1984
1985static void acpiPciConfigWrite(PPCIDEVICE pPciDev, uint32_t Address, uint32_t u32Value, unsigned cb)
1986{
1987 PPDMDEVINS pDevIns = pPciDev->pDevIns;
1988 ACPIState *pThis = PDMINS_2_DATA(pDevIns, ACPIState *);
1989
1990 Log2(("acpi: PCI config write: 0x%x -> 0x%x (%d)\n", u32Value, Address, cb));
1991 pThis->pfnAcpiPciConfigWrite(pPciDev, Address, u32Value, cb);
1992
1993 /* PMREGMISC written */
1994 if (Address == 0x80)
1995 {
1996 /* Check Power Management IO Space Enable (PMIOSE) bit */
1997 if (pPciDev->config[0x80] & 0x1)
1998 {
1999 int rc;
2000
2001 RTIOPORT uNewBase =
2002 RTIOPORT(RT_LE2H_U32(*(uint32_t*)&pPciDev->config[0x40]));
2003 uNewBase &= 0xffc0;
2004
2005 rc = acpiUpdatePmHandlers(pThis, uNewBase);
2006 AssertRC(rc);
2007 }
2008 }
2009}
2010
2011static DECLCALLBACK(void) acpiReset(PPDMDEVINS pDevIns)
2012{
2013 ACPIState *s = PDMINS_2_DATA(pDevIns, ACPIState *);
2014
2015 s->pm1a_en = 0;
2016 s->pm1a_sts = 0;
2017 s->pm1a_ctl = 0;
2018 s->pm_timer_initial = TMTimerGet(s->CTX_SUFF(ts));
2019 acpiPMTimerReset(s);
2020 s->uBatteryIndex = 0;
2021 s->uSystemInfoIndex = 0;
2022 s->gpe0_en = 0;
2023 s->gpe0_sts = 0;
2024 s->uSleepState = 0;
2025
2026 /** @todo Should we really reset PM base? */
2027 acpiUpdatePmHandlers(s, PM_PORT_BASE);
2028
2029 acpiPlantTables(s);
2030}
2031
2032/**
2033 * Relocates the GC pointer members.
2034 */
2035static DECLCALLBACK(void) acpiRelocate(PPDMDEVINS pDevIns, RTGCINTPTR offDelta)
2036{
2037 ACPIState *s = PDMINS_2_DATA(pDevIns, ACPIState *);
2038 s->tsRC = TMTimerRCPtr(s->CTX_SUFF(ts));
2039}
2040
2041/**
2042 * Construct a device instance for a VM.
2043 *
2044 * @returns VBox status.
2045 * @param pDevIns The device instance data.
2046 * If the registration structure is needed, pDevIns->pDevReg points to it.
2047 * @param iInstance Instance number. Use this to figure out which registers and such to use.
2048 * The device number is also found in pDevIns->iInstance, but since it's
2049 * likely to be freqently used PDM passes it as parameter.
2050 * @param pCfgHandle Configuration node handle for the device. Use this to obtain the configuration
2051 * of the device instance. It's also found in pDevIns->pCfgHandle, but like
2052 * iInstance it's expected to be used a bit in this function.
2053 */
2054static DECLCALLBACK(int) acpiConstruct(PPDMDEVINS pDevIns, int iInstance, PCFGMNODE pCfgHandle)
2055{
2056 ACPIState *s = PDMINS_2_DATA(pDevIns, ACPIState *);
2057 PCIDevice *dev = &s->dev;
2058
2059 /* Validate and read the configuration. */
2060 if (!CFGMR3AreValuesValid(pCfgHandle,
2061 "RamSize\0"
2062 "RamHoleSize\0"
2063 "IOAPIC\0"
2064 "NumCPUs\0"
2065 "GCEnabled\0"
2066 "R0Enabled\0"
2067 "HpetEnabled\0"
2068 "SmcEnabled\0"
2069 "FdcEnabled\0"
2070 "ShowRtc\0"
2071 "ShowCpu\0"
2072 ))
2073 return PDMDEV_SET_ERROR(pDevIns, VERR_PDM_DEVINS_UNKNOWN_CFG_VALUES,
2074 N_("Configuration error: Invalid config key for ACPI device"));
2075
2076 s->pDevIns = pDevIns;
2077
2078 /* query whether we are supposed to present an IOAPIC */
2079 int rc = CFGMR3QueryU8Def(pCfgHandle, "IOAPIC", &s->u8UseIOApic, 1);
2080 if (RT_FAILURE(rc))
2081 return PDMDEV_SET_ERROR(pDevIns, rc,
2082 N_("Configuration error: Failed to read \"IOAPIC\""));
2083
2084 rc = CFGMR3QueryU16Def(pCfgHandle, "NumCPUs", &s->cCpus, 1);
2085 if (RT_FAILURE(rc))
2086 return PDMDEV_SET_ERROR(pDevIns, rc,
2087 N_("Configuration error: Querying \"NumCPUs\" as integer failed"));
2088
2089 /* query whether we are supposed to present an FDC controller */
2090 rc = CFGMR3QueryBoolDef(pCfgHandle, "FdcEnabled", &s->fUseFdc, true);
2091 if (RT_FAILURE(rc))
2092 return PDMDEV_SET_ERROR(pDevIns, rc,
2093 N_("Configuration error: Failed to read \"FdcEnabled\""));
2094
2095 /* query whether we are supposed to present HPET */
2096 rc = CFGMR3QueryBoolDef(pCfgHandle, "HpetEnabled", &s->fUseHpet, false);
2097 if (RT_FAILURE(rc))
2098 return PDMDEV_SET_ERROR(pDevIns, rc,
2099 N_("Configuration error: Failed to read \"HpetEnabled\""));
2100 /* query whether we are supposed to present SMC */
2101 rc = CFGMR3QueryBoolDef(pCfgHandle, "SmcEnabled", &s->fUseSmc, false);
2102 if (RT_FAILURE(rc))
2103 return PDMDEV_SET_ERROR(pDevIns, rc,
2104 N_("Configuration error: Failed to read \"SmcEnabled\""));
2105
2106 /* query whether we are supposed to present RTC object */
2107 rc = CFGMR3QueryBoolDef(pCfgHandle, "ShowRtc", &s->fShowRtc, false);
2108 if (RT_FAILURE(rc))
2109 return PDMDEV_SET_ERROR(pDevIns, rc,
2110 N_("Configuration error: Failed to read \"ShowRtc\""));
2111
2112 /* query whether we are supposed to present CPU objects */
2113 rc = CFGMR3QueryBoolDef(pCfgHandle, "ShowCpu", &s->fShowCpu, false);
2114 if (RT_FAILURE(rc))
2115 return PDMDEV_SET_ERROR(pDevIns, rc,
2116 N_("Configuration error: Failed to read \"ShowCpu\""));
2117
2118 rc = CFGMR3QueryBool(pCfgHandle, "GCEnabled", &s->fGCEnabled);
2119 if (rc == VERR_CFGM_VALUE_NOT_FOUND)
2120 s->fGCEnabled = true;
2121 else if (RT_FAILURE(rc))
2122 return PDMDEV_SET_ERROR(pDevIns, rc,
2123 N_("Configuration error: Failed to read \"GCEnabled\""));
2124
2125 rc = CFGMR3QueryBool(pCfgHandle, "R0Enabled", &s->fR0Enabled);
2126 if (rc == VERR_CFGM_VALUE_NOT_FOUND)
2127 s->fR0Enabled = true;
2128 else if (RT_FAILURE(rc))
2129 return PDMDEV_SET_ERROR(pDevIns, rc,
2130 N_("configuration error: failed to read R0Enabled as boolean"));
2131
2132 /* Set default port base */
2133 s->uPmIoPortBase = PM_PORT_BASE;
2134
2135 /* */
2136 uint32_t rsdp_addr = find_rsdp_space();
2137 if (!rsdp_addr)
2138 return PDMDEV_SET_ERROR(pDevIns, VERR_NO_MEMORY,
2139 N_("Can not find space for RSDP. ACPI is disabled"));
2140
2141 rc = acpiPlantTables(s);
2142 if (RT_FAILURE(rc))
2143 return rc;
2144
2145 rc = PDMDevHlpROMRegister(pDevIns, rsdp_addr, 0x1000, s->au8RSDPPage,
2146 PGMPHYS_ROM_FLAGS_PERMANENT_BINARY, "ACPI RSDP");
2147 if (RT_FAILURE(rc))
2148 return rc;
2149
2150 rc = acpiRegisterPmHandlers(s);
2151 if (RT_FAILURE(rc))
2152 return rc;
2153
2154#define R(addr, cnt, writer, reader, description) \
2155 do { \
2156 rc = PDMDevHlpIOPortRegister(pDevIns, addr, cnt, s, writer, reader, \
2157 NULL, NULL, description); \
2158 if (RT_FAILURE(rc)) \
2159 return rc; \
2160 } while (0)
2161 R(SMI_CMD, 1, acpiSmiWrite, NULL, "ACPI SMI");
2162#ifdef DEBUG_ACPI
2163 R(DEBUG_HEX, 1, acpiDhexWrite, NULL, "ACPI Debug hex");
2164 R(DEBUG_CHR, 1, acpiDchrWrite, NULL, "ACPI Debug char");
2165#endif
2166 R(BAT_INDEX, 1, acpiBatIndexWrite, NULL, "ACPI Battery status index");
2167 R(BAT_DATA, 1, NULL, acpiBatDataRead, "ACPI Battery status data");
2168 R(SYSI_INDEX, 1, acpiSysInfoIndexWrite, NULL, "ACPI system info index");
2169 R(SYSI_DATA, 1, acpiSysInfoDataWrite, acpiSysInfoDataRead, "ACPI system info data");
2170 R(ACPI_RESET_BLK, 1, acpiResetWrite, NULL, "ACPI Reset");
2171#undef R
2172
2173 rc = PDMDevHlpTMTimerCreate(pDevIns, TMCLOCK_VIRTUAL_SYNC, acpiTimer, dev,
2174 TMTIMER_FLAGS_DEFAULT_CRIT_SECT, "ACPI Timer", &s->tsR3);
2175 if (RT_FAILURE(rc))
2176 {
2177 AssertMsgFailed(("pfnTMTimerCreate -> %Rrc\n", rc));
2178 return rc;
2179 }
2180
2181 s->tsR0 = TMTimerR0Ptr(s->tsR3);
2182 s->tsRC = TMTimerRCPtr(s->tsR3);
2183 s->pm_timer_initial = TMTimerGet(s->tsR3);
2184 acpiPMTimerReset(s);
2185
2186 PCIDevSetVendorId(dev, 0x8086); /* Intel */
2187 PCIDevSetDeviceId(dev, 0x7113); /* 82371AB */
2188
2189 /* See p. 50 of PIIX4 manual */
2190 dev->config[0x04] = 0x01; /* command */
2191 dev->config[0x05] = 0x00;
2192
2193 dev->config[0x06] = 0x80; /* status */
2194 dev->config[0x07] = 0x02;
2195
2196 dev->config[0x08] = 0x08; /* revision number */
2197
2198 dev->config[0x09] = 0x00; /* class code */
2199 dev->config[0x0a] = 0x80;
2200 dev->config[0x0b] = 0x06;
2201
2202 dev->config[0x0e] = 0x80; /* header type */
2203
2204 dev->config[0x0f] = 0x00; /* reserved */
2205
2206 dev->config[0x3c] = SCI_INT; /* interrupt line */
2207
2208#if 0
2209 dev->config[0x3d] = 0x01; /* interrupt pin */
2210#endif
2211
2212 dev->config[0x40] = 0x01; /* PM base address, this bit marks it as IO range, not PA */
2213
2214 rc = PDMDevHlpPCIRegister(pDevIns, dev);
2215 if (RT_FAILURE(rc))
2216 return rc;
2217
2218 PDMDevHlpPCISetConfigCallbacks(pDevIns, dev,
2219 acpiPciConfigRead, &s->pfnAcpiPciConfigRead,
2220 acpiPciConfigWrite, &s->pfnAcpiPciConfigWrite);
2221
2222 rc = PDMDevHlpSSMRegister(pDevIns, 5, sizeof(*s), acpi_save_state, acpi_load_state);
2223 if (RT_FAILURE(rc))
2224 return rc;
2225
2226 /*
2227 * Interfaces
2228 */
2229 /* IBase */
2230 s->IBase.pfnQueryInterface = acpiQueryInterface;
2231 /* IACPIPort */
2232 s->IACPIPort.pfnSleepButtonPress = acpiSleepButtonPress;
2233 s->IACPIPort.pfnPowerButtonPress = acpiPowerButtonPress;
2234 s->IACPIPort.pfnGetPowerButtonHandled = acpiGetPowerButtonHandled;
2235 s->IACPIPort.pfnGetGuestEnteredACPIMode = acpiGetGuestEnteredACPIMode;
2236
2237 /*
2238 * Get the corresponding connector interface
2239 */
2240 rc = PDMDevHlpDriverAttach(pDevIns, 0, &s->IBase, &s->pDrvBase, "ACPI Driver Port");
2241 if (RT_SUCCESS(rc))
2242 {
2243 s->pDrv = (PPDMIACPICONNECTOR)s->pDrvBase->pfnQueryInterface(s->pDrvBase, PDMINTERFACE_ACPI_CONNECTOR);
2244 if (!s->pDrv)
2245 return PDMDEV_SET_ERROR(pDevIns, VERR_PDM_MISSING_INTERFACE,
2246 N_("LUN #0 doesn't have an ACPI connector interface"));
2247 }
2248 else if (rc == VERR_PDM_NO_ATTACHED_DRIVER)
2249 {
2250 Log(("acpi: %s/%d: warning: no driver attached to LUN #0!\n",
2251 pDevIns->pDevReg->szDeviceName, pDevIns->iInstance));
2252 rc = VINF_SUCCESS;
2253 }
2254 else
2255 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Failed to attach LUN #0"));
2256
2257 return rc;
2258}
2259
2260/**
2261 * The device registration structure.
2262 */
2263const PDMDEVREG g_DeviceACPI =
2264{
2265 /* u32Version */
2266 PDM_DEVREG_VERSION,
2267 /* szDeviceName */
2268 "acpi",
2269 /* szRCMod */
2270 "VBoxDDGC.gc",
2271 /* szR0Mod */
2272 "VBoxDDR0.r0",
2273 /* pszDescription */
2274 "Advanced Configuration and Power Interface",
2275 /* fFlags */
2276 PDM_DEVREG_FLAGS_DEFAULT_BITS | PDM_DEVREG_FLAGS_RC | PDM_DEVREG_FLAGS_R0,
2277 /* fClass */
2278 PDM_DEVREG_CLASS_ACPI,
2279 /* cMaxInstances */
2280 ~0,
2281 /* cbInstance */
2282 sizeof(ACPIState),
2283 /* pfnConstruct */
2284 acpiConstruct,
2285 /* pfnDestruct */
2286 NULL,
2287 /* pfnRelocate */
2288 acpiRelocate,
2289 /* pfnIOCtl */
2290 NULL,
2291 /* pfnPowerOn */
2292 NULL,
2293 /* pfnReset */
2294 acpiReset,
2295 /* pfnSuspend */
2296 NULL,
2297 /* pfnResume */
2298 NULL,
2299 /* pfnAttach */
2300 NULL,
2301 /* pfnDetach */
2302 NULL,
2303 /* pfnQueryInterface. */
2304 NULL,
2305 /* pfnInitComplete */
2306 NULL,
2307 /* pfnPowerOff */
2308 NULL,
2309 /* pfnSoftReset */
2310 NULL,
2311 /* u32VersionEnd */
2312 PDM_DEVREG_VERSION
2313};
2314
2315#endif /* IN_RING3 */
2316#endif /* !VBOX_DEVICE_STRUCT_TESTCASE */
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