VirtualBox

source: vbox/trunk/src/VBox/Devices/PC/DevACPI.cpp@ 16005

Last change on this file since 16005 was 16005, checked in by vboxsync, 16 years ago

Implemented in-place disable of ACPI devices, added disabled by default record
for HPET and SMC into ACPI file.
  • Property svn:eol-style set to native
  • Property svn:keywords set to Id
File size: 69.8 KB
Line 
1/* $Id: DevACPI.cpp 16005 2009-01-16 21:48:26Z vboxsync $ */
2/** @file
3 * DevACPI - Advanced Configuration and Power Interface (ACPI) Device.
4 */
5
6/*
7 * Copyright (C) 2006-2007 Sun Microsystems, Inc.
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 *
17 * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
18 * Clara, CA 95054 USA or visit http://www.sun.com if you need
19 * additional information or have any questions.
20 */
21
22#define LOG_GROUP LOG_GROUP_DEV_ACPI
23#include <VBox/pdmdev.h>
24#include <VBox/log.h>
25#include <iprt/assert.h>
26#include <iprt/asm.h>
27#ifdef IN_RING3
28# include <iprt/alloc.h>
29# include <iprt/string.h>
30#endif /* IN_RING3 */
31
32#include "../Builtins.h"
33
34#ifdef LOG_ENABLED
35# define DEBUG_ACPI
36#endif
37
38/* the compiled DSL */
39#if defined(IN_RING3) && !defined(VBOX_DEVICE_STRUCT_TESTCASE)
40#include <vboxaml.hex>
41#endif /* !IN_RING3 */
42
43#define IO_READ_PROTO(name) \
44 PDMBOTHCBDECL(int) name (PPDMDEVINS pDevIns, void *pvUser, \
45 RTIOPORT Port, uint32_t *pu32, unsigned cb)
46
47#define IO_WRITE_PROTO(name) \
48 PDMBOTHCBDECL(int) name (PPDMDEVINS pDevIns, void *pvUser, \
49 RTIOPORT Port, uint32_t u32, unsigned cb)
50
51#define DEBUG_HEX 0x3000
52#define DEBUG_CHR 0x3001
53
54#define PM_TMR_FREQ 3579545
55#define PM1a_EVT_BLK 0x00004000
56#define PM1b_EVT_BLK 0x00000000 /**< not supported */
57#define PM1a_CTL_BLK 0x00004004
58#define PM1b_CTL_BLK 0x00000000 /**< not supported */
59#define PM2_CTL_BLK 0x00000000 /**< not supported */
60#define PM_TMR_BLK 0x00004008
61#define GPE0_BLK 0x00004020
62#define GPE1_BLK 0x00000000 /**< not supported */
63#define BAT_INDEX 0x00004040
64#define BAT_DATA 0x00004044
65#define SYSI_INDEX 0x00004048
66#define SYSI_DATA 0x0000404c
67#define ACPI_RESET_BLK 0x00004050
68
69/* PM1x status register bits */
70#define TMR_STS RT_BIT(0)
71#define RSR1_STS (RT_BIT(1) | RT_BIT(2) | RT_BIT(3))
72#define BM_STS RT_BIT(4)
73#define GBL_STS RT_BIT(5)
74#define RSR2_STS (RT_BIT(6) | RT_BIT(7))
75#define PWRBTN_STS RT_BIT(8)
76#define SLPBTN_STS RT_BIT(9)
77#define RTC_STS RT_BIT(10)
78#define IGN_STS RT_BIT(11)
79#define RSR3_STS (RT_BIT(12) | RT_BIT(13) | RT_BIT(14))
80#define WAK_STS RT_BIT(15)
81#define RSR_STS (RSR1_STS | RSR2_STS | RSR3_STS)
82
83/* PM1x enable register bits */
84#define TMR_EN RT_BIT(0)
85#define RSR1_EN (RT_BIT(1) | RT_BIT(2) | RT_BIT(3) | RT_BIT(4))
86#define GBL_EN RT_BIT(5)
87#define RSR2_EN (RT_BIT(6) | RT_BIT(7))
88#define PWRBTN_EN RT_BIT(8)
89#define SLPBTN_EN RT_BIT(9)
90#define RTC_EN RT_BIT(10)
91#define RSR3_EN (RT_BIT(11) | RT_BIT(12) | RT_BIT(13) | RT_BIT(14) | RT_BIT(15))
92#define RSR_EN (RSR1_EN | RSR2_EN | RSR3_EN)
93#define IGN_EN 0
94
95/* PM1x control register bits */
96#define SCI_EN RT_BIT(0)
97#define BM_RLD RT_BIT(1)
98#define GBL_RLS RT_BIT(2)
99#define RSR1_CNT (RT_BIT(3) | RT_BIT(4) | RT_BIT(5) | RT_BIT(6) | RT_BIT(7) | RT_BIT(8))
100#define IGN_CNT RT_BIT(9)
101#define SLP_TYPx_SHIFT 10
102#define SLP_TYPx_MASK 7
103#define SLP_EN RT_BIT(13)
104#define RSR2_CNT (RT_BIT(14) | RT_BIT(15))
105#define RSR_CNT (RSR1_CNT | RSR2_CNT)
106
107#define GPE0_BATTERY_INFO_CHANGED RT_BIT(0)
108
109enum
110{
111 BAT_STATUS_STATE = 0x00, /**< BST battery state */
112 BAT_STATUS_PRESENT_RATE = 0x01, /**< BST battery present rate */
113 BAT_STATUS_REMAINING_CAPACITY = 0x02, /**< BST battery remaining capacity */
114 BAT_STATUS_PRESENT_VOLTAGE = 0x03, /**< BST battery present voltage */
115 BAT_INFO_UNITS = 0x04, /**< BIF power unit */
116 BAT_INFO_DESIGN_CAPACITY = 0x05, /**< BIF design capacity */
117 BAT_INFO_LAST_FULL_CHARGE_CAPACITY = 0x06, /**< BIF last full charge capacity */
118 BAT_INFO_TECHNOLOGY = 0x07, /**< BIF battery technology */
119 BAT_INFO_DESIGN_VOLTAGE = 0x08, /**< BIF design voltage */
120 BAT_INFO_DESIGN_CAPACITY_OF_WARNING = 0x09, /**< BIF design capacity of warning */
121 BAT_INFO_DESIGN_CAPACITY_OF_LOW = 0x0A, /**< BIF design capacity of low */
122 BAT_INFO_CAPACITY_GRANULARITY_1 = 0x0B, /**< BIF battery capacity granularity 1 */
123 BAT_INFO_CAPACITY_GRANULARITY_2 = 0x0C, /**< BIF battery capacity granularity 2 */
124 BAT_DEVICE_STATUS = 0x0D, /**< STA device status */
125 BAT_POWER_SOURCE = 0x0E, /**< PSR power source */
126 BAT_INDEX_LAST
127};
128
129enum
130{
131 SYSTEM_INFO_INDEX_MEMORY_LENGTH = 0,
132 SYSTEM_INFO_INDEX_USE_IOAPIC = 1,
133 SYSTEM_INFO_INDEX_HPET_STATUS = 2,
134 SYSTEM_INFO_INDEX_SMC_STATUS = 3,
135 SYSTEM_INFO_INDEX_FDC_STATUS = 4,
136 SYSTEM_INFO_INDEX_LAST = 5,
137 SYSTEM_INFO_INDEX_INVALID = 0x80,
138 SYSTEM_INFO_INDEX_VALID = 0x200
139};
140
141#define AC_OFFLINE 0
142#define AC_ONLINE 1
143
144#define BAT_TECH_PRIMARY 1
145#define BAT_TECH_SECONDARY 2
146
147#define STA_DEVICE_PRESENT_MASK RT_BIT(0)
148#define STA_DEVICE_ENABLED_MASK RT_BIT(1)
149#define STA_DEVICE_SHOW_IN_UI_MASK RT_BIT(2)
150#define STA_DEVICE_FUNCTIONING_PROPERLY_MASK RT_BIT(3)
151#define STA_BATTERY_PRESENT_MASK RT_BIT(4)
152
153struct ACPIState
154{
155 PCIDevice dev;
156 uint16_t pm1a_en;
157 uint16_t pm1a_sts;
158 uint16_t pm1a_ctl;
159 /** Number of logical CPUs in guest */
160 uint16_t cCpus;
161 int64_t pm_timer_initial;
162 PTMTIMERR3 tsR3;
163 PTMTIMERR0 tsR0;
164 PTMTIMERRC tsRC;
165
166 uint32_t gpe0_en;
167 uint32_t gpe0_sts;
168
169 unsigned int uBatteryIndex;
170 uint32_t au8BatteryInfo[13];
171
172 unsigned int uSystemInfoIndex;
173 uint64_t u64RamSize;
174
175 /** Current ACPI S* state. We support S0 and S5 */
176 uint32_t uSleepState;
177 uint8_t au8RSDPPage[0x1000];
178 /** This is a workaround for incorrect index field handling by Intels ACPICA.
179 * The system info _INI method writes to offset 0x200. We either observe a
180 * write request to index 0x80 (in that case we don't change the index) or a
181 * write request to offset 0x200 (in that case we divide the index value by
182 * 4. Note that the _STA method is sometimes called prior to the _INI method
183 * (ACPI spec 6.3.7, _STA). See the special case for BAT_DEVICE_STATUS in
184 * acpiBatIndexWrite() for handling this. */
185 uint8_t u8IndexShift;
186 uint8_t u8UseIOApic;
187 uint8_t u8UseFdc;
188 bool fPowerButtonHandled;
189
190 /** ACPI port base interface. */
191 PDMIBASE IBase;
192 /** ACPI port interface. */
193 PDMIACPIPORT IACPIPort;
194 /** Pointer to the device instance. */
195 PPDMDEVINSR3 pDevIns;
196 /** Pointer to the driver base interface */
197 R3PTRTYPE(PPDMIBASE) pDrvBase;
198 /** Pointer to the driver connector interface */
199 R3PTRTYPE(PPDMIACPICONNECTOR) pDrv;
200
201 /* If High Precision Event Timer device should be supported */
202 uint8_t u8UseHpet;
203 /* If System Management Controller device should be supported */
204 uint8_t u8UseSmc;
205
206 uint32_t Alignment0; /**< Structure size alignment. */
207};
208
209#pragma pack(1)
210
211/** Generic Address Structure (see ACPIspec 3.0, 5.2.3.1) */
212struct ACPIGENADDR
213{
214 uint8_t u8AddressSpaceId; /**< 0=sys, 1=IO, 2=PCICfg, 3=emb, 4=SMBus */
215 uint8_t u8RegisterBitWidth; /**< size in bits of the given register */
216 uint8_t u8RegisterBitOffset; /**< bit offset of register */
217 uint8_t u8AccessSize; /**< 1=byte, 2=word, 3=dword, 4=qword */
218 uint64_t u64Address; /**< 64-bit address of register */
219};
220AssertCompileSize(ACPIGENADDR, 12);
221
222/** Root System Description Pointer */
223struct ACPITBLRSDP
224{
225 uint8_t au8Signature[8]; /**< 'RSD PTR ' */
226 uint8_t u8Checksum; /**< checksum for the first 20 bytes */
227 uint8_t au8OemId[6]; /**< OEM-supplied identifier */
228 uint8_t u8Revision; /**< revision number, currently 2 */
229#define ACPI_REVISION 2 /**< ACPI 3.0 */
230 uint32_t u32RSDT; /**< phys addr of RSDT */
231 uint32_t u32Length; /**< bytes of this table */
232 uint64_t u64XSDT; /**< 64-bit phys addr of XSDT */
233 uint8_t u8ExtChecksum; /**< checksum of entire table */
234 uint8_t u8Reserved[3]; /**< reserved */
235};
236AssertCompileSize(ACPITBLRSDP, 36);
237
238/** System Description Table Header */
239struct ACPITBLHEADER
240{
241 uint8_t au8Signature[4]; /**< table identifier */
242 uint32_t u32Length; /**< length of the table including header */
243 uint8_t u8Revision; /**< revision number */
244 uint8_t u8Checksum; /**< all fields inclusive this add to zero */
245 uint8_t au8OemId[6]; /**< OEM-supplied string */
246 uint8_t au8OemTabId[8]; /**< to identify the particular data table */
247 uint32_t u32OemRevision; /**< OEM-supplied revision number */
248 uint8_t au8CreatorId[4]; /**< ID for the ASL compiler */
249 uint32_t u32CreatorRev; /**< revision for the ASL compiler */
250};
251AssertCompileSize(ACPITBLHEADER, 36);
252
253/** Root System Description Table */
254struct ACPITBLRSDT
255{
256 ACPITBLHEADER header;
257 uint32_t u32Entry[1]; /**< array of phys. addresses to other tables */
258};
259AssertCompileSize(ACPITBLRSDT, 40);
260
261/** Extended System Description Table */
262struct ACPITBLXSDT
263{
264 ACPITBLHEADER header;
265 uint64_t u64Entry[1]; /**< array of phys. addresses to other tables */
266};
267AssertCompileSize(ACPITBLXSDT, 44);
268
269/** Fixed ACPI Description Table */
270struct ACPITBLFADT
271{
272 ACPITBLHEADER header;
273 uint32_t u32FACS; /**< phys. address of FACS */
274 uint32_t u32DSDT; /**< phys. address of DSDT */
275 uint8_t u8IntModel; /**< was eleminated in ACPI 2.0 */
276#define INT_MODEL_DUAL_PIC 1 /**< for ACPI 2+ */
277#define INT_MODEL_MULTIPLE_APIC 2
278 uint8_t u8PreferredPMProfile; /**< preferred power management profile */
279 uint16_t u16SCIInt; /**< system vector the SCI is wired in 8259 mode */
280#define SCI_INT 9
281 uint32_t u32SMICmd; /**< system port address of SMI command port */
282#define SMI_CMD 0x0000442e
283 uint8_t u8AcpiEnable; /**< SMICmd val to disable ownship of ACPIregs */
284#define ACPI_ENABLE 0xa1
285 uint8_t u8AcpiDisable; /**< SMICmd val to re-enable ownship of ACPIregs */
286#define ACPI_DISABLE 0xa0
287 uint8_t u8S4BIOSReq; /**< SMICmd val to enter S4BIOS state */
288 uint8_t u8PStateCnt; /**< SMICmd val to assume processor performance
289 state control responsibility */
290 uint32_t u32PM1aEVTBLK; /**< port addr of PM1a event regs block */
291 uint32_t u32PM1bEVTBLK; /**< port addr of PM1b event regs block */
292 uint32_t u32PM1aCTLBLK; /**< port addr of PM1a control regs block */
293 uint32_t u32PM1bCTLBLK; /**< port addr of PM1b control regs block */
294 uint32_t u32PM2CTLBLK; /**< port addr of PM2 control regs block */
295 uint32_t u32PMTMRBLK; /**< port addr of PMTMR regs block */
296 uint32_t u32GPE0BLK; /**< port addr of gen-purp event 0 regs block */
297 uint32_t u32GPE1BLK; /**< port addr of gen-purp event 1 regs block */
298 uint8_t u8PM1EVTLEN; /**< bytes decoded by PM1a_EVT_BLK. >= 4 */
299 uint8_t u8PM1CTLLEN; /**< bytes decoded by PM1b_CNT_BLK. >= 2 */
300 uint8_t u8PM2CTLLEN; /**< bytes decoded by PM2_CNT_BLK. >= 1 or 0 */
301 uint8_t u8PMTMLEN; /**< bytes decoded by PM_TMR_BLK. ==4 */
302 uint8_t u8GPE0BLKLEN; /**< bytes decoded by GPE0_BLK. %2==0 */
303#define GPE0_BLK_LEN 2
304 uint8_t u8GPE1BLKLEN; /**< bytes decoded by GPE1_BLK. %2==0 */
305#define GPE1_BLK_LEN 0
306 uint8_t u8GPE1BASE; /**< offset of GPE1 based events */
307#define GPE1_BASE 0
308 uint8_t u8CSTCNT; /**< SMICmd val to indicate OS supp for C states */
309 uint16_t u16PLVL2LAT; /**< us to enter/exit C2. >100 => unsupported */
310#define P_LVL2_LAT 101 /**< C2 state not supported */
311 uint16_t u16PLVL3LAT; /**< us to enter/exit C3. >1000 => unsupported */
312#define P_LVL3_LAT 1001 /**< C3 state not supported */
313 uint16_t u16FlushSize; /**< # of flush strides to read to flush dirty
314 lines from any processors memory caches */
315#define FLUSH_SIZE 0 /**< Ignored if WBVIND set in FADT_FLAGS */
316 uint16_t u16FlushStride; /**< cache line width */
317#define FLUSH_STRIDE 0 /**< Ignored if WBVIND set in FADT_FLAGS */
318 uint8_t u8DutyOffset;
319 uint8_t u8DutyWidth;
320 uint8_t u8DayAlarm; /**< RTC CMOS RAM index of day-of-month alarm */
321 uint8_t u8MonAlarm; /**< RTC CMOS RAM index of month-of-year alarm */
322 uint8_t u8Century; /**< RTC CMOS RAM index of century */
323 uint16_t u16IAPCBOOTARCH; /**< IA-PC boot architecture flags */
324#define IAPC_BOOT_ARCH_LEGACY_DEV RT_BIT(0) /**< legacy devices present such as LPT
325 (COM too?) */
326#define IAPC_BOOT_ARCH_8042 RT_BIT(1) /**< legacy keyboard device present */
327#define IAPC_BOOT_ARCH_NO_VGA RT_BIT(2) /**< VGA not present */
328 uint8_t u8Must0_0; /**< must be 0 */
329 uint32_t u32Flags; /**< fixed feature flags */
330#define FADT_FL_WBINVD RT_BIT(0) /**< emulation of WBINVD available */
331#define FADT_FL_WBINVD_FLUSH RT_BIT(1)
332#define FADT_FL_PROC_C1 RT_BIT(2) /**< 1=C1 supported on all processors */
333#define FADT_FL_P_LVL2_UP RT_BIT(3) /**< 1=C2 works on SMP and UNI systems */
334#define FADT_FL_PWR_BUTTON RT_BIT(4) /**< 1=power button handled as ctrl method dev */
335#define FADT_FL_SLP_BUTTON RT_BIT(5) /**< 1=sleep button handled as ctrl method dev */
336#define FADT_FL_FIX_RTC RT_BIT(6) /**< 0=RTC wake status in fixed register */
337#define FADT_FL_RTC_S4 RT_BIT(7) /**< 1=RTC can wake system from S4 */
338#define FADT_FL_TMR_VAL_EXT RT_BIT(8) /**< 1=TMR_VAL implemented as 32 bit */
339#define FADT_FL_DCK_CAP RT_BIT(9) /**< 0=system cannot support docking */
340#define FADT_FL_RESET_REG_SUP RT_BIT(10) /**< 1=system supports system resets */
341#define FADT_FL_SEALED_CASE RT_BIT(11) /**< 1=case is sealed */
342#define FADT_FL_HEADLESS RT_BIT(12) /**< 1=system cannot detect moni/keyb/mouse */
343#define FADT_FL_CPU_SW_SLP RT_BIT(13)
344#define FADT_FL_PCI_EXT_WAK RT_BIT(14) /**< 1=system supports PCIEXP_WAKE_STS */
345#define FADT_FL_USE_PLATFORM_CLOCK RT_BIT(15) /**< 1=system has ACPI PM timer */
346#define FADT_FL_S4_RTC_STS_VALID RT_BIT(16) /**< 1=RTC_STS flag is valid when waking from S4 */
347#define FADT_FL_REMOVE_POWER_ON_CAPABLE RT_BIT(17) /**< 1=platform can remote power on */
348#define FADT_FL_FORCE_APIC_CLUSTER_MODEL RT_BIT(18)
349#define FADT_FL_FORCE_APIC_PHYS_DEST_MODE RT_BIT(19)
350 ACPIGENADDR ResetReg; /**< ext addr of reset register */
351 uint8_t u8ResetVal; /**< ResetReg value to reset the system */
352#define ACPI_RESET_REG_VAL 0x10
353 uint8_t au8Must0_1[3]; /**< must be 0 */
354 uint64_t u64XFACS; /**< 64-bit phys address of FACS */
355 uint64_t u64XDSDT; /**< 64-bit phys address of DSDT */
356 ACPIGENADDR X_PM1aEVTBLK; /**< ext addr of PM1a event regs block */
357 ACPIGENADDR X_PM1bEVTBLK; /**< ext addr of PM1b event regs block */
358 ACPIGENADDR X_PM1aCTLBLK; /**< ext addr of PM1a control regs block */
359 ACPIGENADDR X_PM1bCTLBLK; /**< ext addr of PM1b control regs block */
360 ACPIGENADDR X_PM2CTLBLK; /**< ext addr of PM2 control regs block */
361 ACPIGENADDR X_PMTMRBLK; /**< ext addr of PMTMR control regs block */
362 ACPIGENADDR X_GPE0BLK; /**< ext addr of GPE1 regs block */
363 ACPIGENADDR X_GPE1BLK; /**< ext addr of GPE1 regs block */
364};
365AssertCompileSize(ACPITBLFADT, 244);
366
367/** Firmware ACPI Control Structure */
368struct ACPITBLFACS
369{
370 uint8_t au8Signature[4]; /**< 'FACS' */
371 uint32_t u32Length; /**< bytes of entire FACS structure >= 64 */
372 uint32_t u32HWSignature; /**< systems HW signature at last boot */
373 uint32_t u32FWVector; /**< address of waking vector */
374 uint32_t u32GlobalLock; /**< global lock to sync HW/SW */
375 uint32_t u32Flags; /**< FACS flags */
376 uint64_t u64X_FWVector; /**< 64-bit waking vector */
377 uint8_t u8Version; /**< version of this table */
378 uint8_t au8Reserved[31]; /**< zero */
379};
380AssertCompileSize(ACPITBLFACS, 64);
381
382/** Processor Local APIC Structure */
383struct ACPITBLLAPIC
384{
385 uint8_t u8Type; /**< 0 = LAPIC */
386 uint8_t u8Length; /**< 8 */
387 uint8_t u8ProcId; /**< processor ID */
388 uint8_t u8ApicId; /**< local APIC ID */
389 uint32_t u32Flags; /**< Flags */
390#define LAPIC_ENABLED 0x1
391};
392AssertCompileSize(ACPITBLLAPIC, 8);
393
394/** I/O APIC Structure */
395struct ACPITBLIOAPIC
396{
397 uint8_t u8Type; /**< 1 == I/O APIC */
398 uint8_t u8Length; /**< 12 */
399 uint8_t u8IOApicId; /**< I/O APIC ID */
400 uint8_t u8Reserved; /**< 0 */
401 uint32_t u32Address; /**< phys address to access I/O APIC */
402 uint32_t u32GSIB; /**< global system interrupt number to start */
403};
404AssertCompileSize(ACPITBLIOAPIC, 12);
405
406#ifdef VBOX_WITH_SMP_GUESTS
407#ifdef IN_RING3 /**@todo r=bird: Move this down to where it's used. */
408
409# define PCAT_COMPAT 0x1 /**< system has also a dual-8259 setup */
410
411/**
412 * Multiple APIC Description Table.
413 *
414 * This structure looks somewhat convoluted due layout of MADT table in MP case.
415 * There extpected to be multiple LAPIC records for each CPU, thus we cannot
416 * use regular C structure and proxy to raw memory instead.
417 */
418class AcpiTableMADT
419{
420 /**
421 * All actual data stored in dynamically allocated memory pointed by this field.
422 */
423 uint8_t* pData;
424 /**
425 * Number of CPU entries in this MADT.
426 */
427 uint32_t cCpus;
428
429 public:
430 /**
431 * Address of ACPI header
432 */
433 inline ACPITBLHEADER* header_addr() const
434 {
435 return (ACPITBLHEADER*)pData;
436 }
437
438 /**
439 * Address of local APIC for each CPU. Note that different CPUs address different LAPICs,
440 * although address is the same for all of them.
441 */
442 inline uint32_t* u32LAPIC_addr() const
443 {
444 return (uint32_t*)(header_addr() + 1);
445 }
446
447 /**
448 * Address of APIC flags
449 */
450 inline uint32_t* u32Flags_addr() const
451 {
452 return (uint32_t*)(u32LAPIC_addr() + 1);
453 }
454
455 /**
456 * Address of per-CPU LAPIC descriptions
457 */
458 inline ACPITBLLAPIC* LApics_addr() const
459 {
460 return (ACPITBLLAPIC*)(u32Flags_addr() + 1);
461 }
462
463 /**
464 * Address of IO APIC description
465 */
466 inline ACPITBLIOAPIC* IOApic_addr() const
467 {
468 return (ACPITBLIOAPIC*)(LApics_addr() + cCpus);
469 }
470
471 /**
472 * Size of MADT.
473 * Note that this function assumes IOApic to be the last field in structure.
474 */
475 inline uint32_t size() const
476 {
477 return (uint8_t*)(IOApic_addr() + 1)-(uint8_t*)header_addr();
478 }
479
480 /**
481 * Raw data of MADT.
482 */
483 inline const uint8_t* data() const
484 {
485 return pData;
486 }
487
488 /**
489 * Size of MADT for given ACPI config, useful to compute layout.
490 */
491 static uint32_t sizeFor(ACPIState *s)
492 {
493 return AcpiTableMADT(s->cCpus).size();
494 }
495
496 /*
497 * Constructor, only works in Ring 3, doesn't look like a big deal.
498 */
499 AcpiTableMADT(uint16_t cpus)
500 {
501 cCpus = cpus;
502 pData = 0;
503 uint32_t sSize = size();
504 pData = (uint8_t*)RTMemAllocZ(sSize);
505 }
506
507 ~AcpiTableMADT()
508 {
509 RTMemFree(pData);
510 }
511};
512#endif /* IN_RING3 */
513
514#else /* !VBOX_WITH_SMP_GUESTS */
515/** Multiple APIC Description Table */
516struct ACPITBLMADT
517{
518 ACPITBLHEADER header;
519 uint32_t u32LAPIC; /**< local APIC address */
520 uint32_t u32Flags; /**< Flags */
521#define PCAT_COMPAT 0x1 /**< system has also a dual-8259 setup */
522 ACPITBLLAPIC LApic;
523 ACPITBLIOAPIC IOApic;
524};
525AssertCompileSize(ACPITBLMADT, 64);
526#endif /* !VBOX_WITH_SMP_GUESTS */
527
528#pragma pack()
529
530
531#ifndef VBOX_DEVICE_STRUCT_TESTCASE
532__BEGIN_DECLS
533IO_READ_PROTO (acpiPMTmrRead);
534#ifdef IN_RING3
535IO_READ_PROTO (acpiPm1aEnRead);
536IO_WRITE_PROTO (acpiPM1aEnWrite);
537IO_READ_PROTO (acpiPm1aStsRead);
538IO_WRITE_PROTO (acpiPM1aStsWrite);
539IO_READ_PROTO (acpiPm1aCtlRead);
540IO_WRITE_PROTO (acpiPM1aCtlWrite);
541IO_WRITE_PROTO (acpiSmiWrite);
542IO_WRITE_PROTO (acpiBatIndexWrite);
543IO_READ_PROTO (acpiBatDataRead);
544IO_READ_PROTO (acpiSysInfoDataRead);
545IO_WRITE_PROTO (acpiSysInfoDataWrite);
546IO_READ_PROTO (acpiGpe0EnRead);
547IO_WRITE_PROTO (acpiGpe0EnWrite);
548IO_READ_PROTO (acpiGpe0StsRead);
549IO_WRITE_PROTO (acpiGpe0StsWrite);
550IO_WRITE_PROTO (acpiResetWrite);
551# ifdef DEBUG_ACPI
552IO_WRITE_PROTO (acpiDhexWrite);
553IO_WRITE_PROTO (acpiDchrWrite);
554# endif
555#endif
556__END_DECLS
557
558#ifdef IN_RING3
559
560/* Simple acpiChecksum: all the bytes must add up to 0. */
561static uint8_t acpiChecksum (const uint8_t * const data, uint32_t len)
562{
563 uint8_t sum = 0;
564 for (size_t i = 0; i < len; ++i)
565 sum += data[i];
566 return -sum;
567}
568
569static void acpiPrepareHeader (ACPITBLHEADER *header, const char au8Signature[4],
570 uint32_t u32Length, uint8_t u8Revision)
571{
572 memcpy(header->au8Signature, au8Signature, 4);
573 header->u32Length = RT_H2LE_U32(u32Length);
574 header->u8Revision = u8Revision;
575 memcpy(header->au8OemId, "VBOX ", 6);
576 memcpy(header->au8OemTabId, "VBOX", 4);
577 memcpy(header->au8OemTabId+4, au8Signature, 4);
578 header->u32OemRevision = RT_H2LE_U32(1);
579 memcpy(header->au8CreatorId, "ASL ", 4);
580 header->u32CreatorRev = RT_H2LE_U32(0x61);
581}
582
583static void acpiWriteGenericAddr(ACPIGENADDR *g, uint8_t u8AddressSpaceId,
584 uint8_t u8RegisterBitWidth, uint8_t u8RegisterBitOffset,
585 uint8_t u8AccessSize, uint64_t u64Address)
586{
587 g->u8AddressSpaceId = u8AddressSpaceId;
588 g->u8RegisterBitWidth = u8RegisterBitWidth;
589 g->u8RegisterBitOffset = u8RegisterBitOffset;
590 g->u8AccessSize = u8AccessSize;
591 g->u64Address = RT_H2LE_U64(u64Address);
592}
593
594static void acpiPhyscpy (ACPIState *s, RTGCPHYS32 dst, const void * const src, size_t size)
595{
596 PDMDevHlpPhysWrite (s->pDevIns, dst, src, size);
597}
598
599/* Differentiated System Description Table (DSDT) */
600static void acpiSetupDSDT (ACPIState *s, RTGCPHYS32 addr)
601{
602 acpiPhyscpy (s, addr, AmlCode, sizeof(AmlCode));
603}
604
605/* Firmware ACPI Control Structure (FACS) */
606static void acpiSetupFACS (ACPIState *s, RTGCPHYS32 addr)
607{
608 ACPITBLFACS facs;
609
610 memset (&facs, 0, sizeof(facs));
611 memcpy (facs.au8Signature, "FACS", 4);
612 facs.u32Length = RT_H2LE_U32(sizeof(ACPITBLFACS));
613 facs.u32HWSignature = RT_H2LE_U32(0);
614 facs.u32FWVector = RT_H2LE_U32(0);
615 facs.u32GlobalLock = RT_H2LE_U32(0);
616 facs.u32Flags = RT_H2LE_U32(0);
617 facs.u64X_FWVector = RT_H2LE_U64(0);
618 facs.u8Version = 1;
619
620 acpiPhyscpy (s, addr, (const uint8_t*)&facs, sizeof(facs));
621}
622
623/* Fixed ACPI Description Table (FADT aka FACP) */
624static void acpiSetupFADT (ACPIState *s, RTGCPHYS32 addr, uint32_t facs_addr, uint32_t dsdt_addr)
625{
626 ACPITBLFADT fadt;
627
628 memset (&fadt, 0, sizeof(fadt));
629 acpiPrepareHeader (&fadt.header, "FACP", sizeof(fadt), 4);
630 fadt.u32FACS = RT_H2LE_U32(facs_addr);
631 fadt.u32DSDT = RT_H2LE_U32(dsdt_addr);
632 fadt.u8IntModel = INT_MODEL_DUAL_PIC;
633 fadt.u8PreferredPMProfile = 0; /* unspecified */
634 fadt.u16SCIInt = RT_H2LE_U16(SCI_INT);
635 fadt.u32SMICmd = RT_H2LE_U32(SMI_CMD);
636 fadt.u8AcpiEnable = ACPI_ENABLE;
637 fadt.u8AcpiDisable = ACPI_DISABLE;
638 fadt.u8S4BIOSReq = 0;
639 fadt.u8PStateCnt = 0;
640 fadt.u32PM1aEVTBLK = RT_H2LE_U32(PM1a_EVT_BLK);
641 fadt.u32PM1bEVTBLK = RT_H2LE_U32(PM1b_EVT_BLK);
642 fadt.u32PM1aCTLBLK = RT_H2LE_U32(PM1a_CTL_BLK);
643 fadt.u32PM1bCTLBLK = RT_H2LE_U32(PM1b_CTL_BLK);
644 fadt.u32PM2CTLBLK = RT_H2LE_U32(PM2_CTL_BLK);
645 fadt.u32PMTMRBLK = RT_H2LE_U32(PM_TMR_BLK);
646 fadt.u32GPE0BLK = RT_H2LE_U32(GPE0_BLK);
647 fadt.u32GPE1BLK = RT_H2LE_U32(GPE1_BLK);
648 fadt.u8PM1EVTLEN = 4;
649 fadt.u8PM1CTLLEN = 2;
650 fadt.u8PM2CTLLEN = 0;
651 fadt.u8PMTMLEN = 4;
652 fadt.u8GPE0BLKLEN = GPE0_BLK_LEN;
653 fadt.u8GPE1BLKLEN = GPE1_BLK_LEN;
654 fadt.u8GPE1BASE = GPE1_BASE;
655 fadt.u8CSTCNT = 0;
656 fadt.u16PLVL2LAT = RT_H2LE_U16(P_LVL2_LAT);
657 fadt.u16PLVL3LAT = RT_H2LE_U16(P_LVL3_LAT);
658 fadt.u16FlushSize = RT_H2LE_U16(FLUSH_SIZE);
659 fadt.u16FlushStride = RT_H2LE_U16(FLUSH_STRIDE);
660 fadt.u8DutyOffset = 0;
661 fadt.u8DutyWidth = 0;
662 fadt.u8DayAlarm = 0;
663 fadt.u8MonAlarm = 0;
664 fadt.u8Century = 0;
665 fadt.u16IAPCBOOTARCH = RT_H2LE_U16(IAPC_BOOT_ARCH_LEGACY_DEV | IAPC_BOOT_ARCH_8042);
666 /** @note WBINVD is required for ACPI versions newer than 1.0 */
667 fadt.u32Flags = RT_H2LE_U32( FADT_FL_WBINVD
668 | FADT_FL_FIX_RTC
669 | FADT_FL_TMR_VAL_EXT);
670 acpiWriteGenericAddr(&fadt.ResetReg, 1, 8, 0, 1, ACPI_RESET_BLK);
671 fadt.u8ResetVal = ACPI_RESET_REG_VAL;
672 fadt.u64XFACS = RT_H2LE_U64((uint64_t)facs_addr);
673 fadt.u64XDSDT = RT_H2LE_U64((uint64_t)dsdt_addr);
674 acpiWriteGenericAddr(&fadt.X_PM1aEVTBLK, 1, 32, 0, 2, PM1a_EVT_BLK);
675 acpiWriteGenericAddr(&fadt.X_PM1bEVTBLK, 0, 0, 0, 0, PM1b_EVT_BLK);
676 acpiWriteGenericAddr(&fadt.X_PM1aCTLBLK, 1, 16, 0, 2, PM1a_CTL_BLK);
677 acpiWriteGenericAddr(&fadt.X_PM1bCTLBLK, 0, 0, 0, 0, PM1b_CTL_BLK);
678 acpiWriteGenericAddr(&fadt.X_PM2CTLBLK, 0, 0, 0, 0, PM2_CTL_BLK);
679 acpiWriteGenericAddr(&fadt.X_PMTMRBLK, 1, 32, 0, 3, PM_TMR_BLK);
680 acpiWriteGenericAddr(&fadt.X_GPE0BLK, 1, 16, 0, 1, GPE0_BLK);
681 acpiWriteGenericAddr(&fadt.X_GPE1BLK, 0, 0, 0, 0, GPE1_BLK);
682 fadt.header.u8Checksum = acpiChecksum ((uint8_t*)&fadt, sizeof(fadt));
683 acpiPhyscpy (s, addr, &fadt, sizeof(fadt));
684}
685
686/*
687 * Root System Description Table.
688 * The RSDT and XSDT tables are basically identical. The only difference is 32 vs 64 bits
689 * addresses for description headers. RSDT is for ACPI 1.0. XSDT for ACPI 2.0 and up.
690 */
691static int acpiSetupRSDT (ACPIState *s, RTGCPHYS32 addr, unsigned int nb_entries, uint32_t *addrs)
692{
693 ACPITBLRSDT *rsdt;
694 const size_t size = sizeof(ACPITBLHEADER) + nb_entries * sizeof(rsdt->u32Entry[0]);
695
696 rsdt = (ACPITBLRSDT*)RTMemAllocZ (size);
697 if (!rsdt)
698 return PDMDEV_SET_ERROR(s->pDevIns, VERR_NO_TMP_MEMORY, N_("Cannot allocate RSDT"));
699
700 acpiPrepareHeader (&rsdt->header, "RSDT", size, 1);
701 for (unsigned int i = 0; i < nb_entries; ++i)
702 {
703 rsdt->u32Entry[i] = RT_H2LE_U32(addrs[i]);
704 Log(("Setup RSDT: [%d] = %x\n", i, rsdt->u32Entry[i]));
705 }
706 rsdt->header.u8Checksum = acpiChecksum ((uint8_t*)rsdt, size);
707 acpiPhyscpy (s, addr, rsdt, size);
708 RTMemFree (rsdt);
709 return VINF_SUCCESS;
710}
711
712/* Extended System Description Table. */
713static int acpiSetupXSDT (ACPIState *s, RTGCPHYS32 addr, unsigned int nb_entries, uint32_t *addrs)
714{
715 ACPITBLXSDT *xsdt;
716 const size_t size = sizeof(ACPITBLHEADER) + nb_entries * sizeof(xsdt->u64Entry[0]);
717
718 xsdt = (ACPITBLXSDT*)RTMemAllocZ (size);
719 if (!xsdt)
720 return VERR_NO_TMP_MEMORY;
721
722 acpiPrepareHeader (&xsdt->header, "XSDT", size, 1 /* according to ACPI 3.0 specs */);
723 for (unsigned int i = 0; i < nb_entries; ++i)
724 {
725 xsdt->u64Entry[i] = RT_H2LE_U64((uint64_t)addrs[i]);
726 Log(("Setup XSDT: [%d] = %RX64\n", i, xsdt->u64Entry[i]));
727 }
728 xsdt->header.u8Checksum = acpiChecksum ((uint8_t*)xsdt, size);
729 acpiPhyscpy (s, addr, xsdt, size);
730 RTMemFree (xsdt);
731 return VINF_SUCCESS;
732}
733
734/* Root System Description Pointer (RSDP) */
735static void acpiSetupRSDP (ACPITBLRSDP *rsdp, uint32_t rsdt_addr, uint64_t xsdt_addr)
736{
737 memset(rsdp, 0, sizeof(*rsdp));
738
739 /* ACPI 1.0 part (RSDT */
740 memcpy(rsdp->au8Signature, "RSD PTR ", 8);
741 memcpy(rsdp->au8OemId, "VBOX ", 6);
742 rsdp->u8Revision = ACPI_REVISION;
743 rsdp->u32RSDT = RT_H2LE_U32(rsdt_addr);
744 rsdp->u8Checksum = acpiChecksum((uint8_t*)rsdp, RT_OFFSETOF(ACPITBLRSDP, u32Length));
745
746 /* ACPI 2.0 part (XSDT) */
747 rsdp->u32Length = RT_H2LE_U32(sizeof(ACPITBLRSDP));
748 rsdp->u64XSDT = RT_H2LE_U64(xsdt_addr);
749 rsdp->u8ExtChecksum = acpiChecksum ((uint8_t*)rsdp, sizeof(ACPITBLRSDP));
750}
751
752/* Multiple APIC Description Table. */
753/** @todo All hardcoded, should set this up based on the actual VM config!!!!! */
754/** @note APIC without IO-APIC hangs Windows Vista therefore we setup both */
755static void acpiSetupMADT (ACPIState *s, RTGCPHYS32 addr)
756{
757#ifdef VBOX_WITH_SMP_GUESTS
758 uint16_t cpus = s->cCpus;
759 AcpiTableMADT madt(cpus);
760
761 acpiPrepareHeader(madt.header_addr(), "APIC", madt.size(), 2);
762
763 *madt.u32LAPIC_addr() = RT_H2LE_U32(0xfee00000);
764 *madt.u32Flags_addr() = RT_H2LE_U32(PCAT_COMPAT);
765
766 ACPITBLLAPIC* lapic = madt.LApics_addr();
767 for (uint16_t i = 0; i < cpus; i++)
768 {
769 lapic->u8Type = 0;
770 lapic->u8Length = sizeof(ACPITBLLAPIC);
771 lapic->u8ProcId = i;
772 lapic->u8ApicId = i;
773 lapic->u32Flags = RT_H2LE_U32(LAPIC_ENABLED);
774 lapic++;
775 }
776
777 ACPITBLIOAPIC* ioapic = madt.IOApic_addr();
778
779 ioapic->u8Type = 1;
780 ioapic->u8Length = sizeof(ACPITBLIOAPIC);
781 ioapic->u8IOApicId = cpus;
782 ioapic->u8Reserved = 0;
783 ioapic->u32Address = RT_H2LE_U32(0xfec00000);
784 ioapic->u32GSIB = RT_H2LE_U32(0);
785
786 madt.header_addr()->u8Checksum = acpiChecksum (madt.data(), madt.size());
787 acpiPhyscpy (s, addr, madt.data(), madt.size());
788
789#else /* !VBOX_WITH_SMP_GUESTS */
790 ACPITBLMADT madt;
791
792 /* Don't call this function if u8UseIOApic==false! */
793 Assert(s->u8UseIOApic);
794
795 memset(&madt, 0, sizeof(madt));
796 acpiPrepareHeader(&madt.header, "APIC", sizeof(madt), 2);
797
798 madt.u32LAPIC = RT_H2LE_U32(0xfee00000);
799 madt.u32Flags = RT_H2LE_U32(PCAT_COMPAT);
800
801 madt.LApic.u8Type = 0;
802 madt.LApic.u8Length = sizeof(ACPITBLLAPIC);
803 madt.LApic.u8ProcId = 0;
804 madt.LApic.u8ApicId = 0;
805 madt.LApic.u32Flags = RT_H2LE_U32(LAPIC_ENABLED);
806
807 madt.IOApic.u8Type = 1;
808 madt.IOApic.u8Length = sizeof(ACPITBLIOAPIC);
809 madt.IOApic.u8IOApicId = 0;
810 madt.IOApic.u8Reserved = 0;
811 madt.IOApic.u32Address = RT_H2LE_U32(0xfec00000);
812 madt.IOApic.u32GSIB = RT_H2LE_U32(0);
813
814 madt.header.u8Checksum = acpiChecksum ((uint8_t*)&madt, sizeof(madt));
815 acpiPhyscpy (s, addr, &madt, sizeof(madt));
816#endif /* !VBOX_WITH_SMP_GUESTS */
817}
818
819/* SCI IRQ */
820DECLINLINE(void) acpiSetIrq (ACPIState *s, int level)
821{
822 if (s->pm1a_ctl & SCI_EN)
823 PDMDevHlpPCISetIrq (s->pDevIns, -1, level);
824}
825
826DECLINLINE(uint32_t) pm1a_pure_en (uint32_t en)
827{
828 return en & ~(RSR_EN | IGN_EN);
829}
830
831DECLINLINE(uint32_t) pm1a_pure_sts (uint32_t sts)
832{
833 return sts & ~(RSR_STS | IGN_STS);
834}
835
836DECLINLINE(int) pm1a_level (ACPIState *s)
837{
838 return (pm1a_pure_en (s->pm1a_en) & pm1a_pure_sts (s->pm1a_sts)) != 0;
839}
840
841DECLINLINE(int) gpe0_level (ACPIState *s)
842{
843 return (s->gpe0_en & s->gpe0_sts) != 0;
844}
845
846static void update_pm1a (ACPIState *s, uint32_t sts, uint32_t en)
847{
848 int old_level, new_level;
849
850 if (gpe0_level (s))
851 return;
852
853 old_level = pm1a_level (s);
854 new_level = (pm1a_pure_en (en) & pm1a_pure_sts (sts)) != 0;
855
856 s->pm1a_en = en;
857 s->pm1a_sts = sts;
858
859 if (new_level != old_level)
860 acpiSetIrq (s, new_level);
861}
862
863static void update_gpe0 (ACPIState *s, uint32_t sts, uint32_t en)
864{
865 int old_level, new_level;
866
867 if (pm1a_level (s))
868 return;
869
870 old_level = (s->gpe0_en & s->gpe0_sts) != 0;
871 new_level = (en & sts) != 0;
872
873 s->gpe0_en = en;
874 s->gpe0_sts = sts;
875
876 if (new_level != old_level)
877 acpiSetIrq (s, new_level);
878}
879
880static int acpiPowerDown (ACPIState *s)
881{
882 int rc = PDMDevHlpVMPowerOff(s->pDevIns);
883 if (RT_FAILURE (rc))
884 AssertMsgFailed (("Could not power down the VM. rc = %Rrc\n", rc));
885 return rc;
886}
887
888/** Converts a ACPI port interface pointer to an ACPI state pointer. */
889#define IACPIPORT_2_ACPISTATE(pInterface) ( (ACPIState*)((uintptr_t)pInterface - RT_OFFSETOF(ACPIState, IACPIPort)) )
890
891/**
892 * Send an ACPI power off event.
893 *
894 * @returns VBox status code
895 * @param pInterface Pointer to the interface structure containing the called function pointer.
896 */
897static DECLCALLBACK(int) acpiPowerButtonPress(PPDMIACPIPORT pInterface)
898{
899 ACPIState *s = IACPIPORT_2_ACPISTATE(pInterface);
900 s->fPowerButtonHandled = false;
901 update_pm1a (s, s->pm1a_sts | PWRBTN_STS, s->pm1a_en);
902 return VINF_SUCCESS;
903}
904
905/**
906 * Check if the ACPI power button event was handled.
907 *
908 * @returns VBox status code
909 * @param pInterface Pointer to the interface structure containing the called function pointer.
910 * @param pfHandled Return true if the power button event was handled by the guest.
911 */
912static DECLCALLBACK(int) acpiGetPowerButtonHandled(PPDMIACPIPORT pInterface, bool *pfHandled)
913{
914 ACPIState *s = IACPIPORT_2_ACPISTATE(pInterface);
915 *pfHandled = s->fPowerButtonHandled;
916 return VINF_SUCCESS;
917}
918
919/**
920 * Check if the Guest entered into G0 (working) or G1 (sleeping).
921 *
922 * @returns VBox status code
923 * @param pInterface Pointer to the interface structure containing the called function pointer.
924 * @param pfEntered Return true if the guest entered the ACPI mode.
925 */
926static DECLCALLBACK(int) acpiGetGuestEnteredACPIMode(PPDMIACPIPORT pInterface, bool *pfEntered)
927{
928 ACPIState *s = IACPIPORT_2_ACPISTATE(pInterface);
929 *pfEntered = (s->pm1a_ctl & SCI_EN) != 0;
930 return VINF_SUCCESS;
931}
932
933/**
934 * Send an ACPI sleep button event.
935 *
936 * @returns VBox status code
937 * @param pInterface Pointer to the interface structure containing the called function pointer.
938 */
939static DECLCALLBACK(int) acpiSleepButtonPress(PPDMIACPIPORT pInterface)
940{
941 ACPIState *s = IACPIPORT_2_ACPISTATE(pInterface);
942 update_pm1a (s, s->pm1a_sts | SLPBTN_STS, s->pm1a_en);
943 return VINF_SUCCESS;
944}
945
946/* PM1a_EVT_BLK enable */
947static uint32_t acpiPm1aEnReadw (ACPIState *s, uint32_t addr)
948{
949 uint16_t val = s->pm1a_en;
950 Log (("acpi: acpiPm1aEnReadw -> %#x\n", val));
951 return val;
952}
953
954static void acpiPM1aEnWritew (ACPIState *s, uint32_t addr, uint32_t val)
955{
956 Log (("acpi: acpiPM1aEnWritew <- %#x (%#x)\n", val, val & ~(RSR_EN | IGN_EN)));
957 val &= ~(RSR_EN | IGN_EN);
958 update_pm1a (s, s->pm1a_sts, val);
959}
960
961/* PM1a_EVT_BLK status */
962static uint32_t acpiPm1aStsReadw (ACPIState *s, uint32_t addr)
963{
964 uint16_t val = s->pm1a_sts;
965 Log (("acpi: acpiPm1aStsReadw -> %#x\n", val));
966 return val;
967}
968
969static void acpiPM1aStsWritew (ACPIState *s, uint32_t addr, uint32_t val)
970{
971 Log (("acpi: acpiPM1aStsWritew <- %#x (%#x)\n", val, val & ~(RSR_STS | IGN_STS)));
972 if (val & PWRBTN_STS)
973 s->fPowerButtonHandled = true; /* Remember that the guest handled the last power button event */
974 val = s->pm1a_sts & ~(val & ~(RSR_STS | IGN_STS));
975 update_pm1a (s, val, s->pm1a_en);
976}
977
978/* PM1a_CTL_BLK */
979static uint32_t acpiPm1aCtlReadw (ACPIState *s, uint32_t addr)
980{
981 uint16_t val = s->pm1a_ctl;
982 Log (("acpi: acpiPm1aCtlReadw -> %#x\n", val));
983 return val;
984}
985
986static int acpiPM1aCtlWritew (ACPIState *s, uint32_t addr, uint32_t val)
987{
988 uint32_t uSleepState;
989
990 Log (("acpi: acpiPM1aCtlWritew <- %#x (%#x)\n", val, val & ~(RSR_CNT | IGN_CNT)));
991 s->pm1a_ctl = val & ~(RSR_CNT | IGN_CNT);
992
993 uSleepState = (s->pm1a_ctl >> SLP_TYPx_SHIFT) & SLP_TYPx_MASK;
994 if (uSleepState != s->uSleepState)
995 {
996 s->uSleepState = uSleepState;
997 switch (uSleepState)
998 {
999 case 0x00: /* S0 */
1000 break;
1001 case 0x05: /* S5 */
1002 LogRel (("Entering S5 (power down)\n"));
1003 return acpiPowerDown (s);
1004 default:
1005 AssertMsgFailed (("Unknown sleep state %#x\n", uSleepState));
1006 break;
1007 }
1008 }
1009 return VINF_SUCCESS;
1010}
1011
1012/* GPE0_BLK */
1013static uint32_t acpiGpe0EnReadb (ACPIState *s, uint32_t addr)
1014{
1015 uint8_t val = s->gpe0_en;
1016 Log (("acpi: acpiGpe0EnReadl -> %#x\n", val));
1017 return val;
1018}
1019
1020static void acpiGpe0EnWriteb (ACPIState *s, uint32_t addr, uint32_t val)
1021{
1022 Log (("acpi: acpiGpe0EnWritel <- %#x\n", val));
1023 update_gpe0 (s, s->gpe0_sts, val);
1024}
1025
1026static uint32_t acpiGpe0StsReadb (ACPIState *s, uint32_t addr)
1027{
1028 uint8_t val = s->gpe0_sts;
1029 Log (("acpi: acpiGpe0StsReadl -> %#x\n", val));
1030 return val;
1031}
1032
1033static void acpiGpe0StsWriteb (ACPIState *s, uint32_t addr, uint32_t val)
1034{
1035 val = s->gpe0_sts & ~val;
1036 update_gpe0 (s, val, s->gpe0_en);
1037 Log (("acpi: acpiGpe0StsWritel <- %#x\n", val));
1038}
1039
1040static int acpiResetWriteU8(ACPIState *s, uint32_t addr, uint32_t val)
1041{
1042 int rc = VINF_SUCCESS;
1043
1044 Log(("ACPI: acpiResetWriteU8: %x %x\n", addr, val));
1045 if (val == ACPI_RESET_REG_VAL)
1046 {
1047# ifndef IN_RING3
1048 rc = VINF_IOM_HC_IOPORT_WRITE;
1049# else /* IN_RING3 */
1050 rc = PDMDevHlpVMReset(s->pDevIns);
1051# endif /* !IN_RING3 */
1052 }
1053 return rc;
1054}
1055
1056/* SMI */
1057static void acpiSmiWriteU8 (ACPIState *s, uint32_t addr, uint32_t val)
1058{
1059 Log (("acpi: acpiSmiWriteU8 %#x\n", val));
1060 if (val == ACPI_ENABLE)
1061 s->pm1a_ctl |= SCI_EN;
1062 else if (val == ACPI_DISABLE)
1063 s->pm1a_ctl &= ~SCI_EN;
1064 else
1065 Log (("acpi: acpiSmiWriteU8 %#x <- unknown value\n", val));
1066}
1067
1068static uint32_t find_rsdp_space (void)
1069{
1070 return 0xe0000;
1071}
1072
1073static void acpiPMTimerReset (ACPIState *s)
1074{
1075 uint64_t interval, freq;
1076
1077 freq = TMTimerGetFreq (s->CTX_SUFF(ts));
1078 interval = ASMMultU64ByU32DivByU32 (0xffffffff, freq, PM_TMR_FREQ);
1079 Log (("interval = %RU64\n", interval));
1080 TMTimerSet (s->CTX_SUFF(ts), TMTimerGet (s->CTX_SUFF(ts)) + interval);
1081}
1082
1083static DECLCALLBACK(void) acpiTimer (PPDMDEVINS pDevIns, PTMTIMER pTimer)
1084{
1085 ACPIState *s = PDMINS_2_DATA (pDevIns, ACPIState *);
1086
1087 Log (("acpi: pm timer sts %#x (%d), en %#x (%d)\n",
1088 s->pm1a_sts, (s->pm1a_sts & TMR_STS) != 0,
1089 s->pm1a_en, (s->pm1a_en & TMR_EN) != 0));
1090
1091 update_pm1a (s, s->pm1a_sts | TMR_STS, s->pm1a_en);
1092 acpiPMTimerReset (s);
1093}
1094
1095/**
1096 * _BST method.
1097 */
1098static void acpiFetchBatteryStatus (ACPIState *s)
1099{
1100 uint32_t *p = s->au8BatteryInfo;
1101 bool fPresent; /* battery present? */
1102 PDMACPIBATCAPACITY hostRemainingCapacity; /* 0..100 */
1103 PDMACPIBATSTATE hostBatteryState; /* bitfield */
1104 uint32_t hostPresentRate; /* 0..1000 */
1105 int rc;
1106
1107 if (!s->pDrv)
1108 return;
1109 rc = s->pDrv->pfnQueryBatteryStatus (s->pDrv, &fPresent, &hostRemainingCapacity,
1110 &hostBatteryState, &hostPresentRate);
1111 AssertRC (rc);
1112
1113 /* default values */
1114 p[BAT_STATUS_STATE] = hostBatteryState;
1115 p[BAT_STATUS_PRESENT_RATE] = hostPresentRate == ~0U ? 0xFFFFFFFF
1116 : hostPresentRate * 50; /* mW */
1117 p[BAT_STATUS_REMAINING_CAPACITY] = 50000; /* mWh */
1118 p[BAT_STATUS_PRESENT_VOLTAGE] = 10000; /* mV */
1119
1120 /* did we get a valid battery state? */
1121 if (hostRemainingCapacity != PDM_ACPI_BAT_CAPACITY_UNKNOWN)
1122 p[BAT_STATUS_REMAINING_CAPACITY] = hostRemainingCapacity * 500; /* mWh */
1123 if (hostBatteryState == PDM_ACPI_BAT_STATE_CHARGED)
1124 p[BAT_STATUS_PRESENT_RATE] = 0; /* mV */
1125}
1126
1127/**
1128 * _BIF method.
1129 */
1130static void acpiFetchBatteryInfo (ACPIState *s)
1131{
1132 uint32_t *p = s->au8BatteryInfo;
1133
1134 p[BAT_INFO_UNITS] = 0; /* mWh */
1135 p[BAT_INFO_DESIGN_CAPACITY] = 50000; /* mWh */
1136 p[BAT_INFO_LAST_FULL_CHARGE_CAPACITY] = 50000; /* mWh */
1137 p[BAT_INFO_TECHNOLOGY] = BAT_TECH_PRIMARY;
1138 p[BAT_INFO_DESIGN_VOLTAGE] = 10000; /* mV */
1139 p[BAT_INFO_DESIGN_CAPACITY_OF_WARNING] = 100; /* mWh */
1140 p[BAT_INFO_DESIGN_CAPACITY_OF_LOW] = 50; /* mWh */
1141 p[BAT_INFO_CAPACITY_GRANULARITY_1] = 1; /* mWh */
1142 p[BAT_INFO_CAPACITY_GRANULARITY_2] = 1; /* mWh */
1143}
1144
1145/**
1146 * _STA method.
1147 */
1148static uint32_t acpiGetBatteryDeviceStatus (ACPIState *s)
1149{
1150 bool fPresent; /* battery present? */
1151 PDMACPIBATCAPACITY hostRemainingCapacity; /* 0..100 */
1152 PDMACPIBATSTATE hostBatteryState; /* bitfield */
1153 uint32_t hostPresentRate; /* 0..1000 */
1154 int rc;
1155
1156 if (!s->pDrv)
1157 return 0;
1158 rc = s->pDrv->pfnQueryBatteryStatus (s->pDrv, &fPresent, &hostRemainingCapacity,
1159 &hostBatteryState, &hostPresentRate);
1160 AssertRC (rc);
1161
1162 return fPresent
1163 ? STA_DEVICE_PRESENT_MASK /* present */
1164 | STA_DEVICE_ENABLED_MASK /* enabled and decodes its resources */
1165 | STA_DEVICE_SHOW_IN_UI_MASK /* should be shown in UI */
1166 | STA_DEVICE_FUNCTIONING_PROPERLY_MASK /* functioning properly */
1167 | STA_BATTERY_PRESENT_MASK /* battery is present */
1168 : 0; /* device not present */
1169}
1170
1171static uint32_t acpiGetPowerSource (ACPIState *s)
1172{
1173 PDMACPIPOWERSOURCE ps;
1174
1175 /* query the current power source from the host driver */
1176 if (!s->pDrv)
1177 return AC_ONLINE;
1178 int rc = s->pDrv->pfnQueryPowerSource (s->pDrv, &ps);
1179 AssertRC (rc);
1180 return ps == PDM_ACPI_POWER_SOURCE_BATTERY ? AC_OFFLINE : AC_ONLINE;
1181}
1182
1183IO_WRITE_PROTO (acpiBatIndexWrite)
1184{
1185 ACPIState *s = (ACPIState *)pvUser;
1186
1187 switch (cb)
1188 {
1189 case 4:
1190 u32 >>= s->u8IndexShift;
1191 /* see comment at the declaration of u8IndexShift */
1192 if (s->u8IndexShift == 0 && u32 == (BAT_DEVICE_STATUS << 2))
1193 {
1194 s->u8IndexShift = 2;
1195 u32 >>= 2;
1196 }
1197 Assert (u32 < BAT_INDEX_LAST);
1198 s->uBatteryIndex = u32;
1199 break;
1200 default:
1201 AssertMsgFailed(("Port=%#x cb=%d u32=%#x\n", Port, cb, u32));
1202 break;
1203 }
1204 return VINF_SUCCESS;
1205}
1206
1207IO_READ_PROTO (acpiBatDataRead)
1208{
1209 ACPIState *s = (ACPIState *)pvUser;
1210
1211 switch (cb)
1212 {
1213 case 4:
1214 switch (s->uBatteryIndex)
1215 {
1216 case BAT_STATUS_STATE:
1217 acpiFetchBatteryStatus(s);
1218 case BAT_STATUS_PRESENT_RATE:
1219 case BAT_STATUS_REMAINING_CAPACITY:
1220 case BAT_STATUS_PRESENT_VOLTAGE:
1221 *pu32 = s->au8BatteryInfo[s->uBatteryIndex];
1222 break;
1223
1224 case BAT_INFO_UNITS:
1225 acpiFetchBatteryInfo(s);
1226 case BAT_INFO_DESIGN_CAPACITY:
1227 case BAT_INFO_LAST_FULL_CHARGE_CAPACITY:
1228 case BAT_INFO_TECHNOLOGY:
1229 case BAT_INFO_DESIGN_VOLTAGE:
1230 case BAT_INFO_DESIGN_CAPACITY_OF_WARNING:
1231 case BAT_INFO_DESIGN_CAPACITY_OF_LOW:
1232 case BAT_INFO_CAPACITY_GRANULARITY_1:
1233 case BAT_INFO_CAPACITY_GRANULARITY_2:
1234 *pu32 = s->au8BatteryInfo[s->uBatteryIndex];
1235 break;
1236
1237 case BAT_DEVICE_STATUS:
1238 *pu32 = acpiGetBatteryDeviceStatus(s);
1239 break;
1240
1241 case BAT_POWER_SOURCE:
1242 *pu32 = acpiGetPowerSource(s);
1243 break;
1244
1245 default:
1246 AssertMsgFailed (("Invalid battery index %d\n", s->uBatteryIndex));
1247 break;
1248 }
1249 break;
1250 default:
1251 return VERR_IOM_IOPORT_UNUSED;
1252 }
1253 return VINF_SUCCESS;
1254}
1255
1256IO_WRITE_PROTO (acpiSysInfoIndexWrite)
1257{
1258 ACPIState *s = (ACPIState *)pvUser;
1259
1260 Log(("system_index = %d, %d\n", u32, u32 >> 2));
1261 switch (cb) {
1262 case 4:
1263 if (u32 == SYSTEM_INFO_INDEX_VALID || u32 == SYSTEM_INFO_INDEX_INVALID)
1264 s->uSystemInfoIndex = u32;
1265 else
1266 {
1267 /* see comment at the declaration of u8IndexShift */
1268 if (s->u8IndexShift == 0)
1269 {
1270 uint32_t u32Index;
1271 for (u32Index = 0; u32Index < SYSTEM_INFO_INDEX_LAST; u32Index++)
1272 {
1273 if (u32 == (u32Index << 2))
1274 {
1275 s->u8IndexShift = 2;
1276 break;
1277 }
1278 }
1279 }
1280 u32 >>= s->u8IndexShift;
1281 Assert (u32 < SYSTEM_INFO_INDEX_LAST);
1282 s->uSystemInfoIndex = u32;
1283 }
1284 break;
1285
1286 default:
1287 AssertMsgFailed(("Port=%#x cb=%d u32=%#x\n", Port, cb, u32));
1288 break;
1289 }
1290 return VINF_SUCCESS;
1291}
1292
1293IO_READ_PROTO (acpiSysInfoDataRead)
1294{
1295 ACPIState *s = (ACPIState *)pvUser;
1296
1297 switch (cb)
1298 {
1299 case 4:
1300 switch (s->uSystemInfoIndex)
1301 {
1302 case SYSTEM_INFO_INDEX_MEMORY_LENGTH:
1303 *pu32 = s->u64RamSize;
1304 break;
1305
1306 case SYSTEM_INFO_INDEX_USE_IOAPIC:
1307 *pu32 = s->u8UseIOApic;
1308 break;
1309
1310 case SYSTEM_INFO_INDEX_HPET_STATUS:
1311 *pu32 = s->u8UseHpet ? 0xf : 0;
1312 break;
1313
1314 case SYSTEM_INFO_INDEX_SMC_STATUS:
1315 *pu32 = s->u8UseSmc ? 0xb : 0; /* No need to show in UI */
1316 break;
1317
1318 case SYSTEM_INFO_INDEX_FDC_STATUS:
1319 *pu32 = s->u8UseFdc ? 0xf : 0;
1320 break;
1321
1322 /* Solaris 9 tries to read from this index */
1323 case SYSTEM_INFO_INDEX_INVALID:
1324 *pu32 = 0;
1325 break;
1326
1327 default:
1328 AssertMsgFailed (("Invalid system info index %d\n", s->uSystemInfoIndex));
1329 break;
1330 }
1331 break;
1332
1333 default:
1334 return VERR_IOM_IOPORT_UNUSED;
1335 }
1336
1337 Log(("index %d val %d\n", s->uSystemInfoIndex, *pu32));
1338 return VINF_SUCCESS;
1339}
1340
1341IO_WRITE_PROTO (acpiSysInfoDataWrite)
1342{
1343 ACPIState *s = (ACPIState *)pvUser;
1344
1345 Log(("addr=%#x cb=%d u32=%#x si=%#x\n", Port, cb, u32, s->uSystemInfoIndex));
1346
1347 if (cb == 4 && u32 == 0xbadc0de)
1348 {
1349 switch (s->uSystemInfoIndex)
1350 {
1351 case SYSTEM_INFO_INDEX_INVALID:
1352 s->u8IndexShift = 0;
1353 break;
1354
1355 case SYSTEM_INFO_INDEX_VALID:
1356 s->u8IndexShift = 2;
1357 break;
1358
1359 default:
1360 AssertMsgFailed(("Port=%#x cb=%d u32=%#x system_index=%#x\n",
1361 Port, cb, u32, s->uSystemInfoIndex));
1362 break;
1363 }
1364 }
1365 else
1366 AssertMsgFailed(("Port=%#x cb=%d u32=%#x\n", Port, cb, u32));
1367 return VINF_SUCCESS;
1368}
1369
1370/* IO Helpers */
1371IO_READ_PROTO (acpiPm1aEnRead)
1372{
1373 switch (cb)
1374 {
1375 case 2:
1376 *pu32 = acpiPm1aEnReadw ((ACPIState*)pvUser, Port);
1377 break;
1378 default:
1379 return VERR_IOM_IOPORT_UNUSED;
1380 }
1381 return VINF_SUCCESS;
1382}
1383
1384IO_READ_PROTO (acpiPm1aStsRead)
1385{
1386 switch (cb)
1387 {
1388 case 2:
1389 *pu32 = acpiPm1aStsReadw ((ACPIState*)pvUser, Port);
1390 break;
1391 default:
1392 return VERR_IOM_IOPORT_UNUSED;
1393 }
1394 return VINF_SUCCESS;
1395}
1396
1397IO_READ_PROTO (acpiPm1aCtlRead)
1398{
1399 switch (cb)
1400 {
1401 case 2:
1402 *pu32 = acpiPm1aCtlReadw ((ACPIState*)pvUser, Port);
1403 break;
1404 default:
1405 return VERR_IOM_IOPORT_UNUSED;
1406 }
1407 return VINF_SUCCESS;
1408}
1409
1410IO_WRITE_PROTO (acpiPM1aEnWrite)
1411{
1412 switch (cb)
1413 {
1414 case 2:
1415 acpiPM1aEnWritew ((ACPIState*)pvUser, Port, u32);
1416 break;
1417 default:
1418 AssertMsgFailed(("Port=%#x cb=%d u32=%#x\n", Port, cb, u32));
1419 break;
1420 }
1421 return VINF_SUCCESS;
1422}
1423
1424IO_WRITE_PROTO (acpiPM1aStsWrite)
1425{
1426 switch (cb)
1427 {
1428 case 2:
1429 acpiPM1aStsWritew ((ACPIState*)pvUser, Port, u32);
1430 break;
1431 default:
1432 AssertMsgFailed(("Port=%#x cb=%d u32=%#x\n", Port, cb, u32));
1433 break;
1434 }
1435 return VINF_SUCCESS;
1436}
1437
1438IO_WRITE_PROTO (acpiPM1aCtlWrite)
1439{
1440 switch (cb)
1441 {
1442 case 2:
1443 return acpiPM1aCtlWritew ((ACPIState*)pvUser, Port, u32);
1444 default:
1445 AssertMsgFailed(("Port=%#x cb=%d u32=%#x\n", Port, cb, u32));
1446 break;
1447 }
1448 return VINF_SUCCESS;
1449}
1450
1451#endif /* IN_RING3 */
1452
1453/**
1454 * PMTMR readable from host/guest.
1455 */
1456IO_READ_PROTO (acpiPMTmrRead)
1457{
1458 if (cb == 4)
1459 {
1460 ACPIState *s = PDMINS_2_DATA (pDevIns, ACPIState *);
1461 int64_t now = TMTimerGet (s->CTX_SUFF(ts));
1462 int64_t elapsed = now - s->pm_timer_initial;
1463
1464 *pu32 = ASMMultU64ByU32DivByU32 (elapsed, PM_TMR_FREQ, TMTimerGetFreq (s->CTX_SUFF(ts)));
1465 Log (("acpi: acpiPMTmrRead -> %#x\n", *pu32));
1466 return VINF_SUCCESS;
1467 }
1468 return VERR_IOM_IOPORT_UNUSED;
1469}
1470
1471#ifdef IN_RING3
1472
1473IO_READ_PROTO (acpiGpe0StsRead)
1474{
1475 switch (cb)
1476 {
1477 case 1:
1478 *pu32 = acpiGpe0StsReadb ((ACPIState*)pvUser, Port);
1479 break;
1480 default:
1481 return VERR_IOM_IOPORT_UNUSED;
1482 }
1483 return VINF_SUCCESS;
1484}
1485
1486IO_READ_PROTO (acpiGpe0EnRead)
1487{
1488 switch (cb)
1489 {
1490 case 1:
1491 *pu32 = acpiGpe0EnReadb ((ACPIState*)pvUser, Port);
1492 break;
1493 default:
1494 return VERR_IOM_IOPORT_UNUSED;
1495 }
1496 return VINF_SUCCESS;
1497}
1498
1499IO_WRITE_PROTO (acpiGpe0StsWrite)
1500{
1501 switch (cb)
1502 {
1503 case 1:
1504 acpiGpe0StsWriteb ((ACPIState*)pvUser, Port, u32);
1505 break;
1506 default:
1507 AssertMsgFailed(("Port=%#x cb=%d u32=%#x\n", Port, cb, u32));
1508 break;
1509 }
1510 return VINF_SUCCESS;
1511}
1512
1513IO_WRITE_PROTO (acpiGpe0EnWrite)
1514{
1515 switch (cb)
1516 {
1517 case 1:
1518 acpiGpe0EnWriteb ((ACPIState*)pvUser, Port, u32);
1519 break;
1520 default:
1521 AssertMsgFailed(("Port=%#x cb=%d u32=%#x\n", Port, cb, u32));
1522 break;
1523 }
1524 return VINF_SUCCESS;
1525}
1526
1527IO_WRITE_PROTO (acpiSmiWrite)
1528{
1529 switch (cb)
1530 {
1531 case 1:
1532 acpiSmiWriteU8 ((ACPIState*)pvUser, Port, u32);
1533 break;
1534 default:
1535 AssertMsgFailed(("Port=%#x cb=%d u32=%#x\n", Port, cb, u32));
1536 break;
1537 }
1538 return VINF_SUCCESS;
1539}
1540
1541IO_WRITE_PROTO (acpiResetWrite)
1542{
1543 switch (cb)
1544 {
1545 case 1:
1546 return acpiResetWriteU8 ((ACPIState*)pvUser, Port, u32);
1547 default:
1548 AssertMsgFailed(("Port=%#x cb=%d u32=%#x\n", Port, cb, u32));
1549 break;
1550 }
1551 return VINF_SUCCESS;
1552}
1553
1554#ifdef DEBUG_ACPI
1555
1556IO_WRITE_PROTO (acpiDhexWrite)
1557{
1558 switch (cb)
1559 {
1560 case 1:
1561 Log (("%#x\n", u32 & 0xff));
1562 break;
1563 case 2:
1564 Log (("%#6x\n", u32 & 0xffff));
1565 case 4:
1566 Log (("%#10x\n", u32));
1567 break;
1568 default:
1569 AssertMsgFailed(("Port=%#x cb=%d u32=%#x\n", Port, cb, u32));
1570 break;
1571 }
1572 return VINF_SUCCESS;
1573}
1574
1575IO_WRITE_PROTO (acpiDchrWrite)
1576{
1577 switch (cb)
1578 {
1579 case 1:
1580 Log (("%c", u32 & 0xff));
1581 break;
1582 default:
1583 AssertMsgFailed(("Port=%#x cb=%d u32=%#x\n", Port, cb, u32));
1584 break;
1585 }
1586 return VINF_SUCCESS;
1587}
1588
1589#endif /* DEBUG_ACPI */
1590
1591
1592/**
1593 * Saved state structure description.
1594 */
1595static const SSMFIELD g_AcpiSavedStateFields[] =
1596{
1597 SSMFIELD_ENTRY (ACPIState, pm1a_en),
1598 SSMFIELD_ENTRY (ACPIState, pm1a_sts),
1599 SSMFIELD_ENTRY (ACPIState, pm1a_ctl),
1600 SSMFIELD_ENTRY (ACPIState, pm_timer_initial),
1601 SSMFIELD_ENTRY (ACPIState, gpe0_en),
1602 SSMFIELD_ENTRY (ACPIState, gpe0_sts),
1603 SSMFIELD_ENTRY (ACPIState, uBatteryIndex),
1604 SSMFIELD_ENTRY (ACPIState, uSystemInfoIndex),
1605 SSMFIELD_ENTRY (ACPIState, u64RamSize),
1606 SSMFIELD_ENTRY (ACPIState, u8IndexShift),
1607 SSMFIELD_ENTRY (ACPIState, u8UseIOApic),
1608 SSMFIELD_ENTRY (ACPIState, uSleepState),
1609 SSMFIELD_ENTRY_TERM ()
1610};
1611
1612static DECLCALLBACK(int) acpi_save_state (PPDMDEVINS pDevIns, PSSMHANDLE pSSMHandle)
1613{
1614 ACPIState *s = PDMINS_2_DATA (pDevIns, ACPIState *);
1615 return SSMR3PutStruct (pSSMHandle, s, &g_AcpiSavedStateFields[0]);
1616}
1617
1618static DECLCALLBACK(int) acpi_load_state (PPDMDEVINS pDevIns, PSSMHANDLE pSSMHandle,
1619 uint32_t u32Version)
1620{
1621 ACPIState *s = PDMINS_2_DATA (pDevIns, ACPIState *);
1622 int rc;
1623
1624 if (u32Version != 4)
1625 return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
1626
1627 rc = SSMR3GetStruct (pSSMHandle, s, &g_AcpiSavedStateFields[0]);
1628 if (RT_SUCCESS (rc))
1629 {
1630 acpiFetchBatteryStatus (s);
1631 acpiFetchBatteryInfo (s);
1632 acpiPMTimerReset (s);
1633 }
1634 return rc;
1635}
1636
1637/**
1638 * Queries an interface to the driver.
1639 *
1640 * @returns Pointer to interface.
1641 * @returns NULL if the interface was not supported by the driver.
1642 * @param pInterface Pointer to this interface structure.
1643 * @param enmInterface The requested interface identification.
1644 * @thread Any thread.
1645 */
1646static DECLCALLBACK(void *) acpiQueryInterface(PPDMIBASE pInterface, PDMINTERFACE enmInterface)
1647{
1648 ACPIState *pThis = (ACPIState*)((uintptr_t)pInterface - RT_OFFSETOF(ACPIState, IBase));
1649 switch (enmInterface)
1650 {
1651 case PDMINTERFACE_BASE:
1652 return &pThis->IBase;
1653 case PDMINTERFACE_ACPI_PORT:
1654 return &pThis->IACPIPort;
1655 default:
1656 return NULL;
1657 }
1658}
1659
1660/**
1661 * Create the ACPI tables.
1662 */
1663static int acpiPlantTables (ACPIState *s)
1664{
1665 int rc;
1666 RTGCPHYS32 rsdt_addr, xsdt_addr, fadt_addr, facs_addr, dsdt_addr, last_addr, apic_addr = 0;
1667 uint32_t addend = 0;
1668 RTGCPHYS32 rsdt_addrs[4];
1669 uint32_t cAddr;
1670 size_t rsdt_tbl_len = sizeof(ACPITBLHEADER);
1671 size_t xsdt_tbl_len = sizeof(ACPITBLHEADER);
1672
1673 cAddr = 1; /* FADT */
1674 if (s->u8UseIOApic)
1675 cAddr++; /* MADT */
1676
1677 rsdt_tbl_len += cAddr*4; /* each entry: 32 bits phys. address. */
1678 xsdt_tbl_len += cAddr*8; /* each entry: 64 bits phys. address. */
1679
1680 rc = CFGMR3QueryU64 (s->pDevIns->pCfgHandle, "RamSize", &s->u64RamSize);
1681 if (RT_FAILURE (rc))
1682 return PDMDEV_SET_ERROR(s->pDevIns, rc,
1683 N_("Configuration error: Querying "
1684 "\"RamSize\" as integer failed"));
1685
1686 if (s->u64RamSize > (0xffffffff - 0x10000))
1687 return PDMDEV_SET_ERROR(s->pDevIns, VERR_OUT_OF_RANGE,
1688 N_("Configuration error: Invalid \"RamSize\", maximum allowed "
1689 "value is 4095MB"));
1690 rsdt_addr = 0;
1691 xsdt_addr = RT_ALIGN_32 (rsdt_addr + rsdt_tbl_len, 16);
1692 fadt_addr = RT_ALIGN_32 (xsdt_addr + xsdt_tbl_len, 16);
1693 facs_addr = RT_ALIGN_32 (fadt_addr + sizeof(ACPITBLFADT), 16);
1694 if (s->u8UseIOApic)
1695 {
1696 apic_addr = RT_ALIGN_32 (facs_addr + sizeof(ACPITBLFACS), 16);
1697#ifdef VBOX_WITH_SMP_GUESTS
1698 /**
1699 * @todo nike: maybe some refactoring needed to compute tables layout,
1700 * but as this code is executed only once it doesn't make sense to optimize much
1701 */
1702 dsdt_addr = RT_ALIGN_32 (apic_addr + AcpiTableMADT::sizeFor(s), 16);
1703#else
1704 dsdt_addr = RT_ALIGN_32 (apic_addr + sizeof(ACPITBLMADT), 16);
1705#endif
1706 }
1707 else
1708 {
1709 dsdt_addr = RT_ALIGN_32 (facs_addr + sizeof(ACPITBLFACS), 16);
1710 }
1711
1712 last_addr = RT_ALIGN_32 (dsdt_addr + sizeof(AmlCode), 16);
1713 if (last_addr > 0x10000)
1714 return PDMDEV_SET_ERROR(s->pDevIns, VERR_TOO_MUCH_DATA,
1715 N_("Error: ACPI tables > 64KB"));
1716
1717 Log(("RSDP 0x%08X\n", find_rsdp_space()));
1718 addend = (uint32_t) s->u64RamSize - 0x10000;
1719 Log(("RSDT 0x%08X XSDT 0x%08X\n", rsdt_addr + addend, xsdt_addr + addend));
1720 Log(("FACS 0x%08X FADT 0x%08X\n", facs_addr + addend, fadt_addr + addend));
1721 Log(("DSDT 0x%08X\n", dsdt_addr + addend));
1722 acpiSetupRSDP ((ACPITBLRSDP*)s->au8RSDPPage, rsdt_addr + addend, xsdt_addr + addend);
1723 acpiSetupDSDT (s, dsdt_addr + addend);
1724 acpiSetupFACS (s, facs_addr + addend);
1725 acpiSetupFADT (s, fadt_addr + addend, facs_addr + addend, dsdt_addr + addend);
1726
1727 rsdt_addrs[0] = fadt_addr + addend;
1728 if (s->u8UseIOApic)
1729 {
1730 acpiSetupMADT (s, apic_addr + addend);
1731 rsdt_addrs[1] = apic_addr + addend;
1732 }
1733
1734 rc = acpiSetupRSDT (s, rsdt_addr + addend, cAddr, rsdt_addrs);
1735 if (RT_FAILURE(rc))
1736 return rc;
1737 return acpiSetupXSDT (s, xsdt_addr + addend, cAddr, rsdt_addrs);
1738}
1739
1740/**
1741 * Construct a device instance for a VM.
1742 *
1743 * @returns VBox status.
1744 * @param pDevIns The device instance data.
1745 * If the registration structure is needed, pDevIns->pDevReg points to it.
1746 * @param iInstance Instance number. Use this to figure out which registers and such to use.
1747 * The device number is also found in pDevIns->iInstance, but since it's
1748 * likely to be freqently used PDM passes it as parameter.
1749 * @param pCfgHandle Configuration node handle for the device. Use this to obtain the configuration
1750 * of the device instance. It's also found in pDevIns->pCfgHandle, but like
1751 * iInstance it's expected to be used a bit in this function.
1752 */
1753static DECLCALLBACK(int) acpiConstruct (PPDMDEVINS pDevIns, int iInstance, PCFGMNODE pCfgHandle)
1754{
1755 int rc;
1756 ACPIState *s = PDMINS_2_DATA (pDevIns, ACPIState *);
1757 uint32_t rsdp_addr;
1758 PCIDevice *dev;
1759 bool fGCEnabled;
1760 bool fR0Enabled;
1761
1762 /* Validate and read the configuration. */
1763 if (!CFGMR3AreValuesValid (pCfgHandle,
1764 "RamSize\0"
1765 "IOAPIC\0"
1766 "NumCPUs\0"
1767 "GCEnabled\0"
1768 "R0Enabled\0"
1769 "FdcEnabled\0"
1770 "HpetEnabled\0"
1771 "SmcEnabled\0"))
1772 return PDMDEV_SET_ERROR(pDevIns, VERR_PDM_DEVINS_UNKNOWN_CFG_VALUES,
1773 N_("Configuration error: Invalid config key for ACPI device"));
1774
1775 s->pDevIns = pDevIns;
1776
1777 /* query whether we are supposed to present an IOAPIC */
1778 rc = CFGMR3QueryU8 (pCfgHandle, "IOAPIC", &s->u8UseIOApic);
1779 if (rc == VERR_CFGM_VALUE_NOT_FOUND)
1780 s->u8UseIOApic = 1;
1781 else if (RT_FAILURE (rc))
1782 return PDMDEV_SET_ERROR(pDevIns, rc,
1783 N_("Configuration error: Failed to read \"IOAPIC\""));
1784
1785 /* query whether we are supposed to present HPET */
1786 rc = CFGMR3QueryU8Def (pCfgHandle, "HpetEnabled", &s->u8UseHpet, 0);
1787 if (RT_FAILURE(rc))
1788 return PDMDEV_SET_ERROR(pDevIns, rc,
1789 N_("Configuration error: Failed to read \"HpetEnabled\""));
1790 /* query whether we are supposed to present SMC */
1791 rc = CFGMR3QueryU8Def (pCfgHandle, "SmcEnabled", &s->u8UseSmc, 0);
1792 if (RT_FAILURE(rc))
1793 return PDMDEV_SET_ERROR(pDevIns, rc,
1794 N_("Configuration error: Failed to read \"SmcEnabled\""));
1795
1796 rc = CFGMR3QueryU16Def(pCfgHandle, "NumCPUs", &s->cCpus, 1);
1797 if (RT_FAILURE(rc))
1798 return PDMDEV_SET_ERROR(pDevIns, rc,
1799 N_("Configuration error: Querying \"NumCPUs\" as integer failed"));
1800
1801 /* query whether we are supposed to present an FDC controller */
1802 rc = CFGMR3QueryU8 (pCfgHandle, "FdcEnabled", &s->u8UseFdc);
1803 if (rc == VERR_CFGM_VALUE_NOT_FOUND)
1804 s->u8UseFdc = 1;
1805 else if (RT_FAILURE (rc))
1806 return PDMDEV_SET_ERROR(pDevIns, rc,
1807 N_("Configuration error: Failed to read \"FdcEnabled\""));
1808
1809 rc = CFGMR3QueryBool (pCfgHandle, "GCEnabled", &fGCEnabled);
1810 if (rc == VERR_CFGM_VALUE_NOT_FOUND)
1811 fGCEnabled = true;
1812 else if (RT_FAILURE (rc))
1813 return PDMDEV_SET_ERROR(pDevIns, rc,
1814 N_("Configuration error: Failed to read \"GCEnabled\""));
1815
1816 rc = CFGMR3QueryBool(pCfgHandle, "R0Enabled", &fR0Enabled);
1817 if (rc == VERR_CFGM_VALUE_NOT_FOUND)
1818 fR0Enabled = true;
1819 else if (RT_FAILURE(rc))
1820 return PDMDEV_SET_ERROR(pDevIns, rc,
1821 N_("configuration error: failed to read R0Enabled as boolean"));
1822
1823 /* */
1824 rsdp_addr = find_rsdp_space ();
1825 if (!rsdp_addr)
1826 return PDMDEV_SET_ERROR(pDevIns, VERR_NO_MEMORY,
1827 N_("Can not find space for RSDP. ACPI is disabled"));
1828
1829 rc = acpiPlantTables (s);
1830 if (RT_FAILURE (rc))
1831 return rc;
1832
1833 rc = PDMDevHlpROMRegister (pDevIns, rsdp_addr, 0x1000, s->au8RSDPPage, false /* fShadow */, "ACPI RSDP");
1834 if (RT_FAILURE (rc))
1835 return rc;
1836
1837#define R(addr, cnt, writer, reader, description) \
1838 do { \
1839 rc = PDMDevHlpIOPortRegister (pDevIns, addr, cnt, s, writer, reader, \
1840 NULL, NULL, description); \
1841 if (RT_FAILURE (rc)) \
1842 return rc; \
1843 } while (0)
1844#define L (GPE0_BLK_LEN / 2)
1845
1846 R (PM1a_EVT_BLK+2, 1, acpiPM1aEnWrite, acpiPm1aEnRead, "ACPI PM1a Enable");
1847 R (PM1a_EVT_BLK, 1, acpiPM1aStsWrite, acpiPm1aStsRead, "ACPI PM1a Status");
1848 R (PM1a_CTL_BLK, 1, acpiPM1aCtlWrite, acpiPm1aCtlRead, "ACPI PM1a Control");
1849 R (PM_TMR_BLK, 1, NULL, acpiPMTmrRead, "ACPI PM Timer");
1850 R (SMI_CMD, 1, acpiSmiWrite, NULL, "ACPI SMI");
1851#ifdef DEBUG_ACPI
1852 R (DEBUG_HEX, 1, acpiDhexWrite, NULL, "ACPI Debug hex");
1853 R (DEBUG_CHR, 1, acpiDchrWrite, NULL, "ACPI Debug char");
1854#endif
1855 R (BAT_INDEX, 1, acpiBatIndexWrite, NULL, "ACPI Battery status index");
1856 R (BAT_DATA, 1, NULL, acpiBatDataRead, "ACPI Battery status data");
1857 R (SYSI_INDEX, 1, acpiSysInfoIndexWrite, NULL, "ACPI system info index");
1858 R (SYSI_DATA, 1, acpiSysInfoDataWrite, acpiSysInfoDataRead, "ACPI system info data");
1859 R (GPE0_BLK + L, L, acpiGpe0EnWrite, acpiGpe0EnRead, "ACPI GPE0 Enable");
1860 R (GPE0_BLK, L, acpiGpe0StsWrite, acpiGpe0StsRead, "ACPI GPE0 Status");
1861 R (ACPI_RESET_BLK, 1, acpiResetWrite, NULL, "ACPI Reset");
1862#undef L
1863#undef R
1864
1865 /* register GC stuff */
1866 if (fGCEnabled)
1867 {
1868 rc = PDMDevHlpIOPortRegisterGC (pDevIns, PM_TMR_BLK, 1, 0, NULL, "acpiPMTmrRead",
1869 NULL, NULL, "ACPI PM Timer");
1870 AssertRCReturn(rc, rc);
1871 }
1872
1873 /* register R0 stuff */
1874 if (fR0Enabled)
1875 {
1876 rc = PDMDevHlpIOPortRegisterR0 (pDevIns, PM_TMR_BLK, 1, 0, NULL, "acpiPMTmrRead",
1877 NULL, NULL, "ACPI PM Timer");
1878 AssertRCReturn(rc, rc);
1879 }
1880
1881 rc = PDMDevHlpTMTimerCreate (pDevIns, TMCLOCK_VIRTUAL_SYNC, acpiTimer, "ACPI Timer", &s->tsR3);
1882 if (RT_FAILURE(rc))
1883 {
1884 AssertMsgFailed(("pfnTMTimerCreate -> %Rrc\n", rc));
1885 return rc;
1886 }
1887
1888 s->tsR0 = TMTimerR0Ptr (s->tsR3);
1889 s->tsRC = TMTimerRCPtr (s->tsR3);
1890 s->pm_timer_initial = TMTimerGet (s->tsR3);
1891 acpiPMTimerReset (s);
1892
1893 dev = &s->dev;
1894 dev->config[0x00] = 0x86;
1895 dev->config[0x01] = 0x80;
1896
1897 dev->config[0x02] = 0x13;
1898 dev->config[0x03] = 0x71;
1899
1900 dev->config[0x04] = 0x01;
1901 dev->config[0x05] = 0x00;
1902
1903 dev->config[0x06] = 0x80;
1904 dev->config[0x07] = 0x02;
1905 dev->config[0x08] = 0x08;
1906 dev->config[0x09] = 0x00;
1907
1908 dev->config[0x0a] = 0x80;
1909 dev->config[0x0b] = 0x06;
1910
1911 dev->config[0x0e] = 0x80;
1912 dev->config[0x0f] = 0x00;
1913
1914#if 0 /* The ACPI controller usually has no subsystem ID. */
1915 dev->config[0x2c] = 0x86;
1916 dev->config[0x2d] = 0x80;
1917 dev->config[0x2e] = 0x00;
1918 dev->config[0x2f] = 0x00;
1919#endif
1920 dev->config[0x3c] = SCI_INT;
1921
1922 rc = PDMDevHlpPCIRegister (pDevIns, dev);
1923 if (RT_FAILURE (rc))
1924 return rc;
1925
1926 rc = PDMDevHlpSSMRegister (pDevIns, pDevIns->pDevReg->szDeviceName, iInstance, 4, sizeof(*s),
1927 NULL, acpi_save_state, NULL, NULL, acpi_load_state, NULL);
1928 if (RT_FAILURE(rc))
1929 return rc;
1930
1931 /*
1932 * Interfaces
1933 */
1934 /* IBase */
1935 s->IBase.pfnQueryInterface = acpiQueryInterface;
1936 /* IACPIPort */
1937 s->IACPIPort.pfnSleepButtonPress = acpiSleepButtonPress;
1938 s->IACPIPort.pfnPowerButtonPress = acpiPowerButtonPress;
1939 s->IACPIPort.pfnGetPowerButtonHandled = acpiGetPowerButtonHandled;
1940 s->IACPIPort.pfnGetGuestEnteredACPIMode = acpiGetGuestEnteredACPIMode;
1941
1942 /*
1943 * Get the corresponding connector interface
1944 */
1945 rc = PDMDevHlpDriverAttach (pDevIns, 0, &s->IBase, &s->pDrvBase, "ACPI Driver Port");
1946 if (RT_SUCCESS (rc))
1947 {
1948 s->pDrv = (PPDMIACPICONNECTOR)s->pDrvBase->pfnQueryInterface (s->pDrvBase,
1949 PDMINTERFACE_ACPI_CONNECTOR);
1950 if (!s->pDrv)
1951 return PDMDEV_SET_ERROR(pDevIns, VERR_PDM_MISSING_INTERFACE,
1952 N_("LUN #0 doesn't have an ACPI connector interface"));
1953 }
1954 else if (rc == VERR_PDM_NO_ATTACHED_DRIVER)
1955 {
1956 Log (("acpi: %s/%d: warning: no driver attached to LUN #0!\n",
1957 pDevIns->pDevReg->szDeviceName, pDevIns->iInstance));
1958 rc = VINF_SUCCESS;
1959 }
1960 else
1961 return PDMDEV_SET_ERROR(pDevIns, rc,
1962 N_("Failed to attach LUN #0"));
1963
1964 return rc;
1965}
1966
1967/**
1968 * Relocates the GC pointer members.
1969 */
1970static DECLCALLBACK(void) acpiRelocate (PPDMDEVINS pDevIns, RTGCINTPTR offDelta)
1971{
1972 ACPIState *s = PDMINS_2_DATA (pDevIns, ACPIState *);
1973 s->tsRC = TMTimerRCPtr (s->CTX_SUFF(ts));
1974}
1975
1976static DECLCALLBACK(void) acpiReset (PPDMDEVINS pDevIns)
1977{
1978 ACPIState *s = PDMINS_2_DATA (pDevIns, ACPIState *);
1979
1980 s->pm1a_en = 0;
1981 s->pm1a_sts = 0;
1982 s->pm1a_ctl = 0;
1983 s->pm_timer_initial = TMTimerGet (s->CTX_SUFF(ts));
1984 acpiPMTimerReset(s);
1985 s->uBatteryIndex = 0;
1986 s->uSystemInfoIndex = 0;
1987 s->gpe0_en = 0;
1988 s->gpe0_sts = 0;
1989 s->uSleepState = 0;
1990
1991 acpiPlantTables(s);
1992}
1993
1994/**
1995 * The device registration structure.
1996 */
1997const PDMDEVREG g_DeviceACPI =
1998{
1999 /* u32Version */
2000 PDM_DEVREG_VERSION,
2001 /* szDeviceName */
2002 "acpi",
2003 /* szRCMod */
2004 "VBoxDDGC.gc",
2005 /* szR0Mod */
2006 "VBoxDDR0.r0",
2007 /* pszDescription */
2008 "Advanced Configuration and Power Interface",
2009 /* fFlags */
2010 PDM_DEVREG_FLAGS_DEFAULT_BITS | PDM_DEVREG_FLAGS_RC | PDM_DEVREG_FLAGS_R0,
2011 /* fClass */
2012 PDM_DEVREG_CLASS_ACPI,
2013 /* cMaxInstances */
2014 ~0,
2015 /* cbInstance */
2016 sizeof(ACPIState),
2017 /* pfnConstruct */
2018 acpiConstruct,
2019 /* pfnDestruct */
2020 NULL,
2021 /* pfnRelocate */
2022 acpiRelocate,
2023 /* pfnIOCtl */
2024 NULL,
2025 /* pfnPowerOn */
2026 NULL,
2027 /* pfnReset */
2028 acpiReset,
2029 /* pfnSuspend */
2030 NULL,
2031 /* pfnResume */
2032 NULL,
2033 /* pfnAttach */
2034 NULL,
2035 /* pfnDetach */
2036 NULL,
2037 /* pfnQueryInterface. */
2038 NULL,
2039 /* pfnInitComplete */
2040 NULL,
2041 /* pfnPowerOff */
2042 NULL,
2043 /* pfnSoftReset */
2044 NULL,
2045 /* u32VersionEnd */
2046 PDM_DEVREG_VERSION
2047};
2048
2049#endif /* IN_RING3 */
2050#endif /* !VBOX_DEVICE_STRUCT_TESTCASE */
2051
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