VirtualBox

source: vbox/trunk/src/VBox/Devices/PC/DevACPI.cpp@ 11284

Last change on this file since 11284 was 11284, checked in by vboxsync, 16 years ago

Devices: %Vrc -> %Rrc (just preferred, not mandatory (yet))
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File size: 63.4 KB
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1/* $Id: DevACPI.cpp 11284 2008-08-08 22:32:08Z vboxsync $ */
2/** @file
3 * DevACPI - Advanced Configuration and Power Interface (ACPI) Device.
4 */
5
6/*
7 * Copyright (C) 2006-2007 Sun Microsystems, Inc.
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 *
17 * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
18 * Clara, CA 95054 USA or visit http://www.sun.com if you need
19 * additional information or have any questions.
20 */
21
22#define LOG_GROUP LOG_GROUP_DEV_ACPI
23#include <VBox/pdmdev.h>
24#include <VBox/log.h>
25#include <iprt/assert.h>
26#include <iprt/asm.h>
27#ifdef IN_RING3
28# include <iprt/alloc.h>
29# include <iprt/string.h>
30#endif /* IN_RING3 */
31
32#include "../Builtins.h"
33
34#ifdef LOG_ENABLED
35# define DEBUG_ACPI
36#endif
37
38/* the compiled DSL */
39#if defined(IN_RING3) && !defined(VBOX_DEVICE_STRUCT_TESTCASE)
40#include <vboxaml.hex>
41#endif /* !IN_RING3 */
42
43#define IO_READ_PROTO(name) \
44 PDMBOTHCBDECL(int) name (PPDMDEVINS pDevIns, void *pvUser, \
45 RTIOPORT Port, uint32_t *pu32, unsigned cb)
46
47#define IO_WRITE_PROTO(name) \
48 PDMBOTHCBDECL(int) name (PPDMDEVINS pDevIns, void *pvUser, \
49 RTIOPORT Port, uint32_t u32, unsigned cb)
50
51#define DEBUG_HEX 0x3000
52#define DEBUG_CHR 0x3001
53
54#define PM_TMR_FREQ 3579545
55#define PM1a_EVT_BLK 0x00004000
56#define PM1b_EVT_BLK 0x00000000 /**< not supported */
57#define PM1a_CTL_BLK 0x00004004
58#define PM1b_CTL_BLK 0x00000000 /**< not supported */
59#define PM2_CTL_BLK 0x00000000 /**< not supported */
60#define PM_TMR_BLK 0x00004008
61#define GPE0_BLK 0x00004020
62#define GPE1_BLK 0x00000000 /**< not supported */
63#define BAT_INDEX 0x00004040
64#define BAT_DATA 0x00004044
65#define SYSI_INDEX 0x00004048
66#define SYSI_DATA 0x0000404c
67#define ACPI_RESET_BLK 0x00004050
68#define FDC_STATUS 0x00004054
69
70/* PM1x status register bits */
71#define TMR_STS RT_BIT(0)
72#define RSR1_STS (RT_BIT(1) | RT_BIT(2) | RT_BIT(3))
73#define BM_STS RT_BIT(4)
74#define GBL_STS RT_BIT(5)
75#define RSR2_STS (RT_BIT(6) | RT_BIT(7))
76#define PWRBTN_STS RT_BIT(8)
77#define SLPBTN_STS RT_BIT(9)
78#define RTC_STS RT_BIT(10)
79#define IGN_STS RT_BIT(11)
80#define RSR3_STS (RT_BIT(12) | RT_BIT(13) | RT_BIT(14))
81#define WAK_STS RT_BIT(15)
82#define RSR_STS (RSR1_STS | RSR2_STS | RSR3_STS)
83
84/* PM1x enable register bits */
85#define TMR_EN RT_BIT(0)
86#define RSR1_EN (RT_BIT(1) | RT_BIT(2) | RT_BIT(3) | RT_BIT(4))
87#define GBL_EN RT_BIT(5)
88#define RSR2_EN (RT_BIT(6) | RT_BIT(7))
89#define PWRBTN_EN RT_BIT(8)
90#define SLPBTN_EN RT_BIT(9)
91#define RTC_EN RT_BIT(10)
92#define RSR3_EN (RT_BIT(11) | RT_BIT(12) | RT_BIT(13) | RT_BIT(14) | RT_BIT(15))
93#define RSR_EN (RSR1_EN | RSR2_EN | RSR3_EN)
94#define IGN_EN 0
95
96/* PM1x control register bits */
97#define SCI_EN RT_BIT(0)
98#define BM_RLD RT_BIT(1)
99#define GBL_RLS RT_BIT(2)
100#define RSR1_CNT (RT_BIT(3) | RT_BIT(4) | RT_BIT(5) | RT_BIT(6) | RT_BIT(7) | RT_BIT(8))
101#define IGN_CNT RT_BIT(9)
102#define SLP_TYPx_SHIFT 10
103#define SLP_TYPx_MASK 7
104#define SLP_EN RT_BIT(13)
105#define RSR2_CNT (RT_BIT(14) | RT_BIT(15))
106#define RSR_CNT (RSR1_CNT | RSR2_CNT)
107
108#define GPE0_BATTERY_INFO_CHANGED RT_BIT(0)
109
110enum
111{
112 BAT_STATUS_STATE = 0x00, /**< BST battery state */
113 BAT_STATUS_PRESENT_RATE = 0x01, /**< BST battery present rate */
114 BAT_STATUS_REMAINING_CAPACITY = 0x02, /**< BST battery remaining capacity */
115 BAT_STATUS_PRESENT_VOLTAGE = 0x03, /**< BST battery present voltage */
116 BAT_INFO_UNITS = 0x04, /**< BIF power unit */
117 BAT_INFO_DESIGN_CAPACITY = 0x05, /**< BIF design capacity */
118 BAT_INFO_LAST_FULL_CHARGE_CAPACITY = 0x06, /**< BIF last full charge capacity */
119 BAT_INFO_TECHNOLOGY = 0x07, /**< BIF battery technology */
120 BAT_INFO_DESIGN_VOLTAGE = 0x08, /**< BIF design voltage */
121 BAT_INFO_DESIGN_CAPACITY_OF_WARNING = 0x09, /**< BIF design capacity of warning */
122 BAT_INFO_DESIGN_CAPACITY_OF_LOW = 0x0A, /**< BIF design capacity of low */
123 BAT_INFO_CAPACITY_GRANULARITY_1 = 0x0B, /**< BIF battery capacity granularity 1 */
124 BAT_INFO_CAPACITY_GRANULARITY_2 = 0x0C, /**< BIF battery capacity granularity 2 */
125 BAT_DEVICE_STATUS = 0x0D, /**< STA device status */
126 BAT_POWER_SOURCE = 0x0E, /**< PSR power source */
127 BAT_INDEX_LAST
128};
129
130enum
131{
132 SYSTEM_INFO_INDEX_MEMORY_LENGTH = 0,
133 SYSTEM_INFO_INDEX_USE_IOAPIC = 1,
134 SYSTEM_INFO_INDEX_LAST = 2,
135 SYSTEM_INFO_INDEX_INVALID = 0x80,
136 SYSTEM_INFO_INDEX_VALID = 0x200
137};
138
139#define AC_OFFLINE 0
140#define AC_ONLINE 1
141
142#define BAT_TECH_PRIMARY 1
143#define BAT_TECH_SECONDARY 2
144
145#define BAT_STATUS_DISCHARGING_MASK RT_BIT(0)
146#define BAT_STATUS_CHARGING_MASK RT_BIT(1)
147#define BAT_STATUS_CRITICAL_MASK RT_BIT(2)
148
149#define STA_DEVICE_PRESENT_MASK RT_BIT(0)
150#define STA_DEVICE_ENABLED_MASK RT_BIT(1)
151#define STA_DEVICE_SHOW_IN_UI_MASK RT_BIT(2)
152#define STA_DEVICE_FUNCTIONING_PROPERLY_MASK RT_BIT(3)
153#define STA_BATTERY_PRESENT_MASK RT_BIT(4)
154
155struct ACPIState
156{
157 PCIDevice dev;
158 uint16_t pm1a_en;
159 uint16_t pm1a_sts;
160 uint16_t pm1a_ctl;
161 uint16_t Alignment0;
162 int64_t pm_timer_initial;
163 PTMTIMERR3 tsR3;
164 PTMTIMERR0 tsR0;
165 PTMTIMERRC tsRC;
166
167 uint32_t gpe0_en;
168 uint32_t gpe0_sts;
169
170 unsigned int uBatteryIndex;
171 uint32_t au8BatteryInfo[13];
172
173 unsigned int uSystemInfoIndex;
174 uint64_t u64RamSize;
175
176 /** Current ACPI S* state. We support S0 and S5 */
177 uint32_t uSleepState;
178 uint8_t au8RSDPPage[0x1000];
179 /** This is a workaround for incorrect index field handling by Intels ACPICA.
180 * The system info _INI method writes to offset 0x200. We either observe a
181 * write request to index 0x80 (in that case we don't change the index) or a
182 * write request to offset 0x200 (in that case we divide the index value by
183 * 4. Note that the _STA method is sometimes called prior to the _INI method
184 * (ACPI spec 6.3.7, _STA). See the special case for BAT_DEVICE_STATUS in
185 * acpiBatIndexWrite() for handling this. */
186 uint8_t u8IndexShift;
187 uint8_t u8UseIOApic;
188 uint8_t u8UseFdc;
189 bool fPowerButtonHandled;
190
191 /** ACPI port base interface. */
192 PDMIBASE IBase;
193 /** ACPI port interface. */
194 PDMIACPIPORT IACPIPort;
195 /** Pointer to the device instance. */
196 PPDMDEVINSR3 pDevIns;
197 /** Pointer to the driver base interface */
198 R3PTRTYPE(PPDMIBASE) pDrvBase;
199 /** Pointer to the driver connector interface */
200 R3PTRTYPE(PPDMIACPICONNECTOR) pDrv;
201};
202
203#pragma pack(1)
204
205/** Generic Address Structure (see ACPIspec 3.0, 5.2.3.1) */
206struct ACPIGENADDR
207{
208 uint8_t u8AddressSpaceId; /**< 0=sys, 1=IO, 2=PCICfg, 3=emb, 4=SMBus */
209 uint8_t u8RegisterBitWidth; /**< size in bits of the given register */
210 uint8_t u8RegisterBitOffset; /**< bit offset of register */
211 uint8_t u8AccessSize; /**< 1=byte, 2=word, 3=dword, 4=qword */
212 uint64_t u64Address; /**< 64-bit address of register */
213};
214AssertCompileSize(ACPIGENADDR, 12);
215
216/** Root System Description Pointer */
217struct ACPITBLRSDP
218{
219 uint8_t au8Signature[8]; /**< 'RSD PTR ' */
220 uint8_t u8Checksum; /**< checksum for the first 20 bytes */
221 uint8_t au8OemId[6]; /**< OEM-supplied identifier */
222 uint8_t u8Revision; /**< revision number, currently 2 */
223#define ACPI_REVISION 2 /**< ACPI 3.0 */
224 uint32_t u32RSDT; /**< phys addr of RSDT */
225 uint32_t u32Length; /**< bytes of this table */
226 uint64_t u64XSDT; /**< 64-bit phys addr of XSDT */
227 uint8_t u8ExtChecksum; /**< checksum of entire table */
228 uint8_t u8Reserved[3]; /**< reserved */
229};
230AssertCompileSize(ACPITBLRSDP, 36);
231
232/** System Description Table Header */
233struct ACPITBLHEADER
234{
235 uint8_t au8Signature[4]; /**< table identifier */
236 uint32_t u32Length; /**< length of the table including header */
237 uint8_t u8Revision; /**< revision number */
238 uint8_t u8Checksum; /**< all fields inclusive this add to zero */
239 uint8_t au8OemId[6]; /**< OEM-supplied string */
240 uint8_t au8OemTabId[8]; /**< to identify the particular data table */
241 uint32_t u32OemRevision; /**< OEM-supplied revision number */
242 uint8_t au8CreatorId[4]; /**< ID for the ASL compiler */
243 uint32_t u32CreatorRev; /**< revision for the ASL compiler */
244};
245AssertCompileSize(ACPITBLHEADER, 36);
246
247/** Root System Description Table */
248struct ACPITBLRSDT
249{
250 ACPITBLHEADER header;
251 uint32_t u32Entry[1]; /**< array of phys. addresses to other tables */
252};
253AssertCompileSize(ACPITBLRSDT, 40);
254
255/** Extended System Description Table */
256struct ACPITBLXSDT
257{
258 ACPITBLHEADER header;
259 uint64_t u64Entry[1]; /**< array of phys. addresses to other tables */
260};
261AssertCompileSize(ACPITBLXSDT, 44);
262
263/** Fixed ACPI Description Table */
264struct ACPITBLFADT
265{
266 ACPITBLHEADER header;
267 uint32_t u32FACS; /**< phys. address of FACS */
268 uint32_t u32DSDT; /**< phys. address of DSDT */
269 uint8_t u8IntModel; /**< was eleminated in ACPI 2.0 */
270#define INT_MODEL_DUAL_PIC 1 /**< for ACPI 2+ */
271#define INT_MODEL_MULTIPLE_APIC 2
272 uint8_t u8PreferredPMProfile; /**< preferred power management profile */
273 uint16_t u16SCIInt; /**< system vector the SCI is wired in 8259 mode */
274#define SCI_INT 9
275 uint32_t u32SMICmd; /**< system port address of SMI command port */
276#define SMI_CMD 0x0000442e
277 uint8_t u8AcpiEnable; /**< SMICmd val to disable ownship of ACPIregs */
278#define ACPI_ENABLE 0xa1
279 uint8_t u8AcpiDisable; /**< SMICmd val to re-enable ownship of ACPIregs */
280#define ACPI_DISABLE 0xa0
281 uint8_t u8S4BIOSReq; /**< SMICmd val to enter S4BIOS state */
282 uint8_t u8PStateCnt; /**< SMICmd val to assume processor performance
283 state control responsibility */
284 uint32_t u32PM1aEVTBLK; /**< port addr of PM1a event regs block */
285 uint32_t u32PM1bEVTBLK; /**< port addr of PM1b event regs block */
286 uint32_t u32PM1aCTLBLK; /**< port addr of PM1a control regs block */
287 uint32_t u32PM1bCTLBLK; /**< port addr of PM1b control regs block */
288 uint32_t u32PM2CTLBLK; /**< port addr of PM2 control regs block */
289 uint32_t u32PMTMRBLK; /**< port addr of PMTMR regs block */
290 uint32_t u32GPE0BLK; /**< port addr of gen-purp event 0 regs block */
291 uint32_t u32GPE1BLK; /**< port addr of gen-purp event 1 regs block */
292 uint8_t u8PM1EVTLEN; /**< bytes decoded by PM1a_EVT_BLK. >= 4 */
293 uint8_t u8PM1CTLLEN; /**< bytes decoded by PM1b_CNT_BLK. >= 2 */
294 uint8_t u8PM2CTLLEN; /**< bytes decoded by PM2_CNT_BLK. >= 1 or 0 */
295 uint8_t u8PMTMLEN; /**< bytes decoded by PM_TMR_BLK. ==4 */
296 uint8_t u8GPE0BLKLEN; /**< bytes decoded by GPE0_BLK. %2==0 */
297#define GPE0_BLK_LEN 2
298 uint8_t u8GPE1BLKLEN; /**< bytes decoded by GPE1_BLK. %2==0 */
299#define GPE1_BLK_LEN 0
300 uint8_t u8GPE1BASE; /**< offset of GPE1 based events */
301#define GPE1_BASE 0
302 uint8_t u8CSTCNT; /**< SMICmd val to indicate OS supp for C states */
303 uint16_t u16PLVL2LAT; /**< us to enter/exit C2. >100 => unsupported */
304#define P_LVL2_LAT 101 /**< C2 state not supported */
305 uint16_t u16PLVL3LAT; /**< us to enter/exit C3. >1000 => unsupported */
306#define P_LVL3_LAT 1001 /**< C3 state not supported */
307 uint16_t u16FlushSize; /**< # of flush strides to read to flush dirty
308 lines from any processors memory caches */
309#define FLUSH_SIZE 0 /**< Ignored if WBVIND set in FADT_FLAGS */
310 uint16_t u16FlushStride; /**< cache line width */
311#define FLUSH_STRIDE 0 /**< Ignored if WBVIND set in FADT_FLAGS */
312 uint8_t u8DutyOffset;
313 uint8_t u8DutyWidth;
314 uint8_t u8DayAlarm; /**< RTC CMOS RAM index of day-of-month alarm */
315 uint8_t u8MonAlarm; /**< RTC CMOS RAM index of month-of-year alarm */
316 uint8_t u8Century; /**< RTC CMOS RAM index of century */
317 uint16_t u16IAPCBOOTARCH; /**< IA-PC boot architecture flags */
318#define IAPC_BOOT_ARCH_LEGACY_DEV RT_BIT(0) /**< legacy devices present such as LPT
319 (COM too?) */
320#define IAPC_BOOT_ARCH_8042 RT_BIT(1) /**< legacy keyboard device present */
321#define IAPC_BOOT_ARCH_NO_VGA RT_BIT(2) /**< VGA not present */
322 uint8_t u8Must0_0; /**< must be 0 */
323 uint32_t u32Flags; /**< fixed feature flags */
324#define FADT_FL_WBINVD RT_BIT(0) /**< emulation of WBINVD available */
325#define FADT_FL_WBINVD_FLUSH RT_BIT(1)
326#define FADT_FL_PROC_C1 RT_BIT(2) /**< 1=C1 supported on all processors */
327#define FADT_FL_P_LVL2_UP RT_BIT(3) /**< 1=C2 works on SMP and UNI systems */
328#define FADT_FL_PWR_BUTTON RT_BIT(4) /**< 1=power button handled as ctrl method dev */
329#define FADT_FL_SLP_BUTTON RT_BIT(5) /**< 1=sleep button handled as ctrl method dev */
330#define FADT_FL_FIX_RTC RT_BIT(6) /**< 0=RTC wake status in fixed register */
331#define FADT_FL_RTC_S4 RT_BIT(7) /**< 1=RTC can wake system from S4 */
332#define FADT_FL_TMR_VAL_EXT RT_BIT(8) /**< 1=TMR_VAL implemented as 32 bit */
333#define FADT_FL_DCK_CAP RT_BIT(9) /**< 0=system cannot support docking */
334#define FADT_FL_RESET_REG_SUP RT_BIT(10) /**< 1=system supports system resets */
335#define FADT_FL_SEALED_CASE RT_BIT(11) /**< 1=case is sealed */
336#define FADT_FL_HEADLESS RT_BIT(12) /**< 1=system cannot detect moni/keyb/mouse */
337#define FADT_FL_CPU_SW_SLP RT_BIT(13)
338#define FADT_FL_PCI_EXT_WAK RT_BIT(14) /**< 1=system supports PCIEXP_WAKE_STS */
339#define FADT_FL_USE_PLATFORM_CLOCK RT_BIT(15) /**< 1=system has ACPI PM timer */
340#define FADT_FL_S4_RTC_STS_VALID RT_BIT(16) /**< 1=RTC_STS flag is valid when waking from S4 */
341#define FADT_FL_REMOVE_POWER_ON_CAPABLE RT_BIT(17) /**< 1=platform can remote power on */
342#define FADT_FL_FORCE_APIC_CLUSTER_MODEL RT_BIT(18)
343#define FADT_FL_FORCE_APIC_PHYS_DEST_MODE RT_BIT(19)
344 ACPIGENADDR ResetReg; /**< ext addr of reset register */
345 uint8_t u8ResetVal; /**< ResetReg value to reset the system */
346#define ACPI_RESET_REG_VAL 0x10
347 uint8_t au8Must0_1[3]; /**< must be 0 */
348 uint64_t u64XFACS; /**< 64-bit phys address of FACS */
349 uint64_t u64XDSDT; /**< 64-bit phys address of DSDT */
350 ACPIGENADDR X_PM1aEVTBLK; /**< ext addr of PM1a event regs block */
351 ACPIGENADDR X_PM1bEVTBLK; /**< ext addr of PM1b event regs block */
352 ACPIGENADDR X_PM1aCTLBLK; /**< ext addr of PM1a control regs block */
353 ACPIGENADDR X_PM1bCTLBLK; /**< ext addr of PM1b control regs block */
354 ACPIGENADDR X_PM2CTLBLK; /**< ext addr of PM2 control regs block */
355 ACPIGENADDR X_PMTMRBLK; /**< ext addr of PMTMR control regs block */
356 ACPIGENADDR X_GPE0BLK; /**< ext addr of GPE1 regs block */
357 ACPIGENADDR X_GPE1BLK; /**< ext addr of GPE1 regs block */
358};
359AssertCompileSize(ACPITBLFADT, 244);
360
361/** Firmware ACPI Control Structure */
362struct ACPITBLFACS
363{
364 uint8_t au8Signature[4]; /**< 'FACS' */
365 uint32_t u32Length; /**< bytes of entire FACS structure >= 64 */
366 uint32_t u32HWSignature; /**< systems HW signature at last boot */
367 uint32_t u32FWVector; /**< address of waking vector */
368 uint32_t u32GlobalLock; /**< global lock to sync HW/SW */
369 uint32_t u32Flags; /**< FACS flags */
370 uint64_t u64X_FWVector; /**< 64-bit waking vector */
371 uint8_t u8Version; /**< version of this table */
372 uint8_t au8Reserved[31]; /**< zero */
373};
374AssertCompileSize(ACPITBLFACS, 64);
375
376/** Processor Local APIC Structure */
377struct ACPITBLLAPIC
378{
379 uint8_t u8Type; /**< 0 = LAPIC */
380 uint8_t u8Length; /**< 8 */
381 uint8_t u8ProcId; /**< processor ID */
382 uint8_t u8ApicId; /**< local APIC ID */
383 uint32_t u32Flags; /**< Flags */
384#define LAPIC_ENABLED 0x1
385};
386AssertCompileSize(ACPITBLLAPIC, 8);
387
388/** I/O APIC Structure */
389struct ACPITBLIOAPIC
390{
391 uint8_t u8Type; /**< 1 == I/O APIC */
392 uint8_t u8Length; /**< 12 */
393 uint8_t u8IOApicId; /**< I/O APIC ID */
394 uint8_t u8Reserved; /**< 0 */
395 uint32_t u32Address; /**< phys address to access I/O APIC */
396 uint32_t u32GSIB; /**< global system interrupt number to start */
397};
398AssertCompileSize(ACPITBLIOAPIC, 12);
399
400/** Multiple APIC Description Table */
401struct ACPITBLMADT
402{
403 ACPITBLHEADER header;
404 uint32_t u32LAPIC; /**< local APIC address */
405 uint32_t u32Flags; /**< Flags */
406#define PCAT_COMPAT 0x1 /**< system has also a dual-8259 setup */
407 ACPITBLLAPIC LApic;
408 ACPITBLIOAPIC IOApic;
409};
410AssertCompileSize(ACPITBLMADT, 64);
411
412#pragma pack()
413
414
415#ifndef VBOX_DEVICE_STRUCT_TESTCASE
416__BEGIN_DECLS
417IO_READ_PROTO (acpiPMTmrRead);
418#ifdef IN_RING3
419IO_READ_PROTO (acpiPm1aEnRead);
420IO_WRITE_PROTO (acpiPM1aEnWrite);
421IO_READ_PROTO (acpiPm1aStsRead);
422IO_WRITE_PROTO (acpiPM1aStsWrite);
423IO_READ_PROTO (acpiPm1aCtlRead);
424IO_WRITE_PROTO (acpiPM1aCtlWrite);
425IO_WRITE_PROTO (acpiSmiWrite);
426IO_WRITE_PROTO (acpiBatIndexWrite);
427IO_READ_PROTO (acpiBatDataRead);
428IO_READ_PROTO (acpiFdcStatusRead);
429IO_READ_PROTO (acpiSysInfoDataRead);
430IO_WRITE_PROTO (acpiSysInfoDataWrite);
431IO_READ_PROTO (acpiGpe0EnRead);
432IO_WRITE_PROTO (acpiGpe0EnWrite);
433IO_READ_PROTO (acpiGpe0StsRead);
434IO_WRITE_PROTO (acpiGpe0StsWrite);
435IO_WRITE_PROTO (acpiResetWrite);
436# ifdef DEBUG_ACPI
437IO_WRITE_PROTO (acpiDhexWrite);
438IO_WRITE_PROTO (acpiDchrWrite);
439# endif
440#endif
441__END_DECLS
442
443#ifdef IN_RING3
444
445/* Simple acpiChecksum: all the bytes must add up to 0. */
446static uint8_t acpiChecksum (const uint8_t * const data, uint32_t len)
447{
448 uint8_t sum = 0;
449 for (size_t i = 0; i < len; ++i)
450 sum += data[i];
451 return -sum;
452}
453
454static void acpiPrepareHeader (ACPITBLHEADER *header, const char au8Signature[4],
455 uint32_t u32Length, uint8_t u8Revision)
456{
457 memcpy(header->au8Signature, au8Signature, 4);
458 header->u32Length = RT_H2LE_U32(u32Length);
459 header->u8Revision = u8Revision;
460 memcpy(header->au8OemId, "VBOX ", 6);
461 memcpy(header->au8OemTabId, "VBOX", 4);
462 memcpy(header->au8OemTabId+4, au8Signature, 4);
463 header->u32OemRevision = RT_H2LE_U32(1);
464 memcpy(header->au8CreatorId, "ASL ", 4);
465 header->u32CreatorRev = RT_H2LE_U32(0x61);
466}
467
468static void acpiWriteGenericAddr(ACPIGENADDR *g, uint8_t u8AddressSpaceId,
469 uint8_t u8RegisterBitWidth, uint8_t u8RegisterBitOffset,
470 uint8_t u8AccessSize, uint64_t u64Address)
471{
472 g->u8AddressSpaceId = u8AddressSpaceId;
473 g->u8RegisterBitWidth = u8RegisterBitWidth;
474 g->u8RegisterBitOffset = u8RegisterBitOffset;
475 g->u8AccessSize = u8AccessSize;
476 g->u64Address = RT_H2LE_U64(u64Address);
477}
478
479static void acpiPhyscpy (ACPIState *s, RTGCPHYS32 dst, const void * const src, size_t size)
480{
481 PDMDevHlpPhysWrite (s->pDevIns, dst, src, size);
482}
483
484/* Differentiated System Description Table (DSDT) */
485static void acpiSetupDSDT (ACPIState *s, RTGCPHYS32 addr)
486{
487 acpiPhyscpy (s, addr, AmlCode, sizeof(AmlCode));
488}
489
490/* Firmware ACPI Control Structure (FACS) */
491static void acpiSetupFACS (ACPIState *s, RTGCPHYS32 addr)
492{
493 ACPITBLFACS facs;
494
495 memset (&facs, 0, sizeof(facs));
496 memcpy (facs.au8Signature, "FACS", 4);
497 facs.u32Length = RT_H2LE_U32(sizeof(ACPITBLFACS));
498 facs.u32HWSignature = RT_H2LE_U32(0);
499 facs.u32FWVector = RT_H2LE_U32(0);
500 facs.u32GlobalLock = RT_H2LE_U32(0);
501 facs.u32Flags = RT_H2LE_U32(0);
502 facs.u64X_FWVector = RT_H2LE_U64(0);
503 facs.u8Version = 1;
504
505 acpiPhyscpy (s, addr, (const uint8_t*)&facs, sizeof(facs));
506}
507
508/* Fixed ACPI Description Table (FADT aka FACP) */
509static void acpiSetupFADT (ACPIState *s, RTGCPHYS32 addr, uint32_t facs_addr, uint32_t dsdt_addr)
510{
511 ACPITBLFADT fadt;
512
513 memset (&fadt, 0, sizeof(fadt));
514 acpiPrepareHeader (&fadt.header, "FACP", sizeof(fadt), 4);
515 fadt.u32FACS = RT_H2LE_U32(facs_addr);
516 fadt.u32DSDT = RT_H2LE_U32(dsdt_addr);
517 fadt.u8IntModel = INT_MODEL_DUAL_PIC;
518 fadt.u8PreferredPMProfile = 0; /* unspecified */
519 fadt.u16SCIInt = RT_H2LE_U16(SCI_INT);
520 fadt.u32SMICmd = RT_H2LE_U32(SMI_CMD);
521 fadt.u8AcpiEnable = ACPI_ENABLE;
522 fadt.u8AcpiDisable = ACPI_DISABLE;
523 fadt.u8S4BIOSReq = 0;
524 fadt.u8PStateCnt = 0;
525 fadt.u32PM1aEVTBLK = RT_H2LE_U32(PM1a_EVT_BLK);
526 fadt.u32PM1bEVTBLK = RT_H2LE_U32(PM1b_EVT_BLK);
527 fadt.u32PM1aCTLBLK = RT_H2LE_U32(PM1a_CTL_BLK);
528 fadt.u32PM1bCTLBLK = RT_H2LE_U32(PM1b_CTL_BLK);
529 fadt.u32PM2CTLBLK = RT_H2LE_U32(PM2_CTL_BLK);
530 fadt.u32PMTMRBLK = RT_H2LE_U32(PM_TMR_BLK);
531 fadt.u32GPE0BLK = RT_H2LE_U32(GPE0_BLK);
532 fadt.u32GPE1BLK = RT_H2LE_U32(GPE1_BLK);
533 fadt.u8PM1EVTLEN = 4;
534 fadt.u8PM1CTLLEN = 2;
535 fadt.u8PM2CTLLEN = 0;
536 fadt.u8PMTMLEN = 4;
537 fadt.u8GPE0BLKLEN = GPE0_BLK_LEN;
538 fadt.u8GPE1BLKLEN = GPE1_BLK_LEN;
539 fadt.u8GPE1BASE = GPE1_BASE;
540 fadt.u8CSTCNT = 0;
541 fadt.u16PLVL2LAT = RT_H2LE_U16(P_LVL2_LAT);
542 fadt.u16PLVL3LAT = RT_H2LE_U16(P_LVL3_LAT);
543 fadt.u16FlushSize = RT_H2LE_U16(FLUSH_SIZE);
544 fadt.u16FlushStride = RT_H2LE_U16(FLUSH_STRIDE);
545 fadt.u8DutyOffset = 0;
546 fadt.u8DutyWidth = 0;
547 fadt.u8DayAlarm = 0;
548 fadt.u8MonAlarm = 0;
549 fadt.u8Century = 0;
550 fadt.u16IAPCBOOTARCH = RT_H2LE_U16(IAPC_BOOT_ARCH_LEGACY_DEV | IAPC_BOOT_ARCH_8042);
551 /** @note WBINVD is required for ACPI versions newer than 1.0 */
552 fadt.u32Flags = RT_H2LE_U32( FADT_FL_WBINVD
553 | FADT_FL_FIX_RTC
554 | FADT_FL_TMR_VAL_EXT);
555 acpiWriteGenericAddr(&fadt.ResetReg, 1, 8, 0, 1, ACPI_RESET_BLK);
556 fadt.u8ResetVal = ACPI_RESET_REG_VAL;
557 fadt.u64XFACS = RT_H2LE_U64((uint64_t)facs_addr);
558 fadt.u64XDSDT = RT_H2LE_U64((uint64_t)dsdt_addr);
559 acpiWriteGenericAddr(&fadt.X_PM1aEVTBLK, 1, 32, 0, 2, PM1a_EVT_BLK);
560 acpiWriteGenericAddr(&fadt.X_PM1bEVTBLK, 0, 0, 0, 0, PM1b_EVT_BLK);
561 acpiWriteGenericAddr(&fadt.X_PM1aCTLBLK, 1, 16, 0, 2, PM1a_CTL_BLK);
562 acpiWriteGenericAddr(&fadt.X_PM1bCTLBLK, 0, 0, 0, 0, PM1b_CTL_BLK);
563 acpiWriteGenericAddr(&fadt.X_PM2CTLBLK, 0, 0, 0, 0, PM2_CTL_BLK);
564 acpiWriteGenericAddr(&fadt.X_PMTMRBLK, 1, 32, 0, 3, PM_TMR_BLK);
565 acpiWriteGenericAddr(&fadt.X_GPE0BLK, 1, 16, 0, 1, GPE0_BLK);
566 acpiWriteGenericAddr(&fadt.X_GPE1BLK, 0, 0, 0, 0, GPE1_BLK);
567 fadt.header.u8Checksum = acpiChecksum ((uint8_t*)&fadt, sizeof(fadt));
568 acpiPhyscpy (s, addr, &fadt, sizeof(fadt));
569}
570
571/*
572 * Root System Description Table.
573 * The RSDT and XSDT tables are basically identical. The only difference is 32 vs 64 bits
574 * addresses for description headers. RSDT is for ACPI 1.0. XSDT for ACPI 2.0 and up.
575 */
576static int acpiSetupRSDT (ACPIState *s, RTGCPHYS32 addr, unsigned int nb_entries, uint32_t *addrs)
577{
578 ACPITBLRSDT *rsdt;
579 const size_t size = sizeof(ACPITBLHEADER) + nb_entries * sizeof(rsdt->u32Entry[0]);
580
581 rsdt = (ACPITBLRSDT*)RTMemAllocZ (size);
582 if (!rsdt)
583 return PDMDEV_SET_ERROR(s->pDevIns, VERR_NO_TMP_MEMORY, N_("Cannot allocate RSDT"));
584
585 acpiPrepareHeader (&rsdt->header, "RSDT", size, 1);
586 for (unsigned int i = 0; i < nb_entries; ++i)
587 {
588 rsdt->u32Entry[i] = RT_H2LE_U32(addrs[i]);
589 Log(("Setup RSDT: [%d] = %x\n", i, rsdt->u32Entry[i]));
590 }
591 rsdt->header.u8Checksum = acpiChecksum ((uint8_t*)rsdt, size);
592 acpiPhyscpy (s, addr, rsdt, size);
593 RTMemFree (rsdt);
594 return VINF_SUCCESS;
595}
596
597/* Extended System Description Table. */
598static int acpiSetupXSDT (ACPIState *s, RTGCPHYS32 addr, unsigned int nb_entries, uint32_t *addrs)
599{
600 ACPITBLXSDT *xsdt;
601 const size_t size = sizeof(ACPITBLHEADER) + nb_entries * sizeof(xsdt->u64Entry[0]);
602
603 xsdt = (ACPITBLXSDT*)RTMemAllocZ (size);
604 if (!xsdt)
605 return VERR_NO_TMP_MEMORY;
606
607 acpiPrepareHeader (&xsdt->header, "XSDT", size, 1 /* according to ACPI 3.0 specs */);
608 for (unsigned int i = 0; i < nb_entries; ++i)
609 {
610 xsdt->u64Entry[i] = RT_H2LE_U64((uint64_t)addrs[i]);
611 Log(("Setup XSDT: [%d] = %VX64\n", i, xsdt->u64Entry[i]));
612 }
613 xsdt->header.u8Checksum = acpiChecksum ((uint8_t*)xsdt, size);
614 acpiPhyscpy (s, addr, xsdt, size);
615 RTMemFree (xsdt);
616 return VINF_SUCCESS;
617}
618
619/* Root System Description Pointer (RSDP) */
620static void acpiSetupRSDP (ACPITBLRSDP *rsdp, uint32_t rsdt_addr, uint64_t xsdt_addr)
621{
622 memset(rsdp, 0, sizeof(*rsdp));
623
624 /* ACPI 1.0 part (RSDT */
625 memcpy(rsdp->au8Signature, "RSD PTR ", 8);
626 memcpy(rsdp->au8OemId, "VBOX ", 6);
627 rsdp->u8Revision = ACPI_REVISION;
628 rsdp->u32RSDT = RT_H2LE_U32(rsdt_addr);
629 rsdp->u8Checksum = acpiChecksum((uint8_t*)rsdp, RT_OFFSETOF(ACPITBLRSDP, u32Length));
630
631 /* ACPI 2.0 part (XSDT) */
632 rsdp->u32Length = RT_H2LE_U32(sizeof(ACPITBLRSDP));
633 rsdp->u64XSDT = RT_H2LE_U64(xsdt_addr);
634 rsdp->u8ExtChecksum = acpiChecksum ((uint8_t*)rsdp, sizeof(ACPITBLRSDP));
635}
636
637/* Multiple APIC Description Table. */
638/** @todo All hardcoded, should set this up based on the actual VM config!!!!! */
639/** @note APIC without IO-APIC hangs Windows Vista therefore we setup both */
640static void acpiSetupMADT (ACPIState *s, RTGCPHYS32 addr)
641{
642 ACPITBLMADT madt;
643
644 /* Don't call this function if u8UseIOApic==false! */
645 Assert(s->u8UseIOApic);
646
647 memset(&madt, 0, sizeof(madt));
648 acpiPrepareHeader(&madt.header, "APIC", sizeof(madt), 2);
649
650 madt.u32LAPIC = RT_H2LE_U32(0xfee00000);
651 madt.u32Flags = RT_H2LE_U32(PCAT_COMPAT);
652
653 madt.LApic.u8Type = 0;
654 madt.LApic.u8Length = sizeof(ACPITBLLAPIC);
655 madt.LApic.u8ProcId = 0;
656 madt.LApic.u8ApicId = 0;
657 madt.LApic.u32Flags = RT_H2LE_U32(LAPIC_ENABLED);
658
659 madt.IOApic.u8Type = 1;
660 madt.IOApic.u8Length = sizeof(ACPITBLIOAPIC);
661 madt.IOApic.u8IOApicId = 0;
662 madt.IOApic.u8Reserved = 0;
663 madt.IOApic.u32Address = RT_H2LE_U32(0xfec00000);
664 madt.IOApic.u32GSIB = RT_H2LE_U32(0);
665
666 madt.header.u8Checksum = acpiChecksum ((uint8_t*)&madt, sizeof(madt));
667 acpiPhyscpy (s, addr, &madt, sizeof(madt));
668}
669
670/* SCI IRQ */
671DECLINLINE(void) acpiSetIrq (ACPIState *s, int level)
672{
673 if (s->pm1a_ctl & SCI_EN)
674 PDMDevHlpPCISetIrq (s->pDevIns, -1, level);
675}
676
677DECLINLINE(uint32_t) pm1a_pure_en (uint32_t en)
678{
679 return en & ~(RSR_EN | IGN_EN);
680}
681
682DECLINLINE(uint32_t) pm1a_pure_sts (uint32_t sts)
683{
684 return sts & ~(RSR_STS | IGN_STS);
685}
686
687DECLINLINE(int) pm1a_level (ACPIState *s)
688{
689 return (pm1a_pure_en (s->pm1a_en) & pm1a_pure_sts (s->pm1a_sts)) != 0;
690}
691
692DECLINLINE(int) gpe0_level (ACPIState *s)
693{
694 return (s->gpe0_en & s->gpe0_sts) != 0;
695}
696
697static void update_pm1a (ACPIState *s, uint32_t sts, uint32_t en)
698{
699 int old_level, new_level;
700
701 if (gpe0_level (s))
702 return;
703
704 old_level = pm1a_level (s);
705 new_level = (pm1a_pure_en (en) & pm1a_pure_sts (sts)) != 0;
706
707 s->pm1a_en = en;
708 s->pm1a_sts = sts;
709
710 if (new_level != old_level)
711 acpiSetIrq (s, new_level);
712}
713
714static void update_gpe0 (ACPIState *s, uint32_t sts, uint32_t en)
715{
716 int old_level, new_level;
717
718 if (pm1a_level (s))
719 return;
720
721 old_level = (s->gpe0_en & s->gpe0_sts) != 0;
722 new_level = (en & sts) != 0;
723
724 s->gpe0_en = en;
725 s->gpe0_sts = sts;
726
727 if (new_level != old_level)
728 acpiSetIrq (s, new_level);
729}
730
731static int acpiPowerDown (ACPIState *s)
732{
733 int rc = PDMDevHlpVMPowerOff(s->pDevIns);
734 if (RT_FAILURE (rc))
735 AssertMsgFailed (("Could not power down the VM. rc = %Rrc\n", rc));
736 return rc;
737}
738
739/** Converts a ACPI port interface pointer to an ACPI state pointer. */
740#define IACPIPORT_2_ACPISTATE(pInterface) ( (ACPIState*)((uintptr_t)pInterface - RT_OFFSETOF(ACPIState, IACPIPort)) )
741
742/**
743 * Send an ACPI power off event.
744 *
745 * @returns VBox status code
746 * @param pInterface Pointer to the interface structure containing the called function pointer.
747 */
748static DECLCALLBACK(int) acpiPowerButtonPress(PPDMIACPIPORT pInterface)
749{
750 ACPIState *s = IACPIPORT_2_ACPISTATE(pInterface);
751 s->fPowerButtonHandled = false;
752 update_pm1a (s, s->pm1a_sts | PWRBTN_STS, s->pm1a_en);
753 return VINF_SUCCESS;
754}
755
756static DECLCALLBACK(int) acpiGetPowerButtonHandled(PPDMIACPIPORT pInterface, bool *pfHandled)
757{
758 ACPIState *s = IACPIPORT_2_ACPISTATE(pInterface);
759 *pfHandled = s->fPowerButtonHandled;
760 return VINF_SUCCESS;
761}
762
763/**
764 * Send an ACPI sleep button event.
765 *
766 * @returns VBox status code
767 * @param pInterface Pointer to the interface structure containing the called function pointer.
768 */
769static DECLCALLBACK(int) acpiSleepButtonPress(PPDMIACPIPORT pInterface)
770{
771 ACPIState *s = IACPIPORT_2_ACPISTATE(pInterface);
772 update_pm1a (s, s->pm1a_sts | SLPBTN_STS, s->pm1a_en);
773 return VINF_SUCCESS;
774}
775
776/* PM1a_EVT_BLK enable */
777static uint32_t acpiPm1aEnReadw (ACPIState *s, uint32_t addr)
778{
779 uint16_t val = s->pm1a_en;
780 Log (("acpi: acpiPm1aEnReadw -> %#x\n", val));
781 return val;
782}
783
784static void acpiPM1aEnWritew (ACPIState *s, uint32_t addr, uint32_t val)
785{
786 Log (("acpi: acpiPM1aEnWritew <- %#x (%#x)\n", val, val & ~(RSR_EN | IGN_EN)));
787 val &= ~(RSR_EN | IGN_EN);
788 update_pm1a (s, s->pm1a_sts, val);
789}
790
791/* PM1a_EVT_BLK status */
792static uint32_t acpiPm1aStsReadw (ACPIState *s, uint32_t addr)
793{
794 uint16_t val = s->pm1a_sts;
795 Log (("acpi: acpiPm1aStsReadw -> %#x\n", val));
796 return val;
797}
798
799static void acpiPM1aStsWritew (ACPIState *s, uint32_t addr, uint32_t val)
800{
801 Log (("acpi: acpiPM1aStsWritew <- %#x (%#x)\n", val, val & ~(RSR_STS | IGN_STS)));
802 if (val & PWRBTN_STS)
803 s->fPowerButtonHandled = true; /* Remember that the guest handled the last power button event */
804 val = s->pm1a_sts & ~(val & ~(RSR_STS | IGN_STS));
805 update_pm1a (s, val, s->pm1a_en);
806}
807
808/* PM1a_CTL_BLK */
809static uint32_t acpiPm1aCtlReadw (ACPIState *s, uint32_t addr)
810{
811 uint16_t val = s->pm1a_ctl;
812 Log (("acpi: acpiPm1aCtlReadw -> %#x\n", val));
813 return val;
814}
815
816static int acpiPM1aCtlWritew (ACPIState *s, uint32_t addr, uint32_t val)
817{
818 uint32_t uSleepState;
819
820 Log (("acpi: acpiPM1aCtlWritew <- %#x (%#x)\n", val, val & ~(RSR_CNT | IGN_CNT)));
821 s->pm1a_ctl = val & ~(RSR_CNT | IGN_CNT);
822
823 uSleepState = (s->pm1a_ctl >> SLP_TYPx_SHIFT) & SLP_TYPx_MASK;
824 if (uSleepState != s->uSleepState)
825 {
826 s->uSleepState = uSleepState;
827 switch (uSleepState)
828 {
829 case 0x00: /* S0 */
830 break;
831 case 0x05: /* S5 */
832 LogRel (("Entering S5 (power down)\n"));
833 return acpiPowerDown (s);
834 default:
835 AssertMsgFailed (("Unknown sleep state %#x\n", uSleepState));
836 break;
837 }
838 }
839 return VINF_SUCCESS;
840}
841
842/* GPE0_BLK */
843static uint32_t acpiGpe0EnReadb (ACPIState *s, uint32_t addr)
844{
845 uint8_t val = s->gpe0_en;
846 Log (("acpi: acpiGpe0EnReadl -> %#x\n", val));
847 return val;
848}
849
850static void acpiGpe0EnWriteb (ACPIState *s, uint32_t addr, uint32_t val)
851{
852 Log (("acpi: acpiGpe0EnWritel <- %#x\n", val));
853 update_gpe0 (s, s->gpe0_sts, val);
854}
855
856static uint32_t acpiGpe0StsReadb (ACPIState *s, uint32_t addr)
857{
858 uint8_t val = s->gpe0_sts;
859 Log (("acpi: acpiGpe0StsReadl -> %#x\n", val));
860 return val;
861}
862
863static void acpiGpe0StsWriteb (ACPIState *s, uint32_t addr, uint32_t val)
864{
865 val = s->gpe0_sts & ~val;
866 update_gpe0 (s, val, s->gpe0_en);
867 Log (("acpi: acpiGpe0StsWritel <- %#x\n", val));
868}
869
870static int acpiResetWriteU8(ACPIState *s, uint32_t addr, uint32_t val)
871{
872 int rc = VINF_SUCCESS;
873
874 Log(("ACPI: acpiResetWriteU8: %x %x\n", addr, val));
875 if (val == ACPI_RESET_REG_VAL)
876 {
877# ifndef IN_RING3
878 rc = VINF_IOM_HC_IOPORT_WRITE;
879# else /* IN_RING3 */
880 rc = PDMDevHlpVMReset(s->pDevIns);
881# endif /* !IN_RING3 */
882 }
883 return rc;
884}
885
886/* SMI */
887static void acpiSmiWriteU8 (ACPIState *s, uint32_t addr, uint32_t val)
888{
889 Log (("acpi: acpiSmiWriteU8 %#x\n", val));
890 if (val == ACPI_ENABLE)
891 s->pm1a_ctl |= SCI_EN;
892 else if (val == ACPI_DISABLE)
893 s->pm1a_ctl &= ~SCI_EN;
894 else
895 Log (("acpi: acpiSmiWriteU8 %#x <- unknown value\n", val));
896}
897
898static uint32_t find_rsdp_space (void)
899{
900 return 0xe0000;
901}
902
903static void acpiPMTimerReset (ACPIState *s)
904{
905 uint64_t interval, freq;
906
907 freq = TMTimerGetFreq (s->CTX_SUFF(ts));
908 interval = ASMMultU64ByU32DivByU32 (0xffffffff, freq, PM_TMR_FREQ);
909 Log (("interval = %RU64\n", interval));
910 TMTimerSet (s->CTX_SUFF(ts), TMTimerGet (s->CTX_SUFF(ts)) + interval);
911}
912
913static DECLCALLBACK(void) acpiTimer (PPDMDEVINS pDevIns, PTMTIMER pTimer)
914{
915 ACPIState *s = PDMINS_2_DATA (pDevIns, ACPIState *);
916
917 Log (("acpi: pm timer sts %#x (%d), en %#x (%d)\n",
918 s->pm1a_sts, (s->pm1a_sts & TMR_STS) != 0,
919 s->pm1a_en, (s->pm1a_en & TMR_EN) != 0));
920
921 update_pm1a (s, s->pm1a_sts | TMR_STS, s->pm1a_en);
922 acpiPMTimerReset (s);
923}
924
925/**
926 * _BST method.
927 */
928static void acpiFetchBatteryStatus (ACPIState *s)
929{
930 uint32_t *p = s->au8BatteryInfo;
931 bool fPresent; /* battery present? */
932 PDMACPIBATCAPACITY hostRemainingCapacity; /* 0..100 */
933 PDMACPIBATSTATE hostBatteryState; /* bitfield */
934 uint32_t hostPresentRate; /* 0..1000 */
935 int rc;
936
937 if (!s->pDrv)
938 return;
939 rc = s->pDrv->pfnQueryBatteryStatus (s->pDrv, &fPresent, &hostRemainingCapacity,
940 &hostBatteryState, &hostPresentRate);
941 AssertRC (rc);
942
943 /* default values */
944 p[BAT_STATUS_STATE] = hostBatteryState;
945 p[BAT_STATUS_PRESENT_RATE] = hostPresentRate == ~0U ? 0xFFFFFFFF
946 : hostPresentRate * 50; /* mW */
947 p[BAT_STATUS_REMAINING_CAPACITY] = 50000; /* mWh */
948 p[BAT_STATUS_PRESENT_VOLTAGE] = 10000; /* mV */
949
950 /* did we get a valid battery state? */
951 if (hostRemainingCapacity != PDM_ACPI_BAT_CAPACITY_UNKNOWN)
952 p[BAT_STATUS_REMAINING_CAPACITY] = hostRemainingCapacity * 500; /* mWh */
953 if (hostBatteryState == PDM_ACPI_BAT_STATE_CHARGED)
954 p[BAT_STATUS_PRESENT_RATE] = 0; /* mV */
955}
956
957/**
958 * _BIF method.
959 */
960static void acpiFetchBatteryInfo (ACPIState *s)
961{
962 uint32_t *p = s->au8BatteryInfo;
963
964 p[BAT_INFO_UNITS] = 0; /* mWh */
965 p[BAT_INFO_DESIGN_CAPACITY] = 50000; /* mWh */
966 p[BAT_INFO_LAST_FULL_CHARGE_CAPACITY] = 50000; /* mWh */
967 p[BAT_INFO_TECHNOLOGY] = BAT_TECH_PRIMARY;
968 p[BAT_INFO_DESIGN_VOLTAGE] = 10000; /* mV */
969 p[BAT_INFO_DESIGN_CAPACITY_OF_WARNING] = 100; /* mWh */
970 p[BAT_INFO_DESIGN_CAPACITY_OF_LOW] = 50; /* mWh */
971 p[BAT_INFO_CAPACITY_GRANULARITY_1] = 1; /* mWh */
972 p[BAT_INFO_CAPACITY_GRANULARITY_2] = 1; /* mWh */
973}
974
975/**
976 * _STA method.
977 */
978static uint32_t acpiGetBatteryDeviceStatus (ACPIState *s)
979{
980 bool fPresent; /* battery present? */
981 PDMACPIBATCAPACITY hostRemainingCapacity; /* 0..100 */
982 PDMACPIBATSTATE hostBatteryState; /* bitfield */
983 uint32_t hostPresentRate; /* 0..1000 */
984 int rc;
985
986 if (!s->pDrv)
987 return 0;
988 rc = s->pDrv->pfnQueryBatteryStatus (s->pDrv, &fPresent, &hostRemainingCapacity,
989 &hostBatteryState, &hostPresentRate);
990 AssertRC (rc);
991
992 return fPresent
993 ? STA_DEVICE_PRESENT_MASK /* present */
994 | STA_DEVICE_ENABLED_MASK /* enabled and decodes its resources */
995 | STA_DEVICE_SHOW_IN_UI_MASK /* should be shown in UI */
996 | STA_DEVICE_FUNCTIONING_PROPERLY_MASK /* functioning properly */
997 | STA_BATTERY_PRESENT_MASK /* battery is present */
998 : 0; /* device not present */
999}
1000
1001static uint32_t acpiGetPowerSource (ACPIState *s)
1002{
1003 PDMACPIPOWERSOURCE ps;
1004
1005 /* query the current power source from the host driver */
1006 if (!s->pDrv)
1007 return AC_ONLINE;
1008 int rc = s->pDrv->pfnQueryPowerSource (s->pDrv, &ps);
1009 AssertRC (rc);
1010 return ps == PDM_ACPI_POWER_SOURCE_BATTERY ? AC_OFFLINE : AC_ONLINE;
1011}
1012
1013IO_WRITE_PROTO (acpiBatIndexWrite)
1014{
1015 ACPIState *s = (ACPIState *)pvUser;
1016
1017 switch (cb)
1018 {
1019 case 4:
1020 u32 >>= s->u8IndexShift;
1021 /* see comment at the declaration of u8IndexShift */
1022 if (s->u8IndexShift == 0 && u32 == (BAT_DEVICE_STATUS << 2))
1023 {
1024 s->u8IndexShift = 2;
1025 u32 >>= 2;
1026 }
1027 Assert (u32 < BAT_INDEX_LAST);
1028 s->uBatteryIndex = u32;
1029 break;
1030 default:
1031 AssertMsgFailed(("Port=%#x cb=%d u32=%#x\n", Port, cb, u32));
1032 break;
1033 }
1034 return VINF_SUCCESS;
1035}
1036
1037IO_READ_PROTO (acpiBatDataRead)
1038{
1039 ACPIState *s = (ACPIState *)pvUser;
1040
1041 switch (cb)
1042 {
1043 case 4:
1044 switch (s->uBatteryIndex)
1045 {
1046 case BAT_STATUS_STATE:
1047 acpiFetchBatteryStatus(s);
1048 case BAT_STATUS_PRESENT_RATE:
1049 case BAT_STATUS_REMAINING_CAPACITY:
1050 case BAT_STATUS_PRESENT_VOLTAGE:
1051 *pu32 = s->au8BatteryInfo[s->uBatteryIndex];
1052 break;
1053
1054 case BAT_INFO_UNITS:
1055 acpiFetchBatteryInfo(s);
1056 case BAT_INFO_DESIGN_CAPACITY:
1057 case BAT_INFO_LAST_FULL_CHARGE_CAPACITY:
1058 case BAT_INFO_TECHNOLOGY:
1059 case BAT_INFO_DESIGN_VOLTAGE:
1060 case BAT_INFO_DESIGN_CAPACITY_OF_WARNING:
1061 case BAT_INFO_DESIGN_CAPACITY_OF_LOW:
1062 case BAT_INFO_CAPACITY_GRANULARITY_1:
1063 case BAT_INFO_CAPACITY_GRANULARITY_2:
1064 *pu32 = s->au8BatteryInfo[s->uBatteryIndex];
1065 break;
1066
1067 case BAT_DEVICE_STATUS:
1068 *pu32 = acpiGetBatteryDeviceStatus(s);
1069 break;
1070
1071 case BAT_POWER_SOURCE:
1072 *pu32 = acpiGetPowerSource(s);
1073 break;
1074
1075 default:
1076 AssertMsgFailed (("Invalid battery index %d\n", s->uBatteryIndex));
1077 break;
1078 }
1079 break;
1080 default:
1081 return VERR_IOM_IOPORT_UNUSED;
1082 }
1083 return VINF_SUCCESS;
1084}
1085
1086IO_READ_PROTO (acpiFdcStatusRead)
1087{
1088 ACPIState *s = (ACPIState *)pvUser;
1089
1090 switch (cb)
1091 {
1092 case 4:
1093 *pu32 = s->u8UseFdc
1094 ? STA_DEVICE_PRESENT_MASK /* present */
1095 | STA_DEVICE_ENABLED_MASK /* enabled and decodes its resources */
1096 | STA_DEVICE_SHOW_IN_UI_MASK /* should be shown in UI */
1097 | STA_DEVICE_FUNCTIONING_PROPERLY_MASK /* functioning properly */
1098 : 0; /* device not present */
1099 break;
1100 default:
1101 return VERR_IOM_IOPORT_UNUSED;
1102 }
1103 return VINF_SUCCESS;
1104}
1105
1106IO_WRITE_PROTO (acpiSysInfoIndexWrite)
1107{
1108 ACPIState *s = (ACPIState *)pvUser;
1109
1110 Log(("system_index = %d, %d\n", u32, u32 >> 2));
1111 switch (cb) {
1112 case 4:
1113 if (u32 == SYSTEM_INFO_INDEX_VALID || u32 == SYSTEM_INFO_INDEX_INVALID)
1114 s->uSystemInfoIndex = u32;
1115 else
1116 {
1117 u32 >>= s->u8IndexShift;
1118 Assert (u32 < SYSTEM_INFO_INDEX_LAST);
1119 s->uSystemInfoIndex = u32;
1120 }
1121 break;
1122
1123 default:
1124 AssertMsgFailed(("Port=%#x cb=%d u32=%#x\n", Port, cb, u32));
1125 break;
1126 }
1127 return VINF_SUCCESS;
1128}
1129
1130IO_READ_PROTO (acpiSysInfoDataRead)
1131{
1132 ACPIState *s = (ACPIState *)pvUser;
1133
1134 switch (cb)
1135 {
1136 case 4:
1137 switch (s->uSystemInfoIndex)
1138 {
1139 case SYSTEM_INFO_INDEX_MEMORY_LENGTH:
1140 *pu32 = s->u64RamSize;
1141 break;
1142
1143 case SYSTEM_INFO_INDEX_USE_IOAPIC:
1144 *pu32 = s->u8UseIOApic;
1145 break;
1146
1147 default:
1148 AssertMsgFailed (("Invalid system info index %d\n", s->uSystemInfoIndex));
1149 break;
1150 }
1151 break;
1152
1153 default:
1154 return VERR_IOM_IOPORT_UNUSED;
1155 }
1156
1157 Log(("index %d val %d\n", s->uSystemInfoIndex, *pu32));
1158 return VINF_SUCCESS;
1159}
1160
1161IO_WRITE_PROTO (acpiSysInfoDataWrite)
1162{
1163 ACPIState *s = (ACPIState *)pvUser;
1164
1165 Log(("addr=%#x cb=%d u32=%#x si=%#x\n", Port, cb, u32, s->uSystemInfoIndex));
1166
1167 if (cb == 4 && u32 == 0xbadc0de)
1168 {
1169 switch (s->uSystemInfoIndex)
1170 {
1171 case SYSTEM_INFO_INDEX_INVALID:
1172 s->u8IndexShift = 0;
1173 break;
1174
1175 case SYSTEM_INFO_INDEX_VALID:
1176 s->u8IndexShift = 2;
1177 break;
1178
1179 default:
1180 AssertMsgFailed(("Port=%#x cb=%d u32=%#x system_index=%#x\n",
1181 Port, cb, u32, s->uSystemInfoIndex));
1182 break;
1183 }
1184 }
1185 else
1186 AssertMsgFailed(("Port=%#x cb=%d u32=%#x\n", Port, cb, u32));
1187 return VINF_SUCCESS;
1188}
1189
1190/* IO Helpers */
1191IO_READ_PROTO (acpiPm1aEnRead)
1192{
1193 switch (cb)
1194 {
1195 case 2:
1196 *pu32 = acpiPm1aEnReadw ((ACPIState*)pvUser, Port);
1197 break;
1198 default:
1199 return VERR_IOM_IOPORT_UNUSED;
1200 }
1201 return VINF_SUCCESS;
1202}
1203
1204IO_READ_PROTO (acpiPm1aStsRead)
1205{
1206 switch (cb)
1207 {
1208 case 2:
1209 *pu32 = acpiPm1aStsReadw ((ACPIState*)pvUser, Port);
1210 break;
1211 default:
1212 return VERR_IOM_IOPORT_UNUSED;
1213 }
1214 return VINF_SUCCESS;
1215}
1216
1217IO_READ_PROTO (acpiPm1aCtlRead)
1218{
1219 switch (cb)
1220 {
1221 case 2:
1222 *pu32 = acpiPm1aCtlReadw ((ACPIState*)pvUser, Port);
1223 break;
1224 default:
1225 return VERR_IOM_IOPORT_UNUSED;
1226 }
1227 return VINF_SUCCESS;
1228}
1229
1230IO_WRITE_PROTO (acpiPM1aEnWrite)
1231{
1232 switch (cb)
1233 {
1234 case 2:
1235 acpiPM1aEnWritew ((ACPIState*)pvUser, Port, u32);
1236 break;
1237 default:
1238 AssertMsgFailed(("Port=%#x cb=%d u32=%#x\n", Port, cb, u32));
1239 break;
1240 }
1241 return VINF_SUCCESS;
1242}
1243
1244IO_WRITE_PROTO (acpiPM1aStsWrite)
1245{
1246 switch (cb)
1247 {
1248 case 2:
1249 acpiPM1aStsWritew ((ACPIState*)pvUser, Port, u32);
1250 break;
1251 default:
1252 AssertMsgFailed(("Port=%#x cb=%d u32=%#x\n", Port, cb, u32));
1253 break;
1254 }
1255 return VINF_SUCCESS;
1256}
1257
1258IO_WRITE_PROTO (acpiPM1aCtlWrite)
1259{
1260 switch (cb)
1261 {
1262 case 2:
1263 return acpiPM1aCtlWritew ((ACPIState*)pvUser, Port, u32);
1264 default:
1265 AssertMsgFailed(("Port=%#x cb=%d u32=%#x\n", Port, cb, u32));
1266 break;
1267 }
1268 return VINF_SUCCESS;
1269}
1270
1271#endif /* IN_RING3 */
1272
1273/**
1274 * PMTMR readable from host/guest.
1275 */
1276IO_READ_PROTO (acpiPMTmrRead)
1277{
1278 if (cb == 4)
1279 {
1280 ACPIState *s = PDMINS_2_DATA (pDevIns, ACPIState *);
1281 int64_t now = TMTimerGet (s->CTX_SUFF(ts));
1282 int64_t elapsed = now - s->pm_timer_initial;
1283
1284 *pu32 = ASMMultU64ByU32DivByU32 (elapsed, PM_TMR_FREQ, TMTimerGetFreq (s->CTX_SUFF(ts)));
1285 Log (("acpi: acpiPMTmrRead -> %#x\n", *pu32));
1286 return VINF_SUCCESS;
1287 }
1288 return VERR_IOM_IOPORT_UNUSED;
1289}
1290
1291#ifdef IN_RING3
1292
1293IO_READ_PROTO (acpiGpe0StsRead)
1294{
1295 switch (cb)
1296 {
1297 case 1:
1298 *pu32 = acpiGpe0StsReadb ((ACPIState*)pvUser, Port);
1299 break;
1300 default:
1301 return VERR_IOM_IOPORT_UNUSED;
1302 }
1303 return VINF_SUCCESS;
1304}
1305
1306IO_READ_PROTO (acpiGpe0EnRead)
1307{
1308 switch (cb)
1309 {
1310 case 1:
1311 *pu32 = acpiGpe0EnReadb ((ACPIState*)pvUser, Port);
1312 break;
1313 default:
1314 return VERR_IOM_IOPORT_UNUSED;
1315 }
1316 return VINF_SUCCESS;
1317}
1318
1319IO_WRITE_PROTO (acpiGpe0StsWrite)
1320{
1321 switch (cb)
1322 {
1323 case 1:
1324 acpiGpe0StsWriteb ((ACPIState*)pvUser, Port, u32);
1325 break;
1326 default:
1327 AssertMsgFailed(("Port=%#x cb=%d u32=%#x\n", Port, cb, u32));
1328 break;
1329 }
1330 return VINF_SUCCESS;
1331}
1332
1333IO_WRITE_PROTO (acpiGpe0EnWrite)
1334{
1335 switch (cb)
1336 {
1337 case 1:
1338 acpiGpe0EnWriteb ((ACPIState*)pvUser, Port, u32);
1339 break;
1340 default:
1341 AssertMsgFailed(("Port=%#x cb=%d u32=%#x\n", Port, cb, u32));
1342 break;
1343 }
1344 return VINF_SUCCESS;
1345}
1346
1347IO_WRITE_PROTO (acpiSmiWrite)
1348{
1349 switch (cb)
1350 {
1351 case 1:
1352 acpiSmiWriteU8 ((ACPIState*)pvUser, Port, u32);
1353 break;
1354 default:
1355 AssertMsgFailed(("Port=%#x cb=%d u32=%#x\n", Port, cb, u32));
1356 break;
1357 }
1358 return VINF_SUCCESS;
1359}
1360
1361IO_WRITE_PROTO (acpiResetWrite)
1362{
1363 switch (cb)
1364 {
1365 case 1:
1366 return acpiResetWriteU8 ((ACPIState*)pvUser, Port, u32);
1367 default:
1368 AssertMsgFailed(("Port=%#x cb=%d u32=%#x\n", Port, cb, u32));
1369 break;
1370 }
1371 return VINF_SUCCESS;
1372}
1373
1374#ifdef DEBUG_ACPI
1375
1376IO_WRITE_PROTO (acpiDhexWrite)
1377{
1378 switch (cb)
1379 {
1380 case 1:
1381 Log (("%#x\n", u32 & 0xff));
1382 break;
1383 case 2:
1384 Log (("%#6x\n", u32 & 0xffff));
1385 case 4:
1386 Log (("%#10x\n", u32));
1387 break;
1388 default:
1389 AssertMsgFailed(("Port=%#x cb=%d u32=%#x\n", Port, cb, u32));
1390 break;
1391 }
1392 return VINF_SUCCESS;
1393}
1394
1395IO_WRITE_PROTO (acpiDchrWrite)
1396{
1397 switch (cb)
1398 {
1399 case 1:
1400 Log (("%c", u32 & 0xff));
1401 break;
1402 default:
1403 AssertMsgFailed(("Port=%#x cb=%d u32=%#x\n", Port, cb, u32));
1404 break;
1405 }
1406 return VINF_SUCCESS;
1407}
1408
1409#endif /* DEBUG_ACPI */
1410
1411
1412/**
1413 * Saved state structure description.
1414 */
1415static const SSMFIELD g_AcpiSavedStateFields[] =
1416{
1417 SSMFIELD_ENTRY (ACPIState, pm1a_en),
1418 SSMFIELD_ENTRY (ACPIState, pm1a_sts),
1419 SSMFIELD_ENTRY (ACPIState, pm1a_ctl),
1420 SSMFIELD_ENTRY (ACPIState, pm_timer_initial),
1421 SSMFIELD_ENTRY (ACPIState, gpe0_en),
1422 SSMFIELD_ENTRY (ACPIState, gpe0_sts),
1423 SSMFIELD_ENTRY (ACPIState, uBatteryIndex),
1424 SSMFIELD_ENTRY (ACPIState, uSystemInfoIndex),
1425 SSMFIELD_ENTRY (ACPIState, u64RamSize),
1426 SSMFIELD_ENTRY (ACPIState, u8IndexShift),
1427 SSMFIELD_ENTRY (ACPIState, u8UseIOApic),
1428 SSMFIELD_ENTRY (ACPIState, uSleepState),
1429 SSMFIELD_ENTRY_TERM ()
1430};
1431
1432static DECLCALLBACK(int) acpi_save_state (PPDMDEVINS pDevIns, PSSMHANDLE pSSMHandle)
1433{
1434 ACPIState *s = PDMINS_2_DATA (pDevIns, ACPIState *);
1435 return SSMR3PutStruct (pSSMHandle, s, &g_AcpiSavedStateFields[0]);
1436}
1437
1438static DECLCALLBACK(int) acpi_load_state (PPDMDEVINS pDevIns, PSSMHANDLE pSSMHandle,
1439 uint32_t u32Version)
1440{
1441 ACPIState *s = PDMINS_2_DATA (pDevIns, ACPIState *);
1442 int rc;
1443
1444 if (u32Version != 4)
1445 return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
1446
1447 rc = SSMR3GetStruct (pSSMHandle, s, &g_AcpiSavedStateFields[0]);
1448 if (RT_SUCCESS (rc))
1449 {
1450 acpiFetchBatteryStatus (s);
1451 acpiFetchBatteryInfo (s);
1452 acpiPMTimerReset (s);
1453 }
1454 return rc;
1455}
1456
1457/**
1458 * Queries an interface to the driver.
1459 *
1460 * @returns Pointer to interface.
1461 * @returns NULL if the interface was not supported by the driver.
1462 * @param pInterface Pointer to this interface structure.
1463 * @param enmInterface The requested interface identification.
1464 * @thread Any thread.
1465 */
1466static DECLCALLBACK(void *) acpiQueryInterface(PPDMIBASE pInterface, PDMINTERFACE enmInterface)
1467{
1468 ACPIState *pThis = (ACPIState*)((uintptr_t)pInterface - RT_OFFSETOF(ACPIState, IBase));
1469 switch (enmInterface)
1470 {
1471 case PDMINTERFACE_BASE:
1472 return &pThis->IBase;
1473 case PDMINTERFACE_ACPI_PORT:
1474 return &pThis->IACPIPort;
1475 default:
1476 return NULL;
1477 }
1478}
1479
1480/**
1481 * Create the ACPI tables.
1482 */
1483static int acpiPlantTables (ACPIState *s)
1484{
1485 int rc;
1486 RTGCPHYS32 rsdt_addr, xsdt_addr, fadt_addr, facs_addr, dsdt_addr, last_addr, apic_addr = 0;
1487 uint32_t addend = 0;
1488 RTGCPHYS32 rsdt_addrs[4];
1489 uint32_t cAddr;
1490 size_t rsdt_tbl_len = sizeof(ACPITBLHEADER);
1491 size_t xsdt_tbl_len = sizeof(ACPITBLHEADER);
1492
1493 cAddr = 1; /* FADT */
1494 if (s->u8UseIOApic)
1495 cAddr++; /* MADT */
1496
1497 rsdt_tbl_len += cAddr*4; /* each entry: 32 bits phys. address. */
1498 xsdt_tbl_len += cAddr*8; /* each entry: 64 bits phys. address. */
1499
1500 rc = CFGMR3QueryU64 (s->pDevIns->pCfgHandle, "RamSize", &s->u64RamSize);
1501 if (RT_FAILURE (rc))
1502 return PDMDEV_SET_ERROR(s->pDevIns, rc,
1503 N_("Configuration error: Querying "
1504 "\"RamSize\" as integer failed"));
1505
1506 if (s->u64RamSize > (0xffffffff - 0x10000))
1507 return PDMDEV_SET_ERROR(s->pDevIns, VERR_OUT_OF_RANGE,
1508 N_("Configuration error: Invalid \"RamSize\", maximum allowed "
1509 "value is 4095MB"));
1510
1511 rsdt_addr = 0;
1512 xsdt_addr = RT_ALIGN_32 (rsdt_addr + rsdt_tbl_len, 16);
1513 fadt_addr = RT_ALIGN_32 (xsdt_addr + xsdt_tbl_len, 16);
1514 facs_addr = RT_ALIGN_32 (fadt_addr + sizeof(ACPITBLFADT), 16);
1515 if (s->u8UseIOApic)
1516 {
1517 apic_addr = RT_ALIGN_32 (facs_addr + sizeof(ACPITBLFACS), 16);
1518 dsdt_addr = RT_ALIGN_32 (apic_addr + sizeof(ACPITBLMADT), 16);
1519 }
1520 else
1521 {
1522 dsdt_addr = RT_ALIGN_32 (facs_addr + sizeof(ACPITBLFACS), 16);
1523 }
1524
1525 last_addr = RT_ALIGN_32 (dsdt_addr + sizeof(AmlCode), 16);
1526 if (last_addr > 0x10000)
1527 return PDMDEV_SET_ERROR(s->pDevIns, VERR_TOO_MUCH_DATA,
1528 N_("Error: ACPI tables > 64KB"));
1529
1530 Log(("RSDP 0x%08X\n", find_rsdp_space()));
1531 addend = (uint32_t) s->u64RamSize - 0x10000;
1532 Log(("RSDT 0x%08X XSDT 0x%08X\n", rsdt_addr + addend, xsdt_addr + addend));
1533 Log(("FACS 0x%08X FADT 0x%08X\n", facs_addr + addend, fadt_addr + addend));
1534 Log(("DSDT 0x%08X\n", dsdt_addr + addend));
1535 acpiSetupRSDP ((ACPITBLRSDP*)s->au8RSDPPage, rsdt_addr + addend, xsdt_addr + addend);
1536 acpiSetupDSDT (s, dsdt_addr + addend);
1537 acpiSetupFACS (s, facs_addr + addend);
1538 acpiSetupFADT (s, fadt_addr + addend, facs_addr + addend, dsdt_addr + addend);
1539
1540 rsdt_addrs[0] = fadt_addr + addend;
1541 if (s->u8UseIOApic)
1542 {
1543 acpiSetupMADT (s, apic_addr + addend);
1544 rsdt_addrs[1] = apic_addr + addend;
1545 }
1546
1547 rc = acpiSetupRSDT (s, rsdt_addr + addend, cAddr, rsdt_addrs);
1548 if (RT_FAILURE(rc))
1549 return rc;
1550 return acpiSetupXSDT (s, xsdt_addr + addend, cAddr, rsdt_addrs);
1551}
1552
1553/**
1554 * Construct a device instance for a VM.
1555 *
1556 * @returns VBox status.
1557 * @param pDevIns The device instance data.
1558 * If the registration structure is needed, pDevIns->pDevReg points to it.
1559 * @param iInstance Instance number. Use this to figure out which registers and such to use.
1560 * The device number is also found in pDevIns->iInstance, but since it's
1561 * likely to be freqently used PDM passes it as parameter.
1562 * @param pCfgHandle Configuration node handle for the device. Use this to obtain the configuration
1563 * of the device instance. It's also found in pDevIns->pCfgHandle, but like
1564 * iInstance it's expected to be used a bit in this function.
1565 */
1566static DECLCALLBACK(int) acpiConstruct (PPDMDEVINS pDevIns, int iInstance, PCFGMNODE pCfgHandle)
1567{
1568 int rc;
1569 ACPIState *s = PDMINS_2_DATA (pDevIns, ACPIState *);
1570 uint32_t rsdp_addr;
1571 PCIDevice *dev;
1572 bool fGCEnabled;
1573 bool fR0Enabled;
1574
1575 /* Validate and read the configuration. */
1576 if (!CFGMR3AreValuesValid (pCfgHandle, "RamSize\0IOAPIC\0GCEnabled\0R0Enabled\0FdcEnabled\0"))
1577 return PDMDEV_SET_ERROR(pDevIns, VERR_PDM_DEVINS_UNKNOWN_CFG_VALUES,
1578 N_("Configuration error: Invalid config key for ACPI device"));
1579
1580 s->pDevIns = pDevIns;
1581
1582 /* query whether we are supposed to present an IOAPIC */
1583 rc = CFGMR3QueryU8 (pCfgHandle, "IOAPIC", &s->u8UseIOApic);
1584 if (rc == VERR_CFGM_VALUE_NOT_FOUND)
1585 s->u8UseIOApic = 1;
1586 else if (RT_FAILURE (rc))
1587 return PDMDEV_SET_ERROR(pDevIns, rc,
1588 N_("Configuration error: Failed to read \"IOAPIC\""));
1589
1590 /* query whether we are supposed to present an FDC controller */
1591 rc = CFGMR3QueryU8 (pCfgHandle, "FdcEnabled", &s->u8UseFdc);
1592 if (rc == VERR_CFGM_VALUE_NOT_FOUND)
1593 s->u8UseFdc = 1;
1594 else if (RT_FAILURE (rc))
1595 return PDMDEV_SET_ERROR(pDevIns, rc,
1596 N_("Configuration error: Failed to read \"FdcEnabled\""));
1597
1598 rc = CFGMR3QueryBool (pCfgHandle, "GCEnabled", &fGCEnabled);
1599 if (rc == VERR_CFGM_VALUE_NOT_FOUND)
1600 fGCEnabled = true;
1601 else if (RT_FAILURE (rc))
1602 return PDMDEV_SET_ERROR(pDevIns, rc,
1603 N_("Configuration error: Failed to read \"GCEnabled\""));
1604
1605 rc = CFGMR3QueryBool(pCfgHandle, "R0Enabled", &fR0Enabled);
1606 if (rc == VERR_CFGM_VALUE_NOT_FOUND)
1607 fR0Enabled = true;
1608 else if (RT_FAILURE(rc))
1609 return PDMDEV_SET_ERROR(pDevIns, rc,
1610 N_("configuration error: failed to read R0Enabled as boolean"));
1611
1612 /* */
1613 rsdp_addr = find_rsdp_space ();
1614 if (!rsdp_addr)
1615 return PDMDEV_SET_ERROR(pDevIns, VERR_NO_MEMORY,
1616 N_("Can not find space for RSDP. ACPI is disabled"));
1617
1618 rc = acpiPlantTables (s);
1619 if (RT_FAILURE (rc))
1620 return rc;
1621
1622 rc = PDMDevHlpROMRegister (pDevIns, rsdp_addr, 0x1000, s->au8RSDPPage, false /* fShadow */, "ACPI RSDP");
1623 if (RT_FAILURE (rc))
1624 return rc;
1625
1626#define R(addr, cnt, writer, reader, description) \
1627 do { \
1628 rc = PDMDevHlpIOPortRegister (pDevIns, addr, cnt, s, writer, reader, \
1629 NULL, NULL, description); \
1630 if (RT_FAILURE (rc)) \
1631 return rc; \
1632 } while (0)
1633#define L (GPE0_BLK_LEN / 2)
1634
1635 R (PM1a_EVT_BLK+2, 1, acpiPM1aEnWrite, acpiPm1aEnRead, "ACPI PM1a Enable");
1636 R (PM1a_EVT_BLK, 1, acpiPM1aStsWrite, acpiPm1aStsRead, "ACPI PM1a Status");
1637 R (PM1a_CTL_BLK, 1, acpiPM1aCtlWrite, acpiPm1aCtlRead, "ACPI PM1a Control");
1638 R (PM_TMR_BLK, 1, NULL, acpiPMTmrRead, "ACPI PM Timer");
1639 R (SMI_CMD, 1, acpiSmiWrite, NULL, "ACPI SMI");
1640#ifdef DEBUG_ACPI
1641 R (DEBUG_HEX, 1, acpiDhexWrite, NULL, "ACPI Debug hex");
1642 R (DEBUG_CHR, 1, acpiDchrWrite, NULL, "ACPI Debug char");
1643#endif
1644 R (BAT_INDEX, 1, acpiBatIndexWrite, NULL, "ACPI Battery status index");
1645 R (BAT_DATA, 1, NULL, acpiBatDataRead, "ACPI Battery status data");
1646 R (SYSI_INDEX, 1, acpiSysInfoIndexWrite, NULL, "ACPI system info index");
1647 R (SYSI_DATA, 1, acpiSysInfoDataWrite, acpiSysInfoDataRead, "ACPI system info data");
1648 R (FDC_STATUS, 1, NULL, acpiFdcStatusRead, "ACPI FDC status index");
1649 R (GPE0_BLK + L, L, acpiGpe0EnWrite, acpiGpe0EnRead, "ACPI GPE0 Enable");
1650 R (GPE0_BLK, L, acpiGpe0StsWrite, acpiGpe0StsRead, "ACPI GPE0 Status");
1651 R (ACPI_RESET_BLK, 1, acpiResetWrite, NULL, "ACPI Reset");
1652#undef L
1653#undef R
1654
1655 /* register GC stuff */
1656 if (fGCEnabled)
1657 {
1658 rc = PDMDevHlpIOPortRegisterGC (pDevIns, PM_TMR_BLK, 1, 0, NULL, "acpiPMTmrRead",
1659 NULL, NULL, "ACPI PM Timer");
1660 AssertRCReturn(rc, rc);
1661 }
1662
1663 /* register R0 stuff */
1664 if (fR0Enabled)
1665 {
1666 rc = PDMDevHlpIOPortRegisterR0 (pDevIns, PM_TMR_BLK, 1, 0, NULL, "acpiPMTmrRead",
1667 NULL, NULL, "ACPI PM Timer");
1668 AssertRCReturn(rc, rc);
1669 }
1670
1671 rc = PDMDevHlpTMTimerCreate (pDevIns, TMCLOCK_VIRTUAL_SYNC, acpiTimer, "ACPI Timer", &s->tsR3);
1672 if (RT_FAILURE(rc))
1673 {
1674 AssertMsgFailed(("pfnTMTimerCreate -> %Rrc\n", rc));
1675 return rc;
1676 }
1677
1678 s->tsR0 = TMTimerR0Ptr (s->tsR3);
1679 s->tsRC = TMTimerRCPtr (s->tsR3);
1680 s->pm_timer_initial = TMTimerGet (s->tsR3);
1681 acpiPMTimerReset (s);
1682
1683 dev = &s->dev;
1684 dev->config[0x00] = 0x86;
1685 dev->config[0x01] = 0x80;
1686
1687 dev->config[0x02] = 0x13;
1688 dev->config[0x03] = 0x71;
1689
1690 dev->config[0x04] = 0x01;
1691 dev->config[0x05] = 0x00;
1692
1693 dev->config[0x06] = 0x80;
1694 dev->config[0x07] = 0x02;
1695 dev->config[0x08] = 0x08;
1696 dev->config[0x09] = 0x00;
1697
1698 dev->config[0x0a] = 0x80;
1699 dev->config[0x0b] = 0x06;
1700
1701 dev->config[0x0e] = 0x80;
1702 dev->config[0x0f] = 0x00;
1703
1704#if 0 /* The ACPI controller usually has no subsystem ID. */
1705 dev->config[0x2c] = 0x86;
1706 dev->config[0x2d] = 0x80;
1707 dev->config[0x2e] = 0x00;
1708 dev->config[0x2f] = 0x00;
1709#endif
1710 dev->config[0x3c] = SCI_INT;
1711
1712 rc = PDMDevHlpPCIRegister (pDevIns, dev);
1713 if (RT_FAILURE (rc))
1714 return rc;
1715
1716 rc = PDMDevHlpSSMRegister (pDevIns, pDevIns->pDevReg->szDeviceName, iInstance, 4, sizeof(*s),
1717 NULL, acpi_save_state, NULL, NULL, acpi_load_state, NULL);
1718 if (RT_FAILURE(rc))
1719 return rc;
1720
1721 /*
1722 * Interfaces
1723 */
1724 /* IBase */
1725 s->IBase.pfnQueryInterface = acpiQueryInterface;
1726 /* IACPIPort */
1727 s->IACPIPort.pfnSleepButtonPress = acpiSleepButtonPress;
1728 s->IACPIPort.pfnPowerButtonPress = acpiPowerButtonPress;
1729 s->IACPIPort.pfnGetPowerButtonHandled = acpiGetPowerButtonHandled;
1730
1731 /*
1732 * Get the corresponding connector interface
1733 */
1734 rc = PDMDevHlpDriverAttach (pDevIns, 0, &s->IBase, &s->pDrvBase, "ACPI Driver Port");
1735 if (RT_SUCCESS (rc))
1736 {
1737 s->pDrv = (PPDMIACPICONNECTOR)s->pDrvBase->pfnQueryInterface (s->pDrvBase,
1738 PDMINTERFACE_ACPI_CONNECTOR);
1739 if (!s->pDrv)
1740 return PDMDEV_SET_ERROR(pDevIns, VERR_PDM_MISSING_INTERFACE,
1741 N_("LUN #0 doesn't have an ACPI connector interface"));
1742 }
1743 else if (rc == VERR_PDM_NO_ATTACHED_DRIVER)
1744 {
1745 Log (("acpi: %s/%d: warning: no driver attached to LUN #0!\n",
1746 pDevIns->pDevReg->szDeviceName, pDevIns->iInstance));
1747 rc = VINF_SUCCESS;
1748 }
1749 else
1750 return PDMDEV_SET_ERROR(pDevIns, rc,
1751 N_("Failed to attach LUN #0"));
1752
1753 return rc;
1754}
1755
1756/**
1757 * Relocates the GC pointer members.
1758 */
1759static DECLCALLBACK(void) acpiRelocate (PPDMDEVINS pDevIns, RTGCINTPTR offDelta)
1760{
1761 ACPIState *s = PDMINS_2_DATA (pDevIns, ACPIState *);
1762 s->tsRC = TMTimerGCPtr (s->CTX_SUFF(ts));
1763}
1764
1765static DECLCALLBACK(void) acpiReset (PPDMDEVINS pDevIns)
1766{
1767 ACPIState *s = PDMINS_2_DATA (pDevIns, ACPIState *);
1768
1769 s->pm1a_en = 0;
1770 s->pm1a_sts = 0;
1771 s->pm1a_ctl = 0;
1772 s->pm_timer_initial = TMTimerGet (s->CTX_SUFF(ts));
1773 acpiPMTimerReset(s);
1774 s->uBatteryIndex = 0;
1775 s->uSystemInfoIndex = 0;
1776 s->gpe0_en = 0;
1777 s->gpe0_sts = 0;
1778 s->uSleepState = 0;
1779
1780 acpiPlantTables(s);
1781}
1782
1783/**
1784 * The device registration structure.
1785 */
1786const PDMDEVREG g_DeviceACPI =
1787{
1788 /* u32Version */
1789 PDM_DEVREG_VERSION,
1790 /* szDeviceName */
1791 "acpi",
1792 /* szGCMod */
1793 "VBoxDDGC.gc",
1794 /* szR0Mod */
1795 "VBoxDDR0.r0",
1796 /* pszDescription */
1797 "Advanced Configuration and Power Interface",
1798 /* fFlags */
1799 PDM_DEVREG_FLAGS_HOST_BITS_DEFAULT | PDM_DEVREG_FLAGS_GUEST_BITS_DEFAULT | PDM_DEVREG_FLAGS_GC | PDM_DEVREG_FLAGS_R0,
1800 /* fClass */
1801 PDM_DEVREG_CLASS_ACPI,
1802 /* cMaxInstances */
1803 ~0,
1804 /* cbInstance */
1805 sizeof(ACPIState),
1806 /* pfnConstruct */
1807 acpiConstruct,
1808 /* pfnDestruct */
1809 NULL,
1810 /* pfnRelocate */
1811 acpiRelocate,
1812 /* pfnIOCtl */
1813 NULL,
1814 /* pfnPowerOn */
1815 NULL,
1816 /* pfnReset */
1817 acpiReset,
1818 /* pfnSuspend */
1819 NULL,
1820 /* pfnResume */
1821 NULL,
1822 /* pfnAttach */
1823 NULL,
1824 /* pfnDetach */
1825 NULL,
1826 /* pfnQueryInterface. */
1827 NULL
1828};
1829
1830#endif /* IN_RING3 */
1831#endif /* !VBOX_DEVICE_STRUCT_TESTCASE */
1832
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