VirtualBox

source: vbox/trunk/src/VBox/Devices/PC/DevACPI.cpp@ 106842

Last change on this file since 106842 was 106061, checked in by vboxsync, 3 months ago

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1/* $Id: DevACPI.cpp 106061 2024-09-16 14:03:52Z vboxsync $ */
2/** @file
3 * DevACPI - Advanced Configuration and Power Interface (ACPI) Device.
4 */
5
6/*
7 * Copyright (C) 2006-2024 Oracle and/or its affiliates.
8 *
9 * This file is part of VirtualBox base platform packages, as
10 * available from https://www.virtualbox.org.
11 *
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License
14 * as published by the Free Software Foundation, in version 3 of the
15 * License.
16 *
17 * This program is distributed in the hope that it will be useful, but
18 * WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
20 * General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, see <https://www.gnu.org/licenses>.
24 *
25 * SPDX-License-Identifier: GPL-3.0-only
26 */
27
28
29/*********************************************************************************************************************************
30* Header Files *
31*********************************************************************************************************************************/
32#define LOG_GROUP LOG_GROUP_DEV_ACPI
33#include <VBox/vmm/pdmdev.h>
34#include <VBox/vmm/pgm.h>
35#include <VBox/vmm/dbgftrace.h>
36#include <VBox/vmm/vmcpuset.h>
37#include <VBox/AssertGuest.h>
38#include <VBox/log.h>
39#include <VBox/param.h>
40#include <VBox/pci.h>
41#include <iprt/assert.h>
42#include <iprt/asm.h>
43#include <iprt/asm-math.h>
44#include <iprt/file.h>
45#ifdef IN_RING3
46# include <iprt/alloc.h>
47# include <iprt/string.h>
48# include <iprt/uuid.h>
49#endif /* IN_RING3 */
50#ifdef VBOX_WITH_IOMMU_AMD
51# include <VBox/iommu-amd.h>
52#endif
53#ifdef VBOX_WITH_IOMMU_INTEL
54# include <VBox/iommu-intel.h>
55#endif
56
57#include "VBoxDD.h"
58#ifdef VBOX_WITH_IOMMU_AMD
59# include "../Bus/DevIommuAmd.h"
60#endif
61#ifdef VBOX_WITH_IOMMU_INTEL
62# include "../Bus/DevIommuIntel.h"
63#endif
64
65#ifdef LOG_ENABLED
66# define DEBUG_ACPI
67#endif
68
69
70/*********************************************************************************************************************************
71* Defined Constants And Macros *
72*********************************************************************************************************************************/
73#ifdef IN_RING3
74/** Locks the device state, ring-3 only. */
75# define DEVACPI_LOCK_R3(a_pDevIns, a_pThis) \
76 do { \
77 int rcLock = PDMDevHlpCritSectEnter((a_pDevIns), &(a_pThis)->CritSect, VERR_IGNORED); \
78 PDM_CRITSECT_RELEASE_ASSERT_RC_DEV((a_pDevIns), &(a_pThis)->CritSect, rcLock); \
79 } while (0)
80#endif
81/** Unlocks the device state (all contexts). */
82#define DEVACPI_UNLOCK(a_pDevIns, a_pThis) \
83 do { PDMDevHlpCritSectLeave((a_pDevIns), &(a_pThis)->CritSect); } while (0)
84
85
86#define DEBUG_HEX 0x3000
87#define DEBUG_CHR 0x3001
88
89/** PM Base Address PCI config space offset */
90#define PMBA 0x40
91/** PM Miscellaneous Power Management PCI config space offset */
92#define PMREGMISC 0x80
93
94#define PM_TMR_FREQ 3579545
95/** Default base for PM PIIX4 device */
96#define PM_PORT_BASE 0x4000
97/* Port offsets in PM device */
98enum
99{
100 PM1a_EVT_OFFSET = 0x00,
101 PM1b_EVT_OFFSET = -1, /**< not supported */
102 PM1a_CTL_OFFSET = 0x04,
103 PM1b_CTL_OFFSET = -1, /**< not supported */
104 PM2_CTL_OFFSET = -1, /**< not supported */
105 PM_TMR_OFFSET = 0x08,
106 GPE0_OFFSET = 0x20,
107 GPE1_OFFSET = -1 /**< not supported */
108};
109
110/* Maximum supported number of custom ACPI tables */
111#define MAX_CUST_TABLES 4
112
113/* Undef this to enable 24 bit PM timer (mostly for debugging purposes) */
114#define PM_TMR_32BIT
115
116#define BAT_INDEX 0x00004040
117#define BAT_DATA 0x00004044
118#define SYSI_INDEX 0x00004048
119#define SYSI_DATA 0x0000404c
120#define ACPI_RESET_BLK 0x00004050
121
122/* PM1x status register bits */
123#define TMR_STS RT_BIT(0)
124#define RSR1_STS (RT_BIT(1) | RT_BIT(2) | RT_BIT(3))
125#define BM_STS RT_BIT(4)
126#define GBL_STS RT_BIT(5)
127#define RSR2_STS (RT_BIT(6) | RT_BIT(7))
128#define PWRBTN_STS RT_BIT(8)
129#define SLPBTN_STS RT_BIT(9)
130#define RTC_STS RT_BIT(10)
131#define IGN_STS RT_BIT(11)
132#define RSR3_STS (RT_BIT(12) | RT_BIT(13) | RT_BIT(14))
133#define WAK_STS RT_BIT(15)
134#define RSR_STS (RSR1_STS | RSR2_STS | RSR3_STS)
135
136/* PM1x enable register bits */
137#define TMR_EN RT_BIT(0)
138#define RSR1_EN (RT_BIT(1) | RT_BIT(2) | RT_BIT(3) | RT_BIT(4))
139#define GBL_EN RT_BIT(5)
140#define RSR2_EN (RT_BIT(6) | RT_BIT(7))
141#define PWRBTN_EN RT_BIT(8)
142#define SLPBTN_EN RT_BIT(9)
143#define RTC_EN RT_BIT(10)
144#define RSR3_EN (RT_BIT(11) | RT_BIT(12) | RT_BIT(13) | RT_BIT(14) | RT_BIT(15))
145#define RSR_EN (RSR1_EN | RSR2_EN | RSR3_EN)
146#define IGN_EN 0
147
148/* PM1x control register bits */
149#define SCI_EN RT_BIT(0)
150#define BM_RLD RT_BIT(1)
151#define GBL_RLS RT_BIT(2)
152#define RSR1_CNT (RT_BIT(3) | RT_BIT(4) | RT_BIT(5) | RT_BIT(6) | RT_BIT(7) | RT_BIT(8))
153#define IGN_CNT RT_BIT(9)
154#define SLP_TYPx_SHIFT 10
155#define SLP_TYPx_MASK 7
156#define SLP_EN RT_BIT(13)
157#define RSR2_CNT (RT_BIT(14) | RT_BIT(15))
158#define RSR_CNT (RSR1_CNT | RSR2_CNT)
159
160#define GPE0_BATTERY_INFO_CHANGED RT_BIT(0)
161
162enum
163{
164 BAT_STATUS_STATE = 0x00, /**< BST battery state */
165 BAT_STATUS_PRESENT_RATE = 0x01, /**< BST battery present rate */
166 BAT_STATUS_REMAINING_CAPACITY = 0x02, /**< BST battery remaining capacity */
167 BAT_STATUS_PRESENT_VOLTAGE = 0x03, /**< BST battery present voltage */
168 BAT_INFO_UNITS = 0x04, /**< BIF power unit */
169 BAT_INFO_DESIGN_CAPACITY = 0x05, /**< BIF design capacity */
170 BAT_INFO_LAST_FULL_CHARGE_CAPACITY = 0x06, /**< BIF last full charge capacity */
171 BAT_INFO_TECHNOLOGY = 0x07, /**< BIF battery technology */
172 BAT_INFO_DESIGN_VOLTAGE = 0x08, /**< BIF design voltage */
173 BAT_INFO_DESIGN_CAPACITY_OF_WARNING = 0x09, /**< BIF design capacity of warning */
174 BAT_INFO_DESIGN_CAPACITY_OF_LOW = 0x0A, /**< BIF design capacity of low */
175 BAT_INFO_CAPACITY_GRANULARITY_1 = 0x0B, /**< BIF battery capacity granularity 1 */
176 BAT_INFO_CAPACITY_GRANULARITY_2 = 0x0C, /**< BIF battery capacity granularity 2 */
177 BAT_DEVICE_STATUS = 0x0D, /**< STA device status */
178 BAT_POWER_SOURCE = 0x0E, /**< PSR power source */
179 BAT_INDEX_LAST
180};
181
182enum
183{
184 CPU_EVENT_TYPE_ADD = 0x01, /**< Event type add */
185 CPU_EVENT_TYPE_REMOVE = 0x03 /**< Event type remove */
186};
187
188enum
189{
190 SYSTEM_INFO_INDEX_LOW_MEMORY_LENGTH = 0,
191 SYSTEM_INFO_INDEX_USE_IOAPIC = 1,
192 SYSTEM_INFO_INDEX_HPET_STATUS = 2,
193 SYSTEM_INFO_INDEX_SMC_STATUS = 3,
194 SYSTEM_INFO_INDEX_FDC_STATUS = 4,
195 SYSTEM_INFO_INDEX_SERIAL2_IOBASE = 5,
196 SYSTEM_INFO_INDEX_SERIAL2_IRQ = 6,
197 SYSTEM_INFO_INDEX_SERIAL3_IOBASE = 7,
198 SYSTEM_INFO_INDEX_SERIAL3_IRQ = 8,
199 SYSTEM_INFO_INDEX_PREF64_MEMORY_MIN = 9,
200 SYSTEM_INFO_INDEX_RTC_STATUS = 10,
201 SYSTEM_INFO_INDEX_CPU_LOCKED = 11, /**< Contains a flag indicating whether the CPU is locked or not */
202 SYSTEM_INFO_INDEX_CPU_LOCK_CHECK = 12, /**< For which CPU the lock status should be checked */
203 SYSTEM_INFO_INDEX_CPU_EVENT_TYPE = 13, /**< Type of the CPU hot-plug event */
204 SYSTEM_INFO_INDEX_CPU_EVENT = 14, /**< The CPU id the event is for */
205 SYSTEM_INFO_INDEX_NIC_ADDRESS = 15, /**< NIC PCI address, or 0 */
206 SYSTEM_INFO_INDEX_AUDIO_ADDRESS = 16, /**< Audio card PCI address, or 0 */
207 SYSTEM_INFO_INDEX_POWER_STATES = 17,
208 SYSTEM_INFO_INDEX_IOC_ADDRESS = 18, /**< IO controller PCI address */
209 SYSTEM_INFO_INDEX_HBC_ADDRESS = 19, /**< host bus controller PCI address */
210 SYSTEM_INFO_INDEX_PCI_BASE = 20, /**< PCI bus MCFG MMIO range base */
211 SYSTEM_INFO_INDEX_PCI_LENGTH = 21, /**< PCI bus MCFG MMIO range length */
212 SYSTEM_INFO_INDEX_SERIAL0_IOBASE = 22,
213 SYSTEM_INFO_INDEX_SERIAL0_IRQ = 23,
214 SYSTEM_INFO_INDEX_SERIAL1_IOBASE = 24,
215 SYSTEM_INFO_INDEX_SERIAL1_IRQ = 25,
216 SYSTEM_INFO_INDEX_PARALLEL0_IOBASE = 26,
217 SYSTEM_INFO_INDEX_PARALLEL0_IRQ = 27,
218 SYSTEM_INFO_INDEX_PARALLEL1_IOBASE = 28,
219 SYSTEM_INFO_INDEX_PARALLEL1_IRQ = 29,
220 SYSTEM_INFO_INDEX_PREF64_MEMORY_MAX = 30,
221 SYSTEM_INFO_INDEX_NVME_ADDRESS = 31, /**< First NVMe controller PCI address, or 0 */
222 SYSTEM_INFO_INDEX_IOMMU_ADDRESS = 32, /**< IOMMU PCI address, or 0 */
223 SYSTEM_INFO_INDEX_SB_IOAPIC_ADDRESS = 33, /**< Southbridge I/O APIC (needed by AMD IOMMU) PCI address, or 0 */
224 SYSTEM_INFO_INDEX_END = 34,
225 SYSTEM_INFO_INDEX_INVALID = 0x80,
226 SYSTEM_INFO_INDEX_VALID = 0x200
227};
228
229#define AC_OFFLINE 0
230#define AC_ONLINE 1
231
232#define BAT_TECH_PRIMARY 1
233#define BAT_TECH_SECONDARY 2
234
235#define STA_DEVICE_PRESENT_MASK RT_BIT(0) /**< present */
236#define STA_DEVICE_ENABLED_MASK RT_BIT(1) /**< enabled and decodes its resources */
237#define STA_DEVICE_SHOW_IN_UI_MASK RT_BIT(2) /**< should be shown in UI */
238#define STA_DEVICE_FUNCTIONING_PROPERLY_MASK RT_BIT(3) /**< functioning properly */
239#define STA_BATTERY_PRESENT_MASK RT_BIT(4) /**< the battery is present */
240
241/** SMBus Base Address PCI config space offset */
242#define SMBBA 0x90
243/** SMBus Host Configuration PCI config space offset */
244#define SMBHSTCFG 0xd2
245/** SMBus Slave Command PCI config space offset */
246#define SMBSLVC 0xd3
247/** SMBus Slave Shadow Port 1 PCI config space offset */
248#define SMBSHDW1 0xd4
249/** SMBus Slave Shadow Port 2 PCI config space offset */
250#define SMBSHDW2 0xd5
251/** SMBus Revision Identification PCI config space offset */
252#define SMBREV 0xd6
253
254#define SMBHSTCFG_SMB_HST_EN RT_BIT(0)
255#define SMBHSTCFG_INTRSEL (RT_BIT(1) | RT_BIT(2) | RT_BIT(3))
256#define SMBHSTCFG_INTRSEL_SMI 0
257#define SMBHSTCFG_INTRSEL_IRQ9 4
258#define SMBHSTCFG_INTRSEL_SHIFT 1
259
260/** Default base for SMBus PIIX4 device */
261#define SMB_PORT_BASE 0x4100
262
263/** SMBus Host Status Register I/O offset */
264#define SMBHSTSTS_OFF 0x0000
265/** SMBus Slave Status Register I/O offset */
266#define SMBSLVSTS_OFF 0x0001
267/** SMBus Host Count Register I/O offset */
268#define SMBHSTCNT_OFF 0x0002
269/** SMBus Host Command Register I/O offset */
270#define SMBHSTCMD_OFF 0x0003
271/** SMBus Host Address Register I/O offset */
272#define SMBHSTADD_OFF 0x0004
273/** SMBus Host Data 0 Register I/O offset */
274#define SMBHSTDAT0_OFF 0x0005
275/** SMBus Host Data 1 Register I/O offset */
276#define SMBHSTDAT1_OFF 0x0006
277/** SMBus Block Data Register I/O offset */
278#define SMBBLKDAT_OFF 0x0007
279/** SMBus Slave Control Register I/O offset */
280#define SMBSLVCNT_OFF 0x0008
281/** SMBus Shadow Command Register I/O offset */
282#define SMBSHDWCMD_OFF 0x0009
283/** SMBus Slave Event Register I/O offset */
284#define SMBSLVEVT_OFF 0x000a
285/** SMBus Slave Data Register I/O offset */
286#define SMBSLVDAT_OFF 0x000c
287
288#define SMBHSTSTS_HOST_BUSY RT_BIT(0)
289#define SMBHSTSTS_INTER RT_BIT(1)
290#define SMBHSTSTS_DEV_ERR RT_BIT(2)
291#define SMBHSTSTS_BUS_ERR RT_BIT(3)
292#define SMBHSTSTS_FAILED RT_BIT(4)
293#define SMBHSTSTS_INT_MASK (SMBHSTSTS_INTER | SMBHSTSTS_DEV_ERR | SMBHSTSTS_BUS_ERR | SMBHSTSTS_FAILED)
294
295#define SMBSLVSTS_WRITE_MASK 0x3c
296
297#define SMBHSTCNT_INTEREN RT_BIT(0)
298#define SMBHSTCNT_KILL RT_BIT(1)
299#define SMBHSTCNT_CMD_PROT (RT_BIT(2) | RT_BIT(3) | RT_BIT(4))
300#define SMBHSTCNT_START RT_BIT(6)
301#define SMBHSTCNT_WRITE_MASK (SMBHSTCNT_INTEREN | SMBHSTCNT_KILL | SMBHSTCNT_CMD_PROT)
302
303#define SMBSLVCNT_WRITE_MASK (RT_BIT(0) | RT_BIT(1) | RT_BIT(2) | RT_BIT(3))
304
305
306/*********************************************************************************************************************************
307* Structures and Typedefs *
308*********************************************************************************************************************************/
309/**
310 * The TPM mode configured.
311 */
312typedef enum ACPITPMMODE
313{
314 ACPITPMMODE_INVALID = 0,
315 ACPITPMMODE_DISABLED,
316 ACPITPMMODE_TIS_1_2,
317 ACPITPMMODE_CRB_2_0,
318 ACPITPMMODE_FIFO_2_0,
319 ACPITPMMODE_32BIT_HACK = 0x7fffffff
320} ACPITPMMODE;
321
322
323/**
324 * The shared ACPI device state.
325 */
326typedef struct ACPISTATE
327{
328 /** Critical section protecting the ACPI state. */
329 PDMCRITSECT CritSect;
330
331 uint16_t pm1a_en;
332 uint16_t pm1a_sts;
333 uint16_t pm1a_ctl;
334 /** Number of logical CPUs in guest */
335 uint16_t cCpus;
336
337 uint64_t u64PmTimerInitial;
338 /** The PM timer. */
339 TMTIMERHANDLE hPmTimer;
340 /* PM Timer last calculated value */
341 uint32_t uPmTimerVal;
342 uint32_t Alignment0;
343
344 uint32_t gpe0_en;
345 uint32_t gpe0_sts;
346
347 uint32_t uBatteryIndex;
348 uint32_t au8BatteryInfo[13];
349
350 uint32_t uSystemInfoIndex;
351 uint32_t u32Alignment0;
352 uint64_t u64RamSize;
353 /** Offset of the 64-bit prefetchable memory window. */
354 uint64_t u64PciPref64Min;
355 /** Limit of the 64-bit prefetchable memory window. */
356 uint64_t u64PciPref64Max;
357 /** The number of bytes below 4GB. */
358 uint32_t cbRamLow;
359
360 /** Current ACPI S* state. We support S0 and S5. */
361 uint32_t uSleepState;
362 uint8_t au8RSDPPage[0x1000];
363 /** This is a workaround for incorrect index field handling by Intels ACPICA.
364 * The system info _INI method writes to offset 0x200. We either observe a
365 * write request to index 0x80 (in that case we don't change the index) or a
366 * write request to offset 0x200 (in that case we divide the index value by
367 * 4. Note that the _STA method is sometimes called prior to the _INI method
368 * (ACPI spec 6.3.7, _STA). See the special case for BAT_DEVICE_STATUS in
369 * acpiR3BatIndexWrite() for handling this. */
370 uint8_t u8IndexShift;
371 /** provide an I/O-APIC */
372 uint8_t u8UseIOApic;
373 /** provide a floppy controller */
374 bool fUseFdc;
375 /** If High Precision Event Timer device should be supported */
376 bool fUseHpet;
377 /** If System Management Controller device should be supported */
378 bool fUseSmc;
379 /** the guest handled the last power button event */
380 bool fPowerButtonHandled;
381 /** If ACPI CPU device should be shown */
382 bool fShowCpu;
383 /** If Real Time Clock ACPI object to be shown */
384 bool fShowRtc;
385 /** I/O port address of PM device. */
386 RTIOPORT uPmIoPortBase;
387 /** I/O port address of SMBus device. */
388 RTIOPORT uSMBusIoPortBase;
389 /** Which CPU to check for the locked status. */
390 uint32_t idCpuLockCheck;
391 /** Array of flags of attached CPUs */
392 VMCPUSET CpuSetAttached;
393 /** Mask of locked CPUs (used by the guest). */
394 VMCPUSET CpuSetLocked;
395 /** The CPU event type. */
396 uint32_t u32CpuEventType;
397 /** The CPU id affected. */
398 uint32_t u32CpuEvent;
399 /** Flag whether CPU hot plugging is enabled. */
400 bool fCpuHotPlug;
401 /** If MCFG ACPI table shown to the guest */
402 bool fUseMcfg;
403 /** if the 64-bit prefetchable memory window is shown to the guest */
404 bool fPciPref64Enabled;
405 /** If the IOMMU (AMD) device should be enabled */
406 bool fUseIommuAmd;
407 /** If the IOMMU (Intel) device should be enabled */
408 bool fUseIommuIntel;
409 /** Padding. */
410 bool afPadding0[3];
411 /** Primary NIC PCI address. */
412 uint32_t u32NicPciAddress;
413 /** HD Audio PCI address. */
414 uint32_t u32AudioPciAddress;
415 /** Primary NVMe controller PCI address. */
416 uint32_t u32NvmePciAddress;
417 /** Flag whether S1 power state is enabled. */
418 bool fS1Enabled;
419 /** Flag whether S4 power state is enabled. */
420 bool fS4Enabled;
421 /** Flag whether S1 triggers a state save. */
422 bool fSuspendToSavedState;
423 /** Flag whether to set WAK_STS on resume (restore included). */
424 bool fSetWakeupOnResume;
425 /** PCI address of the IO controller device. */
426 uint32_t u32IocPciAddress;
427 /** PCI address of the host bus controller device. */
428 uint32_t u32HbcPciAddress;
429 /** PCI address of the IOMMU device. */
430 uint32_t u32IommuPciAddress;
431 /** PCI address of the southbridge I/O APIC device. */
432 uint32_t u32SbIoApicPciAddress;
433
434 /** Physical address of PCI config space MMIO region */
435 uint64_t u64PciConfigMMioAddress;
436 /** Length of PCI config space MMIO region */
437 uint64_t u64PciConfigMMioLength;
438 /** Serial 0 IRQ number */
439 uint8_t uSerial0Irq;
440 /** Serial 1 IRQ number */
441 uint8_t uSerial1Irq;
442 /** Serial 2 IRQ number */
443 uint8_t uSerial2Irq;
444 /** Serial 3 IRQ number */
445 uint8_t uSerial3Irq;
446 /** Serial 0 IO port base */
447 RTIOPORT uSerial0IoPortBase;
448 /** Serial 1 IO port base */
449 RTIOPORT uSerial1IoPortBase;
450 /** Serial 2 IO port base */
451 RTIOPORT uSerial2IoPortBase;
452 /** Serial 3 IO port base */
453 RTIOPORT uSerial3IoPortBase;
454
455 /** @name Parallel port config bits
456 * @{ */
457 /** Parallel 0 IO port base */
458 RTIOPORT uParallel0IoPortBase;
459 /** Parallel 1 IO port base */
460 RTIOPORT uParallel1IoPortBase;
461 /** Parallel 0 IRQ number */
462 uint8_t uParallel0Irq;
463 /** Parallel 1 IRQ number */
464 uint8_t uParallel1Irq;
465 /** @} */
466
467#ifdef VBOX_WITH_TPM
468 /** @name TPM config bits
469 * @{ */
470 /** The ACPI TPM mode configured. */
471 ACPITPMMODE enmTpmMode;
472 /** The MMIO register area base address. */
473 RTGCPHYS GCPhysTpmMmio;
474 /** @} */
475#endif
476
477 /** Number of custom ACPI tables */
478 uint8_t cCustTbls;
479 /** ACPI OEM ID */
480 uint8_t au8OemId[6];
481 /** ACPI Crator ID */
482 uint8_t au8CreatorId[4];
483 uint8_t abAlignment2[3];
484 /** ACPI Crator Rev */
485 uint32_t u32CreatorRev;
486 /** ACPI custom OEM Tab ID */
487 uint8_t au8OemTabId[8];
488 /** ACPI custom OEM Rev */
489 uint32_t u32OemRevision;
490
491 /** SMBus Host Status Register */
492 uint8_t u8SMBusHstSts;
493 /** SMBus Slave Status Register */
494 uint8_t u8SMBusSlvSts;
495 /** SMBus Host Control Register */
496 uint8_t u8SMBusHstCnt;
497 /** SMBus Host Command Register */
498 uint8_t u8SMBusHstCmd;
499 /** SMBus Host Address Register */
500 uint8_t u8SMBusHstAdd;
501 /** SMBus Host Data 0 Register */
502 uint8_t u8SMBusHstDat0;
503 /** SMBus Host Data 1 Register */
504 uint8_t u8SMBusHstDat1;
505 /** SMBus Slave Control Register */
506 uint8_t u8SMBusSlvCnt;
507 /** SMBus Slave Event Register */
508 uint16_t u16SMBusSlvEvt;
509 /** SMBus Slave Data Register */
510 uint16_t u16SMBusSlvDat;
511 /** SMBus Shadow Command Register */
512 uint8_t u8SMBusShdwCmd;
513 /** SMBus Host Block Index */
514 uint8_t u8SMBusBlkIdx;
515 uint8_t abAlignment3[2];
516 /** SMBus Host Block Data Buffer */
517 uint8_t au8SMBusBlkDat[32];
518
519 /** @todo DEBUGGING */
520 uint32_t uPmTimeOld;
521 uint32_t uPmTimeA;
522 uint32_t uPmTimeB;
523 uint32_t Alignment5;
524
525 /** @name PM1a, PM timer and GPE0 I/O ports - mapped/unmapped as a group.
526 * @{ */
527 IOMIOPORTHANDLE hIoPortPm1aEn;
528 IOMIOPORTHANDLE hIoPortPm1aSts;
529 IOMIOPORTHANDLE hIoPortPm1aCtl;
530 IOMIOPORTHANDLE hIoPortPmTimer;
531 IOMIOPORTHANDLE hIoPortGpe0En;
532 IOMIOPORTHANDLE hIoPortGpe0Sts;
533 /** @} */
534
535 /** SMBus I/O ports (mapped/unmapped). */
536 IOMIOPORTHANDLE hIoPortSMBus;
537
538 /** @name Fixed I/O ports
539 * @{ */
540 /** ACPI SMI I/O port. */
541 IOMIOPORTHANDLE hIoPortSmi;
542 /** ACPI Debug hex I/O port. */
543 IOMIOPORTHANDLE hIoPortDebugHex;
544 /** ACPI Debug char I/O port. */
545 IOMIOPORTHANDLE hIoPortDebugChar;
546 /** ACPI Battery status index I/O port. */
547 IOMIOPORTHANDLE hIoPortBatteryIndex;
548 /** ACPI Battery status data I/O port. */
549 IOMIOPORTHANDLE hIoPortBatteryData;
550 /** ACPI system info index I/O port. */
551 IOMIOPORTHANDLE hIoPortSysInfoIndex;
552 /** ACPI system info data I/O port. */
553 IOMIOPORTHANDLE hIoPortSysInfoData;
554 /** ACPI Reset I/O port. */
555 IOMIOPORTHANDLE hIoPortReset;
556 /** @} */
557
558} ACPISTATE;
559/** Pointer to the shared ACPI device state. */
560typedef ACPISTATE *PACPISTATE;
561
562
563
564/**
565 * The ring-3 ACPI device state.
566 */
567typedef struct ACPISTATER3
568{
569 /** ACPI port base interface. */
570 PDMIBASE IBase;
571 /** ACPI port interface. */
572 PDMIACPIPORT IACPIPort;
573 /** The button event interface for power button events. */
574 PDMIEVENTBUTTONPORT IButtonEventPort;
575 /** Pointer to the device instance so we can get our bearings from
576 * interface functions. */
577 PPDMDEVINSR3 pDevIns;
578
579 /** Pointer to the driver base interface. */
580 R3PTRTYPE(PPDMIBASE) pDrvBase;
581 /** Pointer to the driver connector interface. */
582 R3PTRTYPE(PPDMIACPICONNECTOR) pDrv;
583
584 /** Custom ACPI tables binary data. */
585 R3PTRTYPE(uint8_t *) apu8CustBin[MAX_CUST_TABLES];
586 /** The size of the custom table binary. */
587 uint64_t acbCustBin[MAX_CUST_TABLES];
588} ACPISTATER3;
589/** Pointer to the ring-3 ACPI device state. */
590typedef ACPISTATER3 *PACPISTATER3;
591
592
593#pragma pack(1)
594
595/** Generic Address Structure (see ACPIspec 3.0, 5.2.3.1) */
596struct ACPIGENADDR
597{
598 uint8_t u8AddressSpaceId; /**< 0=sys, 1=IO, 2=PCICfg, 3=emb, 4=SMBus */
599 uint8_t u8RegisterBitWidth; /**< size in bits of the given register */
600 uint8_t u8RegisterBitOffset; /**< bit offset of register */
601 uint8_t u8AccessSize; /**< 1=byte, 2=word, 3=dword, 4=qword */
602 uint64_t u64Address; /**< 64-bit address of register */
603};
604AssertCompileSize(ACPIGENADDR, 12);
605
606/** Root System Description Pointer */
607struct ACPITBLRSDP
608{
609 uint8_t au8Signature[8]; /**< 'RSD PTR ' */
610 uint8_t u8Checksum; /**< checksum for the first 20 bytes */
611 uint8_t au8OemId[6]; /**< OEM-supplied identifier */
612 uint8_t u8Revision; /**< revision number, currently 2 */
613#define ACPI_REVISION 2 /**< ACPI 3.0 */
614 uint32_t u32RSDT; /**< phys addr of RSDT */
615 uint32_t u32Length; /**< bytes of this table */
616 uint64_t u64XSDT; /**< 64-bit phys addr of XSDT */
617 uint8_t u8ExtChecksum; /**< checksum of entire table */
618 uint8_t u8Reserved[3]; /**< reserved */
619};
620AssertCompileSize(ACPITBLRSDP, 36);
621
622/** System Description Table Header */
623struct ACPITBLHEADER
624{
625 uint8_t au8Signature[4]; /**< table identifier */
626 uint32_t u32Length; /**< length of the table including header */
627 uint8_t u8Revision; /**< revision number */
628 uint8_t u8Checksum; /**< all fields inclusive this add to zero */
629 uint8_t au8OemId[6]; /**< OEM-supplied string */
630 uint8_t au8OemTabId[8]; /**< to identify the particular data table */
631 uint32_t u32OemRevision; /**< OEM-supplied revision number */
632 uint8_t au8CreatorId[4]; /**< ID for the ASL compiler */
633 uint32_t u32CreatorRev; /**< revision for the ASL compiler */
634};
635AssertCompileSize(ACPITBLHEADER, 36);
636
637/** Root System Description Table */
638struct ACPITBLRSDT
639{
640 ACPITBLHEADER header;
641 uint32_t u32Entry[1]; /**< array of phys. addresses to other tables */
642};
643AssertCompileSize(ACPITBLRSDT, 40);
644
645/** Extended System Description Table */
646struct ACPITBLXSDT
647{
648 ACPITBLHEADER header;
649 uint64_t u64Entry[1]; /**< array of phys. addresses to other tables */
650};
651AssertCompileSize(ACPITBLXSDT, 44);
652
653/** Fixed ACPI Description Table */
654struct ACPITBLFADT
655{
656 ACPITBLHEADER header;
657 uint32_t u32FACS; /**< phys. address of FACS */
658 uint32_t u32DSDT; /**< phys. address of DSDT */
659 uint8_t u8IntModel; /**< was eleminated in ACPI 2.0 */
660#define INT_MODEL_DUAL_PIC 1 /**< for ACPI 2+ */
661#define INT_MODEL_MULTIPLE_APIC 2
662 uint8_t u8PreferredPMProfile; /**< preferred power management profile */
663 uint16_t u16SCIInt; /**< system vector the SCI is wired in 8259 mode */
664#define SCI_INT 9
665 uint32_t u32SMICmd; /**< system port address of SMI command port */
666#define SMI_CMD 0x0000442e
667 uint8_t u8AcpiEnable; /**< SMICmd val to disable ownership of ACPIregs */
668#define ACPI_ENABLE 0xa1
669 uint8_t u8AcpiDisable; /**< SMICmd val to re-enable ownership of ACPIregs */
670#define ACPI_DISABLE 0xa0
671 uint8_t u8S4BIOSReq; /**< SMICmd val to enter S4BIOS state */
672 uint8_t u8PStateCnt; /**< SMICmd val to assume processor performance
673 state control responsibility */
674 uint32_t u32PM1aEVTBLK; /**< port addr of PM1a event regs block */
675 uint32_t u32PM1bEVTBLK; /**< port addr of PM1b event regs block */
676 uint32_t u32PM1aCTLBLK; /**< port addr of PM1a control regs block */
677 uint32_t u32PM1bCTLBLK; /**< port addr of PM1b control regs block */
678 uint32_t u32PM2CTLBLK; /**< port addr of PM2 control regs block */
679 uint32_t u32PMTMRBLK; /**< port addr of PMTMR regs block */
680 uint32_t u32GPE0BLK; /**< port addr of gen-purp event 0 regs block */
681 uint32_t u32GPE1BLK; /**< port addr of gen-purp event 1 regs block */
682 uint8_t u8PM1EVTLEN; /**< bytes decoded by PM1a_EVT_BLK. >= 4 */
683 uint8_t u8PM1CTLLEN; /**< bytes decoded by PM1b_CNT_BLK. >= 2 */
684 uint8_t u8PM2CTLLEN; /**< bytes decoded by PM2_CNT_BLK. >= 1 or 0 */
685 uint8_t u8PMTMLEN; /**< bytes decoded by PM_TMR_BLK. ==4 */
686 uint8_t u8GPE0BLKLEN; /**< bytes decoded by GPE0_BLK. %2==0 */
687#define GPE0_BLK_LEN 2
688 uint8_t u8GPE1BLKLEN; /**< bytes decoded by GPE1_BLK. %2==0 */
689#define GPE1_BLK_LEN 0
690 uint8_t u8GPE1BASE; /**< offset of GPE1 based events */
691#define GPE1_BASE 0
692 uint8_t u8CSTCNT; /**< SMICmd val to indicate OS supp for C states */
693 uint16_t u16PLVL2LAT; /**< us to enter/exit C2. >100 => unsupported */
694#define P_LVL2_LAT 101 /**< C2 state not supported */
695 uint16_t u16PLVL3LAT; /**< us to enter/exit C3. >1000 => unsupported */
696#define P_LVL3_LAT 1001 /**< C3 state not supported */
697 uint16_t u16FlushSize; /**< # of flush strides to read to flush dirty
698 lines from any processors memory caches */
699#define FLUSH_SIZE 0 /**< Ignored if WBVIND set in FADT_FLAGS */
700 uint16_t u16FlushStride; /**< cache line width */
701#define FLUSH_STRIDE 0 /**< Ignored if WBVIND set in FADT_FLAGS */
702 uint8_t u8DutyOffset;
703 uint8_t u8DutyWidth;
704 uint8_t u8DayAlarm; /**< RTC CMOS RAM index of day-of-month alarm */
705 uint8_t u8MonAlarm; /**< RTC CMOS RAM index of month-of-year alarm */
706 uint8_t u8Century; /**< RTC CMOS RAM index of century */
707 uint16_t u16IAPCBOOTARCH; /**< IA-PC boot architecture flags */
708#define IAPC_BOOT_ARCH_LEGACY_DEV RT_BIT(0) /**< legacy devices present such as LPT
709 (COM too?) */
710#define IAPC_BOOT_ARCH_8042 RT_BIT(1) /**< legacy keyboard device present */
711#define IAPC_BOOT_ARCH_NO_VGA RT_BIT(2) /**< VGA not present */
712#define IAPC_BOOT_ARCH_NO_MSI RT_BIT(3) /**< OSPM must not enable MSIs on this platform */
713#define IAPC_BOOT_ARCH_NO_ASPM RT_BIT(4) /**< OSPM must not enable ASPM on this platform */
714 uint8_t u8Must0_0; /**< must be 0 */
715 uint32_t u32Flags; /**< fixed feature flags */
716#define FADT_FL_WBINVD RT_BIT(0) /**< emulation of WBINVD available */
717#define FADT_FL_WBINVD_FLUSH RT_BIT(1)
718#define FADT_FL_PROC_C1 RT_BIT(2) /**< 1=C1 supported on all processors */
719#define FADT_FL_P_LVL2_UP RT_BIT(3) /**< 1=C2 works on SMP and UNI systems */
720#define FADT_FL_PWR_BUTTON RT_BIT(4) /**< 1=power button handled as ctrl method dev */
721#define FADT_FL_SLP_BUTTON RT_BIT(5) /**< 1=sleep button handled as ctrl method dev */
722#define FADT_FL_FIX_RTC RT_BIT(6) /**< 0=RTC wake status in fixed register */
723#define FADT_FL_RTC_S4 RT_BIT(7) /**< 1=RTC can wake system from S4 */
724#define FADT_FL_TMR_VAL_EXT RT_BIT(8) /**< 1=TMR_VAL implemented as 32 bit */
725#define FADT_FL_DCK_CAP RT_BIT(9) /**< 0=system cannot support docking */
726#define FADT_FL_RESET_REG_SUP RT_BIT(10) /**< 1=system supports system resets */
727#define FADT_FL_SEALED_CASE RT_BIT(11) /**< 1=case is sealed */
728#define FADT_FL_HEADLESS RT_BIT(12) /**< 1=system cannot detect moni/keyb/mouse */
729#define FADT_FL_CPU_SW_SLP RT_BIT(13)
730#define FADT_FL_PCI_EXT_WAK RT_BIT(14) /**< 1=system supports PCIEXP_WAKE_STS */
731#define FADT_FL_USE_PLATFORM_CLOCK RT_BIT(15) /**< 1=system has ACPI PM timer */
732#define FADT_FL_S4_RTC_STS_VALID RT_BIT(16) /**< 1=RTC_STS flag is valid when waking from S4 */
733#define FADT_FL_REMOVE_POWER_ON_CAPABLE RT_BIT(17) /**< 1=platform can remote power on */
734#define FADT_FL_FORCE_APIC_CLUSTER_MODEL RT_BIT(18)
735#define FADT_FL_FORCE_APIC_PHYS_DEST_MODE RT_BIT(19)
736
737/* PM Timer mask and msb */
738#ifndef PM_TMR_32BIT
739#define TMR_VAL_MSB 0x800000
740#define TMR_VAL_MASK 0xffffff
741#undef FADT_FL_TMR_VAL_EXT
742#define FADT_FL_TMR_VAL_EXT 0
743#else
744#define TMR_VAL_MSB 0x80000000
745#define TMR_VAL_MASK 0xffffffff
746#endif
747
748 /** Start of the ACPI 2.0 extension. */
749 ACPIGENADDR ResetReg; /**< ext addr of reset register */
750 uint8_t u8ResetVal; /**< ResetReg value to reset the system */
751#define ACPI_RESET_REG_VAL 0x10
752 uint8_t au8Must0_1[3]; /**< must be 0 */
753 uint64_t u64XFACS; /**< 64-bit phys address of FACS */
754 uint64_t u64XDSDT; /**< 64-bit phys address of DSDT */
755 ACPIGENADDR X_PM1aEVTBLK; /**< ext addr of PM1a event regs block */
756 ACPIGENADDR X_PM1bEVTBLK; /**< ext addr of PM1b event regs block */
757 ACPIGENADDR X_PM1aCTLBLK; /**< ext addr of PM1a control regs block */
758 ACPIGENADDR X_PM1bCTLBLK; /**< ext addr of PM1b control regs block */
759 ACPIGENADDR X_PM2CTLBLK; /**< ext addr of PM2 control regs block */
760 ACPIGENADDR X_PMTMRBLK; /**< ext addr of PMTMR control regs block */
761 ACPIGENADDR X_GPE0BLK; /**< ext addr of GPE1 regs block */
762 ACPIGENADDR X_GPE1BLK; /**< ext addr of GPE1 regs block */
763};
764AssertCompileSize(ACPITBLFADT, 244);
765#define ACPITBLFADT_VERSION1_SIZE RT_OFFSETOF(ACPITBLFADT, ResetReg)
766
767/** Firmware ACPI Control Structure */
768struct ACPITBLFACS
769{
770 uint8_t au8Signature[4]; /**< 'FACS' */
771 uint32_t u32Length; /**< bytes of entire FACS structure >= 64 */
772 uint32_t u32HWSignature; /**< systems HW signature at last boot */
773 uint32_t u32FWVector; /**< address of waking vector */
774 uint32_t u32GlobalLock; /**< global lock to sync HW/SW */
775 uint32_t u32Flags; /**< FACS flags */
776 uint64_t u64X_FWVector; /**< 64-bit waking vector */
777 uint8_t u8Version; /**< version of this table */
778 uint8_t au8Reserved[31]; /**< zero */
779};
780AssertCompileSize(ACPITBLFACS, 64);
781
782/** Processor Local APIC Structure */
783struct ACPITBLLAPIC
784{
785 uint8_t u8Type; /**< 0 = LAPIC */
786 uint8_t u8Length; /**< 8 */
787 uint8_t u8ProcId; /**< processor ID */
788 uint8_t u8ApicId; /**< local APIC ID */
789 uint32_t u32Flags; /**< Flags */
790#define LAPIC_ENABLED 0x1
791};
792AssertCompileSize(ACPITBLLAPIC, 8);
793
794/** I/O APIC Structure */
795struct ACPITBLIOAPIC
796{
797 uint8_t u8Type; /**< 1 == I/O APIC */
798 uint8_t u8Length; /**< 12 */
799 uint8_t u8IOApicId; /**< I/O APIC ID */
800 uint8_t u8Reserved; /**< 0 */
801 uint32_t u32Address; /**< phys address to access I/O APIC */
802 uint32_t u32GSIB; /**< global system interrupt number to start */
803};
804AssertCompileSize(ACPITBLIOAPIC, 12);
805
806/** Interrupt Source Override Structure */
807struct ACPITBLISO
808{
809 uint8_t u8Type; /**< 2 == Interrupt Source Override*/
810 uint8_t u8Length; /**< 10 */
811 uint8_t u8Bus; /**< Bus */
812 uint8_t u8Source; /**< Bus-relative interrupt source (IRQ) */
813 uint32_t u32GSI; /**< Global System Interrupt */
814 uint16_t u16Flags; /**< MPS INTI flags Global */
815};
816AssertCompileSize(ACPITBLISO, 10);
817#define NUMBER_OF_IRQ_SOURCE_OVERRIDES 2
818
819/** HPET Descriptor Structure */
820struct ACPITBLHPET
821{
822 ACPITBLHEADER aHeader;
823 uint32_t u32Id; /**< hardware ID of event timer block
824 [31:16] PCI vendor ID of first timer block
825 [15] legacy replacement IRQ routing capable
826 [14] reserved
827 [13] COUNT_SIZE_CAP counter size
828 [12:8] number of comparators in first timer block
829 [7:0] hardware rev ID */
830 ACPIGENADDR HpetAddr; /**< lower 32-bit base address */
831 uint8_t u32Number; /**< sequence number starting at 0 */
832 uint16_t u32MinTick; /**< minimum clock ticks which can be set without
833 lost interrupts while the counter is programmed
834 to operate in periodic mode. Unit: clock tick. */
835 uint8_t u8Attributes; /**< page protection and OEM attribute. */
836};
837AssertCompileSize(ACPITBLHPET, 56);
838
839#ifdef VBOX_WITH_IOMMU_AMD
840/** AMD IOMMU: IVRS (I/O Virtualization Reporting Structure).
841 * In accordance with the AMD spec. */
842typedef struct ACPIIVRS
843{
844 ACPITBLHEADER header;
845 uint32_t u32IvInfo; /**< IVInfo: I/O virtualization info. common to all IOMMUs in the system. */
846 uint64_t u64Rsvd; /**< Reserved (MBZ). */
847 /* IVHD type block follows. */
848} ACPIIVRS;
849AssertCompileSize(ACPIIVRS, 48);
850AssertCompileMemberOffset(ACPIIVRS, u32IvInfo, 36);
851
852/**
853 * AMD IOMMU: The ACPI table.
854 */
855typedef struct ACPITBLIOMMU
856{
857 ACPIIVRS Hdr;
858 ACPIIVHDTYPE10 IvhdType10;
859 ACPIIVHDDEVENTRY4 IvhdType10Start;
860 ACPIIVHDDEVENTRY4 IvhdType10End;
861 ACPIIVHDDEVENTRY4 IvhdType10Rsvd0;
862 ACPIIVHDDEVENTRY4 IvhdType10Rsvd1;
863 ACPIIVHDDEVENTRY8 IvhdType10IoApic;
864 ACPIIVHDDEVENTRY8 IvhdType10Hpet;
865
866 ACPIIVHDTYPE11 IvhdType11;
867 ACPIIVHDDEVENTRY4 IvhdType11Start;
868 ACPIIVHDDEVENTRY4 IvhdType11End;
869 ACPIIVHDDEVENTRY4 IvhdType11Rsvd0;
870 ACPIIVHDDEVENTRY4 IvhdType11Rsvd1;
871 ACPIIVHDDEVENTRY8 IvhdType11IoApic;
872 ACPIIVHDDEVENTRY8 IvhdType11Hpet;
873} ACPITBLIOMMU;
874AssertCompileMemberAlignment(ACPITBLIOMMU, IvhdType10Start, 4);
875AssertCompileMemberAlignment(ACPITBLIOMMU, IvhdType10End, 4);
876AssertCompileMemberAlignment(ACPITBLIOMMU, IvhdType11Start, 4);
877AssertCompileMemberAlignment(ACPITBLIOMMU, IvhdType11End, 4);
878#endif /* VBOX_WITH_IOMMU_AMD */
879
880#ifdef VBOX_WITH_IOMMU_INTEL
881/** Intel IOMMU: DMAR (DMA Remapping) Reporting Structure.
882 * In accordance with the AMD spec. */
883typedef struct ACPIDMAR
884{
885 ACPITBLHEADER Hdr;
886 /** Host-address Width (N+1 physical bits addressable). */
887 uint8_t uHostAddrWidth;
888 /** Flags, see ACPI_DMAR_F_XXX. */
889 uint8_t fFlags;
890 /** Reserved. */
891 uint8_t abRsvd[10];
892 /* Remapping Structures[] follows. */
893} ACPIDMAR;
894AssertCompileSize(ACPIDMAR, 48);
895AssertCompileMemberOffset(ACPIDMAR, uHostAddrWidth, 36);
896AssertCompileMemberOffset(ACPIDMAR, fFlags, 37);
897
898/**
899 * Intel VT-d: The ACPI table.
900 */
901typedef struct ACPITBLVTD
902{
903 ACPIDMAR Dmar;
904 ACPIDRHD Drhd;
905 ACPIDMARDEVSCOPE DevScopeIoApic;
906} ACPITBLVTD;
907#endif /* VBOX_WITH_IOMMU_INTEL */
908
909/** MCFG Descriptor Structure */
910typedef struct ACPITBLMCFG
911{
912 ACPITBLHEADER aHeader;
913 uint64_t u64Reserved;
914} ACPITBLMCFG;
915AssertCompileSize(ACPITBLMCFG, 44);
916
917/** Number of such entries can be computed from the whole table length in header */
918typedef struct ACPITBLMCFGENTRY
919{
920 uint64_t u64BaseAddress;
921 uint16_t u16PciSegmentGroup;
922 uint8_t u8StartBus;
923 uint8_t u8EndBus;
924 uint32_t u32Reserved;
925} ACPITBLMCFGENTRY;
926AssertCompileSize(ACPITBLMCFGENTRY, 16);
927
928#define PCAT_COMPAT 0x1 /**< system has also a dual-8259 setup */
929
930/** Custom Description Table */
931struct ACPITBLCUST
932{
933 ACPITBLHEADER header;
934 uint8_t au8Data[476];
935};
936AssertCompileSize(ACPITBLCUST, 512);
937
938
939#ifdef VBOX_WITH_TPM
940/**
941 * TPM: The ACPI table for a TPM 2.0 device
942 * (from: https://trustedcomputinggroup.org/wp-content/uploads/TCG_ACPIGeneralSpec_v1p3_r8_pub.pdf).
943 */
944typedef struct ACPITBLTPM20
945{
946 /** The common ACPI table header. */
947 ACPITBLHEADER Hdr;
948 /** The platform class. */
949 uint16_t u16PlatCls;
950 /** Reserved. */
951 uint16_t u16Rsvd0;
952 /** Address of the CRB control area or FIFO base address. */
953 uint64_t u64BaseAddrCrbOrFifo;
954 /** The start method selector. */
955 uint32_t u32StartMethod;
956 /** Following are start method specific parameters and optional LAML and LASA fields we don't implement right now. */
957 /** @todo */
958} ACPITBLTPM20;
959AssertCompileSize(ACPITBLTPM20, 52);
960
961/** Revision of the TPM2.0 ACPI table. */
962#define ACPI_TPM20_REVISION 4
963/** The default MMIO base address of the TPM. */
964#define ACPI_TPM_MMIO_BASE_DEFAULT 0xfed40000
965
966
967/** @name Possible values for the ACPITBLTPM20::u16PlatCls member.
968 * @{ */
969/** Client platform. */
970#define ACPITBL_TPM20_PLAT_CLS_CLIENT UINT16_C(0)
971/** Server platform. */
972#define ACPITBL_TPM20_PLAT_CLS_SERVER UINT16_C(1)
973/** @} */
974
975
976/** @name Possible values for the ACPITBLTPM20::u32StartMethod member.
977 * @{ */
978/** MMIO interface (TIS1.2+Cancel). */
979#define ACPITBL_TPM20_START_METHOD_TIS12 UINT16_C(6)
980/** CRB interface. */
981#define ACPITBL_TPM20_START_METHOD_CRB UINT16_C(7)
982/** @} */
983
984
985/**
986 * TPM: The ACPI table for a TPM 1.2 device
987 * (from: https://trustedcomputinggroup.org/wp-content/uploads/TCG_ACPIGeneralSpecification_v1.20_r8.pdf).
988 */
989typedef struct ACPITBLTCPA
990{
991 /** The common ACPI table header. */
992 ACPITBLHEADER Hdr;
993 /** The platform class. */
994 uint16_t u16PlatCls;
995 /** Log Area Minimum Length. */
996 uint32_t u32Laml;
997 /** Log Area Start Address. */
998 uint64_t u64Lasa;
999} ACPITBLTCPA;
1000AssertCompileSize(ACPITBLTCPA, 50);
1001
1002/** Revision of the TPM1.2 ACPI table. */
1003#define ACPI_TCPA_REVISION 2
1004/** LAML region size. */
1005#define ACPI_TCPA_LAML_SZ _16K
1006
1007
1008/** @name Possible values for the ACPITBLTCPA::u16PlatCls member.
1009 * @{ */
1010/** Client platform. */
1011#define ACPI_TCPA_PLAT_CLS_CLIENT UINT16_C(0)
1012/** @} */
1013#endif
1014
1015
1016#pragma pack()
1017
1018
1019#ifndef VBOX_DEVICE_STRUCT_TESTCASE /* exclude the rest of the file */
1020
1021
1022/*********************************************************************************************************************************
1023* Internal Functions *
1024*********************************************************************************************************************************/
1025#ifdef IN_RING3
1026static int acpiR3PlantTables(PPDMDEVINS pDevIns, PACPISTATE pThis, PACPISTATER3 pThisCC);
1027#endif
1028
1029/* SCI, usually IRQ9 */
1030DECLINLINE(void) acpiSetIrq(PPDMDEVINS pDevIns, int level)
1031{
1032 PDMDevHlpPCISetIrq(pDevIns, 0, level);
1033}
1034
1035DECLINLINE(bool) pm1a_level(PACPISTATE pThis)
1036{
1037 return (pThis->pm1a_ctl & SCI_EN)
1038 && (pThis->pm1a_en & pThis->pm1a_sts & ~(RSR_EN | IGN_EN));
1039}
1040
1041DECLINLINE(bool) gpe0_level(PACPISTATE pThis)
1042{
1043 return !!(pThis->gpe0_en & pThis->gpe0_sts);
1044}
1045
1046DECLINLINE(bool) smbus_level(PPDMDEVINS pDevIns, PACPISTATE pThis)
1047{
1048 PPDMPCIDEV pPciDev = pDevIns->apPciDevs[0];
1049 return (pThis->u8SMBusHstCnt & SMBHSTCNT_INTEREN)
1050 && (pPciDev->abConfig[SMBHSTCFG] & SMBHSTCFG_SMB_HST_EN)
1051 && (pPciDev->abConfig[SMBHSTCFG] & SMBHSTCFG_INTRSEL) == SMBHSTCFG_INTRSEL_IRQ9 << SMBHSTCFG_INTRSEL_SHIFT
1052 && (pThis->u8SMBusHstSts & SMBHSTSTS_INT_MASK);
1053}
1054
1055DECLINLINE(bool) acpiSCILevel(PPDMDEVINS pDevIns, PACPISTATE pThis)
1056{
1057 return pm1a_level(pThis) || gpe0_level(pThis) || smbus_level(pDevIns, pThis);
1058}
1059
1060/**
1061 * Used by acpiR3PM1aStsWrite, acpiR3PM1aEnWrite, acpiR3PmTimer,
1062 * acpiR3Port_PowerBuffonPress, acpiR3Port_SleepButtonPress
1063 * and acpiPmTmrRead to update the PM1a.STS and PM1a.EN
1064 * registers and trigger IRQs.
1065 *
1066 * Caller must hold the state lock.
1067 *
1068 * @param pDevIns The PDM device instance.
1069 * @param pThis The ACPI shared instance data.
1070 * @param sts The new PM1a.STS value.
1071 * @param en The new PM1a.EN value.
1072 */
1073static void acpiUpdatePm1a(PPDMDEVINS pDevIns, PACPISTATE pThis, uint32_t sts, uint32_t en)
1074{
1075 Assert(PDMDevHlpCritSectIsOwner(pDevIns, &pThis->CritSect));
1076
1077 const bool old_level = acpiSCILevel(pDevIns, pThis);
1078 pThis->pm1a_en = en;
1079 pThis->pm1a_sts = sts;
1080 const bool new_level = acpiSCILevel(pDevIns, pThis);
1081
1082 LogFunc(("old=%x new=%x\n", old_level, new_level));
1083
1084 if (new_level != old_level)
1085 acpiSetIrq(pDevIns, new_level);
1086}
1087
1088#ifdef IN_RING3
1089
1090/**
1091 * Used by acpiR3Gpe0StsWrite, acpiR3Gpe0EnWrite, acpiAttach and acpiDetach to
1092 * update the GPE0.STS and GPE0.EN registers and trigger IRQs.
1093 *
1094 * Caller must hold the state lock.
1095 *
1096 * @param pDevIns The PDM device instance.
1097 * @param pThis The ACPI shared instance data.
1098 * @param sts The new GPE0.STS value.
1099 * @param en The new GPE0.EN value.
1100 */
1101static void apicR3UpdateGpe0(PPDMDEVINS pDevIns, PACPISTATE pThis, uint32_t sts, uint32_t en)
1102{
1103 Assert(PDMDevHlpCritSectIsOwner(pDevIns, &pThis->CritSect));
1104
1105 const bool old_level = acpiSCILevel(pDevIns, pThis);
1106 pThis->gpe0_en = en;
1107 pThis->gpe0_sts = sts;
1108 const bool new_level = acpiSCILevel(pDevIns, pThis);
1109
1110 LogFunc(("old=%x new=%x\n", old_level, new_level));
1111
1112 if (new_level != old_level)
1113 acpiSetIrq(pDevIns, new_level);
1114}
1115
1116/**
1117 * Used by acpiR3PM1aCtlWrite to power off the VM.
1118 *
1119 * @param pDevIns The device instance.
1120 * @returns Strict VBox status code.
1121 */
1122static VBOXSTRICTRC acpiR3DoPowerOff(PPDMDEVINS pDevIns)
1123{
1124 VBOXSTRICTRC rc = PDMDevHlpVMPowerOff(pDevIns);
1125 AssertRC(VBOXSTRICTRC_VAL(rc));
1126 return rc;
1127}
1128
1129/**
1130 * Used by acpiR3PM1aCtlWrite to put the VM to sleep.
1131 *
1132 * @param pDevIns The device instance.
1133 * @param pThis The ACPI shared instance data.
1134 * @returns Strict VBox status code.
1135 */
1136static VBOXSTRICTRC acpiR3DoSleep(PPDMDEVINS pDevIns, PACPISTATE pThis)
1137{
1138 /* We must set WAK_STS on resume (includes restore) so the guest knows that
1139 we've woken up and can continue executing code. The guest is probably
1140 reading the PMSTS register in a loop to check this. */
1141 VBOXSTRICTRC rc;
1142 pThis->fSetWakeupOnResume = true;
1143 if (pThis->fSuspendToSavedState)
1144 {
1145 rc = PDMDevHlpVMSuspendSaveAndPowerOff(pDevIns);
1146 if (rc != VERR_NOT_SUPPORTED)
1147 AssertRC(VBOXSTRICTRC_VAL(rc));
1148 else
1149 {
1150 LogRel(("ACPI: PDMDevHlpVMSuspendSaveAndPowerOff is not supported, falling back to suspend-only\n"));
1151 rc = PDMDevHlpVMSuspend(pDevIns);
1152 AssertRC(VBOXSTRICTRC_VAL(rc));
1153 }
1154 }
1155 else
1156 {
1157 rc = PDMDevHlpVMSuspend(pDevIns);
1158 AssertRC(VBOXSTRICTRC_VAL(rc));
1159 }
1160 return rc;
1161}
1162
1163
1164/**
1165 * @interface_method_impl{PDMIACPIPORT,pfnGetGuestEnteredACPIMode, Check if the
1166 * Guest entered into G0 (working) or G1 (sleeping)}
1167 */
1168static DECLCALLBACK(int) acpiR3Port_GetGuestEnteredACPIMode(PPDMIACPIPORT pInterface, bool *pfEntered)
1169{
1170 PACPISTATER3 pThisCC = RT_FROM_MEMBER(pInterface, ACPISTATER3, IACPIPort);
1171 PPDMDEVINS pDevIns = pThisCC->pDevIns;
1172 PACPISTATE pThis = PDMDEVINS_2_DATA(pDevIns, PACPISTATE);
1173 DEVACPI_LOCK_R3(pDevIns, pThis);
1174
1175 *pfEntered = (pThis->pm1a_ctl & SCI_EN) != 0;
1176
1177 DEVACPI_UNLOCK(pDevIns, pThis);
1178 return VINF_SUCCESS;
1179}
1180
1181/**
1182 * @interface_method_impl{PDMIACPIPORT,pfnGetCpuStatus}
1183 */
1184static DECLCALLBACK(int) acpiR3Port_GetCpuStatus(PPDMIACPIPORT pInterface, unsigned uCpu, bool *pfLocked)
1185{
1186 PACPISTATER3 pThisCC = RT_FROM_MEMBER(pInterface, ACPISTATER3, IACPIPort);
1187 PPDMDEVINS pDevIns = pThisCC->pDevIns;
1188 PACPISTATE pThis = PDMDEVINS_2_DATA(pDevIns, PACPISTATE);
1189 DEVACPI_LOCK_R3(pDevIns, pThis);
1190
1191 *pfLocked = VMCPUSET_IS_PRESENT(&pThis->CpuSetLocked, uCpu);
1192
1193 DEVACPI_UNLOCK(pDevIns, pThis);
1194 return VINF_SUCCESS;
1195}
1196
1197
1198/**
1199 * Send an ACPI monitor hot-plug event.
1200 *
1201 * @returns VBox status code
1202 * @param pInterface Pointer to the interface structure containing the
1203 * called function pointer.
1204 */
1205static DECLCALLBACK(int) acpiR3Port_MonitorHotPlugEvent(PPDMIACPIPORT pInterface)
1206{
1207 PACPISTATER3 pThisCC = RT_FROM_MEMBER(pInterface, ACPISTATER3, IACPIPort);
1208 PPDMDEVINS pDevIns = pThisCC->pDevIns;
1209 PACPISTATE pThis = PDMDEVINS_2_DATA(pDevIns, PACPISTATE);
1210 DEVACPI_LOCK_R3(pDevIns, pThis);
1211
1212 apicR3UpdateGpe0(pDevIns, pThis, pThis->gpe0_sts | 0x4, pThis->gpe0_en);
1213
1214 DEVACPI_UNLOCK(pDevIns, pThis);
1215 return VINF_SUCCESS;
1216}
1217
1218/**
1219 * Send an ACPI battery status change event.
1220 *
1221 * @returns VBox status code
1222 * @param pInterface Pointer to the interface structure containing the
1223 * called function pointer.
1224 */
1225static DECLCALLBACK(int) acpiR3Port_BatteryStatusChangeEvent(PPDMIACPIPORT pInterface)
1226{
1227 PACPISTATER3 pThisCC = RT_FROM_MEMBER(pInterface, ACPISTATER3, IACPIPort);
1228 PPDMDEVINS pDevIns = pThisCC->pDevIns;
1229 PACPISTATE pThis = PDMDEVINS_2_DATA(pDevIns, PACPISTATE);
1230 DEVACPI_LOCK_R3(pDevIns, pThis);
1231
1232 apicR3UpdateGpe0(pDevIns, pThis, pThis->gpe0_sts | 0x1, pThis->gpe0_en);
1233
1234 DEVACPI_UNLOCK(pDevIns, pThis);
1235 return VINF_SUCCESS;
1236}
1237
1238
1239/**
1240 * @interface_method_impl{PDMIEVENTBUTTONPORT,pfnQueryGuestCanHandleButtonEvents}
1241 */
1242static DECLCALLBACK(int) acpiR3Port_QueryGuestCanHandleButtonEvents(PPDMIEVENTBUTTONPORT pInterface, bool *pfCanHandleButtonEvents)
1243{
1244 PACPISTATER3 pThisCC = RT_FROM_MEMBER(pInterface, ACPISTATER3, IButtonEventPort);
1245 PPDMDEVINS pDevIns = pThisCC->pDevIns;
1246 PACPISTATE pThis = PDMDEVINS_2_DATA(pDevIns, PACPISTATE);
1247 DEVACPI_LOCK_R3(pDevIns, pThis);
1248
1249 /* Just checks whether the guest has entered ACPI mode. */
1250 *pfCanHandleButtonEvents = (pThis->pm1a_ctl & SCI_EN) != 0;
1251
1252 DEVACPI_UNLOCK(pDevIns, pThis);
1253 return VINF_SUCCESS;
1254}
1255
1256
1257/**
1258 * @interface_method_impl{PDMIEVENTBUTTONPORT,pfnPowerButtonPress}
1259 */
1260static DECLCALLBACK(int) acpiR3Port_PowerButtonPress(PPDMIEVENTBUTTONPORT pInterface)
1261{
1262 PACPISTATER3 pThisCC = RT_FROM_MEMBER(pInterface, ACPISTATER3, IButtonEventPort);
1263 PPDMDEVINS pDevIns = pThisCC->pDevIns;
1264 PACPISTATE pThis = PDMDEVINS_2_DATA(pDevIns, PACPISTATE);
1265 DEVACPI_LOCK_R3(pDevIns, pThis);
1266
1267 Log(("acpiR3Port_PowerButtonPress: handled=%d status=%x\n", pThis->fPowerButtonHandled, pThis->pm1a_sts));
1268 pThis->fPowerButtonHandled = false;
1269 acpiUpdatePm1a(pDevIns, pThis, pThis->pm1a_sts | PWRBTN_STS, pThis->pm1a_en);
1270
1271 DEVACPI_UNLOCK(pDevIns, pThis);
1272 return VINF_SUCCESS;
1273}
1274
1275
1276/**
1277 * @interface_method_impl{PDMIEVENTBUTTONPORT,pfnSleepButtonPress}
1278 */
1279static DECLCALLBACK(int) acpiR3Port_SleepButtonPress(PPDMIEVENTBUTTONPORT pInterface)
1280{
1281 PACPISTATER3 pThisCC = RT_FROM_MEMBER(pInterface, ACPISTATER3, IButtonEventPort);
1282 PPDMDEVINS pDevIns = pThisCC->pDevIns;
1283 PACPISTATE pThis = PDMDEVINS_2_DATA(pDevIns, PACPISTATE);
1284 DEVACPI_LOCK_R3(pDevIns, pThis);
1285
1286 acpiUpdatePm1a(pDevIns, pThis, pThis->pm1a_sts | SLPBTN_STS, pThis->pm1a_en);
1287
1288 DEVACPI_UNLOCK(pDevIns, pThis);
1289 return VINF_SUCCESS;
1290}
1291
1292
1293/**
1294 * @interface_method_impl{PDMIEVENTBUTTONPORT,pfnQueryPowerButtonHandled}
1295 */
1296static DECLCALLBACK(int) acpiR3Port_QueryPowerButtonHandled(PPDMIEVENTBUTTONPORT pInterface, bool *pfHandled)
1297{
1298 PACPISTATER3 pThisCC = RT_FROM_MEMBER(pInterface, ACPISTATER3, IButtonEventPort);
1299 PPDMDEVINS pDevIns = pThisCC->pDevIns;
1300 PACPISTATE pThis = PDMDEVINS_2_DATA(pDevIns, PACPISTATE);
1301 DEVACPI_LOCK_R3(pDevIns, pThis);
1302
1303 *pfHandled = pThis->fPowerButtonHandled;
1304
1305 DEVACPI_UNLOCK(pDevIns, pThis);
1306 return VINF_SUCCESS;
1307}
1308
1309
1310/**
1311 * Used by acpiR3PmTimer to re-arm the PM timer.
1312 *
1313 * The caller is expected to either hold the clock lock or to have made sure
1314 * the VM is resetting or loading state.
1315 *
1316 * @param pDevIns The device instance.
1317 * @param pThis The ACPI shared instance data.
1318 * @param uNow The current time.
1319 */
1320static void acpiR3PmTimerReset(PPDMDEVINS pDevIns, PACPISTATE pThis, uint64_t uNow)
1321{
1322 uint64_t uTimerFreq = PDMDevHlpTimerGetFreq(pDevIns, pThis->hPmTimer);
1323 uint32_t uPmTmrCyclesToRollover = TMR_VAL_MSB - (pThis->uPmTimerVal & (TMR_VAL_MSB - 1));
1324 uint64_t uInterval = ASMMultU64ByU32DivByU32(uPmTmrCyclesToRollover, uTimerFreq, PM_TMR_FREQ);
1325 PDMDevHlpTimerSet(pDevIns, pThis->hPmTimer, uNow + uInterval + 1);
1326 Log(("acpi: uInterval = %RU64\n", uInterval));
1327}
1328
1329#endif /* IN_RING3 */
1330
1331/**
1332 * Used by acpiR3PMTimer & acpiPmTmrRead to update TMR_VAL and update TMR_STS
1333 *
1334 * The caller is expected to either hold the clock lock or to have made sure
1335 * the VM is resetting or loading state.
1336 *
1337 * @param pDevIns The PDM device instance.
1338 * @param pThis The ACPI instance
1339 * @param u64Now The current time
1340 */
1341static void acpiPmTimerUpdate(PPDMDEVINS pDevIns, PACPISTATE pThis, uint64_t u64Now)
1342{
1343 uint32_t msb = pThis->uPmTimerVal & TMR_VAL_MSB;
1344 uint64_t u64Elapsed = u64Now - pThis->u64PmTimerInitial;
1345 Assert(PDMDevHlpTimerIsLockOwner(pDevIns, pThis->hPmTimer));
1346
1347 pThis->uPmTimerVal = ASMMultU64ByU32DivByU32(u64Elapsed, PM_TMR_FREQ, PDMDevHlpTimerGetFreq(pDevIns, pThis->hPmTimer))
1348 & TMR_VAL_MASK;
1349
1350 if ((pThis->uPmTimerVal & TMR_VAL_MSB) != msb)
1351 acpiUpdatePm1a(pDevIns, pThis, pThis->pm1a_sts | TMR_STS, pThis->pm1a_en);
1352}
1353
1354#ifdef IN_RING3
1355
1356/**
1357 * @callback_method_impl{FNTMTIMERDEV, PM Timer callback}
1358 */
1359static DECLCALLBACK(void) acpiR3PmTimer(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, void *pvUser)
1360{
1361 PACPISTATE pThis = PDMDEVINS_2_DATA(pDevIns, PACPISTATE);
1362 Assert(pThis->hPmTimer == hTimer);
1363 Assert(PDMDevHlpTimerIsLockOwner(pDevIns, hTimer));
1364 RT_NOREF(pvUser);
1365
1366 DEVACPI_LOCK_R3(pDevIns, pThis);
1367 Log(("acpi: pm timer sts %#x (%d), en %#x (%d)\n",
1368 pThis->pm1a_sts, (pThis->pm1a_sts & TMR_STS) != 0,
1369 pThis->pm1a_en, (pThis->pm1a_en & TMR_EN) != 0));
1370 uint64_t tsNow = PDMDevHlpTimerGet(pDevIns, hTimer);
1371 acpiPmTimerUpdate(pDevIns, pThis, tsNow);
1372 DEVACPI_UNLOCK(pDevIns, pThis);
1373
1374 acpiR3PmTimerReset(pDevIns, pThis, tsNow);
1375}
1376
1377/**
1378 * _BST method - used by acpiR3BatDataRead to implement BAT_STATUS_STATE and
1379 * acpiR3LoadState.
1380 *
1381 * @returns VINF_SUCCESS.
1382 * @param pThis The ACPI shared instance data.
1383 * @param pThisCC The ACPI instance data for ring-3.
1384 */
1385static int acpiR3FetchBatteryStatus(PACPISTATE pThis, PACPISTATER3 pThisCC)
1386{
1387 uint32_t *p = pThis->au8BatteryInfo;
1388 bool fPresent; /* battery present? */
1389 PDMACPIBATCAPACITY hostRemainingCapacity; /* 0..100 */
1390 PDMACPIBATSTATE hostBatteryState; /* bitfield */
1391 uint32_t hostPresentRate; /* 0..1000 */
1392 int rc;
1393
1394 if (!pThisCC->pDrv)
1395 return VINF_SUCCESS;
1396 rc = pThisCC->pDrv->pfnQueryBatteryStatus(pThisCC->pDrv, &fPresent, &hostRemainingCapacity,
1397 &hostBatteryState, &hostPresentRate);
1398 AssertRC(rc);
1399
1400 /* default values */
1401 p[BAT_STATUS_STATE] = hostBatteryState;
1402 p[BAT_STATUS_PRESENT_RATE] = hostPresentRate == ~0U ? 0xFFFFFFFF
1403 : hostPresentRate * 50; /* mW */
1404 p[BAT_STATUS_REMAINING_CAPACITY] = 50000; /* mWh */
1405 p[BAT_STATUS_PRESENT_VOLTAGE] = 10000; /* mV */
1406
1407 /* did we get a valid battery state? */
1408 if (hostRemainingCapacity != PDM_ACPI_BAT_CAPACITY_UNKNOWN)
1409 p[BAT_STATUS_REMAINING_CAPACITY] = hostRemainingCapacity * 500; /* mWh */
1410 if (hostBatteryState == PDM_ACPI_BAT_STATE_CHARGED)
1411 p[BAT_STATUS_PRESENT_RATE] = 0; /* mV */
1412
1413 return VINF_SUCCESS;
1414}
1415
1416/**
1417 * _BIF method - used by acpiR3BatDataRead to implement BAT_INFO_UNITS and
1418 * acpiR3LoadState.
1419 *
1420 * @returns VINF_SUCCESS.
1421 * @param pThis The ACPI shared instance data.
1422 */
1423static int acpiR3FetchBatteryInfo(PACPISTATE pThis)
1424{
1425 uint32_t *p = pThis->au8BatteryInfo;
1426
1427 p[BAT_INFO_UNITS] = 0; /* mWh */
1428 p[BAT_INFO_DESIGN_CAPACITY] = 50000; /* mWh */
1429 p[BAT_INFO_LAST_FULL_CHARGE_CAPACITY] = 50000; /* mWh */
1430 p[BAT_INFO_TECHNOLOGY] = BAT_TECH_PRIMARY;
1431 p[BAT_INFO_DESIGN_VOLTAGE] = 10000; /* mV */
1432 p[BAT_INFO_DESIGN_CAPACITY_OF_WARNING] = 100; /* mWh */
1433 p[BAT_INFO_DESIGN_CAPACITY_OF_LOW] = 50; /* mWh */
1434 p[BAT_INFO_CAPACITY_GRANULARITY_1] = 1; /* mWh */
1435 p[BAT_INFO_CAPACITY_GRANULARITY_2] = 1; /* mWh */
1436
1437 return VINF_SUCCESS;
1438}
1439
1440/**
1441 * The _STA method - used by acpiR3BatDataRead to implement BAT_DEVICE_STATUS.
1442 *
1443 * @returns status mask or 0.
1444 * @param pThisCC The ACPI instance data for ring-3.
1445 */
1446static uint32_t acpiR3GetBatteryDeviceStatus(PACPISTATER3 pThisCC)
1447{
1448 bool fPresent; /* battery present? */
1449 PDMACPIBATCAPACITY hostRemainingCapacity; /* 0..100 */
1450 PDMACPIBATSTATE hostBatteryState; /* bitfield */
1451 uint32_t hostPresentRate; /* 0..1000 */
1452 int rc;
1453
1454 if (!pThisCC->pDrv)
1455 return 0;
1456 rc = pThisCC->pDrv->pfnQueryBatteryStatus(pThisCC->pDrv, &fPresent, &hostRemainingCapacity,
1457 &hostBatteryState, &hostPresentRate);
1458 AssertRC(rc);
1459
1460 return fPresent
1461 ? STA_DEVICE_PRESENT_MASK /* present */
1462 | STA_DEVICE_ENABLED_MASK /* enabled and decodes its resources */
1463 | STA_DEVICE_SHOW_IN_UI_MASK /* should be shown in UI */
1464 | STA_DEVICE_FUNCTIONING_PROPERLY_MASK /* functioning properly */
1465 | STA_BATTERY_PRESENT_MASK /* battery is present */
1466 : 0; /* device not present */
1467}
1468
1469/**
1470 * Used by acpiR3BatDataRead to implement BAT_POWER_SOURCE.
1471 *
1472 * @returns status.
1473 * @param pThisCC The ACPI instance data for ring-3.
1474 */
1475static uint32_t acpiR3GetPowerSource(PACPISTATER3 pThisCC)
1476{
1477 /* query the current power source from the host driver */
1478 if (!pThisCC->pDrv)
1479 return AC_ONLINE;
1480
1481 PDMACPIPOWERSOURCE ps;
1482 int rc = pThisCC->pDrv->pfnQueryPowerSource(pThisCC->pDrv, &ps);
1483 AssertRC(rc);
1484 return ps == PDM_ACPI_POWER_SOURCE_BATTERY ? AC_OFFLINE : AC_ONLINE;
1485}
1486
1487/**
1488 * @callback_method_impl{FNIOMIOPORTNEWOUT, Battery status index}
1489 */
1490static DECLCALLBACK(VBOXSTRICTRC) acpiR3BatIndexWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT offPort, uint32_t u32, unsigned cb)
1491{
1492 RT_NOREF(pvUser, offPort);
1493 Log(("acpiR3BatIndexWrite: %#x (%#x)\n", u32, u32 >> 2));
1494 if (cb != 4)
1495 return PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "cb=%d offPort=%u u32=%#x\n", cb, offPort, u32);
1496
1497 PACPISTATE pThis = PDMDEVINS_2_DATA(pDevIns, PACPISTATE);
1498 DEVACPI_LOCK_R3(pDevIns, pThis);
1499
1500 u32 >>= pThis->u8IndexShift;
1501 /* see comment at the declaration of u8IndexShift */
1502 if (pThis->u8IndexShift == 0 && u32 == (BAT_DEVICE_STATUS << 2))
1503 {
1504 pThis->u8IndexShift = 2;
1505 u32 >>= 2;
1506 }
1507 ASSERT_GUEST_MSG(u32 < BAT_INDEX_LAST, ("%#x\n", u32));
1508 pThis->uBatteryIndex = u32;
1509
1510 DEVACPI_UNLOCK(pDevIns, pThis);
1511 return VINF_SUCCESS;
1512}
1513
1514/**
1515 * @callback_method_impl{FNIOMIOPORTNEWIN, Battery status data}
1516 */
1517static DECLCALLBACK(VBOXSTRICTRC) acpiR3BatDataRead(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT offPort, uint32_t *pu32, unsigned cb)
1518{
1519 RT_NOREF(pvUser, offPort);
1520 if (cb != 4)
1521 return VERR_IOM_IOPORT_UNUSED;
1522
1523 PACPISTATE pThis = PDMDEVINS_2_DATA(pDevIns, PACPISTATE);
1524 PACPISTATER3 pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PACPISTATER3);
1525 DEVACPI_LOCK_R3(pDevIns, pThis);
1526
1527 VBOXSTRICTRC rc = VINF_SUCCESS;
1528 switch (pThis->uBatteryIndex)
1529 {
1530 case BAT_STATUS_STATE:
1531 acpiR3FetchBatteryStatus(pThis, pThisCC);
1532 RT_FALL_THRU();
1533 case BAT_STATUS_PRESENT_RATE:
1534 case BAT_STATUS_REMAINING_CAPACITY:
1535 case BAT_STATUS_PRESENT_VOLTAGE:
1536 *pu32 = pThis->au8BatteryInfo[pThis->uBatteryIndex];
1537 break;
1538
1539 case BAT_INFO_UNITS:
1540 acpiR3FetchBatteryInfo(pThis);
1541 RT_FALL_THRU();
1542 case BAT_INFO_DESIGN_CAPACITY:
1543 case BAT_INFO_LAST_FULL_CHARGE_CAPACITY:
1544 case BAT_INFO_TECHNOLOGY:
1545 case BAT_INFO_DESIGN_VOLTAGE:
1546 case BAT_INFO_DESIGN_CAPACITY_OF_WARNING:
1547 case BAT_INFO_DESIGN_CAPACITY_OF_LOW:
1548 case BAT_INFO_CAPACITY_GRANULARITY_1:
1549 case BAT_INFO_CAPACITY_GRANULARITY_2:
1550 *pu32 = pThis->au8BatteryInfo[pThis->uBatteryIndex];
1551 break;
1552
1553 case BAT_DEVICE_STATUS:
1554 *pu32 = acpiR3GetBatteryDeviceStatus(pThisCC);
1555 break;
1556
1557 case BAT_POWER_SOURCE:
1558 *pu32 = acpiR3GetPowerSource(pThisCC);
1559 break;
1560
1561 default:
1562 rc = PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "cb=%d offPort=%u idx=%u\n", cb, offPort, pThis->uBatteryIndex);
1563 *pu32 = UINT32_MAX;
1564 break;
1565 }
1566
1567 DEVACPI_UNLOCK(pDevIns, pThis);
1568 return rc;
1569}
1570
1571/**
1572 * @callback_method_impl{FNIOMIOPORTNEWOUT, System info index}
1573 */
1574static DECLCALLBACK(VBOXSTRICTRC) acpiR3SysInfoIndexWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT offPort, uint32_t u32, unsigned cb)
1575{
1576 RT_NOREF(pvUser, offPort);
1577 Log(("acpiR3SysInfoIndexWrite: %#x (%#x)\n", u32, u32 >> 2));
1578 if (cb != 4)
1579 return PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "cb=%d offPort=%u u32=%#x\n", cb, offPort, u32);
1580
1581 PACPISTATE pThis = PDMDEVINS_2_DATA(pDevIns, PACPISTATE);
1582 DEVACPI_LOCK_R3(pDevIns, pThis);
1583
1584 if (u32 == SYSTEM_INFO_INDEX_VALID || u32 == SYSTEM_INFO_INDEX_INVALID)
1585 pThis->uSystemInfoIndex = u32;
1586 else
1587 {
1588 /* see comment at the declaration of u8IndexShift */
1589 if (u32 > SYSTEM_INFO_INDEX_END && pThis->u8IndexShift == 0)
1590 {
1591 if ((u32 >> 2) < SYSTEM_INFO_INDEX_END && (u32 & 0x3) == 0)
1592 pThis->u8IndexShift = 2;
1593 }
1594
1595 u32 >>= pThis->u8IndexShift;
1596
1597 /* If the index exceeds 31 (which is all we can fit within offset 0x80), we need to divide the index again
1598 for indices > 31 and < SYSTEM_INFO_INDEX_END. */
1599 if (u32 > SYSTEM_INFO_INDEX_END && pThis->u8IndexShift == 2 && (u32 >> 2) < SYSTEM_INFO_INDEX_END)
1600 u32 >>= 2;
1601
1602 ASSERT_GUEST_MSG(u32 < SYSTEM_INFO_INDEX_END, ("%u - Max=%u. IndexShift=%u\n", u32, SYSTEM_INFO_INDEX_END, pThis->u8IndexShift));
1603 pThis->uSystemInfoIndex = u32;
1604 }
1605
1606 DEVACPI_UNLOCK(pDevIns, pThis);
1607 return VINF_SUCCESS;
1608}
1609
1610/**
1611 * @callback_method_impl{FNIOMIOPORTNEWIN, System info data}
1612 */
1613static DECLCALLBACK(VBOXSTRICTRC) acpiR3SysInfoDataRead(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT offPort, uint32_t *pu32, unsigned cb)
1614{
1615 RT_NOREF(pvUser, offPort);
1616 if (cb != 4)
1617 return VERR_IOM_IOPORT_UNUSED;
1618
1619 PACPISTATE pThis = PDMDEVINS_2_DATA(pDevIns, PACPISTATE);
1620 DEVACPI_LOCK_R3(pDevIns, pThis);
1621
1622 VBOXSTRICTRC rc = VINF_SUCCESS;
1623 uint32_t const uSystemInfoIndex = pThis->uSystemInfoIndex;
1624 switch (uSystemInfoIndex)
1625 {
1626 case SYSTEM_INFO_INDEX_LOW_MEMORY_LENGTH:
1627 *pu32 = pThis->cbRamLow;
1628 break;
1629
1630 case SYSTEM_INFO_INDEX_PREF64_MEMORY_MIN:
1631 *pu32 = pThis->u64PciPref64Min >> 16; /* 64KB units */
1632 Assert(((uint64_t)*pu32 << 16) == pThis->u64PciPref64Min);
1633 break;
1634
1635 case SYSTEM_INFO_INDEX_PREF64_MEMORY_MAX:
1636 *pu32 = pThis->u64PciPref64Max >> 16; /* 64KB units */
1637 Assert(((uint64_t)*pu32 << 16) == pThis->u64PciPref64Max);
1638 break;
1639
1640 case SYSTEM_INFO_INDEX_USE_IOAPIC:
1641 *pu32 = pThis->u8UseIOApic;
1642 break;
1643
1644 case SYSTEM_INFO_INDEX_HPET_STATUS:
1645 *pu32 = pThis->fUseHpet
1646 ? ( STA_DEVICE_PRESENT_MASK
1647 | STA_DEVICE_ENABLED_MASK
1648 | STA_DEVICE_SHOW_IN_UI_MASK
1649 | STA_DEVICE_FUNCTIONING_PROPERLY_MASK)
1650 : 0;
1651 break;
1652
1653 case SYSTEM_INFO_INDEX_SMC_STATUS:
1654 *pu32 = pThis->fUseSmc
1655 ? ( STA_DEVICE_PRESENT_MASK
1656 | STA_DEVICE_ENABLED_MASK
1657 /* no need to show this device in the UI */
1658 | STA_DEVICE_FUNCTIONING_PROPERLY_MASK)
1659 : 0;
1660 break;
1661
1662 case SYSTEM_INFO_INDEX_FDC_STATUS:
1663 *pu32 = pThis->fUseFdc
1664 ? ( STA_DEVICE_PRESENT_MASK
1665 | STA_DEVICE_ENABLED_MASK
1666 | STA_DEVICE_SHOW_IN_UI_MASK
1667 | STA_DEVICE_FUNCTIONING_PROPERLY_MASK)
1668 : 0;
1669 break;
1670
1671 case SYSTEM_INFO_INDEX_NIC_ADDRESS:
1672 *pu32 = pThis->u32NicPciAddress;
1673 break;
1674
1675 case SYSTEM_INFO_INDEX_AUDIO_ADDRESS:
1676 *pu32 = pThis->u32AudioPciAddress;
1677 break;
1678
1679 case SYSTEM_INFO_INDEX_NVME_ADDRESS:
1680 *pu32 = pThis->u32NvmePciAddress;
1681 break;
1682
1683 case SYSTEM_INFO_INDEX_POWER_STATES:
1684 *pu32 = RT_BIT(0) | RT_BIT(5); /* S1 and S5 always exposed */
1685 if (pThis->fS1Enabled) /* Optionally expose S1 and S4 */
1686 *pu32 |= RT_BIT(1);
1687 if (pThis->fS4Enabled)
1688 *pu32 |= RT_BIT(4);
1689 break;
1690
1691 case SYSTEM_INFO_INDEX_IOC_ADDRESS:
1692 *pu32 = pThis->u32IocPciAddress;
1693 break;
1694
1695 case SYSTEM_INFO_INDEX_HBC_ADDRESS:
1696 *pu32 = pThis->u32HbcPciAddress;
1697 break;
1698
1699 case SYSTEM_INFO_INDEX_PCI_BASE:
1700 /** @todo couldn't MCFG be in 64-bit range? */
1701 Assert(pThis->u64PciConfigMMioAddress < 0xffffffff);
1702 *pu32 = (uint32_t)pThis->u64PciConfigMMioAddress;
1703 break;
1704
1705 case SYSTEM_INFO_INDEX_PCI_LENGTH:
1706 /** @todo couldn't MCFG be in 64-bit range? */
1707 Assert(pThis->u64PciConfigMMioLength < 0xffffffff);
1708 *pu32 = (uint32_t)pThis->u64PciConfigMMioLength;
1709 break;
1710
1711 case SYSTEM_INFO_INDEX_RTC_STATUS:
1712 *pu32 = pThis->fShowRtc
1713 ? ( STA_DEVICE_PRESENT_MASK
1714 | STA_DEVICE_ENABLED_MASK
1715 | STA_DEVICE_SHOW_IN_UI_MASK
1716 | STA_DEVICE_FUNCTIONING_PROPERLY_MASK)
1717 : 0;
1718 break;
1719
1720 case SYSTEM_INFO_INDEX_CPU_LOCKED:
1721 if (pThis->idCpuLockCheck < VMM_MAX_CPU_COUNT)
1722 {
1723 *pu32 = VMCPUSET_IS_PRESENT(&pThis->CpuSetLocked, pThis->idCpuLockCheck);
1724 pThis->idCpuLockCheck = UINT32_C(0xffffffff); /* Make the entry invalid */
1725 }
1726 else
1727 {
1728 rc = PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "CPU lock check protocol violation (idCpuLockCheck=%#x)\n",
1729 pThis->idCpuLockCheck);
1730 /* Always return locked status just to be safe */
1731 *pu32 = 1;
1732 }
1733 break;
1734
1735 case SYSTEM_INFO_INDEX_CPU_EVENT_TYPE:
1736 *pu32 = pThis->u32CpuEventType;
1737 break;
1738
1739 case SYSTEM_INFO_INDEX_CPU_EVENT:
1740 *pu32 = pThis->u32CpuEvent;
1741 break;
1742
1743 case SYSTEM_INFO_INDEX_SERIAL0_IOBASE:
1744 *pu32 = pThis->uSerial0IoPortBase;
1745 break;
1746
1747 case SYSTEM_INFO_INDEX_SERIAL0_IRQ:
1748 *pu32 = pThis->uSerial0Irq;
1749 break;
1750
1751 case SYSTEM_INFO_INDEX_SERIAL1_IOBASE:
1752 *pu32 = pThis->uSerial1IoPortBase;
1753 break;
1754
1755 case SYSTEM_INFO_INDEX_SERIAL1_IRQ:
1756 *pu32 = pThis->uSerial1Irq;
1757 break;
1758
1759 case SYSTEM_INFO_INDEX_SERIAL2_IOBASE:
1760 *pu32 = pThis->uSerial2IoPortBase;
1761 break;
1762
1763 case SYSTEM_INFO_INDEX_SERIAL2_IRQ:
1764 *pu32 = pThis->uSerial2Irq;
1765 break;
1766
1767 case SYSTEM_INFO_INDEX_SERIAL3_IOBASE:
1768 *pu32 = pThis->uSerial3IoPortBase;
1769 break;
1770
1771 case SYSTEM_INFO_INDEX_SERIAL3_IRQ:
1772 *pu32 = pThis->uSerial3Irq;
1773 break;
1774
1775 case SYSTEM_INFO_INDEX_PARALLEL0_IOBASE:
1776 *pu32 = pThis->uParallel0IoPortBase;
1777 break;
1778
1779 case SYSTEM_INFO_INDEX_PARALLEL0_IRQ:
1780 *pu32 = pThis->uParallel0Irq;
1781 break;
1782
1783 case SYSTEM_INFO_INDEX_PARALLEL1_IOBASE:
1784 *pu32 = pThis->uParallel1IoPortBase;
1785 break;
1786
1787 case SYSTEM_INFO_INDEX_PARALLEL1_IRQ:
1788 *pu32 = pThis->uParallel1Irq;
1789 break;
1790
1791 case SYSTEM_INFO_INDEX_IOMMU_ADDRESS:
1792 *pu32 = pThis->u32IommuPciAddress;
1793 break;
1794
1795 case SYSTEM_INFO_INDEX_SB_IOAPIC_ADDRESS:
1796 *pu32 = pThis->u32SbIoApicPciAddress;
1797 break;
1798
1799 case SYSTEM_INFO_INDEX_END:
1800 /** @todo why isn't this setting any output value? */
1801 break;
1802
1803 /* Solaris 9 tries to read from this index */
1804 case SYSTEM_INFO_INDEX_INVALID:
1805 *pu32 = 0;
1806 break;
1807
1808 default:
1809 *pu32 = UINT32_MAX;
1810 rc = PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "cb=%d offPort=%u idx=%u\n", cb, offPort, uSystemInfoIndex);
1811 break;
1812 }
1813
1814 DEVACPI_UNLOCK(pDevIns, pThis);
1815 Log(("acpiR3SysInfoDataRead: idx=%d val=%#x (%u) rc=%Rrc\n", uSystemInfoIndex, *pu32, *pu32, VBOXSTRICTRC_VAL(rc)));
1816 return rc;
1817}
1818
1819/**
1820 * @callback_method_impl{FNIOMIOPORTNEWOUT, System info data}
1821 */
1822static DECLCALLBACK(VBOXSTRICTRC) acpiR3SysInfoDataWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT offPort, uint32_t u32, unsigned cb)
1823{
1824 RT_NOREF(pvUser, offPort);
1825 PACPISTATE pThis = PDMDEVINS_2_DATA(pDevIns, PACPISTATE);
1826 if (cb != 4)
1827 return PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "cb=%d offPort=%u u32=%#x idx=%u\n", cb, offPort, u32, pThis->uSystemInfoIndex);
1828
1829 DEVACPI_LOCK_R3(pDevIns, pThis);
1830 Log(("addr=%#x cb=%d u32=%#x si=%#x\n", offPort, cb, u32, pThis->uSystemInfoIndex));
1831
1832 VBOXSTRICTRC rc = VINF_SUCCESS;
1833 switch (pThis->uSystemInfoIndex)
1834 {
1835 case SYSTEM_INFO_INDEX_INVALID:
1836 AssertMsg(u32 == 0xbadc0de, ("u32=%u\n", u32));
1837 pThis->u8IndexShift = 0;
1838 break;
1839
1840 case SYSTEM_INFO_INDEX_VALID:
1841 AssertMsg(u32 == 0xbadc0de, ("u32=%u\n", u32));
1842 pThis->u8IndexShift = 2;
1843 break;
1844
1845 case SYSTEM_INFO_INDEX_CPU_LOCK_CHECK:
1846 pThis->idCpuLockCheck = u32;
1847 break;
1848
1849 case SYSTEM_INFO_INDEX_CPU_LOCKED:
1850 if (u32 < pThis->cCpus)
1851 VMCPUSET_DEL(&pThis->CpuSetLocked, u32); /* Unlock the CPU */
1852 else
1853 LogRel(("ACPI: CPU %u does not exist\n", u32));
1854 break;
1855
1856 default:
1857 rc = PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "cb=%d offPort=%u u32=%#x idx=%u\n", cb, offPort, u32, pThis->uSystemInfoIndex);
1858 break;
1859 }
1860
1861 DEVACPI_UNLOCK(pDevIns, pThis);
1862 return rc;
1863}
1864
1865/**
1866 * @callback_method_impl{FNIOMIOPORTNEWIN, PM1a Enable}
1867 */
1868static DECLCALLBACK(VBOXSTRICTRC) acpiR3Pm1aEnRead(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT offPort, uint32_t *pu32, unsigned cb)
1869{
1870 RT_NOREF(offPort, pvUser);
1871 if (cb != 2)
1872 return VERR_IOM_IOPORT_UNUSED;
1873
1874 PACPISTATE pThis = PDMDEVINS_2_DATA(pDevIns, PACPISTATE);
1875 DEVACPI_LOCK_R3(pDevIns, pThis);
1876
1877 *pu32 = pThis->pm1a_en;
1878
1879 DEVACPI_UNLOCK(pDevIns, pThis);
1880 Log(("acpiR3Pm1aEnRead -> %#x\n", *pu32));
1881 return VINF_SUCCESS;
1882}
1883
1884/**
1885 * @callback_method_impl{FNIOMIOPORTNEWOUT, PM1a Enable}
1886 */
1887static DECLCALLBACK(VBOXSTRICTRC) acpiR3PM1aEnWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT offPort, uint32_t u32, unsigned cb)
1888{
1889 RT_NOREF(offPort, pvUser);
1890 if (cb != 2 && cb != 4)
1891 return PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "cb=%d offPort=%u u32=%#x\n", cb, offPort, u32);
1892
1893 PACPISTATE pThis = PDMDEVINS_2_DATA(pDevIns, PACPISTATE);
1894 DEVACPI_LOCK_R3(pDevIns, pThis);
1895
1896 Log(("acpiR3PM1aEnWrite: %#x (%#x)\n", u32, u32 & ~(RSR_EN | IGN_EN) & 0xffff));
1897 u32 &= ~(RSR_EN | IGN_EN);
1898 u32 &= 0xffff;
1899 acpiUpdatePm1a(pDevIns, pThis, pThis->pm1a_sts, u32);
1900
1901 DEVACPI_UNLOCK(pDevIns, pThis);
1902 return VINF_SUCCESS;
1903}
1904
1905/**
1906 * @callback_method_impl{FNIOMIOPORTNEWIN, PM1a Status}
1907 */
1908static DECLCALLBACK(VBOXSTRICTRC) acpiR3Pm1aStsRead(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT offPort, uint32_t *pu32, unsigned cb)
1909{
1910 RT_NOREF(offPort, pvUser);
1911 if (cb != 2)
1912 {
1913 int rc = PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "cb=%d offPort=%u\n", cb, offPort);
1914 return rc == VINF_SUCCESS ? VERR_IOM_IOPORT_UNUSED : rc;
1915 }
1916
1917 PACPISTATE pThis = PDMDEVINS_2_DATA(pDevIns, PACPISTATE);
1918 DEVACPI_LOCK_R3(pDevIns, pThis);
1919
1920 *pu32 = pThis->pm1a_sts;
1921
1922 DEVACPI_UNLOCK(pDevIns, pThis);
1923 Log(("acpiR3Pm1aStsRead: %#x\n", *pu32));
1924 return VINF_SUCCESS;
1925}
1926
1927/**
1928 * @callback_method_impl{FNIOMIOPORTNEWOUT, PM1a Status}
1929 */
1930static DECLCALLBACK(VBOXSTRICTRC) acpiR3PM1aStsWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT offPort, uint32_t u32, unsigned cb)
1931{
1932 RT_NOREF(offPort, pvUser);
1933 if (cb != 2 && cb != 4)
1934 return PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "cb=%d offPort=%u u32=%#x\n", cb, offPort, u32);
1935
1936 PACPISTATE pThis = PDMDEVINS_2_DATA(pDevIns, PACPISTATE);
1937 DEVACPI_LOCK_R3(pDevIns, pThis);
1938
1939 Log(("acpiR3PM1aStsWrite: %#x (%#x)\n", u32, u32 & ~(RSR_STS | IGN_STS) & 0xffff));
1940 u32 &= 0xffff;
1941 if (u32 & PWRBTN_STS)
1942 pThis->fPowerButtonHandled = true; /* Remember that the guest handled the last power button event */
1943 u32 = pThis->pm1a_sts & ~(u32 & ~(RSR_STS | IGN_STS));
1944 acpiUpdatePm1a(pDevIns, pThis, u32, pThis->pm1a_en);
1945
1946 DEVACPI_UNLOCK(pDevIns, pThis);
1947 return VINF_SUCCESS;
1948}
1949
1950/**
1951 * @callback_method_impl{FNIOMIOPORTNEWIN, PM1a Control}
1952 */
1953static DECLCALLBACK(VBOXSTRICTRC) acpiR3Pm1aCtlRead(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT offPort, uint32_t *pu32, unsigned cb)
1954{
1955 RT_NOREF(offPort, pvUser);
1956 if (cb != 2)
1957 {
1958 int rc = PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "cb=%d offPort=%u\n", cb, offPort);
1959 return rc == VINF_SUCCESS ? VERR_IOM_IOPORT_UNUSED : rc;
1960 }
1961
1962 PACPISTATE pThis = PDMDEVINS_2_DATA(pDevIns, PACPISTATE);
1963 DEVACPI_LOCK_R3(pDevIns, pThis);
1964
1965 *pu32 = pThis->pm1a_ctl;
1966
1967 DEVACPI_UNLOCK(pDevIns, pThis);
1968 Log(("acpiR3Pm1aCtlRead: %#x\n", *pu32));
1969 return VINF_SUCCESS;
1970}
1971
1972/**
1973 * @callback_method_impl{FNIOMIOPORTNEWOUT, PM1a Control}
1974 */
1975static DECLCALLBACK(VBOXSTRICTRC) acpiR3PM1aCtlWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT offPort, uint32_t u32, unsigned cb)
1976{
1977 RT_NOREF(offPort, pvUser);
1978 if (cb != 2 && cb != 4)
1979 return PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "cb=%d offPort=%u u32=%#x\n", cb, offPort, u32);
1980
1981 PACPISTATE pThis = PDMDEVINS_2_DATA(pDevIns, PACPISTATE);
1982 DEVACPI_LOCK_R3(pDevIns, pThis);
1983
1984 Log(("acpiR3PM1aCtlWrite: %#x (%#x)\n", u32, u32 & ~(RSR_CNT | IGN_CNT) & 0xffff));
1985 u32 &= 0xffff;
1986 pThis->pm1a_ctl = u32 & ~(RSR_CNT | IGN_CNT);
1987
1988 VBOXSTRICTRC rc = VINF_SUCCESS;
1989 uint32_t const uSleepState = (pThis->pm1a_ctl >> SLP_TYPx_SHIFT) & SLP_TYPx_MASK;
1990 if (uSleepState != pThis->uSleepState)
1991 {
1992 pThis->uSleepState = uSleepState;
1993 switch (uSleepState)
1994 {
1995 case 0x00: /* S0 */
1996 break;
1997
1998 case 0x01: /* S1 */
1999 if (pThis->fS1Enabled)
2000 {
2001 LogRel(("ACPI: Entering S1 power state (powered-on suspend)\n"));
2002 rc = acpiR3DoSleep(pDevIns, pThis);
2003 break;
2004 }
2005 LogRel(("ACPI: Ignoring guest attempt to enter S1 power state (powered-on suspend)!\n"));
2006 RT_FALL_THRU();
2007
2008 case 0x04: /* S4 */
2009 if (pThis->fS4Enabled)
2010 {
2011 LogRel(("ACPI: Entering S4 power state (suspend to disk)\n"));
2012 rc = acpiR3DoPowerOff(pDevIns);/* Same behavior as S5 */
2013 break;
2014 }
2015 LogRel(("ACPI: Ignoring guest attempt to enter S4 power state (suspend to disk)!\n"));
2016 RT_FALL_THRU();
2017
2018 case 0x05: /* S5 */
2019 LogRel(("ACPI: Entering S5 power state (power down)\n"));
2020 rc = acpiR3DoPowerOff(pDevIns);
2021 break;
2022
2023 default:
2024 rc = PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "Unknown sleep state %#x (u32=%#x)\n", uSleepState, u32);
2025 break;
2026 }
2027 }
2028
2029 DEVACPI_UNLOCK(pDevIns, pThis);
2030 Log(("acpiR3PM1aCtlWrite: rc=%Rrc\n", VBOXSTRICTRC_VAL(rc)));
2031 return rc;
2032}
2033
2034#endif /* IN_RING3 */
2035
2036/**
2037 * @callback_method_impl{FNIOMIOPORTNEWIN, PMTMR}
2038 *
2039 * @remarks The only I/O port currently implemented in all contexts.
2040 */
2041static DECLCALLBACK(VBOXSTRICTRC) acpiPMTmrRead(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT offPort, uint32_t *pu32, unsigned cb)
2042{
2043 RT_NOREF(offPort, pvUser);
2044 if (cb != 4)
2045 return VERR_IOM_IOPORT_UNUSED;
2046
2047 /*
2048 * We use the clock lock to serialize access to u64PmTimerInitial and to
2049 * make sure we get a reliable time from the clock
2050 * as well as and to prevent uPmTimerVal from being updated during read.
2051 */
2052 PACPISTATE pThis = PDMDEVINS_2_DATA(pDevIns, PACPISTATE);
2053 VBOXSTRICTRC rc = PDMDevHlpTimerLockClock2(pDevIns, pThis->hPmTimer, &pThis->CritSect, VINF_IOM_R3_IOPORT_READ);
2054 if (rc == VINF_SUCCESS)
2055 {
2056 uint64_t u64Now = PDMDevHlpTimerGet(pDevIns, pThis->hPmTimer);
2057 acpiPmTimerUpdate(pDevIns, pThis, u64Now);
2058 *pu32 = pThis->uPmTimerVal;
2059
2060 PDMDevHlpTimerUnlockClock2(pDevIns, pThis->hPmTimer, &pThis->CritSect);
2061
2062 DBGFTRACE_PDM_U64_TAG(pDevIns, u64Now, "acpi");
2063 Log(("acpi: acpiPMTmrRead -> %#x\n", *pu32));
2064
2065#if 0
2066 /** @todo temporary: sanity check against running backwards */
2067 uint32_t uOld = ASMAtomicXchgU32(&pThis->uPmTimeOld, *pu32);
2068 if (*pu32 - uOld >= 0x10000000)
2069 {
2070# if defined(IN_RING0)
2071 pThis->uPmTimeA = uOld;
2072 pThis->uPmTimeB = *pu32;
2073 return VERR_TM_TIMER_BAD_CLOCK;
2074# elif defined(IN_RING3)
2075 AssertReleaseMsgFailed(("acpiPMTmrRead: old=%08RX32, current=%08RX32\n", uOld, *pu32));
2076# endif
2077 }
2078#endif
2079 }
2080 return rc;
2081}
2082
2083#ifdef IN_RING3
2084
2085/**
2086 * @callback_method_impl{FNIOMIOPORTNEWIN, GPE0 Status}
2087 */
2088static DECLCALLBACK(VBOXSTRICTRC) acpiR3Gpe0StsRead(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT offPort, uint32_t *pu32, unsigned cb)
2089{
2090 RT_NOREF(offPort, pvUser);
2091 if (cb != 1)
2092 {
2093 int rc = PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "cb=%d offPort=%u\n", cb, offPort);
2094 return rc == VINF_SUCCESS ? VERR_IOM_IOPORT_UNUSED : rc;
2095 }
2096
2097 PACPISTATE pThis = PDMDEVINS_2_DATA(pDevIns, PACPISTATE);
2098 DEVACPI_LOCK_R3(pDevIns, pThis);
2099
2100 *pu32 = pThis->gpe0_sts & 0xff;
2101
2102 DEVACPI_UNLOCK(pDevIns, pThis);
2103 Log(("acpiR3Gpe0StsRead: %#x\n", *pu32));
2104 return VINF_SUCCESS;
2105}
2106
2107/**
2108 * @callback_method_impl{FNIOMIOPORTNEWOUT, GPE0 Status}
2109 */
2110static DECLCALLBACK(VBOXSTRICTRC) acpiR3Gpe0StsWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT offPort, uint32_t u32, unsigned cb)
2111{
2112 RT_NOREF(offPort, pvUser);
2113 if (cb != 1)
2114 return PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "cb=%d offPort=%u u32=%#x\n", cb, offPort, u32);
2115
2116 PACPISTATE pThis = PDMDEVINS_2_DATA(pDevIns, PACPISTATE);
2117 DEVACPI_LOCK_R3(pDevIns, pThis);
2118
2119 Log(("acpiR3Gpe0StsWrite: %#x (%#x)\n", u32, pThis->gpe0_sts & ~u32));
2120 u32 = pThis->gpe0_sts & ~u32;
2121 apicR3UpdateGpe0(pDevIns, pThis, u32, pThis->gpe0_en);
2122
2123 DEVACPI_UNLOCK(pDevIns, pThis);
2124 return VINF_SUCCESS;
2125}
2126
2127/**
2128 * @callback_method_impl{FNIOMIOPORTNEWIN, GPE0 Enable}
2129 */
2130static DECLCALLBACK(VBOXSTRICTRC) acpiR3Gpe0EnRead(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT offPort, uint32_t *pu32, unsigned cb)
2131{
2132 RT_NOREF(offPort, pvUser);
2133 if (cb != 1)
2134 {
2135 int rc = PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "cb=%d offPort=%u\n", cb, offPort);
2136 return rc == VINF_SUCCESS ? VERR_IOM_IOPORT_UNUSED : rc;
2137 }
2138
2139 PACPISTATE pThis = PDMDEVINS_2_DATA(pDevIns, PACPISTATE);
2140 DEVACPI_LOCK_R3(pDevIns, pThis);
2141
2142 *pu32 = pThis->gpe0_en & 0xff;
2143
2144 DEVACPI_UNLOCK(pDevIns, pThis);
2145 Log(("acpiR3Gpe0EnRead: %#x\n", *pu32));
2146 return VINF_SUCCESS;
2147}
2148
2149/**
2150 * @callback_method_impl{FNIOMIOPORTNEWOUT, GPE0 Enable}
2151 */
2152static DECLCALLBACK(VBOXSTRICTRC) acpiR3Gpe0EnWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT offPort, uint32_t u32, unsigned cb)
2153{
2154 RT_NOREF(offPort, pvUser);
2155 if (cb != 1)
2156 return PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "cb=%d offPort=%u u32=%#x\n", cb, offPort, u32);
2157
2158 PACPISTATE pThis = PDMDEVINS_2_DATA(pDevIns, PACPISTATE);
2159 DEVACPI_LOCK_R3(pDevIns, pThis);
2160
2161 Log(("acpiR3Gpe0EnWrite: %#x\n", u32));
2162 apicR3UpdateGpe0(pDevIns, pThis, pThis->gpe0_sts, u32);
2163
2164 DEVACPI_UNLOCK(pDevIns, pThis);
2165 return VINF_SUCCESS;
2166}
2167
2168/**
2169 * @callback_method_impl{FNIOMIOPORTNEWOUT, SMI_CMD}
2170 */
2171static DECLCALLBACK(VBOXSTRICTRC) acpiR3SmiWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT offPort, uint32_t u32, unsigned cb)
2172{
2173 RT_NOREF(offPort, pvUser);
2174 Log(("acpiR3SmiWrite %#x\n", u32));
2175 if (cb != 1)
2176 return PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "cb=%d offPort=%u u32=%#x\n", cb, offPort, u32);
2177
2178 PACPISTATE pThis = PDMDEVINS_2_DATA(pDevIns, PACPISTATE);
2179 DEVACPI_LOCK_R3(pDevIns, pThis);
2180
2181 if (u32 == ACPI_ENABLE)
2182 pThis->pm1a_ctl |= SCI_EN;
2183 else if (u32 == ACPI_DISABLE)
2184 pThis->pm1a_ctl &= ~SCI_EN;
2185 else
2186 Log(("acpiR3SmiWrite: %#x <- unknown value\n", u32));
2187
2188 DEVACPI_UNLOCK(pDevIns, pThis);
2189 return VINF_SUCCESS;
2190}
2191
2192/**
2193 * @callback_method_impl{FNIOMIOPORTNEWOUT, ACPI_RESET_BLK}
2194 */
2195static DECLCALLBACK(VBOXSTRICTRC) acpiR3ResetWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT offPort, uint32_t u32, unsigned cb)
2196{
2197 RT_NOREF(offPort, pvUser);
2198 Log(("acpiR3ResetWrite: %#x\n", u32));
2199 NOREF(pvUser);
2200 if (cb != 1)
2201 return PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "cb=%d offPort=%u u32=%#x\n", cb, offPort, u32);
2202
2203 /* No state locking required. */
2204 VBOXSTRICTRC rc;
2205 if (u32 == ACPI_RESET_REG_VAL)
2206 {
2207 LogRel(("ACPI: Reset initiated by ACPI\n"));
2208 rc = PDMDevHlpVMReset(pDevIns, PDMVMRESET_F_ACPI);
2209 }
2210 else
2211 {
2212 Log(("acpiR3ResetWrite: %#x <- unknown value\n", u32));
2213 rc = VINF_SUCCESS;
2214 }
2215
2216 return rc;
2217}
2218
2219# ifdef DEBUG_ACPI
2220
2221/**
2222 * @callback_method_impl{FNIOMIOPORTNEWOUT, Debug hex value logger}
2223 */
2224static DECLCALLBACK(VBOXSTRICTRC) acpiR3DebugHexWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT offPort, uint32_t u32, unsigned cb)
2225{
2226 NOREF(pvUser);
2227 switch (cb)
2228 {
2229 case 1:
2230 Log(("%#x\n", u32 & 0xff));
2231 break;
2232 case 2:
2233 Log(("%#6x\n", u32 & 0xffff));
2234 break;
2235 case 4:
2236 Log(("%#10x\n", u32));
2237 break;
2238 default:
2239 return PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "cb=%d offPort=%u u32=%#x\n", cb, offPort, u32);
2240 }
2241 return VINF_SUCCESS;
2242}
2243
2244/**
2245 * @callback_method_impl{FNIOMIOPORTNEWOUT, Debug char logger}
2246 */
2247static DECLCALLBACK(VBOXSTRICTRC) acpiR3DebugCharWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT offPort, uint32_t u32, unsigned cb)
2248{
2249 NOREF(pvUser);
2250 switch (cb)
2251 {
2252 case 1:
2253 Log(("%c", u32 & 0xff));
2254 break;
2255 default:
2256 return PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "cb=%d offPort=%u u32=%#x\n", cb, offPort, u32);
2257 }
2258 return VINF_SUCCESS;
2259}
2260
2261# endif /* DEBUG_ACPI */
2262
2263/**
2264 * @callback_method_impl{FNDBGFHANDLERDEV}
2265 */
2266static DECLCALLBACK(void) acpiR3Info(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
2267{
2268 RT_NOREF(pszArgs);
2269 PACPISTATE pThis = PDMDEVINS_2_DATA(pDevIns, PACPISTATE);
2270 pHlp->pfnPrintf(pHlp,
2271 "timer: old=%08RX32, current=%08RX32\n", pThis->uPmTimeA, pThis->uPmTimeB);
2272}
2273
2274/**
2275 * Called by acpiR3Reset and acpiR3Construct to set up the PM PCI config space.
2276 *
2277 * @param pDevIns The PDM device instance.
2278 * @param pThis The ACPI shared instance data.
2279 */
2280static void acpiR3PmPCIBIOSFake(PPDMDEVINS pDevIns, PACPISTATE pThis)
2281{
2282 PPDMPCIDEV pPciDev = pDevIns->apPciDevs[0];
2283 pPciDev->abConfig[PMBA ] = pThis->uPmIoPortBase | 1; /* PMBA, PM base address, bit 0 marks it as IO range */
2284 pPciDev->abConfig[PMBA + 1] = pThis->uPmIoPortBase >> 8;
2285 pPciDev->abConfig[PMBA + 2] = 0x00;
2286 pPciDev->abConfig[PMBA + 3] = 0x00;
2287}
2288
2289/**
2290 * Used to calculate the value of a PM I/O port.
2291 *
2292 * @returns The actual I/O port value.
2293 * @param pThis The ACPI shared instance data.
2294 * @param offset The offset into the I/O space, or -1 if invalid.
2295 */
2296static RTIOPORT acpiR3CalcPmPort(PACPISTATE pThis, int32_t offset)
2297{
2298 Assert(pThis->uPmIoPortBase != 0);
2299
2300 if (offset == -1)
2301 return 0;
2302
2303 return (RTIOPORT)(pThis->uPmIoPortBase + offset);
2304}
2305
2306/**
2307 * Called by acpiR3LoadState and acpiR3UpdatePmHandlers to map the PM1a, PM
2308 * timer and GPE0 I/O ports.
2309 *
2310 * @returns VBox status code.
2311 * @param pDevIns The device instance.
2312 * @param pThis The ACPI shared instance data.
2313 */
2314static int acpiR3MapPmIoPorts(PPDMDEVINS pDevIns, PACPISTATE pThis)
2315{
2316 if (pThis->uPmIoPortBase == 0)
2317 return VINF_SUCCESS;
2318
2319 int rc;
2320 rc = PDMDevHlpIoPortMap(pDevIns, pThis->hIoPortPm1aSts, acpiR3CalcPmPort(pThis, PM1a_EVT_OFFSET));
2321 AssertRCReturn(rc, rc);
2322 rc = PDMDevHlpIoPortMap(pDevIns, pThis->hIoPortPm1aEn, acpiR3CalcPmPort(pThis, PM1a_EVT_OFFSET + 2));
2323 AssertRCReturn(rc, rc);
2324 rc = PDMDevHlpIoPortMap(pDevIns, pThis->hIoPortPm1aCtl, acpiR3CalcPmPort(pThis, PM1a_CTL_OFFSET));
2325 AssertRCReturn(rc, rc);
2326 rc = PDMDevHlpIoPortMap(pDevIns, pThis->hIoPortPmTimer, acpiR3CalcPmPort(pThis, PM_TMR_OFFSET));
2327 AssertRCReturn(rc, rc);
2328 rc = PDMDevHlpIoPortMap(pDevIns, pThis->hIoPortGpe0Sts, acpiR3CalcPmPort(pThis, GPE0_OFFSET));
2329 AssertRCReturn(rc, rc);
2330 rc = PDMDevHlpIoPortMap(pDevIns, pThis->hIoPortGpe0En, acpiR3CalcPmPort(pThis, GPE0_OFFSET + GPE0_BLK_LEN / 2));
2331
2332 return VINF_SUCCESS;
2333}
2334
2335/**
2336 * Called by acpiR3LoadState and acpiR3UpdatePmHandlers to unmap the PM1a, PM
2337 * timer and GPE0 I/O ports.
2338 *
2339 * @returns VBox status code.
2340 * @param pDevIns The device instance.
2341 * @param pThis The ACPI shared instance data.
2342 */
2343static int acpiR3UnmapPmIoPorts(PPDMDEVINS pDevIns, PACPISTATE pThis)
2344{
2345 if (pThis->uPmIoPortBase != 0)
2346 {
2347 int rc;
2348 rc = PDMDevHlpIoPortUnmap(pDevIns, pThis->hIoPortPm1aSts);
2349 AssertRCReturn(rc, rc);
2350 rc = PDMDevHlpIoPortUnmap(pDevIns, pThis->hIoPortPm1aEn);
2351 AssertRCReturn(rc, rc);
2352 rc = PDMDevHlpIoPortUnmap(pDevIns, pThis->hIoPortPm1aCtl);
2353 AssertRCReturn(rc, rc);
2354 rc = PDMDevHlpIoPortUnmap(pDevIns, pThis->hIoPortPmTimer);
2355 AssertRCReturn(rc, rc);
2356 rc = PDMDevHlpIoPortUnmap(pDevIns, pThis->hIoPortGpe0Sts);
2357 AssertRCReturn(rc, rc);
2358 rc = PDMDevHlpIoPortUnmap(pDevIns, pThis->hIoPortGpe0En);
2359 AssertRCReturn(rc, rc);
2360 }
2361 return VINF_SUCCESS;
2362}
2363
2364/**
2365 * Called by acpiR3PciConfigWrite and acpiReset to change the location of the
2366 * PM1a, PM timer and GPE0 ports.
2367 *
2368 * @returns VBox status code.
2369 *
2370 * @param pDevIns The device instance.
2371 * @param pThis The ACPI shared instance data.
2372 * @param pThisCC The ACPI instance data for ring-3.
2373 * @param NewIoPortBase The new base address of the I/O ports.
2374 */
2375static int acpiR3UpdatePmHandlers(PPDMDEVINS pDevIns, PACPISTATE pThis, PACPISTATER3 pThisCC, RTIOPORT NewIoPortBase)
2376{
2377 Log(("acpi: rebasing PM 0x%x -> 0x%x\n", pThis->uPmIoPortBase, NewIoPortBase));
2378 if (NewIoPortBase != pThis->uPmIoPortBase)
2379 {
2380 int rc = acpiR3UnmapPmIoPorts(pDevIns, pThis);
2381 if (RT_FAILURE(rc))
2382 return rc;
2383
2384 pThis->uPmIoPortBase = NewIoPortBase;
2385
2386 rc = acpiR3MapPmIoPorts(pDevIns, pThis);
2387 if (RT_FAILURE(rc))
2388 return rc;
2389
2390 /* We have to update FADT table acccording to the new base */
2391 rc = acpiR3PlantTables(pDevIns, pThis, pThisCC);
2392 AssertRC(rc);
2393 if (RT_FAILURE(rc))
2394 return rc;
2395 }
2396
2397 return VINF_SUCCESS;
2398}
2399
2400/**
2401 * @callback_method_impl{FNIOMIOPORTNEWOUT, SMBus}
2402 */
2403static DECLCALLBACK(VBOXSTRICTRC) acpiR3SMBusWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT offPort, uint32_t u32, unsigned cb)
2404{
2405 RT_NOREF(pvUser);
2406 PACPISTATE pThis = PDMDEVINS_2_DATA(pDevIns, PACPISTATE);
2407
2408 LogFunc(("offPort=%#x u32=%#x cb=%u\n", offPort, u32, cb));
2409 uint8_t off = offPort & 0x000f;
2410 if ( (cb != 1 && off <= SMBSHDWCMD_OFF)
2411 || (cb != 2 && (off == SMBSLVEVT_OFF || off == SMBSLVDAT_OFF)))
2412 return PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "cb=%d offPort=%u u32=%#x\n", cb, offPort, u32);
2413
2414 DEVACPI_LOCK_R3(pDevIns, pThis);
2415 switch (off)
2416 {
2417 case SMBHSTSTS_OFF:
2418 /* Bit 0 is readonly, bits 1..4 are write clear, bits 5..7 are reserved */
2419 pThis->u8SMBusHstSts &= ~(u32 & SMBHSTSTS_INT_MASK);
2420 break;
2421 case SMBSLVSTS_OFF:
2422 /* Bit 0 is readonly, bit 1 is reserved, bits 2..5 are write clear, bits 6..7 are reserved */
2423 pThis->u8SMBusSlvSts &= ~(u32 & SMBSLVSTS_WRITE_MASK);
2424 break;
2425 case SMBHSTCNT_OFF:
2426 {
2427 Assert(PDMDevHlpCritSectIsOwner(pDevIns, &pThis->CritSect));
2428
2429 const bool old_level = acpiSCILevel(pDevIns, pThis);
2430 pThis->u8SMBusHstCnt = u32 & SMBHSTCNT_WRITE_MASK;
2431 if (u32 & SMBHSTCNT_START)
2432 {
2433 /* Start, trigger error as this is a dummy implementation */
2434 pThis->u8SMBusHstSts |= SMBHSTSTS_DEV_ERR | SMBHSTSTS_INTER;
2435 }
2436 if (u32 & SMBHSTCNT_KILL)
2437 {
2438 /* Kill */
2439 pThis->u8SMBusHstSts |= SMBHSTSTS_FAILED | SMBHSTSTS_INTER;
2440 }
2441 const bool new_level = acpiSCILevel(pDevIns, pThis);
2442
2443 LogFunc(("old=%x new=%x\n", old_level, new_level));
2444
2445 /* This handles only SCI/IRQ9. SMI# makes not much sense today and
2446 * needs to be implemented later if it ever becomes relevant. */
2447 if (new_level != old_level)
2448 acpiSetIrq(pDevIns, new_level);
2449 break;
2450 }
2451 case SMBHSTCMD_OFF:
2452 pThis->u8SMBusHstCmd = u32;
2453 break;
2454 case SMBHSTADD_OFF:
2455 pThis->u8SMBusHstAdd = u32;
2456 break;
2457 case SMBHSTDAT0_OFF:
2458 pThis->u8SMBusHstDat0 = u32;
2459 break;
2460 case SMBHSTDAT1_OFF:
2461 pThis->u8SMBusHstDat1 = u32;
2462 break;
2463 case SMBBLKDAT_OFF:
2464 pThis->au8SMBusBlkDat[pThis->u8SMBusBlkIdx] = u32;
2465 pThis->u8SMBusBlkIdx++;
2466 pThis->u8SMBusBlkIdx &= sizeof(pThis->au8SMBusBlkDat) - 1;
2467 break;
2468 case SMBSLVCNT_OFF:
2469 pThis->u8SMBusSlvCnt = u32 & SMBSLVCNT_WRITE_MASK;
2470 break;
2471 case SMBSHDWCMD_OFF:
2472 /* readonly register */
2473 break;
2474 case SMBSLVEVT_OFF:
2475 pThis->u16SMBusSlvEvt = u32;
2476 break;
2477 case SMBSLVDAT_OFF:
2478 /* readonly register */
2479 break;
2480 default:
2481 /* caught by the sanity check above */
2482 ;
2483 }
2484
2485 DEVACPI_UNLOCK(pDevIns, pThis);
2486 return VINF_SUCCESS;
2487}
2488
2489/**
2490 * @callback_method_impl{FNIOMIOPORTNEWIN, SMBus}
2491 */
2492static DECLCALLBACK(VBOXSTRICTRC) acpiR3SMBusRead(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT offPort, uint32_t *pu32, unsigned cb)
2493{
2494 RT_NOREF(pvUser);
2495 PACPISTATE pThis = PDMDEVINS_2_DATA(pDevIns, PACPISTATE);
2496
2497 VBOXSTRICTRC rc = VINF_SUCCESS;
2498 LogFunc(("offPort=%#x cb=%u\n", offPort, cb));
2499 uint8_t const off = offPort & 0x000f;
2500 if ( (cb != 1 && off <= SMBSHDWCMD_OFF)
2501 || (cb != 2 && (off == SMBSLVEVT_OFF || off == SMBSLVDAT_OFF)))
2502 return VERR_IOM_IOPORT_UNUSED;
2503
2504 DEVACPI_LOCK_R3(pDevIns, pThis);
2505 switch (off)
2506 {
2507 case SMBHSTSTS_OFF:
2508 *pu32 = pThis->u8SMBusHstSts;
2509 break;
2510 case SMBSLVSTS_OFF:
2511 *pu32 = pThis->u8SMBusSlvSts;
2512 break;
2513 case SMBHSTCNT_OFF:
2514 pThis->u8SMBusBlkIdx = 0;
2515 *pu32 = pThis->u8SMBusHstCnt;
2516 break;
2517 case SMBHSTCMD_OFF:
2518 *pu32 = pThis->u8SMBusHstCmd;
2519 break;
2520 case SMBHSTADD_OFF:
2521 *pu32 = pThis->u8SMBusHstAdd;
2522 break;
2523 case SMBHSTDAT0_OFF:
2524 *pu32 = pThis->u8SMBusHstDat0;
2525 break;
2526 case SMBHSTDAT1_OFF:
2527 *pu32 = pThis->u8SMBusHstDat1;
2528 break;
2529 case SMBBLKDAT_OFF:
2530 *pu32 = pThis->au8SMBusBlkDat[pThis->u8SMBusBlkIdx];
2531 pThis->u8SMBusBlkIdx++;
2532 pThis->u8SMBusBlkIdx &= sizeof(pThis->au8SMBusBlkDat) - 1;
2533 break;
2534 case SMBSLVCNT_OFF:
2535 *pu32 = pThis->u8SMBusSlvCnt;
2536 break;
2537 case SMBSHDWCMD_OFF:
2538 *pu32 = pThis->u8SMBusShdwCmd;
2539 break;
2540 case SMBSLVEVT_OFF:
2541 *pu32 = pThis->u16SMBusSlvEvt;
2542 break;
2543 case SMBSLVDAT_OFF:
2544 *pu32 = pThis->u16SMBusSlvDat;
2545 break;
2546 default:
2547 /* caught by the sanity check above */
2548 rc = VERR_IOM_IOPORT_UNUSED;
2549 }
2550 DEVACPI_UNLOCK(pDevIns, pThis);
2551
2552 LogFunc(("offPort=%#x u32=%#x cb=%u rc=%Rrc\n", offPort, *pu32, cb, VBOXSTRICTRC_VAL(rc)));
2553 return rc;
2554}
2555
2556/**
2557 * Called by acpiR3Reset and acpiR3Construct to set up the SMBus PCI config space.
2558 *
2559 * @param pDevIns The PDM device instance.
2560 * @param pThis The ACPI shared instance data.
2561 */
2562static void acpiR3SMBusPCIBIOSFake(PPDMDEVINS pDevIns, PACPISTATE pThis)
2563{
2564 PPDMPCIDEV pPciDev = pDevIns->apPciDevs[0];
2565 pPciDev->abConfig[SMBBA ] = pThis->uSMBusIoPortBase | 1; /* SMBBA, SMBus base address, bit 0 marks it as IO range */
2566 pPciDev->abConfig[SMBBA+1] = pThis->uSMBusIoPortBase >> 8;
2567 pPciDev->abConfig[SMBBA+2] = 0x00;
2568 pPciDev->abConfig[SMBBA+3] = 0x00;
2569 pPciDev->abConfig[SMBHSTCFG] = SMBHSTCFG_INTRSEL_IRQ9 << SMBHSTCFG_INTRSEL_SHIFT | SMBHSTCFG_SMB_HST_EN; /* SMBHSTCFG */
2570 pPciDev->abConfig[SMBSLVC] = 0x00; /* SMBSLVC */
2571 pPciDev->abConfig[SMBSHDW1] = 0x00; /* SMBSHDW1 */
2572 pPciDev->abConfig[SMBSHDW2] = 0x00; /* SMBSHDW2 */
2573 pPciDev->abConfig[SMBREV] = 0x00; /* SMBREV */
2574}
2575
2576/**
2577 * Called by acpiR3LoadState, acpiR3Reset and acpiR3Construct to reset the SMBus device register state.
2578 *
2579 * @param pThis The ACPI shared instance data.
2580 */
2581static void acpiR3SMBusResetDevice(PACPISTATE pThis)
2582{
2583 pThis->u8SMBusHstSts = 0x00;
2584 pThis->u8SMBusSlvSts = 0x00;
2585 pThis->u8SMBusHstCnt = 0x00;
2586 pThis->u8SMBusHstCmd = 0x00;
2587 pThis->u8SMBusHstAdd = 0x00;
2588 pThis->u8SMBusHstDat0 = 0x00;
2589 pThis->u8SMBusHstDat1 = 0x00;
2590 pThis->u8SMBusSlvCnt = 0x00;
2591 pThis->u8SMBusShdwCmd = 0x00;
2592 pThis->u16SMBusSlvEvt = 0x0000;
2593 pThis->u16SMBusSlvDat = 0x0000;
2594 memset(pThis->au8SMBusBlkDat, 0x00, sizeof(pThis->au8SMBusBlkDat));
2595 pThis->u8SMBusBlkIdx = 0;
2596}
2597
2598/**
2599 * Called by acpiR3LoadState and acpiR3UpdateSMBusHandlers to map the SMBus ports.
2600 *
2601 * @returns VBox status code.
2602 * @param pDevIns The device instance.
2603 * @param pThis The ACPI shared instance data.
2604 */
2605static int acpiR3MapSMBusIoPorts(PPDMDEVINS pDevIns, PACPISTATE pThis)
2606{
2607 if (pThis->uSMBusIoPortBase != 0)
2608 {
2609 int rc = PDMDevHlpIoPortMap(pDevIns, pThis->hIoPortSMBus, pThis->uSMBusIoPortBase);
2610 AssertRCReturn(rc, rc);
2611 }
2612 return VINF_SUCCESS;
2613}
2614
2615/**
2616 * Called by acpiR3LoadState and acpiR3UpdateSMBusHandlers to unmap the SMBus ports.
2617 *
2618 * @returns VBox status code.
2619 * @param pDevIns The device instance.
2620 * @param pThis The ACPI shared instance data.
2621 */
2622static int acpiR3UnmapSMBusPorts(PPDMDEVINS pDevIns, PACPISTATE pThis)
2623{
2624 if (pThis->uSMBusIoPortBase != 0)
2625 {
2626 int rc = PDMDevHlpIoPortUnmap(pDevIns, pThis->hIoPortSMBus);
2627 AssertRCReturn(rc, rc);
2628 }
2629 return VINF_SUCCESS;
2630}
2631
2632/**
2633 * Called by acpiR3PciConfigWrite and acpiReset to change the location of the
2634 * SMBus ports.
2635 *
2636 * @returns VBox status code.
2637 *
2638 * @param pDevIns The device instance.
2639 * @param pThis The ACPI shared instance data.
2640 * @param NewIoPortBase The new base address of the I/O ports.
2641 */
2642static int acpiR3UpdateSMBusHandlers(PPDMDEVINS pDevIns, PACPISTATE pThis, RTIOPORT NewIoPortBase)
2643{
2644 Log(("acpi: rebasing SMBus 0x%x -> 0x%x\n", pThis->uSMBusIoPortBase, NewIoPortBase));
2645 if (NewIoPortBase != pThis->uSMBusIoPortBase)
2646 {
2647 int rc = acpiR3UnmapSMBusPorts(pDevIns, pThis);
2648 AssertRCReturn(rc, rc);
2649
2650 pThis->uSMBusIoPortBase = NewIoPortBase;
2651
2652 rc = acpiR3MapSMBusIoPorts(pDevIns, pThis);
2653 AssertRCReturn(rc, rc);
2654
2655#if 0 /* is there an FADT table entry for the SMBus base? */
2656 /* We have to update FADT table acccording to the new base */
2657 rc = acpiR3PlantTables(pThis);
2658 AssertRC(rc);
2659 if (RT_FAILURE(rc))
2660 return rc;
2661#endif
2662 }
2663
2664 return VINF_SUCCESS;
2665}
2666
2667
2668/**
2669 * Saved state structure description, version 4.
2670 */
2671static const SSMFIELD g_AcpiSavedStateFields4[] =
2672{
2673 SSMFIELD_ENTRY(ACPISTATE, pm1a_en),
2674 SSMFIELD_ENTRY(ACPISTATE, pm1a_sts),
2675 SSMFIELD_ENTRY(ACPISTATE, pm1a_ctl),
2676 SSMFIELD_ENTRY(ACPISTATE, u64PmTimerInitial),
2677 SSMFIELD_ENTRY(ACPISTATE, gpe0_en),
2678 SSMFIELD_ENTRY(ACPISTATE, gpe0_sts),
2679 SSMFIELD_ENTRY(ACPISTATE, uBatteryIndex),
2680 SSMFIELD_ENTRY(ACPISTATE, uSystemInfoIndex),
2681 SSMFIELD_ENTRY(ACPISTATE, u64RamSize),
2682 SSMFIELD_ENTRY(ACPISTATE, u8IndexShift),
2683 SSMFIELD_ENTRY(ACPISTATE, u8UseIOApic),
2684 SSMFIELD_ENTRY(ACPISTATE, uSleepState),
2685 SSMFIELD_ENTRY_TERM()
2686};
2687
2688/**
2689 * Saved state structure description, version 5.
2690 */
2691static const SSMFIELD g_AcpiSavedStateFields5[] =
2692{
2693 SSMFIELD_ENTRY(ACPISTATE, pm1a_en),
2694 SSMFIELD_ENTRY(ACPISTATE, pm1a_sts),
2695 SSMFIELD_ENTRY(ACPISTATE, pm1a_ctl),
2696 SSMFIELD_ENTRY(ACPISTATE, u64PmTimerInitial),
2697 SSMFIELD_ENTRY(ACPISTATE, gpe0_en),
2698 SSMFIELD_ENTRY(ACPISTATE, gpe0_sts),
2699 SSMFIELD_ENTRY(ACPISTATE, uBatteryIndex),
2700 SSMFIELD_ENTRY(ACPISTATE, uSystemInfoIndex),
2701 SSMFIELD_ENTRY(ACPISTATE, uSleepState),
2702 SSMFIELD_ENTRY(ACPISTATE, u8IndexShift),
2703 SSMFIELD_ENTRY(ACPISTATE, uPmIoPortBase),
2704 SSMFIELD_ENTRY_TERM()
2705};
2706
2707/**
2708 * Saved state structure description, version 6.
2709 */
2710static const SSMFIELD g_AcpiSavedStateFields6[] =
2711{
2712 SSMFIELD_ENTRY(ACPISTATE, pm1a_en),
2713 SSMFIELD_ENTRY(ACPISTATE, pm1a_sts),
2714 SSMFIELD_ENTRY(ACPISTATE, pm1a_ctl),
2715 SSMFIELD_ENTRY(ACPISTATE, u64PmTimerInitial),
2716 SSMFIELD_ENTRY(ACPISTATE, gpe0_en),
2717 SSMFIELD_ENTRY(ACPISTATE, gpe0_sts),
2718 SSMFIELD_ENTRY(ACPISTATE, uBatteryIndex),
2719 SSMFIELD_ENTRY(ACPISTATE, uSystemInfoIndex),
2720 SSMFIELD_ENTRY(ACPISTATE, uSleepState),
2721 SSMFIELD_ENTRY(ACPISTATE, u8IndexShift),
2722 SSMFIELD_ENTRY(ACPISTATE, uPmIoPortBase),
2723 SSMFIELD_ENTRY(ACPISTATE, fSuspendToSavedState),
2724 SSMFIELD_ENTRY_TERM()
2725};
2726
2727/**
2728 * Saved state structure description, version 7.
2729 */
2730static const SSMFIELD g_AcpiSavedStateFields7[] =
2731{
2732 SSMFIELD_ENTRY(ACPISTATE, pm1a_en),
2733 SSMFIELD_ENTRY(ACPISTATE, pm1a_sts),
2734 SSMFIELD_ENTRY(ACPISTATE, pm1a_ctl),
2735 SSMFIELD_ENTRY(ACPISTATE, u64PmTimerInitial),
2736 SSMFIELD_ENTRY(ACPISTATE, uPmTimerVal),
2737 SSMFIELD_ENTRY(ACPISTATE, gpe0_en),
2738 SSMFIELD_ENTRY(ACPISTATE, gpe0_sts),
2739 SSMFIELD_ENTRY(ACPISTATE, uBatteryIndex),
2740 SSMFIELD_ENTRY(ACPISTATE, uSystemInfoIndex),
2741 SSMFIELD_ENTRY(ACPISTATE, uSleepState),
2742 SSMFIELD_ENTRY(ACPISTATE, u8IndexShift),
2743 SSMFIELD_ENTRY(ACPISTATE, uPmIoPortBase),
2744 SSMFIELD_ENTRY(ACPISTATE, fSuspendToSavedState),
2745 SSMFIELD_ENTRY_TERM()
2746};
2747
2748/**
2749 * Saved state structure description, version 8.
2750 */
2751static const SSMFIELD g_AcpiSavedStateFields8[] =
2752{
2753 SSMFIELD_ENTRY(ACPISTATE, pm1a_en),
2754 SSMFIELD_ENTRY(ACPISTATE, pm1a_sts),
2755 SSMFIELD_ENTRY(ACPISTATE, pm1a_ctl),
2756 SSMFIELD_ENTRY(ACPISTATE, u64PmTimerInitial),
2757 SSMFIELD_ENTRY(ACPISTATE, uPmTimerVal),
2758 SSMFIELD_ENTRY(ACPISTATE, gpe0_en),
2759 SSMFIELD_ENTRY(ACPISTATE, gpe0_sts),
2760 SSMFIELD_ENTRY(ACPISTATE, uBatteryIndex),
2761 SSMFIELD_ENTRY(ACPISTATE, uSystemInfoIndex),
2762 SSMFIELD_ENTRY(ACPISTATE, uSleepState),
2763 SSMFIELD_ENTRY(ACPISTATE, u8IndexShift),
2764 SSMFIELD_ENTRY(ACPISTATE, uPmIoPortBase),
2765 SSMFIELD_ENTRY(ACPISTATE, fSuspendToSavedState),
2766 SSMFIELD_ENTRY(ACPISTATE, uSMBusIoPortBase),
2767 SSMFIELD_ENTRY(ACPISTATE, u8SMBusHstSts),
2768 SSMFIELD_ENTRY(ACPISTATE, u8SMBusSlvSts),
2769 SSMFIELD_ENTRY(ACPISTATE, u8SMBusHstCnt),
2770 SSMFIELD_ENTRY(ACPISTATE, u8SMBusHstCmd),
2771 SSMFIELD_ENTRY(ACPISTATE, u8SMBusHstAdd),
2772 SSMFIELD_ENTRY(ACPISTATE, u8SMBusHstDat0),
2773 SSMFIELD_ENTRY(ACPISTATE, u8SMBusHstDat1),
2774 SSMFIELD_ENTRY(ACPISTATE, u8SMBusSlvCnt),
2775 SSMFIELD_ENTRY(ACPISTATE, u8SMBusShdwCmd),
2776 SSMFIELD_ENTRY(ACPISTATE, u16SMBusSlvEvt),
2777 SSMFIELD_ENTRY(ACPISTATE, u16SMBusSlvDat),
2778 SSMFIELD_ENTRY(ACPISTATE, au8SMBusBlkDat),
2779 SSMFIELD_ENTRY(ACPISTATE, u8SMBusBlkIdx),
2780 SSMFIELD_ENTRY_TERM()
2781};
2782
2783/**
2784 * @callback_method_impl{FNSSMDEVSAVEEXEC}
2785 */
2786static DECLCALLBACK(int) acpiR3SaveState(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
2787{
2788 PACPISTATE pThis = PDMDEVINS_2_DATA(pDevIns, PACPISTATE);
2789 PCPDMDEVHLPR3 pHlp = pDevIns->pHlpR3;
2790 return pHlp->pfnSSMPutStruct(pSSM, pThis, &g_AcpiSavedStateFields8[0]);
2791}
2792
2793/**
2794 * @callback_method_impl{FNSSMDEVLOADEXEC}
2795 */
2796static DECLCALLBACK(int) acpiR3LoadState(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
2797{
2798 PACPISTATE pThis = PDMDEVINS_2_DATA(pDevIns, PACPISTATE);
2799 PACPISTATER3 pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PACPISTATER3);
2800 PCPDMDEVHLPR3 pHlp = pDevIns->pHlpR3;
2801 Assert(uPass == SSM_PASS_FINAL); NOREF(uPass);
2802
2803 /*
2804 * Unmap PM I/O ports, will remap it with the actual base after state
2805 * successfully loaded.
2806 */
2807 int rc = acpiR3UnmapPmIoPorts(pDevIns, pThis);
2808 AssertRCReturn(rc, rc);
2809
2810 /*
2811 * Unregister SMBus handlers, will register with actual base after state
2812 * successfully loaded.
2813 */
2814 rc = acpiR3UnmapSMBusPorts(pDevIns, pThis);
2815 AssertRCReturn(rc, rc);
2816 acpiR3SMBusResetDevice(pThis);
2817
2818 switch (uVersion)
2819 {
2820 case 4:
2821 rc = pHlp->pfnSSMGetStruct(pSSM, pThis, &g_AcpiSavedStateFields4[0]);
2822 break;
2823 case 5:
2824 rc = pHlp->pfnSSMGetStruct(pSSM, pThis, &g_AcpiSavedStateFields5[0]);
2825 break;
2826 case 6:
2827 rc = pHlp->pfnSSMGetStruct(pSSM, pThis, &g_AcpiSavedStateFields6[0]);
2828 break;
2829 case 7:
2830 rc = pHlp->pfnSSMGetStruct(pSSM, pThis, &g_AcpiSavedStateFields7[0]);
2831 break;
2832 case 8:
2833 rc = pHlp->pfnSSMGetStruct(pSSM, pThis, &g_AcpiSavedStateFields8[0]);
2834 break;
2835 default:
2836 rc = VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
2837 break;
2838 }
2839 if (RT_SUCCESS(rc))
2840 {
2841 AssertLogRelMsgReturn(pThis->u8SMBusBlkIdx < RT_ELEMENTS(pThis->au8SMBusBlkDat),
2842 ("%#x\n", pThis->u8SMBusBlkIdx), VERR_SSM_LOAD_CONFIG_MISMATCH);
2843 rc = acpiR3MapPmIoPorts(pDevIns, pThis);
2844 AssertRCReturn(rc, rc);
2845 rc = acpiR3MapSMBusIoPorts(pDevIns, pThis);
2846 AssertRCReturn(rc, rc);
2847 rc = acpiR3FetchBatteryStatus(pThis, pThisCC);
2848 AssertRCReturn(rc, rc);
2849 rc = acpiR3FetchBatteryInfo(pThis);
2850 AssertRCReturn(rc, rc);
2851
2852 PDMDevHlpTimerLockClock(pDevIns, pThis->hPmTimer, VERR_IGNORED);
2853 DEVACPI_LOCK_R3(pDevIns, pThis);
2854 uint64_t u64Now = PDMDevHlpTimerGet(pDevIns, pThis->hPmTimer);
2855 /* The interrupt may be incorrectly re-generated if the state is restored from versions < 7. */
2856 acpiPmTimerUpdate(pDevIns, pThis, u64Now);
2857 acpiR3PmTimerReset(pDevIns, pThis, u64Now);
2858 DEVACPI_UNLOCK(pDevIns, pThis);
2859 PDMDevHlpTimerUnlockClock(pDevIns, pThis->hPmTimer);
2860 }
2861 return rc;
2862}
2863
2864/**
2865 * @interface_method_impl{PDMIBASE,pfnQueryInterface}
2866 */
2867static DECLCALLBACK(void *) acpiR3QueryInterface(PPDMIBASE pInterface, const char *pszIID)
2868{
2869 PACPISTATER3 pThisCC = RT_FROM_MEMBER(pInterface, ACPISTATER3, IBase);
2870 PDMIBASE_RETURN_INTERFACE(pszIID, PDMIBASE, &pThisCC->IBase);
2871 PDMIBASE_RETURN_INTERFACE(pszIID, PDMIACPIPORT, &pThisCC->IACPIPort);
2872 PDMIBASE_RETURN_INTERFACE(pszIID, PDMIEVENTBUTTONPORT, &pThisCC->IButtonEventPort);
2873 return NULL;
2874}
2875
2876/**
2877 * Calculate the check sum for some ACPI data before planting it.
2878 *
2879 * All the bytes must add up to 0.
2880 *
2881 * @returns check sum.
2882 * @param pvSrc What to check sum.
2883 * @param cbData The amount of data to checksum.
2884 */
2885static uint8_t acpiR3Checksum(const void * const pvSrc, size_t cbData)
2886{
2887 uint8_t const *pbSrc = (uint8_t const *)pvSrc;
2888 uint8_t uSum = 0;
2889 for (size_t i = 0; i < cbData; ++i)
2890 uSum += pbSrc[i];
2891 return -uSum;
2892}
2893
2894/**
2895 * Prepare a ACPI table header.
2896 */
2897static void acpiR3PrepareHeader(PACPISTATE pThis, ACPITBLHEADER *header,
2898 const char au8Signature[4],
2899 uint32_t u32Length, uint8_t u8Revision)
2900{
2901 memcpy(header->au8Signature, au8Signature, 4);
2902 header->u32Length = RT_H2LE_U32(u32Length);
2903 header->u8Revision = u8Revision;
2904 memcpy(header->au8OemId, pThis->au8OemId, 6);
2905 memcpy(header->au8OemTabId, "VBOX", 4);
2906 memcpy(header->au8OemTabId+4, au8Signature, 4);
2907 header->u32OemRevision = RT_H2LE_U32(1);
2908 memcpy(header->au8CreatorId, pThis->au8CreatorId, 4);
2909 header->u32CreatorRev = pThis->u32CreatorRev;
2910}
2911
2912/**
2913 * Initialize a generic address structure (ACPIGENADDR).
2914 */
2915static void acpiR3WriteGenericAddr(ACPIGENADDR *g, uint8_t u8AddressSpaceId,
2916 uint8_t u8RegisterBitWidth, uint8_t u8RegisterBitOffset,
2917 uint8_t u8AccessSize, uint64_t u64Address)
2918{
2919 g->u8AddressSpaceId = u8AddressSpaceId;
2920 g->u8RegisterBitWidth = u8RegisterBitWidth;
2921 g->u8RegisterBitOffset = u8RegisterBitOffset;
2922 g->u8AccessSize = u8AccessSize;
2923 g->u64Address = RT_H2LE_U64(u64Address);
2924}
2925
2926/**
2927 * Wrapper around PDMDevHlpPhysWrite used when planting ACPI tables.
2928 */
2929DECLINLINE(void) acpiR3PhysCopy(PPDMDEVINS pDevIns, RTGCPHYS32 GCPhys32Dst, const void *pvSrc, size_t cbToCopy)
2930{
2931 PDMDevHlpPhysWrite(pDevIns, GCPhys32Dst, pvSrc, cbToCopy);
2932}
2933
2934/**
2935 * Plant the Differentiated System Description Table (DSDT).
2936 */
2937static void acpiR3SetupDsdt(PPDMDEVINS pDevIns, RTGCPHYS32 GCPhys32, void const *pvSrc, size_t cbDsdt)
2938{
2939 acpiR3PhysCopy(pDevIns, GCPhys32, pvSrc, cbDsdt);
2940}
2941
2942/**
2943 * Plant the Secondary System Description Table (SSDT).
2944 */
2945static void acpiR3SetupSsdt(PPDMDEVINS pDevIns, RTGCPHYS32 addr, void const *pvSrc, size_t uSsdtLen)
2946{
2947 acpiR3PhysCopy(pDevIns, addr, pvSrc, uSsdtLen);
2948}
2949
2950#ifdef VBOX_WITH_TPM
2951/**
2952 * Plant the Secondary System Description Table (SSDT).
2953 */
2954static void acpiR3SetupTpmSsdt(PPDMDEVINS pDevIns, RTGCPHYS32 addr, void const *pvSrc, size_t uSsdtLen)
2955{
2956 acpiR3PhysCopy(pDevIns, addr, pvSrc, uSsdtLen);
2957}
2958#endif
2959
2960/**
2961 * Plant the Firmware ACPI Control Structure (FACS).
2962 */
2963static void acpiR3SetupFacs(PPDMDEVINS pDevIns, RTGCPHYS32 addr)
2964{
2965 ACPITBLFACS facs;
2966
2967 memset(&facs, 0, sizeof(facs));
2968 memcpy(facs.au8Signature, "FACS", 4);
2969 facs.u32Length = RT_H2LE_U32(sizeof(ACPITBLFACS));
2970 facs.u32HWSignature = RT_H2LE_U32(0);
2971 facs.u32FWVector = RT_H2LE_U32(0);
2972 facs.u32GlobalLock = RT_H2LE_U32(0);
2973 facs.u32Flags = RT_H2LE_U32(0);
2974 facs.u64X_FWVector = RT_H2LE_U64(0);
2975 facs.u8Version = 1;
2976
2977 acpiR3PhysCopy(pDevIns, addr, (const uint8_t *)&facs, sizeof(facs));
2978}
2979
2980/**
2981 * Plant the Fixed ACPI Description Table (FADT aka FACP).
2982 */
2983static void acpiR3SetupFadt(PPDMDEVINS pDevIns, PACPISTATE pThis, RTGCPHYS32 GCPhysAcpi1, RTGCPHYS32 GCPhysAcpi2,
2984 RTGCPHYS32 GCPhysFacs, RTGCPHYS GCPhysDsdt)
2985{
2986 ACPITBLFADT fadt;
2987
2988 /* First the ACPI version 2+ version of the structure. */
2989 memset(&fadt, 0, sizeof(fadt));
2990 acpiR3PrepareHeader(pThis, &fadt.header, "FACP", sizeof(fadt), 4);
2991 fadt.u32FACS = RT_H2LE_U32(GCPhysFacs);
2992 fadt.u32DSDT = RT_H2LE_U32(GCPhysDsdt);
2993 fadt.u8IntModel = 0; /* dropped from the ACPI 2.0 spec. */
2994 fadt.u8PreferredPMProfile = 0; /* unspecified */
2995 fadt.u16SCIInt = RT_H2LE_U16(SCI_INT);
2996 fadt.u32SMICmd = RT_H2LE_U32(SMI_CMD);
2997 fadt.u8AcpiEnable = ACPI_ENABLE;
2998 fadt.u8AcpiDisable = ACPI_DISABLE;
2999 fadt.u8S4BIOSReq = 0;
3000 fadt.u8PStateCnt = 0;
3001 fadt.u32PM1aEVTBLK = RT_H2LE_U32(acpiR3CalcPmPort(pThis, PM1a_EVT_OFFSET));
3002 fadt.u32PM1bEVTBLK = RT_H2LE_U32(acpiR3CalcPmPort(pThis, PM1b_EVT_OFFSET));
3003 fadt.u32PM1aCTLBLK = RT_H2LE_U32(acpiR3CalcPmPort(pThis, PM1a_CTL_OFFSET));
3004 fadt.u32PM1bCTLBLK = RT_H2LE_U32(acpiR3CalcPmPort(pThis, PM1b_CTL_OFFSET));
3005 fadt.u32PM2CTLBLK = RT_H2LE_U32(acpiR3CalcPmPort(pThis, PM2_CTL_OFFSET));
3006 fadt.u32PMTMRBLK = RT_H2LE_U32(acpiR3CalcPmPort(pThis, PM_TMR_OFFSET));
3007 fadt.u32GPE0BLK = RT_H2LE_U32(acpiR3CalcPmPort(pThis, GPE0_OFFSET));
3008 fadt.u32GPE1BLK = RT_H2LE_U32(acpiR3CalcPmPort(pThis, GPE1_OFFSET));
3009 fadt.u8PM1EVTLEN = 4;
3010 fadt.u8PM1CTLLEN = 2;
3011 fadt.u8PM2CTLLEN = 0;
3012 fadt.u8PMTMLEN = 4;
3013 fadt.u8GPE0BLKLEN = GPE0_BLK_LEN;
3014 fadt.u8GPE1BLKLEN = GPE1_BLK_LEN;
3015 fadt.u8GPE1BASE = GPE1_BASE;
3016 fadt.u8CSTCNT = 0;
3017 fadt.u16PLVL2LAT = RT_H2LE_U16(P_LVL2_LAT);
3018 fadt.u16PLVL3LAT = RT_H2LE_U16(P_LVL3_LAT);
3019 fadt.u16FlushSize = RT_H2LE_U16(FLUSH_SIZE);
3020 fadt.u16FlushStride = RT_H2LE_U16(FLUSH_STRIDE);
3021 fadt.u8DutyOffset = 0;
3022 fadt.u8DutyWidth = 0;
3023 fadt.u8DayAlarm = 0;
3024 fadt.u8MonAlarm = 0;
3025 fadt.u8Century = 0;
3026 fadt.u16IAPCBOOTARCH = RT_H2LE_U16(IAPC_BOOT_ARCH_LEGACY_DEV | IAPC_BOOT_ARCH_8042);
3027 /** @note WBINVD is required for ACPI versions newer than 1.0 */
3028 fadt.u32Flags = RT_H2LE_U32( FADT_FL_WBINVD
3029 | FADT_FL_FIX_RTC
3030 | FADT_FL_TMR_VAL_EXT
3031 | FADT_FL_RESET_REG_SUP);
3032
3033 /* We have to force physical APIC mode or Linux can't use more than 8 CPUs */
3034 if (pThis->fCpuHotPlug)
3035 fadt.u32Flags |= RT_H2LE_U32(FADT_FL_FORCE_APIC_PHYS_DEST_MODE);
3036
3037 acpiR3WriteGenericAddr(&fadt.ResetReg, 1, 8, 0, 1, ACPI_RESET_BLK);
3038 fadt.u8ResetVal = ACPI_RESET_REG_VAL;
3039 fadt.u64XFACS = RT_H2LE_U64((uint64_t)GCPhysFacs);
3040 fadt.u64XDSDT = RT_H2LE_U64((uint64_t)GCPhysDsdt);
3041 acpiR3WriteGenericAddr(&fadt.X_PM1aEVTBLK, 1, 32, 0, 2, acpiR3CalcPmPort(pThis, PM1a_EVT_OFFSET));
3042 acpiR3WriteGenericAddr(&fadt.X_PM1bEVTBLK, 0, 0, 0, 0, acpiR3CalcPmPort(pThis, PM1b_EVT_OFFSET));
3043 acpiR3WriteGenericAddr(&fadt.X_PM1aCTLBLK, 1, 16, 0, 2, acpiR3CalcPmPort(pThis, PM1a_CTL_OFFSET));
3044 acpiR3WriteGenericAddr(&fadt.X_PM1bCTLBLK, 0, 0, 0, 0, acpiR3CalcPmPort(pThis, PM1b_CTL_OFFSET));
3045 acpiR3WriteGenericAddr(&fadt.X_PM2CTLBLK, 0, 0, 0, 0, acpiR3CalcPmPort(pThis, PM2_CTL_OFFSET));
3046 acpiR3WriteGenericAddr(&fadt.X_PMTMRBLK, 1, 32, 0, 3, acpiR3CalcPmPort(pThis, PM_TMR_OFFSET));
3047 acpiR3WriteGenericAddr(&fadt.X_GPE0BLK, 1, 16, 0, 1, acpiR3CalcPmPort(pThis, GPE0_OFFSET));
3048 acpiR3WriteGenericAddr(&fadt.X_GPE1BLK, 0, 0, 0, 0, acpiR3CalcPmPort(pThis, GPE1_OFFSET));
3049 fadt.header.u8Checksum = acpiR3Checksum(&fadt, sizeof(fadt));
3050 acpiR3PhysCopy(pDevIns, GCPhysAcpi2, &fadt, sizeof(fadt));
3051
3052 /* Now the ACPI 1.0 version. */
3053 fadt.header.u32Length = ACPITBLFADT_VERSION1_SIZE;
3054 fadt.u8IntModel = INT_MODEL_DUAL_PIC;
3055 fadt.header.u8Checksum = 0; /* Must be zeroed before recalculating checksum! */
3056 fadt.header.u8Checksum = acpiR3Checksum(&fadt, ACPITBLFADT_VERSION1_SIZE);
3057 acpiR3PhysCopy(pDevIns, GCPhysAcpi1, &fadt, ACPITBLFADT_VERSION1_SIZE);
3058}
3059
3060/**
3061 * Plant the root System Description Table.
3062 *
3063 * The RSDT and XSDT tables are basically identical. The only difference is 32
3064 * vs 64 bits addresses for description headers. RSDT is for ACPI 1.0. XSDT for
3065 * ACPI 2.0 and up.
3066 */
3067static int acpiR3SetupRsdt(PPDMDEVINS pDevIns, PACPISTATE pThis, RTGCPHYS32 addr, unsigned int nb_entries, uint32_t *addrs)
3068{
3069 ACPITBLRSDT *rsdt;
3070 const size_t size = sizeof(ACPITBLHEADER) + nb_entries * sizeof(rsdt->u32Entry[0]);
3071
3072 rsdt = (ACPITBLRSDT*)RTMemAllocZ(size);
3073 if (!rsdt)
3074 return PDMDEV_SET_ERROR(pDevIns, VERR_NO_TMP_MEMORY, N_("Cannot allocate RSDT"));
3075
3076 acpiR3PrepareHeader(pThis, &rsdt->header, "RSDT", (uint32_t)size, 1);
3077 for (unsigned int i = 0; i < nb_entries; ++i)
3078 {
3079 rsdt->u32Entry[i] = RT_H2LE_U32(addrs[i]);
3080 Log(("Setup RSDT: [%d] = %x\n", i, rsdt->u32Entry[i]));
3081 }
3082 rsdt->header.u8Checksum = acpiR3Checksum(rsdt, size);
3083 acpiR3PhysCopy(pDevIns, addr, rsdt, size);
3084 RTMemFree(rsdt);
3085 return VINF_SUCCESS;
3086}
3087
3088/**
3089 * Plant the Extended System Description Table.
3090 */
3091static int acpiR3SetupXsdt(PPDMDEVINS pDevIns, PACPISTATE pThis, RTGCPHYS32 addr, unsigned int nb_entries, uint32_t *addrs)
3092{
3093 ACPITBLXSDT *xsdt;
3094 const size_t cbXsdt = sizeof(ACPITBLHEADER) + nb_entries * sizeof(xsdt->u64Entry[0]);
3095 xsdt = (ACPITBLXSDT *)RTMemAllocZ(cbXsdt);
3096 if (!xsdt)
3097 return VERR_NO_TMP_MEMORY;
3098
3099 acpiR3PrepareHeader(pThis, &xsdt->header, "XSDT", (uint32_t)cbXsdt, 1 /* according to ACPI 3.0 specs */);
3100
3101 if (pThis->cCustTbls > 0)
3102 memcpy(xsdt->header.au8OemTabId, pThis->au8OemTabId, 8);
3103
3104 for (unsigned int i = 0; i < nb_entries; ++i)
3105 {
3106 xsdt->u64Entry[i] = RT_H2LE_U64((uint64_t)addrs[i]);
3107 Log(("Setup XSDT: [%d] = %RX64\n", i, xsdt->u64Entry[i]));
3108 }
3109 xsdt->header.u8Checksum = acpiR3Checksum(xsdt, cbXsdt);
3110 acpiR3PhysCopy(pDevIns, addr, xsdt, cbXsdt);
3111
3112 RTMemFree(xsdt);
3113 return VINF_SUCCESS;
3114}
3115
3116/**
3117 * Plant the Root System Description Pointer (RSDP).
3118 */
3119static void acpiR3SetupRsdp(PACPISTATE pThis, ACPITBLRSDP *rsdp, RTGCPHYS32 GCPhysRsdt, RTGCPHYS GCPhysXsdt)
3120{
3121 memset(rsdp, 0, sizeof(*rsdp));
3122
3123 /* ACPI 1.0 part (RSDT) */
3124 memcpy(rsdp->au8Signature, "RSD PTR ", 8);
3125 memcpy(rsdp->au8OemId, pThis->au8OemId, 6);
3126 rsdp->u8Revision = ACPI_REVISION;
3127 rsdp->u32RSDT = RT_H2LE_U32(GCPhysRsdt);
3128 rsdp->u8Checksum = acpiR3Checksum(rsdp, RT_OFFSETOF(ACPITBLRSDP, u32Length));
3129
3130 /* ACPI 2.0 part (XSDT) */
3131 rsdp->u32Length = RT_H2LE_U32(sizeof(ACPITBLRSDP));
3132 rsdp->u64XSDT = RT_H2LE_U64(GCPhysXsdt);
3133 rsdp->u8ExtChecksum = acpiR3Checksum(rsdp, sizeof(ACPITBLRSDP));
3134}
3135
3136/**
3137 * Multiple APIC Description Table.
3138 *
3139 * This structure looks somewhat convoluted due layout of MADT table in MP case.
3140 * There extpected to be multiple LAPIC records for each CPU, thus we cannot
3141 * use regular C structure and proxy to raw memory instead.
3142 */
3143class AcpiTableMadt
3144{
3145 /**
3146 * All actual data stored in dynamically allocated memory pointed by this field.
3147 */
3148 uint8_t *m_pbData;
3149 /**
3150 * Number of CPU entries in this MADT.
3151 */
3152 uint32_t m_cCpus;
3153
3154 /**
3155 * Number of interrupt overrides.
3156 */
3157 uint32_t m_cIsos;
3158
3159public:
3160 /**
3161 * Address of ACPI header
3162 */
3163 inline ACPITBLHEADER *header_addr(void) const
3164 {
3165 return (ACPITBLHEADER *)m_pbData;
3166 }
3167
3168 /**
3169 * Address of local APIC for each CPU. Note that different CPUs address different LAPICs,
3170 * although address is the same for all of them.
3171 */
3172 inline uint32_t *u32LAPIC_addr(void) const
3173 {
3174 return (uint32_t *)(header_addr() + 1);
3175 }
3176
3177 /**
3178 * Address of APIC flags
3179 */
3180 inline uint32_t *u32Flags_addr(void) const
3181 {
3182 return (uint32_t *)(u32LAPIC_addr() + 1);
3183 }
3184
3185 /**
3186 * Address of ISO description
3187 */
3188 inline ACPITBLISO *ISO_addr(void) const
3189 {
3190 return (ACPITBLISO *)(u32Flags_addr() + 1);
3191 }
3192
3193 /**
3194 * Address of per-CPU LAPIC descriptions
3195 */
3196 inline ACPITBLLAPIC *LApics_addr(void) const
3197 {
3198 return (ACPITBLLAPIC *)(ISO_addr() + m_cIsos);
3199 }
3200
3201 /**
3202 * Address of IO APIC description
3203 */
3204 inline ACPITBLIOAPIC *IOApic_addr(void) const
3205 {
3206 return (ACPITBLIOAPIC *)(LApics_addr() + m_cCpus);
3207 }
3208
3209 /**
3210 * Size of MADT.
3211 * Note that this function assumes IOApic to be the last field in structure.
3212 */
3213 inline uint32_t size(void) const
3214 {
3215 return (uint8_t *)(IOApic_addr() + 1) - (uint8_t *)header_addr();
3216 }
3217
3218 /**
3219 * Raw data of MADT.
3220 */
3221 inline const uint8_t *data(void) const
3222 {
3223 return m_pbData;
3224 }
3225
3226 /**
3227 * Size of MADT for given ACPI config, useful to compute layout.
3228 */
3229 static uint32_t sizeFor(PACPISTATE pThis, uint32_t cIsos)
3230 {
3231 return AcpiTableMadt(pThis->cCpus, cIsos).size();
3232 }
3233
3234 /*
3235 * Constructor, only works in Ring 3, doesn't look like a big deal.
3236 */
3237 AcpiTableMadt(uint32_t cCpus, uint32_t cIsos)
3238 {
3239 m_cCpus = cCpus;
3240 m_cIsos = cIsos;
3241 m_pbData = NULL; /* size() uses this and gcc will complain if not initialized. */
3242 uint32_t cb = size();
3243 m_pbData = (uint8_t *)RTMemAllocZ(cb);
3244 }
3245
3246 ~AcpiTableMadt()
3247 {
3248 RTMemFree(m_pbData);
3249 }
3250};
3251
3252
3253/**
3254 * Plant the Multiple APIC Description Table (MADT).
3255 *
3256 * @note APIC without IO-APIC hangs Windows Vista therefore we setup both.
3257 *
3258 * @todo All hardcoded, should set this up based on the actual VM config!!!!!
3259 */
3260static void acpiR3SetupMadt(PPDMDEVINS pDevIns, PACPISTATE pThis, RTGCPHYS32 addr)
3261{
3262 uint16_t cpus = pThis->cCpus;
3263 AcpiTableMadt madt(cpus, NUMBER_OF_IRQ_SOURCE_OVERRIDES);
3264
3265 acpiR3PrepareHeader(pThis, madt.header_addr(), "APIC", madt.size(), 2);
3266
3267 *madt.u32LAPIC_addr() = RT_H2LE_U32(0xfee00000);
3268 *madt.u32Flags_addr() = RT_H2LE_U32(PCAT_COMPAT);
3269
3270 /* LAPICs records */
3271 ACPITBLLAPIC* lapic = madt.LApics_addr();
3272 for (uint16_t i = 0; i < cpus; i++)
3273 {
3274 lapic->u8Type = 0;
3275 lapic->u8Length = sizeof(ACPITBLLAPIC);
3276 lapic->u8ProcId = i;
3277 /** Must match numbering convention in MPTABLES */
3278 lapic->u8ApicId = i;
3279 lapic->u32Flags = VMCPUSET_IS_PRESENT(&pThis->CpuSetAttached, i) ? RT_H2LE_U32(LAPIC_ENABLED) : 0;
3280 lapic++;
3281 }
3282
3283 /* IO-APIC record */
3284 ACPITBLIOAPIC* ioapic = madt.IOApic_addr();
3285 ioapic->u8Type = 1;
3286 ioapic->u8Length = sizeof(ACPITBLIOAPIC);
3287 /** Must match MP tables ID */
3288 ioapic->u8IOApicId = cpus;
3289 ioapic->u8Reserved = 0;
3290 ioapic->u32Address = RT_H2LE_U32(0xfec00000);
3291 ioapic->u32GSIB = RT_H2LE_U32(0);
3292
3293 /* Interrupt Source Overrides */
3294 /* Flags:
3295 bits[3:2]:
3296 00 conforms to the bus
3297 01 edge-triggered
3298 10 reserved
3299 11 level-triggered
3300 bits[1:0]
3301 00 conforms to the bus
3302 01 active-high
3303 10 reserved
3304 11 active-low */
3305 /* If changing, also update PDMIsaSetIrq() and MPS */
3306 ACPITBLISO* isos = madt.ISO_addr();
3307 /* Timer interrupt rule IRQ0 to GSI2 */
3308 isos[0].u8Type = 2;
3309 isos[0].u8Length = sizeof(ACPITBLISO);
3310 isos[0].u8Bus = 0; /* Must be 0 */
3311 isos[0].u8Source = 0; /* IRQ0 */
3312 isos[0].u32GSI = 2; /* connected to pin 2 */
3313 isos[0].u16Flags = 0; /* conform to the bus */
3314
3315 /* ACPI interrupt rule - IRQ9 to GSI9 */
3316 isos[1].u8Type = 2;
3317 isos[1].u8Length = sizeof(ACPITBLISO);
3318 isos[1].u8Bus = 0; /* Must be 0 */
3319 isos[1].u8Source = 9; /* IRQ9 */
3320 isos[1].u32GSI = 9; /* connected to pin 9 */
3321 isos[1].u16Flags = 0xf; /* active low, level triggered */
3322 Assert(NUMBER_OF_IRQ_SOURCE_OVERRIDES == 2);
3323
3324 madt.header_addr()->u8Checksum = acpiR3Checksum(madt.data(), madt.size());
3325 acpiR3PhysCopy(pDevIns, addr, madt.data(), madt.size());
3326}
3327
3328/**
3329 * Plant the High Performance Event Timer (HPET) descriptor.
3330 */
3331static void acpiR3SetupHpet(PPDMDEVINS pDevIns, PACPISTATE pThis, RTGCPHYS32 addr)
3332{
3333 ACPITBLHPET hpet;
3334
3335 memset(&hpet, 0, sizeof(hpet));
3336
3337 acpiR3PrepareHeader(pThis, &hpet.aHeader, "HPET", sizeof(hpet), 1);
3338 /* Keep base address consistent with appropriate DSDT entry (vbox.dsl) */
3339 acpiR3WriteGenericAddr(&hpet.HpetAddr,
3340 0 /* Memory address space */,
3341 64 /* Register bit width */,
3342 0 /* Bit offset */,
3343 0, /* Register access size, is it correct? */
3344 0xfed00000 /* Address */);
3345
3346 hpet.u32Id = 0x8086a201; /* must match what HPET ID returns, is it correct ? */
3347 hpet.u32Number = 0;
3348 hpet.u32MinTick = 4096;
3349 hpet.u8Attributes = 0;
3350
3351 hpet.aHeader.u8Checksum = acpiR3Checksum(&hpet, sizeof(hpet));
3352
3353 acpiR3PhysCopy(pDevIns, addr, (const uint8_t *)&hpet, sizeof(hpet));
3354}
3355
3356
3357#ifdef VBOX_WITH_IOMMU_AMD
3358/**
3359 * Plant the AMD IOMMU descriptor.
3360 */
3361static void acpiR3SetupIommuAmd(PPDMDEVINS pDevIns, PACPISTATE pThis, RTGCPHYS32 addr)
3362{
3363 ACPITBLIOMMU Ivrs;
3364 RT_ZERO(Ivrs);
3365
3366 uint16_t const uIommuBus = 0;
3367 uint16_t const uIommuDev = RT_HI_U16(pThis->u32IommuPciAddress);
3368 uint16_t const uIommuFn = RT_LO_U16(pThis->u32IommuPciAddress);
3369
3370 /* IVRS header. */
3371 acpiR3PrepareHeader(pThis, &Ivrs.Hdr.header, "IVRS", sizeof(Ivrs), ACPI_IVRS_FMT_REV_FIXED);
3372 /* NOTE! The values here must match what we expose via MMIO/PCI config. space in the IOMMU device code. */
3373 Ivrs.Hdr.u32IvInfo = RT_BF_MAKE(ACPI_IVINFO_BF_EFR_SUP, 1)
3374 | RT_BF_MAKE(ACPI_IVINFO_BF_DMA_REMAP_SUP, 0) /* Pre-boot DMA remap support not supported. */
3375 | RT_BF_MAKE(ACPI_IVINFO_BF_GVA_SIZE, 2) /* Guest Virt. Addr size (2=48 bits) */
3376 | RT_BF_MAKE(ACPI_IVINFO_BF_PA_SIZE, 48) /* Physical Addr size (48 bits) */
3377 | RT_BF_MAKE(ACPI_IVINFO_BF_VA_SIZE, 64) /* Virt. Addr size (64 bits) */
3378 | RT_BF_MAKE(ACPI_IVINFO_BF_HT_ATS_RESV, 0); /* ATS response range reserved (only applicable for HT) */
3379
3380 /* IVHD type 10 definition block. */
3381 Ivrs.IvhdType10.u8Type = 0x10;
3382 Ivrs.IvhdType10.u16Length = sizeof(Ivrs.IvhdType10)
3383 + sizeof(Ivrs.IvhdType10Start)
3384 + sizeof(Ivrs.IvhdType10End)
3385 + sizeof(Ivrs.IvhdType10Rsvd0)
3386 + sizeof(Ivrs.IvhdType10Rsvd1)
3387 + sizeof(Ivrs.IvhdType10IoApic)
3388 + sizeof(Ivrs.IvhdType10Hpet);
3389 Ivrs.IvhdType10.u16DeviceId = PCIBDF_MAKE(uIommuBus, VBOX_PCI_DEVFN_MAKE(uIommuDev, uIommuFn));
3390 Ivrs.IvhdType10.u16CapOffset = IOMMU_PCI_OFF_CAP_HDR;
3391 Ivrs.IvhdType10.u64BaseAddress = IOMMU_MMIO_BASE_ADDR;
3392 Ivrs.IvhdType10.u16PciSegmentGroup = 0;
3393 /* NOTE! Subfields in the following fields must match any corresponding field in PCI/MMIO registers of the IOMMU device. */
3394 Ivrs.IvhdType10.u8Flags = ACPI_IVHD_10H_F_COHERENT; /* Remote IOTLB etc. not supported. */
3395 Ivrs.IvhdType10.u16IommuInfo = RT_BF_MAKE(ACPI_IOMMU_INFO_BF_MSI_NUM, 0)
3396 | RT_BF_MAKE(ACPI_IOMMU_INFO_BF_UNIT_ID, 0);
3397 Ivrs.IvhdType10.u32Features = RT_BF_MAKE(ACPI_IOMMU_FEAT_BF_XT_SUP, 0)
3398 | RT_BF_MAKE(ACPI_IOMMU_FEAT_BF_NX_SUP, 0)
3399 | RT_BF_MAKE(ACPI_IOMMU_FEAT_BF_GT_SUP, 0)
3400 | RT_BF_MAKE(ACPI_IOMMU_FEAT_BF_GLX_SUP, 0)
3401 | RT_BF_MAKE(ACPI_IOMMU_FEAT_BF_IA_SUP, 1)
3402 | RT_BF_MAKE(ACPI_IOMMU_FEAT_BF_GA_SUP, 0)
3403 | RT_BF_MAKE(ACPI_IOMMU_FEAT_BF_HE_SUP, 1)
3404 | RT_BF_MAKE(ACPI_IOMMU_FEAT_BF_PAS_MAX, 0)
3405 | RT_BF_MAKE(ACPI_IOMMU_FEAT_BF_PN_COUNTERS, 0)
3406 | RT_BF_MAKE(ACPI_IOMMU_FEAT_BF_PN_BANKS, 0)
3407 | RT_BF_MAKE(ACPI_IOMMU_FEAT_BF_PN_COUNTERS, 0)
3408 | RT_BF_MAKE(ACPI_IOMMU_FEAT_BF_MSI_NUM_PPR, 0)
3409 | RT_BF_MAKE(ACPI_IOMMU_FEAT_BF_GATS, 0)
3410 | RT_BF_MAKE(ACPI_IOMMU_FEAT_BF_HATS, IOMMU_MAX_HOST_PT_LEVEL & 3);
3411 /* Start range from BDF (00:01:00). */
3412 Ivrs.IvhdType10Start.u8DevEntryType = ACPI_IVHD_DEVENTRY_TYPE_START_RANGE;
3413 Ivrs.IvhdType10Start.u16DevId = PCIBDF_MAKE(0, VBOX_PCI_DEVFN_MAKE(1, 0));
3414 Ivrs.IvhdType10Start.u8DteSetting = 0;
3415 /* End range at BDF (ff:1f:7). */
3416 Ivrs.IvhdType10End.u8DevEntryType = ACPI_IVHD_DEVENTRY_TYPE_END_RANGE;
3417 Ivrs.IvhdType10End.u16DevId = PCIBDF_MAKE(0xff, VBOX_PCI_DEVFN_MAKE(0x1f, 7U));
3418 Ivrs.IvhdType10End.u8DteSetting = 0;
3419
3420 /* Southbridge I/O APIC special device entry. */
3421 Ivrs.IvhdType10IoApic.u8DevEntryType = 0x48;
3422 Ivrs.IvhdType10IoApic.u.special.u16Rsvd0 = 0;
3423 Ivrs.IvhdType10IoApic.u.special.u8DteSetting = RT_BF_MAKE(ACPI_IVHD_DTE_INIT_PASS, 1)
3424 | RT_BF_MAKE(ACPI_IVHD_DTE_EXTINT_PASS, 1)
3425 | RT_BF_MAKE(ACPI_IVHD_DTE_NMI_PASS, 1)
3426 | RT_BF_MAKE(ACPI_IVHD_DTE_LINT0_PASS, 1)
3427 | RT_BF_MAKE(ACPI_IVHD_DTE_LINT1_PASS, 1);
3428 Ivrs.IvhdType10IoApic.u.special.u8Handle = pThis->cCpus; /* The I/O APIC ID, see u8IOApicId in acpiR3SetupMadt(). */
3429 Ivrs.IvhdType10IoApic.u.special.u16DevIdB = VBOX_PCI_BDF_SB_IOAPIC;
3430 Ivrs.IvhdType10IoApic.u.special.u8Variety = ACPI_IVHD_VARIETY_IOAPIC;
3431
3432 /* HPET special device entry. */
3433 Ivrs.IvhdType10Hpet.u8DevEntryType = 0x48;
3434 Ivrs.IvhdType10Hpet.u.special.u16Rsvd0 = 0;
3435 Ivrs.IvhdType10Hpet.u.special.u8DteSetting = 0;
3436 Ivrs.IvhdType10Hpet.u.special.u8Handle = 0; /* HPET number. ASSUMING it's identical to u32Number in acpiR3SetupHpet(). */
3437 Ivrs.IvhdType10Hpet.u.special.u16DevIdB = VBOX_PCI_BDF_SB_IOAPIC; /* HPET goes through the I/O APIC. */
3438 Ivrs.IvhdType10Hpet.u.special.u8Variety = ACPI_IVHD_VARIETY_HPET;
3439
3440 /* IVHD type 11 definition block. */
3441 Ivrs.IvhdType11.u8Type = 0x11;
3442 Ivrs.IvhdType11.u16Length = sizeof(Ivrs.IvhdType11)
3443 + sizeof(Ivrs.IvhdType11Start)
3444 + sizeof(Ivrs.IvhdType11End)
3445 + sizeof(Ivrs.IvhdType11Rsvd0)
3446 + sizeof(Ivrs.IvhdType11Rsvd1)
3447 + sizeof(Ivrs.IvhdType11IoApic)
3448 + sizeof(Ivrs.IvhdType11Hpet);
3449 Ivrs.IvhdType11.u16DeviceId = Ivrs.IvhdType10.u16DeviceId;
3450 Ivrs.IvhdType11.u16CapOffset = Ivrs.IvhdType10.u16CapOffset;
3451 Ivrs.IvhdType11.u64BaseAddress = Ivrs.IvhdType10.u64BaseAddress;
3452 Ivrs.IvhdType11.u16PciSegmentGroup = Ivrs.IvhdType10.u16PciSegmentGroup;
3453 Ivrs.IvhdType11.u8Flags = ACPI_IVHD_11H_F_COHERENT;
3454 Ivrs.IvhdType11.u16IommuInfo = Ivrs.IvhdType10.u16IommuInfo;
3455 Ivrs.IvhdType11.u32IommuAttr = RT_BF_MAKE(ACPI_IOMMU_ATTR_BF_PN_COUNTERS, 0)
3456 | RT_BF_MAKE(ACPI_IOMMU_ATTR_BF_PN_BANKS, 0)
3457 | RT_BF_MAKE(ACPI_IOMMU_ATTR_BF_MSI_NUM_PPR, 0);
3458 /* NOTE! The feature bits below must match the IOMMU device code (MMIO/PCI access of the EFR register). */
3459 Ivrs.IvhdType11.u64EfrRegister = RT_BF_MAKE(IOMMU_EXT_FEAT_BF_PREF_SUP, 0)
3460 | RT_BF_MAKE(IOMMU_EXT_FEAT_BF_PPR_SUP, 0)
3461 | RT_BF_MAKE(IOMMU_EXT_FEAT_BF_X2APIC_SUP, 0)
3462 | RT_BF_MAKE(IOMMU_EXT_FEAT_BF_NO_EXEC_SUP, 0)
3463 | RT_BF_MAKE(IOMMU_EXT_FEAT_BF_GT_SUP, 0)
3464 | RT_BF_MAKE(IOMMU_EXT_FEAT_BF_IA_SUP, 1)
3465 | RT_BF_MAKE(IOMMU_EXT_FEAT_BF_GA_SUP, 0)
3466 | RT_BF_MAKE(IOMMU_EXT_FEAT_BF_HE_SUP, 1)
3467 | RT_BF_MAKE(IOMMU_EXT_FEAT_BF_PC_SUP, 0)
3468 | RT_BF_MAKE(IOMMU_EXT_FEAT_BF_HATS, IOMMU_MAX_HOST_PT_LEVEL & 3)
3469 | RT_BF_MAKE(IOMMU_EXT_FEAT_BF_GATS, 0)
3470 | RT_BF_MAKE(IOMMU_EXT_FEAT_BF_GLX_SUP, 0)
3471 | RT_BF_MAKE(IOMMU_EXT_FEAT_BF_SMI_FLT_SUP, 0)
3472 | RT_BF_MAKE(IOMMU_EXT_FEAT_BF_SMI_FLT_REG_CNT, 0)
3473 | RT_BF_MAKE(IOMMU_EXT_FEAT_BF_GAM_SUP, 0)
3474 | RT_BF_MAKE(IOMMU_EXT_FEAT_BF_DUAL_PPR_LOG_SUP, 0)
3475 | RT_BF_MAKE(IOMMU_EXT_FEAT_BF_DUAL_EVT_LOG_SUP, 0)
3476 | RT_BF_MAKE(IOMMU_EXT_FEAT_BF_PASID_MAX, 0)
3477 | RT_BF_MAKE(IOMMU_EXT_FEAT_BF_US_SUP, 0)
3478 | RT_BF_MAKE(IOMMU_EXT_FEAT_BF_DEV_TBL_SEG_SUP, IOMMU_MAX_DEV_TAB_SEGMENTS)
3479 | RT_BF_MAKE(IOMMU_EXT_FEAT_BF_PPR_OVERFLOW_EARLY, 0)
3480 | RT_BF_MAKE(IOMMU_EXT_FEAT_BF_PPR_AUTO_RES_SUP, 0)
3481 | RT_BF_MAKE(IOMMU_EXT_FEAT_BF_MARC_SUP, 0)
3482 | RT_BF_MAKE(IOMMU_EXT_FEAT_BF_BLKSTOP_MARK_SUP, 0)
3483 | RT_BF_MAKE(IOMMU_EXT_FEAT_BF_PERF_OPT_SUP, 0)
3484 | RT_BF_MAKE(IOMMU_EXT_FEAT_BF_MSI_CAP_MMIO_SUP, 1)
3485 | RT_BF_MAKE(IOMMU_EXT_FEAT_BF_GST_IO_PROT_SUP, 0)
3486 | RT_BF_MAKE(IOMMU_EXT_FEAT_BF_HST_ACCESS_SUP, 0)
3487 | RT_BF_MAKE(IOMMU_EXT_FEAT_BF_ENHANCED_PPR_SUP, 0)
3488 | RT_BF_MAKE(IOMMU_EXT_FEAT_BF_ATTR_FW_SUP, 0)
3489 | RT_BF_MAKE(IOMMU_EXT_FEAT_BF_HST_DIRTY_SUP, 0)
3490 | RT_BF_MAKE(IOMMU_EXT_FEAT_BF_INV_IOTLB_TYPE_SUP, 0)
3491 | RT_BF_MAKE(IOMMU_EXT_FEAT_BF_GA_UPDATE_DIS_SUP, 0)
3492 | RT_BF_MAKE(IOMMU_EXT_FEAT_BF_FORCE_PHYS_DST_SUP, 0);
3493
3494 /* The IVHD type 11 entries can be copied from their type 10 counterparts. */
3495 Ivrs.IvhdType11Start = Ivrs.IvhdType10Start;
3496 Ivrs.IvhdType11End = Ivrs.IvhdType10End;
3497 Ivrs.IvhdType11Rsvd0 = Ivrs.IvhdType10Rsvd0;
3498 Ivrs.IvhdType11Rsvd1 = Ivrs.IvhdType10Rsvd1;
3499 Ivrs.IvhdType11IoApic = Ivrs.IvhdType10IoApic;
3500 Ivrs.IvhdType11Hpet = Ivrs.IvhdType10Hpet;
3501
3502 /* Finally, compute checksum. */
3503 Ivrs.Hdr.header.u8Checksum = acpiR3Checksum(&Ivrs, sizeof(Ivrs));
3504
3505 /* Plant the ACPI table. */
3506 acpiR3PhysCopy(pDevIns, addr, (const uint8_t *)&Ivrs, sizeof(Ivrs));
3507}
3508#endif /* VBOX_WITH_IOMMU_AMD */
3509
3510
3511#ifdef VBOX_WITH_IOMMU_INTEL
3512/**
3513 * Plant the Intel IOMMU (VT-d) descriptor.
3514 */
3515static void acpiR3SetupIommuIntel(PPDMDEVINS pDevIns, PACPISTATE pThis, RTGCPHYS32 addr)
3516{
3517 ACPITBLVTD VtdTable;
3518 RT_ZERO(VtdTable);
3519
3520 /* VT-d Table. */
3521 acpiR3PrepareHeader(pThis, &VtdTable.Dmar.Hdr, "DMAR", sizeof(ACPITBLVTD), ACPI_DMAR_REVISION);
3522
3523 /* DMAR. */
3524 uint8_t cPhysAddrBits;
3525 uint8_t cLinearAddrBits;
3526 PDMDevHlpCpuGetGuestAddrWidths(pDevIns, &cPhysAddrBits, &cLinearAddrBits);
3527 Assert(cPhysAddrBits > 0); NOREF(cLinearAddrBits);
3528 VtdTable.Dmar.uHostAddrWidth = cPhysAddrBits - 1;
3529 VtdTable.Dmar.fFlags = DMAR_ACPI_DMAR_FLAGS;
3530
3531 /* DRHD. */
3532 VtdTable.Drhd.cbLength = sizeof(ACPIDRHD);
3533 VtdTable.Drhd.fFlags = ACPI_DRHD_F_INCLUDE_PCI_ALL;
3534 VtdTable.Drhd.uRegBaseAddr = DMAR_MMIO_BASE_PHYSADDR;
3535
3536 /* Device Scopes: I/O APIC. */
3537 if (pThis->u8UseIOApic)
3538 {
3539 uint8_t const uIoApicBus = 0;
3540 uint8_t const uIoApicDev = RT_HI_U16(pThis->u32SbIoApicPciAddress);
3541 uint8_t const uIoApicFn = RT_LO_U16(pThis->u32SbIoApicPciAddress);
3542
3543 VtdTable.DevScopeIoApic.uType = ACPIDMARDEVSCOPE_TYPE_IOAPIC;
3544 VtdTable.DevScopeIoApic.cbLength = sizeof(ACPIDMARDEVSCOPE);
3545 VtdTable.DevScopeIoApic.idEnum = pThis->cCpus; /* The I/O APIC ID, see u8IOApicId in acpiR3SetupMadt(). */
3546 VtdTable.DevScopeIoApic.uStartBusNum = uIoApicBus;
3547 VtdTable.DevScopeIoApic.Path.uDevice = uIoApicDev;
3548 VtdTable.DevScopeIoApic.Path.uFunction = uIoApicFn;
3549
3550 VtdTable.Drhd.cbLength += sizeof(VtdTable.DevScopeIoApic);
3551 }
3552
3553 /* Finally, compute checksum. */
3554 VtdTable.Dmar.Hdr.u8Checksum = acpiR3Checksum(&VtdTable, sizeof(VtdTable));
3555
3556 /* Plant the ACPI table. */
3557 acpiR3PhysCopy(pDevIns, addr, (const uint8_t *)&VtdTable, sizeof(VtdTable));
3558}
3559#endif /* VBOX_WITH_IOMMU_INTEL */
3560
3561
3562#ifdef VBOX_WITH_TPM
3563/**
3564 * Plant the TPM 2.0 ACPI descriptor.
3565 */
3566static void acpiR3SetupTpm(PPDMDEVINS pDevIns, PACPISTATE pThis, RTGCPHYS32 addr)
3567{
3568 if (pThis->enmTpmMode == ACPITPMMODE_TIS_1_2)
3569 {
3570 ACPITBLTCPA TcpaTbl;
3571 RT_ZERO(TcpaTbl);
3572
3573 acpiR3PrepareHeader(pThis, &TcpaTbl.Hdr, "TCPA", sizeof(TcpaTbl), ACPI_TCPA_REVISION);
3574
3575 TcpaTbl.u16PlatCls = ACPI_TCPA_PLAT_CLS_CLIENT;
3576 TcpaTbl.u32Laml = ACPI_TCPA_LAML_SZ;
3577 TcpaTbl.u64Lasa = addr + sizeof(TcpaTbl);
3578
3579 /* Finally, compute checksum. */
3580 TcpaTbl.Hdr.u8Checksum = acpiR3Checksum(&TcpaTbl, sizeof(TcpaTbl));
3581
3582 /* Plant the ACPI table. */
3583 acpiR3PhysCopy(pDevIns, addr, (const uint8_t *)&TcpaTbl, sizeof(TcpaTbl));
3584 }
3585 else
3586 {
3587 ACPITBLTPM20 Tpm2Tbl;
3588 RT_ZERO(Tpm2Tbl);
3589
3590 acpiR3PrepareHeader(pThis, &Tpm2Tbl.Hdr, "TPM2", sizeof(ACPITBLTPM20), ACPI_TPM20_REVISION);
3591
3592 switch (pThis->enmTpmMode)
3593 {
3594 case ACPITPMMODE_CRB_2_0:
3595 Tpm2Tbl.u32StartMethod = ACPITBL_TPM20_START_METHOD_CRB;
3596 Tpm2Tbl.u64BaseAddrCrbOrFifo = pThis->GCPhysTpmMmio;
3597 break;
3598 case ACPITPMMODE_FIFO_2_0:
3599 Tpm2Tbl.u32StartMethod = ACPITBL_TPM20_START_METHOD_TIS12;
3600 break;
3601 case ACPITPMMODE_TIS_1_2: /* Handled above. */
3602 case ACPITPMMODE_DISABLED: /* Should never be called with the TPM disabled. */
3603 default:
3604 AssertFailed();
3605 }
3606
3607 Tpm2Tbl.u16PlatCls = ACPITBL_TPM20_PLAT_CLS_CLIENT;
3608
3609 /* Finally, compute checksum. */
3610 Tpm2Tbl.Hdr.u8Checksum = acpiR3Checksum(&Tpm2Tbl, sizeof(Tpm2Tbl));
3611
3612 /* Plant the ACPI table. */
3613 acpiR3PhysCopy(pDevIns, addr, (const uint8_t *)&Tpm2Tbl, sizeof(Tpm2Tbl));
3614 }
3615}
3616#endif
3617
3618
3619/**
3620 * Used by acpiR3PlantTables to plant a MMCONFIG PCI config space access (MCFG)
3621 * descriptor.
3622 *
3623 * @param pDevIns The device instance.
3624 * @param pThis The ACPI shared instance data.
3625 * @param GCPhysDst Where to plant it.
3626 */
3627static void acpiR3SetupMcfg(PPDMDEVINS pDevIns, PACPISTATE pThis, RTGCPHYS32 GCPhysDst)
3628{
3629 struct
3630 {
3631 ACPITBLMCFG hdr;
3632 ACPITBLMCFGENTRY entry;
3633 } tbl;
3634 uint8_t u8StartBus = 0;
3635 uint8_t u8EndBus = (pThis->u64PciConfigMMioLength >> 20) - 1;
3636
3637 RT_ZERO(tbl);
3638
3639 acpiR3PrepareHeader(pThis, &tbl.hdr.aHeader, "MCFG", sizeof(tbl), 1);
3640 tbl.entry.u64BaseAddress = pThis->u64PciConfigMMioAddress;
3641 tbl.entry.u8StartBus = u8StartBus;
3642 tbl.entry.u8EndBus = u8EndBus;
3643 // u16PciSegmentGroup must match _SEG in ACPI table
3644
3645 tbl.hdr.aHeader.u8Checksum = acpiR3Checksum(&tbl, sizeof(tbl));
3646
3647 acpiR3PhysCopy(pDevIns, GCPhysDst, (const uint8_t *)&tbl, sizeof(tbl));
3648}
3649
3650/**
3651 * Used by acpiR3PlantTables and acpiConstruct.
3652 *
3653 * @returns Guest memory address.
3654 */
3655static uint32_t apicR3FindRsdpSpace(void)
3656{
3657 return 0xe0000;
3658}
3659
3660/**
3661 * Called by acpiR3Construct to read and allocate a custom ACPI table
3662 *
3663 * @param pDevIns The device instance.
3664 * @param ppu8CustBin Address to receive the address of the table
3665 * @param pcbCustBin Address to receive the size of the the table.
3666 * @param pszCustBinFile
3667 * @param cbBufAvail Maximum space in bytes available for the custom
3668 * table (including header).
3669 */
3670static int acpiR3ReadCustomTable(PPDMDEVINS pDevIns, uint8_t **ppu8CustBin, uint64_t *pcbCustBin,
3671 char *pszCustBinFile, uint32_t cbBufAvail)
3672{
3673 RTFILE FileCUSTBin;
3674 int rc = RTFileOpen(&FileCUSTBin, pszCustBinFile,
3675 RTFILE_O_READ | RTFILE_O_OPEN | RTFILE_O_DENY_WRITE);
3676 if (RT_SUCCESS(rc))
3677 {
3678 rc = RTFileQuerySize(FileCUSTBin, pcbCustBin);
3679 if (RT_SUCCESS(rc))
3680 {
3681 /* The following checks should be in sync the AssertReleaseMsg's below. */
3682 if ( *pcbCustBin > cbBufAvail
3683 || *pcbCustBin < sizeof(ACPITBLHEADER))
3684 rc = VERR_TOO_MUCH_DATA;
3685
3686 /*
3687 * Allocate buffer for the custom table binary data.
3688 */
3689 *ppu8CustBin = (uint8_t *)PDMDevHlpMMHeapAlloc(pDevIns, *pcbCustBin);
3690 if (*ppu8CustBin)
3691 {
3692 rc = RTFileRead(FileCUSTBin, *ppu8CustBin, *pcbCustBin, NULL);
3693 if (RT_FAILURE(rc))
3694 {
3695 AssertMsgFailed(("RTFileRead(,,%d,NULL) -> %Rrc\n", *pcbCustBin, rc));
3696 PDMDevHlpMMHeapFree(pDevIns, *ppu8CustBin);
3697 *ppu8CustBin = NULL;
3698 }
3699 }
3700 else
3701 {
3702 rc = VERR_NO_MEMORY;
3703 }
3704 RTFileClose(FileCUSTBin);
3705 }
3706 }
3707 return rc;
3708}
3709
3710/**
3711 * Create the ACPI tables in guest memory.
3712 */
3713static int acpiR3PlantTables(PPDMDEVINS pDevIns, PACPISTATE pThis, PACPISTATER3 pThisCC)
3714{
3715 int rc;
3716 RTGCPHYS32 GCPhysCur, GCPhysRsdt, GCPhysXsdt, GCPhysFadtAcpi1, GCPhysFadtAcpi2, GCPhysFacs, GCPhysDsdt;
3717 RTGCPHYS32 GCPhysHpet = 0;
3718#if defined(VBOX_WITH_IOMMU_AMD) || defined(VBOX_WITH_IOMMU_INTEL)
3719 RTGCPHYS32 GCPhysIommu = 0;
3720#endif
3721#ifdef VBOX_WITH_TPM
3722 RTGCPHYS32 GCPhysTpm = 0;
3723 RTGCPHYS32 GCPhysSsdtTpm = 0;
3724#endif
3725 RTGCPHYS32 GCPhysApic = 0;
3726 RTGCPHYS32 GCPhysSsdt = 0;
3727 RTGCPHYS32 GCPhysMcfg = 0;
3728 RTGCPHYS32 aGCPhysCust[MAX_CUST_TABLES] = {0};
3729 uint32_t addend = 0;
3730#if defined(VBOX_WITH_IOMMU_AMD) || defined(VBOX_WITH_IOMMU_INTEL)
3731# ifdef VBOX_WITH_TPM
3732 RTGCPHYS32 aGCPhysRsdt[10 + MAX_CUST_TABLES];
3733 RTGCPHYS32 aGCPhysXsdt[10 + MAX_CUST_TABLES];
3734# else
3735 RTGCPHYS32 aGCPhysRsdt[8 + MAX_CUST_TABLES];
3736 RTGCPHYS32 aGCPhysXsdt[8 + MAX_CUST_TABLES];
3737# endif
3738#else
3739# ifdef VBOX_WITH_TPM
3740 RTGCPHYS32 aGCPhysRsdt[9 + MAX_CUST_TABLES];
3741 RTGCPHYS32 aGCPhysXsdt[9 + MAX_CUST_TABLES];
3742# else
3743 RTGCPHYS32 aGCPhysRsdt[7 + MAX_CUST_TABLES];
3744 RTGCPHYS32 aGCPhysXsdt[7 + MAX_CUST_TABLES];
3745# endif
3746#endif
3747 uint32_t cAddr;
3748 uint32_t iMadt = 0;
3749 uint32_t iHpet = 0;
3750#if defined(VBOX_WITH_IOMMU_AMD) || defined(VBOX_WITH_IOMMU_INTEL)
3751 uint32_t iIommu = 0;
3752#endif
3753#ifdef VBOX_WITH_TPM
3754 uint32_t iTpm = 0;
3755 uint32_t iSsdtTpm = 0;
3756#endif
3757 uint32_t iSsdt = 0;
3758 uint32_t iMcfg = 0;
3759 uint32_t iCust = 0;
3760 size_t cbRsdt = sizeof(ACPITBLHEADER);
3761 size_t cbXsdt = sizeof(ACPITBLHEADER);
3762
3763 cAddr = 1; /* FADT */
3764 if (pThis->u8UseIOApic)
3765 iMadt = cAddr++; /* MADT */
3766
3767 if (pThis->fUseHpet)
3768 iHpet = cAddr++; /* HPET */
3769
3770#ifdef VBOX_WITH_IOMMU_AMD
3771 if (pThis->fUseIommuAmd)
3772 iIommu = cAddr++; /* IOMMU (AMD) */
3773#endif
3774
3775#ifdef VBOX_WITH_IOMMU_INTEL
3776 if (pThis->fUseIommuIntel)
3777 iIommu = cAddr++; /* IOMMU (Intel) */
3778#endif
3779
3780#ifdef VBOX_WITH_TPM
3781 if (pThis->enmTpmMode != ACPITPMMODE_DISABLED)
3782 {
3783 iTpm = cAddr++; /* TPM device */
3784 iSsdtTpm = cAddr++;
3785 }
3786#endif
3787
3788 if (pThis->fUseMcfg)
3789 iMcfg = cAddr++; /* MCFG */
3790
3791 if (pThis->cCustTbls > 0)
3792 {
3793 iCust = cAddr; /* CUST */
3794 cAddr += pThis->cCustTbls;
3795 }
3796
3797 iSsdt = cAddr++; /* SSDT */
3798
3799 Assert(cAddr < RT_ELEMENTS(aGCPhysRsdt));
3800 Assert(cAddr < RT_ELEMENTS(aGCPhysXsdt));
3801
3802 cbRsdt += cAddr * sizeof(uint32_t); /* each entry: 32 bits phys. address. */
3803 cbXsdt += cAddr * sizeof(uint64_t); /* each entry: 64 bits phys. address. */
3804
3805 /*
3806 * Calculate the sizes for the low region and for the 64-bit prefetchable memory.
3807 * The latter starts never below 4G.
3808 */
3809 uint32_t cbBelow4GB = PDMDevHlpMMPhysGetRamSizeBelow4GB(pDevIns);
3810 uint64_t const cbAbove4GB = PDMDevHlpMMPhysGetRamSizeAbove4GB(pDevIns);
3811
3812 pThis->u64RamSize = PDMDevHlpMMPhysGetRamSize(pDevIns);
3813 if (pThis->fPciPref64Enabled)
3814 {
3815 uint64_t const u64PciPref64Min = _4G + cbAbove4GB;
3816 if (pThis->u64PciPref64Max > u64PciPref64Min)
3817 {
3818 /* Activate MEM4. See also DevPciIch9.cpp / ich9pciFakePCIBIOS() / uPciBiosMmio64 */
3819 pThis->u64PciPref64Min = u64PciPref64Min;
3820 LogRel(("ACPI: Enabling 64-bit prefetch root bus resource %#018RX64..%#018RX64\n",
3821 u64PciPref64Min, pThis->u64PciPref64Max-1));
3822 }
3823 else
3824 LogRel(("ACPI: NOT enabling 64-bit prefetch root bus resource (min/%#018RX64 >= max/%#018RX64)\n",
3825 u64PciPref64Min, pThis->u64PciPref64Max-1));
3826 }
3827 if (cbBelow4GB > UINT32_C(0xfe000000)) /* See MEM3. */
3828 {
3829 /* Note: This is also enforced by DevPcBios.cpp. */
3830 LogRel(("ACPI: Clipping cbRamLow=%#RX64 down to 0xfe000000.\n", cbBelow4GB));
3831 cbBelow4GB = UINT32_C(0xfe000000);
3832 }
3833 pThis->cbRamLow = cbBelow4GB;
3834
3835 GCPhysCur = 0;
3836 GCPhysRsdt = GCPhysCur;
3837
3838 GCPhysCur = RT_ALIGN_32(GCPhysCur + cbRsdt, 16);
3839 GCPhysXsdt = GCPhysCur;
3840
3841 GCPhysCur = RT_ALIGN_32(GCPhysCur + cbXsdt, 16);
3842 GCPhysFadtAcpi1 = GCPhysCur;
3843
3844 GCPhysCur = RT_ALIGN_32(GCPhysCur + ACPITBLFADT_VERSION1_SIZE, 16);
3845 GCPhysFadtAcpi2 = GCPhysCur;
3846
3847 GCPhysCur = RT_ALIGN_32(GCPhysCur + sizeof(ACPITBLFADT), 64);
3848 GCPhysFacs = GCPhysCur;
3849
3850 GCPhysCur = RT_ALIGN_32(GCPhysCur + sizeof(ACPITBLFACS), 16);
3851 if (pThis->u8UseIOApic)
3852 {
3853 GCPhysApic = GCPhysCur;
3854 GCPhysCur = RT_ALIGN_32(GCPhysCur + AcpiTableMadt::sizeFor(pThis, NUMBER_OF_IRQ_SOURCE_OVERRIDES), 16);
3855 }
3856 if (pThis->fUseHpet)
3857 {
3858 GCPhysHpet = GCPhysCur;
3859 GCPhysCur = RT_ALIGN_32(GCPhysCur + sizeof(ACPITBLHPET), 16);
3860 }
3861#ifdef VBOX_WITH_IOMMU_AMD
3862 if (pThis->fUseIommuAmd)
3863 {
3864 GCPhysIommu = GCPhysCur;
3865 GCPhysCur = RT_ALIGN_32(GCPhysCur + sizeof(ACPITBLIOMMU), 16);
3866 }
3867#endif
3868#ifdef VBOX_WITH_IOMMU_INTEL
3869 if (pThis->fUseIommuIntel)
3870 {
3871 GCPhysIommu = GCPhysCur;
3872 GCPhysCur = RT_ALIGN_32(GCPhysCur + sizeof(ACPITBLVTD), 16);
3873 }
3874#endif
3875#ifdef VBOX_WITH_TPM
3876 void *pvSsdtTpmCode = NULL;
3877 size_t cbSsdtTpm = 0;
3878
3879 if (pThis->enmTpmMode != ACPITPMMODE_DISABLED)
3880 {
3881 GCPhysTpm = GCPhysCur;
3882
3883 if (pThis->enmTpmMode == ACPITPMMODE_TIS_1_2)
3884 GCPhysCur = RT_ALIGN_32(GCPhysCur + sizeof(ACPITBLTCPA) + ACPI_TCPA_LAML_SZ, 16);
3885 else
3886 GCPhysCur = RT_ALIGN_32(GCPhysCur + sizeof(ACPITBLTPM20), 16);
3887
3888 rc = acpiPrepareTpmSsdt(pDevIns, &pvSsdtTpmCode, &cbSsdtTpm);
3889 if (RT_FAILURE(rc))
3890 return rc;
3891
3892 GCPhysSsdtTpm = GCPhysCur;
3893 GCPhysCur = RT_ALIGN_32(GCPhysCur + cbSsdtTpm, 16);
3894 }
3895#endif
3896
3897 if (pThis->fUseMcfg)
3898 {
3899 GCPhysMcfg = GCPhysCur;
3900 /* Assume one entry */
3901 GCPhysCur = RT_ALIGN_32(GCPhysCur + sizeof(ACPITBLMCFG) + sizeof(ACPITBLMCFGENTRY), 16);
3902 }
3903
3904 for (uint8_t i = 0; i < pThis->cCustTbls; i++)
3905 {
3906 aGCPhysCust[i] = GCPhysCur;
3907 GCPhysCur = RT_ALIGN_32(GCPhysCur + pThisCC->acbCustBin[i], 16);
3908 }
3909
3910 void *pvSsdtCode = NULL;
3911 size_t cbSsdt = 0;
3912 rc = acpiPrepareSsdt(pDevIns, &pvSsdtCode, &cbSsdt);
3913 if (RT_FAILURE(rc))
3914 return rc;
3915
3916 GCPhysSsdt = GCPhysCur;
3917 GCPhysCur = RT_ALIGN_32(GCPhysCur + cbSsdt, 16);
3918
3919 GCPhysDsdt = GCPhysCur;
3920
3921 void *pvDsdtCode = NULL;
3922 size_t cbDsdt = 0;
3923 rc = acpiPrepareDsdt(pDevIns, &pvDsdtCode, &cbDsdt);
3924 if (RT_FAILURE(rc))
3925 return rc;
3926
3927 GCPhysCur = RT_ALIGN_32(GCPhysCur + cbDsdt, 16);
3928
3929 if (GCPhysCur > 0x10000)
3930 return PDMDEV_SET_ERROR(pDevIns, VERR_TOO_MUCH_DATA,
3931 N_("Error: ACPI tables bigger than 64KB"));
3932
3933 Log(("RSDP 0x%08X\n", apicR3FindRsdpSpace()));
3934 addend = pThis->cbRamLow - 0x10000;
3935 Log(("RSDT 0x%08X XSDT 0x%08X\n", GCPhysRsdt + addend, GCPhysXsdt + addend));
3936 Log(("FACS 0x%08X FADT (1.0) 0x%08X, FADT (2+) 0x%08X\n", GCPhysFacs + addend, GCPhysFadtAcpi1 + addend, GCPhysFadtAcpi2 + addend));
3937 Log(("DSDT 0x%08X", GCPhysDsdt + addend));
3938 if (pThis->u8UseIOApic)
3939 Log((" MADT 0x%08X", GCPhysApic + addend));
3940 if (pThis->fUseHpet)
3941 Log((" HPET 0x%08X", GCPhysHpet + addend));
3942 if (pThis->fUseMcfg)
3943 Log((" MCFG 0x%08X", GCPhysMcfg + addend));
3944 for (uint8_t i = 0; i < pThis->cCustTbls; i++)
3945 Log((" CUST(%d) 0x%08X", i, aGCPhysCust[i] + addend));
3946 Log((" SSDT 0x%08X", GCPhysSsdt + addend));
3947 Log(("\n"));
3948
3949 acpiR3SetupRsdp(pThis, (ACPITBLRSDP *)pThis->au8RSDPPage, GCPhysRsdt + addend, GCPhysXsdt + addend);
3950 acpiR3SetupDsdt(pDevIns, GCPhysDsdt + addend, pvDsdtCode, cbDsdt);
3951 acpiCleanupDsdt(pDevIns, pvDsdtCode);
3952 acpiR3SetupFacs(pDevIns, GCPhysFacs + addend);
3953 acpiR3SetupFadt(pDevIns, pThis, GCPhysFadtAcpi1 + addend, GCPhysFadtAcpi2 + addend, GCPhysFacs + addend, GCPhysDsdt + addend);
3954
3955 aGCPhysRsdt[0] = GCPhysFadtAcpi1 + addend;
3956 aGCPhysXsdt[0] = GCPhysFadtAcpi2 + addend;
3957 if (pThis->u8UseIOApic)
3958 {
3959 acpiR3SetupMadt(pDevIns, pThis, GCPhysApic + addend);
3960 aGCPhysRsdt[iMadt] = GCPhysApic + addend;
3961 aGCPhysXsdt[iMadt] = GCPhysApic + addend;
3962 }
3963 if (pThis->fUseHpet)
3964 {
3965 acpiR3SetupHpet(pDevIns, pThis, GCPhysHpet + addend);
3966 aGCPhysRsdt[iHpet] = GCPhysHpet + addend;
3967 aGCPhysXsdt[iHpet] = GCPhysHpet + addend;
3968 }
3969#ifdef VBOX_WITH_IOMMU_AMD
3970 if (pThis->fUseIommuAmd)
3971 {
3972 acpiR3SetupIommuAmd(pDevIns, pThis, GCPhysIommu + addend);
3973 aGCPhysRsdt[iIommu] = GCPhysIommu + addend;
3974 aGCPhysXsdt[iIommu] = GCPhysIommu + addend;
3975 }
3976#endif
3977#ifdef VBOX_WITH_IOMMU_INTEL
3978 if (pThis->fUseIommuIntel)
3979 {
3980 acpiR3SetupIommuIntel(pDevIns, pThis, GCPhysIommu + addend);
3981 aGCPhysRsdt[iIommu] = GCPhysIommu + addend;
3982 aGCPhysXsdt[iIommu] = GCPhysIommu + addend;
3983 }
3984#endif
3985#ifdef VBOX_WITH_TPM
3986 if (pThis->enmTpmMode != ACPITPMMODE_DISABLED)
3987 {
3988 acpiR3SetupTpm(pDevIns, pThis, GCPhysTpm + addend);
3989 aGCPhysRsdt[iTpm] = GCPhysTpm + addend;
3990 aGCPhysXsdt[iTpm] = GCPhysTpm + addend;
3991
3992 acpiR3SetupTpmSsdt(pDevIns, GCPhysSsdtTpm + addend, pvSsdtTpmCode, cbSsdtTpm);
3993 acpiCleanupTpmSsdt(pDevIns, pvSsdtTpmCode);
3994 aGCPhysRsdt[iSsdtTpm] = GCPhysSsdtTpm + addend;
3995 aGCPhysXsdt[iSsdtTpm] = GCPhysSsdtTpm + addend;
3996 }
3997#endif
3998
3999 if (pThis->fUseMcfg)
4000 {
4001 acpiR3SetupMcfg(pDevIns, pThis, GCPhysMcfg + addend);
4002 aGCPhysRsdt[iMcfg] = GCPhysMcfg + addend;
4003 aGCPhysXsdt[iMcfg] = GCPhysMcfg + addend;
4004 }
4005 for (uint8_t i = 0; i < pThis->cCustTbls; i++)
4006 {
4007 AssertBreak(i < MAX_CUST_TABLES);
4008 acpiR3PhysCopy(pDevIns, aGCPhysCust[i] + addend, pThisCC->apu8CustBin[i], pThisCC->acbCustBin[i]);
4009 aGCPhysRsdt[iCust + i] = aGCPhysCust[i] + addend;
4010 aGCPhysXsdt[iCust + i] = aGCPhysCust[i] + addend;
4011 uint8_t* pSig = pThisCC->apu8CustBin[i];
4012 LogRel(("ACPI: Planted custom table '%c%c%c%c' at 0x%08X\n",
4013 pSig[0], pSig[1], pSig[2], pSig[3], aGCPhysCust[i] + addend));
4014 }
4015
4016 acpiR3SetupSsdt(pDevIns, GCPhysSsdt + addend, pvSsdtCode, cbSsdt);
4017 acpiCleanupSsdt(pDevIns, pvSsdtCode);
4018 aGCPhysRsdt[iSsdt] = GCPhysSsdt + addend;
4019 aGCPhysXsdt[iSsdt] = GCPhysSsdt + addend;
4020
4021 rc = acpiR3SetupRsdt(pDevIns, pThis, GCPhysRsdt + addend, cAddr, aGCPhysRsdt);
4022 if (RT_FAILURE(rc))
4023 return rc;
4024 return acpiR3SetupXsdt(pDevIns, pThis, GCPhysXsdt + addend, cAddr, aGCPhysXsdt);
4025}
4026
4027/**
4028 * @callback_method_impl{FNPCICONFIGREAD}
4029 */
4030static DECLCALLBACK(VBOXSTRICTRC) acpiR3PciConfigRead(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev,
4031 uint32_t uAddress, unsigned cb, uint32_t *pu32Value)
4032{
4033 VBOXSTRICTRC rcStrict = PDMDevHlpPCIConfigRead(pDevIns, pPciDev, uAddress, cb, pu32Value);
4034 Log2(("acpi: PCI config read: %#x (%d) -> %#x %Rrc\n", uAddress, cb, *pu32Value, VBOXSTRICTRC_VAL(rcStrict)));
4035 return rcStrict;
4036}
4037
4038/**
4039 * @callback_method_impl{FNPCICONFIGWRITE}
4040 */
4041static DECLCALLBACK(VBOXSTRICTRC) acpiR3PciConfigWrite(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev,
4042 uint32_t uAddress, unsigned cb, uint32_t u32Value)
4043{
4044 PACPISTATE pThis = PDMDEVINS_2_DATA(pDevIns, PACPISTATE);
4045 PACPISTATER3 pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PACPISTATER3);
4046
4047 Log2(("acpi: PCI config write: 0x%x -> 0x%x (%d)\n", u32Value, uAddress, cb));
4048 DEVACPI_LOCK_R3(pDevIns, pThis);
4049
4050 if (uAddress == VBOX_PCI_INTERRUPT_LINE)
4051 {
4052 Log(("acpi: ignore interrupt line settings: %d, we'll use hardcoded value %d\n", u32Value, SCI_INT));
4053 u32Value = SCI_INT;
4054 }
4055
4056 VBOXSTRICTRC rcStrict = PDMDevHlpPCIConfigWrite(pDevIns, pPciDev, uAddress, cb, u32Value);
4057
4058 /* Assume that the base address is only changed when the corresponding
4059 * hardware functionality is disabled. The IO region is mapped when the
4060 * functionality is enabled by the guest. */
4061
4062 if (uAddress == PMREGMISC)
4063 {
4064 RTIOPORT NewIoPortBase = 0;
4065 /* Check Power Management IO Space Enable (PMIOSE) bit */
4066 if (pPciDev->abConfig[PMREGMISC] & 0x01)
4067 {
4068 NewIoPortBase = (RTIOPORT)PDMPciDevGetDWord(pPciDev, PMBA);
4069 NewIoPortBase &= 0xffc0;
4070 }
4071
4072 int rc = acpiR3UpdatePmHandlers(pDevIns, pThis, pThisCC, NewIoPortBase);
4073 AssertRC(rc);
4074 }
4075
4076 if (uAddress == SMBHSTCFG)
4077 {
4078 RTIOPORT NewIoPortBase = 0;
4079 /* Check SMBus Controller Host Interface Enable (SMB_HST_EN) bit */
4080 if (pPciDev->abConfig[SMBHSTCFG] & SMBHSTCFG_SMB_HST_EN)
4081 {
4082 NewIoPortBase = (RTIOPORT)PDMPciDevGetDWord(pPciDev, SMBBA);
4083 NewIoPortBase &= 0xfff0;
4084 }
4085
4086 int rc = acpiR3UpdateSMBusHandlers(pDevIns, pThis, NewIoPortBase);
4087 AssertRC(rc);
4088 }
4089
4090 DEVACPI_UNLOCK(pDevIns, pThis);
4091 return rcStrict;
4092}
4093
4094/**
4095 * Attach a new CPU.
4096 *
4097 * @returns VBox status code.
4098 * @param pDevIns The device instance.
4099 * @param iLUN The logical unit which is being attached.
4100 * @param fFlags Flags, combination of the PDMDEVATT_FLAGS_* \#defines.
4101 *
4102 * @remarks This code path is not used during construction.
4103 */
4104static DECLCALLBACK(int) acpiR3Attach(PPDMDEVINS pDevIns, unsigned iLUN, uint32_t fFlags)
4105{
4106 PACPISTATE pThis = PDMDEVINS_2_DATA(pDevIns, PACPISTATE);
4107 PACPISTATER3 pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PACPISTATER3);
4108 LogFlow(("acpiAttach: pDevIns=%p iLUN=%u fFlags=%#x\n", pDevIns, iLUN, fFlags));
4109
4110 AssertMsgReturn(!(fFlags & PDM_TACH_FLAGS_NOT_HOT_PLUG),
4111 ("Hot-plug flag is not set\n"),
4112 VERR_NOT_SUPPORTED);
4113 AssertReturn(iLUN < VMM_MAX_CPU_COUNT, VERR_PDM_NO_SUCH_LUN);
4114
4115 /* Check if it was already attached */
4116 int rc = VINF_SUCCESS;
4117 DEVACPI_LOCK_R3(pDevIns, pThis);
4118 if (!VMCPUSET_IS_PRESENT(&pThis->CpuSetAttached, iLUN))
4119 {
4120 PPDMIBASE IBaseTmp;
4121 rc = PDMDevHlpDriverAttach(pDevIns, iLUN, &pThisCC->IBase, &IBaseTmp, "ACPI CPU");
4122 if (RT_SUCCESS(rc))
4123 {
4124 /* Enable the CPU */
4125 VMCPUSET_ADD(&pThis->CpuSetAttached, iLUN);
4126
4127 /*
4128 * Lock the CPU because we don't know if the guest will use it or not.
4129 * Prevents ejection while the CPU is still used
4130 */
4131 VMCPUSET_ADD(&pThis->CpuSetLocked, iLUN);
4132 pThis->u32CpuEventType = CPU_EVENT_TYPE_ADD;
4133 pThis->u32CpuEvent = iLUN;
4134
4135 /* Notify the guest */
4136 apicR3UpdateGpe0(pDevIns, pThis, pThis->gpe0_sts | 0x2, pThis->gpe0_en);
4137 }
4138 }
4139 DEVACPI_UNLOCK(pDevIns, pThis);
4140 return rc;
4141}
4142
4143/**
4144 * Detach notification.
4145 *
4146 * @param pDevIns The device instance.
4147 * @param iLUN The logical unit which is being detached.
4148 * @param fFlags Flags, combination of the PDMDEVATT_FLAGS_* \#defines.
4149 */
4150static DECLCALLBACK(void) acpiR3Detach(PPDMDEVINS pDevIns, unsigned iLUN, uint32_t fFlags)
4151{
4152 PACPISTATE pThis = PDMDEVINS_2_DATA(pDevIns, PACPISTATE);
4153
4154 LogFlow(("acpiDetach: pDevIns=%p iLUN=%u fFlags=%#x\n", pDevIns, iLUN, fFlags));
4155
4156 AssertMsgReturnVoid(!(fFlags & PDM_TACH_FLAGS_NOT_HOT_PLUG),
4157 ("Hot-plug flag is not set\n"));
4158
4159 /* Check if it was already detached */
4160 DEVACPI_LOCK_R3(pDevIns, pThis);
4161 if (VMCPUSET_IS_PRESENT(&pThis->CpuSetAttached, iLUN))
4162 {
4163 if (!VMCPUSET_IS_PRESENT(&pThis->CpuSetLocked, iLUN))
4164 {
4165 /* Disable the CPU */
4166 VMCPUSET_DEL(&pThis->CpuSetAttached, iLUN);
4167 pThis->u32CpuEventType = CPU_EVENT_TYPE_REMOVE;
4168 pThis->u32CpuEvent = iLUN;
4169
4170 /* Notify the guest */
4171 apicR3UpdateGpe0(pDevIns, pThis, pThis->gpe0_sts | 0x2, pThis->gpe0_en);
4172 }
4173 else
4174 AssertMsgFailed(("CPU is still locked by the guest\n"));
4175 }
4176 DEVACPI_UNLOCK(pDevIns, pThis);
4177}
4178
4179/**
4180 * @interface_method_impl{PDMDEVREG,pfnResume}
4181 */
4182static DECLCALLBACK(void) acpiR3Resume(PPDMDEVINS pDevIns)
4183{
4184 PACPISTATE pThis = PDMDEVINS_2_DATA(pDevIns, PACPISTATE);
4185 if (pThis->fSetWakeupOnResume)
4186 {
4187 Log(("acpiResume: setting WAK_STS\n"));
4188 pThis->fSetWakeupOnResume = false;
4189 pThis->pm1a_sts |= WAK_STS;
4190 }
4191}
4192
4193/**
4194 * @interface_method_impl{PDMDEVREG,pfnMemSetup}
4195 */
4196static DECLCALLBACK(void) acpiR3MemSetup(PPDMDEVINS pDevIns, PDMDEVMEMSETUPCTX enmCtx)
4197{
4198 RT_NOREF(enmCtx);
4199 PACPISTATE pThis = PDMDEVINS_2_DATA(pDevIns, PACPISTATE);
4200 PACPISTATER3 pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PACPISTATER3);
4201 acpiR3PlantTables(pDevIns, pThis, pThisCC);
4202}
4203
4204/**
4205 * @interface_method_impl{PDMDEVREG,pfnReset}
4206 */
4207static DECLCALLBACK(void) acpiR3Reset(PPDMDEVINS pDevIns)
4208{
4209 PACPISTATE pThis = PDMDEVINS_2_DATA(pDevIns, PACPISTATE);
4210 PACPISTATER3 pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PACPISTATER3);
4211
4212 /* Play safe: make sure that the IRQ isn't stuck after a reset. */
4213 acpiSetIrq(pDevIns, 0);
4214
4215 PDMDevHlpTimerLockClock(pDevIns, pThis->hPmTimer, VERR_IGNORED);
4216 pThis->pm1a_en = 0;
4217 pThis->pm1a_sts = 0;
4218 pThis->pm1a_ctl = 0;
4219 pThis->u64PmTimerInitial = PDMDevHlpTimerGet(pDevIns, pThis->hPmTimer);
4220 pThis->uPmTimerVal = 0;
4221 acpiR3PmTimerReset(pDevIns, pThis, pThis->u64PmTimerInitial);
4222 pThis->uPmTimeOld = pThis->uPmTimerVal;
4223 pThis->uBatteryIndex = 0;
4224 pThis->uSystemInfoIndex = 0;
4225 pThis->gpe0_en = 0;
4226 pThis->gpe0_sts = 0;
4227 pThis->uSleepState = 0;
4228 PDMDevHlpTimerUnlockClock(pDevIns, pThis->hPmTimer);
4229
4230 /* Real device behavior is resetting only the PM controller state,
4231 * but we're additionally doing the job of the BIOS. */
4232 acpiR3UpdatePmHandlers(pDevIns, pThis, pThisCC, PM_PORT_BASE);
4233 acpiR3PmPCIBIOSFake(pDevIns, pThis);
4234
4235 /* Reset SMBus base and PCI config space in addition to the SMBus controller
4236 * state. Real device behavior is only the SMBus controller state reset,
4237 * but we're additionally doing the job of the BIOS. */
4238 acpiR3UpdateSMBusHandlers(pDevIns, pThis, SMB_PORT_BASE);
4239 acpiR3SMBusPCIBIOSFake(pDevIns, pThis);
4240 acpiR3SMBusResetDevice(pThis);
4241}
4242
4243/**
4244 * @interface_method_impl{PDMDEVREG,pfnDestruct}
4245 */
4246static DECLCALLBACK(int) acpiR3Destruct(PPDMDEVINS pDevIns)
4247{
4248 PDMDEV_CHECK_VERSIONS_RETURN(pDevIns);
4249 PACPISTATE pThis = PDMDEVINS_2_DATA(pDevIns, PACPISTATE);
4250 PACPISTATER3 pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PACPISTATER3);
4251
4252 for (uint8_t i = 0; i < pThis->cCustTbls; i++)
4253 {
4254 if (pThisCC->apu8CustBin[i])
4255 {
4256 PDMDevHlpMMHeapFree(pDevIns, pThisCC->apu8CustBin[i]);
4257 pThisCC->apu8CustBin[i] = NULL;
4258 }
4259 }
4260 return VINF_SUCCESS;
4261}
4262
4263/**
4264 * @interface_method_impl{PDMDEVREG,pfnConstruct}
4265 */
4266static DECLCALLBACK(int) acpiR3Construct(PPDMDEVINS pDevIns, int iInstance, PCFGMNODE pCfg)
4267{
4268 PDMDEV_CHECK_VERSIONS_RETURN(pDevIns);
4269 PACPISTATE pThis = PDMDEVINS_2_DATA(pDevIns, PACPISTATE);
4270 PACPISTATER3 pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PACPISTATER3);
4271 PCPDMDEVHLPR3 pHlp = pDevIns->pHlpR3;
4272
4273 /*
4274 * Init data and set defaults.
4275 */
4276 /** @todo move more of the code up! */
4277
4278 pThisCC->pDevIns = pDevIns;
4279 VMCPUSET_EMPTY(&pThis->CpuSetAttached);
4280 VMCPUSET_EMPTY(&pThis->CpuSetLocked);
4281 pThis->idCpuLockCheck = UINT32_C(0xffffffff);
4282 pThis->u32CpuEventType = 0;
4283 pThis->u32CpuEvent = UINT32_C(0xffffffff);
4284
4285 /* The first CPU can't be attached/detached */
4286 VMCPUSET_ADD(&pThis->CpuSetAttached, 0);
4287 VMCPUSET_ADD(&pThis->CpuSetLocked, 0);
4288
4289 /* IBase */
4290 pThisCC->IBase.pfnQueryInterface = acpiR3QueryInterface;
4291 /* IACPIPort */
4292 pThisCC->IACPIPort.pfnGetGuestEnteredACPIMode = acpiR3Port_GetGuestEnteredACPIMode;
4293 pThisCC->IACPIPort.pfnGetCpuStatus = acpiR3Port_GetCpuStatus;
4294 pThisCC->IACPIPort.pfnMonitorHotPlugEvent = acpiR3Port_MonitorHotPlugEvent;
4295 pThisCC->IACPIPort.pfnBatteryStatusChangeEvent = acpiR3Port_BatteryStatusChangeEvent;
4296 /* IButtonEventPort */
4297 pThisCC->IButtonEventPort.pfnSleepButtonPress = acpiR3Port_SleepButtonPress;
4298 pThisCC->IButtonEventPort.pfnPowerButtonPress = acpiR3Port_PowerButtonPress;
4299 pThisCC->IButtonEventPort.pfnQueryPowerButtonHandled = acpiR3Port_QueryPowerButtonHandled;
4300 pThisCC->IButtonEventPort.pfnQueryGuestCanHandleButtonEvents = acpiR3Port_QueryGuestCanHandleButtonEvents;
4301
4302 /*
4303 * Set the default critical section to NOP (related to the PM timer).
4304 */
4305 int rc = PDMDevHlpSetDeviceCritSect(pDevIns, PDMDevHlpCritSectGetNop(pDevIns));
4306 AssertRCReturn(rc, rc);
4307
4308 rc = PDMDevHlpCritSectInit(pDevIns, &pThis->CritSect, RT_SRC_POS, "acpi#%u", iInstance);
4309 AssertRCReturn(rc, rc);
4310
4311 /*
4312 * Validate and read the configuration.
4313 */
4314 PDMDEV_VALIDATE_CONFIG_RETURN(pDevIns,
4315 "IOAPIC"
4316 "|NumCPUs"
4317 "|HpetEnabled"
4318 "|McfgEnabled"
4319 "|McfgBase"
4320 "|McfgLength"
4321 "|PciPref64Enabled"
4322 "|PciPref64LimitGB"
4323 "|SmcEnabled"
4324 "|FdcEnabled"
4325 "|ShowRtc"
4326 "|ShowCpu"
4327 "|NicPciAddress"
4328 "|AudioPciAddress"
4329 "|NvmePciAddress"
4330 "|IocPciAddress"
4331 "|HostBusPciAddress"
4332 "|EnableSuspendToDisk"
4333 "|PowerS1Enabled"
4334 "|PowerS4Enabled"
4335 "|CpuHotPlug"
4336 "|AmlFilePath"
4337 "|Serial0IoPortBase"
4338 "|Serial1IoPortBase"
4339 "|Serial2IoPortBase"
4340 "|Serial3IoPortBase"
4341 "|Serial0Irq"
4342 "|Serial1Irq"
4343 "|Serial2Irq"
4344 "|Serial3Irq"
4345 "|AcpiOemId"
4346 "|AcpiCreatorId"
4347 "|AcpiCreatorRev"
4348 "|CustomTable"
4349 "|CustomTable0"
4350 "|CustomTable1"
4351 "|CustomTable2"
4352 "|CustomTable3"
4353 "|Parallel0IoPortBase"
4354 "|Parallel1IoPortBase"
4355 "|Parallel0Irq"
4356 "|Parallel1Irq"
4357 "|IommuIntelEnabled"
4358 "|IommuAmdEnabled"
4359 "|IommuPciAddress"
4360 "|SbIoApicPciAddress"
4361 "|TpmMode"
4362 "|TpmMmioAddress"
4363 "|SsdtTpmFilePath"
4364 , "");
4365
4366 /* query whether we are supposed to present an IOAPIC */
4367 rc = pHlp->pfnCFGMQueryU8Def(pCfg, "IOAPIC", &pThis->u8UseIOApic, 1);
4368 if (RT_FAILURE(rc))
4369 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to read \"IOAPIC\""));
4370
4371 rc = pHlp->pfnCFGMQueryU16Def(pCfg, "NumCPUs", &pThis->cCpus, 1);
4372 if (RT_FAILURE(rc))
4373 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Querying \"NumCPUs\" as integer failed"));
4374
4375 /* query whether we are supposed to present an FDC controller */
4376 rc = pHlp->pfnCFGMQueryBoolDef(pCfg, "FdcEnabled", &pThis->fUseFdc, true);
4377 if (RT_FAILURE(rc))
4378 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to read \"FdcEnabled\""));
4379
4380 /* query whether we are supposed to present HPET */
4381 rc = pHlp->pfnCFGMQueryBoolDef(pCfg, "HpetEnabled", &pThis->fUseHpet, false);
4382 if (RT_FAILURE(rc))
4383 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to read \"HpetEnabled\""));
4384 /* query MCFG configuration */
4385 rc = pHlp->pfnCFGMQueryU64Def(pCfg, "McfgBase", &pThis->u64PciConfigMMioAddress, 0);
4386 if (RT_FAILURE(rc))
4387 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to read \"McfgBase\""));
4388 rc = pHlp->pfnCFGMQueryU64Def(pCfg, "McfgLength", &pThis->u64PciConfigMMioLength, 0);
4389 if (RT_FAILURE(rc))
4390 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to read \"McfgLength\""));
4391 pThis->fUseMcfg = (pThis->u64PciConfigMMioAddress != 0) && (pThis->u64PciConfigMMioLength != 0);
4392
4393 /* query whether we are supposed to set up the 64-bit prefetchable memory window */
4394 rc = pHlp->pfnCFGMQueryBoolDef(pCfg, "PciPref64Enabled", &pThis->fPciPref64Enabled, false);
4395 if (RT_FAILURE(rc))
4396 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to read \"PciPref64Enabled\""));
4397
4398 /* query the limit of the the 64-bit prefetchable memory window */
4399 uint64_t u64PciPref64MaxGB;
4400 rc = pHlp->pfnCFGMQueryU64Def(pCfg, "PciPref64LimitGB", &u64PciPref64MaxGB, 64);
4401 if (RT_FAILURE(rc))
4402 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to read \"PciPref64LimitGB\""));
4403 pThis->u64PciPref64Max = _1G64 * u64PciPref64MaxGB;
4404
4405 /* query whether we are supposed to present SMC */
4406 rc = pHlp->pfnCFGMQueryBoolDef(pCfg, "SmcEnabled", &pThis->fUseSmc, false);
4407 if (RT_FAILURE(rc))
4408 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to read \"SmcEnabled\""));
4409
4410 /* query whether we are supposed to present RTC object */
4411 rc = pHlp->pfnCFGMQueryBoolDef(pCfg, "ShowRtc", &pThis->fShowRtc, false);
4412 if (RT_FAILURE(rc))
4413 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to read \"ShowRtc\""));
4414
4415 /* query whether we are supposed to present CPU objects */
4416 rc = pHlp->pfnCFGMQueryBoolDef(pCfg, "ShowCpu", &pThis->fShowCpu, false);
4417 if (RT_FAILURE(rc))
4418 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to read \"ShowCpu\""));
4419
4420 /* query primary NIC PCI address (GIGE) */
4421 rc = pHlp->pfnCFGMQueryU32Def(pCfg, "NicPciAddress", &pThis->u32NicPciAddress, 0);
4422 if (RT_FAILURE(rc))
4423 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to read \"NicPciAddress\""));
4424
4425 /* query HD Audio PCI address (HDAA) */
4426 rc = pHlp->pfnCFGMQueryU32Def(pCfg, "AudioPciAddress", &pThis->u32AudioPciAddress, 0);
4427 if (RT_FAILURE(rc))
4428 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to read \"AudioPciAddress\""));
4429
4430 /* query NVMe PCI address (NVMA) */
4431 rc = pHlp->pfnCFGMQueryU32Def(pCfg, "NvmePciAddress", &pThis->u32NvmePciAddress, 0);
4432 if (RT_FAILURE(rc))
4433 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to read \"NvmePciAddress\""));
4434
4435 /* query IO controller (southbridge) PCI address */
4436 rc = pHlp->pfnCFGMQueryU32Def(pCfg, "IocPciAddress", &pThis->u32IocPciAddress, 0);
4437 if (RT_FAILURE(rc))
4438 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to read \"IocPciAddress\""));
4439
4440 /* query host bus controller PCI address */
4441 rc = pHlp->pfnCFGMQueryU32Def(pCfg, "HostBusPciAddress", &pThis->u32HbcPciAddress, 0);
4442 if (RT_FAILURE(rc))
4443 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to read \"HostBusPciAddress\""));
4444
4445 /* query whether S1 power state should be exposed */
4446 rc = pHlp->pfnCFGMQueryBoolDef(pCfg, "PowerS1Enabled", &pThis->fS1Enabled, false);
4447 if (RT_FAILURE(rc))
4448 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to read \"PowerS1Enabled\""));
4449
4450 /* query whether S4 power state should be exposed */
4451 rc = pHlp->pfnCFGMQueryBoolDef(pCfg, "PowerS4Enabled", &pThis->fS4Enabled, false);
4452 if (RT_FAILURE(rc))
4453 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to read \"PowerS4Enabled\""));
4454
4455 /* query whether S1 power state should save the VM state */
4456 rc = pHlp->pfnCFGMQueryBoolDef(pCfg, "EnableSuspendToDisk", &pThis->fSuspendToSavedState, false);
4457 if (RT_FAILURE(rc))
4458 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to read \"EnableSuspendToDisk\""));
4459
4460 /* query whether we are allow CPU hot plugging */
4461 rc = pHlp->pfnCFGMQueryBoolDef(pCfg, "CpuHotPlug", &pThis->fCpuHotPlug, false);
4462 if (RT_FAILURE(rc))
4463 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to read \"CpuHotPlug\""));
4464
4465 /* query serial info */
4466 rc = pHlp->pfnCFGMQueryU8Def(pCfg, "Serial0Irq", &pThis->uSerial0Irq, 4);
4467 if (RT_FAILURE(rc))
4468 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to read \"Serial0Irq\""));
4469
4470 rc = pHlp->pfnCFGMQueryU16Def(pCfg, "Serial0IoPortBase", &pThis->uSerial0IoPortBase, 0x3f8);
4471 if (RT_FAILURE(rc))
4472 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to read \"Serial0IoPortBase\""));
4473
4474 /* Serial 1 is enabled, get config data */
4475 rc = pHlp->pfnCFGMQueryU8Def(pCfg, "Serial1Irq", &pThis->uSerial1Irq, 3);
4476 if (RT_FAILURE(rc))
4477 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to read \"Serial1Irq\""));
4478
4479 rc = pHlp->pfnCFGMQueryU16Def(pCfg, "Serial1IoPortBase", &pThis->uSerial1IoPortBase, 0x2f8);
4480 if (RT_FAILURE(rc))
4481 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to read \"Serial1IoPortBase\""));
4482
4483 /* Read serial port 2 settings; disabled if CFGM keys do not exist. */
4484 rc = pHlp->pfnCFGMQueryU8Def(pCfg, "Serial2Irq", &pThis->uSerial2Irq, 0);
4485 if (RT_FAILURE(rc))
4486 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to read \"Serial2Irq\""));
4487
4488 rc = pHlp->pfnCFGMQueryU16Def(pCfg, "Serial2IoPortBase", &pThis->uSerial2IoPortBase, 0);
4489 if (RT_FAILURE(rc))
4490 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to read \"Serial2IoPortBase\""));
4491
4492 /* Read serial port 3 settings; disabled if CFGM keys do not exist. */
4493 rc = pHlp->pfnCFGMQueryU8Def(pCfg, "Serial3Irq", &pThis->uSerial3Irq, 0);
4494 if (RT_FAILURE(rc))
4495 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to read \"Serial3Irq\""));
4496
4497 rc = pHlp->pfnCFGMQueryU16Def(pCfg, "Serial3IoPortBase", &pThis->uSerial3IoPortBase, 0);
4498 if (RT_FAILURE(rc))
4499 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to read \"Serial3IoPortBase\""));
4500 /*
4501 * Query settings for both parallel ports, if the CFGM keys don't exist pretend that
4502 * the corresponding parallel port is not enabled.
4503 */
4504 rc = pHlp->pfnCFGMQueryU8Def(pCfg, "Parallel0Irq", &pThis->uParallel0Irq, 0);
4505 if (RT_FAILURE(rc))
4506 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to read \"Parallel0Irq\""));
4507
4508 rc = pHlp->pfnCFGMQueryU16Def(pCfg, "Parallel0IoPortBase", &pThis->uParallel0IoPortBase, 0);
4509 if (RT_FAILURE(rc))
4510 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to read \"Parallel0IoPortBase\""));
4511
4512 rc = pHlp->pfnCFGMQueryU8Def(pCfg, "Parallel1Irq", &pThis->uParallel1Irq, 0);
4513 if (RT_FAILURE(rc))
4514 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to read \"Parallel1Irq\""));
4515
4516 rc = pHlp->pfnCFGMQueryU16Def(pCfg, "Parallel1IoPortBase", &pThis->uParallel1IoPortBase, 0);
4517 if (RT_FAILURE(rc))
4518 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to read \"Parallel1IoPortBase\""));
4519
4520#ifdef VBOX_WITH_IOMMU_AMD
4521 /* Query whether an IOMMU (AMD) is enabled. */
4522 rc = pHlp->pfnCFGMQueryBoolDef(pCfg, "IommuAmdEnabled", &pThis->fUseIommuAmd, false);
4523 if (RT_FAILURE(rc))
4524 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to read \"IommuAmdEnabled\""));
4525
4526 if (pThis->fUseIommuAmd)
4527 {
4528 /* Query IOMMU AMD address (IOMA). */
4529 rc = pHlp->pfnCFGMQueryU32(pCfg, "IommuPciAddress", &pThis->u32IommuPciAddress);
4530 if (RT_FAILURE(rc))
4531 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to read \"IommuPciAddress\""));
4532
4533 /* Query southbridge I/O APIC address (required when an AMD IOMMU is configured). */
4534 rc = pHlp->pfnCFGMQueryU32(pCfg, "SbIoApicPciAddress", &pThis->u32SbIoApicPciAddress);
4535 if (RT_FAILURE(rc))
4536 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to read \"SbIoApicAddress\""));
4537
4538 /* Warn if the IOMMU Address is at the PCI host-bridge address. */
4539 /** @todo We should eventually not assign the IOMMU at this address, see
4540 * @bugref{9654#c53}. */
4541 if (!pThis->u32IommuPciAddress)
4542 LogRel(("ACPI: Warning! AMD IOMMU assigned the PCI host bridge address.\n"));
4543
4544 /* Warn if the IOAPIC is not at the expected address. */
4545 if (pThis->u32SbIoApicPciAddress != RT_MAKE_U32(VBOX_PCI_FN_SB_IOAPIC, VBOX_PCI_DEV_SB_IOAPIC))
4546 {
4547 LogRel(("ACPI: Southbridge I/O APIC not at %#x:%#x:%#x when an AMD IOMMU is present.\n",
4548 VBOX_PCI_BUS_SB_IOAPIC, VBOX_PCI_DEV_SB_IOAPIC, VBOX_PCI_FN_SB_IOAPIC));
4549 return PDMDEV_SET_ERROR(pDevIns, VERR_MISMATCH, N_("Configuration error: \"SbIoApicAddress\" mismatch"));
4550 }
4551 }
4552#endif
4553
4554#ifdef VBOX_WITH_IOMMU_INTEL
4555 /* Query whether an IOMMU (Intel) is enabled. */
4556 rc = pHlp->pfnCFGMQueryBoolDef(pCfg, "IommuIntelEnabled", &pThis->fUseIommuIntel, false);
4557 if (RT_FAILURE(rc))
4558 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to read \"IommuIntelEnabled\""));
4559
4560 if (pThis->fUseIommuIntel)
4561 {
4562 /* Query IOMMU Intel address. */
4563 rc = pHlp->pfnCFGMQueryU32(pCfg, "IommuPciAddress", &pThis->u32IommuPciAddress);
4564 if (RT_FAILURE(rc))
4565 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to read \"IommuPciAddress\""));
4566
4567 /* Get the reserved I/O APIC PCI address (required when an Intel IOMMU is configured). */
4568 rc = pHlp->pfnCFGMQueryU32(pCfg, "SbIoApicPciAddress", &pThis->u32SbIoApicPciAddress);
4569 if (RT_FAILURE(rc))
4570 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to read \"SbIoApicAddress\""));
4571
4572 /* Warn if the IOAPIC is not at the expected address. */
4573 if (pThis->u32SbIoApicPciAddress != RT_MAKE_U32(VBOX_PCI_FN_SB_IOAPIC, VBOX_PCI_DEV_SB_IOAPIC))
4574 {
4575 LogRel(("ACPI: Southbridge I/O APIC not at %#x:%#x:%#x when an Intel IOMMU is present.\n",
4576 VBOX_PCI_BUS_SB_IOAPIC, VBOX_PCI_DEV_SB_IOAPIC, VBOX_PCI_FN_SB_IOAPIC));
4577 return PDMDEV_SET_ERROR(pDevIns, VERR_MISMATCH, N_("Configuration error: \"SbIoApicAddress\" mismatch"));
4578 }
4579 }
4580#endif
4581
4582 /* Don't even think about enabling an Intel and an AMD IOMMU at the same time! */
4583 if ( pThis->fUseIommuAmd
4584 && pThis->fUseIommuIntel)
4585 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Cannot enable Intel and AMD IOMMU simultaneously!"));
4586
4587#ifdef VBOX_WITH_TPM
4588 char szTpmMode[64]; RT_ZERO(szTpmMode);
4589
4590 rc = pHlp->pfnCFGMQueryStringDef(pCfg, "TpmMode", &szTpmMode[0], RT_ELEMENTS(szTpmMode) - 1, "disabled");
4591 if (RT_FAILURE(rc))
4592 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to read \"TpmMode\""));
4593
4594 if (!RTStrICmp(szTpmMode, "disabled"))
4595 pThis->enmTpmMode = ACPITPMMODE_DISABLED;
4596 else if (!RTStrICmp(szTpmMode, "tis1.2"))
4597 pThis->enmTpmMode = ACPITPMMODE_TIS_1_2;
4598 else if (!RTStrICmp(szTpmMode, "crb2.0"))
4599 pThis->enmTpmMode = ACPITPMMODE_CRB_2_0;
4600 else if (!RTStrICmp(szTpmMode, "fifo2.0"))
4601 pThis->enmTpmMode = ACPITPMMODE_FIFO_2_0;
4602 else
4603 return PDMDEV_SET_ERROR(pDevIns, VERR_INVALID_PARAMETER, N_("Configuration error: Value of \"TpmMode\" is not known"));
4604
4605 rc = pHlp->pfnCFGMQueryU64Def(pCfg, "TpmMmioAddress", (uint64_t *)&pThis->GCPhysTpmMmio, ACPI_TPM_MMIO_BASE_DEFAULT);
4606 if (RT_FAILURE(rc))
4607 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to read \"TpmMmioAddress\""));
4608#endif
4609
4610 /* Try to attach the other CPUs */
4611 for (unsigned i = 1; i < pThis->cCpus; i++)
4612 {
4613 if (pThis->fCpuHotPlug)
4614 {
4615 PPDMIBASE IBaseTmp;
4616 rc = PDMDevHlpDriverAttach(pDevIns, i, &pThisCC->IBase, &IBaseTmp, "ACPI CPU");
4617
4618 if (RT_SUCCESS(rc))
4619 {
4620 VMCPUSET_ADD(&pThis->CpuSetAttached, i);
4621 VMCPUSET_ADD(&pThis->CpuSetLocked, i);
4622 Log(("acpi: Attached CPU %u\n", i));
4623 }
4624 else if (rc == VERR_PDM_NO_ATTACHED_DRIVER)
4625 Log(("acpi: CPU %u not attached yet\n", i));
4626 else
4627 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Failed to attach CPU object\n"));
4628 }
4629 else
4630 {
4631 /* CPU is always attached if hot-plug is not enabled. */
4632 VMCPUSET_ADD(&pThis->CpuSetAttached, i);
4633 VMCPUSET_ADD(&pThis->CpuSetLocked, i);
4634 }
4635 }
4636
4637 char szOemId[16];
4638 rc = pHlp->pfnCFGMQueryStringDef(pCfg, "AcpiOemId", szOemId, sizeof(szOemId), "VBOX ");
4639 if (RT_FAILURE(rc))
4640 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Querying \"AcpiOemId\" as string failed"));
4641 size_t cchOemId = strlen(szOemId);
4642 if (cchOemId > 6)
4643 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: \"AcpiOemId\" must contain not more than 6 characters"));
4644 memset(pThis->au8OemId, ' ', sizeof(pThis->au8OemId));
4645 memcpy(pThis->au8OemId, szOemId, cchOemId);
4646
4647 char szCreatorId[16];
4648 rc = pHlp->pfnCFGMQueryStringDef(pCfg, "AcpiCreatorId", szCreatorId, sizeof(szCreatorId), "ASL ");
4649 if (RT_FAILURE(rc))
4650 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Querying \"AcpiCreatorId\" as string failed"));
4651 size_t cchCreatorId = strlen(szCreatorId);
4652 if (cchCreatorId > 4)
4653 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: \"AcpiCreatorId\" must contain not more than 4 characters"));
4654 memset(pThis->au8CreatorId, ' ', sizeof(pThis->au8CreatorId));
4655 memcpy(pThis->au8CreatorId, szCreatorId, cchCreatorId);
4656
4657 rc = pHlp->pfnCFGMQueryU32Def(pCfg, "AcpiCreatorRev", &pThis->u32CreatorRev, RT_H2LE_U32(0x61));
4658 if (RT_FAILURE(rc))
4659 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Querying \"AcpiCreatorRev\" as integer failed"));
4660
4661 pThis->u32OemRevision = RT_H2LE_U32(0x1);
4662
4663 /*
4664 * Load custom ACPI tables.
4665 */
4666 /* Total space available for custom ACPI tables */
4667 /** @todo define as appropriate, remove as a magic number, and document
4668 * limitation in product manual */
4669 uint32_t cbBufAvail = 3072;
4670 pThis->cCustTbls = 0;
4671
4672 static const char *s_apszCustTblConfigKeys[] = {"CustomTable0", "CustomTable1", "CustomTable2", "CustomTable3"};
4673 AssertCompile(RT_ELEMENTS(s_apszCustTblConfigKeys) <= RT_ELEMENTS(pThisCC->apu8CustBin));
4674 for (unsigned i = 0; i < RT_ELEMENTS(s_apszCustTblConfigKeys); ++i)
4675 {
4676 const char *pszConfigKey = s_apszCustTblConfigKeys[i];
4677
4678 /*
4679 * Get the custom table binary file name.
4680 */
4681 char *pszCustBinFile = NULL;
4682 rc = pHlp->pfnCFGMQueryStringAlloc(pCfg, pszConfigKey, &pszCustBinFile);
4683 if (rc == VERR_CFGM_VALUE_NOT_FOUND && i == 0)
4684 rc = pHlp->pfnCFGMQueryStringAlloc(pCfg, "CustomTable", &pszCustBinFile); /* legacy */
4685 if (rc == VERR_CFGM_VALUE_NOT_FOUND)
4686 {
4687 rc = VINF_SUCCESS;
4688 pszCustBinFile = NULL;
4689 }
4690 else if (RT_FAILURE(rc))
4691 return PDMDEV_SET_ERROR(pDevIns, rc,
4692 N_("Configuration error: Querying \"CustomTableN\" as a string failed"));
4693 else if (!*pszCustBinFile)
4694 {
4695 PDMDevHlpMMHeapFree(pDevIns, pszCustBinFile);
4696 pszCustBinFile = NULL;
4697 }
4698
4699 /*
4700 * Determine the custom table binary size, open specified file in the process.
4701 */
4702 if (pszCustBinFile)
4703 {
4704 uint32_t idxCust = pThis->cCustTbls;
4705 rc = acpiR3ReadCustomTable(pDevIns, &pThisCC->apu8CustBin[idxCust],
4706 &pThisCC->acbCustBin[idxCust], pszCustBinFile, cbBufAvail);
4707 LogRel(("ACPI: Reading custom ACPI table(%u) from file '%s' (%d bytes)\n",
4708 idxCust, pszCustBinFile, pThisCC->acbCustBin[idxCust]));
4709 PDMDevHlpMMHeapFree(pDevIns, pszCustBinFile);
4710 if (RT_FAILURE(rc))
4711 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Error reading custom ACPI table."));
4712 cbBufAvail -= pThisCC->acbCustBin[idxCust];
4713
4714 /* Update custom OEM attributes based on custom table */
4715 /** @todo is it intended for custom tables to overwrite user provided values above? */
4716 ACPITBLHEADER *pTblHdr = (ACPITBLHEADER*)pThisCC->apu8CustBin[idxCust];
4717 memcpy(&pThis->au8OemId[0], &pTblHdr->au8OemId[0], 6);
4718 memcpy(&pThis->au8OemTabId[0], &pTblHdr->au8OemTabId[0], 8);
4719 pThis->u32OemRevision = pTblHdr->u32OemRevision;
4720 memcpy(&pThis->au8CreatorId[0], &pTblHdr->au8CreatorId[0], 4);
4721 pThis->u32CreatorRev = pTblHdr->u32CreatorRev;
4722
4723 pThis->cCustTbls++;
4724 AssertBreak(pThis->cCustTbls <= MAX_CUST_TABLES);
4725 }
4726 }
4727
4728 /* Set default PM port base */
4729 pThis->uPmIoPortBase = PM_PORT_BASE;
4730
4731 /* Set default SMBus port base */
4732 pThis->uSMBusIoPortBase = SMB_PORT_BASE;
4733
4734 /*
4735 * FDC and SMC try to use the same non-shareable interrupt (6),
4736 * enable only one device.
4737 */
4738 if (pThis->fUseSmc)
4739 pThis->fUseFdc = false;
4740
4741 /*
4742 * Plant ACPI tables.
4743 */
4744 /** @todo Part of this is redone by acpiR3MemSetup, we only need to init the
4745 * au8RSDPPage here. However, there should be no harm in doing it
4746 * twice, so the lazy bird is taking the quick way out for now. */
4747 RTGCPHYS32 GCPhysRsdp = apicR3FindRsdpSpace();
4748 if (!GCPhysRsdp)
4749 return PDMDEV_SET_ERROR(pDevIns, VERR_NO_MEMORY, N_("Can not find space for RSDP. ACPI is disabled"));
4750
4751 rc = acpiR3PlantTables(pDevIns, pThis, pThisCC);
4752 AssertRCReturn(rc, rc);
4753
4754 rc = PDMDevHlpROMRegister(pDevIns, GCPhysRsdp, 0x1000, pThis->au8RSDPPage, 0x1000,
4755 PGMPHYS_ROM_FLAGS_PERMANENT_BINARY, "ACPI RSDP");
4756 AssertRCReturn(rc, rc);
4757
4758 /*
4759 * Create the PM I/O ports. These can be unmapped and remapped.
4760 */
4761 rc = PDMDevHlpIoPortCreateIsa(pDevIns, 1 /*cPorts*/, acpiR3PM1aStsWrite, acpiR3Pm1aStsRead, NULL /*pvUser*/,
4762 "ACPI PM1a Status", NULL /*paExtDesc*/, &pThis->hIoPortPm1aSts);
4763 AssertRCReturn(rc, rc);
4764 rc = PDMDevHlpIoPortCreateIsa(pDevIns, 1 /*cPorts*/, acpiR3PM1aEnWrite, acpiR3Pm1aEnRead, NULL /*pvUser*/,
4765 "ACPI PM1a Enable", NULL /*paExtDesc*/, &pThis->hIoPortPm1aEn);
4766 AssertRCReturn(rc, rc);
4767 rc = PDMDevHlpIoPortCreateIsa(pDevIns, 1 /*cPorts*/, acpiR3PM1aCtlWrite, acpiR3Pm1aCtlRead, NULL /*pvUser*/,
4768 "ACPI PM1a Control", NULL /*paExtDesc*/, &pThis->hIoPortPm1aCtl);
4769 AssertRCReturn(rc, rc);
4770 rc = PDMDevHlpIoPortCreateIsa(pDevIns, 1 /*cPorts*/, NULL, acpiPMTmrRead, NULL /*pvUser*/,
4771 "ACPI PM Timer", NULL /*paExtDesc*/, &pThis->hIoPortPmTimer);
4772 AssertRCReturn(rc, rc);
4773 rc = PDMDevHlpIoPortCreateIsa(pDevIns, GPE0_BLK_LEN / 2 /*cPorts*/, acpiR3Gpe0StsWrite, acpiR3Gpe0StsRead, NULL /*pvUser*/,
4774 "ACPI GPE0 Status", NULL /*paExtDesc*/, &pThis->hIoPortGpe0Sts);
4775 AssertRCReturn(rc, rc);
4776 rc = PDMDevHlpIoPortCreateIsa(pDevIns, GPE0_BLK_LEN / 2 /*cPorts*/, acpiR3Gpe0EnWrite, acpiR3Gpe0EnRead, NULL /*pvUser*/,
4777 "ACPI GPE0 Enable", NULL /*paExtDesc*/, &pThis->hIoPortGpe0En);
4778 AssertRCReturn(rc, rc);
4779 rc = acpiR3MapPmIoPorts(pDevIns, pThis);
4780 AssertRCReturn(rc, rc);
4781
4782 /*
4783 * Create the System Management Bus I/O ports. These can be unmapped and remapped.
4784 */
4785 rc = PDMDevHlpIoPortCreateIsa(pDevIns, 16, acpiR3SMBusWrite, acpiR3SMBusRead, NULL /*pvUser*/,
4786 "SMBus", NULL /*paExtDesc*/, &pThis->hIoPortSMBus);
4787 AssertRCReturn(rc, rc);
4788 rc = acpiR3MapSMBusIoPorts(pDevIns, pThis);
4789 AssertRCReturn(rc, rc);
4790
4791 /*
4792 * Create and map the fixed I/O ports.
4793 */
4794 rc = PDMDevHlpIoPortCreateAndMap(pDevIns, SMI_CMD, 1, acpiR3SmiWrite, NULL,
4795 "ACPI SMI", NULL /*paExtDesc*/, &pThis->hIoPortSmi);
4796 AssertRCReturn(rc, rc);
4797#ifdef DEBUG_ACPI
4798 rc = PDMDevHlpIoPortCreateAndMap(pDevIns, DEBUG_HEX, 1, acpiR3DebugHexWrite, NULL,
4799 "ACPI Debug hex", NULL /*paExtDesc*/, &pThis->hIoPortDebugHex);
4800 AssertRCReturn(rc, rc);
4801 rc = PDMDevHlpIoPortCreateAndMap(pDevIns, DEBUG_CHR, 1, acpiR3DebugCharWrite, NULL,
4802 "ACPI Debug char", NULL /*paExtDesc*/, &pThis->hIoPortDebugChar);
4803 AssertRCReturn(rc, rc);
4804#endif
4805 rc = PDMDevHlpIoPortCreateAndMap(pDevIns, BAT_INDEX, 1, acpiR3BatIndexWrite, NULL,
4806 "ACPI Battery status index", NULL /*paExtDesc*/, &pThis->hIoPortBatteryIndex);
4807 AssertRCReturn(rc, rc);
4808 rc = PDMDevHlpIoPortCreateAndMap(pDevIns, BAT_DATA, 1, NULL, acpiR3BatDataRead,
4809 "ACPI Battery status data", NULL /*paExtDesc*/, &pThis->hIoPortBatteryData);
4810 AssertRCReturn(rc, rc);
4811 rc = PDMDevHlpIoPortCreateAndMap(pDevIns, SYSI_INDEX, 1, acpiR3SysInfoIndexWrite, NULL,
4812 "ACPI system info index", NULL /*paExtDesc*/, &pThis->hIoPortSysInfoIndex);
4813 AssertRCReturn(rc, rc);
4814 rc = PDMDevHlpIoPortCreateAndMap(pDevIns, SYSI_DATA, 1, acpiR3SysInfoDataWrite, acpiR3SysInfoDataRead,
4815 "ACPI system info data", NULL /*paExtDesc*/, &pThis->hIoPortSysInfoData);
4816 AssertRCReturn(rc, rc);
4817 rc = PDMDevHlpIoPortCreateAndMap(pDevIns, ACPI_RESET_BLK, 1, acpiR3ResetWrite, NULL,
4818 "ACPI Reset", NULL /*paExtDesc*/, &pThis->hIoPortReset);
4819 AssertRCReturn(rc, rc);
4820
4821 /*
4822 * Create the PM timer.
4823 */
4824 rc = PDMDevHlpTimerCreate(pDevIns, TMCLOCK_VIRTUAL_SYNC, acpiR3PmTimer, NULL /*pvUser*/,
4825 TMTIMER_FLAGS_NO_CRIT_SECT | TMTIMER_FLAGS_RING0, "ACPI PM", &pThis->hPmTimer);
4826 AssertRCReturn(rc, rc);
4827
4828 PDMDevHlpTimerLockClock(pDevIns, pThis->hPmTimer, VERR_IGNORED);
4829 pThis->u64PmTimerInitial = PDMDevHlpTimerGet(pDevIns, pThis->hPmTimer);
4830 acpiR3PmTimerReset(pDevIns, pThis, pThis->u64PmTimerInitial);
4831 PDMDevHlpTimerUnlockClock(pDevIns, pThis->hPmTimer);
4832
4833 /*
4834 * Set up the PCI device.
4835 */
4836 PPDMPCIDEV pPciDev = pDevIns->apPciDevs[0];
4837 PDMPCIDEV_ASSERT_VALID(pDevIns, pPciDev);
4838
4839 PDMPciDevSetVendorId(pPciDev, 0x8086); /* Intel */
4840 PDMPciDevSetDeviceId(pPciDev, 0x7113); /* 82371AB */
4841
4842 /* See p. 50 of PIIX4 manual */
4843 PDMPciDevSetCommand(pPciDev, PCI_COMMAND_IOACCESS);
4844 PDMPciDevSetStatus(pPciDev, 0x0280);
4845
4846 PDMPciDevSetRevisionId(pPciDev, 0x08);
4847
4848 PDMPciDevSetClassProg(pPciDev, 0x00);
4849 PDMPciDevSetClassSub(pPciDev, 0x80);
4850 PDMPciDevSetClassBase(pPciDev, 0x06);
4851
4852 PDMPciDevSetHeaderType(pPciDev, 0x80);
4853
4854 PDMPciDevSetBIST(pPciDev, 0x00);
4855
4856 PDMPciDevSetInterruptLine(pPciDev, SCI_INT);
4857 PDMPciDevSetInterruptPin(pPciDev, 0x01);
4858
4859 Assert((pThis->uPmIoPortBase & 0x003f) == 0);
4860 acpiR3PmPCIBIOSFake(pDevIns, pThis);
4861
4862 Assert((pThis->uSMBusIoPortBase & 0x000f) == 0);
4863 acpiR3SMBusPCIBIOSFake(pDevIns, pThis);
4864 acpiR3SMBusResetDevice(pThis);
4865
4866 rc = PDMDevHlpPCIRegister(pDevIns, pPciDev);
4867 AssertRCReturn(rc, rc);
4868
4869 rc = PDMDevHlpPCIInterceptConfigAccesses(pDevIns, pPciDev, acpiR3PciConfigRead, acpiR3PciConfigWrite);
4870 AssertRCReturn(rc, rc);
4871
4872 /*
4873 * Register the saved state.
4874 */
4875 rc = PDMDevHlpSSMRegister(pDevIns, 8, sizeof(*pThis), acpiR3SaveState, acpiR3LoadState);
4876 AssertRCReturn(rc, rc);
4877
4878 /*
4879 * Get the corresponding connector interface
4880 */
4881 rc = PDMDevHlpDriverAttach(pDevIns, 0, &pThisCC->IBase, &pThisCC->pDrvBase, "ACPI Driver Port");
4882 if (RT_SUCCESS(rc))
4883 {
4884 pThisCC->pDrv = PDMIBASE_QUERY_INTERFACE(pThisCC->pDrvBase, PDMIACPICONNECTOR);
4885 if (!pThisCC->pDrv)
4886 return PDMDEV_SET_ERROR(pDevIns, VERR_PDM_MISSING_INTERFACE, N_("LUN #0 doesn't have an ACPI connector interface"));
4887 }
4888 else if (rc == VERR_PDM_NO_ATTACHED_DRIVER)
4889 {
4890 Log(("acpi: %s/%d: warning: no driver attached to LUN #0!\n", pDevIns->pReg->szName, pDevIns->iInstance));
4891 rc = VINF_SUCCESS;
4892 }
4893 else
4894 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Failed to attach LUN #0"));
4895
4896 PDMDevHlpDBGFInfoRegister(pDevIns, "acpi", "ACPI info", acpiR3Info);
4897
4898 return rc;
4899}
4900
4901#else /* !IN_RING3 */
4902
4903/**
4904 * @callback_method_impl{PDMDEVREGR0,pfnConstruct}
4905 */
4906static DECLCALLBACK(int) acpiRZConstruct(PPDMDEVINS pDevIns)
4907{
4908 PDMDEV_CHECK_VERSIONS_RETURN(pDevIns);
4909 PACPISTATE pThis = PDMDEVINS_2_DATA(pDevIns, PACPISTATE);
4910
4911 int rc = PDMDevHlpSetDeviceCritSect(pDevIns, PDMDevHlpCritSectGetNop(pDevIns));
4912 AssertRCReturn(rc, rc);
4913
4914 /* Only the PM timer read port is handled directly in ring-0/raw-mode. */
4915 rc = PDMDevHlpIoPortSetUpContext(pDevIns, pThis->hIoPortPmTimer, NULL, acpiPMTmrRead, NULL);
4916 AssertRCReturn(rc, rc);
4917
4918 return VINF_SUCCESS;
4919}
4920
4921#endif /* !IN_RING3 */
4922
4923/**
4924 * The device registration structure.
4925 */
4926const PDMDEVREG g_DeviceACPI =
4927{
4928 /* .u32Version = */ PDM_DEVREG_VERSION,
4929 /* .uReserved0 = */ 0,
4930 /* .szName = */ "acpi",
4931 /* .fFlags = */ PDM_DEVREG_FLAGS_DEFAULT_BITS | PDM_DEVREG_FLAGS_RZ | PDM_DEVREG_FLAGS_NEW_STYLE,
4932 /* .fClass = */ PDM_DEVREG_CLASS_ACPI,
4933 /* .cMaxInstances = */ ~0U,
4934 /* .uSharedVersion = */ 42,
4935 /* .cbInstanceShared = */ sizeof(ACPISTATE),
4936 /* .cbInstanceCC = */ CTX_EXPR(sizeof(ACPISTATER3), 0, 0),
4937 /* .cbInstanceRC = */ 0,
4938 /* .cMaxPciDevices = */ 1,
4939 /* .cMaxMsixVectors = */ 0,
4940 /* .pszDescription = */ "Advanced Configuration and Power Interface",
4941#if defined(IN_RING3)
4942 /* .pszRCMod = */ "VBoxDDRC.rc",
4943 /* .pszR0Mod = */ "VBoxDDR0.r0",
4944 /* .pfnConstruct = */ acpiR3Construct,
4945 /* .pfnDestruct = */ acpiR3Destruct,
4946 /* .pfnRelocate = */ NULL,
4947 /* .pfnMemSetup = */ acpiR3MemSetup,
4948 /* .pfnPowerOn = */ NULL,
4949 /* .pfnReset = */ acpiR3Reset,
4950 /* .pfnSuspend = */ NULL,
4951 /* .pfnResume = */ acpiR3Resume,
4952 /* .pfnAttach = */ acpiR3Attach,
4953 /* .pfnDetach = */ acpiR3Detach,
4954 /* .pfnQueryInterface = */ NULL,
4955 /* .pfnInitComplete = */ NULL,
4956 /* .pfnPowerOff = */ NULL,
4957 /* .pfnSoftReset = */ NULL,
4958 /* .pfnReserved0 = */ NULL,
4959 /* .pfnReserved1 = */ NULL,
4960 /* .pfnReserved2 = */ NULL,
4961 /* .pfnReserved3 = */ NULL,
4962 /* .pfnReserved4 = */ NULL,
4963 /* .pfnReserved5 = */ NULL,
4964 /* .pfnReserved6 = */ NULL,
4965 /* .pfnReserved7 = */ NULL,
4966#elif defined(IN_RING0)
4967 /* .pfnEarlyConstruct = */ NULL,
4968 /* .pfnConstruct = */ acpiRZConstruct,
4969 /* .pfnDestruct = */ NULL,
4970 /* .pfnFinalDestruct = */ NULL,
4971 /* .pfnRequest = */ NULL,
4972 /* .pfnReserved0 = */ NULL,
4973 /* .pfnReserved1 = */ NULL,
4974 /* .pfnReserved2 = */ NULL,
4975 /* .pfnReserved3 = */ NULL,
4976 /* .pfnReserved4 = */ NULL,
4977 /* .pfnReserved5 = */ NULL,
4978 /* .pfnReserved6 = */ NULL,
4979 /* .pfnReserved7 = */ NULL,
4980#elif defined(IN_RC)
4981 /* .pfnConstruct = */ acpiRZConstruct,
4982 /* .pfnReserved0 = */ NULL,
4983 /* .pfnReserved1 = */ NULL,
4984 /* .pfnReserved2 = */ NULL,
4985 /* .pfnReserved3 = */ NULL,
4986 /* .pfnReserved4 = */ NULL,
4987 /* .pfnReserved5 = */ NULL,
4988 /* .pfnReserved6 = */ NULL,
4989 /* .pfnReserved7 = */ NULL,
4990#else
4991# error "Not in IN_RING3, IN_RING0 or IN_RC!"
4992#endif
4993 /* .u32VersionEnd = */ PDM_DEVREG_VERSION
4994};
4995
4996#endif /* !VBOX_DEVICE_STRUCT_TESTCASE */
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