| 1 | /*
|
|---|
| 2 | * Copyright (C) 2006-2016 Oracle Corporation
|
|---|
| 3 | *
|
|---|
| 4 | * This file is part of VirtualBox Open Source Edition (OSE), as
|
|---|
| 5 | * available from http://www.virtualbox.org. This file is free software;
|
|---|
| 6 | * you can redistribute it and/or modify it under the terms of the GNU
|
|---|
| 7 | * General Public License (GPL) as published by the Free Software
|
|---|
| 8 | * Foundation, in version 2 as it comes in the "COPYING" file of the
|
|---|
| 9 | * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
|
|---|
| 10 | * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
|
|---|
| 11 | * --------------------------------------------------------------------
|
|---|
| 12 | *
|
|---|
| 13 | * This code is based on:
|
|---|
| 14 | *
|
|---|
| 15 | * ROM BIOS for use with Bochs/Plex86/QEMU emulation environment
|
|---|
| 16 | *
|
|---|
| 17 | * Copyright (C) 2002 MandrakeSoft S.A.
|
|---|
| 18 | *
|
|---|
| 19 | * MandrakeSoft S.A.
|
|---|
| 20 | * 43, rue d'Aboukir
|
|---|
| 21 | * 75002 Paris - France
|
|---|
| 22 | * http://www.linux-mandrake.com/
|
|---|
| 23 | * http://www.mandrakesoft.com/
|
|---|
| 24 | *
|
|---|
| 25 | * This library is free software; you can redistribute it and/or
|
|---|
| 26 | * modify it under the terms of the GNU Lesser General Public
|
|---|
| 27 | * License as published by the Free Software Foundation; either
|
|---|
| 28 | * version 2 of the License, or (at your option) any later version.
|
|---|
| 29 | *
|
|---|
| 30 | * This library is distributed in the hope that it will be useful,
|
|---|
| 31 | * but WITHOUT ANY WARRANTY; without even the implied warranty of
|
|---|
| 32 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
|
|---|
| 33 | * Lesser General Public License for more details.
|
|---|
| 34 | *
|
|---|
| 35 | * You should have received a copy of the GNU Lesser General Public
|
|---|
| 36 | * License along with this library; if not, write to the Free Software
|
|---|
| 37 | * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
|
|---|
| 38 | *
|
|---|
| 39 | */
|
|---|
| 40 |
|
|---|
| 41 |
|
|---|
| 42 | #include <stdint.h>
|
|---|
| 43 | #include "biosint.h"
|
|---|
| 44 | #include "inlines.h"
|
|---|
| 45 |
|
|---|
| 46 | #if DEBUG_INT1A
|
|---|
| 47 | # define BX_DEBUG_INT1A(...) BX_DEBUG(__VA_ARGS__)
|
|---|
| 48 | #else
|
|---|
| 49 | # define BX_DEBUG_INT1A(...)
|
|---|
| 50 | #endif
|
|---|
| 51 |
|
|---|
| 52 | // for access to RAM area which is used by interrupt vectors
|
|---|
| 53 | // and BIOS Data Area
|
|---|
| 54 |
|
|---|
| 55 | typedef struct {
|
|---|
| 56 | uint8_t filler1[0x400];
|
|---|
| 57 | uint8_t filler2[0x6c];
|
|---|
| 58 | uint16_t ticks_low;
|
|---|
| 59 | uint16_t ticks_high;
|
|---|
| 60 | uint8_t midnight_flag;
|
|---|
| 61 | } bios_data_t;
|
|---|
| 62 |
|
|---|
| 63 | #define BiosData ((bios_data_t __far *) 0)
|
|---|
| 64 |
|
|---|
| 65 | void init_rtc(void)
|
|---|
| 66 | {
|
|---|
| 67 | outb_cmos(0x0a, 0x26);
|
|---|
| 68 | outb_cmos(0x0b, 0x02);
|
|---|
| 69 | inb_cmos(0x0c);
|
|---|
| 70 | inb_cmos(0x0d);
|
|---|
| 71 | }
|
|---|
| 72 |
|
|---|
| 73 | bx_bool rtc_updating(void)
|
|---|
| 74 | {
|
|---|
| 75 | // This function checks to see if the update-in-progress bit
|
|---|
| 76 | // is set in CMOS Status Register A. If not, it returns 0.
|
|---|
| 77 | // If it is set, it tries to wait until there is a transition
|
|---|
| 78 | // to 0, and will return 0 if such a transition occurs. A 1
|
|---|
| 79 | // is returned only after timing out. The maximum period
|
|---|
| 80 | // that this bit should be set is constrained to 244useconds.
|
|---|
| 81 | // The count I use below guarantees coverage or more than
|
|---|
| 82 | // this time, with any reasonable IPS setting.
|
|---|
| 83 |
|
|---|
| 84 | uint16_t iter;
|
|---|
| 85 |
|
|---|
| 86 | iter = 25000;
|
|---|
| 87 | while (--iter != 0) {
|
|---|
| 88 | if ( (inb_cmos(0x0a) & 0x80) == 0 )
|
|---|
| 89 | return 0;
|
|---|
| 90 | }
|
|---|
| 91 | return 1; // update-in-progress never transitioned to 0
|
|---|
| 92 | }
|
|---|
| 93 |
|
|---|
| 94 |
|
|---|
| 95 | extern void eoi_both_pics(void); /* in assembly code */
|
|---|
| 96 | #pragma aux eoi_both_pics "*";
|
|---|
| 97 |
|
|---|
| 98 | void call_int_4a(void);
|
|---|
| 99 | #pragma aux call_int_4a = "int 4Ah";
|
|---|
| 100 |
|
|---|
| 101 | void BIOSCALL int70_function(pusha_regs_t regs, uint16_t ds, uint16_t es, iret_addr_t iret_addr)
|
|---|
| 102 | {
|
|---|
| 103 | // INT 70h: IRQ 8 - CMOS RTC interrupt from periodic or alarm modes
|
|---|
| 104 | uint8_t registerB = 0, registerC = 0;
|
|---|
| 105 |
|
|---|
| 106 | // Check which modes are enabled and have occurred.
|
|---|
| 107 | registerB = inb_cmos( 0xB );
|
|---|
| 108 | registerC = inb_cmos( 0xC );
|
|---|
| 109 |
|
|---|
| 110 | if( ( registerB & 0x60 ) != 0 ) {
|
|---|
| 111 | if( ( registerC & 0x20 ) != 0 ) {
|
|---|
| 112 | // Handle Alarm Interrupt.
|
|---|
| 113 | int_enable();
|
|---|
| 114 | call_int_4a();
|
|---|
| 115 | int_disable();
|
|---|
| 116 | }
|
|---|
| 117 | if( ( registerC & 0x40 ) != 0 ) {
|
|---|
| 118 | // Handle Periodic Interrupt.
|
|---|
| 119 |
|
|---|
| 120 | if( read_byte( 0x40, 0xA0 ) != 0 ) {
|
|---|
| 121 | // Wait Interval (Int 15, AH=83) active.
|
|---|
| 122 | uint32_t time;
|
|---|
| 123 |
|
|---|
| 124 | time = read_dword( 0x40, 0x9C ); // Time left in microseconds.
|
|---|
| 125 | if( time < 0x3D1 ) {
|
|---|
| 126 | // Done waiting.
|
|---|
| 127 | uint16_t segment, offset;
|
|---|
| 128 |
|
|---|
| 129 | segment = read_word( 0x40, 0x98 );
|
|---|
| 130 | offset = read_word( 0x40, 0x9A );
|
|---|
| 131 | write_byte( 0x40, 0xA0, 0 ); // Turn of status byte.
|
|---|
| 132 | outb_cmos( 0xB, registerB & 0x37 ); // Clear the Periodic Interrupt.
|
|---|
| 133 | write_byte( segment, offset, read_byte(segment, offset) | 0x80 ); // Write to specified flag byte.
|
|---|
| 134 | } else {
|
|---|
| 135 | // Continue waiting.
|
|---|
| 136 | time -= 0x3D1;
|
|---|
| 137 | write_dword( 0x40, 0x9C, time );
|
|---|
| 138 | }
|
|---|
| 139 | }
|
|---|
| 140 | }
|
|---|
| 141 | }
|
|---|
| 142 | eoi_both_pics();
|
|---|
| 143 | }
|
|---|
| 144 |
|
|---|
| 145 | // @todo: the coding style WRT register access is totally inconsistent
|
|---|
| 146 | // in the following routines
|
|---|
| 147 |
|
|---|
| 148 | void BIOSCALL int1a_function(pusha_regs_t regs, uint16_t ds, uint16_t es, iret_addr_t iret_addr)
|
|---|
| 149 | {
|
|---|
| 150 | uint8_t val8;
|
|---|
| 151 |
|
|---|
| 152 | BX_DEBUG_INT1A("int1a: AX=%04x BX=%04x CX=%04x DX=%04x DS=%04x\n",
|
|---|
| 153 | regs.u.r16.ax, regs.u.r16.bx, regs.u.r16.cx, regs.u.r16.dx, ds);
|
|---|
| 154 | int_enable();
|
|---|
| 155 |
|
|---|
| 156 | switch (regs.u.r8.ah) {
|
|---|
| 157 | case 0: // get current clock count
|
|---|
| 158 | int_disable();
|
|---|
| 159 | regs.u.r16.cx = BiosData->ticks_high;
|
|---|
| 160 | regs.u.r16.dx = BiosData->ticks_low;
|
|---|
| 161 | regs.u.r8.al = BiosData->midnight_flag;
|
|---|
| 162 | BiosData->midnight_flag = 0; // reset flag
|
|---|
| 163 | int_enable();
|
|---|
| 164 | // AH already 0
|
|---|
| 165 | ClearCF(iret_addr.flags); // OK
|
|---|
| 166 | break;
|
|---|
| 167 |
|
|---|
| 168 | case 1: // Set Current Clock Count
|
|---|
| 169 | int_disable();
|
|---|
| 170 | BiosData->ticks_high = regs.u.r16.cx;
|
|---|
| 171 | BiosData->ticks_low = regs.u.r16.dx;
|
|---|
| 172 | BiosData->midnight_flag = 0; // reset flag
|
|---|
| 173 | int_enable();
|
|---|
| 174 | regs.u.r8.ah = 0;
|
|---|
| 175 | ClearCF(iret_addr.flags); // OK
|
|---|
| 176 | break;
|
|---|
| 177 |
|
|---|
| 178 | case 2: // Read CMOS Time
|
|---|
| 179 | if (rtc_updating()) {
|
|---|
| 180 | SetCF(iret_addr.flags);
|
|---|
| 181 | break;
|
|---|
| 182 | }
|
|---|
| 183 |
|
|---|
| 184 | regs.u.r8.dh = inb_cmos(0x00); // Seconds
|
|---|
| 185 | regs.u.r8.cl = inb_cmos(0x02); // Minutes
|
|---|
| 186 | regs.u.r8.ch = inb_cmos(0x04); // Hours
|
|---|
| 187 | regs.u.r8.dl = inb_cmos(0x0b) & 0x01; // Stat Reg B
|
|---|
| 188 | regs.u.r8.ah = 0;
|
|---|
| 189 | regs.u.r8.al = regs.u.r8.ch;
|
|---|
| 190 | ClearCF(iret_addr.flags); // OK
|
|---|
| 191 | break;
|
|---|
| 192 |
|
|---|
| 193 | case 3: // Set CMOS Time
|
|---|
| 194 | // Using a debugger, I notice the following masking/setting
|
|---|
| 195 | // of bits in Status Register B, by setting Reg B to
|
|---|
| 196 | // a few values and getting its value after INT 1A was called.
|
|---|
| 197 | //
|
|---|
| 198 | // try#1 try#2 try#3
|
|---|
| 199 | // before 1111 1101 0111 1101 0000 0000
|
|---|
| 200 | // after 0110 0010 0110 0010 0000 0010
|
|---|
| 201 | //
|
|---|
| 202 | // Bit4 in try#1 flipped in hardware (forced low) due to bit7=1
|
|---|
| 203 | // My assumption: RegB = ((RegB & 01100000b) | 00000010b)
|
|---|
| 204 | if (rtc_updating()) {
|
|---|
| 205 | init_rtc();
|
|---|
| 206 | // fall through as if an update were not in progress
|
|---|
| 207 | }
|
|---|
| 208 | outb_cmos(0x00, regs.u.r8.dh); // Seconds
|
|---|
| 209 | outb_cmos(0x02, regs.u.r8.cl); // Minutes
|
|---|
| 210 | outb_cmos(0x04, regs.u.r8.ch); // Hours
|
|---|
| 211 | // Set Daylight Savings time enabled bit to requested value
|
|---|
| 212 | val8 = (inb_cmos(0x0b) & 0x60) | 0x02 | (regs.u.r8.dl & 0x01);
|
|---|
| 213 | // (reg B already selected)
|
|---|
| 214 | outb_cmos(0x0b, val8);
|
|---|
| 215 | regs.u.r8.ah = 0;
|
|---|
| 216 | regs.u.r8.al = val8; // val last written to Reg B
|
|---|
| 217 | ClearCF(iret_addr.flags); // OK
|
|---|
| 218 | break;
|
|---|
| 219 |
|
|---|
| 220 | case 4: // Read CMOS Date
|
|---|
| 221 | regs.u.r8.ah = 0;
|
|---|
| 222 | if (rtc_updating()) {
|
|---|
| 223 | SetCF(iret_addr.flags);
|
|---|
| 224 | break;
|
|---|
| 225 | }
|
|---|
| 226 | regs.u.r8.cl = inb_cmos(0x09); // Year
|
|---|
| 227 | regs.u.r8.dh = inb_cmos(0x08); // Month
|
|---|
| 228 | regs.u.r8.dl = inb_cmos(0x07); // Day of Month
|
|---|
| 229 | regs.u.r8.ch = inb_cmos(0x32); // Century
|
|---|
| 230 | regs.u.r8.al = regs.u.r8.ch;
|
|---|
| 231 | ClearCF(iret_addr.flags); // OK
|
|---|
| 232 | break;
|
|---|
| 233 |
|
|---|
| 234 | case 5: // Set CMOS Date
|
|---|
| 235 | // Using a debugger, I notice the following masking/setting
|
|---|
| 236 | // of bits in Status Register B, by setting Reg B to
|
|---|
| 237 | // a few values and getting its value after INT 1A was called.
|
|---|
| 238 | //
|
|---|
| 239 | // try#1 try#2 try#3 try#4
|
|---|
| 240 | // before 1111 1101 0111 1101 0000 0010 0000 0000
|
|---|
| 241 | // after 0110 1101 0111 1101 0000 0010 0000 0000
|
|---|
| 242 | //
|
|---|
| 243 | // Bit4 in try#1 flipped in hardware (forced low) due to bit7=1
|
|---|
| 244 | // My assumption: RegB = (RegB & 01111111b)
|
|---|
| 245 | if (rtc_updating()) {
|
|---|
| 246 | init_rtc();
|
|---|
| 247 | SetCF(iret_addr.flags);
|
|---|
| 248 | break;
|
|---|
| 249 | }
|
|---|
| 250 | outb_cmos(0x09, regs.u.r8.cl); // Year
|
|---|
| 251 | outb_cmos(0x08, regs.u.r8.dh); // Month
|
|---|
| 252 | outb_cmos(0x07, regs.u.r8.dl); // Day of Month
|
|---|
| 253 | outb_cmos(0x32, regs.u.r8.ch); // Century
|
|---|
| 254 | val8 = inb_cmos(0x0b) & 0x7f; // clear halt-clock bit
|
|---|
| 255 | outb_cmos(0x0b, val8);
|
|---|
| 256 | regs.u.r8.ah = 0;
|
|---|
| 257 | regs.u.r8.al = val8; // AL = val last written to Reg B
|
|---|
| 258 | ClearCF(iret_addr.flags); // OK
|
|---|
| 259 | break;
|
|---|
| 260 |
|
|---|
| 261 | case 6: // Set Alarm Time in CMOS
|
|---|
| 262 | // Using a debugger, I notice the following masking/setting
|
|---|
| 263 | // of bits in Status Register B, by setting Reg B to
|
|---|
| 264 | // a few values and getting its value after INT 1A was called.
|
|---|
| 265 | //
|
|---|
| 266 | // try#1 try#2 try#3
|
|---|
| 267 | // before 1101 1111 0101 1111 0000 0000
|
|---|
| 268 | // after 0110 1111 0111 1111 0010 0000
|
|---|
| 269 | //
|
|---|
| 270 | // Bit4 in try#1 flipped in hardware (forced low) due to bit7=1
|
|---|
| 271 | // My assumption: RegB = ((RegB & 01111111b) | 00100000b)
|
|---|
| 272 | val8 = inb_cmos(0x0b); // Get Status Reg B
|
|---|
| 273 | regs.u.r16.ax = 0;
|
|---|
| 274 | if (val8 & 0x20) {
|
|---|
| 275 | // Alarm interrupt enabled already
|
|---|
| 276 | SetCF(iret_addr.flags); // Error: alarm in use
|
|---|
| 277 | break;
|
|---|
| 278 | }
|
|---|
| 279 | if (rtc_updating()) {
|
|---|
| 280 | init_rtc();
|
|---|
| 281 | // fall through as if an update were not in progress
|
|---|
| 282 | }
|
|---|
| 283 | outb_cmos(0x01, regs.u.r8.dh); // Seconds alarm
|
|---|
| 284 | outb_cmos(0x03, regs.u.r8.cl); // Minutes alarm
|
|---|
| 285 | outb_cmos(0x05, regs.u.r8.ch); // Hours alarm
|
|---|
| 286 | outb(0xa1, inb(0xa1) & 0xfe); // enable IRQ 8
|
|---|
| 287 | // enable Status Reg B alarm bit, clear halt clock bit
|
|---|
| 288 | outb_cmos(0x0b, (val8 & 0x7f) | 0x20);
|
|---|
| 289 | ClearCF(iret_addr.flags); // OK
|
|---|
| 290 | break;
|
|---|
| 291 |
|
|---|
| 292 | case 7: // Turn off Alarm
|
|---|
| 293 | // Using a debugger, I notice the following masking/setting
|
|---|
| 294 | // of bits in Status Register B, by setting Reg B to
|
|---|
| 295 | // a few values and getting its value after INT 1A was called.
|
|---|
| 296 | //
|
|---|
| 297 | // try#1 try#2 try#3 try#4
|
|---|
| 298 | // before 1111 1101 0111 1101 0010 0000 0010 0010
|
|---|
| 299 | // after 0100 0101 0101 0101 0000 0000 0000 0010
|
|---|
| 300 | //
|
|---|
| 301 | // Bit4 in try#1 flipped in hardware (forced low) due to bit7=1
|
|---|
| 302 | // My assumption: RegB = (RegB & 01010111b)
|
|---|
| 303 | val8 = inb_cmos(0x0b); // Get Status Reg B
|
|---|
| 304 | // clear clock-halt bit, disable alarm bit
|
|---|
| 305 | outb_cmos(0x0b, val8 & 0x57); // disable alarm bit
|
|---|
| 306 | regs.u.r8.ah = 0;
|
|---|
| 307 | regs.u.r8.al = val8; // val last written to Reg B
|
|---|
| 308 | ClearCF(iret_addr.flags); // OK
|
|---|
| 309 | break;
|
|---|
| 310 |
|
|---|
| 311 | default:
|
|---|
| 312 | BX_DEBUG_INT1A("int1a: AX=%04x unsupported\n", regs.u.r16.ax);
|
|---|
| 313 | SetCF(iret_addr.flags); // Unsupported
|
|---|
| 314 | }
|
|---|
| 315 | }
|
|---|
