| 1 | /* $Id: post.c 93115 2022-01-01 11:31:46Z vboxsync $ */
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| 2 | /** @file
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| 3 | * BIOS POST routines. Used only during initialization.
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| 4 | */
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| 5 |
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| 6 | /*
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| 7 | * Copyright (C) 2004-2022 Oracle Corporation
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| 8 | *
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| 9 | * This file is part of VirtualBox Open Source Edition (OSE), as
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| 10 | * available from http://www.virtualbox.org. This file is free software;
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| 11 | * you can redistribute it and/or modify it under the terms of the GNU
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| 12 | * General Public License (GPL) as published by the Free Software
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| 13 | * Foundation, in version 2 as it comes in the "COPYING" file of the
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| 14 | * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
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| 15 | * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
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| 16 | */
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| 17 |
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| 18 | #include <stdint.h>
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| 19 | #include <string.h>
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| 20 | #include "biosint.h"
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| 21 | #include "inlines.h"
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| 22 |
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| 23 | #if DEBUG_POST
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| 24 | # define DPRINT(...) BX_DEBUG(__VA_ARGS__)
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| 25 | #else
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| 26 | # define DPRINT(...)
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| 27 | #endif
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| 28 |
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| 29 | /* In general, checksumming ROMs in a VM just wastes time. */
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| 30 | //#define CHECKSUM_ROMS
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| 31 |
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| 32 | /* The format of a ROM is as follows:
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| 33 | *
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| 34 | * ------------------------------
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| 35 | * 0 | AA55h signature (word) |
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| 36 | * ------------------------------
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| 37 | * 2 | Size in 512B blocks (byte) |
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| 38 | * ------------------------------
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| 39 | * 3 | Start of executable code |
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| 40 | * | ....... |
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| 41 | * end | |
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| 42 | * ------------------------------
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| 43 | */
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| 44 |
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| 45 | typedef struct rom_hdr_tag {
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| 46 | uint16_t signature;
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| 47 | uint8_t num_blks;
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| 48 | uint8_t code;
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| 49 | } rom_hdr;
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| 50 |
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| 51 |
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| 52 | /* Calculate the checksum of a ROM. Note that the ROM might be
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| 53 | * larger than 64K.
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| 54 | */
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| 55 | static inline uint8_t rom_checksum(uint8_t __far *rom, uint8_t blocks)
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| 56 | {
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| 57 | uint8_t sum = 0;
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| 58 |
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| 59 | #ifdef CHECKSUM_ROMS
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| 60 | while (blocks--) {
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| 61 | int i;
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| 62 |
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| 63 | for (i = 0; i < 512; ++i)
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| 64 | sum += rom[i];
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| 65 | /* Add 512 bytes (32 paragraphs) to segment. */
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| 66 | rom = MK_FP(FP_SEG(rom) + (512 >> 4), 0);
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| 67 | }
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| 68 | #endif
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| 69 | return sum;
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| 70 | }
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| 71 |
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| 72 | /* The ROM init routine might trash register. Give the compiler a heads-up. */
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| 73 | typedef void (rom_init_rtn)(void);
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| 74 | #pragma aux rom_init_rtn modify [ax bx cx dx si di es] loadds;
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| 75 |
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| 76 | /* Scan for ROMs in the given range and execute their POST code. */
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| 77 | void rom_scan(uint16_t start_seg, uint16_t end_seg)
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| 78 | {
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| 79 | rom_hdr __far *rom;
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| 80 | uint8_t rom_blks;
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| 81 |
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| 82 | DPRINT("Scanning for ROMs in %04X-%04X range\n", start_seg, end_seg);
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| 83 |
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| 84 | while (start_seg < end_seg) {
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| 85 | rom = MK_FP(start_seg, 0);
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| 86 | /* Check for the ROM signature. */
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| 87 | if (rom->signature == 0xAA55) {
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| 88 | DPRINT("Found ROM at segment %04X\n", start_seg);
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| 89 | if (!rom_checksum((void __far *)rom, rom->num_blks)) {
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| 90 | rom_init_rtn __far *rom_init;
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| 91 |
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| 92 | /* Checksum good, initialize ROM. */
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| 93 | rom_init = (void __far *)&rom->code;
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| 94 | rom_init();
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| 95 | int_disable();
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| 96 | DPRINT("ROM initialized\n");
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| 97 |
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| 98 | /* Continue scanning past the end of this ROM. */
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| 99 | rom_blks = (rom->num_blks + 3) & ~3; /* 4 blocks = 2K */
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| 100 | start_seg += rom_blks / 4;
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| 101 | }
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| 102 | } else {
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| 103 | /* Scanning is done in 2K steps. */
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| 104 | start_seg += 2048 >> 4;
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| 105 | }
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| 106 | }
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| 107 | }
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| 108 |
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| 109 | #if VBOX_BIOS_CPU >= 80386
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| 110 |
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| 111 | /* NB: The CPUID detection is generic but currently not used elsewhere. */
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| 112 |
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| 113 | /* Check CPUID availability. */
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| 114 | int is_cpuid_supported( void )
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| 115 | {
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| 116 | uint32_t old_flags, new_flags;
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| 117 |
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| 118 | old_flags = eflags_read();
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| 119 | new_flags = old_flags ^ (1L << 21); /* Toggle CPUID bit. */
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| 120 | eflags_write( new_flags );
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| 121 | new_flags = eflags_read();
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| 122 | return( old_flags != new_flags ); /* Supported if bit changed. */
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| 123 | }
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| 124 |
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| 125 | #define APICMODE_DISABLED 0
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| 126 | #define APICMODE_APIC 1
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| 127 | #define APICMODE_X2APIC 2
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| 128 |
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| 129 | #define APIC_BASE_MSR 0x1B
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| 130 | #define APICBASE_X2APIC 0x400 /* bit 10 */
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| 131 | #define APICBASE_ENABLE 0x800 /* bit 11 */
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| 132 |
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| 133 | /*
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| 134 | * Set up APIC/x2APIC. See also DevPcBios.cpp.
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| 135 | *
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| 136 | * NB: Virtual wire compatibility is set up earlier in 32-bit protected
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| 137 | * mode assembler (because it needs to access MMIO just under 4GB).
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| 138 | * Switching to x2APIC mode or disabling the APIC is done through an MSR
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| 139 | * and needs no 32-bit addressing. Going to x2APIC mode does not lose the
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| 140 | * existing virtual wire setup.
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| 141 | *
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| 142 | * NB: This code does not assume that there is a local APIC. It is necessary
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| 143 | * to check CPUID whether APIC is present; the CPUID instruction might not be
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| 144 | * available either.
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| 145 | *
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| 146 | * NB: Destroys high bits of 32-bit registers.
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| 147 | */
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| 148 | void BIOSCALL apic_setup(void)
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| 149 | {
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| 150 | uint64_t base_msr;
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| 151 | uint16_t mask_set;
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| 152 | uint16_t mask_clr;
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| 153 | uint8_t apic_mode;
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| 154 | uint32_t cpu_id[4];
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| 155 |
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| 156 | /* If there's no CPUID, there's certainly no APIC. */
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| 157 | if (!is_cpuid_supported()) {
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| 158 | return;
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| 159 | }
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| 160 |
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| 161 | /* Check EDX bit 9 */
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| 162 | cpuid(&cpu_id, 1);
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| 163 | BX_DEBUG("CPUID EDX: 0x%lx\n", cpu_id[3]);
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| 164 | if ((cpu_id[3] & (1 << 9)) == 0) {
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| 165 | return; /* No local APIC, nothing to do. */
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| 166 | }
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| 167 |
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| 168 | /* APIC mode at offset 78h in CMOS NVRAM. */
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| 169 | apic_mode = inb_cmos(0x78);
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| 170 |
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| 171 | mask_set = mask_clr = 0;
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| 172 | if (apic_mode == APICMODE_X2APIC)
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| 173 | mask_set = APICBASE_X2APIC;
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| 174 | else if (apic_mode == APICMODE_DISABLED)
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| 175 | mask_clr = APICBASE_ENABLE;
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| 176 | else
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| 177 | ; /* Any other setting leaves things alone. */
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| 178 |
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| 179 | if (mask_set || mask_clr) {
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| 180 | base_msr = msr_read(APIC_BASE_MSR);
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| 181 | base_msr &= ~(uint64_t)mask_clr;
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| 182 | base_msr |= mask_set;
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| 183 | msr_write(base_msr, APIC_BASE_MSR);
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| 184 | }
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| 185 | }
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| 186 |
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| 187 | #endif
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