| 1 | /* $Id: post.c 98103 2023-01-17 14:15:46Z vboxsync $ */
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| 2 | /** @file
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| 3 | * BIOS POST routines. Used only during initialization.
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| 4 | */
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| 5 |
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| 6 | /*
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| 7 | * Copyright (C) 2004-2023 Oracle and/or its affiliates.
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| 8 | *
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| 9 | * This file is part of VirtualBox base platform packages, as
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| 10 | * available from https://www.virtualbox.org.
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| 11 | *
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| 12 | * This program is free software; you can redistribute it and/or
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| 13 | * modify it under the terms of the GNU General Public License
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| 14 | * as published by the Free Software Foundation, in version 3 of the
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| 15 | * License.
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| 16 | *
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| 17 | * This program is distributed in the hope that it will be useful, but
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| 18 | * WITHOUT ANY WARRANTY; without even the implied warranty of
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| 19 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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| 20 | * General Public License for more details.
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| 21 | *
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| 22 | * You should have received a copy of the GNU General Public License
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| 23 | * along with this program; if not, see <https://www.gnu.org/licenses>.
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| 24 | *
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| 25 | * SPDX-License-Identifier: GPL-3.0-only
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| 26 | */
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| 27 |
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| 28 | #include <stdint.h>
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| 29 | #include <string.h>
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| 30 | #include "biosint.h"
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| 31 | #include "inlines.h"
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| 32 |
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| 33 | #if DEBUG_POST || 0
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| 34 | # define DPRINT(...) BX_DEBUG(__VA_ARGS__)
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| 35 | #else
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| 36 | # define DPRINT(...)
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| 37 | #endif
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| 38 |
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| 39 | /* In general, checksumming ROMs in a VM just wastes time. */
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| 40 | //#define CHECKSUM_ROMS
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| 41 |
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| 42 | /* The format of a ROM is as follows:
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| 43 | *
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| 44 | * ------------------------------
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| 45 | * 0 | AA55h signature (word) |
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| 46 | * ------------------------------
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| 47 | * 2 | Size in 512B blocks (byte) |
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| 48 | * ------------------------------
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| 49 | * 3 | Start of executable code |
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| 50 | * | ....... |
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| 51 | * end | |
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| 52 | * ------------------------------
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| 53 | */
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| 54 |
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| 55 | typedef struct rom_hdr_tag {
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| 56 | uint16_t signature;
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| 57 | uint8_t num_blks;
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| 58 | uint8_t code;
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| 59 | } rom_hdr;
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| 60 |
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| 61 |
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| 62 | /* Calculate the checksum of a ROM. Note that the ROM might be
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| 63 | * larger than 64K.
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| 64 | */
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| 65 | static inline uint8_t rom_checksum(uint8_t __far *rom, uint8_t blocks)
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| 66 | {
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| 67 | uint8_t sum = 0;
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| 68 |
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| 69 | #ifdef CHECKSUM_ROMS
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| 70 | while (blocks--) {
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| 71 | int i;
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| 72 |
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| 73 | for (i = 0; i < 512; ++i)
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| 74 | sum += rom[i];
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| 75 | /* Add 512 bytes (32 paragraphs) to segment. */
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| 76 | rom = MK_FP(FP_SEG(rom) + (512 >> 4), 0);
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| 77 | }
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| 78 | #endif
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| 79 | return sum;
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| 80 | }
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| 81 |
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| 82 | /* The ROM init routine might trash register. Give the compiler a heads-up. */
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| 83 | typedef void __far (rom_init_rtn)(void);
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| 84 | #pragma aux rom_init_rtn modify [ax bx cx dx si di es /*ignored:*/ bp] /*ignored:*/ loadds;
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| 85 |
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| 86 | /* The loadds bit is ignored for rom_init_rtn, the impression from the code
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| 87 | generator is that this is due to using a memory model where DS is fixed.
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| 88 | If we add DS as a modified register, we'll get run into compiler error
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| 89 | E1122 (BAD_REG) because FixedRegs() in cg/intel/386/c/386rgtbl.c returns
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| 90 | HW_DS as part of the fixed register set that cannot be modified.
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| 91 |
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| 92 | The problem of the vga bios trashing DS isn't a biggie, except when
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| 93 | something goes sideways before we can reload it. Setting a I/O port
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| 94 | breakpoint on port 80h and wait a while before resuming execution
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| 95 | (ba i 1 80 "sleep 400 ; g") will usually trigger a keyboard init panic and
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| 96 | showcase the issue. The panic message is garbage because it's read from
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| 97 | segment 0c000h instead of 0f000h. */
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| 98 | static void restore_ds_as_dgroup(void);
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| 99 | #pragma aux restore_ds_as_dgroup = \
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| 100 | "mov ax, 0f000h" \
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| 101 | "mov ds, ax" \
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| 102 | modify exact [ax];
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| 103 |
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| 104 |
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| 105 | /* Scan for ROMs in the given range and execute their POST code. */
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| 106 | void rom_scan(uint16_t start_seg, uint16_t end_seg)
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| 107 | {
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| 108 | rom_hdr __far *rom;
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| 109 | uint8_t rom_blks;
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| 110 |
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| 111 | DPRINT("Scanning for ROMs in %04X-%04X range\n", start_seg, end_seg);
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| 112 |
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| 113 | while (start_seg < end_seg) {
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| 114 | rom = MK_FP(start_seg, 0);
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| 115 | /* Check for the ROM signature. */
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| 116 | if (rom->signature == 0xAA55) {
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| 117 | DPRINT("Found ROM at segment %04X\n", start_seg);
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| 118 | if (!rom_checksum((void __far *)rom, rom->num_blks)) {
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| 119 | rom_init_rtn *rom_init;
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| 120 |
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| 121 | /* Checksum good, initialize ROM. */
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| 122 | rom_init = (rom_init_rtn *)&rom->code;
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| 123 | rom_init();
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| 124 | int_disable();
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| 125 | restore_ds_as_dgroup();
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| 126 | /** @todo BP is not restored. */
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| 127 | DPRINT("ROM initialized\n");
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| 128 |
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| 129 | /* Continue scanning past the end of this ROM. */
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| 130 | rom_blks = (rom->num_blks + 3) & ~3; /* 4 blocks = 2K */
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| 131 | start_seg += rom_blks / 4;
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| 132 | }
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| 133 | } else {
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| 134 | /* Scanning is done in 2K steps. */
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| 135 | start_seg += 2048 >> 4;
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| 136 | }
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| 137 | }
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| 138 | }
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| 139 |
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| 140 | #if VBOX_BIOS_CPU >= 80386
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| 141 |
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| 142 | /* NB: The CPUID detection is generic but currently not used elsewhere. */
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| 143 |
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| 144 | /* Check CPUID availability. */
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| 145 | int is_cpuid_supported( void )
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| 146 | {
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| 147 | uint32_t old_flags, new_flags;
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| 148 |
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| 149 | old_flags = eflags_read();
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| 150 | new_flags = old_flags ^ (1L << 21); /* Toggle CPUID bit. */
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| 151 | eflags_write( new_flags );
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| 152 | new_flags = eflags_read();
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| 153 | return( old_flags != new_flags ); /* Supported if bit changed. */
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| 154 | }
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| 155 |
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| 156 | #define APICMODE_DISABLED 0
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| 157 | #define APICMODE_APIC 1
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| 158 | #define APICMODE_X2APIC 2
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| 159 |
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| 160 | #define APIC_BASE_MSR 0x1B
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| 161 | #define APICBASE_X2APIC 0x400 /* bit 10 */
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| 162 | #define APICBASE_ENABLE 0x800 /* bit 11 */
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| 163 |
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| 164 | /*
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| 165 | * Set up APIC/x2APIC. See also DevPcBios.cpp.
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| 166 | *
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| 167 | * NB: Virtual wire compatibility is set up earlier in 32-bit protected
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| 168 | * mode assembler (because it needs to access MMIO just under 4GB).
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| 169 | * Switching to x2APIC mode or disabling the APIC is done through an MSR
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| 170 | * and needs no 32-bit addressing. Going to x2APIC mode does not lose the
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| 171 | * existing virtual wire setup.
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| 172 | *
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| 173 | * NB: This code does not assume that there is a local APIC. It is necessary
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| 174 | * to check CPUID whether APIC is present; the CPUID instruction might not be
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| 175 | * available either.
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| 176 | *
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| 177 | * NB: Destroys high bits of 32-bit registers.
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| 178 | */
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| 179 | void BIOSCALL apic_setup(void)
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| 180 | {
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| 181 | uint64_t base_msr;
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| 182 | uint16_t mask_set;
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| 183 | uint16_t mask_clr;
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| 184 | uint8_t apic_mode;
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| 185 | uint32_t cpu_id[4];
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| 186 |
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| 187 | /* If there's no CPUID, there's certainly no APIC. */
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| 188 | if (!is_cpuid_supported()) {
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| 189 | return;
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| 190 | }
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| 191 |
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| 192 | /* Check EDX bit 9 */
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| 193 | cpuid(&cpu_id, 1);
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| 194 | BX_DEBUG("CPUID EDX: 0x%lx\n", cpu_id[3]);
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| 195 | if ((cpu_id[3] & (1 << 9)) == 0) {
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| 196 | return; /* No local APIC, nothing to do. */
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| 197 | }
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| 198 |
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| 199 | /* APIC mode at offset 78h in CMOS NVRAM. */
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| 200 | apic_mode = inb_cmos(0x78);
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| 201 |
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| 202 | mask_set = mask_clr = 0;
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| 203 | if (apic_mode == APICMODE_X2APIC)
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| 204 | mask_set = APICBASE_X2APIC;
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| 205 | else if (apic_mode == APICMODE_DISABLED)
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| 206 | mask_clr = APICBASE_ENABLE;
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| 207 | else
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| 208 | ; /* Any other setting leaves things alone. */
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| 209 |
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| 210 | if (mask_set || mask_clr) {
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| 211 | base_msr = msr_read(APIC_BASE_MSR);
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| 212 | base_msr &= ~(uint64_t)mask_clr;
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| 213 | base_msr |= mask_set;
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| 214 | msr_write(base_msr, APIC_BASE_MSR);
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| 215 | }
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| 216 | }
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| 217 |
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| 218 | #endif
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