ne2000.c@ 61

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1	#ifdef VBOX
2	/** @file
3	*
4	* VBox network devices:
5	* NE2000 ethernet controller
6	*/
7
8	/*
9	* Copyright (C) 2006 InnoTek Systemberatung GmbH
10	*
11	* This file is part of VirtualBox Open Source Edition (OSE), as
12	* available from http://www.virtualbox.org. This file is free software;
13	* you can redistribute it and/or modify it under the terms of the GNU
14	* General Public License as published by the Free Software Foundation,
15	* in version 2 as it comes in the "COPYING" file of the VirtualBox OSE
16	* distribution. VirtualBox OSE is distributed in the hope that it will
17	* be useful, but WITHOUT ANY WARRANTY of any kind.
18	*
19	* If you received this file as part of a commercial VirtualBox
20	* distribution, then only the terms of your commercial VirtualBox
21	* license agreement apply instead of the previous paragraph.
22	*
23	* --------------------------------------------------------------------
24	*
25	* This code is based on:
26	*
27	* QEMU NE2000 emulation
28	*
29	* Copyright (c) 2003-2004 Fabrice Bellard
30	*
31	* Permission is hereby granted, free of charge, to any person obtaining a copy
32	* of this software and associated documentation files (the "Software"), to deal
33	* in the Software without restriction, including without limitation the rights
34	* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
35	* copies of the Software, and to permit persons to whom the Software is
36	* furnished to do so, subject to the following conditions:
37	*
38	* The above copyright notice and this permission notice shall be included in
39	* all copies or substantial portions of the Software.
40	*
41	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
42	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
43	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
44	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
45	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
46	* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
47	* THE SOFTWARE.
48	*/
49
50
51	/*******************************************************************************
52	* Header Files *
53	*******************************************************************************/
54	#define LOG_GROUP LOG_GROUP_DEV_NE2000
55	#include <VBox/pdm.h>
56	#include <VBox/err.h>
57
58	#include <VBox/log.h>
59	#include <iprt/assert.h>
60	#include <iprt/uuid.h>
61	#include <iprt/string.h>
62	#include <iprt/alloc.h>
63
64	#include "Builtins.h"
65	#include "vl_vbox.h"
66
67	#endif /* VBOX */
68
69	#ifndef VBOX
70	#include "vl.h"
71	#endif
72
73	#define ETHER_ADDR_LEN ETH_ALEN
74	#define ETH_ALEN 6
75	#undef bcmp
76	#define bcmp(b1,b2,len) memcmp((b1), (b2), (size_t)(len))
77	#pragma pack(1)
78	struct ether_header
79	{
80	uint8_t ether_dhost[ETH_ALEN]; /* destination ethernet address */
81	uint8_t ether_shost[ETH_ALEN]; /* source ethernet address */
82	uint16_t ether_type; /* packet type ID field */
83	};
84	#pragma pack()
85	#undef htonl
86	#define htonl(x) ( (((x) & 0xff000000) >> 24) \| (((x) & 0x00ff0000) >> 8) \| \
87	(((x) & 0x0000ff00) << 8) \| (((x) & 0x000000ff) << 24) )
88	#undef htons
89	#define htons(x) ( (((x) & 0xff00) >> 8) \| (((x) & 0x00ff) << 8) )
90
91	/* debug NE2000 card */
92	#define DEBUG_NE2000
93
94	#define MAX_ETH_FRAME_SIZE 1514
95
96	#define E8390_CMD 0x00 /* The command register (for all pages) */
97	/* Page 0 register offsets. */
98	#define EN0_CLDALO 0x01 /* Low byte of current local dma addr RD */
99	#define EN0_STARTPG 0x01 /* Starting page of ring bfr WR */
100	#define EN0_CLDAHI 0x02 /* High byte of current local dma addr RD */
101	#define EN0_STOPPG 0x02 /* Ending page +1 of ring bfr WR */
102	#define EN0_BOUNDARY 0x03 /* Boundary page of ring bfr RD WR */
103	#define EN0_TSR 0x04 /* Transmit status reg RD */
104	#define EN0_TPSR 0x04 /* Transmit starting page WR */
105	#define EN0_NCR 0x05 /* Number of collision reg RD */
106	#define EN0_TCNTLO 0x05 /* Low byte of tx byte count WR */
107	#define EN0_FIFO 0x06 /* FIFO RD */
108	#define EN0_TCNTHI 0x06 /* High byte of tx byte count WR */
109	#define EN0_ISR 0x07 /* Interrupt status reg RD WR */
110	#define EN0_CRDALO 0x08 /* low byte of current remote dma address RD */
111	#define EN0_RSARLO 0x08 /* Remote start address reg 0 */
112	#define EN0_CRDAHI 0x09 /* high byte, current remote dma address RD */
113	#define EN0_RSARHI 0x09 /* Remote start address reg 1 */
114	#define EN0_RCNTLO 0x0a /* Remote byte count reg WR */
115	#define EN0_RCNTHI 0x0b /* Remote byte count reg WR */
116	#define EN0_RSR 0x0c /* rx status reg RD */
117	#define EN0_RXCR 0x0c /* RX configuration reg WR */
118	#define EN0_TXCR 0x0d /* TX configuration reg WR */
119	#define EN0_COUNTER0 0x0d /* Rcv alignment error counter RD */
120	#define EN0_DCFG 0x0e /* Data configuration reg WR */
121	#define EN0_COUNTER1 0x0e /* Rcv CRC error counter RD */
122	#define EN0_IMR 0x0f /* Interrupt mask reg WR */
123	#define EN0_COUNTER2 0x0f /* Rcv missed frame error counter RD */
124
125	#define EN1_PHYS 0x11
126	#define EN1_CURPAG 0x17
127	#define EN1_MULT 0x18
128
129	#define EN2_STARTPG 0x21 /* Starting page of ring bfr RD */
130	#define EN2_STOPPG 0x22 /* Ending page +1 of ring bfr RD */
131
132	/* Register accessed at EN_CMD, the 8390 base addr. */
133	#define E8390_STOP 0x01 /* Stop and reset the chip */
134	#define E8390_START 0x02 /* Start the chip, clear reset */
135	#define E8390_TRANS 0x04 /* Transmit a frame */
136	#define E8390_RREAD 0x08 /* Remote read */
137	#define E8390_RWRITE 0x10 /* Remote write */
138	#define E8390_NODMA 0x20 /* Remote DMA */
139	#define E8390_PAGE0 0x00 /* Select page chip registers */
140	#define E8390_PAGE1 0x40 /* using the two high-order bits */
141	#define E8390_PAGE2 0x80 /* Page 3 is invalid. */
142
143	/* Bits in EN0_ISR - Interrupt status register */
144	#define ENISR_RX 0x01 /* Receiver, no error */
145	#define ENISR_TX 0x02 /* Transmitter, no error */
146	#define ENISR_RX_ERR 0x04 /* Receiver, with error */
147	#define ENISR_TX_ERR 0x08 /* Transmitter, with error */
148	#define ENISR_OVER 0x10 /* Receiver overwrote the ring */
149	#define ENISR_COUNTERS 0x20 /* Counters need emptying */
150	#define ENISR_RDC 0x40 /* remote dma complete */
151	#define ENISR_RESET 0x80 /* Reset completed */
152	#define ENISR_ALL 0x3f /* Interrupts we will enable */
153
154	/* Bits in received packet status byte and EN0_RSR*/
155	#define ENRSR_RXOK 0x01 /* Received a good packet */
156	#define ENRSR_CRC 0x02 /* CRC error */
157	#define ENRSR_FAE 0x04 /* frame alignment error */
158	#define ENRSR_FO 0x08 /* FIFO overrun */
159	#define ENRSR_MPA 0x10 /* missed pkt */
160	#define ENRSR_PHY 0x20 /* physical/multicast address */
161	#define ENRSR_DIS 0x40 /* receiver disable. set in monitor mode */
162	#define ENRSR_DEF 0x80 /* deferring */
163
164	/* Transmitted packet status, EN0_TSR. */
165	#define ENTSR_PTX 0x01 /* Packet transmitted without error */
166	#define ENTSR_ND 0x02 /* The transmit wasn't deferred. */
167	#define ENTSR_COL 0x04 /* The transmit collided at least once. */
168	#define ENTSR_ABT 0x08 /* The transmit collided 16 times, and was deferred. */
169	#define ENTSR_CRS 0x10 /* The carrier sense was lost. */
170	#define ENTSR_FU 0x20 /* A "FIFO underrun" occurred during transmit. */
171	#define ENTSR_CDH 0x40 /* The collision detect "heartbeat" signal was lost. */
172	#define ENTSR_OWC 0x80 /* There was an out-of-window collision. */
173
174	#define NE2000_PMEM_SIZE (32*1024)
175	#define NE2000_PMEM_START (16*1024)
176	#define NE2000_PMEM_END (NE2000_PMEM_SIZE+NE2000_PMEM_START)
177	#define NE2000_MEM_SIZE NE2000_PMEM_END
178
179	typedef struct NE2000State {
180	#ifdef VBOX
181	PCIDevice dev;
182	#endif
183	uint8_t cmd;
184	uint32_t start;
185	uint32_t stop;
186	uint8_t boundary;
187	uint8_t tsr;
188	uint8_t tpsr;
189	uint16_t tcnt;
190	uint16_t rcnt;
191	uint32_t rsar;
192	uint8_t rsr;
193	uint8_t isr;
194	uint8_t dcfg;
195	uint8_t imr;
196	uint8_t phys[6]; /* mac address */
197	uint8_t curpag;
198	uint8_t mult[8]; /* multicast mask array */
199	int irq;
200	#ifndef VBOX
201	PCIDevice *pci_dev;
202
203	NetDriverState *nd;
204	#else
205	/** Restore timer.
206	* This is used to disconnect and reconnect the link after a restore. */
207	PTMTIMER pTimerRestore;
208	/** Pointer to the device instance. */
209	PPDMDEVINS pDevIns;
210	/** Pointer to the connector of the attached network driver. */
211	PPDMINETWORKCONNECTOR pDrv;
212	/** Pointer to the attached network driver. */
213	PPDMIBASE pDrvBase;
214	/** The base interface. */
215	PDMIBASE IBase;
216	/** The network port interface. */
217	PDMINETWORKPORT INetworkPort;
218	/** The network config port interface. */
219	PDMINETWORKCONFIG INetworkConfig;
220	/** Base port of the I/O space region. */
221	RTIOPORT IOPortBase;
222	/** If set the link is temporarily down because of a saved state load. */
223	bool fLinkTempDown;
224	/** Number of times we've reported the link down. */
225	RTUINT cLinkDownReported;
226	/** The configured MAC address. */
227	PDMMAC MacConfigured;
228
229	/** The LED. */
230	PDMLED Led;
231	/** The LED ports. */
232	PDMILEDPORTS ILeds;
233	/** Partner of ILeds. */
234	PPDMILEDCONNECTORS pLedsConnector;
235	#endif
236
237	uint8_t mem[NE2000_MEM_SIZE];
238	} NE2000State;
239
240
241	#ifdef VBOX
242	#define NE2000STATE_2_DEVINS(pNE2000) ( (pNE2000)->pDevIns )
243	#define PCIDEV_2_NE2000STATE(pPciDev) ( (NE2000State *)(pPciDev) )
244	#endif /* VBOX */
245
246	static void ne2000_reset(NE2000State *s)
247	{
248	int i;
249
250	s->isr = ENISR_RESET;
251	#ifndef VBOX
252	memcpy(s->mem, s->nd->macaddr, 6);
253	#else /* VBOX */
254	Assert(sizeof(s->MacConfigured) == 6);
255	memcpy(s->mem, &s->MacConfigured, sizeof(s->MacConfigured));
256	#endif /* VBOX */
257	s->mem[14] = 0x57;
258	s->mem[15] = 0x57;
259
260	/* duplicate prom data */
261	for(i = 15;i >= 0; i--) {
262	s->mem[2 * i] = s->mem[i];
263	s->mem[2 * i + 1] = s->mem[i];
264	}
265	}
266
267	static void ne2000_update_irq(NE2000State *s)
268	{
269	#ifdef VBOX
270	PPDMDEVINS pDevIns = NE2000STATE_2_DEVINS(s);
271	#endif /* VBOX */
272	int isr;
273	isr = (s->isr & s->imr) & 0x7f;
274	#if defined(DEBUG_NE2000)
275	Log(("NE2000: Set IRQ line %d to %d (%02x %02x)\n",
276	s->irq, isr ? 1 : 0, s->isr, s->imr));
277	#endif
278	if (s->irq == 16) {
279	/* PCI irq */
280	#ifndef VBOX
281	pci_set_irq(s->pci_dev, 0, (isr != 0));
282	#else /* VBOX */
283	pDevIns->pDevHlp->pfnPCISetIrq(pDevIns, 0, (isr != 0));
284	#endif /* VBOX */
285	} else {
286	/* ISA irq */
287	#ifndef VBOX
288	pic_set_irq(s->irq, (isr != 0));
289	#else /* VBOX */
290	pDevIns->pDevHlp->pfnISASetIrq(pDevIns, 0, (isr != 0));
291	#endif /* VBOX */
292	}
293	}
294
295	/* return the max buffer size if the NE2000 can receive more data */
296	static int ne2000_can_receive(void *opaque)
297	{
298	NE2000State *s = opaque;
299	int avail, index, boundary;
300
301	if (s->cmd & E8390_STOP)
302	return 0;
303	index = s->curpag << 8;
304	boundary = s->boundary << 8;
305	if (index < boundary)
306	avail = boundary - index;
307	else
308	avail = (s->stop - s->start) - (index - boundary);
309	if (avail < (MAX_ETH_FRAME_SIZE + 4))
310	return 0;
311	return MAX_ETH_FRAME_SIZE;
312	}
313
314	#define MIN_BUF_SIZE 60
315
316	static void ne2000_receive(void opaque, const uint8_t buf, int size)
317	{
318	NE2000State *s = opaque;
319	uint8_t *p;
320	int total_len, next, avail, len, index;
321	uint8_t buf1[60];
322
323	#ifdef DEBUG_NE2000
324	Log(("NE2000: received len=%d\n", size));
325	#endif
326	/* if too small buffer, then expand it */
327	if (size < MIN_BUF_SIZE) {
328	memcpy(buf1, buf, size);
329	memset(buf1 + size, 0, MIN_BUF_SIZE - size);
330	buf = buf1;
331	size = MIN_BUF_SIZE;
332	}
333
334	index = s->curpag << 8;
335	/* 4 bytes for header */
336	total_len = size + 4;
337	/* address for next packet (4 bytes for CRC) */
338	next = index + ((total_len + 4 + 255) & ~0xff);
339	if (next >= s->stop)
340	next -= (s->stop - s->start);
341	/* prepare packet header */
342	p = s->mem + index;
343	s->rsr = ENRSR_RXOK; /* receive status */
344	/* XXX: check this */
345	if (buf[0] & 0x01)
346	s->rsr \|= ENRSR_PHY;
347	p[0] = s->rsr;
348	p[1] = next >> 8;
349	p[2] = total_len;
350	p[3] = total_len >> 8;
351	index += 4;
352
353	/* write packet data */
354	while (size > 0) {
355	avail = s->stop - index;
356	len = size;
357	if (len > avail)
358	len = avail;
359	memcpy(s->mem + index, buf, len);
360	buf += len;
361	index += len;
362	if (index == s->stop)
363	index = s->start;
364	size -= len;
365	}
366	s->curpag = next >> 8;
367
368	/* now we can signal we have receive something */
369	s->isr \|= ENISR_RX;
370	ne2000_update_irq(s);
371	}
372
373	static void ne2000_ioport_write(void *opaque, uint32_t addr, uint32_t val)
374	{
375	NE2000State *s = opaque;
376	int offset, page, index;
377
378	addr &= 0xf;
379	#ifdef DEBUG_NE2000
380	Log(("NE2000: write addr=0x%x val=0x%02x\n", addr, val));
381	#endif
382	if (addr == E8390_CMD) {
383	/* control register */
384	s->cmd = val;
385	if (!(val & E8390_STOP)) { /* START bit makes no sense on RTL8029... */
386	s->isr &= ~ENISR_RESET;
387	/* test specific case: zero length transfert */
388	if ((val & (E8390_RREAD \| E8390_RWRITE)) &&
389	s->rcnt == 0) {
390	s->isr \|= ENISR_RDC;
391	ne2000_update_irq(s);
392	}
393	if (val & E8390_TRANS) {
394	index = (s->tpsr << 8);
395	/* XXX: next 2 lines are a hack to make netware 3.11 work */
396	Assert(index < NE2000_PMEM_END);
397	if (index >= NE2000_PMEM_END)
398	index -= NE2000_PMEM_SIZE;
399	/* fail safe: check range on the transmitted length */
400	Assert(index + s->tcnt <= NE2000_PMEM_END);
401	if (index + s->tcnt <= NE2000_PMEM_END) {
402	#ifndef VBOX
403	qemu_send_packet(s->nd, s->mem + index, s->tcnt);
404	#else
405	if (s->tcnt > 70) /* unqualified guess */
406	s->Led.Asserted.s.fWriting = s->Led.Actual.s.fWriting = 1;
407	s->pDrv->pfnSend(s->pDrv, s->mem + index, s->tcnt);
408	s->Led.Actual.s.fWriting = 0;
409	#endif
410	}
411	/* signal end of transfert */
412	s->tsr = ENTSR_PTX;
413	s->isr \|= ENISR_TX;
414	s->cmd &= ~E8390_TRANS;
415	ne2000_update_irq(s);
416	}
417	}
418	} else {
419	page = s->cmd >> 6;
420	offset = addr \| (page << 4);
421	switch(offset) {
422	case EN0_STARTPG:
423	s->start = val << 8;
424	break;
425	case EN0_STOPPG:
426	s->stop = val << 8;
427	break;
428	case EN0_BOUNDARY:
429	s->boundary = val;
430	break;
431	case EN0_IMR:
432	s->imr = val;
433	ne2000_update_irq(s);
434	break;
435	case EN0_TPSR:
436	s->tpsr = val;
437	break;
438	case EN0_TCNTLO:
439	s->tcnt = (s->tcnt & 0xff00) \| val;
440	break;
441	case EN0_TCNTHI:
442	s->tcnt = (s->tcnt & 0x00ff) \| (val << 8);
443	break;
444	case EN0_RSARLO:
445	s->rsar = (s->rsar & 0xff00) \| val;
446	break;
447	case EN0_RSARHI:
448	s->rsar = (s->rsar & 0x00ff) \| (val << 8);
449	break;
450	case EN0_RCNTLO:
451	s->rcnt = (s->rcnt & 0xff00) \| val;
452	break;
453	case EN0_RCNTHI:
454	s->rcnt = (s->rcnt & 0x00ff) \| (val << 8);
455	break;
456	case EN0_DCFG:
457	s->dcfg = val;
458	break;
459	case EN0_ISR:
460	s->isr &= ~(val & 0x7f);
461	ne2000_update_irq(s);
462	break;
463	#ifdef VBOX
464	case EN1_PHYS:
465	case EN1_PHYS + 1:
466	case EN1_PHYS + 2:
467	case EN1_PHYS + 3:
468	case EN1_PHYS + 4:
469	case EN1_PHYS + 5:
470	#else
471	case EN1_PHYS ... EN1_PHYS + 5:
472	#endif
473	s->phys[offset - EN1_PHYS] = val;
474	break;
475	case EN1_CURPAG:
476	s->curpag = val;
477	break;
478	#ifdef VBOX
479	case EN1_MULT:
480	case EN1_MULT + 1:
481	case EN1_MULT + 2:
482	case EN1_MULT + 3:
483	case EN1_MULT + 4:
484	case EN1_MULT + 5:
485	case EN1_MULT + 6:
486	case EN1_MULT + 7:
487	#else
488	case EN1_MULT ... EN1_MULT + 7:
489	#endif
490	s->mult[offset - EN1_MULT] = val;
491	break;
492	}
493	}
494	}
495
496	static uint32_t ne2000_ioport_read(void *opaque, uint32_t addr)
497	{
498	NE2000State *s = opaque;
499	int offset, page, ret;
500
501	addr &= 0xf;
502	if (addr == E8390_CMD) {
503	ret = s->cmd;
504	} else {
505	page = s->cmd >> 6;
506	offset = addr \| (page << 4);
507	switch(offset) {
508	case EN0_TSR:
509	ret = s->tsr;
510	break;
511	case EN0_BOUNDARY:
512	ret = s->boundary;
513	break;
514	case EN0_ISR:
515	ret = s->isr;
516	break;
517	case EN0_RSARLO:
518	ret = s->rsar & 0x00ff;
519	break;
520	case EN0_RSARHI:
521	ret = s->rsar >> 8;
522	break;
523	#ifdef VBOX
524	case EN1_PHYS:
525	case EN1_PHYS + 1:
526	case EN1_PHYS + 2:
527	case EN1_PHYS + 3:
528	case EN1_PHYS + 4:
529	case EN1_PHYS + 5:
530	#else
531	case EN1_PHYS ... EN1_PHYS + 5:
532	#endif
533	ret = s->phys[offset - EN1_PHYS];
534	break;
535	case EN1_CURPAG:
536	ret = s->curpag;
537	break;
538	#ifdef VBOX
539	case EN1_MULT:
540	case EN1_MULT + 1:
541	case EN1_MULT + 2:
542	case EN1_MULT + 3:
543	case EN1_MULT + 4:
544	case EN1_MULT + 5:
545	case EN1_MULT + 6:
546	case EN1_MULT + 7:
547	#else
548	case EN1_MULT ... EN1_MULT + 7:
549	#endif
550	ret = s->mult[offset - EN1_MULT];
551	break;
552	case EN0_RSR:
553	ret = s->rsr;
554	break;
555	case EN2_STARTPG:
556	ret = s->start >> 8;
557	break;
558	case EN2_STOPPG:
559	ret = s->stop >> 8;
560	break;
561	default:
562	ret = 0x00;
563	break;
564	}
565	}
566	#ifdef DEBUG_NE2000
567	Log(("NE2000: read addr=0x%x val=%02x\n", addr, ret));
568	#endif
569	return ret;
570	}
571
572	static inline void ne2000_mem_writeb(NE2000State *s, uint32_t addr,
573	uint32_t val)
574	{
575	if (addr < 32 \|\|
576	(addr >= NE2000_PMEM_START && addr < NE2000_MEM_SIZE)) {
577	s->mem[addr] = val;
578	}
579	}
580
581	static inline void ne2000_mem_writew(NE2000State *s, uint32_t addr,
582	uint32_t val)
583	{
584	addr &= ~1; /* XXX: check exact behaviour if not even */
585	if (addr < 32 \|\|
586	(addr >= NE2000_PMEM_START && addr < NE2000_MEM_SIZE)) {
587	(uint16_t )(s->mem + addr) = cpu_to_le16(val);
588	}
589	}
590
591	static inline void ne2000_mem_writel(NE2000State *s, uint32_t addr,
592	uint32_t val)
593	{
594	addr &= ~1; /* XXX: check exact behaviour if not even */
595	if (addr < 32 \|\|
596	(addr >= NE2000_PMEM_START && addr < NE2000_MEM_SIZE)) {
597	cpu_to_le32wu((uint32_t *)(s->mem + addr), val);
598	}
599	}
600
601	static inline uint32_t ne2000_mem_readb(NE2000State *s, uint32_t addr)
602	{
603	if (addr < 32 \|\|
604	(addr >= NE2000_PMEM_START && addr < NE2000_MEM_SIZE)) {
605	return s->mem[addr];
606	} else {
607	return 0xff;
608	}
609	}
610
611	static inline uint32_t ne2000_mem_readw(NE2000State *s, uint32_t addr)
612	{
613	addr &= ~1; /* XXX: check exact behaviour if not even */
614	if (addr < 32 \|\|
615	(addr >= NE2000_PMEM_START && addr < NE2000_MEM_SIZE)) {
616	return le16_to_cpu((uint16_t )(s->mem + addr));
617	} else {
618	return 0xffff;
619	}
620	}
621
622	static inline uint32_t ne2000_mem_readl(NE2000State *s, uint32_t addr)
623	{
624	addr &= ~1; /* XXX: check exact behaviour if not even */
625	if (addr < 32 \|\|
626	(addr >= NE2000_PMEM_START && addr < NE2000_MEM_SIZE)) {
627	return le32_to_cpupu((uint32_t *)(s->mem + addr));
628	} else {
629	return 0xffffffff;
630	}
631	}
632
633	static inline void ne2000_dma_update(NE2000State *s, int len)
634	{
635	s->rsar += len;
636	/* wrap */
637	/* XXX: check what to do if rsar > stop */
638	if (s->rsar == s->stop)
639	s->rsar = s->start;
640
641	if (s->rcnt <= len) {
642	s->rcnt = 0;
643	/* signal end of transfert */
644	s->isr \|= ENISR_RDC;
645	ne2000_update_irq(s);
646	} else {
647	s->rcnt -= len;
648	}
649	}
650
651	static void ne2000_asic_ioport_write(void *opaque, uint32_t addr, uint32_t val)
652	{
653	NE2000State *s = opaque;
654
655	#ifdef DEBUG_NE2000
656	Log(("NE2000: asic write val=0x%04x\n", val));
657	#endif
658	if (s->rcnt == 0)
659	return;
660	if (s->dcfg & 0x01) {
661	/* 16 bit access */
662	ne2000_mem_writew(s, s->rsar, val);
663	ne2000_dma_update(s, 2);
664	} else {
665	/* 8 bit access */
666	ne2000_mem_writeb(s, s->rsar, val);
667	ne2000_dma_update(s, 1);
668	}
669	}
670
671	static uint32_t ne2000_asic_ioport_read(void *opaque, uint32_t addr)
672	{
673	NE2000State *s = opaque;
674	int ret;
675
676	if (s->dcfg & 0x01) {
677	/* 16 bit access */
678	ret = ne2000_mem_readw(s, s->rsar);
679	ne2000_dma_update(s, 2);
680	} else {
681	/* 8 bit access */
682	ret = ne2000_mem_readb(s, s->rsar);
683	ne2000_dma_update(s, 1);
684	}
685	#ifdef DEBUG_NE2000
686	Log(("NE2000: asic read val=0x%04x\n", ret));
687	#endif
688	return ret;
689	}
690
691	static void ne2000_asic_ioport_writel(void *opaque, uint32_t addr, uint32_t val)
692	{
693	NE2000State *s = opaque;
694
695	#ifdef DEBUG_NE2000
696	Log(("NE2000: asic writel val=0x%04x\n", val));
697	#endif
698	if (s->rcnt == 0)
699	return;
700	/* 32 bit access */
701	ne2000_mem_writel(s, s->rsar, val);
702	ne2000_dma_update(s, 4);
703	}
704
705	static uint32_t ne2000_asic_ioport_readl(void *opaque, uint32_t addr)
706	{
707	NE2000State *s = opaque;
708	int ret;
709
710	/* 32 bit access */
711	ret = ne2000_mem_readl(s, s->rsar);
712	ne2000_dma_update(s, 4);
713	#ifdef DEBUG_NE2000
714	Log(("NE2000: asic readl val=0x%04x\n", ret));
715	#endif
716	return ret;
717	}
718
719	static void ne2000_reset_ioport_write(void *opaque, uint32_t addr, uint32_t val)
720	{
721	/* nothing to do (end of reset pulse) */
722	}
723
724	static uint32_t ne2000_reset_ioport_read(void *opaque, uint32_t addr)
725	{
726	NE2000State *s = opaque;
727	ne2000_reset(s);
728	return 0;
729	}
730
731	static void ne2000_save(QEMUFile* f,void* opaque)
732	{
733	NE2000State* s=(NE2000State*)opaque;
734
735	qemu_put_8s(f, &s->cmd);
736	qemu_put_be32s(f, &s->start);
737	qemu_put_be32s(f, &s->stop);
738	qemu_put_8s(f, &s->boundary);
739	qemu_put_8s(f, &s->tsr);
740	qemu_put_8s(f, &s->tpsr);
741	qemu_put_be16s(f, &s->tcnt);
742	qemu_put_be16s(f, &s->rcnt);
743	qemu_put_be32s(f, &s->rsar);
744	qemu_put_8s(f, &s->rsr);
745	qemu_put_8s(f, &s->isr);
746	qemu_put_8s(f, &s->dcfg);
747	qemu_put_8s(f, &s->imr);
748	qemu_put_buffer(f, s->phys, 6);
749	qemu_put_8s(f, &s->curpag);
750	qemu_put_buffer(f, s->mult, 8);
751	qemu_put_be32s(f, &s->irq);
752	qemu_put_buffer(f, s->mem, NE2000_MEM_SIZE);
753	}
754
755	static int ne2000_load(QEMUFile* f,void* opaque,int version_id)
756	{
757	NE2000State* s=(NE2000State*)opaque;
758
759	if (version_id != 1)
760	#ifdef VBOX
761	return -1;
762	#else
763	return -EINVAL;
764	#endif
765	qemu_get_8s(f, &s->cmd);
766	qemu_get_be32s(f, &s->start);
767	qemu_get_be32s(f, &s->stop);
768	qemu_get_8s(f, &s->boundary);
769	qemu_get_8s(f, &s->tsr);
770	qemu_get_8s(f, &s->tpsr);
771	qemu_get_be16s(f, &s->tcnt);
772	qemu_get_be16s(f, &s->rcnt);
773	qemu_get_be32s(f, &s->rsar);
774	qemu_get_8s(f, &s->rsr);
775	qemu_get_8s(f, &s->isr);
776	qemu_get_8s(f, &s->dcfg);
777	qemu_get_8s(f, &s->imr);
778	qemu_get_buffer(f, s->phys, 6);
779	qemu_get_8s(f, &s->curpag);
780	qemu_get_buffer(f, s->mult, 8);
781	qemu_get_be32s(f, &s->irq);
782	qemu_get_buffer(f, s->mem, NE2000_MEM_SIZE);
783
784	return 0;
785	}
786
787	#ifndef VBOX
788
789	void isa_ne2000_init(int base, int irq, NetDriverState *nd)
790	{
791	NE2000State *s;
792
793	s = qemu_mallocz(sizeof(NE2000State));
794	if (!s)
795	return;
796
797	register_ioport_write(base, 16, 1, ne2000_ioport_write, s);
798	register_ioport_read(base, 16, 1, ne2000_ioport_read, s);
799
800	register_ioport_write(base + 0x10, 1, 1, ne2000_asic_ioport_write, s);
801	register_ioport_read(base + 0x10, 1, 1, ne2000_asic_ioport_read, s);
802	register_ioport_write(base + 0x10, 2, 2, ne2000_asic_ioport_write, s);
803	register_ioport_read(base + 0x10, 2, 2, ne2000_asic_ioport_read, s);
804
805	register_ioport_write(base + 0x1f, 1, 1, ne2000_reset_ioport_write, s);
806	register_ioport_read(base + 0x1f, 1, 1, ne2000_reset_ioport_read, s);
807	s->irq = irq;
808	s->nd = nd;
809
810	ne2000_reset(s);
811
812	qemu_add_read_packet(nd, ne2000_can_receive, ne2000_receive, s);
813
814	register_savevm("ne2000", 0, 1, ne2000_save, ne2000_load, s);
815
816	}
817
818	/***********************************************************/
819	/* PCI NE2000 definitions */
820
821	typedef struct PCINE2000State {
822	PCIDevice dev;
823	NE2000State ne2000;
824	} PCINE2000State;
825
826	static void ne2000_map(PCIDevice *pci_dev, int region_num,
827	uint32_t addr, uint32_t size, int type)
828	{
829	PCINE2000State d = (PCINE2000State )pci_dev;
830	NE2000State *s = &d->ne2000;
831
832	register_ioport_write(addr, 16, 1, ne2000_ioport_write, s);
833	register_ioport_read(addr, 16, 1, ne2000_ioport_read, s);
834
835	register_ioport_write(addr + 0x10, 1, 1, ne2000_asic_ioport_write, s);
836	register_ioport_read(addr + 0x10, 1, 1, ne2000_asic_ioport_read, s);
837	register_ioport_write(addr + 0x10, 2, 2, ne2000_asic_ioport_write, s);
838	register_ioport_read(addr + 0x10, 2, 2, ne2000_asic_ioport_read, s);
839	register_ioport_write(addr + 0x10, 4, 4, ne2000_asic_ioport_writel, s);
840	register_ioport_read(addr + 0x10, 4, 4, ne2000_asic_ioport_readl, s);
841
842	register_ioport_write(addr + 0x1f, 1, 1, ne2000_reset_ioport_write, s);
843	register_ioport_read(addr + 0x1f, 1, 1, ne2000_reset_ioport_read, s);
844	}
845
846	void pci_ne2000_init(PCIBus bus, NetDriverState nd)
847	{
848	PCINE2000State *d;
849	NE2000State *s;
850	uint8_t *pci_conf;
851
852	d = (PCINE2000State *)pci_register_device(bus,
853	"NE2000", sizeof(PCINE2000State),
854	-1,
855	NULL, NULL);
856	pci_conf = d->dev.config;
857	pci_conf[0x00] = 0xec; // Realtek 8029
858	pci_conf[0x01] = 0x10;
859	pci_conf[0x02] = 0x29;
860	pci_conf[0x03] = 0x80;
861	pci_conf[0x0a] = 0x00; // ethernet network controller
862	pci_conf[0x0b] = 0x02;
863	pci_conf[0x0e] = 0x00; // header_type
864	pci_conf[0x3d] = 1; // interrupt pin 0
865
866	pci_register_io_region(&d->dev, 0, 0x100,
867	PCI_ADDRESS_SPACE_IO, ne2000_map);
868	s = &d->ne2000;
869	s->irq = 16; // PCI interrupt
870	s->pci_dev = (PCIDevice *)d;
871	s->nd = nd;
872	ne2000_reset(s);
873	qemu_add_read_packet(nd, ne2000_can_receive, ne2000_receive, s);
874
875	/* XXX: instance number ? */
876	register_savevm("ne2000", 0, 1, ne2000_save, ne2000_load, s);
877	register_savevm("ne2000_pci", 0, 1, generic_pci_save, generic_pci_load,
878	&d->dev);
879	}
880
881	#else
882
883	/**
884	* Port I/O Handler for IN operations.
885	*
886	* @returns VBox status code.
887	*
888	* @param pDevIns The device instance.
889	* @param pvUser User argument.
890	* @param uPort Port number used for the IN operation.
891	* @param pu32 Where to store the result.
892	* @param cb Number of bytes read.
893	*/
894	static DECLCALLBACK(int) ne2000IOPortRead(PPDMDEVINS pDevIns, void pvUser, RTIOPORT Port, uint32_t pu32, unsigned cb)
895	{
896	switch (cb)
897	{
898	case 1: *pu32 = ne2000_ioport_read(pvUser, Port); break;
899	default:
900	return VERR_IOM_IOPORT_UNUSED;
901	}
902	return VINF_SUCCESS;
903	}
904
905
906	/**
907	* Port I/O Handler for OUT operations.
908	*
909	* @returns VBox status code.
910	*
911	* @param pDevIns The device instance.
912	* @param pvUser User argument.
913	* @param uPort Port number used for the IN operation.
914	* @param u32 The value to output.
915	* @param cb The value size in bytes.
916	*/
917	static DECLCALLBACK(int) ne2000IOPortWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb)
918	{
919	switch (cb)
920	{
921	case 1: ne2000_ioport_write(pvUser, Port, u32); break;
922	default:
923	return VERR_IOM_IOPORT_UNUSED;
924	}
925	return VINF_SUCCESS;
926	}
927
928	/**
929	* Port I/O Handler for IN operations.
930	*
931	* @returns VBox status code.
932	*
933	* @param pDevIns The device instance.
934	* @param pvUser User argument.
935	* @param uPort Port number used for the IN operation.
936	* @param pu32 Where to store the result.
937	* @param cb Number of bytes read.
938	*/
939	static DECLCALLBACK(int) ne2000ASICIOPortRead(PPDMDEVINS pDevIns, void pvUser, RTIOPORT Port, uint32_t pu32, unsigned cb)
940	{
941	switch (cb)
942	{
943	case 1:
944	case 2: *pu32 = ne2000_asic_ioport_read(pvUser, Port); break;
945	case 4: *pu32 = ne2000_asic_ioport_readl(pvUser, Port); break;
946	default:
947	return VERR_IOM_IOPORT_UNUSED;
948	}
949	return VINF_SUCCESS;
950	}
951
952
953	/**
954	* Port I/O Handler for OUT operations.
955	*
956	* @returns VBox status code.
957	*
958	* @param pDevIns The device instance.
959	* @param pvUser User argument.
960	* @param uPort Port number used for the IN operation.
961	* @param u32 The value to output.
962	* @param cb The value size in bytes.
963	*/
964	static DECLCALLBACK(int) ne2000ASICIOPortWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb)
965	{
966	switch (cb)
967	{
968	case 1:
969	case 2: ne2000_asic_ioport_write(pvUser, Port, u32); break;
970	case 4: ne2000_asic_ioport_writel(pvUser, Port, u32); break;
971	default:
972	return VERR_IOM_IOPORT_UNUSED;
973	}
974	return VINF_SUCCESS;
975	}
976
977
978	/**
979	* Port I/O Handler for IN operations.
980	*
981	* @returns VBox status code.
982	*
983	* @param pDevIns The device instance.
984	* @param pvUser User argument.
985	* @param uPort Port number used for the IN operation.
986	* @param pu32 Where to store the result.
987	* @param cb Number of bytes read.
988	*/
989	static DECLCALLBACK(int) ne2000ResetIOPortRead(PPDMDEVINS pDevIns, void pvUser, RTIOPORT Port, uint32_t pu32, unsigned cb)
990	{
991	switch (cb)
992	{
993	case 1: *pu32 = ne2000_reset_ioport_read(pvUser, Port); break;
994	default:
995	return VERR_IOM_IOPORT_UNUSED;
996	}
997	return VINF_SUCCESS;
998	}
999
1000
1001	/**
1002	* Port I/O Handler for OUT operations.
1003	*
1004	* @returns VBox status code.
1005	*
1006	* @param pDevIns The device instance.
1007	* @param pvUser User argument.
1008	* @param uPort Port number used for the IN operation.
1009	* @param u32 The value to output.
1010	* @param cb The value size in bytes.
1011	*/
1012	static DECLCALLBACK(int) ne2000ResetIOPortWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb)
1013	{
1014	switch (cb)
1015	{
1016	case 1: ne2000_reset_ioport_write(pvUser, Port, u32); break;
1017	default:
1018	return VERR_IOM_IOPORT_UNUSED;
1019	}
1020	return VINF_SUCCESS;
1021	}
1022
1023	/**
1024	* Callback function for mapping an PCI I/O region.
1025	*
1026	* @return VBox status code.
1027	* @param pPciDev Pointer to PCI device. Use pPciDev->pDevIns to get the device instance.
1028	* @param iRegion The region number.
1029	* @param GCPhysAddress Physical address of the region. If iType is PCI_ADDRESS_SPACE_IO, this is an
1030	* I/O port, else it's a physical address.
1031	* This address is NOT relative to pci_mem_base like earlier!
1032	* @param enmType One of the PCI_ADDRESS_SPACE_* values.
1033	*/
1034	static DECLCALLBACK(int) ne2000IOPortMap(PPCIDEVICE pPciDev, /unsigned/ int iRegion, RTGCPHYS GCPhysAddress, uint32_t cb, PCIADDRESSSPACE enmType)
1035	{
1036	int rc;
1037	PPDMDEVINS pDevIns = pPciDev->pDevIns;
1038	RTIOPORT Port = (RTIOPORT)GCPhysAddress;
1039	NE2000State *pData = PCIDEV_2_NE2000STATE(pPciDev);
1040
1041	Assert(enmType == PCI_ADDRESS_SPACE_IO);
1042	Assert(cb >= 0x20);
1043
1044	rc = pDevIns->pDevHlp->pfnIOPortRegister(pDevIns, Port, 0x10, pData, ne2000IOPortWrite, ne2000IOPortRead, NULL, NULL, "ne2000");
1045	if (VBOX_FAILURE(rc))
1046	return rc;
1047
1048	rc = pDevIns->pDevHlp->pfnIOPortRegister(pDevIns, Port + 0x10, 0x04, pData, ne2000ASICIOPortWrite, ne2000ASICIOPortRead, NULL, NULL, "ne2000 ASIC");
1049	if (VBOX_FAILURE(rc))
1050	return rc;
1051
1052	rc = pDevIns->pDevHlp->pfnIOPortRegister(pDevIns, Port + 0x1f, 0x01, pData, ne2000ResetIOPortWrite, ne2000ResetIOPortRead, NULL, NULL, "ne2000 Reset");
1053	if (VBOX_FAILURE(rc))
1054	return rc;
1055
1056	pData->IOPortBase = Port;
1057	return VINF_SUCCESS;
1058	}
1059
1060	/**
1061	* Restore timer callback.
1062	*
1063	* This is only called when've restored a saved state and temporarily
1064	* disconnected the network link to inform the guest that network connections
1065	* should be considered lost.
1066	*
1067	* @param pDevIns Device instance of the device which registered the timer.
1068	* @param pTimer The timer handle.
1069	*/
1070	static DECLCALLBACK(void) ne2000TimerRestore(PPDMDEVINS pDevIns, PTMTIMER pTimer)
1071	{
1072	NE2000State pData = PDMINS2DATA(pDevIns, NE2000State );
1073
1074	int rc = VERR_GENERAL_FAILURE;
1075	if (pData->cLinkDownReported <= 3)
1076	rc = TMTimerSetMillies(pData->pTimerRestore, 1500);
1077	if (VBOX_FAILURE(rc))
1078	{
1079	Log(("ne2000TimerRestore: Clearing ERR and CERR after load. cLinkDownReported=%d\n", pData->cLinkDownReported));
1080	pData->fLinkTempDown = false;
1081	AssertFailed();
1082	//// pData->csr[0] &= ~(BIT(15) \| BIT(13)); /* ERR \| CERR - probably not 100% correct either... */
1083	pData->Led.Actual.s.fError = 0;
1084	}
1085	else
1086	Log(("ne2000TimerRestore: cLinkDownReported=%d, wait another 1500ms...\n", pData->cLinkDownReported));
1087	}
1088
1089
1090	/**
1091	* Saves a state of the PC-Net II device.
1092	*
1093	* @returns VBox status code.
1094	* @param pDevIns The device instance.
1095	* @param pSSMHandle The handle to save the state to.
1096	*/
1097	static DECLCALLBACK(int) ne2000SaveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSMHandle)
1098	{
1099	NE2000State pData = PDMINS2DATA(pDevIns, NE2000State );
1100
1101	ne2000_save(pSSMHandle, pData);
1102
1103	SSMR3PutMem(pSSMHandle, &pData->MacConfigured, sizeof(pData->MacConfigured));
1104
1105	return VINF_SUCCESS;
1106	}
1107
1108
1109	/**
1110	* Loads a saved PC-Net II device state.
1111	*
1112	* @returns VBox status code.
1113	* @param pDevIns The device instance.
1114	* @param pSSMHandle The handle to the saved state.
1115	* @param u32Version The data unit version number.
1116	*/
1117	static DECLCALLBACK(int) ne2000LoadExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSMHandle, uint32_t u32Version)
1118	{
1119	NE2000State pData = PDMINS2DATA(pDevIns, NE2000State );
1120	PDMMAC Mac;
1121	if (u32Version != 1)
1122	{
1123	AssertFailed();
1124	return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
1125	}
1126
1127	/* restore data */
1128	ne2000_load(pSSMHandle, pData, u32Version);
1129
1130	SSMR3GetMem(pSSMHandle, &Mac, sizeof(Mac));
1131	Assert(!memcmp(&Mac, &pData->MacConfigured, sizeof(Mac)));
1132
1133	/* Indicate link down to the guest OS that all network connections have been lost. */
1134	pData->fLinkTempDown = true;
1135	pData->cLinkDownReported = 0;
1136	AssertFailed();
1137	/*
1138	* todo !!!!!
1139	*/
1140	//////pData->csr[0] \|= BIT(15) \| BIT(13); /* ERR \| CERR (this is probably wrong) */
1141
1142	pData->Led.Asserted.s.fError = pData->Led.Actual.s.fError = 1;
1143	return TMTimerSetMillies(pData->pTimerRestore, 5000);
1144	}
1145
1146
1147	/**
1148	* Queries an interface to the driver.
1149	*
1150	* @returns Pointer to interface.
1151	* @returns NULL if the interface was not supported by the driver.
1152	* @param pInterface Pointer to this interface structure.
1153	* @param enmInterface The requested interface identification.
1154	* @thread Any thread.
1155	*/
1156	static DECLCALLBACK(void ) ne2000QueryInterface(struct PDMIBASE pInterface, PDMINTERFACE enmInterface)
1157	{
1158	NE2000State pData = (NE2000State )((uintptr_t)pInterface - RT_OFFSETOF(NE2000State, IBase));
1159	Assert(&pData->IBase == pInterface);
1160	switch (enmInterface)
1161	{
1162	case PDMINTERFACE_BASE:
1163	return &pData->IBase;
1164	case PDMINTERFACE_NETWORK_PORT:
1165	return &pData->INetworkPort;
1166	case PDMINTERFACE_NETWORK_CONFIG:
1167	return &pData->INetworkConfig;
1168	case PDMINTERFACE_LED_PORTS:
1169	return &pData->ILeds;
1170	default:
1171	return NULL;
1172	}
1173	}
1174
1175	/** Converts a pointer to NE2000State::INetworkPort to a NE2000State pointer. */
1176	#define INETWORKPORT_2_DATA(pInterface) ( (NE2000State *)((uintptr_t)pInterface - RT_OFFSETOF(NE2000State, INetworkPort)) )
1177
1178	/**
1179	* Check if the device/driver can receive data now.
1180	* This must be called before the pfnRecieve() method is called.
1181	*
1182	* @returns Number of bytes the driver can receive.
1183	* @param pInterface Pointer to the interface structure containing the called function pointer.
1184	* @thread EMT
1185	*/
1186	static DECLCALLBACK(size_t) ne2000CanReceive(PPDMINETWORKPORT pInterface)
1187	{
1188	NE2000State *pData = INETWORKPORT_2_DATA(pInterface);
1189	return ne2000_can_receive(pData);
1190	}
1191
1192
1193	/**
1194	* Receive data from the network.
1195	*
1196	* @returns VBox status code.
1197	* @param pInterface Pointer to the interface structure containing the called function pointer.
1198	* @param pvBuf The available data.
1199	* @param cb Number of bytes available in the buffer.
1200	* @thread EMT
1201	*/
1202	static DECLCALLBACK(int) ne2000Receive(PPDMINETWORKPORT pInterface, const void *pvBuf, size_t cb)
1203	{
1204	NE2000State *pData = INETWORKPORT_2_DATA(pInterface);
1205
1206	if (cb > 70) /* unqualified guess */
1207	pData->Led.Asserted.s.fReading = pData->Led.Actual.s.fReading = 1;
1208	ne2000_receive(pData, pvBuf, cb);
1209	pData->Led.Actual.s.fReading = 0;
1210
1211	return VINF_SUCCESS;
1212	}
1213
1214	/** Converts a pointer to NE2000State::INetworkConfig to a NE2000State pointer. */
1215	#define INETWORKCONFIG_2_DATA(pInterface) ( (NE2000State *)((uintptr_t)pInterface - RT_OFFSETOF(NE2000State, INetworkConfig)) )
1216
1217
1218	/**
1219	* Gets the current Media Access Control (MAC) address.
1220	*
1221	* @returns VBox status code.
1222	* @param pInterface Pointer to the interface structure containing the called function pointer.
1223	* @param pMac Where to store the MAC address.
1224	* @thread EMT
1225	*/
1226	static DECLCALLBACK(int) ne2000GetMac(PPDMINETWORKCONFIG pInterface, PPDMMAC *pMac)
1227	{
1228	NE2000State *pData = INETWORKCONFIG_2_DATA(pInterface);
1229	memcpy(pMac, pData->mem, sizeof(*pMac));
1230	return VINF_SUCCESS;
1231	}
1232
1233
1234	/**
1235	* Gets the pointer to the status LED of a unit.
1236	*
1237	* @returns VBox status code.
1238	* @param pInterface Pointer to the interface structure containing the called function pointer.
1239	* @param iLUN The unit which status LED we desire.
1240	* @param ppLed Where to store the LED pointer.
1241	*/
1242	static DECLCALLBACK(int) ne2000QueryStatusLed(PPDMILEDPORTS pInterface, unsigned iLUN, PPDMLED *ppLed)
1243	{
1244	NE2000State pData = (NE2000State )( (uintptr_t)pInterface - RT_OFFSETOF(NE2000State, ILeds) );
1245	if (iLUN == 0)
1246	{
1247	*ppLed = &pData->Led;
1248	return VINF_SUCCESS;
1249	}
1250	return VERR_PDM_LUN_NOT_FOUND;
1251	}
1252
1253	/**
1254	* Construct a device instance for a VM.
1255	*
1256	* @returns VBox status.
1257	* @param pDevIns The device instance data.
1258	* If the registration structure is needed, pDevIns->pDevReg points to it.
1259	* @param iInstance Instance number. Use this to figure out which registers and such to use.
1260	* The device number is also found in pDevIns->iInstance, but since it's
1261	* likely to be freqently used PDM passes it as parameter.
1262	* @param pCfgHandle Configuration node handle for the device. Use this to obtain the configuration
1263	* of the device instance. It's also found in pDevIns->pCfgHandle, but like
1264	* iInstance it's expected to be used a bit in this function.
1265	*/
1266	static DECLCALLBACK(int) ne2000Construct(PPDMDEVINS pDevIns, int iInstance, PCFGMNODE pCfgHandle)
1267	{
1268	NE2000State pData = PDMINS2DATA(pDevIns, NE2000State );
1269	PPDMIBASE pBase;
1270	int rc;
1271	Assert(iInstance == 0);
1272
1273	/*
1274	* Validate configuration.
1275	*/
1276	if (!CFGMR3AreValuesValid(pCfgHandle, "MAC\0CableConnected\0"))
1277	return VERR_PDM_DEVINS_UNKNOWN_CFG_VALUES;
1278
1279	/*
1280	* Read the configuration.
1281	*/
1282	rc = CFGMR3QueryBytes(pCfgHandle, "MAC", &pData->MacConfigured, sizeof(pData->MacConfigured));
1283	if (VBOX_FAILURE(rc))
1284	{
1285	AssertMsgFailed(("Configuration error: Failed to get the \"MAC\" value, rc=%Vrc\n", rc));
1286	return rc;
1287	}
1288
1289	/*
1290	* Initialize data (most of it anyway).
1291	*/
1292	pData->pDevIns = pDevIns;
1293	pData->Led.u32Magic = PDMLED_MAGIC;
1294	/* IBase */
1295	pData->IBase.pfnQueryInterface = ne2000QueryInterface;
1296	/* INeworkPort */
1297	pData->INetworkPort.pfnCanReceive = ne2000CanReceive;
1298	pData->INetworkPort.pfnReceive = ne2000Receive;
1299	/* INetworkConfig */
1300	pData->INetworkConfig.pfnGetMac = ne2000GetMac;
1301	/** @todo link state */
1302	/* ILeds */
1303	pData->ILeds.pfnQueryStatusLed = ne2000QueryStatusLed;
1304
1305
1306	/* PCI Device */
1307	pData->dev.config[0x00] = 0xec; // Realtek 8029
1308	pData->dev.config[0x01] = 0x10;
1309	pData->dev.config[0x02] = 0x29;
1310	pData->dev.config[0x03] = 0x80;
1311	pData->dev.config[0x0a] = 0x00; // ethernet network controller
1312	pData->dev.config[0x0b] = 0x02;
1313	pData->dev.config[0x0e] = 0x00; // header_type
1314	pData->dev.config[0x3d] = 1; // interrupt pin 0
1315
1316	/*
1317	* Register the PCI device, its I/O regions, the timer and the saved state item.
1318	*/
1319	rc = pDevIns->pDevHlp->pfnPCIRegister(pDevIns, &pData->dev);
1320	if (VBOX_FAILURE(rc))
1321	return rc;
1322	rc = pDevIns->pDevHlp->pfnPCIIORegionRegister(pDevIns, 0, 0x100, PCI_ADDRESS_SPACE_IO, ne2000IOPortMap);
1323	if (VBOX_FAILURE(rc))
1324	return rc;
1325
1326	rc = pDevIns->pDevHlp->pfnTMTimerCreate(pDevIns, TMCLOCK_VIRTUAL, ne2000TimerRestore, "NE2000 Restore Timer", &pData->pTimerRestore);
1327	if (VBOX_FAILURE(rc))
1328	{
1329	AssertMsgFailed(("pfnTMTimerCreate -> %Vrc\n", rc));
1330	return rc;
1331	}
1332
1333	rc = pDevIns->pDevHlp->pfnSSMRegister(pDevIns, pDevIns->pDevReg->szDeviceName, iInstance, 1 /* version /, sizeof(pData),
1334	NULL, ne2000SaveExec, NULL,
1335	NULL, ne2000LoadExec, NULL);
1336	if (VBOX_FAILURE(rc))
1337	return rc;
1338
1339	/*
1340	* Attach status driver (optional).
1341	*/
1342	rc = pDevIns->pDevHlp->pfnDriverAttach(pDevIns, PDM_STATUS_LUN, &pData->IBase, &pBase, "Status Port");
1343	if (VBOX_SUCCESS(rc))
1344	pData->pLedsConnector = pBase->pfnQueryInterface(pBase, PDMINTERFACE_LED_CONNECTORS);
1345	else if (rc != VERR_PDM_NO_ATTACHED_DRIVER)
1346	{
1347	AssertMsgFailed(("Failed to attach to status driver. rc=%Vrc\n", rc));
1348	return rc;
1349	}
1350
1351	/*
1352	* Attach driver.
1353	*/
1354	rc = pDevIns->pDevHlp->pfnDriverAttach(pDevIns, 0, &pData->IBase, &pData->pDrvBase, "Network Port");
1355	if (VBOX_SUCCESS(rc))
1356	{
1357	pData->pDrv = (PPDMINETWORKCONNECTOR)pData->pDrvBase->pfnQueryInterface(pData->pDrvBase, PDMINTERFACE_NETWORK_CONNECTOR);
1358	if (!pData->pDrv)
1359	{
1360	AssertMsgFailed(("Failed to obtain the PDMINTERFACE_NETWORK_CONNECTOR interface!\n"));
1361	return VERR_PDM_MISSING_INTERFACE_BELOW;
1362	}
1363	}
1364	else if (rc == VERR_PDM_NO_ATTACHED_DRIVER)
1365	Log(("ne2000: No attached driver!\n"));
1366	else
1367	return rc;
1368
1369	pData->irq = 16; // PCI interrupt
1370
1371	/*
1372	* Reset the device state (will need pDrv later).
1373	*/
1374	ne2000_reset(pData);
1375
1376	return VINF_SUCCESS;
1377	}
1378
1379
1380	/**
1381	* The device registration structure.
1382	*/
1383	const PDMDEVREG g_DeviceNE2000 =
1384	{
1385	/* u32Version */
1386	PDM_DEVREG_VERSION,
1387	/* szDeviceName */
1388	"ne2000",
1389	/* szGCMod */
1390	"",
1391	/* szR0Mod */
1392	"",
1393	/* pszDescription */
1394	"NE2000 Ethernet controller.\n",
1395	/* fFlags */
1396	PDM_DEVREG_FLAGS_HOST_BITS_DEFAULT \| PDM_DEVREG_FLAGS_GUEST_BITS_DEFAULT,
1397	/* fClass */
1398	PDM_DEVREG_CLASS_NETWORK,
1399	/* cMaxInstances */
1400	~0,
1401	/* cbInstance */
1402	sizeof(NE2000State),
1403	/* pfnConstruct */
1404	ne2000Construct,
1405	/* pfnDestruct */
1406	NULL,
1407	/* pfnRelocate */
1408	NULL,
1409	/* pfnIOCtl */
1410	NULL,
1411	/* pfnPowerOn */
1412	NULL,
1413	/* pfnReset */
1414	NULL, /** @todo check if this card is actually reset in anyway... */
1415	/* pfnSuspend */
1416	NULL,
1417	/* pfnResume */
1418	NULL,
1419	/* pfnAttach */
1420	NULL,
1421	/* pfnDetach */
1422	NULL,
1423	/* pfnQueryInterface. */
1424	NULL
1425	};
1426
1427	#endif /* VBOX */

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source: vbox/trunk/src/VBox/Devices/Network/ne2000.c@ 61

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