DevPCNet.cpp@ 82254

Last change on this file since 82254 was 82215, checked in by vboxsync, 5 years ago
DevPCNet: Convered the temp MMIO2 region we create when loading old old saved states. bugref:9218
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1	/* $Id: DevPCNet.cpp 82215 2019-11-26 03:03:45Z vboxsync $ */
2	/** @file
3	* DevPCNet - AMD PCnet-PCI II / PCnet-FAST III (Am79C970A / Am79C973) Ethernet Controller Emulation.
4	*
5	* This software was written to be compatible with the specifications:
6	* AMD Am79C970A PCnet-PCI II Ethernet Controller Data-Sheet
7	* AMD Publication# 19436 Rev:E Amendment/0 Issue Date: June 2000
8	* and
9	* AMD Am79C973/Am79C975 PCnet-FAST III Single-Chip 10/100 Mbps PCI Ethernet Controller datasheet
10	* AMD publication# 20510 Rev:E Amendment/0 Issue Date: August 2000
11	* and
12	* AMD Am79C960 PCnet-ISA Single-Chip Ethernet Controller datasheet
13	* AMD publication# 16907 Rev:B Amendment/0 Issue Date: May 1994
14	*/
15
16	/*
17	* Copyright (C) 2006-2019 Oracle Corporation
18	*
19	* This file is part of VirtualBox Open Source Edition (OSE), as
20	* available from http://www.virtualbox.org. This file is free software;
21	* you can redistribute it and/or modify it under the terms of the GNU
22	* General Public License (GPL) as published by the Free Software
23	* Foundation, in version 2 as it comes in the "COPYING" file of the
24	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
25	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
26	* --------------------------------------------------------------------
27	*
28	* This code is based on:
29	*
30	* AMD PCnet-PCI II (Am79C970A) emulation
31	*
32	* Copyright (c) 2004 Antony T Curtis
33	*
34	* Permission is hereby granted, free of charge, to any person obtaining a copy
35	* of this software and associated documentation files (the "Software"), to deal
36	* in the Software without restriction, including without limitation the rights
37	* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
38	* copies of the Software, and to permit persons to whom the Software is
39	* furnished to do so, subject to the following conditions:
40	*
41	* The above copyright notice and this permission notice shall be included in
42	* all copies or substantial portions of the Software.
43	*
44	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
45	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
46	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
47	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
48	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
49	* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
50	* THE SOFTWARE.
51	*/
52
53
54	/*********************************************************************************************************************************
55	* Header Files *
56	*********************************************************************************************************************************/
57	#define LOG_GROUP LOG_GROUP_DEV_PCNET
58	#include <VBox/vmm/pdmdev.h>
59	#include <VBox/vmm/pdmnetifs.h>
60	#include <VBox/vmm/pgm.h>
61	#include <VBox/version.h>
62	#include <iprt/asm.h>
63	#include <iprt/assert.h>
64	#include <iprt/critsect.h>
65	#include <iprt/net.h>
66	#include <iprt/string.h>
67	#include <iprt/time.h>
68	#ifdef IN_RING3
69	# include <iprt/mem.h>
70	# include <iprt/semaphore.h>
71	# include <iprt/uuid.h>
72	#endif
73
74	#include "VBoxDD.h"
75
76
77	/*********************************************************************************************************************************
78	* Defined Constants And Macros *
79	*********************************************************************************************************************************/
80	/* Enable this to catch writes to the ring descriptors instead of using excessive polling */
81	/* #define PCNET_NO_POLLING */
82
83	/* Enable to handle frequent io reads in the guest context (recommended) */
84	#define PCNET_GC_ENABLED
85
86	/* PCNET_DEBUG_IO - Log6 */
87	/* PCNET_DEBUG_BCR - Log7 */
88	/* PCNET_DEBUG_CSR - Log8 */
89	/* PCNET_DEBUG_RMD - Log9 */
90	/* PCNET_DEBUG_TMD - Log10 */
91	/* PCNET_DEBUG_MATCH - Log11 */
92	/* PCNET_DEBUG_MII - Log12 */
93
94	#define PCNET_IOPORT_SIZE 0x20
95	#define PCNET_PNPMMIO_SIZE 0x20
96
97	#define PCNET_SAVEDSTATE_VERSION 10
98
99	#define BCR_MAX_RAP 50
100	#define MII_MAX_REG 32
101	#define CSR_MAX_REG 128
102
103	/** Maximum number of times we report a link down to the guest (failure to send frame) */
104	#define PCNET_MAX_LINKDOWN_REPORTED 3
105
106	/** Maximum frame size we handle */
107	#define MAX_FRAME 1536
108
109	#define PCNET_INST_NR (pThis->iInstance)
110
111	/** @name Bus configuration registers
112	* @{ */
113	#define BCR_MSRDA 0
114	#define BCR_MSWRA 1
115	#define BCR_MC 2
116	#define BCR_RESERVED3 3
117	#define BCR_LNKST 4
118	#define BCR_LED1 5
119	#define BCR_LED2 6
120	#define BCR_LED3 7
121	#define BCR_RESERVED8 8
122	#define BCR_FDC 9
123	/* 10 - 15 = reserved */
124	#define BCR_IOBASEL 16 /* Reserved */
125	#define BCR_IOBASEU 16 /* Reserved */
126	#define BCR_BSBC 18
127	#define BCR_EECAS 19
128	#define BCR_SWS 20
129	#define BCR_INTCON 21 /* Reserved */
130	#define BCR_PLAT 22
131	#define BCR_PCISVID 23
132	#define BCR_PCISID 24
133	#define BCR_SRAMSIZ 25
134	#define BCR_SRAMB 26
135	#define BCR_SRAMIC 27
136	#define BCR_EBADDRL 28
137	#define BCR_EBADDRU 29
138	#define BCR_EBD 30
139	#define BCR_STVAL 31
140	#define BCR_MIICAS 32
141	#define BCR_MIIADDR 33
142	#define BCR_MIIMDR 34
143	#define BCR_PCIVID 35
144	#define BCR_PMC_A 36
145	#define BCR_DATA0 37
146	#define BCR_DATA1 38
147	#define BCR_DATA2 39
148	#define BCR_DATA3 40
149	#define BCR_DATA4 41
150	#define BCR_DATA5 42
151	#define BCR_DATA6 43
152	#define BCR_DATA7 44
153	#define BCR_PMR1 45
154	#define BCR_PMR2 46
155	#define BCR_PMR3 47
156	/** @} */
157
158	/** @name Bus configuration sub register accessors.
159	* @{ */
160	#define BCR_DWIO(S) !!((S)->aBCR[BCR_BSBC] & 0x0080)
161	#define BCR_SSIZE32(S) !!((S)->aBCR[BCR_SWS ] & 0x0100)
162	#define BCR_SWSTYLE(S) ((S)->aBCR[BCR_SWS ] & 0x00FF)
163	/** @} */
164
165	/** @name CSR subregister accessors.
166	* @{ */
167	#define CSR_INIT(S) !!((S)->aCSR[0] & 0x0001) /*< Init assertion /
168	#define CSR_STRT(S) !!((S)->aCSR[0] & 0x0002) /*< Start assertion /
169	#define CSR_STOP(S) !!((S)->aCSR[0] & 0x0004) /*< Stop assertion /
170	#define CSR_TDMD(S) !!((S)->aCSR[0] & 0x0008) /*< Transmit demand. (perform xmit poll now (readable, settable, not clearable) /
171	#define CSR_TXON(S) !!((S)->aCSR[0] & 0x0010) /*< Transmit on (readonly) /
172	#define CSR_RXON(S) !!((S)->aCSR[0] & 0x0020) /*< Receive On /
173	#define CSR_INEA(S) !!((S)->aCSR[0] & 0x0040) /*< Interrupt Enable /
174	#define CSR_LAPPEN(S) !!((S)->aCSR[3] & 0x0020) /*< Look Ahead Packet Processing Enable /
175	#define CSR_DXSUFLO(S) !!((S)->aCSR[3] & 0x0040) /*< Disable Transmit Stop on Underflow error /
176	#define CSR_ASTRP_RCV(S) !!((S)->aCSR[4] & 0x0400) /*< Auto Strip Receive /
177	#define CSR_DPOLL(S) !!((S)->aCSR[4] & 0x1000) /*< Disable Transmit Polling /
178	#define CSR_SPND(S) !!((S)->aCSR[5] & 0x0001) /*< Suspend /
179	#define CSR_LTINTEN(S) !!((S)->aCSR[5] & 0x4000) /*< Last Transmit Interrupt Enable /
180	#define CSR_TOKINTD(S) !!((S)->aCSR[5] & 0x8000) /*< Transmit OK Interrupt Disable /
181
182	#define CSR_STINT !!((S)->aCSR[7] & 0x0800) /*< Software Timer Interrupt /
183	#define CSR_STINTE !!((S)->aCSR[7] & 0x0400) /*< Software Timer Interrupt Enable /
184
185	#define CSR_DRX(S) !!((S)->aCSR[15] & 0x0001) /*< Disable Receiver /
186	#define CSR_DTX(S) !!((S)->aCSR[15] & 0x0002) /*< Disable Transmit /
187	#define CSR_LOOP(S) !!((S)->aCSR[15] & 0x0004) /*< Loopback Enable /
188	#define CSR_DRCVPA(S) !!((S)->aCSR[15] & 0x2000) /*< Disable Receive Physical Address /
189	#define CSR_DRCVBC(S) !!((S)->aCSR[15] & 0x4000) /*< Disable Receive Broadcast /
190	#define CSR_PROM(S) !!((S)->aCSR[15] & 0x8000) /*< Promiscuous Mode /
191	/** @} */
192
193	#if !defined(RT_ARCH_X86) && !defined(RT_ARCH_AMD64)
194	# error fix macros (and more in this file) for big-endian machines
195	#endif
196
197	/** @name CSR register accessors.
198	* @{ */
199	#define CSR_IADR(S) ((uint32_t)((S)->aCSR + 1)) /*< Initialization Block Address /
200	#define CSR_CRBA(S) ((uint32_t)((S)->aCSR + 18)) /*< Current Receive Buffer Address /
201	#define CSR_CXBA(S) ((uint32_t)((S)->aCSR + 20)) /*< Current Transmit Buffer Address /
202	#define CSR_NRBA(S) ((uint32_t)((S)->aCSR + 22)) /*< Next Receive Buffer Address /
203	#define CSR_BADR(S) ((uint32_t)((S)->aCSR + 24)) /*< Base Address of Receive Ring /
204	#define CSR_NRDA(S) ((uint32_t)((S)->aCSR + 26)) /*< Next Receive Descriptor Address /
205	#define CSR_CRDA(S) ((uint32_t)((S)->aCSR + 28)) /*< Current Receive Descriptor Address /
206	#define CSR_BADX(S) ((uint32_t)((S)->aCSR + 30)) /*< Base Address of Transmit Descriptor /
207	#define CSR_NXDA(S) ((uint32_t)((S)->aCSR + 32)) /*< Next Transmit Descriptor Address /
208	#define CSR_CXDA(S) ((uint32_t)((S)->aCSR + 34)) /*< Current Transmit Descriptor Address /
209	#define CSR_NNRD(S) ((uint32_t)((S)->aCSR + 36)) /*< Next Next Receive Descriptor Address /
210	#define CSR_NNXD(S) ((uint32_t)((S)->aCSR + 38)) /*< Next Next Transmit Descriptor Address /
211	#define CSR_CRBC(S) ((S)->aCSR[40]) /*< Current Receive Byte Count /
212	#define CSR_CRST(S) ((S)->aCSR[41]) /*< Current Receive Status /
213	#define CSR_CXBC(S) ((S)->aCSR[42]) /*< Current Transmit Byte Count /
214	#define CSR_CXST(S) ((S)->aCSR[43]) /*< Current transmit status /
215	#define CSR_NRBC(S) ((S)->aCSR[44]) /*< Next Receive Byte Count /
216	#define CSR_NRST(S) ((S)->aCSR[45]) /*< Next Receive Status /
217	#define CSR_POLL(S) ((S)->aCSR[46]) /*< Transmit Poll Time Counter /
218	#define CSR_PINT(S) ((S)->aCSR[47]) /*< Transmit Polling Interval /
219	#define CSR_PXDA(S) ((uint32_t)((S)->aCSR + 60)) /*< Previous Transmit Descriptor Address/
220	#define CSR_PXBC(S) ((S)->aCSR[62]) /*< Previous Transmit Byte Count /
221	#define CSR_PXST(S) ((S)->aCSR[63]) /*< Previous Transmit Status /
222	#define CSR_NXBA(S) ((uint32_t)((S)->aCSR + 64)) /*< Next Transmit Buffer Address /
223	#define CSR_NXBC(S) ((S)->aCSR[66]) /*< Next Transmit Byte Count /
224	#define CSR_NXST(S) ((S)->aCSR[67]) /*< Next Transmit Status /
225	#define CSR_RCVRC(S) ((S)->aCSR[72]) /*< Receive Descriptor Ring Counter /
226	#define CSR_XMTRC(S) ((S)->aCSR[74]) /*< Transmit Descriptor Ring Counter /
227	#define CSR_RCVRL(S) ((S)->aCSR[76]) /*< Receive Descriptor Ring Length /
228	#define CSR_XMTRL(S) ((S)->aCSR[78]) /*< Transmit Descriptor Ring Length /
229	#define CSR_MISSC(S) ((S)->aCSR[112]) /*< Missed Frame Count /
230	/** @} */
231
232	/** @name Version for the PCnet/FAST III 79C973 card
233	* @{ */
234	#define CSR_VERSION_LOW_79C973 0x5003 /* the lower two bits are always 11b for AMD (JEDEC) */
235	#define CSR_VERSION_LOW_79C970A 0x1003
236	#define CSR_VERSION_LOW_79C960 0x3003
237	#define CSR_VERSION_HIGH 0x0262
238	/** @} */
239
240	/** Calculates the full physical address. */
241	#define PHYSADDR(S,A) ((A) \| (S)->GCUpperPhys)
242
243
244	/*********************************************************************************************************************************
245	* Structures and Typedefs *
246	*********************************************************************************************************************************/
247
248	/**
249	* Emulated device types.
250	*/
251	enum PCNET_DEVICE_TYPE
252	{
253	DEV_AM79C970A = 0, /* PCnet-PCI II (PCI, 10 Mbps). */
254	DEV_AM79C973 = 1, /* PCnet-FAST III (PCI, 10/100 Mbps). */
255	DEV_AM79C960 = 2, /* PCnet-ISA (ISA, 10 Mbps, NE2100/NE1500T compatible) */
256	DEV_AM79C960_EB = 3 /* PCnet-ISA (ISA, 10 Mbps, Racal InterLan EtherBlaster compatible) */
257	};
258
259	#define PCNET_IS_PCI(pcnet) ((pcnet->uDevType == DEV_AM79C970A) \|\| (pcnet->uDevType == DEV_AM79C973))
260	#define PCNET_IS_ISA(pcnet) ((pcnet->uDevType == DEV_AM79C960) \|\| (pcnet->uDevType == DEV_AM79C960_EB))
261
262	/*
263	* Note: Old adapters, including the original NE2100/NE1500T, used the LANCE (Am7990) or
264	* possibly C-LANCE (Am79C90) chips. Those only had the RAP/RDP register and any PROMs were
265	* decoded by external circuitry; as a consequence, different vendors used different layouts.
266	* Several different variants are known:
267	*
268	* 1) Racal Interlan NI6510 (before PCnet-based EtherBlaster variants):
269	* - RDP at iobase + 0x00 (16-bit)
270	* - RAP at iobase + 0x02 (16-bit)
271	* - reset at iobase + 0x04 (8-bit)
272	* - config at iobase + 0x05 (8-bit)
273	* - PROM at iobase + 0x08
274	*
275	* 2) BICC Data Networks ISOLAN 4110-2 (ISA) / 4110-3 (MCA):
276	* - PROM at iobase + 0x00
277	* - reset at iobase + 0x04
278	* - config at iobase + 0x05
279	* - RDP at iobase + 0x0c (16-bit)
280	* - RAP at iobase + 0x0e (16-bit)
281	*
282	* 3) Novell NE2100/NE1500T, AMD Am2100, all PCnet chips:
283	* - PROM at iobase + 0x00
284	* - RDP at iobase + 0x10 (16-bit)
285	* - RAP at iobase + 0x12 (16-bit)
286	* - reset at iobase + 0x14 (16-bit)
287	* - BDP/IDP at iobase + 0x16 (16-bit)
288	*
289	* There were also non-busmastering LANCE adapters, such as the BICC 4110-1, DEC DEPCA,
290	* or NTI 16. Those are uninteresting.
291	*
292	* Newer adapters based on the integrated PCnet-ISA (Am79C960) and later have a fixed
293	* register layout compatible with the NE2100. However, they may still require different
294	* drivers. At least two different incompatible drivers exist for PCnet-based cards:
295	* Those from AMD and those from Racal InterLan for their EtherBlaster cards. The PROM
296	* on EtherBlaster cards uses a different signature ('RD' instead of 'WW') and Racal's
297	* drivers insist on the MAC address having the Racal-Datacom OUI (02 07 01).
298	*/
299
300	/**
301	* PCNET state.
302	*
303	* @implements PDMIBASE
304	* @implements PDMINETWORKDOWN
305	* @implements PDMINETWORKCONFIG
306	* @implements PDMILEDPORTS
307	*/
308	typedef struct PCNETSTATE
309	{
310	/** Software Interrupt timer - R3. */
311	TMTIMERHANDLE hTimerSoftInt;
312	#ifndef PCNET_NO_POLLING
313	/** Poll timer - R3. */
314	TMTIMERHANDLE hTimerPoll;
315	#endif
316	/** Restore timer.
317	* This is used to disconnect and reconnect the link after a restore. */
318	TMTIMERHANDLE hTimerRestore;
319
320	/** Transmit signaller. */
321	PDMTASKHANDLE hXmitTask;
322
323	/** Register Address Pointer */
324	uint32_t u32RAP;
325	/** Internal interrupt service */
326	int32_t iISR;
327	/** ??? */
328	uint32_t u32Lnkst;
329	/** Address of the RX descriptor table (ring). Loaded at init. */
330	RTGCPHYS32 GCRDRA;
331	/** Address of the TX descriptor table (ring). Loaded at init. */
332	RTGCPHYS32 GCTDRA;
333	uint8_t aPROM[16];
334	uint16_t aCSR[CSR_MAX_REG];
335	uint16_t aBCR[BCR_MAX_RAP];
336	uint16_t aMII[MII_MAX_REG];
337
338	/** Holds the bits which were really seen by the guest. Relevant are bits
339	* 8..14 (IDON, TINT, RINT, MERR, MISS, CERR, BABL). We don't allow the
340	* guest to clear any of these bits (by writing a ONE) before a bit was
341	* seen by the guest. */
342	uint16_t u16CSR0LastSeenByGuest;
343	/** The configured IRQ for ISA operation. */
344	uint8_t uIsaIrq;
345	/** Alignment padding. */
346	uint8_t Alignment2[1+4];
347
348	/** Last time we polled the queues */
349	uint64_t u64LastPoll;
350
351	/** Size of a RX/TX descriptor (8 or 16 bytes according to SWSTYLE */
352	int32_t iLog2DescSize;
353	/** Bits 16..23 in 16-bit mode */
354	RTGCPHYS32 GCUpperPhys;
355
356	/** Base port of the I/O space region. */
357	RTIOPORT IOPortBase;
358	/** If set the link is currently up. */
359	bool fLinkUp;
360	/** If set the link is temporarily down because of a saved state load. */
361	bool fLinkTempDown;
362
363	/** Number of times we've reported the link down. */
364	uint32_t cLinkDownReported;
365	/** The configured MAC address. */
366	RTMAC MacConfigured;
367	/** Set if PCNETSTATER3::pDrvR3 is not NULL. */
368	bool fDriverAttached;
369	/** Alignment padding. */
370	uint8_t bAlignment3;
371
372	/** The LED. */
373	PDMLED Led;
374
375	/** Access critical section. */
376	PDMCRITSECT CritSect;
377	/** Event semaphore for blocking on receive. */
378	SUPSEMEVENT hEventOutOfRxSpace;
379	/** We are waiting/about to start waiting for more receive buffers. */
380	bool volatile fMaybeOutOfSpace;
381	/** True if we signal the guest that RX packets are missing. */
382	bool fSignalRxMiss;
383	/** Alignment padding. */
384	uint8_t Alignment4[HC_ARCH_BITS == 64 ? 2 : 6];
385
386	#ifdef PCNET_NO_POLLING
387	PGMPHYSHANDLERTYPE hNoPollingHandlerType;
388	RTGCPHYS32 TDRAPhysOld;
389	uint32_t cbTDRAOld;
390
391	RTGCPHYS32 RDRAPhysOld;
392	uint32_t cbRDRAOld;
393	#endif
394
395	/** Error counter for bad receive descriptors. */
396	uint32_t uCntBadRMD;
397	/** Emulated device type. */
398	uint8_t uDevType;
399	bool afAlignment5[3];
400	/** Link speed to be reported through CSR68. */
401	uint32_t u32LinkSpeed;
402	/** MS to wait before we enable the link. */
403	uint32_t cMsLinkUpDelay;
404	/** The device instance number (for logging). */
405	uint32_t iInstance;
406
407	/** PCI Region \#0: I/O ports offset 0x10-0x1f. */
408	IOMIOPORTHANDLE hIoPortsPci;
409	/** PCI Region \#0: I/O ports offset 0x00-0x0f. */
410	IOMIOPORTHANDLE hIoPortsPciAProm;
411	/** PCI Region \#1: MMIO alternative to the I/O ports in region \#0. */
412	IOMMMIOHANDLE hMmioPci;
413
414	/** ISA I/O ports offset 0x10-0x1f. */
415	IOMIOPORTHANDLE hIoPortsIsa;
416	/** ISA I/O ports offset 0x00-0x0f. */
417	IOMIOPORTHANDLE hIoPortsIsaAProm;
418
419	/** Backwards compatible shared memory region during state loading (before 4.3.6). */
420	PGMMMIO2HANDLE hMmio2Shared;
421
422	/** The loopback transmit buffer (avoid stack allocations). */
423	uint8_t abLoopBuf[4096];
424	/** The recv buffer. */
425	uint8_t abRecvBuf[4096];
426
427	STAMCOUNTER StatReceiveBytes;
428	STAMCOUNTER StatTransmitBytes;
429	#ifdef VBOX_WITH_STATISTICS
430	STAMPROFILEADV StatMMIOReadRZ;
431	STAMPROFILEADV StatMMIOReadR3;
432	STAMPROFILEADV StatMMIOWriteRZ;
433	STAMPROFILEADV StatMMIOWriteR3;
434	STAMPROFILEADV StatAPROMRead;
435	STAMPROFILEADV StatAPROMWrite;
436	STAMPROFILEADV StatIOReadRZ;
437	STAMPROFILEADV StatIOReadR3;
438	STAMPROFILEADV StatIOWriteRZ;
439	STAMPROFILEADV StatIOWriteR3;
440	STAMPROFILEADV StatTimer;
441	STAMPROFILEADV StatReceive;
442	STAMPROFILEADV StatTransmitR3;
443	STAMPROFILEADV StatTransmitRZ;
444	STAMCOUNTER StatTransmitCase1;
445	STAMCOUNTER StatTransmitCase2;
446	STAMPROFILE StatTransmitSendR3;
447	STAMPROFILE StatTransmitSendRZ;
448	STAMPROFILEADV StatTxLenCalcRZ;
449	STAMPROFILEADV StatTxLenCalcR3;
450	STAMPROFILEADV StatTdtePollRZ;
451	STAMPROFILEADV StatTdtePollR3;
452	STAMPROFILEADV StatTmdStoreRZ;
453	STAMPROFILEADV StatTmdStoreR3;
454	STAMPROFILEADV StatRdtePollR3;
455	STAMPROFILEADV StatRdtePollRZ;
456	STAMPROFILE StatRxOverflow;
457	STAMCOUNTER StatRxOverflowWakeup;
458	STAMCOUNTER aStatXmitFlush[16];
459	STAMCOUNTER aStatXmitChainCounts[16];
460	STAMCOUNTER StatXmitSkipCurrent;
461	STAMPROFILEADV StatInterrupt;
462	STAMPROFILEADV StatPollTimer;
463	STAMCOUNTER StatMIIReads;
464	# ifdef PCNET_NO_POLLING
465	STAMCOUNTER StatRCVRingWrite;
466	STAMCOUNTER StatTXRingWrite;
467	STAMCOUNTER StatRingWriteR3;
468	STAMCOUNTER StatRingWriteR0;
469	STAMCOUNTER StatRingWriteRC;
470
471	STAMCOUNTER StatRingWriteFailedR3;
472	STAMCOUNTER StatRingWriteFailedR0;
473	STAMCOUNTER StatRingWriteFailedRC;
474
475	STAMCOUNTER StatRingWriteOutsideR3;
476	STAMCOUNTER StatRingWriteOutsideR0;
477	STAMCOUNTER StatRingWriteOutsideRC;
478	# endif
479	#endif /* VBOX_WITH_STATISTICS */
480	} PCNETSTATE;
481	/** Pointer to a shared PCnet state structure. */
482	typedef PCNETSTATE *PPCNETSTATE;
483
484
485	/**
486	* PCNET state for ring-3.
487	*
488	* @implements PDMIBASE
489	* @implements PDMINETWORKDOWN
490	* @implements PDMINETWORKCONFIG
491	* @implements PDMILEDPORTS
492	*/
493	typedef struct PCNETSTATER3
494	{
495	/** Pointer to the device instance. */
496	PPDMDEVINSR3 pDevIns;
497	/** Pointer to the connector of the attached network driver. */
498	PPDMINETWORKUPR3 pDrv;
499	/** Pointer to the attached network driver. */
500	R3PTRTYPE(PPDMIBASE) pDrvBase;
501	/** LUN\#0 + status LUN: The base interface. */
502	PDMIBASE IBase;
503	/** LUN\#0: The network port interface. */
504	PDMINETWORKDOWN INetworkDown;
505	/** LUN\#0: The network config port interface. */
506	PDMINETWORKCONFIG INetworkConfig;
507
508	/** Status LUN: The LED ports. */
509	PDMILEDPORTS ILeds;
510	/** Partner of ILeds. */
511	R3PTRTYPE(PPDMILEDCONNECTORS) pLedsConnector;
512	} PCNETSTATER3;
513	/** Pointer to a PCnet state structure for ring-3. */
514	typedef PCNETSTATER3 *PPCNETSTATER3;
515
516
517	/**
518	* PCNET state for ring-0.
519	*/
520	typedef struct PCNETSTATER0
521	{
522	/** Pointer to the connector of the attached network driver. */
523	PPDMINETWORKUPR0 pDrv;
524	#ifdef PCNET_NO_POLLING
525	DECLR0CALLBACKMEMBER(int, pfnEMInterpretInstructionR0, (PVM pVM, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize));
526	#endif
527	} PCNETSTATER0;
528	/** Pointer to a PCnet state structure for ring-0. */
529	typedef PCNETSTATER0 *PPCNETSTATER0;
530
531
532	/**
533	* PCNET state for raw-mode.
534	*/
535	typedef struct PCNETSTATERC
536	{
537	/** Pointer to the connector of the attached network driver. */
538	PPDMINETWORKUPRC pDrv;
539	#ifdef PCNET_NO_POLLING
540	DECLRCCALLBACKMEMBER(int, pfnEMInterpretInstructionRC, (PVM pVM, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize));
541	#endif
542	} PCNETSTATERC;
543	/** Pointer to a PCnet state structure for raw-mode. */
544	typedef PCNETSTATERC *PPCNETSTATERC;
545
546
547	/** The PCnet state structure for the current context. */
548	typedef CTX_SUFF(PCNETSTATE) PCNETSTATECC;
549	/** Pointer to a PCnet state structure for the current context. */
550	typedef CTX_SUFF(PPCNETSTATE) PPCNETSTATECC;
551
552
553	/** @todo All structs: big endian? */
554
555	struct INITBLK16
556	{
557	uint16_t mode; /*< copied into csr15 /
558	uint16_t padr1; /*< MAC 0..15 /
559	uint16_t padr2; /*< MAC 16..32 /
560	uint16_t padr3; /*< MAC 33..47 /
561	uint16_t ladrf1; /*< logical address filter 0..15 /
562	uint16_t ladrf2; /*< logical address filter 16..31 /
563	uint16_t ladrf3; /*< logical address filter 32..47 /
564	uint16_t ladrf4; /*< logical address filter 48..63 /
565	uint32_t rdra:24; /*< address of receive descriptor ring /
566	uint32_t res1:5; /*< reserved /
567	uint32_t rlen:3; /*< number of receive descriptor ring entries /
568	uint32_t tdra:24; /*< address of transmit descriptor ring /
569	uint32_t res2:5; /*< reserved /
570	uint32_t tlen:3; /*< number of transmit descriptor ring entries /
571	};
572	AssertCompileSize(INITBLK16, 24);
573
574	/** bird: I've changed the type for the bitfields. They should only be 16-bit all together.
575	* frank: I've changed the bitfiled types to uint32_t to prevent compiler warnings. */
576	struct INITBLK32
577	{
578	uint16_t mode; /*< copied into csr15 /
579	uint16_t res1:4; /*< reserved /
580	uint16_t rlen:4; /*< number of receive descriptor ring entries /
581	uint16_t res2:4; /*< reserved /
582	uint16_t tlen:4; /*< number of transmit descriptor ring entries /
583	uint16_t padr1; /*< MAC 0..15 /
584	uint16_t padr2; /*< MAC 16..31 /
585	uint16_t padr3; /*< MAC 32..47 /
586	uint16_t res3; /*< reserved /
587	uint16_t ladrf1; /*< logical address filter 0..15 /
588	uint16_t ladrf2; /*< logical address filter 16..31 /
589	uint16_t ladrf3; /*< logical address filter 32..47 /
590	uint16_t ladrf4; /*< logical address filter 48..63 /
591	uint32_t rdra; /*< address of receive descriptor ring /
592	uint32_t tdra; /*< address of transmit descriptor ring /
593	};
594	AssertCompileSize(INITBLK32, 28);
595
596	/** Transmit Message Descriptor */
597	typedef struct TMD
598	{
599	struct
600	{
601	uint32_t tbadr; /*< transmit buffer address /
602	} tmd0;
603	struct
604	{
605	uint32_t bcnt:12; /*< buffer byte count (two's complement) /
606	uint32_t ones:4; /*< must be 1111b /
607	uint32_t res:7; /*< reserved /
608	uint32_t bpe:1; /*< bus parity error /
609	uint32_t enp:1; /*< end of packet /
610	uint32_t stp:1; /*< start of packet /
611	uint32_t def:1; /*< deferred /
612	uint32_t one:1; /*< exactly one retry was needed to transmit a frame /
613	uint32_t ltint:1; /*< suppress interrupts after successful transmission /
614	uint32_t nofcs:1; /**< when set, the state of DXMTFCS is ignored and
615	transmitter FCS generation is activated. */
616	uint32_t err:1; /*< error occurred /
617	uint32_t own:1; /*< 0=owned by guest driver, 1=owned by controller /
618	} tmd1;
619	struct
620	{
621	uint32_t trc:4; /*< transmit retry count /
622	uint32_t res:12; /*< reserved /
623	uint32_t tdr:10; /*< ??? /
624	uint32_t rtry:1; /*< retry error /
625	uint32_t lcar:1; /*< loss of carrier /
626	uint32_t lcol:1; /*< late collision /
627	uint32_t exdef:1; /*< excessive deferral /
628	uint32_t uflo:1; /*< underflow error /
629	uint32_t buff:1; /*< out of buffers (ENP not found) /
630	} tmd2;
631	struct
632	{
633	uint32_t res; /*< reserved for user defined space /
634	} tmd3;
635	} TMD;
636	AssertCompileSize(TMD, 16);
637
638	/** Receive Message Descriptor */
639	typedef struct RMD
640	{
641	struct
642	{
643	uint32_t rbadr; /*< receive buffer address /
644	} rmd0;
645	struct
646	{
647	uint32_t bcnt:12; /*< buffer byte count (two's complement) /
648	uint32_t ones:4; /*< must be 1111b /
649	uint32_t res:4; /*< reserved /
650	uint32_t bam:1; /*< broadcast address match /
651	uint32_t lafm:1; /*< logical filter address match /
652	uint32_t pam:1; /*< physical address match /
653	uint32_t bpe:1; /*< bus parity error /
654	uint32_t enp:1; /*< end of packet /
655	uint32_t stp:1; /*< start of packet /
656	uint32_t buff:1; /*< buffer error /
657	uint32_t crc:1; /*< crc error on incoming frame /
658	uint32_t oflo:1; /*< overflow error (lost all or part of incoming frame) /
659	uint32_t fram:1; /*< frame error /
660	uint32_t err:1; /*< error occurred /
661	uint32_t own:1; /*< 0=owned by guest driver, 1=owned by controller /
662	} rmd1;
663	struct
664	{
665	uint32_t mcnt:12; /*< message byte count /
666	uint32_t zeros:4; /*< 0000b /
667	uint32_t rpc:8; /*< receive frame tag /
668	uint32_t rcc:8; /*< receive frame tag + reserved /
669	} rmd2;
670	struct
671	{
672	uint32_t res; /*< reserved for user defined space /
673	} rmd3;
674	} RMD;
675	AssertCompileSize(RMD, 16);
676
677
678	#ifndef VBOX_DEVICE_STRUCT_TESTCASE
679
680
681	/*********************************************************************************************************************************
682	* Internal Functions *
683	*********************************************************************************************************************************/
684	static void pcnetPollRxTx(PPDMDEVINS pDevIns, PPCNETSTATE pThis, PPCNETSTATECC pThisCC);
685	static void pcnetPollTimer(PPDMDEVINS pDevIns, PPCNETSTATE pThis, PPCNETSTATECC pThisCC);
686	static void pcnetUpdateIrq(PPDMDEVINS pDevIns, PPCNETSTATE pThis);
687	static uint32_t pcnetBCRReadU16(PPCNETSTATE pThis, uint32_t u32RAP);
688	static VBOXSTRICTRC pcnetBCRWriteU16(PPDMDEVINS pDevIns, PPCNETSTATE pThis, uint32_t u32RAP, uint32_t val);
689	#ifndef PCNET_NO_POLLING
690	static void pcnetPollTimerStart(PPDMDEVINS pDevIns, PPCNETSTATE pThis);
691	#endif
692	static int pcnetXmitPending(PPDMDEVINS pDevIns, PPCNETSTATE pThis, PPCNETSTATECC pThisCC, bool fOnWorkerThread);
693	#ifdef PCNET_NO_POLLING
694	# ifndef IN_RING3
695	RT_C_DECLS_BEGIN
696	DECLEXPORT(FNPGMRZPHYSPFHANDLER) pcnetHandleRingWritePf;
697	RT_C_DECLS_END
698	# endif
699	#endif
700
701	#define PRINT_TMD(T) Log10(( \
702	"TMD0 : TBADR=%#010x\n" \
703	"TMD1 : OWN=%d, ERR=%d, FCS=%d, LTI=%d, " \
704	"ONE=%d, DEF=%d, STP=%d, ENP=%d,\n" \
705	" BPE=%d, BCNT=%d\n" \
706	"TMD2 : BUF=%d, UFL=%d, EXD=%d, LCO=%d, " \
707	"LCA=%d, RTR=%d,\n" \
708	" TDR=%d, TRC=%d\n", \
709	(T)->tmd0.tbadr, \
710	(T)->tmd1.own, (T)->tmd1.err, (T)->tmd1.nofcs, \
711	(T)->tmd1.ltint, (T)->tmd1.one, (T)->tmd1.def, \
712	(T)->tmd1.stp, (T)->tmd1.enp, (T)->tmd1.bpe, \
713	4096-(T)->tmd1.bcnt, \
714	(T)->tmd2.buff, (T)->tmd2.uflo, (T)->tmd2.exdef,\
715	(T)->tmd2.lcol, (T)->tmd2.lcar, (T)->tmd2.rtry, \
716	(T)->tmd2.tdr, (T)->tmd2.trc))
717
718	#define PRINT_RMD(R) Log9(( \
719	"RMD0 : RBADR=%#010x\n" \
720	"RMD1 : OWN=%d, ERR=%d, FRAM=%d, OFLO=%d, " \
721	"CRC=%d, BUFF=%d, STP=%d, ENP=%d,\n " \
722	"BPE=%d, PAM=%d, LAFM=%d, BAM=%d, ONES=%d, BCNT=%d\n" \
723	"RMD2 : RCC=%d, RPC=%d, MCNT=%d, ZEROS=%d\n", \
724	(R)->rmd0.rbadr, \
725	(R)->rmd1.own, (R)->rmd1.err, (R)->rmd1.fram, \
726	(R)->rmd1.oflo, (R)->rmd1.crc, (R)->rmd1.buff, \
727	(R)->rmd1.stp, (R)->rmd1.enp, (R)->rmd1.bpe, \
728	(R)->rmd1.pam, (R)->rmd1.lafm, (R)->rmd1.bam, \
729	(R)->rmd1.ones, 4096-(R)->rmd1.bcnt, \
730	(R)->rmd2.rcc, (R)->rmd2.rpc, (R)->rmd2.mcnt, \
731	(R)->rmd2.zeros))
732
733
734
735	/**
736	* Checks if the link is up.
737	* @returns true if the link is up.
738	* @returns false if the link is down.
739	*/
740	DECLINLINE(bool) pcnetIsLinkUp(PPCNETSTATE pThis)
741	{
742	return pThis->fDriverAttached && !pThis->fLinkTempDown && pThis->fLinkUp;
743	}
744
745	/**
746	* Memory write helper to handle PCI/ISA differences.
747	*
748	* @returns nothing.
749	* @param pDevIns The device instance.
750	* @param pThis Pointer to the PCNet device instance
751	* @param GCPhys Guest physical memory address
752	* @param pvBuf Host side buffer address
753	* @param cbWrite Number of bytes to write
754	*/
755	static void pcnetPhysWrite(PPDMDEVINS pDevIns, PPCNETSTATE pThis, RTGCPHYS GCPhys, const void *pvBuf, size_t cbWrite)
756	{
757	if (!PCNET_IS_ISA(pThis))
758	PDMDevHlpPCIPhysWrite(pDevIns, GCPhys, pvBuf, cbWrite);
759	else
760	PDMDevHlpPhysWrite(pDevIns, GCPhys, pvBuf, cbWrite);
761	}
762
763	/**
764	* Load transmit message descriptor
765	* Make sure we read the own flag first.
766	*
767	* @param pDevIns The device instance.
768	* @param pThis adapter private data
769	* @param addr physical address of the descriptor
770	* @param fRetIfNotOwn return immediately after reading the own flag if we don't own the descriptor
771	* @return true if we own the descriptor, false otherwise
772	*/
773	DECLINLINE(bool) pcnetTmdLoad(PPDMDEVINS pDevIns, PPCNETSTATE pThis, TMD *tmd, RTGCPHYS32 addr, bool fRetIfNotOwn)
774	{
775	uint8_t ownbyte;
776
777	if (RT_UNLIKELY(BCR_SWSTYLE(pThis) == 0))
778	{
779	uint16_t xda[4];
780
781	PDMDevHlpPhysRead(pDevIns, addr+3, &ownbyte, 1);
782	if (!(ownbyte & 0x80) && fRetIfNotOwn)
783	return false;
784	PDMDevHlpPhysRead(pDevIns, addr, (void*)&xda[0], sizeof(xda));
785	((uint32_t *)tmd)[0] = (uint32_t)xda[0] \| ((uint32_t)(xda[1] & 0x00ff) << 16);
786	((uint32_t *)tmd)[1] = (uint32_t)xda[2] \| ((uint32_t)(xda[1] & 0xff00) << 16);
787	((uint32_t *)tmd)[2] = (uint32_t)xda[3] << 16;
788	((uint32_t *)tmd)[3] = 0;
789	}
790	else if (RT_LIKELY(BCR_SWSTYLE(pThis) != 3))
791	{
792	PDMDevHlpPhysRead(pDevIns, addr+7, &ownbyte, 1);
793	if (!(ownbyte & 0x80) && fRetIfNotOwn)
794	return false;
795	PDMDevHlpPhysRead(pDevIns, addr, (void*)tmd, 16);
796	}
797	else
798	{
799	uint32_t xda[4];
800	PDMDevHlpPhysRead(pDevIns, addr+7, &ownbyte, 1);
801	if (!(ownbyte & 0x80) && fRetIfNotOwn)
802	return false;
803	PDMDevHlpPhysRead(pDevIns, addr, (void*)&xda[0], sizeof(xda));
804	((uint32_t *)tmd)[0] = xda[2];
805	((uint32_t *)tmd)[1] = xda[1];
806	((uint32_t *)tmd)[2] = xda[0];
807	((uint32_t *)tmd)[3] = xda[3];
808	}
809	/* Double check the own bit; guest drivers might be buggy and lock prefixes in the recompiler are ignored by other threads. */
810	#ifdef DEBUG
811	if (tmd->tmd1.own == 1 && !(ownbyte & 0x80))
812	Log(("pcnetTmdLoad: own bit flipped while reading!!\n"));
813	#endif
814	if (!(ownbyte & 0x80))
815	tmd->tmd1.own = 0;
816
817	return !!tmd->tmd1.own;
818	}
819
820	/**
821	* Store transmit message descriptor and hand it over to the host (the VM guest).
822	* Make sure that all data are transmitted before we clear the own flag.
823	*/
824	DECLINLINE(void) pcnetTmdStorePassHost(PPDMDEVINS pDevIns, PPCNETSTATE pThis, TMD *tmd, RTGCPHYS32 addr)
825	{
826	STAM_PROFILE_ADV_START(&pThis->CTX_SUFF_Z(StatTmdStore), a);
827	if (RT_UNLIKELY(BCR_SWSTYLE(pThis) == 0))
828	{
829	uint16_t xda[4];
830	xda[0] = ((uint32_t *)tmd)[0] & 0xffff;
831	xda[1] = ((((uint32_t )tmd)[0] >> 16) & 0xff) \| ((((uint32_t )tmd)[1]>>16) & 0xff00);
832	xda[2] = ((uint32_t *)tmd)[1] & 0xffff;
833	xda[3] = ((uint32_t *)tmd)[2] >> 16;
834	xda[1] \|= 0x8000;
835	pcnetPhysWrite(pDevIns, pThis, addr, (void*)&xda[0], sizeof(xda));
836	xda[1] &= ~0x8000;
837	pcnetPhysWrite(pDevIns, pThis, addr+3, (uint8_t*)xda + 3, 1);
838	}
839	else if (RT_LIKELY(BCR_SWSTYLE(pThis) != 3))
840	{
841	((uint32_t*)tmd)[1] \|= 0x80000000;
842	pcnetPhysWrite(pDevIns, pThis, addr, (void*)tmd, 12);
843	((uint32_t*)tmd)[1] &= ~0x80000000;
844	pcnetPhysWrite(pDevIns, pThis, addr+7, (uint8_t*)tmd + 7, 1);
845	}
846	else
847	{
848	uint32_t xda[3];
849	xda[0] = ((uint32_t *)tmd)[2];
850	xda[1] = ((uint32_t *)tmd)[1];
851	xda[2] = ((uint32_t *)tmd)[0];
852	xda[1] \|= 0x80000000;
853	pcnetPhysWrite(pDevIns, pThis, addr, (void*)&xda[0], sizeof(xda));
854	xda[1] &= ~0x80000000;
855	pcnetPhysWrite(pDevIns, pThis, addr+7, (uint8_t*)xda + 7, 1);
856	}
857	STAM_PROFILE_ADV_STOP(&pThis->CTX_SUFF_Z(StatTmdStore), a);
858	}
859
860	/**
861	* Load receive message descriptor
862	*
863	* Make sure we read the own flag first.
864	*
865	* @param pDevIns The device instance.
866	* @param pThis Adapter private data.
867	* @param addr Physical address of the descriptor.
868	* @param fRetIfNotOwn Return immediately after reading the own flag if we
869	* don't own the descriptor.
870	* @returns true if we own the descriptor, false otherwise
871	*/
872	DECLINLINE(bool) pcnetRmdLoad(PPDMDEVINS pDevIns, PPCNETSTATE pThis, RMD *rmd, RTGCPHYS32 addr, bool fRetIfNotOwn)
873	{
874	uint8_t ownbyte;
875
876	if (RT_UNLIKELY(BCR_SWSTYLE(pThis) == 0))
877	{
878	uint16_t rda[4];
879	PDMDevHlpPhysRead(pDevIns, addr+3, &ownbyte, 1);
880	if (!(ownbyte & 0x80) && fRetIfNotOwn)
881	return false;
882	PDMDevHlpPhysRead(pDevIns, addr, (void*)&rda[0], sizeof(rda));
883	((uint32_t *)rmd)[0] = (uint32_t)rda[0] \| ((rda[1] & 0x00ff) << 16);
884	((uint32_t *)rmd)[1] = (uint32_t)rda[2] \| ((rda[1] & 0xff00) << 16);
885	((uint32_t *)rmd)[2] = (uint32_t)rda[3];
886	((uint32_t *)rmd)[3] = 0;
887	}
888	else if (RT_LIKELY(BCR_SWSTYLE(pThis) != 3))
889	{
890	PDMDevHlpPhysRead(pDevIns, addr+7, &ownbyte, 1);
891	if (!(ownbyte & 0x80) && fRetIfNotOwn)
892	return false;
893	PDMDevHlpPhysRead(pDevIns, addr, (void*)rmd, 16);
894	}
895	else
896	{
897	uint32_t rda[4];
898	PDMDevHlpPhysRead(pDevIns, addr+7, &ownbyte, 1);
899	if (!(ownbyte & 0x80) && fRetIfNotOwn)
900	return false;
901	PDMDevHlpPhysRead(pDevIns, addr, (void*)&rda[0], sizeof(rda));
902	((uint32_t *)rmd)[0] = rda[2];
903	((uint32_t *)rmd)[1] = rda[1];
904	((uint32_t *)rmd)[2] = rda[0];
905	((uint32_t *)rmd)[3] = rda[3];
906	}
907	/* Double check the own bit; guest drivers might be buggy and lock prefixes in the recompiler are ignored by other threads. */
908	#ifdef DEBUG
909	if (rmd->rmd1.own == 1 && !(ownbyte & 0x80))
910	Log(("pcnetRmdLoad: own bit flipped while reading!!\n"));
911	#endif
912	if (!(ownbyte & 0x80))
913	rmd->rmd1.own = 0;
914
915	return !!rmd->rmd1.own;
916	}
917
918
919	/**
920	* Store receive message descriptor and hand it over to the host (the VM guest).
921	* Make sure that all data are transmitted before we clear the own flag.
922	*/
923	DECLINLINE(void) pcnetRmdStorePassHost(PPDMDEVINS pDevIns, PPCNETSTATE pThis, RMD *rmd, RTGCPHYS32 addr)
924	{
925	if (RT_UNLIKELY(BCR_SWSTYLE(pThis) == 0))
926	{
927	uint16_t rda[4];
928	rda[0] = ((uint32_t *)rmd)[0] & 0xffff;
929	rda[1] = ((((uint32_t )rmd)[0]>>16) & 0xff) \| ((((uint32_t )rmd)[1]>>16) & 0xff00);
930	rda[2] = ((uint32_t *)rmd)[1] & 0xffff;
931	rda[3] = ((uint32_t *)rmd)[2] & 0xffff;
932	rda[1] \|= 0x8000;
933	pcnetPhysWrite(pDevIns, pThis, addr, (void*)&rda[0], sizeof(rda));
934	rda[1] &= ~0x8000;
935	pcnetPhysWrite(pDevIns, pThis, addr+3, (uint8_t*)rda + 3, 1);
936	}
937	else if (RT_LIKELY(BCR_SWSTYLE(pThis) != 3))
938	{
939	((uint32_t*)rmd)[1] \|= 0x80000000;
940	pcnetPhysWrite(pDevIns, pThis, addr, (void*)rmd, 12);
941	((uint32_t*)rmd)[1] &= ~0x80000000;
942	pcnetPhysWrite(pDevIns, pThis, addr+7, (uint8_t*)rmd + 7, 1);
943	}
944	else
945	{
946	uint32_t rda[3];
947	rda[0] = ((uint32_t *)rmd)[2];
948	rda[1] = ((uint32_t *)rmd)[1];
949	rda[2] = ((uint32_t *)rmd)[0];
950	rda[1] \|= 0x80000000;
951	pcnetPhysWrite(pDevIns, pThis, addr, (void*)&rda[0], sizeof(rda));
952	rda[1] &= ~0x80000000;
953	pcnetPhysWrite(pDevIns, pThis, addr+7, (uint8_t*)rda + 7, 1);
954	}
955	}
956
957	#ifdef IN_RING3
958	/**
959	* Read+Write a TX/RX descriptor to prevent PDMDevHlpPCIPhysWrite() allocating
960	* pages later when we shouldn't schedule to EMT. Temporarily hack.
961	*/
962	static void pcnetDescTouch(PPDMDEVINS pDevIns, PPCNETSTATE pThis, RTGCPHYS32 addr)
963	{
964	uint8_t aBuf[16];
965	size_t cbDesc;
966	if (RT_UNLIKELY(BCR_SWSTYLE(pThis) == 0))
967	cbDesc = 8;
968	else
969	cbDesc = 16;
970	PDMDevHlpPhysRead(pDevIns, addr, aBuf, cbDesc);
971	pcnetPhysWrite(pDevIns, pThis, addr, aBuf, cbDesc);
972	}
973	#endif /* IN_RING3 */
974
975	/** Checks if it's a bad (as in invalid) RMD.*/
976	#define IS_RMD_BAD(rmd) ((rmd).rmd1.ones != 15)
977
978	/** The network card is the owner of the RDTE/TDTE, actually it is this driver */
979	#define CARD_IS_OWNER(desc) (((desc) & 0x8000))
980
981	/** The host is the owner of the RDTE/TDTE -- actually the VM guest. */
982	#define HOST_IS_OWNER(desc) (!((desc) & 0x8000))
983
984	#ifndef ETHER_IS_MULTICAST /* Net/Open BSD macro it seems */
985	#define ETHER_IS_MULTICAST(a) (((uint8_t )(a)) & 1)
986	#endif
987
988	#define ETHER_ADDR_LEN ETH_ALEN
989	#define ETH_ALEN 6
990	#pragma pack(1)
991	struct ether_header /** @todo Use RTNETETHERHDR */
992	{
993	uint8_t ether_dhost[ETH_ALEN]; /*< destination ethernet address /
994	uint8_t ether_shost[ETH_ALEN]; /*< source ethernet address /
995	uint16_t ether_type; /*< packet type ID field /
996	};
997	#pragma pack()
998
999	#define PRINT_PKTHDR(BUF) do { \
1000	struct ether_header hdr = (struct ether_header )(BUF); \
1001	Log12(("#%d packet dhost=%02x:%02x:%02x:%02x:%02x:%02x, shost=%02x:%02x:%02x:%02x:%02x:%02x, type=%#06x (bcast=%d)\n", \
1002	PCNET_INST_NR, \
1003	hdr->ether_dhost[0],hdr->ether_dhost[1],hdr->ether_dhost[2], \
1004	hdr->ether_dhost[3],hdr->ether_dhost[4],hdr->ether_dhost[5], \
1005	hdr->ether_shost[0],hdr->ether_shost[1],hdr->ether_shost[2], \
1006	hdr->ether_shost[3],hdr->ether_shost[4],hdr->ether_shost[5], \
1007	htons(hdr->ether_type), \
1008	!!ETHER_IS_MULTICAST(hdr->ether_dhost))); \
1009	} while (0)
1010
1011
1012	#define MULTICAST_FILTER_LEN 8
1013
1014	DECLINLINE(uint32_t) lnc_mchash(const uint8_t *ether_addr)
1015	{
1016	#define LNC_POLYNOMIAL 0xEDB88320UL
1017	uint32_t crc = 0xFFFFFFFF;
1018	int idx, bit;
1019	uint8_t data;
1020
1021	for (idx = 0; idx < ETHER_ADDR_LEN; idx++)
1022	{
1023	for (data = *ether_addr++, bit = 0; bit < MULTICAST_FILTER_LEN; bit++)
1024	{
1025	crc = (crc >> 1) ^ (((crc ^ data) & 1) ? LNC_POLYNOMIAL : 0);
1026	data >>= 1;
1027	}
1028	}
1029	return crc;
1030	#undef LNC_POLYNOMIAL
1031	}
1032
1033	#define CRC(crc, ch) (crc = (crc >> 8) ^ crctab[(crc ^ (ch)) & 0xff])
1034
1035	/* generated using the AUTODIN II polynomial
1036	* x^32 + x^26 + x^23 + x^22 + x^16 +
1037	* x^12 + x^11 + x^10 + x^8 + x^7 + x^5 + x^4 + x^2 + x^1 + 1
1038	*/
1039	static const uint32_t crctab[256] =
1040	{
1041	0x00000000, 0x77073096, 0xee0e612c, 0x990951ba,
1042	0x076dc419, 0x706af48f, 0xe963a535, 0x9e6495a3,
1043	0x0edb8832, 0x79dcb8a4, 0xe0d5e91e, 0x97d2d988,
1044	0x09b64c2b, 0x7eb17cbd, 0xe7b82d07, 0x90bf1d91,
1045	0x1db71064, 0x6ab020f2, 0xf3b97148, 0x84be41de,
1046	0x1adad47d, 0x6ddde4eb, 0xf4d4b551, 0x83d385c7,
1047	0x136c9856, 0x646ba8c0, 0xfd62f97a, 0x8a65c9ec,
1048	0x14015c4f, 0x63066cd9, 0xfa0f3d63, 0x8d080df5,
1049	0x3b6e20c8, 0x4c69105e, 0xd56041e4, 0xa2677172,
1050	0x3c03e4d1, 0x4b04d447, 0xd20d85fd, 0xa50ab56b,
1051	0x35b5a8fa, 0x42b2986c, 0xdbbbc9d6, 0xacbcf940,
1052	0x32d86ce3, 0x45df5c75, 0xdcd60dcf, 0xabd13d59,
1053	0x26d930ac, 0x51de003a, 0xc8d75180, 0xbfd06116,
1054	0x21b4f4b5, 0x56b3c423, 0xcfba9599, 0xb8bda50f,
1055	0x2802b89e, 0x5f058808, 0xc60cd9b2, 0xb10be924,
1056	0x2f6f7c87, 0x58684c11, 0xc1611dab, 0xb6662d3d,
1057	0x76dc4190, 0x01db7106, 0x98d220bc, 0xefd5102a,
1058	0x71b18589, 0x06b6b51f, 0x9fbfe4a5, 0xe8b8d433,
1059	0x7807c9a2, 0x0f00f934, 0x9609a88e, 0xe10e9818,
1060	0x7f6a0dbb, 0x086d3d2d, 0x91646c97, 0xe6635c01,
1061	0x6b6b51f4, 0x1c6c6162, 0x856530d8, 0xf262004e,
1062	0x6c0695ed, 0x1b01a57b, 0x8208f4c1, 0xf50fc457,
1063	0x65b0d9c6, 0x12b7e950, 0x8bbeb8ea, 0xfcb9887c,
1064	0x62dd1ddf, 0x15da2d49, 0x8cd37cf3, 0xfbd44c65,
1065	0x4db26158, 0x3ab551ce, 0xa3bc0074, 0xd4bb30e2,
1066	0x4adfa541, 0x3dd895d7, 0xa4d1c46d, 0xd3d6f4fb,
1067	0x4369e96a, 0x346ed9fc, 0xad678846, 0xda60b8d0,
1068	0x44042d73, 0x33031de5, 0xaa0a4c5f, 0xdd0d7cc9,
1069	0x5005713c, 0x270241aa, 0xbe0b1010, 0xc90c2086,
1070	0x5768b525, 0x206f85b3, 0xb966d409, 0xce61e49f,
1071	0x5edef90e, 0x29d9c998, 0xb0d09822, 0xc7d7a8b4,
1072	0x59b33d17, 0x2eb40d81, 0xb7bd5c3b, 0xc0ba6cad,
1073	0xedb88320, 0x9abfb3b6, 0x03b6e20c, 0x74b1d29a,
1074	0xead54739, 0x9dd277af, 0x04db2615, 0x73dc1683,
1075	0xe3630b12, 0x94643b84, 0x0d6d6a3e, 0x7a6a5aa8,
1076	0xe40ecf0b, 0x9309ff9d, 0x0a00ae27, 0x7d079eb1,
1077	0xf00f9344, 0x8708a3d2, 0x1e01f268, 0x6906c2fe,
1078	0xf762575d, 0x806567cb, 0x196c3671, 0x6e6b06e7,
1079	0xfed41b76, 0x89d32be0, 0x10da7a5a, 0x67dd4acc,
1080	0xf9b9df6f, 0x8ebeeff9, 0x17b7be43, 0x60b08ed5,
1081	0xd6d6a3e8, 0xa1d1937e, 0x38d8c2c4, 0x4fdff252,
1082	0xd1bb67f1, 0xa6bc5767, 0x3fb506dd, 0x48b2364b,
1083	0xd80d2bda, 0xaf0a1b4c, 0x36034af6, 0x41047a60,
1084	0xdf60efc3, 0xa867df55, 0x316e8eef, 0x4669be79,
1085	0xcb61b38c, 0xbc66831a, 0x256fd2a0, 0x5268e236,
1086	0xcc0c7795, 0xbb0b4703, 0x220216b9, 0x5505262f,
1087	0xc5ba3bbe, 0xb2bd0b28, 0x2bb45a92, 0x5cb36a04,
1088	0xc2d7ffa7, 0xb5d0cf31, 0x2cd99e8b, 0x5bdeae1d,
1089	0x9b64c2b0, 0xec63f226, 0x756aa39c, 0x026d930a,
1090	0x9c0906a9, 0xeb0e363f, 0x72076785, 0x05005713,
1091	0x95bf4a82, 0xe2b87a14, 0x7bb12bae, 0x0cb61b38,
1092	0x92d28e9b, 0xe5d5be0d, 0x7cdcefb7, 0x0bdbdf21,
1093	0x86d3d2d4, 0xf1d4e242, 0x68ddb3f8, 0x1fda836e,
1094	0x81be16cd, 0xf6b9265b, 0x6fb077e1, 0x18b74777,
1095	0x88085ae6, 0xff0f6a70, 0x66063bca, 0x11010b5c,
1096	0x8f659eff, 0xf862ae69, 0x616bffd3, 0x166ccf45,
1097	0xa00ae278, 0xd70dd2ee, 0x4e048354, 0x3903b3c2,
1098	0xa7672661, 0xd06016f7, 0x4969474d, 0x3e6e77db,
1099	0xaed16a4a, 0xd9d65adc, 0x40df0b66, 0x37d83bf0,
1100	0xa9bcae53, 0xdebb9ec5, 0x47b2cf7f, 0x30b5ffe9,
1101	0xbdbdf21c, 0xcabac28a, 0x53b39330, 0x24b4a3a6,
1102	0xbad03605, 0xcdd70693, 0x54de5729, 0x23d967bf,
1103	0xb3667a2e, 0xc4614ab8, 0x5d681b02, 0x2a6f2b94,
1104	0xb40bbe37, 0xc30c8ea1, 0x5a05df1b, 0x2d02ef8d,
1105	};
1106
1107	DECLINLINE(int) padr_match(PPCNETSTATE pThis, const uint8_t *buf, size_t size)
1108	{
1109	struct ether_header hdr = (struct ether_header )buf;
1110	int result;
1111	#if defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)
1112	result = !CSR_DRCVPA(pThis) && !memcmp(hdr->ether_dhost, pThis->aCSR + 12, 6);
1113	#else
1114	uint8_t padr[6];
1115	padr[0] = pThis->aCSR[12] & 0xff;
1116	padr[1] = pThis->aCSR[12] >> 8;
1117	padr[2] = pThis->aCSR[13] & 0xff;
1118	padr[3] = pThis->aCSR[13] >> 8;
1119	padr[4] = pThis->aCSR[14] & 0xff;
1120	padr[5] = pThis->aCSR[14] >> 8;
1121	result = !CSR_DRCVPA(pThis) && !memcmp(hdr->ether_dhost, padr, 6);
1122	#endif
1123
1124	Log11(("#%d packet dhost=%02x:%02x:%02x:%02x:%02x:%02x, padr=%02x:%02x:%02x:%02x:%02x:%02x => %d\n", PCNET_INST_NR,
1125	hdr->ether_dhost[0],hdr->ether_dhost[1],hdr->ether_dhost[2],
1126	hdr->ether_dhost[3],hdr->ether_dhost[4],hdr->ether_dhost[5],
1127	pThis->aCSR[12] & 0xff, pThis->aCSR[12] >> 8,
1128	pThis->aCSR[13] & 0xff, pThis->aCSR[13] >> 8,
1129	pThis->aCSR[14] & 0xff, pThis->aCSR[14] >> 8, result));
1130	RT_NOREF_PV(size);
1131	return result;
1132	}
1133
1134	DECLINLINE(int) padr_bcast(PPCNETSTATE pThis, const uint8_t *buf, size_t size)
1135	{
1136	static uint8_t aBCAST[6] = { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff };
1137	struct ether_header hdr = (struct ether_header )buf;
1138	int result = !CSR_DRCVBC(pThis) && !memcmp(hdr->ether_dhost, aBCAST, 6);
1139	Log11(("#%d padr_bcast result=%d\n", PCNET_INST_NR, result));
1140	RT_NOREF_PV(size);
1141	return result;
1142	}
1143
1144	static int ladr_match(PPCNETSTATE pThis, const uint8_t *buf, size_t size)
1145	{
1146	struct ether_header hdr = (struct ether_header )buf;
1147	if (RT_UNLIKELY(hdr->ether_dhost[0] & 0x01) && ((uint64_t *)&pThis->aCSR[8])[0] != 0LL)
1148	{
1149	int index;
1150	#if defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)
1151	index = lnc_mchash(hdr->ether_dhost) >> 26;
1152	return ((uint8_t*)(pThis->aCSR + 8))[index >> 3] & (1 << (index & 7));
1153	#else
1154	uint8_t ladr[8];
1155	ladr[0] = pThis->aCSR[8] & 0xff;
1156	ladr[1] = pThis->aCSR[8] >> 8;
1157	ladr[2] = pThis->aCSR[9] & 0xff;
1158	ladr[3] = pThis->aCSR[9] >> 8;
1159	ladr[4] = pThis->aCSR[10] & 0xff;
1160	ladr[5] = pThis->aCSR[10] >> 8;
1161	ladr[6] = pThis->aCSR[11] & 0xff;
1162	ladr[7] = pThis->aCSR[11] >> 8;
1163	index = lnc_mchash(hdr->ether_dhost) >> 26;
1164	return (ladr[index >> 3] & (1 << (index & 7)));
1165	#endif
1166	}
1167	RT_NOREF_PV(size);
1168	return 0;
1169	}
1170
1171
1172	/**
1173	* Get the receive descriptor ring address with a given index.
1174	*/
1175	DECLINLINE(RTGCPHYS32) pcnetRdraAddr(PPCNETSTATE pThis, int idx)
1176	{
1177	return pThis->GCRDRA + ((CSR_RCVRL(pThis) - idx) << pThis->iLog2DescSize);
1178	}
1179
1180	/**
1181	* Get the transmit descriptor ring address with a given index.
1182	*/
1183	DECLINLINE(RTGCPHYS32) pcnetTdraAddr(PPCNETSTATE pThis, int idx)
1184	{
1185	return pThis->GCTDRA + ((CSR_XMTRL(pThis) - idx) << pThis->iLog2DescSize);
1186	}
1187
1188
1189	#undef htonl
1190	#define htonl(x) ASMByteSwapU32(x)
1191	#undef htons
1192	#define htons(x) ( (((x) & 0xff00) >> 8) \| (((x) & 0x00ff) << 8) )
1193
1194
1195
1196	#ifdef PCNET_NO_POLLING
1197
1198	# ifndef IN_RING3
1199	/**
1200	* @callback_method_impl{FNPGMRZPHYSPFHANDLER,
1201	* \#PF write access handler for a PCNET ring.}
1202	*
1203	* @remarks The @a pvUser argument points to the PCNETSTATE.
1204	*/
1205	DECLEXPORT(int) pcnetHandleRingWritePf(PVM pVM, PVMCPU pVCpu, RTGCUINT uErrorCode, PCPUMCTXCORE pRegFrame,
1206	RTGCPTR pvFault, RTGCPHYS GCPhysFault, void *pvUser)
1207	{
1208	PPCNETSTATE pThis = (PPCNETSTATE)pvUser;
1209
1210	Log(("#%d pcnetHandleRingWritePf: write to %#010x\n", PCNET_INST_NR, GCPhysFault));
1211
1212	uint32_t cb;
1213	int rc = pThis->CTX_SUFF(pfnEMInterpretInstruction)(pVM, pRegFrame, pvFault, &cb);
1214	if (RT_SUCCESS(rc) && cb)
1215	{
1216	if ( (GCPhysFault >= pThis->GCTDRA && GCPhysFault + cb < pcnetTdraAddr(pThis, 0))
1217	# ifdef PCNET_MONITOR_RECEIVE_RING
1218	\|\| (GCPhysFault >= pThis->GCRDRA && GCPhysFault + cb < pcnetRdraAddr(pThis, 0))
1219	# endif
1220	)
1221	{
1222	uint32_t offsetTDRA = (GCPhysFault - pThis->GCTDRA);
1223
1224	int rc = PDMDevHlpCritSectEnter(pDevIns, &pThis->CritSect, VERR_SEM_BUSY);
1225	if (RT_SUCCESS(rc))
1226	{
1227	STAM_COUNTER_INC(&pThis->CTX_SUFF(StatRingWrite));
1228
1229	/* Check if we can do something now */
1230	pcnetPollRxTx(pDevIns, pThis, pThisCC);
1231	pcnetUpdateIrq(pDevIns, pThis);
1232
1233	PDMDevHlpCritSectLeave(pDevIns, &pThis->CritSect);
1234	return VINF_SUCCESS;
1235	}
1236	}
1237	else
1238	{
1239	STAM_COUNTER_INC(&pThis->CTX_SUFF(StatRingWriteOutside));
1240	return VINF_SUCCESS; /* outside of the ring range */
1241	}
1242	}
1243	STAM_COUNTER_INC(&pThis->CTX_SUFF(StatRingWriteFailed)); ;
1244	return VINF_IOM_R3_MMIO_WRITE; /* handle in ring3 */
1245	}
1246	# endif /* !IN_RING3 */
1247
1248	/**
1249	* @callback_method_impl{FNPGMPHYSHANDLER,
1250	* Write access handler for a PCNET ring.}
1251	*/
1252	PGM_ALL_CB_DECL(VBOXSTRICTRC)
1253	pcnetHandleRingWrite(PVM pVM, PVMCPU pVCpu, RTGCPHYS GCPhys, void pvPhys, void pvBuf, size_t cbBuf,
1254	PGMACCESSTYPE enmAccessType, PGMACCESSORIGIN enmOrigin, void *pvUser)
1255	{
1256	PPDMDEVINS pDevIns = (PPDMDEVINS)pvUser;
1257	PPCNETSTATE pThis = PDMDEVINS_2_DATA(pDevIns, PPCNETSTATE);
1258
1259	Log(("#%d pcnetHandleRingWrite: write to %#010x\n", PCNET_INST_NR, GCPhys));
1260	# ifdef VBOX_WITH_STATISTICS
1261	STAM_COUNTER_INC(&pThis->CTX_SUFF(StatRingWrite));
1262	if (GCPhys >= pThis->GCRDRA && GCPhys < pcnetRdraAddr(pThis, 0))
1263	STAM_COUNTER_INC(&pThis->StatRCVRingWrite);
1264	else if (GCPhys >= pThis->GCTDRA && GCPhys < pcnetTdraAddr(pThis, 0))
1265	STAM_COUNTER_INC(&pThis->StatTXRingWrite);
1266	# endif
1267	/* Perform the actual write */
1268	memcpy((char *)pvPhys, pvBuf, cbBuf);
1269
1270	/* Writes done by our code don't require polling of course */
1271	if (PDMDevHlpCritSectIsOwner(pDevIns, &pThis->CritSect) == false)
1272	{
1273	if ( (GCPhys >= pThis->GCTDRA && GCPhys + cbBuf < pcnetTdraAddr(pThis, 0))
1274	# ifdef PCNET_MONITOR_RECEIVE_RING
1275	\|\| (GCPhys >= pThis->GCRDRA && GCPhys + cbBuf < pcnetRdraAddr(pThis, 0))
1276	# endif
1277	)
1278	{
1279	int rc = PDMDevHlpCritSectEnter(pDevIns, &pThis->CritSect, VERR_SEM_BUSY);
1280	AssertReleaseRC(rc);
1281	/* Check if we can do something now */
1282	pcnetPollRxTx(pDevIns, pThis, pThisCC);
1283	pcnetUpdateIrq(pDevIns, pThis);
1284	PDMDevHlpCritSectLeave(pDevIns, &pThis->CritSect);
1285	}
1286	}
1287	return VINF_SUCCESS;
1288	}
1289
1290	#endif /* PCNET_NO_POLLING */
1291
1292	static void pcnetSoftReset(PPCNETSTATE pThis)
1293	{
1294	Log(("#%d pcnetSoftReset:\n", PCNET_INST_NR));
1295
1296	pThis->u32Lnkst = 0x40;
1297	pThis->GCRDRA = 0;
1298	pThis->GCTDRA = 0;
1299	pThis->u32RAP = 0;
1300
1301	pThis->aCSR[0] = 0x0004;
1302	pThis->aCSR[3] = 0x0000;
1303	pThis->aCSR[4] = 0x0115;
1304	pThis->aCSR[5] = 0x0000;
1305	pThis->aCSR[6] = 0x0000;
1306	pThis->aCSR[8] = 0;
1307	pThis->aCSR[9] = 0;
1308	pThis->aCSR[10] = 0;
1309	pThis->aCSR[11] = 0;
1310	pThis->aCSR[12] = RT_LE2H_U16(((uint16_t *)&pThis->aPROM[0])[0]);
1311	pThis->aCSR[13] = RT_LE2H_U16(((uint16_t *)&pThis->aPROM[0])[1]);
1312	pThis->aCSR[14] = RT_LE2H_U16(((uint16_t *)&pThis->aPROM[0])[2]);
1313	pThis->aCSR[15] &= 0x21c4;
1314	CSR_RCVRC(pThis) = 1;
1315	CSR_XMTRC(pThis) = 1;
1316	CSR_RCVRL(pThis) = 1;
1317	CSR_XMTRL(pThis) = 1;
1318	pThis->aCSR[80] = 0x1410;
1319	switch (pThis->uDevType)
1320	{
1321	default:
1322	case DEV_AM79C970A:
1323	pThis->aCSR[88] = CSR_VERSION_LOW_79C970A;
1324	pThis->aCSR[89] = CSR_VERSION_HIGH;
1325	break;
1326	case DEV_AM79C973:
1327	pThis->aCSR[88] = CSR_VERSION_LOW_79C973;
1328	pThis->aCSR[89] = CSR_VERSION_HIGH;
1329	break;
1330	case DEV_AM79C960:
1331	case DEV_AM79C960_EB:
1332	pThis->aCSR[88] = CSR_VERSION_LOW_79C960;
1333	pThis->aCSR[89] = 0x0000;
1334	break;
1335	}
1336	pThis->aCSR[94] = 0x0000;
1337	pThis->aCSR[100] = 0x0200;
1338	pThis->aCSR[103] = 0x0105;
1339	CSR_MISSC(pThis) = 0;
1340	pThis->aCSR[114] = 0x0000;
1341	pThis->aCSR[122] = 0x0000;
1342	pThis->aCSR[124] = 0x0000;
1343	}
1344
1345	/**
1346	* Check if we have to send an interrupt to the guest. An interrupt can occur on
1347	* - csr0 (written quite often)
1348	* - csr4 (only written by pcnetSoftReset(), pcnetStop() or by the guest driver)
1349	* - csr5 (only written by pcnetSoftReset(), pcnetStop or by the driver guest)
1350	*/
1351	static void pcnetUpdateIrq(PPDMDEVINS pDevIns, PPCNETSTATE pThis)
1352	{
1353	int iISR = 0;
1354	uint16_t csr0 = pThis->aCSR[0];
1355
1356	csr0 &= ~0x0080; /* clear INTR */
1357
1358	STAM_PROFILE_ADV_START(&pThis->StatInterrupt, a);
1359
1360	/* Linux guests set csr4=0x0915
1361	* W2k guests set csr3=0x4940 (disable BABL, MERR, IDON, DXSUFLO */
1362
1363	#if 1
1364	if ( ( (csr0 & ~pThis->aCSR[3]) & 0x5f00)
1365	\|\| (((pThis->aCSR[4]>>1) & ~pThis->aCSR[4]) & 0x0115)
1366	\|\| (((pThis->aCSR[5]>>1) & pThis->aCSR[5]) & 0x0048))
1367	#else
1368	if ( ( !(pThis->aCSR[3] & 0x4000) && !!(csr0 & 0x4000)) /* BABL */
1369	\|\|( !(pThis->aCSR[3] & 0x1000) && !!(csr0 & 0x1000)) /* MISS */
1370	\|\|( !(pThis->aCSR[3] & 0x0100) && !!(csr0 & 0x0100)) /* IDON */
1371	\|\|( !(pThis->aCSR[3] & 0x0200) && !!(csr0 & 0x0200)) /* TINT */
1372	\|\|( !(pThis->aCSR[3] & 0x0400) && !!(csr0 & 0x0400)) /* RINT */
1373	\|\|( !(pThis->aCSR[3] & 0x0800) && !!(csr0 & 0x0800)) /* MERR */
1374	\|\|( !(pThis->aCSR[4] & 0x0001) && !!(pThis->aCSR[4] & 0x0002)) /* JAB */
1375	\|\|( !(pThis->aCSR[4] & 0x0004) && !!(pThis->aCSR[4] & 0x0008)) /* TXSTRT */
1376	\|\|( !(pThis->aCSR[4] & 0x0010) && !!(pThis->aCSR[4] & 0x0020)) /* RCVO */
1377	\|\|( !(pThis->aCSR[4] & 0x0100) && !!(pThis->aCSR[4] & 0x0200)) /* MFCO */
1378	\|\|(!!(pThis->aCSR[5] & 0x0040) && !!(pThis->aCSR[5] & 0x0080)) /* EXDINT */
1379	\|\|(!!(pThis->aCSR[5] & 0x0008) && !!(pThis->aCSR[5] & 0x0010)) /* MPINT */)
1380	#endif
1381	{
1382	iISR = !!(csr0 & 0x0040); /* CSR_INEA */
1383	csr0 \|= 0x0080; /* set INTR */
1384	}
1385
1386	#ifdef VBOX
1387	if (pThis->aCSR[4] & 0x0080) /* UINTCMD */
1388	{
1389	pThis->aCSR[4] &= ~0x0080; /* clear UINTCMD */
1390	pThis->aCSR[4] \|= 0x0040; /* set UINT */
1391	Log(("#%d user int\n", PCNET_INST_NR));
1392	}
1393	if (pThis->aCSR[4] & csr0 & 0x0040 /* CSR_INEA */)
1394	{
1395	csr0 \|= 0x0080; /* set INTR */
1396	iISR = 1;
1397	}
1398	#else /* !VBOX */
1399	if (!!(pThis->aCSR[4] & 0x0080) && CSR_INEA(pThis)) /* UINTCMD */
1400	{
1401	pThis->aCSR[4] &= ~0x0080;
1402	pThis->aCSR[4] \|= 0x0040; /* set UINT */
1403	csr0 \|= 0x0080; /* set INTR */
1404	iISR = 1;
1405	Log(("#%d user int\n", PCNET_INST_NR));
1406	}
1407	#endif /* !VBOX */
1408
1409	#if 1
1410	if (((pThis->aCSR[5]>>1) & pThis->aCSR[5]) & 0x0500)
1411	#else
1412	if ( (!!(pThis->aCSR[5] & 0x0400) && !!(pThis->aCSR[5] & 0x0800)) /* SINT */
1413	\|\|(!!(pThis->aCSR[5] & 0x0100) && !!(pThis->aCSR[5] & 0x0200)) /* SLPINT */)
1414	#endif
1415	{
1416	iISR = 1;
1417	csr0 \|= 0x0080; /* INTR */
1418	}
1419
1420	if ((pThis->aCSR[7] & 0x0C00) == 0x0C00) /* STINT + STINTE */
1421	iISR = 1;
1422
1423	pThis->aCSR[0] = csr0;
1424
1425	Log2(("#%d set irq iISR=%d\n", PCNET_INST_NR, iISR));
1426
1427	/* normal path is to _not_ change the IRQ status */
1428	if (RT_UNLIKELY(iISR != pThis->iISR))
1429	{
1430	if (!PCNET_IS_ISA(pThis))
1431	{
1432	Log(("#%d INTA=%d\n", PCNET_INST_NR, iISR));
1433	PDMDevHlpPCISetIrq(pDevIns, 0, iISR);
1434	}
1435	else
1436	{
1437	Log(("#%d IRQ=%d, state=%d\n", PCNET_INST_NR, pThis->uIsaIrq, iISR));
1438	PDMDevHlpISASetIrq(pDevIns, pThis->uIsaIrq, iISR);
1439	}
1440	pThis->iISR = iISR;
1441	}
1442	STAM_PROFILE_ADV_STOP(&pThis->StatInterrupt, a);
1443	}
1444
1445	#ifdef IN_RING3
1446
1447	# ifdef PCNET_NO_POLLING
1448	static void pcnetR3UpdateRingHandlers(PPCNETSTATE pThis)
1449	{
1450	PPDMDEVINS pDevIns = pDevIns;
1451	int rc;
1452
1453	Log(("pcnetR3UpdateRingHandlers TD %RX32 size %#x -> %RX32 ?size? %#x\n", pThis->TDRAPhysOld, pThis->cbTDRAOld, pThis->GCTDRA, pcnetTdraAddr(pThis, 0)));
1454	Log(("pcnetR3UpdateRingHandlers RX %RX32 size %#x -> %RX32 ?size? %#x\n", pThis->RDRAPhysOld, pThis->cbRDRAOld, pThis->GCRDRA, pcnetRdraAddr(pThis, 0)));
1455
1456	/** @todo unregister order not correct! */
1457
1458	# ifdef PCNET_MONITOR_RECEIVE_RING
1459	if (pThis->GCRDRA != pThis->RDRAPhysOld \|\| CSR_RCVRL(pThis) != pThis->cbRDRAOld)
1460	{
1461	if (pThis->RDRAPhysOld != 0)
1462	PGMHandlerPhysicalDeregister(PDMDevHlpGetVM(pDevIns),
1463	pThis->RDRAPhysOld & ~PAGE_OFFSET_MASK);
1464
1465	rc = PGMHandlerPhysicalRegister(PDMDevHlpGetVM(pDevIns),
1466	pThis->GCRDRA & ~PAGE_OFFSET_MASK,
1467	RT_ALIGN(pcnetRdraAddr(pThis, 0), PAGE_SIZE) - 1,
1468	pThis->hNoPollingHandlerType, pDevIns,
1469	pThis->pDevInsHC->pvInstanceDataHC,
1470	pThis->pDevInsHC->pvInstanceDataRC,
1471	"PCnet receive ring write access handler");
1472	AssertRC(rc);
1473
1474	pThis->RDRAPhysOld = pThis->GCRDRA;
1475	pThis->cbRDRAOld = pcnetRdraAddr(pThis, 0);
1476	}
1477	# endif /* PCNET_MONITOR_RECEIVE_RING */
1478
1479	# ifdef PCNET_MONITOR_RECEIVE_RING
1480	/* 3 possibilities:
1481	* 1) TDRA on different physical page as RDRA
1482	* 2) TDRA completely on same physical page as RDRA
1483	* 3) TDRA & RDRA overlap partly with different physical pages
1484	*/
1485	RTGCPHYS32 RDRAPageStart = pThis->GCRDRA & ~PAGE_OFFSET_MASK;
1486	RTGCPHYS32 RDRAPageEnd = (pcnetRdraAddr(pThis, 0) - 1) & ~PAGE_OFFSET_MASK;
1487	RTGCPHYS32 TDRAPageStart = pThis->GCTDRA & ~PAGE_OFFSET_MASK;
1488	RTGCPHYS32 TDRAPageEnd = (pcnetTdraAddr(pThis, 0) - 1) & ~PAGE_OFFSET_MASK;
1489
1490	if ( RDRAPageStart > TDRAPageEnd
1491	\|\| TDRAPageStart > RDRAPageEnd)
1492	{
1493	# endif /* PCNET_MONITOR_RECEIVE_RING */
1494	/* 1) */
1495	if (pThis->GCTDRA != pThis->TDRAPhysOld \|\| CSR_XMTRL(pThis) != pThis->cbTDRAOld)
1496	{
1497	if (pThis->TDRAPhysOld != 0)
1498	PGMHandlerPhysicalDeregister(PDMDevHlpGetVM(pDevIns),
1499	pThis->TDRAPhysOld & ~PAGE_OFFSET_MASK);
1500
1501	rc = PGMHandlerPhysicalRegister(PDMDevHlpGetVM(pDevIns),
1502	pThis->GCTDRA & ~PAGE_OFFSET_MASK,
1503	RT_ALIGN(pcnetTdraAddr(pThis, 0), PAGE_SIZE) - 1,
1504	pThis->hNoPollingHandlerType,
1505	pDevIns->pvInstanceDataR3,
1506	pDevIns->pvInstanceDataR0,
1507	pDevIns->pvInstanceDataRC,
1508	"PCnet transmit ring write access handler");
1509	AssertRC(rc);
1510
1511	pThis->TDRAPhysOld = pThis->GCTDRA;
1512	pThis->cbTDRAOld = pcnetTdraAddr(pThis, 0);
1513	}
1514	# ifdef PCNET_MONITOR_RECEIVE_RING
1515	}
1516	else
1517	if ( RDRAPageStart != TDRAPageStart
1518	&& ( TDRAPageStart == RDRAPageEnd
1519	\|\| TDRAPageEnd == RDRAPageStart
1520	)
1521	)
1522	{
1523	/* 3) */
1524	AssertFailed();
1525	}
1526	/* else 2) */
1527	# endif
1528	}
1529	# endif /* PCNET_NO_POLLING */
1530
1531	static void pcnetR3Init(PPDMDEVINS pDevIns, PPCNETSTATE pThis, PPCNETSTATECC pThisCC)
1532	{
1533	Log(("#%d pcnetR3Init: init_addr=%#010x\n", PCNET_INST_NR, PHYSADDR(pThis, CSR_IADR(pThis))));
1534
1535	/** @todo Documentation says that RCVRL and XMTRL are stored as two's complement!
1536	* Software is allowed to write these registers directly. */
1537	# define PCNET_INIT() do { \
1538	PDMDevHlpPhysRead(pDevIns, PHYSADDR(pThis, CSR_IADR(pThis)), \
1539	(uint8_t *)&initblk, sizeof(initblk)); \
1540	pThis->aCSR[15] = RT_LE2H_U16(initblk.mode); \
1541	CSR_RCVRL(pThis) = (initblk.rlen < 9) ? (1 << initblk.rlen) : 512; \
1542	CSR_XMTRL(pThis) = (initblk.tlen < 9) ? (1 << initblk.tlen) : 512; \
1543	pThis->aCSR[ 6] = (initblk.tlen << 12) \| (initblk.rlen << 8); \
1544	pThis->aCSR[ 8] = RT_LE2H_U16(initblk.ladrf1); \
1545	pThis->aCSR[ 9] = RT_LE2H_U16(initblk.ladrf2); \
1546	pThis->aCSR[10] = RT_LE2H_U16(initblk.ladrf3); \
1547	pThis->aCSR[11] = RT_LE2H_U16(initblk.ladrf4); \
1548	pThis->aCSR[12] = RT_LE2H_U16(initblk.padr1); \
1549	pThis->aCSR[13] = RT_LE2H_U16(initblk.padr2); \
1550	pThis->aCSR[14] = RT_LE2H_U16(initblk.padr3); \
1551	pThis->GCRDRA = PHYSADDR(pThis, initblk.rdra); \
1552	pThis->GCTDRA = PHYSADDR(pThis, initblk.tdra); \
1553	} while (0)
1554
1555	if (BCR_SSIZE32(pThis))
1556	{
1557	struct INITBLK32 initblk;
1558	pThis->GCUpperPhys = 0;
1559	PCNET_INIT();
1560	Log(("#%d initblk.rlen=%#04x, initblk.tlen=%#04x\n",
1561	PCNET_INST_NR, initblk.rlen, initblk.tlen));
1562	}
1563	else
1564	{
1565	struct INITBLK16 initblk;
1566	pThis->GCUpperPhys = (0xff00 & (uint32_t)pThis->aCSR[2]) << 16;
1567	PCNET_INIT();
1568	Log(("#%d initblk.rlen=%#04x, initblk.tlen=%#04x\n",
1569	PCNET_INST_NR, initblk.rlen, initblk.tlen));
1570	}
1571
1572	# undef PCNET_INIT
1573
1574	size_t cbRxBuffers = 0;
1575	for (int i = CSR_RCVRL(pThis); i >= 1; i--)
1576	{
1577	RMD rmd;
1578	RTGCPHYS32 rdaddr = PHYSADDR(pThis, pcnetRdraAddr(pThis, i));
1579
1580	pcnetDescTouch(pDevIns, pThis, rdaddr);
1581	/* At this time it is not guaranteed that the buffers are already initialized. */
1582	if (pcnetRmdLoad(pDevIns, pThis, &rmd, rdaddr, false))
1583	{
1584	uint32_t cbBuf = 4096U-rmd.rmd1.bcnt;
1585	cbRxBuffers += cbBuf;
1586	}
1587	}
1588
1589	for (int i = CSR_XMTRL(pThis); i >= 1; i--)
1590	{
1591	RTGCPHYS32 tdaddr = PHYSADDR(pThis, pcnetTdraAddr(pThis, i));
1592
1593	pcnetDescTouch(pDevIns, pThis, tdaddr);
1594	}
1595
1596	/*
1597	* Heuristics: The Solaris pcn driver allocates too few RX buffers (128 buffers of a
1598	* size of 128 bytes are 16KB in summary) leading to frequent RX buffer overflows. In
1599	* that case we don't signal RX overflows through the CSR0_MISS flag as the driver
1600	* re-initializes the device on every miss. Other guests use at least 32 buffers of
1601	* usually 1536 bytes and should therefore not run into condition. If they are still
1602	* short in RX buffers we notify this condition.
1603	*/
1604	pThis->fSignalRxMiss = (cbRxBuffers == 0 \|\| cbRxBuffers >= 32*_1K);
1605
1606	if (pThisCC->pDrv)
1607	pThisCC->pDrv->pfnSetPromiscuousMode(pThisCC->pDrv, CSR_PROM(pThis));
1608
1609	CSR_RCVRC(pThis) = CSR_RCVRL(pThis);
1610	CSR_XMTRC(pThis) = CSR_XMTRL(pThis);
1611
1612	# ifdef PCNET_NO_POLLING
1613	pcnetR3UpdateRingHandlers(pThis);
1614	# endif
1615
1616	/* Reset cached RX and TX states */
1617	CSR_CRST(pThis) = CSR_CRBC(pThis) = CSR_NRST(pThis) = CSR_NRBC(pThis) = 0;
1618	CSR_CXST(pThis) = CSR_CXBC(pThis) = CSR_NXST(pThis) = CSR_NXBC(pThis) = 0;
1619
1620	LogRel(("PCnet#%d: Init: SWSTYLE=%d GCRDRA=%#010x[%d] GCTDRA=%#010x[%d]%s\n",
1621	PCNET_INST_NR, BCR_SWSTYLE(pThis),
1622	pThis->GCRDRA, CSR_RCVRL(pThis), pThis->GCTDRA, CSR_XMTRL(pThis),
1623	!pThis->fSignalRxMiss ? " (CSR0_MISS disabled)" : ""));
1624
1625	if (pThis->GCRDRA & (pThis->iLog2DescSize - 1))
1626	LogRel(("PCnet#%d: Warning: Misaligned RDRA\n", PCNET_INST_NR));
1627	if (pThis->GCTDRA & (pThis->iLog2DescSize - 1))
1628	LogRel(("PCnet#%d: Warning: Misaligned TDRA\n", PCNET_INST_NR));
1629
1630	pThis->aCSR[0] \|= 0x0101; /* Initialization done */
1631	pThis->aCSR[0] &= ~0x0004; /* clear STOP bit */
1632	}
1633
1634	#endif /* IN_RING3 */
1635
1636	/**
1637	* Start RX/TX operation.
1638	*/
1639	static void pcnetStart(PPDMDEVINS pDevIns, PPCNETSTATE pThis)
1640	{
1641	Log(("#%d pcnetStart:\n", PCNET_INST_NR));
1642
1643	/* Reset any cached RX/TX descriptor state. */
1644	CSR_CRDA(pThis) = CSR_CRBA(pThis) = CSR_NRDA(pThis) = CSR_NRBA(pThis) = 0;
1645	CSR_CRBC(pThis) = CSR_NRBC(pThis) = CSR_CRST(pThis) = 0;
1646
1647	if (!CSR_DTX(pThis))
1648	pThis->aCSR[0] \|= 0x0010; /* set TXON */
1649	if (!CSR_DRX(pThis))
1650	pThis->aCSR[0] \|= 0x0020; /* set RXON */
1651	pThis->aCSR[0] &= ~0x0004; /* clear STOP bit */
1652	pThis->aCSR[0] \|= 0x0002; /* STRT */
1653	#ifndef PCNET_NO_POLLING
1654	pcnetPollTimerStart(pDevIns, pThis); /* start timer if it was stopped */
1655	#endif
1656	}
1657
1658	/**
1659	* Stop RX/TX operation.
1660	*/
1661	static void pcnetStop(PPDMDEVINS pDevIns, PPCNETSTATE pThis, PPCNETSTATECC pThisCC)
1662	{
1663	Log(("#%d pcnetStop:\n", PCNET_INST_NR));
1664	pThis->aCSR[0] = 0x0004;
1665	pThis->aCSR[4] &= ~0x02c2;
1666	pThis->aCSR[5] &= ~0x0011;
1667	pcnetPollTimer(pDevIns, pThis, pThisCC);
1668	}
1669
1670	/**
1671	* Wakes up a receive thread stuck waiting for buffers.
1672	*/
1673	static void pcnetWakeupReceive(PPDMDEVINS pDevIns)
1674	{
1675	PPCNETSTATE pThis = PDMDEVINS_2_DATA(pDevIns, PPCNETSTATE);
1676	STAM_COUNTER_INC(&pThis->StatRxOverflowWakeup);
1677	if (pThis->hEventOutOfRxSpace != NIL_SUPSEMEVENT)
1678	{
1679	int rc = PDMDevHlpSUPSemEventSignal(pDevIns, pThis->hEventOutOfRxSpace);
1680	AssertRC(rc);
1681	}
1682	}
1683
1684	/**
1685	* Poll Receive Descriptor Table Entry and cache the results in the appropriate registers.
1686	*
1687	* @note Once a descriptor belongs to the network card (this driver), it
1688	* cannot be changed by the host (the guest driver) anymore. Well, it
1689	* could but the results are undefined by definition.
1690	*
1691	* @param pDevIns The device instance.
1692	* @param pThis The shared PCnet state data.
1693	* @param fSkipCurrent if true, don't scan the current RDTE.
1694	*/
1695	static void pcnetRdtePoll(PPDMDEVINS pDevIns, PPCNETSTATE pThis, bool fSkipCurrent=false)
1696	{
1697	STAM_PROFILE_ADV_START(&pThis->CTX_SUFF_Z(StatRdtePoll), a);
1698	/* assume lack of a next receive descriptor */
1699	CSR_NRST(pThis) = 0;
1700
1701	if (RT_LIKELY(pThis->GCRDRA))
1702	{
1703	/*
1704	* The current receive message descriptor.
1705	*/
1706	RMD rmd;
1707	int i = CSR_RCVRC(pThis);
1708	RTGCPHYS32 addr;
1709
1710	if (i < 1)
1711	i = CSR_RCVRL(pThis);
1712
1713	if (!fSkipCurrent)
1714	{
1715	addr = pcnetRdraAddr(pThis, i);
1716	CSR_CRDA(pThis) = CSR_CRBA(pThis) = 0;
1717	CSR_CRBC(pThis) = CSR_CRST(pThis) = 0;
1718	if (!pcnetRmdLoad(pDevIns, pThis, &rmd, PHYSADDR(pThis, addr), true))
1719	{
1720	STAM_PROFILE_ADV_STOP(&pThis->CTX_SUFF_Z(StatRdtePoll), a);
1721	return;
1722	}
1723	if (RT_LIKELY(!IS_RMD_BAD(rmd)))
1724	{
1725	CSR_CRDA(pThis) = addr; /* Receive Descriptor Address */
1726	CSR_CRBA(pThis) = rmd.rmd0.rbadr; /* Receive Buffer Address */
1727	CSR_CRBC(pThis) = rmd.rmd1.bcnt; /* Receive Byte Count */
1728	CSR_CRST(pThis) = ((uint32_t )&rmd)[1] >> 16; / Receive Status */
1729	if (pThis->fMaybeOutOfSpace)
1730	pcnetWakeupReceive(pDevIns);
1731	}
1732	else
1733	{
1734	STAM_PROFILE_ADV_STOP(&pThis->CTX_SUFF_Z(StatRdtePoll), a);
1735	/* This is not problematic since we don't own the descriptor
1736	* We actually do own it, otherwise pcnetRmdLoad would have returned false.
1737	* Don't flood the release log with errors.
1738	*/
1739	if (++pThis->uCntBadRMD < 50)
1740	LogRel(("PCnet#%d: BAD RMD ENTRIES AT %#010x (i=%d)\n",
1741	PCNET_INST_NR, addr, i));
1742	return;
1743	}
1744	}
1745
1746	/*
1747	* The next descriptor.
1748	*/
1749	if (--i < 1)
1750	i = CSR_RCVRL(pThis);
1751	addr = pcnetRdraAddr(pThis, i);
1752	CSR_NRDA(pThis) = CSR_NRBA(pThis) = 0;
1753	CSR_NRBC(pThis) = 0;
1754	if (!pcnetRmdLoad(pDevIns, pThis, &rmd, PHYSADDR(pThis, addr), true))
1755	{
1756	STAM_PROFILE_ADV_STOP(&pThis->CTX_SUFF_Z(StatRdtePoll), a);
1757	return;
1758	}
1759	if (RT_LIKELY(!IS_RMD_BAD(rmd)))
1760	{
1761	CSR_NRDA(pThis) = addr; /* Receive Descriptor Address */
1762	CSR_NRBA(pThis) = rmd.rmd0.rbadr; /* Receive Buffer Address */
1763	CSR_NRBC(pThis) = rmd.rmd1.bcnt; /* Receive Byte Count */
1764	CSR_NRST(pThis) = ((uint32_t )&rmd)[1] >> 16; / Receive Status */
1765	}
1766	else
1767	{
1768	STAM_PROFILE_ADV_STOP(&pThis->CTX_SUFF_Z(StatRdtePoll), a);
1769	/* This is not problematic since we don't own the descriptor
1770	* We actually do own it, otherwise pcnetRmdLoad would have returned false.
1771	* Don't flood the release log with errors.
1772	*/
1773	if (++pThis->uCntBadRMD < 50)
1774	LogRel(("PCnet#%d: BAD RMD ENTRIES + AT %#010x (i=%d)\n",
1775	PCNET_INST_NR, addr, i));
1776	return;
1777	}
1778
1779	/**
1780	* @todo NNRD
1781	*/
1782	}
1783	else
1784	{
1785	CSR_CRDA(pThis) = CSR_CRBA(pThis) = CSR_NRDA(pThis) = CSR_NRBA(pThis) = 0;
1786	CSR_CRBC(pThis) = CSR_NRBC(pThis) = CSR_CRST(pThis) = 0;
1787	}
1788	STAM_PROFILE_ADV_STOP(&pThis->CTX_SUFF_Z(StatRdtePoll), a);
1789	}
1790
1791	/**
1792	* Poll Transmit Descriptor Table Entry
1793	* @return true if transmit descriptors available
1794	*/
1795	static int pcnetTdtePoll(PPDMDEVINS pDevIns, PPCNETSTATE pThis, TMD *tmd)
1796	{
1797	STAM_PROFILE_ADV_START(&pThis->CTX_SUFF_Z(StatTdtePoll), a);
1798	if (RT_LIKELY(pThis->GCTDRA))
1799	{
1800	RTGCPHYS32 cxda = pcnetTdraAddr(pThis, CSR_XMTRC(pThis));
1801
1802	if (!pcnetTmdLoad(pDevIns, pThis, tmd, PHYSADDR(pThis, cxda), true))
1803	{
1804	STAM_PROFILE_ADV_STOP(&pThis->CTX_SUFF_Z(StatTdtePoll), a);
1805	return 0;
1806	}
1807
1808	if (RT_UNLIKELY(tmd->tmd1.ones != 15))
1809	{
1810	STAM_PROFILE_ADV_STOP(&pThis->CTX_SUFF_Z(StatTdtePoll), a);
1811	LogRel(("PCnet#%d: BAD TMD XDA=%#010x\n",
1812	PCNET_INST_NR, PHYSADDR(pThis, cxda)));
1813	return 0;
1814	}
1815
1816	/* previous xmit descriptor */
1817	CSR_PXDA(pThis) = CSR_CXDA(pThis);
1818	CSR_PXBC(pThis) = CSR_CXBC(pThis);
1819	CSR_PXST(pThis) = CSR_CXST(pThis);
1820
1821	/* set current transmit descriptor. */
1822	CSR_CXDA(pThis) = cxda;
1823	CSR_CXBC(pThis) = tmd->tmd1.bcnt;
1824	CSR_CXST(pThis) = ((uint32_t *)tmd)[1] >> 16;
1825	STAM_PROFILE_ADV_STOP(&pThis->CTX_SUFF_Z(StatTdtePoll), a);
1826	return CARD_IS_OWNER(CSR_CXST(pThis));
1827	}
1828	else
1829	{
1830	/** @todo consistency with previous receive descriptor */
1831	CSR_CXDA(pThis) = 0;
1832	CSR_CXBC(pThis) = CSR_CXST(pThis) = 0;
1833	STAM_PROFILE_ADV_STOP(&pThis->CTX_SUFF_Z(StatTdtePoll), a);
1834	return 0;
1835	}
1836	}
1837
1838
1839	/**
1840	* Poll Transmit Descriptor Table Entry
1841	* @return true if transmit descriptors available
1842	*/
1843	static int pcnetCalcPacketLen(PPDMDEVINS pDevIns, PPCNETSTATE pThis, unsigned cb)
1844	{
1845	TMD tmd;
1846	unsigned cbPacket = cb;
1847	uint32_t iDesc = CSR_XMTRC(pThis);
1848	uint32_t iFirstDesc = iDesc;
1849
1850	STAM_PROFILE_ADV_START(&pThis->CTX_SUFF_Z(StatTxLenCalc), a);
1851	do
1852	{
1853	/* Advance the ring counter */
1854	if (iDesc < 2)
1855	iDesc = CSR_XMTRL(pThis);
1856	else
1857	iDesc--;
1858
1859	if (iDesc == iFirstDesc)
1860	break;
1861
1862	RTGCPHYS32 addrDesc = pcnetTdraAddr(pThis, iDesc);
1863
1864	if (!pcnetTmdLoad(pDevIns, pThis, &tmd, PHYSADDR(pThis, addrDesc), true))
1865	{
1866	STAM_PROFILE_ADV_STOP(&pThis->CTX_SUFF_Z(StatTxLenCalc), a);
1867	/*
1868	* No need to count further since this packet won't be sent anyway
1869	* due to underflow.
1870	*/
1871	Log3(("#%d pcnetCalcPacketLen: underflow, return %u\n", PCNET_INST_NR, cbPacket));
1872	return cbPacket;
1873	}
1874	if (RT_UNLIKELY(tmd.tmd1.ones != 15))
1875	{
1876	STAM_PROFILE_ADV_STOP(&pThis->CTX_SUFF_Z(StatTxLenCalc), a);
1877	LogRel(("PCnet#%d: BAD TMD XDA=%#010x\n",
1878	PCNET_INST_NR, PHYSADDR(pThis, addrDesc)));
1879	Log3(("#%d pcnetCalcPacketLen: bad TMD, return %u\n", PCNET_INST_NR, cbPacket));
1880	return cbPacket;
1881	}
1882	Log3(("#%d pcnetCalcPacketLen: got valid TMD, cb=%u\n", PCNET_INST_NR, 4096 - tmd.tmd1.bcnt));
1883	cbPacket += 4096 - tmd.tmd1.bcnt;
1884	} while (!tmd.tmd1.enp);
1885	STAM_PROFILE_ADV_STOP(&pThis->CTX_SUFF_Z(StatTxLenCalc), a);
1886
1887	Log3(("#%d pcnetCalcPacketLen: return %u\n", PCNET_INST_NR, cbPacket));
1888	return cbPacket;
1889	}
1890
1891
1892	/**
1893	* Write data into guest receive buffers.
1894	*/
1895	static void pcnetReceiveNoSync(PPDMDEVINS pDevIns, PPCNETSTATE pThis, PPCNETSTATECC pThisCC,
1896	const uint8_t *buf, size_t cbToRecv, bool fAddFCS, bool fLoopback)
1897	{
1898	int is_padr = 0;
1899	int is_bcast = 0;
1900	int is_ladr = 0;
1901	unsigned iRxDesc;
1902	int cbPacket;
1903
1904	if (RT_UNLIKELY(CSR_DRX(pThis) \|\| CSR_STOP(pThis) \|\| CSR_SPND(pThis) \|\| !cbToRecv))
1905	return;
1906
1907	/*
1908	* Drop packets if the VM is not running yet/anymore.
1909	*/
1910	VMSTATE enmVMState = PDMDevHlpVMState(pDevIns);
1911	if ( enmVMState != VMSTATE_RUNNING
1912	&& enmVMState != VMSTATE_RUNNING_LS)
1913	return;
1914
1915	/*
1916	* Drop packets if the cable is not connected
1917	*/
1918	if (!pcnetIsLinkUp(pThis))
1919	return;
1920
1921	Log(("#%d pcnetReceiveNoSync: size=%d\n", PCNET_INST_NR, cbToRecv));
1922
1923	/*
1924	* Perform address matching.
1925	*/
1926	if ( CSR_PROM(pThis)
1927	\|\| (is_padr = padr_match(pThis, buf, cbToRecv))
1928	\|\| (is_bcast = padr_bcast(pThis, buf, cbToRecv))
1929	\|\| (is_ladr = ladr_match(pThis, buf, cbToRecv)))
1930	{
1931	if (HOST_IS_OWNER(CSR_CRST(pThis)))
1932	pcnetRdtePoll(pDevIns, pThis);
1933	if (RT_UNLIKELY(HOST_IS_OWNER(CSR_CRST(pThis))))
1934	{
1935	/* Not owned by controller. This should not be possible as
1936	* we already called pcnetR3CanReceive(). */
1937	LogRel(("PCnet#%d: no buffer: RCVRC=%d\n", PCNET_INST_NR, CSR_RCVRC(pThis)));
1938	/* Dump the status of all RX descriptors */
1939	const unsigned cb = 1 << pThis->iLog2DescSize;
1940	RTGCPHYS32 GCPhys = pThis->GCRDRA;
1941	iRxDesc = CSR_RCVRL(pThis);
1942	while (iRxDesc-- > 0)
1943	{
1944	RMD rmd;
1945	pcnetRmdLoad(pDevIns, pThis, &rmd, PHYSADDR(pThis, GCPhys), false);
1946	LogRel((" %#010x\n", rmd.rmd1));
1947	GCPhys += cb;
1948	}
1949	pThis->aCSR[0] \|= 0x1000; /* Set MISS flag */
1950	CSR_MISSC(pThis)++;
1951	}
1952	else
1953	{
1954	PCRTNETETHERHDR pEth = (PCRTNETETHERHDR)buf;
1955	bool fStrip = false;
1956	size_t len_802_3;
1957	uint8_t *src = &pThis->abRecvBuf[8];
1958	RTGCPHYS32 crda = CSR_CRDA(pThis);
1959	RTGCPHYS32 next_crda;
1960	RMD rmd, next_rmd;
1961
1962	/*
1963	* Ethernet framing considers these two octets to be
1964	* payload type; 802.3 framing considers them to be
1965	* payload length. IEEE 802.3x-1997 restricts Ethernet
1966	* type to be greater than or equal to 1536 (0x0600), so
1967	* that both framings can coexist on the wire.
1968	*
1969	* NB: CSR_ASTRP_RCV bit affects only 802.3 frames!
1970	*/
1971	len_802_3 = RT_BE2H_U16(pEth->EtherType);
1972	if (len_802_3 < 46 && CSR_ASTRP_RCV(pThis))
1973	{
1974	cbToRecv = RT_MIN(sizeof(RTNETETHERHDR) + len_802_3, cbToRecv);
1975	fStrip = true;
1976	fAddFCS = false;
1977	}
1978
1979	memcpy(src, buf, cbToRecv);
1980
1981	if (!fStrip) {
1982	/* In loopback mode, Runt Packed Accept is always enabled internally;
1983	* don't do any padding because guest may be looping back very short packets.
1984	*/
1985	if (!fLoopback)
1986	while (cbToRecv < 60)
1987	src[cbToRecv++] = 0;
1988
1989	if (fAddFCS)
1990	{
1991	uint32_t fcs = UINT32_MAX;
1992	uint8_t *p = src;
1993
1994	while (p != &src[cbToRecv])
1995	CRC(fcs, *p++);
1996
1997	/* FCS at the end of the packet */
1998	((uint32_t *)&src[cbToRecv])[0] = htonl(fcs);
1999	cbToRecv += 4;
2000	}
2001	}
2002
2003	cbPacket = (int)cbToRecv; Assert((size_t)cbPacket == cbToRecv);
2004
2005	#ifdef LOG_ENABLED
2006	PRINT_PKTHDR(buf);
2007	#endif
2008
2009	pcnetRmdLoad(pDevIns, pThis, &rmd, PHYSADDR(pThis, crda), false);
2010	/if (!CSR_LAPPEN(pThis))/
2011	rmd.rmd1.stp = 1;
2012
2013	size_t cbBuf = RT_MIN(4096 - (size_t)rmd.rmd1.bcnt, cbToRecv);
2014	RTGCPHYS32 rbadr = PHYSADDR(pThis, rmd.rmd0.rbadr);
2015
2016	/* save the old value to check if it was changed as long as we didn't
2017	* hold the critical section */
2018	iRxDesc = CSR_RCVRC(pThis);
2019
2020	/* We have to leave the critical section here or we risk deadlocking
2021	* with EMT when the write is to an unallocated page or has an access
2022	* handler associated with it.
2023	*
2024	* This shouldn't be a problem because:
2025	* - any modification to the RX descriptor by the driver is
2026	* forbidden as long as it is owned by the device
2027	* - we don't cache any register state beyond this point
2028	*/
2029	PDMDevHlpCritSectLeave(pDevIns, &pThis->CritSect);
2030	pcnetPhysWrite(pDevIns, pThis, rbadr, src, cbBuf);
2031	int rc = PDMDevHlpCritSectEnter(pDevIns, &pThis->CritSect, VERR_SEM_BUSY);
2032	AssertReleaseRC(rc);
2033
2034	/* RX disabled in the meantime? If so, abort RX. */
2035	if (RT_UNLIKELY(CSR_DRX(pThis) \|\| CSR_STOP(pThis) \|\| CSR_SPND(pThis)))
2036	return;
2037
2038	/* Was the register modified in the meantime? If so, don't touch the
2039	* register but still update the RX descriptor. */
2040	if (RT_LIKELY(iRxDesc == CSR_RCVRC(pThis)))
2041	{
2042	if (iRxDesc-- < 2)
2043	iRxDesc = CSR_RCVRL(pThis);
2044	CSR_RCVRC(pThis) = iRxDesc;
2045	}
2046	else
2047	iRxDesc = CSR_RCVRC(pThis);
2048
2049	src += cbBuf;
2050	cbToRecv -= cbBuf;
2051
2052	while (cbToRecv > 0)
2053	{
2054	/* Read the entire next descriptor as we're likely to need it. */
2055	next_crda = pcnetRdraAddr(pThis, iRxDesc);
2056
2057	/* Check next descriptor's own bit. If we don't own it, we have
2058	* to quit and write error status into the last descriptor we own.
2059	*/
2060	if (!pcnetRmdLoad(pDevIns, pThis, &next_rmd, PHYSADDR(pThis, next_crda), true))
2061	break;
2062
2063	/* Write back current descriptor, clear the own bit. */
2064	pcnetRmdStorePassHost(pDevIns, pThis, &rmd, PHYSADDR(pThis, crda));
2065
2066	/* Switch to the next descriptor */
2067	crda = next_crda;
2068	rmd = next_rmd;
2069
2070	cbBuf = RT_MIN(4096 - (size_t)rmd.rmd1.bcnt, cbToRecv);
2071	RTGCPHYS32 rbadr2 = PHYSADDR(pThis, rmd.rmd0.rbadr);
2072
2073	/* We have to leave the critical section here or we risk deadlocking
2074	* with EMT when the write is to an unallocated page or has an access
2075	* handler associated with it. See above for additional comments. */
2076	PDMDevHlpCritSectLeave(pDevIns, &pThis->CritSect);
2077	pcnetPhysWrite(pDevIns, pThis, rbadr2, src, cbBuf);
2078	rc = PDMDevHlpCritSectEnter(pDevIns, &pThis->CritSect, VERR_SEM_BUSY);
2079	AssertReleaseRC(rc);
2080
2081	/* RX disabled in the meantime? If so, abort RX. */
2082	if (RT_UNLIKELY(CSR_DRX(pThis) \|\| CSR_STOP(pThis) \|\| CSR_SPND(pThis)))
2083	return;
2084
2085	/* Was the register modified in the meantime? If so, don't touch the
2086	* register but still update the RX descriptor. */
2087	if (RT_LIKELY(iRxDesc == CSR_RCVRC(pThis)))
2088	{
2089	if (iRxDesc-- < 2)
2090	iRxDesc = CSR_RCVRL(pThis);
2091	CSR_RCVRC(pThis) = iRxDesc;
2092	}
2093	else
2094	iRxDesc = CSR_RCVRC(pThis);
2095
2096	src += cbBuf;
2097	cbToRecv -= cbBuf;
2098	}
2099
2100	if (RT_LIKELY(cbToRecv == 0))
2101	{
2102	rmd.rmd1.enp = 1;
2103	rmd.rmd1.pam = !CSR_PROM(pThis) && is_padr;
2104	rmd.rmd1.lafm = !CSR_PROM(pThis) && is_ladr;
2105	rmd.rmd1.bam = !CSR_PROM(pThis) && is_bcast;
2106	rmd.rmd2.mcnt = cbPacket;
2107	rmd.rmd2.zeros = 0;
2108
2109	STAM_REL_COUNTER_ADD(&pThis->StatReceiveBytes, cbPacket);
2110	}
2111	else
2112	{
2113	Log(("#%d: Overflow by %ubytes\n", PCNET_INST_NR, cbToRecv));
2114	rmd.rmd1.oflo = 1;
2115	rmd.rmd1.buff = 1;
2116	rmd.rmd1.err = 1;
2117	}
2118
2119	/* write back, clear the own bit */
2120	pcnetRmdStorePassHost(pDevIns, pThis, &rmd, PHYSADDR(pThis, crda));
2121
2122	pThis->aCSR[0] \|= 0x0400;
2123
2124	Log(("#%d RCVRC=%d CRDA=%#010x\n", PCNET_INST_NR, CSR_RCVRC(pThis), PHYSADDR(pThis, CSR_CRDA(pThis))));
2125	#ifdef LOG_ENABLED
2126	PRINT_RMD(&rmd);
2127	#endif
2128
2129	/* guest driver is owner: force repoll of current and next RDTEs */
2130	CSR_CRST(pThis) = 0;
2131	}
2132	}
2133
2134	/* see description of TXDPOLL:
2135	* ``transmit polling will take place following receive activities'' */
2136	if (!fLoopback)
2137	pcnetPollRxTx(pDevIns, pThis, pThisCC);
2138	pcnetUpdateIrq(pDevIns, pThis);
2139	}
2140
2141
2142	#ifdef IN_RING3
2143	/**
2144	* @callback_method_impl{FNPDMTASKDEV,
2145	* This is just a very simple way of delaying sending to R3.}
2146	*/
2147	static DECLCALLBACK(void) pcnetR3XmitTaskCallback(PPDMDEVINS pDevIns, void *pvUser)
2148	{
2149	PPCNETSTATE pThis = PDMDEVINS_2_DATA(pDevIns, PPCNETSTATE);
2150	PPCNETSTATECC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PPCNETSTATECC);
2151	NOREF(pvUser);
2152
2153	/*
2154	* Transmit as much as we can.
2155	*/
2156	pcnetXmitPending(pDevIns, pThis, pThisCC, true /fOnWorkerThread/);
2157	}
2158	#endif /* IN_RING3 */
2159
2160
2161	/**
2162	* Allocates a scatter/gather buffer for a transfer.
2163	*
2164	* @returns See PPDMINETWORKUP::pfnAllocBuf.
2165	* @param pThis The shared PCNet state data.
2166	* @param cbMin The minimum buffer size.
2167	* @param fLoopback Set if we're in loopback mode.
2168	* @param pSgLoop Pointer to stack storage for the loopback SG.
2169	* @param ppSgBuf Where to return the SG buffer descriptor on success.
2170	* Always set.
2171	*/
2172	DECLINLINE(int) pcnetXmitAllocBuf(PPCNETSTATE pThis, PPCNETSTATECC pThisCC, size_t cbMin, bool fLoopback,
2173	PPDMSCATTERGATHER pSgLoop, PPPDMSCATTERGATHER ppSgBuf)
2174	{
2175	int rc;
2176
2177	if (RT_UNLIKELY(fLoopback)) /* hope that loopback mode is rare */
2178	{
2179	pSgLoop->fFlags = PDMSCATTERGATHER_FLAGS_MAGIC \| PDMSCATTERGATHER_FLAGS_OWNER_1;
2180	pSgLoop->cbUsed = 0;
2181	pSgLoop->cbAvailable = sizeof(pThis->abLoopBuf);
2182	pSgLoop->pvAllocator = pThis;
2183	pSgLoop->pvUser = NULL;
2184	pSgLoop->cSegs = 1;
2185	pSgLoop->aSegs[0].cbSeg = sizeof(pThis->abLoopBuf);
2186	pSgLoop->aSegs[0].pvSeg = pThis->abLoopBuf;
2187	*ppSgBuf = pSgLoop;
2188	rc = VINF_SUCCESS;
2189	}
2190	else
2191	{
2192	PPDMINETWORKUP pDrv = pThisCC->pDrv;
2193	if (RT_LIKELY(pDrv))
2194	{
2195	rc = pDrv->pfnAllocBuf(pDrv, cbMin, NULL /pGso/, ppSgBuf);
2196	AssertMsg(rc == VINF_SUCCESS \|\| rc == VERR_TRY_AGAIN \|\| rc == VERR_NET_DOWN \|\| rc == VERR_NO_MEMORY, ("%Rrc\n", rc));
2197	if (RT_FAILURE(rc))
2198	*ppSgBuf = NULL;
2199	}
2200	else
2201	{
2202	rc = VERR_NET_DOWN;
2203	*ppSgBuf = NULL;
2204	}
2205	}
2206	return rc;
2207	}
2208
2209
2210	/**
2211	* Frees an unsent buffer.
2212	*
2213	* @param pThisCC The PCNet state data for the current context.
2214	* @param fLoopback Set if we're in loopback mode.
2215	* @param pSgBuf The SG to free. Can be NULL.
2216	*/
2217	DECLINLINE(void) pcnetXmitFreeBuf(PPCNETSTATECC pThisCC, bool fLoopback, PPDMSCATTERGATHER pSgBuf)
2218	{
2219	if (pSgBuf)
2220	{
2221	if (RT_UNLIKELY(fLoopback))
2222	pSgBuf->pvAllocator = NULL;
2223	else
2224	{
2225	PPDMINETWORKUP pDrv = pThisCC->pDrv;
2226	if (RT_LIKELY(pDrv))
2227	pDrv->pfnFreeBuf(pDrv, pSgBuf);
2228	}
2229	}
2230	}
2231
2232
2233	/**
2234	* Sends the scatter/gather buffer.
2235	*
2236	* Wrapper around PDMINETWORKUP::pfnSendBuf, so check it out for the fine print.
2237	*
2238	* @returns See PDMINETWORKUP::pfnSendBuf.
2239	* @param pDevIns The device instance.
2240	* @param pThis The shared PCNet state data.
2241	* @param pThisCC The PCNet state data for the current context.
2242	* @param fLoopback Set if we're in loopback mode.
2243	* @param pSgBuf The SG to send.
2244	* @param fOnWorkerThread Set if we're being called on a work thread. Clear
2245	* if an EMT.
2246	*/
2247	DECLINLINE(int) pcnetXmitSendBuf(PPDMDEVINS pDevIns, PPCNETSTATE pThis, PPCNETSTATECC pThisCC, bool fLoopback,
2248	PPDMSCATTERGATHER pSgBuf, bool fOnWorkerThread)
2249	{
2250	int rc;
2251	STAM_REL_COUNTER_ADD(&pThis->StatTransmitBytes, pSgBuf->cbUsed);
2252	if (RT_UNLIKELY(fLoopback)) /* hope that loopback mode is rare */
2253	{
2254	Assert(pSgBuf->pvAllocator == (void *)pThis);
2255	pThis->Led.Asserted.s.fReading = pThis->Led.Actual.s.fReading = 1;
2256	if (HOST_IS_OWNER(CSR_CRST(pThis)))
2257	pcnetRdtePoll(pDevIns, pThis);
2258
2259	pcnetReceiveNoSync(pDevIns, pThis, pThisCC, pThis->abLoopBuf, pSgBuf->cbUsed, true /* fAddFCS */, fLoopback);
2260	pThis->Led.Actual.s.fReading = 0;
2261	rc = VINF_SUCCESS;
2262	}
2263	else
2264	{
2265	/** @todo We used to leave the critsect here, not sure if that's necessary any
2266	* longer. If we could avoid that we could cache a bit more info in
2267	* the loop and make it part of the driver<->device contract, saving
2268	* critsect mess down in DrvIntNet. */
2269	STAM_PROFILE_START(&pThis->CTX_SUFF_Z(StatTransmitSend), a);
2270	if (pSgBuf->cbUsed > 70) /* unqualified guess */
2271	pThis->Led.Asserted.s.fWriting = pThis->Led.Actual.s.fWriting = 1;
2272
2273	PPDMINETWORKUP pDrv = pThisCC->pDrv;
2274	if (RT_LIKELY(pDrv))
2275	{
2276	rc = pDrv->pfnSendBuf(pDrv, pSgBuf, fOnWorkerThread);
2277	AssertMsg(rc == VINF_SUCCESS \|\| rc == VERR_NET_DOWN \|\| rc == VERR_NET_NO_BUFFER_SPACE, ("%Rrc\n", rc));
2278	}
2279	else
2280	rc = VERR_NET_DOWN;
2281
2282	pThis->Led.Actual.s.fWriting = 0;
2283	STAM_PROFILE_STOP(&pThis->CTX_SUFF_Z(StatTransmitSend), a);
2284	}
2285	return rc;
2286	}
2287
2288
2289	/**
2290	* pcnetXmitRead1st worker that handles the unlikely + slower segmented code
2291	* path.
2292	*/
2293	static void pcnetXmitRead1stSlow(PPDMDEVINS pDevIns, RTGCPHYS32 GCPhysFrame, unsigned cbFrame, PPDMSCATTERGATHER pSgBuf)
2294	{
2295	AssertFailed(); /* This path is not supposed to be taken atm */
2296
2297	pSgBuf->cbUsed = cbFrame;
2298	for (uint32_t iSeg = 0; ; iSeg++)
2299	{
2300	Assert(iSeg < pSgBuf->cSegs);
2301	uint32_t cbRead = (uint32_t)RT_MIN(cbFrame, pSgBuf->aSegs[iSeg].cbSeg);
2302	PDMDevHlpPhysRead(pDevIns, GCPhysFrame, pSgBuf->aSegs[iSeg].pvSeg, cbRead);
2303	cbFrame -= cbRead;
2304	if (!cbFrame)
2305	return;
2306	GCPhysFrame += cbRead;
2307	}
2308	}
2309
2310
2311	/**
2312	* pcnetXmitSgReadMore worker that handles the unlikely + slower segmented code
2313	* path.
2314	*/
2315	static void pcnetXmitReadMoreSlow(PPDMDEVINS pDevIns, RTGCPHYS32 GCPhysFrame, unsigned cbFrame, PPDMSCATTERGATHER pSgBuf)
2316	{
2317	AssertFailed(); /* This path is not supposed to be taken atm */
2318
2319	/* Find the segment which we'll put the next byte into. */
2320	size_t off = pSgBuf->cbUsed;
2321	size_t offSeg = 0;
2322	uint32_t iSeg = 0;
2323	while (offSeg + pSgBuf->aSegs[iSeg].cbSeg <= off)
2324	{
2325	offSeg += pSgBuf->aSegs[iSeg].cbSeg;
2326	iSeg++;
2327	Assert(iSeg < pSgBuf->cSegs);
2328	}
2329
2330	/* Commit before we start copying so we can decrement cbFrame. */
2331	pSgBuf->cbUsed = off + cbFrame;
2332
2333	/* Deal with the first segment if we at an offset into it. */
2334	if (off != offSeg)
2335	{
2336	size_t offIntoSeg = off - offSeg;
2337	uint32_t cbRead = (uint32_t)RT_MIN(pSgBuf->aSegs[iSeg].cbSeg - offIntoSeg, cbFrame);
2338	PDMDevHlpPhysRead(pDevIns, GCPhysFrame,
2339	(uint8_t *)pSgBuf->aSegs[iSeg].pvSeg + offIntoSeg, cbRead);
2340	cbFrame -= cbRead;
2341	if (!cbFrame)
2342	return;
2343	GCPhysFrame += cbRead;
2344	iSeg++;
2345	}
2346
2347	/* For the remainder, we've got whole segments. */
2348	for (;; iSeg++)
2349	{
2350	Assert(iSeg < pSgBuf->cSegs);
2351
2352	uint32_t cbRead = (uint32_t)RT_MIN(pSgBuf->aSegs[iSeg].cbSeg, cbFrame);
2353	PDMDevHlpPhysRead(pDevIns, GCPhysFrame, pSgBuf->aSegs[iSeg].pvSeg, cbRead);
2354	cbFrame -= cbRead;
2355	if (!cbFrame)
2356	return;
2357	GCPhysFrame += cbFrame;
2358	}
2359	}
2360
2361
2362	/**
2363	* Reads the first part of a frame into the scatter gather buffer.
2364	*/
2365	DECLINLINE(void) pcnetXmitRead1st(PPDMDEVINS pDevIns, PPCNETSTATE pThis, RTGCPHYS32 GCPhysFrame, const unsigned cbFrame,
2366	PPDMSCATTERGATHER pSgBuf)
2367	{
2368	Assert(PDMDevHlpCritSectIsOwner(pDevIns, &pThis->CritSect)); RT_NOREF(pThis);
2369	Assert(pSgBuf->cbAvailable >= cbFrame);
2370
2371	if (RT_LIKELY(pSgBuf->aSegs[0].cbSeg >= cbFrame)) /* justification: all drivers returns a single segment atm. */
2372	{
2373	pSgBuf->cbUsed = cbFrame;
2374	PDMDevHlpPhysRead(pDevIns, GCPhysFrame, pSgBuf->aSegs[0].pvSeg, cbFrame);
2375	}
2376	else
2377	pcnetXmitRead1stSlow(pDevIns, GCPhysFrame, cbFrame, pSgBuf);
2378	}
2379
2380	/**
2381	* Reads more into the current frame.
2382	*/
2383	DECLINLINE(void) pcnetXmitReadMore(PPDMDEVINS pDevIns, RTGCPHYS32 GCPhysFrame, const unsigned cbFrame, PPDMSCATTERGATHER pSgBuf)
2384	{
2385	size_t off = pSgBuf->cbUsed;
2386	Assert(pSgBuf->cbAvailable >= cbFrame + off);
2387
2388	if (RT_LIKELY(pSgBuf->aSegs[0].cbSeg >= cbFrame + off))
2389	{
2390	pSgBuf->cbUsed = cbFrame + off;
2391	PDMDevHlpPhysRead(pDevIns, GCPhysFrame, (uint8_t *)pSgBuf->aSegs[0].pvSeg + off, cbFrame);
2392	}
2393	else
2394	pcnetXmitReadMoreSlow(pDevIns, GCPhysFrame, cbFrame, pSgBuf);
2395	}
2396
2397
2398	/**
2399	* Fails a TMD with a link down error.
2400	*/
2401	static void pcnetXmitFailTMDLinkDown(PPCNETSTATE pThis, TMD *pTmd)
2402	{
2403	/* make carrier error - hope this is correct. */
2404	pThis->cLinkDownReported++;
2405	pTmd->tmd2.lcar = pTmd->tmd1.err = 1;
2406	pThis->aCSR[0] \|= RT_BIT(15) \| RT_BIT(13); /* ERR \| CERR */
2407	pThis->Led.Asserted.s.fError = pThis->Led.Actual.s.fError = 1;
2408	Log(("#%d pcnetTransmit: Signaling send error. swstyle=%#x\n",
2409	PCNET_INST_NR, pThis->aBCR[BCR_SWS]));
2410	}
2411
2412	/**
2413	* Fails a TMD with a generic error.
2414	*/
2415	static void pcnetXmitFailTMDGeneric(PPCNETSTATE pThis, TMD *pTmd)
2416	{
2417	/* make carrier error - hope this is correct. */
2418	pTmd->tmd2.lcar = pTmd->tmd1.err = 1;
2419	pThis->aCSR[0] \|= RT_BIT(15) \| RT_BIT(13); /* ERR \| CERR */
2420	pThis->Led.Asserted.s.fError = pThis->Led.Actual.s.fError = 1;
2421	Log(("#%d pcnetTransmit: Signaling send error. swstyle=%#x\n",
2422	PCNET_INST_NR, pThis->aBCR[BCR_SWS]));
2423	}
2424
2425
2426	/**
2427	* Try to transmit frames
2428	*/
2429	static void pcnetTransmit(PPDMDEVINS pDevIns, PPCNETSTATE pThis, PPCNETSTATECC pThisCC)
2430	{
2431	if (RT_UNLIKELY(!CSR_TXON(pThis)))
2432	{
2433	pThis->aCSR[0] &= ~0x0008; /* Clear TDMD */
2434	return;
2435	}
2436
2437	/*
2438	* Check the current transmit descriptors.
2439	*/
2440	TMD tmd;
2441	if (!pcnetTdtePoll(pDevIns, pThis, &tmd))
2442	return;
2443
2444	/*
2445	* Clear TDMD.
2446	*/
2447	pThis->aCSR[0] &= ~0x0008;
2448
2449	/*
2450	* Transmit pending packets if possible, defer it if we cannot do it
2451	* in the current context.
2452	*/
2453	#if defined(IN_RING0) \|\| defined(IN_RC)
2454	if (!pThisCC->pDrv)
2455	{
2456	int rc = PDMDevHlpTaskTrigger(pDevIns, pThis->hXmitTask);
2457	AssertRC(rc);
2458	}
2459	else
2460	#endif
2461	{
2462	int rc = pcnetXmitPending(pDevIns, pThis, pThisCC, false /fOnWorkerThread/);
2463	if (rc == VERR_TRY_AGAIN)
2464	rc = VINF_SUCCESS;
2465	AssertRC(rc);
2466	}
2467	}
2468
2469
2470	/**
2471	* Actually try transmit frames.
2472	*
2473	* @threads TX or EMT.
2474	*/
2475	static int pcnetAsyncTransmit(PPDMDEVINS pDevIns, PPCNETSTATE pThis, PPCNETSTATECC pThisCC, bool fOnWorkerThread)
2476	{
2477	Assert(PDMDevHlpCritSectIsOwner(pDevIns, &pThis->CritSect));
2478
2479	/*
2480	* Just cleared transmit demand if the transmitter is off.
2481	*/
2482	if (RT_UNLIKELY(!CSR_TXON(pThis)))
2483	{
2484	pThis->aCSR[0] &= ~0x0008; /* Clear TDMD */
2485	return VINF_SUCCESS;
2486	}
2487
2488	/*
2489	* Iterate the transmit descriptors.
2490	*/
2491	int rc;
2492	unsigned cFlushIrq = 0;
2493	int cMax = 32;
2494	STAM_PROFILE_ADV_START(&pThis->CTX_SUFF_Z(StatTransmit), a);
2495	do
2496	{
2497	#ifdef VBOX_WITH_STATISTICS
2498	unsigned cBuffers = 1;
2499	#endif
2500	TMD tmd;
2501	if (!pcnetTdtePoll(pDevIns, pThis, &tmd))
2502	break;
2503
2504	/* Don't continue sending packets when the link is down. */
2505	if (RT_UNLIKELY( !pcnetIsLinkUp(pThis)
2506	&& pThis->cLinkDownReported > PCNET_MAX_LINKDOWN_REPORTED)
2507	)
2508	break;
2509
2510	#ifdef LOG_ENABLED
2511	Log10(("#%d TMDLOAD %#010x\n", PCNET_INST_NR, PHYSADDR(pThis, CSR_CXDA(pThis))));
2512	PRINT_TMD(&tmd);
2513	#endif
2514	bool const fLoopback = CSR_LOOP(pThis);
2515	PDMSCATTERGATHER SgLoop;
2516	PPDMSCATTERGATHER pSgBuf;
2517
2518	/*
2519	* The typical case - a complete packet.
2520	*/
2521	if (tmd.tmd1.stp && tmd.tmd1.enp)
2522	{
2523	const unsigned cb = 4096 - tmd.tmd1.bcnt;
2524	Log(("#%d pcnetAsyncTransmit: stp&enp: cb=%d xmtrc=%#x\n", PCNET_INST_NR, cb, CSR_XMTRC(pThis)));
2525	STAM_COUNTER_INC(&pThis->StatTransmitCase1);
2526
2527	if (RT_LIKELY(pcnetIsLinkUp(pThis) \|\| fLoopback))
2528	{
2529	/* From the manual: ``A zero length buffer is acceptable as
2530	* long as it is not the last buffer in a chain (STP = 0 and
2531	* ENP = 1).'' That means that the first buffer might have a
2532	* zero length if it is not the last one in the chain. */
2533	if (RT_LIKELY(cb <= MAX_FRAME))
2534	{
2535	rc = pcnetXmitAllocBuf(pThis, pThisCC, cb, fLoopback, &SgLoop, &pSgBuf);
2536	if (RT_SUCCESS(rc))
2537	{
2538	pcnetXmitRead1st(pDevIns, pThis, PHYSADDR(pThis, tmd.tmd0.tbadr), cb, pSgBuf);
2539	rc = pcnetXmitSendBuf(pDevIns, pThis, pThisCC, fLoopback, pSgBuf, fOnWorkerThread);
2540	}
2541	else if (rc == VERR_TRY_AGAIN)
2542	{
2543	STAM_PROFILE_ADV_STOP(&pThis->CTX_SUFF_Z(StatTransmit), a);
2544	return VINF_SUCCESS;
2545	}
2546	if (RT_FAILURE(rc))
2547	pcnetXmitFailTMDLinkDown(pThis, &tmd);
2548	}
2549	else if (cb == 4096)
2550	{
2551	/* The Windows NT4 pcnet driver sometimes marks the first
2552	* unused descriptor as owned by us. Ignore that (by
2553	* passing it back). Do not update the ring counter in this
2554	* case (otherwise that driver becomes even more confused,
2555	* which causes transmit to stall for about 10 seconds).
2556	* This is just a workaround, not a final solution. */
2557	/* r=frank: IMHO this is the correct implementation. The
2558	* manual says: ``If the OWN bit is set and the buffer
2559	* length is 0, the OWN bit will be cleared. In the C-LANCE
2560	* the buffer length of 0 is interpreted as a 4096-byte
2561	* buffer.'' */
2562	/* r=michaln: Perhaps not quite right. The C-LANCE (Am79C90)
2563	* datasheet explains that the old LANCE (Am7990) ignored
2564	* the top four bits next to BCNT and a count of 0 was
2565	* interpreted as 4096. In the C-LANCE, that is still the
2566	* case if the top bits are all ones. If all 16 bits are
2567	* zero, the C-LANCE interprets it as zero-length transmit
2568	* buffer. It's not entirely clear if the later models
2569	* (PCnet-ISA, PCnet-PCI) behave like the C-LANCE or not.
2570	* It is possible that the actual behavior of the C-LANCE
2571	* and later hardware is that the buffer lengths are 16-bit
2572	* two's complement numbers between 0 and 4096. AMD's drivers
2573	* in fact generally treat the length as a 16-bit quantity. */
2574	LogRel(("PCnet#%d: pcnetAsyncTransmit: illegal 4kb frame -> ignoring\n", PCNET_INST_NR));
2575	pcnetTmdStorePassHost(pDevIns, pThis, &tmd, PHYSADDR(pThis, CSR_CXDA(pThis)));
2576	break;
2577	}
2578	else
2579	{
2580	/* Signal error, as this violates the Ethernet specs. */
2581	/** @todo check if the correct error is generated. */
2582	LogRel(("PCnet#%d: pcnetAsyncTransmit: illegal 4kb frame -> signalling error\n", PCNET_INST_NR));
2583
2584	pcnetXmitFailTMDGeneric(pThis, &tmd);
2585	}
2586	}
2587	else
2588	pcnetXmitFailTMDLinkDown(pThis, &tmd);
2589
2590	/* Write back the TMD and pass it to the host (clear own bit). */
2591	pcnetTmdStorePassHost(pDevIns, pThis, &tmd, PHYSADDR(pThis, CSR_CXDA(pThis)));
2592
2593	/* advance the ring counter register */
2594	if (CSR_XMTRC(pThis) < 2)
2595	CSR_XMTRC(pThis) = CSR_XMTRL(pThis);
2596	else
2597	CSR_XMTRC(pThis)--;
2598	}
2599	else if (tmd.tmd1.stp)
2600	{
2601	STAM_COUNTER_INC(&pThis->StatTransmitCase2);
2602
2603	/*
2604	* Read TMDs until end-of-packet or tdte poll fails (underflow).
2605	*
2606	* We allocate a maximum sized buffer here since we do not wish to
2607	* waste time finding out how much space we actually need even if
2608	* we could reliably do that on SMP guests.
2609	*/
2610	unsigned cb = 4096 - tmd.tmd1.bcnt;
2611	rc = pcnetXmitAllocBuf(pThis, pThisCC, pcnetCalcPacketLen(pDevIns, pThis, cb), fLoopback, &SgLoop, &pSgBuf);
2612	if (rc == VERR_TRY_AGAIN)
2613	{
2614	STAM_PROFILE_ADV_STOP(&pThis->CTX_SUFF_Z(StatTransmit), a);
2615	return VINF_SUCCESS;
2616	}
2617
2618	bool fDropFrame = RT_FAILURE(rc);
2619	if (!fDropFrame)
2620	pcnetXmitRead1st(pDevIns, pThis, PHYSADDR(pThis, tmd.tmd0.tbadr), cb, pSgBuf);
2621
2622	for (;;)
2623	{
2624	/*
2625	* Advance the ring counter register and check the next tmd.
2626	*/
2627	#ifdef LOG_ENABLED
2628	const uint32_t iStart = CSR_XMTRC(pThis);
2629	#endif
2630	const uint32_t GCPhysPrevTmd = PHYSADDR(pThis, CSR_CXDA(pThis));
2631	if (CSR_XMTRC(pThis) < 2)
2632	CSR_XMTRC(pThis) = CSR_XMTRL(pThis);
2633	else
2634	CSR_XMTRC(pThis)--;
2635
2636	TMD dummy;
2637	if (!pcnetTdtePoll(pDevIns, pThis, &dummy))
2638	{
2639	/*
2640	* Underflow!
2641	*/
2642	tmd.tmd2.buff = tmd.tmd2.uflo = tmd.tmd1.err = 1;
2643	pThis->aCSR[0] \|= 0x0200; /* set TINT */
2644	/* Don't allow the guest to clear TINT before reading it */
2645	pThis->u16CSR0LastSeenByGuest &= ~0x0200;
2646	if (!CSR_DXSUFLO(pThis)) /* stop on xmit underflow */
2647	pThis->aCSR[0] &= ~0x0010; /* clear TXON */
2648	pcnetTmdStorePassHost(pDevIns, pThis, &tmd, GCPhysPrevTmd);
2649	AssertMsgFailed(("pcnetAsyncTransmit: Underflow!!!\n"));
2650	pcnetXmitFreeBuf(pThisCC, fLoopback, pSgBuf);
2651	break;
2652	}
2653
2654	/* release & save the previous tmd, pass it to the host */
2655	pcnetTmdStorePassHost(pDevIns, pThis, &tmd, GCPhysPrevTmd);
2656
2657	/*
2658	* The next tmd.
2659	*/
2660	#ifdef VBOX_WITH_STATISTICS
2661	cBuffers++;
2662	#endif
2663	pcnetTmdLoad(pDevIns, pThis, &tmd, PHYSADDR(pThis, CSR_CXDA(pThis)), false);
2664	cb = 4096 - tmd.tmd1.bcnt;
2665	if ( !fDropFrame
2666	&& pSgBuf->cbUsed + cb <= MAX_FRAME) /** @todo this used to be ... + cb < MAX_FRAME. */
2667	pcnetXmitReadMore(pDevIns, PHYSADDR(pThis, tmd.tmd0.tbadr), cb, pSgBuf);
2668	else
2669	{
2670	AssertMsg(fDropFrame, ("pcnetAsyncTransmit: Frame is too big!!! %d bytes\n", pSgBuf->cbUsed + cb));
2671	fDropFrame = true;
2672	}
2673
2674	/*
2675	* Done already?
2676	*/
2677	if (tmd.tmd1.enp)
2678	{
2679	Log(("#%d pcnetAsyncTransmit: stp: cb=%d xmtrc=%#x-%#x\n", PCNET_INST_NR,
2680	pSgBuf ? pSgBuf->cbUsed : 0, iStart, CSR_XMTRC(pThis)));
2681	if (!fDropFrame && (pcnetIsLinkUp(pThis) \|\| fLoopback))
2682	{
2683	rc = pcnetXmitSendBuf(pDevIns, pThis, pThisCC, fLoopback, pSgBuf, fOnWorkerThread);
2684	fDropFrame = RT_FAILURE(rc);
2685	}
2686	else
2687	pcnetXmitFreeBuf(pThisCC, fLoopback, pSgBuf);
2688	if (fDropFrame)
2689	pcnetXmitFailTMDLinkDown(pThis, &tmd);
2690
2691	/* Write back the TMD, pass it to the host */
2692	pcnetTmdStorePassHost(pDevIns, pThis, &tmd, PHYSADDR(pThis, CSR_CXDA(pThis)));
2693
2694	/* advance the ring counter register */
2695	if (CSR_XMTRC(pThis) < 2)
2696	CSR_XMTRC(pThis) = CSR_XMTRL(pThis);
2697	else
2698	CSR_XMTRC(pThis)--;
2699	break;
2700	}
2701	} /* the loop */
2702	}
2703	else
2704	{
2705	/*
2706	* We underflowed in a previous transfer, or the driver is giving us shit.
2707	* Simply stop the transmitting for now.
2708	*/
2709	/** @todo according to the specs we're supposed to clear the own bit and move on to the next one. */
2710	Log(("#%d pcnetAsyncTransmit: guest is giving us shit!\n", PCNET_INST_NR));
2711	break;
2712	}
2713	/* Update TDMD, TXSTRT and TINT. */
2714	pThis->aCSR[0] &= ~0x0008; /* clear TDMD */
2715
2716	pThis->aCSR[4] \|= 0x0008; /* set TXSTRT */
2717	if ( !CSR_TOKINTD(pThis) /* Transmit OK Interrupt Disable, no infl. on errors. */
2718	\|\| (CSR_LTINTEN(pThis) && tmd.tmd1.ltint)
2719	\|\| tmd.tmd1.err)
2720	{
2721	cFlushIrq++;
2722	}
2723
2724	/** @todo should we continue after an error (tmd.tmd1.err) or not? */
2725
2726	STAM_COUNTER_INC(&pThis->aStatXmitChainCounts[RT_MIN(cBuffers,
2727	RT_ELEMENTS(pThis->aStatXmitChainCounts)) - 1]);
2728	if (--cMax == 0)
2729	break;
2730	} while (CSR_TXON(pThis)); /* transfer on */
2731
2732	if (cFlushIrq)
2733	{
2734	STAM_COUNTER_INC(&pThis->aStatXmitFlush[RT_MIN(cFlushIrq, RT_ELEMENTS(pThis->aStatXmitFlush)) - 1]);
2735	/* The WinXP PCnet driver has apparently a bug: It sets CSR0.TDMD _before_
2736	* it clears CSR0.TINT. This can lead to a race where the driver clears
2737	* CSR0.TINT right after it was set by the device. The driver waits until
2738	* CSR0.TINT is set again but this will never happen. So prevent clearing
2739	* this bit as long as the driver didn't read it. See @bugref{5288}. */
2740	pThis->aCSR[0] \|= 0x0200; /* set TINT */
2741	/* Don't allow the guest to clear TINT before reading it */
2742	pThis->u16CSR0LastSeenByGuest &= ~0x0200;
2743	pcnetUpdateIrq(pDevIns, pThis);
2744	}
2745
2746	STAM_PROFILE_ADV_STOP(&pThis->CTX_SUFF_Z(StatTransmit), a);
2747
2748	return VINF_SUCCESS;
2749	}
2750
2751
2752	/**
2753	* Transmit pending descriptors.
2754	*
2755	* @returns VBox status code. VERR_TRY_AGAIN is returned if we're busy.
2756	*
2757	* @param pDevIns The device instance.
2758	* @param pThis The PCnet shared instance data.
2759	* @param pThisCC The PCNet state data for the current context.
2760	* @param fOnWorkerThread Whether we're on a worker thread or on an EMT.
2761	*/
2762	static int pcnetXmitPending(PPDMDEVINS pDevIns, PPCNETSTATE pThis, PPCNETSTATECC pThisCC, bool fOnWorkerThread)
2763	{
2764	RT_NOREF_PV(fOnWorkerThread);
2765	int rc;
2766
2767	/*
2768	* Grab the xmit lock of the driver as well as the E1K device state.
2769	*/
2770	PPDMINETWORKUP pDrv = pThisCC->pDrv;
2771	if (pDrv)
2772	{
2773	rc = pDrv->pfnBeginXmit(pDrv, false /fOnWorkerThread/);
2774	if (RT_FAILURE(rc))
2775	return rc;
2776	}
2777	rc = PDMDevHlpCritSectEnter(pDevIns, &pThis->CritSect, VERR_SEM_BUSY);
2778	if (RT_SUCCESS(rc))
2779	{
2780	/** @todo check if we're supposed to suspend now. */
2781	/*
2782	* Do the transmitting.
2783	*/
2784	int rc2 = pcnetAsyncTransmit(pDevIns, pThis, pThisCC, false /fOnWorkerThread/);
2785	AssertReleaseRC(rc2);
2786
2787	/*
2788	* Release the locks.
2789	*/
2790	PDMDevHlpCritSectLeave(pDevIns, &pThis->CritSect);
2791	}
2792	else
2793	AssertLogRelRC(rc);
2794	if (pDrv)
2795	pDrv->pfnEndXmit(pDrv);
2796
2797	return rc;
2798	}
2799
2800
2801	/**
2802	* Poll for changes in RX and TX descriptor rings.
2803	*/
2804	static void pcnetPollRxTx(PPDMDEVINS pDevIns, PPCNETSTATE pThis, PPCNETSTATECC pThisCC)
2805	{
2806	if (CSR_RXON(pThis))
2807	{
2808	/*
2809	* The second case is important for pcnetWaitReceiveAvail(): If CSR_CRST(pThis) was
2810	* true but pcnetR3CanReceive() returned false for some other reason we need to check
2811	* _now_ if we have to wakeup pcnetWaitReceiveAvail().
2812	*/
2813	if ( HOST_IS_OWNER(CSR_CRST(pThis)) /* only poll RDTEs if none available or ... */
2814	\|\| pThis->fMaybeOutOfSpace) /* ... for waking up pcnetWaitReceiveAvail() */
2815	pcnetRdtePoll(pDevIns, pThis);
2816	}
2817
2818	if (CSR_TDMD(pThis) \|\| (CSR_TXON(pThis) && !CSR_DPOLL(pThis)))
2819	pcnetTransmit(pDevIns, pThis, pThisCC);
2820	}
2821
2822
2823	#ifndef PCNET_NO_POLLING
2824	/**
2825	* Start the poller timer.
2826	* Poll timer interval is fixed to 500Hz. Don't stop it.
2827	* @thread EMT, TAP.
2828	*/
2829	static void pcnetPollTimerStart(PPDMDEVINS pDevIns, PPCNETSTATE pThis)
2830	{
2831	PDMDevHlpTimerSetMillies(pDevIns, pThis->hTimerPoll, 2);
2832	}
2833	#endif
2834
2835
2836	/**
2837	* Update the poller timer.
2838	* @thread EMT.
2839	*/
2840	static void pcnetPollTimer(PPDMDEVINS pDevIns, PPCNETSTATE pThis, PPCNETSTATECC pThisCC)
2841	{
2842	STAM_PROFILE_ADV_START(&pThis->StatPollTimer, a);
2843
2844	#ifdef LOG_ENABLED
2845	TMD dummy;
2846	if (CSR_STOP(pThis) \|\| CSR_SPND(pThis))
2847	Log2(("#%d pcnetPollTimer time=%#010llx CSR_STOP=%d CSR_SPND=%d\n",
2848	PCNET_INST_NR, RTTimeMilliTS(), CSR_STOP(pThis), CSR_SPND(pThis)));
2849	else
2850	Log2(("#%d pcnetPollTimer time=%#010llx TDMD=%d TXON=%d POLL=%d TDTE=%d TDRA=%#x\n",
2851	PCNET_INST_NR, RTTimeMilliTS(), CSR_TDMD(pThis), CSR_TXON(pThis),
2852	!CSR_DPOLL(pThis), pcnetTdtePoll(pDevIns, pThis, &dummy), pThis->GCTDRA));
2853	Log2(("#%d pcnetPollTimer: CSR_CXDA=%#x CSR_XMTRL=%d CSR_XMTRC=%d\n",
2854	PCNET_INST_NR, CSR_CXDA(pThis), CSR_XMTRL(pThis), CSR_XMTRC(pThis)));
2855	#endif
2856	#ifdef LOG_ENABLED
2857	if (CSR_CXDA(pThis))
2858	{
2859	TMD tmd;
2860	pcnetTmdLoad(pDevIns, pThis, &tmd, PHYSADDR(pThis, CSR_CXDA(pThis)), false);
2861	Log10(("#%d pcnetPollTimer: TMDLOAD %#010x\n", PCNET_INST_NR, PHYSADDR(pThis, CSR_CXDA(pThis))));
2862	PRINT_TMD(&tmd);
2863	}
2864	#endif
2865	if (CSR_TDMD(pThis))
2866	pcnetTransmit(pDevIns, pThis, pThisCC);
2867
2868	pcnetUpdateIrq(pDevIns, pThis);
2869
2870	/* If the receive thread is waiting for new descriptors, poll TX/RX even if polling
2871	* disabled. We wouldn't need to poll for new TX descriptors in that case but it will
2872	* not hurt as waiting for RX descriptors should happen very seldom */
2873	if (RT_LIKELY( !CSR_STOP(pThis)
2874	&& !CSR_SPND(pThis)
2875	&& ( !CSR_DPOLL(pThis)
2876	\|\| pThis->fMaybeOutOfSpace)))
2877	{
2878	/* We ensure that we poll at least every 2ms (500Hz) but not more often than
2879	* 5000 times per second. This way we completely prevent the overhead from
2880	* heavy reprogramming the timer which turned out to be very CPU-intensive.
2881	* The drawback is that csr46 and csr47 are not updated properly anymore
2882	* but so far I have not seen any guest depending on these values. The 2ms
2883	* interval is the default polling interval of the PCnet card (65536/33MHz). */
2884	#ifdef PCNET_NO_POLLING
2885	pcnetPollRxTx(pDevIns, pThis, pThisCC);
2886	#else
2887	uint64_t u64Now = PDMDevHlpTimerGet(pDevIns, pThis->hTimerPoll);
2888	if (RT_UNLIKELY(u64Now - pThis->u64LastPoll > 200000))
2889	{
2890	pThis->u64LastPoll = u64Now;
2891	pcnetPollRxTx(pDevIns, pThis, pThisCC);
2892	}
2893	if (!PDMDevHlpTimerIsActive(pDevIns, pThis->hTimerPoll))
2894	pcnetPollTimerStart(pDevIns, pThis);
2895	#endif
2896	}
2897	STAM_PROFILE_ADV_STOP(&pThis->StatPollTimer, a);
2898	}
2899
2900
2901	static VBOXSTRICTRC pcnetCSRWriteU16(PPDMDEVINS pDevIns, PPCNETSTATE pThis, PPCNETSTATECC pThisCC, uint32_t u32RAP, uint32_t val)
2902	{
2903	VBOXSTRICTRC rc = VINF_SUCCESS;
2904	Log8(("#%d pcnetCSRWriteU16: rap=%d val=%#06x\n", PCNET_INST_NR, u32RAP, val));
2905	switch (u32RAP)
2906	{
2907	case 0:
2908	{
2909	uint16_t csr0 = pThis->aCSR[0];
2910	/* Clear any interrupt flags.
2911	* Don't clear an interrupt flag which was not seen by the guest yet. */
2912	csr0 &= ~(val & 0x7f00 & pThis->u16CSR0LastSeenByGuest);
2913	csr0 = (csr0 & ~0x0040) \| (val & 0x0048);
2914	val = (val & 0x007f) \| (csr0 & 0x7f00);
2915
2916	/* Iff STOP, STRT and INIT are set, clear STRT and INIT */
2917	if ((val & 7) == 7)
2918	val &= ~3;
2919
2920	Log(("#%d CSR0: old=%#06x new=%#06x\n", PCNET_INST_NR, pThis->aCSR[0], csr0));
2921
2922	#ifndef IN_RING3
2923	if (!(csr0 & 0x0001/init/) && (val & 1))
2924	{
2925	Log(("#%d pcnetCSRWriteU16: pcnetR3Init requested => HC\n", PCNET_INST_NR));
2926	return VINF_IOM_R3_IOPORT_WRITE;
2927	}
2928	#endif
2929	pThis->aCSR[0] = csr0;
2930
2931	if (!CSR_STOP(pThis) && (val & 4))
2932	pcnetStop(pDevIns, pThis, pThisCC);
2933
2934	#ifdef IN_RING3
2935	if (!CSR_INIT(pThis) && (val & 1))
2936	pcnetR3Init(pDevIns, pThis, pThisCC);
2937	#endif
2938
2939	if (!CSR_STRT(pThis) && (val & 2))
2940	pcnetStart(pDevIns, pThis);
2941
2942	if (CSR_TDMD(pThis))
2943	pcnetTransmit(pDevIns, pThis, pThisCC);
2944
2945	return rc;
2946	}
2947	case 2: /* IADRH */
2948	if (PCNET_IS_ISA(pThis))
2949	val &= 0x00ff; /* Upper 8 bits ignored on ISA chips. */
2950	RT_FALL_THRU();
2951	case 1: /* IADRL */
2952	case 8: /* LADRF 0..15 */
2953	case 9: /* LADRF 16..31 */
2954	case 10: /* LADRF 32..47 */
2955	case 11: /* LADRF 48..63 */
2956	case 12: /* PADR 0..15 */
2957	case 13: /* PADR 16..31 */
2958	case 14: /* PADR 32..47 */
2959	case 18: /* CRBAL */
2960	case 19: /* CRBAU */
2961	case 20: /* CXBAL */
2962	case 21: /* CXBAU */
2963	case 22: /* NRBAL */
2964	case 23: /* NRBAU */
2965	case 26: /* NRDAL */
2966	case 27: /* NRDAU */
2967	case 28: /* CRDAL */
2968	case 29: /* CRDAU */
2969	case 32: /* NXDAL */
2970	case 33: /* NXDAU */
2971	case 34: /* CXDAL */
2972	case 35: /* CXDAU */
2973	case 36: /* NNRDL */
2974	case 37: /* NNRDU */
2975	case 38: /* NNXDL */
2976	case 39: /* NNXDU */
2977	case 40: /* CRBCL */
2978	case 41: /* CRBCU */
2979	case 42: /* CXBCL */
2980	case 43: /* CXBCU */
2981	case 44: /* NRBCL */
2982	case 45: /* NRBCU */
2983	case 46: /* POLL */
2984	case 47: /* POLLINT */
2985	case 72: /* RCVRC */
2986	case 74: /* XMTRC */
2987	case 112: /* MISSC */
2988	if (CSR_STOP(pThis) \|\| CSR_SPND(pThis))
2989	break;
2990	else
2991	{
2992	Log(("#%d: WRITE CSR%d, %#06x, ignoring!!\n", PCNET_INST_NR, u32RAP, val));
2993	return rc;
2994	}
2995	case 3: /* Interrupt Mask and Deferral Control */
2996	break;
2997	case 4: /* Test and Features Control */
2998	pThis->aCSR[4] &= ~(val & 0x026a);
2999	val &= ~0x026a;
3000	val \|= pThis->aCSR[4] & 0x026a;
3001	break;
3002	case 5: /* Extended Control and Interrupt 1 */
3003	pThis->aCSR[5] &= ~(val & 0x0a90);
3004	val &= ~0x0a90;
3005	val \|= pThis->aCSR[5] & 0x0a90;
3006	break;
3007	case 7: /* Extended Control and Interrupt 2 */
3008	{
3009	uint16_t csr7 = pThis->aCSR[7];
3010	csr7 &= ~0x0400 ;
3011	csr7 &= ~(val & 0x0800);
3012	csr7 \|= (val & 0x0400);
3013	pThis->aCSR[7] = csr7;
3014	return rc;
3015	}
3016	case 15: /* Mode */
3017	if ((pThis->aCSR[15] & 0x8000) != (uint16_t)(val & 0x8000) && pThis->fDriverAttached)
3018	{
3019	Log(("#%d: promiscuous mode changed to %d\n", PCNET_INST_NR, !!(val & 0x8000)));
3020	#ifndef IN_RING3
3021	return VINF_IOM_R3_IOPORT_WRITE;
3022	#else
3023	/* check for promiscuous mode change */
3024	if (pThisCC->pDrv)
3025	pThisCC->pDrv->pfnSetPromiscuousMode(pThisCC->pDrv, !!(val & 0x8000));
3026	#endif
3027	}
3028	break;
3029	case 16: /* IADRL */
3030	return pcnetCSRWriteU16(pDevIns, pThis, pThisCC, 1, val);
3031	case 17: /* IADRH */
3032	return pcnetCSRWriteU16(pDevIns, pThis, pThisCC, 2, val);
3033
3034	/*
3035	* 24 and 25 are the Base Address of Receive Descriptor.
3036	* We combine and mirror these in GCRDRA.
3037	*/
3038	case 24: /* BADRL */
3039	case 25: /* BADRU */
3040	if (!CSR_STOP(pThis) && !CSR_SPND(pThis))
3041	{
3042	Log(("#%d: WRITE CSR%d, %#06x, ignoring!!\n", PCNET_INST_NR, u32RAP, val));
3043	return rc;
3044	}
3045	if (u32RAP == 24)
3046	pThis->GCRDRA = (pThis->GCRDRA & 0xffff0000) \| (val & 0x0000ffff);
3047	else
3048	pThis->GCRDRA = (pThis->GCRDRA & 0x0000ffff) \| ((val & 0x0000ffff) << 16);
3049	Log(("#%d: WRITE CSR%d, %#06x => GCRDRA=%08x (alt init)\n", PCNET_INST_NR, u32RAP, val, pThis->GCRDRA));
3050	if (pThis->GCRDRA & (pThis->iLog2DescSize - 1))
3051	LogRel(("PCnet#%d: Warning: Misaligned RDRA (GCRDRA=%#010x)\n", PCNET_INST_NR, pThis->GCRDRA));
3052	break;
3053
3054	/*
3055	* 30 & 31 are the Base Address of Transmit Descriptor.
3056	* We combine and mirrorthese in GCTDRA.
3057	*/
3058	case 30: /* BADXL */
3059	case 31: /* BADXU */
3060	if (!CSR_STOP(pThis) && !CSR_SPND(pThis))
3061	{
3062	Log(("#%d: WRITE CSR%d, %#06x !!\n", PCNET_INST_NR, u32RAP, val));
3063	return rc;
3064	}
3065	if (u32RAP == 30)
3066	pThis->GCTDRA = (pThis->GCTDRA & 0xffff0000) \| (val & 0x0000ffff);
3067	else
3068	pThis->GCTDRA = (pThis->GCTDRA & 0x0000ffff) \| ((val & 0x0000ffff) << 16);
3069	Log(("#%d: WRITE CSR%d, %#06x => GCTDRA=%08x (alt init)\n", PCNET_INST_NR, u32RAP, val, pThis->GCTDRA));
3070	if (pThis->GCTDRA & (pThis->iLog2DescSize - 1))
3071	LogRel(("PCnet#%d: Warning: Misaligned TDRA (GCTDRA=%#010x)\n", PCNET_INST_NR, pThis->GCTDRA));
3072	break;
3073
3074	case 58: /* Software Style */
3075	rc = pcnetBCRWriteU16(pDevIns, pThis, BCR_SWS, val);
3076	break;
3077
3078	/*
3079	* Registers 76 and 78 aren't stored correctly (see todos), but I'm don't dare
3080	* try fix that right now. So, as a quick hack for 'alt init' I'll just correct them here.
3081	*/
3082	case 76: /* RCVRL / /* @todo call pcnetR3UpdateRingHandlers */
3083	/** @todo receive ring length is stored in two's complement! */
3084	case 78: /* XMTRL / /* @todo call pcnetR3UpdateRingHandlers */
3085	/** @todo transmit ring length is stored in two's complement! */
3086	if (!CSR_STOP(pThis) && !CSR_SPND(pThis))
3087	{
3088	Log(("#%d: WRITE CSR%d, %#06x !!\n", PCNET_INST_NR, u32RAP, val));
3089	return rc;
3090	}
3091	Log(("#%d: WRITE CSR%d, %#06x (hacked %#06x) (alt init)\n", PCNET_INST_NR,
3092	u32RAP, val, 1 + ~(uint16_t)val));
3093	val = 1 + ~(uint16_t)val;
3094
3095	/*
3096	* HACK ALERT! Set the counter registers too.
3097	*/
3098	pThis->aCSR[u32RAP - 4] = val;
3099	break;
3100
3101	default:
3102	return rc;
3103	}
3104	pThis->aCSR[u32RAP] = val;
3105	return rc;
3106	}
3107
3108	/**
3109	* Encode a 32-bit link speed into a custom 16-bit floating-point value
3110	*/
3111	static uint32_t pcnetLinkSpd(uint32_t speed)
3112	{
3113	unsigned exp = 0;
3114
3115	while (speed & 0xFFFFE000)
3116	{
3117	speed /= 10;
3118	++exp;
3119	}
3120	return (exp << 13) \| speed;
3121	}
3122
3123	static uint32_t pcnetCSRReadU16(PPDMDEVINS pDevIns, PPCNETSTATE pThis, uint32_t u32RAP)
3124	{
3125	uint32_t val;
3126	switch (u32RAP)
3127	{
3128	case 0:
3129	pcnetUpdateIrq(pDevIns, pThis);
3130	val = pThis->aCSR[0];
3131	val \|= (val & 0x7800) ? 0x8000 : 0;
3132	pThis->u16CSR0LastSeenByGuest = val;
3133	break;
3134	case 16:
3135	return pcnetCSRReadU16(pDevIns, pThis, 1);
3136	case 17:
3137	return pcnetCSRReadU16(pDevIns, pThis, 2);
3138	case 58:
3139	return pcnetBCRReadU16(pThis, BCR_SWS);
3140	case 68: /* Custom register to pass link speed to driver */
3141	return pcnetLinkSpd(pThis->u32LinkSpeed);
3142	case 88:
3143	val = pThis->aCSR[89];
3144	val <<= 16;
3145	val \|= pThis->aCSR[88];
3146	break;
3147	default:
3148	val = pThis->aCSR[u32RAP];
3149	}
3150	Log8(("#%d pcnetCSRReadU16: rap=%d val=%#06x\n", PCNET_INST_NR, u32RAP, val));
3151	return val;
3152	}
3153
3154	static VBOXSTRICTRC pcnetBCRWriteU16(PPDMDEVINS pDevIns, PPCNETSTATE pThis, uint32_t u32RAP, uint32_t val)
3155	{
3156	u32RAP &= 0x7f;
3157	Log7(("#%d pcnetBCRWriteU16: rap=%d val=%#06x\n", PCNET_INST_NR, u32RAP, val));
3158	switch (u32RAP)
3159	{
3160	case BCR_SWS:
3161	if (!(CSR_STOP(pThis) \|\| CSR_SPND(pThis)))
3162	return VINF_SUCCESS;
3163	val &= ~0x0300;
3164	switch (val & 0x00ff)
3165	{
3166	default:
3167	Log(("#%d Bad SWSTYLE=%#04x\n", PCNET_INST_NR, val & 0xff));
3168	RT_FALL_THRU();
3169	case 0:
3170	val \|= 0x0200; /* 16 bit */
3171	pThis->iLog2DescSize = 3;
3172	pThis->GCUpperPhys = (0xff00 & (uint32_t)pThis->aCSR[2]) << 16;
3173	break;
3174	case 1:
3175	val \|= 0x0100; /* 32 bit */
3176	pThis->iLog2DescSize = 4;
3177	pThis->GCUpperPhys = 0;
3178	break;
3179	case 2:
3180	case 3:
3181	val \|= 0x0300; /* 32 bit */
3182	pThis->iLog2DescSize = 4;
3183	pThis->GCUpperPhys = 0;
3184	break;
3185	}
3186	Log(("#%d BCR_SWS=%#06x\n", PCNET_INST_NR, val));
3187	pThis->aCSR[58] = val;
3188	RT_FALL_THRU();
3189	case BCR_LNKST:
3190	case BCR_LED1:
3191	case BCR_LED2:
3192	case BCR_LED3:
3193	case BCR_MC:
3194	case BCR_FDC:
3195	case BCR_BSBC:
3196	case BCR_EECAS:
3197	case BCR_PLAT:
3198	case BCR_MIICAS:
3199	case BCR_MIIADDR:
3200	pThis->aBCR[u32RAP] = val;
3201	break;
3202
3203	case BCR_STVAL:
3204	val &= 0xffff;
3205	pThis->aBCR[BCR_STVAL] = val;
3206	if (pThis->uDevType == DEV_AM79C973)
3207	PDMDevHlpTimerSetNano(pDevIns, pThis->hTimerSoftInt, 12800U * val);
3208	break;
3209
3210	case BCR_MIIMDR:
3211	pThis->aMII[pThis->aBCR[BCR_MIIADDR] & 0x1f] = val;
3212	Log12(("#%d pcnet: mii write %d <- %#x\n", PCNET_INST_NR, pThis->aBCR[BCR_MIIADDR] & 0x1f, val));
3213	break;
3214
3215	default:
3216	break;
3217	}
3218	return VINF_SUCCESS;
3219	}
3220
3221	static uint32_t pcnetMIIReadU16(PPCNETSTATE pThis, uint32_t miiaddr)
3222	{
3223	uint32_t val;
3224	bool autoneg, duplex, fast, isolate;
3225	STAM_COUNTER_INC(&pThis->StatMIIReads);
3226
3227	/* If the DANAS (BCR32.7) bit is set, the MAC does not do any
3228	* auto-negotiation and the PHY must be set up explicitly. DANAS
3229	* effectively disables most other BCR32 bits.
3230	*/
3231	if (pThis->aBCR[BCR_MIICAS] & 0x80)
3232	{
3233	/* PHY controls auto-negotiation. */
3234	autoneg = duplex = fast = 1;
3235	}
3236	else
3237	{
3238	/* BCR32 controls auto-negotiation. */
3239	autoneg = (pThis->aBCR[BCR_MIICAS] & 0x20) != 0;
3240	duplex = (pThis->aBCR[BCR_MIICAS] & 0x10) != 0;
3241	fast = (pThis->aBCR[BCR_MIICAS] & 0x08) != 0;
3242	}
3243
3244	/* Electrically isolating the PHY mostly disables it. */
3245	isolate = (pThis->aMII[0] & RT_BIT(10)) != 0;
3246
3247	switch (miiaddr)
3248	{
3249	case 0:
3250	/* MII basic mode control register. */
3251	val = 0;
3252	if (autoneg)
3253	val \|= 0x1000; /* Enable auto negotiation. */
3254	if (fast)
3255	val \|= 0x2000; /* 100 Mbps */
3256	if (duplex) /* Full duplex forced */
3257	val \|= 0x0100; /* Full duplex */
3258	if (isolate) /* PHY electrically isolated. */
3259	val \|= 0x0400; /* Isolated */
3260	break;
3261
3262	case 1:
3263	/* MII basic mode status register. */
3264	val = 0x7800 /* Can do 100mbps FD/HD and 10mbps FD/HD. */
3265	\| 0x0040 /* Mgmt frame preamble not required. */
3266	\| 0x0020 /* Auto-negotiation complete. */
3267	\| 0x0008 /* Able to do auto-negotiation. */
3268	\| 0x0004 /* Link up. */
3269	\| 0x0001; /* Extended Capability, i.e. registers 4+ valid. */
3270	if (!pThis->fLinkUp \|\| pThis->fLinkTempDown \|\| isolate) {
3271	val &= ~(0x0020 \| 0x0004);
3272	pThis->cLinkDownReported++;
3273	}
3274	if (!autoneg) {
3275	/* Auto-negotiation disabled. */
3276	val &= ~(0x0020 \| 0x0008);
3277	if (duplex)
3278	/* Full duplex forced. */
3279	val &= ~0x2800;
3280	else
3281	/* Half duplex forced. */
3282	val &= ~0x5000;
3283
3284	if (fast)
3285	/* 100 Mbps forced */
3286	val &= ~0x1800;
3287	else
3288	/* 10 Mbps forced */
3289	val &= ~0x6000;
3290	}
3291	break;
3292
3293	case 2:
3294	/* PHY identifier 1. */
3295	val = 0x22; /* Am79C874/AC101 PHY */
3296	break;
3297
3298	case 3:
3299	/* PHY identifier 2. */
3300	val = 0x561b; /* Am79C874/AC101 PHY */
3301	break;
3302
3303	case 4:
3304	/* Advertisement control register. */
3305	val = 0x01e0 /* Try 100mbps FD/HD and 10mbps FD/HD. */
3306	#if 0
3307	// Advertising flow control is a) not the default, and b) confuses
3308	// the link speed detection routine in Windows PCnet driver
3309	\| 0x0400 /* Try flow control. */
3310	#endif
3311	\| 0x0001; /* CSMA selector. */
3312	break;
3313
3314	case 5:
3315	/* Link partner ability register. */
3316	if (pThis->fLinkUp && !pThis->fLinkTempDown && !isolate)
3317	val = 0x8000 /* Next page bit. */
3318	\| 0x4000 /* Link partner acked us. */
3319	\| 0x0400 /* Can do flow control. */
3320	\| 0x01e0 /* Can do 100mbps FD/HD and 10mbps FD/HD. */
3321	\| 0x0001; /* Use CSMA selector. */
3322	else
3323	{
3324	val = 0;
3325	pThis->cLinkDownReported++;
3326	}
3327	break;
3328
3329	case 6:
3330	/* Auto negotiation expansion register. */
3331	if (pThis->fLinkUp && !pThis->fLinkTempDown && !isolate)
3332	val = 0x0008 /* Link partner supports npage. */
3333	\| 0x0004 /* Enable npage words. */
3334	\| 0x0001; /* Can do N-way auto-negotiation. */
3335	else
3336	{
3337	val = 0;
3338	pThis->cLinkDownReported++;
3339	}
3340	break;
3341
3342	case 18:
3343	/* Diagnostic Register (FreeBSD pcn/ac101 driver reads this). */
3344	if (pThis->fLinkUp && !pThis->fLinkTempDown && !isolate)
3345	{
3346	val = 0x0100 /* Receive PLL locked. */
3347	\| 0x0200; /* Signal detected. */
3348
3349	if (autoneg)
3350	{
3351	val \|= 0x0400 /* 100Mbps rate. */
3352	\| 0x0800; /* Full duplex. */
3353	}
3354	else
3355	{
3356	if (fast)
3357	val \|= 0x0400; /* 100Mbps rate. */
3358	if (duplex)
3359	val \|= 0x0800; /* Full duplex. */
3360	}
3361	}
3362	else
3363	{
3364	val = 0;
3365	pThis->cLinkDownReported++;
3366	}
3367	break;
3368
3369	default:
3370	val = 0;
3371	break;
3372	}
3373
3374	Log12(("#%d pcnet: mii read %d -> %#x\n", PCNET_INST_NR, miiaddr, val));
3375	return val;
3376	}
3377
3378	static uint32_t pcnetBCRReadU16(PPCNETSTATE pThis, uint32_t u32RAP)
3379	{
3380	uint32_t val;
3381	u32RAP &= 0x7f;
3382	switch (u32RAP)
3383	{
3384	case BCR_LNKST:
3385	case BCR_LED1:
3386	case BCR_LED2:
3387	case BCR_LED3:
3388	val = pThis->aBCR[u32RAP] & ~0x8000;
3389	/* Clear LNKSTE if we're not connected or if we've just loaded a VM state. */
3390	if (!pThis->fDriverAttached \|\| pThis->fLinkTempDown \|\| !pThis->fLinkUp)
3391	{
3392	if (u32RAP == 4)
3393	pThis->cLinkDownReported++;
3394	val &= ~0x40;
3395	}
3396	val \|= (val & 0x017f & pThis->u32Lnkst) ? 0x8000 : 0;
3397	break;
3398
3399	case BCR_MIIMDR:
3400	if ((pThis->uDevType == DEV_AM79C973) && (pThis->aBCR[BCR_MIIADDR] >> 5 & 0x1f) == 0)
3401	{
3402	uint32_t miiaddr = pThis->aBCR[BCR_MIIADDR] & 0x1f;
3403	val = pcnetMIIReadU16(pThis, miiaddr);
3404	}
3405	else
3406	val = 0xffff;
3407	break;
3408
3409	default:
3410	val = u32RAP < BCR_MAX_RAP ? pThis->aBCR[u32RAP] : 0;
3411	break;
3412	}
3413	Log7(("#%d pcnetBCRReadU16: rap=%d val=%#06x\n", PCNET_INST_NR, u32RAP, val));
3414	return val;
3415	}
3416
3417	#ifdef IN_RING3 /* move down */
3418	static void pcnetR3HardReset(PPDMDEVINS pDevIns, PPCNETSTATE pThis)
3419	{
3420	int i;
3421	uint16_t checksum;
3422
3423	/* Lower any raised interrupts, see @bugref(9556) */
3424	if (RT_UNLIKELY(pThis->iISR))
3425	{
3426	pThis->iISR = 0;
3427	if (!PCNET_IS_ISA(pThis))
3428	{
3429	Log(("#%d INTA=%d\n", PCNET_INST_NR, pThis->iISR));
3430	PDMDevHlpPCISetIrq(pDevIns, 0, pThis->iISR);
3431	}
3432	else
3433	{
3434	Log(("#%d IRQ=%d, state=%d\n", PCNET_INST_NR, pThis->uIsaIrq, pThis->iISR));
3435	PDMDevHlpISASetIrq(pDevIns, pThis->uIsaIrq, pThis->iISR);
3436	}
3437	}
3438	/* Initialize the PROM */
3439	Assert(sizeof(pThis->MacConfigured) == 6);
3440	memcpy(pThis->aPROM, &pThis->MacConfigured, sizeof(pThis->MacConfigured));
3441	pThis->aPROM[ 8] = 0x00;
3442	pThis->aPROM[12] = pThis->aPROM[13] = 0x00;
3443	if (pThis->uDevType == DEV_AM79C960_EB)
3444	{
3445	pThis->aPROM[14] = 0x52;
3446	pThis->aPROM[15] = 0x44; /* NI6510 EtherBlaster 'RD' signature. */
3447	}
3448	else
3449	pThis->aPROM[14] = pThis->aPROM[15] = 0x57; /* NE2100 'WW' signature. */
3450
3451	/* 0x00/0xFF=ISA, 0x01=PnP, 0x10=VLB, 0x11=PCI */
3452	if (PCNET_IS_PCI(pThis))
3453	pThis->aPROM[ 9] = 0x11;
3454	else
3455	pThis->aPROM[ 9] = 0x00;
3456
3457	for (i = 0, checksum = 0; i < 16; i++)
3458	checksum += pThis->aPROM[i];
3459	(uint16_t )&pThis->aPROM[12] = RT_H2LE_U16(checksum);
3460
3461	/* Many of the BCR values would normally be read from the EEPROM. */
3462	pThis->aBCR[BCR_MSRDA] = 0x0005;
3463	pThis->aBCR[BCR_MSWRA] = 0x0005;
3464	pThis->aBCR[BCR_MC ] = 0x0002;
3465	pThis->aBCR[BCR_LNKST] = 0x00c0;
3466	pThis->aBCR[BCR_LED1 ] = 0x0084;
3467	pThis->aBCR[BCR_LED2 ] = 0x0088;
3468	pThis->aBCR[BCR_LED3 ] = 0x0090;
3469	/* For ISA PnP cards, BCR8 reports IRQ/DMA (e.g. 0x0035 means IRQ 3, DMA 5). */
3470	pThis->aBCR[BCR_FDC ] = 0x0000;
3471	pThis->aBCR[BCR_BSBC ] = 0x9001;
3472	pThis->aBCR[BCR_EECAS] = 0x0002;
3473	pThis->aBCR[BCR_STVAL] = 0xffff;
3474	pThis->aCSR[58 ] = /* CSR58 is an alias for BCR20 */
3475	pThis->aBCR[BCR_SWS ] = 0x0200;
3476	pThis->iLog2DescSize = 3;
3477	pThis->aBCR[BCR_PLAT ] = 0xff06;
3478	pThis->aBCR[BCR_MIICAS ] = 0x20; /* Auto-negotiation on. */
3479	pThis->aBCR[BCR_MIIADDR ] = 0; /* Internal PHY on Am79C973 would be (0x1e << 5) */
3480	PPDMPCIDEV pPciDev = pDevIns->apPciDevs[0];
3481	pThis->aBCR[BCR_PCIVID] = PCIDevGetVendorId(pPciDev);
3482	pThis->aBCR[BCR_PCISID] = PCIDevGetSubSystemId(pPciDev);
3483	pThis->aBCR[BCR_PCISVID] = PCIDevGetSubSystemVendorId(pPciDev);
3484
3485	/* Reset the error counter. */
3486	pThis->uCntBadRMD = 0;
3487
3488	pcnetSoftReset(pThis);
3489	}
3490	#endif /* IN_RING3 */
3491
3492
3493	/* -=-=-=-=-=- APROM I/O Port access -=-=-=-=-=- */
3494
3495	static void pcnetAPROMWriteU8(PPCNETSTATE pThis, uint32_t addr, uint32_t val)
3496	{
3497	addr &= 0x0f;
3498	val &= 0xff;
3499	Log(("#%d pcnetAPROMWriteU8: addr=%#010x val=%#04x\n", PCNET_INST_NR, addr, val));
3500	/* Check APROMWE bit to enable write access */
3501	if (pcnetBCRReadU16(pThis, 2) & 0x80)
3502	pThis->aPROM[addr] = val;
3503	}
3504
3505	static uint32_t pcnetAPROMReadU8(PPCNETSTATE pThis, uint32_t addr)
3506	{
3507	uint32_t val = pThis->aPROM[addr &= 0x0f];
3508	Log(("#%d pcnetAPROMReadU8: addr=%#010x val=%#04x\n", PCNET_INST_NR, addr, val));
3509	return val;
3510	}
3511
3512	/**
3513	* @callback_method_impl{FNIOMIOPORTIN, APROM}
3514	*/
3515	static DECLCALLBACK(VBOXSTRICTRC)
3516	pcnetIOPortAPromRead(PPDMDEVINS pDevIns, void pvUser, RTIOPORT offPort, uint32_t pu32, unsigned cb)
3517	{
3518	PPCNETSTATE pThis = PDMDEVINS_2_DATA(pDevIns, PPCNETSTATE);
3519	VBOXSTRICTRC rc = VINF_SUCCESS;
3520	STAM_PROFILE_ADV_START(&pThis->StatAPROMRead, a);
3521	Assert(PDMDevHlpCritSectIsOwner(pDevIns, &pThis->CritSect));
3522	RT_NOREF_PV(pvUser);
3523
3524	/* FreeBSD is accessing in dwords. */
3525	if (cb == 1)
3526	*pu32 = pcnetAPROMReadU8(pThis, offPort);
3527	else if (cb == 2 && !BCR_DWIO(pThis))
3528	*pu32 = pcnetAPROMReadU8(pThis, offPort)
3529	\| (pcnetAPROMReadU8(pThis, offPort + 1) << 8);
3530	else if (cb == 4 && BCR_DWIO(pThis))
3531	*pu32 = pcnetAPROMReadU8(pThis, offPort)
3532	\| (pcnetAPROMReadU8(pThis, offPort + 1) << 8)
3533	\| (pcnetAPROMReadU8(pThis, offPort + 2) << 16)
3534	\| (pcnetAPROMReadU8(pThis, offPort + 3) << 24);
3535	else
3536	{
3537	Log(("#%d pcnetIOPortAPromRead: offPort=%RTiop cb=%d BCR_DWIO !!\n", PCNET_INST_NR, offPort, cb));
3538	rc = VERR_IOM_IOPORT_UNUSED;
3539	}
3540
3541	STAM_PROFILE_ADV_STOP(&pThis->StatAPROMRead, a);
3542	LogFlow(("#%d pcnetIOPortAPromRead: offPort=%RTiop *pu32=%#RX32 cb=%d rc=%Rrc\n",
3543	PCNET_INST_NR, offPort, *pu32, cb, VBOXSTRICTRC_VAL(rc)));
3544	return rc;
3545	}
3546
3547
3548	/**
3549	* @callback_method_impl{FNIOMIOPORTOUT, APROM}
3550	*/
3551	static DECLCALLBACK(VBOXSTRICTRC)
3552	pcnetIoPortAPromWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT offPort, uint32_t u32, unsigned cb)
3553	{
3554	PPCNETSTATE pThis = PDMDEVINS_2_DATA(pDevIns, PPCNETSTATE);
3555	VBOXSTRICTRC rc = VINF_SUCCESS;
3556	Assert(PDMDevHlpCritSectIsOwner(pDevIns, &pThis->CritSect));
3557	RT_NOREF_PV(pvUser);
3558
3559	if (cb == 1)
3560	{
3561	STAM_PROFILE_ADV_START(&pThis->StatAPROMWrite, a);
3562	pcnetAPROMWriteU8(pThis, offPort, u32);
3563	STAM_PROFILE_ADV_STOP(&pThis->StatAPROMWrite, a);
3564	}
3565	else
3566	rc = PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "offPort=%#x cb=%d u32=%#x\n", offPort, cb, u32);
3567
3568	LogFlow(("#%d pcnetIoPortAPromWrite: offPort=%RTiop u32=%#RX32 cb=%d rc=%Rrc\n",
3569	PCNET_INST_NR, offPort, u32, cb, VBOXSTRICTRC_VAL(rc)));
3570	return rc;
3571	}
3572
3573
3574	/* -=-=-=-=-=- I/O Port access -=-=-=-=-=- */
3575
3576
3577	static VBOXSTRICTRC pcnetIoPortWriteU8(PPCNETSTATE pThis, uint32_t addr, uint32_t val)
3578	{
3579	RT_NOREF1(val);
3580	Log6(("#%d pcnetIoPortWriteU8: addr=%#010x val=%#06x\n", PCNET_INST_NR, addr, val));
3581	if (RT_LIKELY(!BCR_DWIO(pThis)))
3582	{
3583	switch (addr & 0x0f)
3584	{
3585	case 0x04: /* RESET */
3586	break;
3587	}
3588	}
3589	else
3590	Log(("#%d pcnetIoPortWriteU8: addr=%#010x val=%#06x BCR_DWIO !!\n", PCNET_INST_NR, addr, val));
3591
3592	return VINF_SUCCESS;
3593	}
3594
3595	static uint32_t pcnetIoPortReadU8(PPDMDEVINS pDevIns, PPCNETSTATE pThis, uint32_t addr)
3596	{
3597	uint32_t val = UINT32_MAX;
3598
3599	if (RT_LIKELY(!BCR_DWIO(pThis)))
3600	{
3601	switch (addr & 0x0f)
3602	{
3603	case 0x04: /* RESET */
3604	pcnetSoftReset(pThis);
3605	val = 0;
3606	break;
3607	}
3608	}
3609	else
3610	Log(("#%d pcnetIoPortReadU8: addr=%#010x val=%#06x BCR_DWIO !!\n", PCNET_INST_NR, addr, val & 0xff));
3611
3612	pcnetUpdateIrq(pDevIns, pThis);
3613
3614	Log6(("#%d pcnetIoPortReadU8: addr=%#010x val=%#06x\n", PCNET_INST_NR, addr, val & 0xff));
3615	return val;
3616	}
3617
3618	static VBOXSTRICTRC pcnetIoPortWriteU16(PPDMDEVINS pDevIns, PPCNETSTATE pThis, PPCNETSTATECC pThisCC, uint32_t addr, uint32_t val)
3619	{
3620	VBOXSTRICTRC rc = VINF_SUCCESS;
3621
3622	Log6(("#%d pcnetIoPortWriteU16: addr=%#010x val=%#06x\n", PCNET_INST_NR, addr, val));
3623	if (RT_LIKELY(!BCR_DWIO(pThis)))
3624	{
3625	switch (addr & 0x0f)
3626	{
3627	case 0x00: /* RDP */
3628	pcnetPollTimer(pDevIns, pThis, pThisCC);
3629	rc = pcnetCSRWriteU16(pDevIns, pThis, pThisCC, pThis->u32RAP, val);
3630	pcnetUpdateIrq(pDevIns, pThis);
3631	break;
3632	case 0x02: /* RAP */
3633	pThis->u32RAP = val & 0x7f;
3634	break;
3635	case 0x06: /* BDP */
3636	rc = pcnetBCRWriteU16(pDevIns, pThis, pThis->u32RAP, val);
3637	break;
3638	}
3639	}
3640	else
3641	Log(("#%d pcnetIoPortWriteU16: addr=%#010x val=%#06x BCR_DWIO !!\n", PCNET_INST_NR, addr, val));
3642
3643	return rc;
3644	}
3645
3646	static uint32_t pcnetIoPortReadU16(PPDMDEVINS pDevIns, PPCNETSTATE pThis, PPCNETSTATECC pThisCC, uint32_t addr)
3647	{
3648	uint32_t val = ~0U;
3649
3650	if (RT_LIKELY(!BCR_DWIO(pThis)))
3651	{
3652	switch (addr & 0x0f)
3653	{
3654	case 0x00: /* RDP */
3655	/** @note if we're not polling, then the guest will tell us when to poll by setting TDMD in CSR0 */
3656	/** Polling is then useless here and possibly expensive. */
3657	if (!CSR_DPOLL(pThis))
3658	pcnetPollTimer(pDevIns, pThis, pThisCC);
3659
3660	val = pcnetCSRReadU16(pDevIns, pThis, pThis->u32RAP);
3661	if (pThis->u32RAP == 0) // pcnetUpdateIrq() already called by pcnetCSRReadU16()
3662	goto skip_update_irq;
3663	break;
3664	case 0x02: /* RAP */
3665	val = pThis->u32RAP;
3666	goto skip_update_irq;
3667	case 0x04: /* RESET */
3668	pcnetSoftReset(pThis);
3669	val = 0;
3670	break;
3671	case 0x06: /* BDP */
3672	val = pcnetBCRReadU16(pThis, pThis->u32RAP);
3673	break;
3674	}
3675	}
3676	else
3677	Log(("#%d pcnetIoPortReadU16: addr=%#010x val=%#06x BCR_DWIO !!\n", PCNET_INST_NR, addr, val & 0xffff));
3678
3679	pcnetUpdateIrq(pDevIns, pThis);
3680
3681	skip_update_irq:
3682	Log6(("#%d pcnetIoPortReadU16: addr=%#010x val=%#06x\n", PCNET_INST_NR, addr, val & 0xffff));
3683	return val;
3684	}
3685
3686	static VBOXSTRICTRC pcnetIoPortWriteU32(PPDMDEVINS pDevIns, PPCNETSTATE pThis, PPCNETSTATECC pThisCC, uint32_t addr, uint32_t val)
3687	{
3688	VBOXSTRICTRC rc = VINF_SUCCESS;
3689
3690	Log6(("#%d pcnetIoPortWriteU32: addr=%#010x val=%#010x\n", PCNET_INST_NR, addr, val));
3691	if (RT_LIKELY(BCR_DWIO(pThis)))
3692	{
3693	switch (addr & 0x0f)
3694	{
3695	case 0x00: /* RDP */
3696	pcnetPollTimer(pDevIns, pThis, pThisCC);
3697	rc = pcnetCSRWriteU16(pDevIns, pThis, pThisCC, pThis->u32RAP, val & 0xffff);
3698	pcnetUpdateIrq(pDevIns, pThis);
3699	break;
3700	case 0x04: /* RAP */
3701	pThis->u32RAP = val & 0x7f;
3702	break;
3703	case 0x0c: /* BDP */
3704	rc = pcnetBCRWriteU16(pDevIns, pThis, pThis->u32RAP, val & 0xffff);
3705	break;
3706	}
3707	}
3708	else if ((addr & 0x0f) == 0)
3709	{
3710	/* switch device to dword I/O mode */
3711	pcnetBCRWriteU16(pDevIns, pThis, BCR_BSBC, pcnetBCRReadU16(pThis, BCR_BSBC) \| 0x0080);
3712	Log6(("device switched into dword i/o mode\n"));
3713	}
3714	else
3715	Log(("#%d pcnetIoPortWriteU32: addr=%#010x val=%#010x !BCR_DWIO !!\n", PCNET_INST_NR, addr, val));
3716
3717	return rc;
3718	}
3719
3720	static uint32_t pcnetIoPortReadU32(PPDMDEVINS pDevIns, PPCNETSTATE pThis, PPCNETSTATECC pThisCC, uint32_t addr)
3721	{
3722	uint32_t val = ~0U;
3723
3724	if (RT_LIKELY(BCR_DWIO(pThis)))
3725	{
3726	switch (addr & 0x0f)
3727	{
3728	case 0x00: /* RDP */
3729	/** @note if we're not polling, then the guest will tell us when to poll by setting TDMD in CSR0 */
3730	/** Polling is then useless here and possibly expensive. */
3731	if (!CSR_DPOLL(pThis))
3732	pcnetPollTimer(pDevIns, pThis, pThisCC);
3733
3734	val = pcnetCSRReadU16(pDevIns, pThis, pThis->u32RAP);
3735	if (pThis->u32RAP == 0) // pcnetUpdateIrq() already called by pcnetCSRReadU16()
3736	goto skip_update_irq;
3737	break;
3738	case 0x04: /* RAP */
3739	val = pThis->u32RAP;
3740	goto skip_update_irq;
3741	case 0x08: /* RESET */
3742	pcnetSoftReset(pThis);
3743	val = 0;
3744	break;
3745	case 0x0c: /* BDP */
3746	val = pcnetBCRReadU16(pThis, pThis->u32RAP);
3747	break;
3748	}
3749	}
3750	else
3751	Log(("#%d pcnetIoPortReadU32: addr=%#010x val=%#010x !BCR_DWIO !!\n", PCNET_INST_NR, addr, val));
3752	pcnetUpdateIrq(pDevIns, pThis);
3753
3754	skip_update_irq:
3755	Log6(("#%d pcnetIoPortReadU32: addr=%#010x val=%#010x\n", PCNET_INST_NR, addr, val));
3756	return val;
3757	}
3758
3759
3760	/**
3761	* @callback_method_impl{FNIOMIOPORTIN}
3762	*/
3763	static DECLCALLBACK(VBOXSTRICTRC) pcnetIoPortRead(PPDMDEVINS pDevIns, void pvUser, RTIOPORT offPort, uint32_t pu32, unsigned cb)
3764	{
3765	PPCNETSTATE pThis = PDMDEVINS_2_DATA(pDevIns, PPCNETSTATE);
3766	PPCNETSTATECC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PPCNETSTATECC);
3767	VBOXSTRICTRC rc = VINF_SUCCESS;
3768	STAM_PROFILE_ADV_START(&pThis->CTX_SUFF_Z(StatIORead), a);
3769	Assert(PDMDevHlpCritSectIsOwner(pDevIns, &pThis->CritSect));
3770	RT_NOREF_PV(pvUser);
3771
3772	switch (cb)
3773	{
3774	case 1: *pu32 = pcnetIoPortReadU8(pDevIns, pThis, offPort); break;
3775	case 2: *pu32 = pcnetIoPortReadU16(pDevIns, pThis, pThisCC, offPort); break;
3776	case 4: *pu32 = pcnetIoPortReadU32(pDevIns, pThis, pThisCC, offPort); break;
3777	default:
3778	rc = PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "pcnetIoPortRead: unsupported op size: offset=%#10x cb=%u\n", offPort, cb);
3779	}
3780
3781	Log2(("#%d pcnetIoPortRead: offPort=%RTiop pu32=%#RX32 cb=%d rc=%Rrc\n", PCNET_INST_NR, offPort, pu32, cb, VBOXSTRICTRC_VAL(rc)));
3782	STAM_PROFILE_ADV_STOP(&pThis->CTX_SUFF_Z(StatIORead), a);
3783	return rc;
3784	}
3785
3786
3787	/**
3788	* @callback_method_impl{FNIOMIOPORTOUT}
3789	*/
3790	static DECLCALLBACK(VBOXSTRICTRC) pcnetIoPortWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT offPort, uint32_t u32, unsigned cb)
3791	{
3792	PPCNETSTATE pThis = PDMDEVINS_2_DATA(pDevIns, PPCNETSTATE);
3793	PPCNETSTATECC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PPCNETSTATECC);
3794	VBOXSTRICTRC rc;
3795	STAM_PROFILE_ADV_START(&pThis->CTX_SUFF_Z(StatIOWrite), a);
3796	Assert(PDMDevHlpCritSectIsOwner(pDevIns, &pThis->CritSect));
3797	RT_NOREF_PV(pvUser);
3798
3799	switch (cb)
3800	{
3801	case 1: rc = pcnetIoPortWriteU8(pThis, offPort, u32); break;
3802	case 2: rc = pcnetIoPortWriteU16(pDevIns, pThis, pThisCC, offPort, u32); break;
3803	case 4: rc = pcnetIoPortWriteU32(pDevIns, pThis, pThisCC, offPort, u32); break;
3804	default:
3805	rc = PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "pcnetIoPortWrite: unsupported op size: offset=%#10x cb=%u\n", offPort, cb);
3806	}
3807
3808	Log2(("#%d pcnetIoPortWrite: offPort=%RTiop u32=%#RX32 cb=%d rc=%Rrc\n", PCNET_INST_NR, offPort, u32, cb, VBOXSTRICTRC_VAL(rc)));
3809	STAM_PROFILE_ADV_STOP(&pThis->CTX_SUFF_Z(StatIOWrite), a);
3810	return rc;
3811	}
3812
3813
3814	/* -=-=-=-=-=- MMIO -=-=-=-=-=- */
3815
3816	#ifdef IN_RING3
3817
3818	static void pcnetR3MmioWriteU8(PPCNETSTATE pThis, RTGCPHYS off, uint32_t val)
3819	{
3820	Log6(("#%d pcnetR3MmioWriteU8: off=%#010x val=%#04x\n", PCNET_INST_NR, off, val));
3821	if (!(off & 0x10))
3822	pcnetAPROMWriteU8(pThis, off, val);
3823	}
3824
3825	static uint32_t pcnetR3MmioReadU8(PPCNETSTATE pThis, RTGCPHYS addr)
3826	{
3827	uint32_t val = ~0U;
3828	if (!(addr & 0x10))
3829	val = pcnetAPROMReadU8(pThis, addr);
3830	Log6(("#%d pcnetR3MmioReadU8: addr=%#010x val=%#04x\n", PCNET_INST_NR, addr, val & 0xff));
3831	return val;
3832	}
3833
3834	static VBOXSTRICTRC pcnetR3MmioWriteU16(PPDMDEVINS pDevIns, PPCNETSTATE pThis, PPCNETSTATECC pThisCC, RTGCPHYS off, uint32_t val)
3835	{
3836	VBOXSTRICTRC rcStrict;
3837	Log6(("#%d pcnetR3MmioWriteU16: off=%#010x val=%#06x\n", PCNET_INST_NR, off, val));
3838	if (off & 0x10)
3839	{
3840	rcStrict = pcnetIoPortWriteU16(pDevIns, pThis, pThisCC, off & 0x0f, val);
3841	if (rcStrict == VINF_IOM_R3_IOPORT_WRITE)
3842	rcStrict = VINF_IOM_R3_MMIO_WRITE;
3843	}
3844	else
3845	{
3846	pcnetAPROMWriteU8(pThis, off, val );
3847	pcnetAPROMWriteU8(pThis, off + 1, val >> 8);
3848	rcStrict = VINF_SUCCESS;
3849	}
3850	return rcStrict;
3851	}
3852
3853	static uint32_t pcnetR3MmioReadU16(PPDMDEVINS pDevIns, PPCNETSTATE pThis, PPCNETSTATECC pThisCC, RTGCPHYS addr)
3854	{
3855	uint32_t val = ~0U;
3856
3857	if (addr & 0x10)
3858	val = pcnetIoPortReadU16(pDevIns, pThis, pThisCC, addr & 0x0f);
3859	else
3860	{
3861	val = pcnetAPROMReadU8(pThis, addr+1);
3862	val <<= 8;
3863	val \|= pcnetAPROMReadU8(pThis, addr);
3864	}
3865	Log6(("#%d pcnetR3MmioReadU16: addr=%#010x val = %#06x\n", PCNET_INST_NR, addr, val & 0xffff));
3866	return val;
3867	}
3868
3869	static VBOXSTRICTRC pcnetR3MmioWriteU32(PPDMDEVINS pDevIns, PPCNETSTATE pThis, PPCNETSTATECC pThisCC, RTGCPHYS off, uint32_t val)
3870	{
3871	VBOXSTRICTRC rcStrict;
3872	Log6(("#%d pcnetR3MmioWriteU32: off=%#010x val=%#010x\n", PCNET_INST_NR, off, val));
3873	if (off & 0x10)
3874	{
3875	rcStrict = pcnetIoPortWriteU32(pDevIns, pThis, pThisCC, off & 0x0f, val);
3876	if (rcStrict == VINF_IOM_R3_IOPORT_WRITE)
3877	rcStrict = VINF_IOM_R3_MMIO_WRITE;
3878	}
3879	else
3880	{
3881	pcnetAPROMWriteU8(pThis, off, val );
3882	pcnetAPROMWriteU8(pThis, off + 1, val >> 8);
3883	pcnetAPROMWriteU8(pThis, off + 2, val >> 16);
3884	pcnetAPROMWriteU8(pThis, off + 3, val >> 24);
3885	rcStrict = VINF_SUCCESS;
3886	}
3887	return rcStrict;
3888	}
3889
3890	static uint32_t pcnetR3MmioReadU32(PPDMDEVINS pDevIns, PPCNETSTATE pThis, PPCNETSTATECC pThisCC, RTGCPHYS addr)
3891	{
3892	uint32_t val;
3893
3894	if (addr & 0x10)
3895	val = pcnetIoPortReadU32(pDevIns, pThis, pThisCC, addr & 0x0f);
3896	else
3897	{
3898	val = pcnetAPROMReadU8(pThis, addr+3);
3899	val <<= 8;
3900	val \|= pcnetAPROMReadU8(pThis, addr+2);
3901	val <<= 8;
3902	val \|= pcnetAPROMReadU8(pThis, addr+1);
3903	val <<= 8;
3904	val \|= pcnetAPROMReadU8(pThis, addr );
3905	}
3906	Log6(("#%d pcnetR3MmioReadU32: addr=%#010x val=%#010x\n", PCNET_INST_NR, addr, val));
3907	return val;
3908	}
3909
3910
3911	/**
3912	* @callback_method_impl{FNIOMMMIONEWREAD}
3913	*/
3914	static DECLCALLBACK(VBOXSTRICTRC) pcnetR3MmioRead(PPDMDEVINS pDevIns, void pvUser, RTGCPHYS off, void pv, unsigned cb)
3915	{
3916	PPCNETSTATE pThis = PDMDEVINS_2_DATA(pDevIns, PPCNETSTATE);
3917	PPCNETSTATECC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PPCNETSTATECC);
3918	VBOXSTRICTRC rc = VINF_SUCCESS;
3919	Assert(PDMDevHlpCritSectIsOwner(pDevIns, &pThis->CritSect));
3920	RT_NOREF_PV(pvUser);
3921
3922	/*
3923	* We have to check the range, because we're page aligning the MMIO.
3924	*/
3925	if (off < PCNET_PNPMMIO_SIZE)
3926	{
3927	STAM_PROFILE_ADV_START(&pThis->CTX_SUFF_Z(StatMMIORead), a);
3928	switch (cb)
3929	{
3930	case 1: (uint8_t )pv = pcnetR3MmioReadU8 (pThis, off); break;
3931	case 2: (uint16_t )pv = pcnetR3MmioReadU16(pDevIns, pThis, pThisCC, off); break;
3932	case 4: (uint32_t )pv = pcnetR3MmioReadU32(pDevIns, pThis, pThisCC, off); break;
3933	default:
3934	rc = PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "pcnetR3MmioRead: unsupported op size: address=%RGp cb=%u\n", off, cb);
3935	}
3936	STAM_PROFILE_ADV_STOP(&pThis->CTX_SUFF_Z(StatMMIORead), a);
3937	}
3938	else
3939	memset(pv, 0, cb);
3940
3941	LogFlow(("#%d pcnetR3MmioRead: pvUser=%p:{%.*Rhxs} cb=%d off=%RGp rc=%Rrc\n",
3942	PCNET_INST_NR, pv, cb, pv, cb, off, VBOXSTRICTRC_VAL(rc)));
3943	return rc;
3944	}
3945
3946
3947	/**
3948	* @callback_method_impl{FNIOMMMIONEWWRITE}
3949	*/
3950	static DECLCALLBACK(VBOXSTRICTRC) pcnetR3MmioWrite(PPDMDEVINS pDevIns, void pvUser, RTGCPHYS off, void const pv, unsigned cb)
3951	{
3952	PPCNETSTATE pThis = PDMDEVINS_2_DATA(pDevIns, PPCNETSTATE);
3953	PPCNETSTATECC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PPCNETSTATECC);
3954	VBOXSTRICTRC rc = VINF_SUCCESS;
3955	Assert(PDMDevHlpCritSectIsOwner(pDevIns, &pThis->CritSect));
3956	RT_NOREF_PV(pvUser);
3957
3958	/*
3959	* We have to check the range, because we're page aligning the MMIO stuff presently.
3960	*/
3961	if (off < PCNET_PNPMMIO_SIZE)
3962	{
3963	STAM_PROFILE_ADV_START(&pThis->CTX_SUFF_Z(StatMMIOWrite), a);
3964	switch (cb)
3965	{
3966	case 1: pcnetR3MmioWriteU8(pThis, off, (uint8_t )pv); break;
3967	case 2: rc = pcnetR3MmioWriteU16(pDevIns, pThis, pThisCC, off, (uint16_t )pv); break;
3968	case 4: rc = pcnetR3MmioWriteU32(pDevIns, pThis, pThisCC, off, (uint32_t )pv); break;
3969	default:
3970	rc = PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "pcnetR3MmioWrite: unsupported op size: address=%RGp cb=%u\n", off, cb);
3971	}
3972
3973	STAM_PROFILE_ADV_STOP(&pThis->CTX_SUFF_Z(StatMMIOWrite), a);
3974	}
3975	LogFlow(("#%d pcnetR3MmioWrite: pvUser=%p:{%.*Rhxs} cb=%d off=%RGp rc=%Rrc\n",
3976	PCNET_INST_NR, pv, cb, pv, cb, off, VBOXSTRICTRC_VAL(rc)));
3977	return rc;
3978	}
3979
3980
3981
3982	/* -=-=-=-=-=- Timer Callbacks -=-=-=-=-=- */
3983
3984	/**
3985	* @callback_method_impl{FNTMTIMERDEV, Poll timer}
3986	*/
3987	static DECLCALLBACK(void) pcnetR3Timer(PPDMDEVINS pDevIns, PTMTIMER pTimer, void *pvUser)
3988	{
3989	PPCNETSTATE pThis = PDMDEVINS_2_DATA(pDevIns, PPCNETSTATE);
3990	PPCNETSTATECC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PPCNETSTATECC);
3991	Assert(PDMDevHlpCritSectIsOwner(pDevIns, &pThis->CritSect));
3992	RT_NOREF(pvUser, pTimer);
3993
3994	STAM_PROFILE_ADV_START(&pThis->StatTimer, a);
3995	pcnetPollTimer(pDevIns, pThis, pThisCC);
3996	STAM_PROFILE_ADV_STOP(&pThis->StatTimer, a);
3997	}
3998
3999
4000	/**
4001	* @callback_method_impl{FNTMTIMERDEV,
4002	* Software interrupt timer callback function.}
4003	*/
4004	static DECLCALLBACK(void) pcnetR3TimerSoftInt(PPDMDEVINS pDevIns, PTMTIMER pTimer, void *pvUser)
4005	{
4006	PPCNETSTATE pThis = PDMDEVINS_2_DATA(pDevIns, PPCNETSTATE);
4007	Assert(PDMDevHlpCritSectIsOwner(pDevIns, &pThis->CritSect));
4008	RT_NOREF(pvUser, pTimer);
4009
4010	pThis->aCSR[7] \|= 0x0800; /* STINT */
4011	pcnetUpdateIrq(pDevIns, pThis);
4012	PDMDevHlpTimerSetNano(pDevIns, pThis->hTimerSoftInt, 12800U * (pThis->aBCR[BCR_STVAL] & 0xffff));
4013	}
4014
4015
4016	/**
4017	* @callback_method_impl{FNTMTIMERDEV, Restore timer callback}
4018	*
4019	* This is only called when we restore a saved state and temporarily
4020	* disconnected the network link to inform the guest that network connections
4021	* should be considered lost.
4022	*/
4023	static DECLCALLBACK(void) pcnetR3TimerRestore(PPDMDEVINS pDevIns, PTMTIMER pTimer, void *pvUser)
4024	{
4025	PPCNETSTATE pThis = PDMDEVINS_2_DATA(pDevIns, PPCNETSTATE);
4026	RT_NOREF(pTimer, pvUser);
4027
4028	int rc = PDMDevHlpCritSectEnter(pDevIns, &pThis->CritSect, VERR_SEM_BUSY);
4029	AssertReleaseRC(rc);
4030
4031	rc = VERR_GENERAL_FAILURE;
4032	if (pThis->cLinkDownReported <= PCNET_MAX_LINKDOWN_REPORTED)
4033	{
4034	rc = PDMDevHlpTimerSetMillies(pDevIns, pThis->hTimerRestore, 1500);
4035	AssertRC(rc);
4036	}
4037	if (RT_FAILURE(rc))
4038	{
4039	pThis->fLinkTempDown = false;
4040	if (pThis->fLinkUp)
4041	{
4042	LogRel(("PCnet#%d: The link is back up again after the restore.\n", pDevIns->iInstance));
4043	Log(("#%d pcnetR3TimerRestore: Clearing ERR and CERR after load. cLinkDownReported=%d\n",
4044	pDevIns->iInstance, pThis->cLinkDownReported));
4045	pThis->aCSR[0] &= ~(RT_BIT(15) \| RT_BIT(13)); /* ERR \| CERR - probably not 100% correct either... */
4046	pThis->Led.Actual.s.fError = 0;
4047	}
4048	}
4049	else
4050	Log(("#%d pcnetR3TimerRestore: cLinkDownReported=%d, wait another 1500ms...\n",
4051	pDevIns->iInstance, pThis->cLinkDownReported));
4052
4053	PDMDevHlpCritSectLeave(pDevIns, &pThis->CritSect);
4054	}
4055
4056
4057	/* -=-=-=-=-=- PCI Device Callbacks -=-=-=-=-=- */
4058
4059	/**
4060	* @callback_method_impl{FNPCIIOREGIONMAP, For the PCnet I/O Ports.}
4061	*/
4062	static DECLCALLBACK(int) pcnetR3PciMapUnmapIoPorts(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t iRegion,
4063	RTGCPHYS GCPhysAddress, RTGCPHYS cb, PCIADDRESSSPACE enmType)
4064	{
4065	PPCNETSTATE pThis = PDMDEVINS_2_DATA(pDevIns, PPCNETSTATE);
4066	int rc;
4067	RT_NOREF(iRegion, cb, enmType, pPciDev);
4068
4069	Assert(pDevIns->apPciDevs[0] == pPciDev);
4070	Assert(enmType == PCI_ADDRESS_SPACE_IO);
4071	Assert(cb >= 0x20);
4072
4073	if (GCPhysAddress != NIL_RTGCPHYS)
4074	{
4075	RTIOPORT Port = (RTIOPORT)GCPhysAddress;
4076	rc = PDMDevHlpIoPortMap(pDevIns, pThis->hIoPortsPciAProm, Port);
4077	AssertRCReturn(rc, rc);
4078	rc = PDMDevHlpIoPortMap(pDevIns, pThis->hIoPortsPci, Port + 0x10);
4079	AssertRCReturn(rc, rc);
4080	pThis->IOPortBase = Port;
4081	}
4082	else
4083	{
4084	rc = PDMDevHlpIoPortUnmap(pDevIns, pThis->hIoPortsPciAProm);
4085	AssertRCReturn(rc, rc);
4086	rc = PDMDevHlpIoPortUnmap(pDevIns, pThis->hIoPortsPci);
4087	AssertRCReturn(rc, rc);
4088	pThis->IOPortBase = 0;
4089	}
4090
4091	return VINF_SUCCESS;
4092	}
4093
4094
4095	/* -=-=-=-=-=- Debug Info Handler -=-=-=-=-=- */
4096
4097	/**
4098	* @callback_method_impl{FNDBGFHANDLERDEV}
4099	*/
4100	static DECLCALLBACK(void) pcnetR3Info(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
4101	{
4102	PPCNETSTATE pThis = PDMDEVINS_2_DATA(pDevIns, PPCNETSTATE);
4103	bool fRcvRing = false;
4104	bool fXmtRing = false;
4105	bool fAPROM = false;
4106
4107	/*
4108	* Parse args.
4109	*/
4110	if (pszArgs)
4111	{
4112	fRcvRing = strstr(pszArgs, "verbose") \|\| strstr(pszArgs, "rcv");
4113	fXmtRing = strstr(pszArgs, "verbose") \|\| strstr(pszArgs, "xmt");
4114	fAPROM = strstr(pszArgs, "verbose") \|\| strstr(pszArgs, "aprom");
4115	}
4116
4117	/*
4118	* Show info.
4119	*/
4120	const char *pcszModel;
4121	switch (pThis->uDevType)
4122	{
4123	case DEV_AM79C970A: pcszModel = "AM79C970A"; break;
4124	case DEV_AM79C973: pcszModel = "AM79C973"; break;
4125	case DEV_AM79C960: pcszModel = "AM79C960/NE2100"; break;
4126	case DEV_AM79C960_EB: pcszModel = "AM79C960/EtherBlaster"; break;
4127	default: pcszModel = "Unknown"; break;
4128	}
4129	pHlp->pfnPrintf(pHlp,
4130	"pcnet #%d: port=%RTiop mmio=%RX32 mac-cfg=%RTmac %s%s%s\n", pDevIns->iInstance,
4131	pThis->IOPortBase, PDMDevHlpMmioGetMappingAddress(pDevIns, pThis->hMmioPci),
4132	&pThis->MacConfigured, pcszModel, pDevIns->fRCEnabled ? " RC" : "", pDevIns->fR0Enabled ? " R0" : "");
4133
4134	PDMDevHlpCritSectEnter(pDevIns, &pThis->CritSect, VERR_INTERNAL_ERROR); /* Take it here so we know why we're hanging... */
4135
4136	pHlp->pfnPrintf(pHlp,
4137	"CSR0=%#06x: INIT=%d STRT=%d STOP=%d TDMD=%d TXON=%d RXON=%d IENA=%d INTR=%d IDON=%d TINT=%d RINT=%d MERR=%d\n"
4138	" MISS=%d CERR=%d BABL=%d ERR=%d\n",
4139	pThis->aCSR[0],
4140	!!(pThis->aCSR[0] & RT_BIT(0)), !!(pThis->aCSR[0] & RT_BIT(1)), !!(pThis->aCSR[0] & RT_BIT(2)), !!(pThis->aCSR[0] & RT_BIT(3)), !!(pThis->aCSR[0] & RT_BIT(4)),
4141	!!(pThis->aCSR[0] & RT_BIT(5)), !!(pThis->aCSR[0] & RT_BIT(6)), !!(pThis->aCSR[0] & RT_BIT(7)), !!(pThis->aCSR[0] & RT_BIT(8)), !!(pThis->aCSR[0] & RT_BIT(9)),
4142	!!(pThis->aCSR[0] & RT_BIT(10)), !!(pThis->aCSR[0] & RT_BIT(11)), !!(pThis->aCSR[0] & RT_BIT(12)), !!(pThis->aCSR[0] & RT_BIT(13)),
4143	!!(pThis->aCSR[0] & RT_BIT(14)), !!(pThis->aCSR[0] & RT_BIT(15)));
4144
4145	pHlp->pfnPrintf(pHlp,
4146	"CSR1=%#06x:\n",
4147	pThis->aCSR[1]);
4148
4149	pHlp->pfnPrintf(pHlp,
4150	"CSR2=%#06x:\n",
4151	pThis->aCSR[2]);
4152
4153	pHlp->pfnPrintf(pHlp,
4154	"CSR3=%#06x: BSWP=%d EMBA=%d DXMT2PD=%d LAPPEN=%d DXSUFLO=%d IDONM=%d TINTM=%d RINTM=%d MERRM=%d MISSM=%d BABLM=%d\n",
4155	pThis->aCSR[3],
4156	!!(pThis->aCSR[3] & RT_BIT(2)), !!(pThis->aCSR[3] & RT_BIT(3)), !!(pThis->aCSR[3] & RT_BIT(4)), CSR_LAPPEN(pThis),
4157	CSR_DXSUFLO(pThis), !!(pThis->aCSR[3] & RT_BIT(8)), !!(pThis->aCSR[3] & RT_BIT(9)), !!(pThis->aCSR[3] & RT_BIT(10)),
4158	!!(pThis->aCSR[3] & RT_BIT(11)), !!(pThis->aCSR[3] & RT_BIT(12)), !!(pThis->aCSR[3] & RT_BIT(14)));
4159
4160	pHlp->pfnPrintf(pHlp,
4161	"CSR4=%#06x: JABM=%d JAB=%d TXSTRM=%d TXSTRT=%d RCVCOOM=%d RCVCCO=%d UINT=%d UINTCMD=%d\n"
4162	" MFCOM=%d MFCO=%d ASTRP_RCV=%d APAD_XMT=%d DPOLL=%d TIMER=%d EMAPLUS=%d EN124=%d\n",
4163	pThis->aCSR[4],
4164	!!(pThis->aCSR[4] & RT_BIT( 0)), !!(pThis->aCSR[4] & RT_BIT( 1)), !!(pThis->aCSR[4] & RT_BIT( 2)), !!(pThis->aCSR[4] & RT_BIT( 3)),
4165	!!(pThis->aCSR[4] & RT_BIT( 4)), !!(pThis->aCSR[4] & RT_BIT( 5)), !!(pThis->aCSR[4] & RT_BIT( 6)), !!(pThis->aCSR[4] & RT_BIT( 7)),
4166	!!(pThis->aCSR[4] & RT_BIT( 8)), !!(pThis->aCSR[4] & RT_BIT( 9)), !!(pThis->aCSR[4] & RT_BIT(10)), !!(pThis->aCSR[4] & RT_BIT(11)),
4167	!!(pThis->aCSR[4] & RT_BIT(12)), !!(pThis->aCSR[4] & RT_BIT(13)), !!(pThis->aCSR[4] & RT_BIT(14)), !!(pThis->aCSR[4] & RT_BIT(15)));
4168
4169	pHlp->pfnPrintf(pHlp,
4170	"CSR5=%#06x:\n",
4171	pThis->aCSR[5]);
4172
4173	pHlp->pfnPrintf(pHlp,
4174	"CSR6=%#06x: RLEN=%#x* TLEN=%#x* [* encoded]\n",
4175	pThis->aCSR[6],
4176	(pThis->aCSR[6] >> 8) & 0xf, (pThis->aCSR[6] >> 12) & 0xf);
4177
4178	pHlp->pfnPrintf(pHlp,
4179	"CSR8..11=%#06x,%#06x,%#06x,%#06x: LADRF=%#018llx\n",
4180	pThis->aCSR[8], pThis->aCSR[9], pThis->aCSR[10], pThis->aCSR[11],
4181	(uint64_t)(pThis->aCSR[ 8] & 0xffff)
4182	\| (uint64_t)(pThis->aCSR[ 9] & 0xffff) << 16
4183	\| (uint64_t)(pThis->aCSR[10] & 0xffff) << 32
4184	\| (uint64_t)(pThis->aCSR[11] & 0xffff) << 48);
4185
4186	pHlp->pfnPrintf(pHlp,
4187	"CSR12..14=%#06x,%#06x,%#06x: PADR=%02x:%02x:%02x:%02x:%02x:%02x (Current MAC Address)\n",
4188	pThis->aCSR[12], pThis->aCSR[13], pThis->aCSR[14],
4189	pThis->aCSR[12] & 0xff,
4190	(pThis->aCSR[12] >> 8) & 0xff,
4191	pThis->aCSR[13] & 0xff,
4192	(pThis->aCSR[13] >> 8) & 0xff,
4193	pThis->aCSR[14] & 0xff,
4194	(pThis->aCSR[14] >> 8) & 0xff);
4195
4196	pHlp->pfnPrintf(pHlp,
4197	"CSR15=%#06x: DXR=%d DTX=%d LOOP=%d DXMTFCS=%d FCOLL=%d DRTY=%d INTL=%d PORTSEL=%d LTR=%d\n"
4198	" MENDECL=%d DAPC=%d DLNKTST=%d DRCVPV=%d DRCVBC=%d PROM=%d\n",
4199	pThis->aCSR[15],
4200	!!(pThis->aCSR[15] & RT_BIT( 0)), !!(pThis->aCSR[15] & RT_BIT( 1)), !!(pThis->aCSR[15] & RT_BIT( 2)), !!(pThis->aCSR[15] & RT_BIT( 3)),
4201	!!(pThis->aCSR[15] & RT_BIT( 4)), !!(pThis->aCSR[15] & RT_BIT( 5)), !!(pThis->aCSR[15] & RT_BIT( 6)), (pThis->aCSR[15] >> 7) & 3,
4202	!!(pThis->aCSR[15] & RT_BIT( 9)), !!(pThis->aCSR[15] & RT_BIT(10)), !!(pThis->aCSR[15] & RT_BIT(11)),
4203	!!(pThis->aCSR[15] & RT_BIT(12)), !!(pThis->aCSR[15] & RT_BIT(13)), !!(pThis->aCSR[15] & RT_BIT(14)), !!(pThis->aCSR[15] & RT_BIT(15)));
4204
4205	pHlp->pfnPrintf(pHlp,
4206	"CSR46=%#06x: POLL=%#06x (Poll Time Counter)\n",
4207	pThis->aCSR[46], pThis->aCSR[46] & 0xffff);
4208
4209	pHlp->pfnPrintf(pHlp,
4210	"CSR47=%#06x: POLLINT=%#06x (Poll Time Interval)\n",
4211	pThis->aCSR[47], pThis->aCSR[47] & 0xffff);
4212
4213	pHlp->pfnPrintf(pHlp,
4214	"CSR58=%#06x: SWSTYLE=%d %s SSIZE32=%d CSRPCNET=%d APERRENT=%d\n",
4215	pThis->aCSR[58],
4216	pThis->aCSR[58] & 0x7f,
4217	(pThis->aCSR[58] & 0x7f) == 0 ? "C-LANCE / PCnet-ISA"
4218	: (pThis->aCSR[58] & 0x7f) == 1 ? "ILACC"
4219	: (pThis->aCSR[58] & 0x7f) == 2 ? "PCnet-32"
4220	: (pThis->aCSR[58] & 0x7f) == 3 ? "PCnet-PCI II"
4221	: "!!reserved!!",
4222	!!(pThis->aCSR[58] & RT_BIT(8)), !!(pThis->aCSR[58] & RT_BIT(9)), !!(pThis->aCSR[58] & RT_BIT(10)));
4223
4224	pHlp->pfnPrintf(pHlp,
4225	"CSR112=%04RX32: MFC=%04x (Missed receive Frame Count)\n",
4226	pThis->aCSR[112], pThis->aCSR[112] & 0xffff);
4227
4228	pHlp->pfnPrintf(pHlp,
4229	"CSR122=%04RX32: RCVALGN=%04x (Receive Frame Align)\n",
4230	pThis->aCSR[122], !!(pThis->aCSR[122] & RT_BIT(0)));
4231
4232	pHlp->pfnPrintf(pHlp,
4233	"CSR124=%04RX32: RPA=%04x (Runt Packet Accept)\n",
4234	pThis->aCSR[122], !!(pThis->aCSR[122] & RT_BIT(3)));
4235
4236	if (pThis->uDevType == DEV_AM79C973)
4237	{
4238	/* Print a bit of the MII state. */
4239	pHlp->pfnPrintf(pHlp,
4240	"BCR32=%#06x: MIIILP=%d XPHYSP=%d XPHYFD=%d XPHYANE=%d XPHYRST=%d\n"
4241	" DANAS=%d APDW=%u APEP=%d FMDC=%u MIIPD=%d ANTST=%d\n",
4242	pThis->aBCR[32],
4243	!!(pThis->aBCR[32] & RT_BIT( 1)), !!(pThis->aBCR[32] & RT_BIT( 3)), !!(pThis->aBCR[32] & RT_BIT( 4)),
4244	!!(pThis->aBCR[32] & RT_BIT( 5)), !!(pThis->aBCR[32] & RT_BIT( 6)), !!(pThis->aBCR[32] & RT_BIT( 7)),
4245	(pThis->aBCR[32] >> 8) & 0x7,
4246	!!(pThis->aBCR[32] & RT_BIT(11)),
4247	(pThis->aBCR[32] >> 12) & 0x3,
4248	!!(pThis->aBCR[32] & RT_BIT(14)), !!(pThis->aBCR[32] & RT_BIT(15)));
4249	}
4250
4251	/*
4252	* Dump the receive ring.
4253	*/
4254	pHlp->pfnPrintf(pHlp,
4255	"RCVRL=%04x RCVRC=%04x GCRDRA=%RX32 \n"
4256	"CRDA=%08RX32 CRBA=%08RX32 CRBC=%03x CRST=%04x\n"
4257	"NRDA=%08RX32 NRBA=%08RX32 NRBC=%03x NRST=%04x\n"
4258	"NNRDA=%08RX32\n"
4259	,
4260	CSR_RCVRL(pThis), CSR_RCVRC(pThis), pThis->GCRDRA,
4261	CSR_CRDA(pThis), CSR_CRBA(pThis), CSR_CRBC(pThis), CSR_CRST(pThis),
4262	CSR_NRDA(pThis), CSR_NRBA(pThis), CSR_NRBC(pThis), CSR_NRST(pThis),
4263	CSR_NNRD(pThis));
4264	if (fRcvRing)
4265	{
4266	const unsigned cb = 1 << pThis->iLog2DescSize;
4267	RTGCPHYS32 GCPhys = pThis->GCRDRA;
4268	unsigned i = CSR_RCVRL(pThis);
4269	while (i-- > 0)
4270	{
4271	RMD rmd;
4272	pcnetRmdLoad(pDevIns, pThis, &rmd, PHYSADDR(pThis, GCPhys), false);
4273	pHlp->pfnPrintf(pHlp,
4274	"%04x %RX32:%c%c RBADR=%08RX32 BCNT=%03x MCNT=%03x "
4275	"OWN=%d ERR=%d FRAM=%d OFLO=%d CRC=%d BUFF=%d STP=%d ENP=%d BPE=%d "
4276	"PAM=%d LAFM=%d BAM=%d RCC=%02x RPC=%02x ONES=%#x ZEROS=%d\n",
4277	i, GCPhys, i + 1 == CSR_RCVRC(pThis) ? '' : ' ', GCPhys == CSR_CRDA(pThis) ? '' : ' ',
4278	rmd.rmd0.rbadr, 4096 - rmd.rmd1.bcnt, rmd.rmd2.mcnt,
4279	rmd.rmd1.own, rmd.rmd1.err, rmd.rmd1.fram, rmd.rmd1.oflo, rmd.rmd1.crc, rmd.rmd1.buff,
4280	rmd.rmd1.stp, rmd.rmd1.enp, rmd.rmd1.bpe,
4281	rmd.rmd1.pam, rmd.rmd1.lafm, rmd.rmd1.bam, rmd.rmd2.rcc, rmd.rmd2.rpc,
4282	rmd.rmd1.ones, rmd.rmd2.zeros);
4283
4284	GCPhys += cb;
4285	}
4286	}
4287
4288	/*
4289	* Dump the transmit ring.
4290	*/
4291	pHlp->pfnPrintf(pHlp,
4292	"XMTRL=%04x XMTRC=%04x GCTDRA=%08RX32 BADX=%08RX32\n"
4293	"PXDA=%08RX32 PXBC=%03x PXST=%04x\n"
4294	"CXDA=%08RX32 CXBA=%08RX32 CXBC=%03x CXST=%04x\n"
4295	"NXDA=%08RX32 NXBA=%08RX32 NXBC=%03x NXST=%04x\n"
4296	"NNXDA=%08RX32\n"
4297	,
4298	CSR_XMTRL(pThis), CSR_XMTRC(pThis),
4299	pThis->GCTDRA, CSR_BADX(pThis),
4300	CSR_PXDA(pThis), CSR_PXBC(pThis), CSR_PXST(pThis),
4301	CSR_CXDA(pThis), CSR_CXBA(pThis), CSR_CXBC(pThis), CSR_CXST(pThis),
4302	CSR_NXDA(pThis), CSR_NXBA(pThis), CSR_NXBC(pThis), CSR_NXST(pThis),
4303	CSR_NNXD(pThis));
4304	if (fXmtRing)
4305	{
4306	const unsigned cb = 1 << pThis->iLog2DescSize;
4307	RTGCPHYS32 GCPhys = pThis->GCTDRA;
4308	unsigned i = CSR_XMTRL(pThis);
4309	while (i-- > 0)
4310	{
4311	TMD tmd;
4312	pcnetTmdLoad(pDevIns, pThis, &tmd, PHYSADDR(pThis, GCPhys), false);
4313	pHlp->pfnPrintf(pHlp,
4314	"%04x %RX32:%c%c TBADR=%08RX32 BCNT=%03x OWN=%d "
4315	"ERR=%d NOFCS=%d LTINT=%d ONE=%d DEF=%d STP=%d ENP=%d BPE=%d "
4316	"BUFF=%d UFLO=%d EXDEF=%d LCOL=%d LCAR=%d RTRY=%d TDR=%03x TRC=%#x ONES=%#x\n"
4317	,
4318	i,
4319	GCPhys,
4320	i + 1 == CSR_XMTRC(pThis) ? '*' : ' ',
4321	GCPhys == CSR_CXDA(pThis) ? '*' : ' ',
4322	tmd.tmd0.tbadr,
4323	4096 - tmd.tmd1.bcnt,
4324	tmd.tmd1.own,
4325	tmd.tmd1.err,
4326	tmd.tmd1.nofcs,
4327	tmd.tmd1.ltint,
4328	tmd.tmd1.one,
4329	tmd.tmd1.def,
4330	tmd.tmd1.stp,
4331	tmd.tmd1.enp,
4332	tmd.tmd1.bpe,
4333	tmd.tmd2.buff,
4334	tmd.tmd2.uflo,
4335	tmd.tmd2.exdef,
4336	tmd.tmd2.lcol,
4337	tmd.tmd2.lcar,
4338	tmd.tmd2.rtry,
4339	tmd.tmd2.tdr,
4340	tmd.tmd2.trc,
4341	tmd.tmd1.ones);
4342
4343	GCPhys += cb;
4344	}
4345	}
4346
4347	/* Dump the Addres PROM (APROM). */
4348	if (fAPROM)
4349	{
4350	pHlp->pfnPrintf(pHlp,
4351	"Address PROM:\n %Rhxs\n", pThis->aPROM);
4352
4353
4354	}
4355
4356	PDMDevHlpCritSectLeave(pDevIns, &pThis->CritSect);
4357	}
4358
4359
4360	/* -=-=-=-=-=- Helper(s) -=-=-=-=-=- */
4361
4362	/**
4363	* Takes down the link temporarily if it's current status is up.
4364	*
4365	* This is used during restore and when replumbing the network link.
4366	*
4367	* The temporary link outage is supposed to indicate to the OS that all network
4368	* connections have been lost and that it for instance is appropriate to
4369	* renegotiate any DHCP lease.
4370	*
4371	* @param pThis The PCnet shared instance data.
4372	*/
4373	static void pcnetR3TempLinkDown(PPDMDEVINS pDevIns, PPCNETSTATE pThis)
4374	{
4375	if (pThis->fLinkUp)
4376	{
4377	pThis->fLinkTempDown = true;
4378	pThis->cLinkDownReported = 0;
4379	pThis->aCSR[0] \|= RT_BIT(15) \| RT_BIT(13); /* ERR \| CERR (this is probably wrong) */
4380	pThis->Led.Asserted.s.fError = pThis->Led.Actual.s.fError = 1;
4381	int rc = PDMDevHlpTimerSetMillies(pDevIns, pThis->hTimerRestore, pThis->cMsLinkUpDelay);
4382	AssertRC(rc);
4383	}
4384	}
4385
4386
4387	/* -=-=-=-=-=- Saved State -=-=-=-=-=- */
4388
4389	/**
4390	* Saves the configuration.
4391	*
4392	* @param pHlp The device helpers.
4393	* @param pThis The PCnet shared instance data.
4394	* @param pSSM The saved state handle.
4395	*/
4396	static void pcnetR3SaveConfig(PCPDMDEVHLPR3 pHlp, PPCNETSTATE pThis, PSSMHANDLE pSSM)
4397	{
4398	pHlp->pfnSSMPutMem(pSSM, &pThis->MacConfigured, sizeof(pThis->MacConfigured));
4399	pHlp->pfnSSMPutU8(pSSM, pThis->uDevType);
4400	pHlp->pfnSSMPutU32(pSSM, pThis->u32LinkSpeed);
4401	}
4402
4403
4404	/**
4405	* @callback_method_impl{FNSSMDEVLIVEEXEC, Pass 0 only.}
4406	*/
4407	static DECLCALLBACK(int) pcnetR3LiveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t uPass)
4408	{
4409	RT_NOREF(uPass);
4410	PPCNETSTATE pThis = PDMDEVINS_2_DATA(pDevIns, PPCNETSTATE);
4411	pcnetR3SaveConfig(pDevIns->pHlpR3, pThis, pSSM);
4412	return VINF_SSM_DONT_CALL_AGAIN;
4413	}
4414
4415
4416	/**
4417	* @callback_method_impl{FNSSMDEVSAVEPREP,
4418	* Serializes the receive thread, it may be working inside the critsect.}
4419	*/
4420	static DECLCALLBACK(int) pcnetR3SavePrep(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
4421	{
4422	RT_NOREF(pSSM);
4423	PPCNETSTATE pThis = PDMDEVINS_2_DATA(pDevIns, PPCNETSTATE);
4424
4425	int rc = PDMDevHlpCritSectEnter(pDevIns, &pThis->CritSect, VERR_SEM_BUSY);
4426	AssertRC(rc);
4427	PDMDevHlpCritSectLeave(pDevIns, &pThis->CritSect);
4428
4429	return VINF_SUCCESS;
4430	}
4431
4432
4433	/**
4434	* @callback_method_impl{FNSSMDEVSAVEEXEC}
4435	*/
4436	static DECLCALLBACK(int) pcnetR3SaveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
4437	{
4438	PPCNETSTATE pThis = PDMDEVINS_2_DATA(pDevIns, PPCNETSTATE);
4439	PCPDMDEVHLPR3 pHlp = pDevIns->pHlpR3;
4440
4441	pHlp->pfnSSMPutBool(pSSM, pThis->fLinkUp);
4442	pHlp->pfnSSMPutU32(pSSM, pThis->u32RAP);
4443	pHlp->pfnSSMPutS32(pSSM, pThis->iISR);
4444	pHlp->pfnSSMPutU32(pSSM, pThis->u32Lnkst);
4445	pHlp->pfnSSMPutBool(pSSM, false/* was ffPrivIfEnabled /); / >= If version 0.9 */
4446	pHlp->pfnSSMPutBool(pSSM, pThis->fSignalRxMiss); /* >= If version 0.10 */
4447	pHlp->pfnSSMPutGCPhys32(pSSM, pThis->GCRDRA);
4448	pHlp->pfnSSMPutGCPhys32(pSSM, pThis->GCTDRA);
4449	pHlp->pfnSSMPutMem(pSSM, pThis->aPROM, sizeof(pThis->aPROM));
4450	pHlp->pfnSSMPutMem(pSSM, pThis->aCSR, sizeof(pThis->aCSR));
4451	pHlp->pfnSSMPutMem(pSSM, pThis->aBCR, sizeof(pThis->aBCR));
4452	pHlp->pfnSSMPutMem(pSSM, pThis->aMII, sizeof(pThis->aMII));
4453	pHlp->pfnSSMPutU16(pSSM, pThis->u16CSR0LastSeenByGuest);
4454	pHlp->pfnSSMPutU64(pSSM, pThis->u64LastPoll);
4455	pcnetR3SaveConfig(pHlp, pThis, pSSM);
4456
4457	int rc = VINF_SUCCESS;
4458	#ifndef PCNET_NO_POLLING
4459	rc = PDMDevHlpTimerSave(pDevIns, pThis->hTimerPoll, pSSM);
4460	if (RT_FAILURE(rc))
4461	return rc;
4462	#endif
4463	if (pThis->uDevType == DEV_AM79C973)
4464	rc = PDMDevHlpTimerSave(pDevIns, pThis->hTimerSoftInt, pSSM);
4465	return rc;
4466	}
4467
4468
4469	/**
4470	* @callback_method_impl{FNSSMDEVLOADPREP},
4471	* Serializes the receive thread, it may be working inside the critsect.}
4472	*/
4473	static DECLCALLBACK(int) pcnetR3LoadPrep(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
4474	{
4475	PPCNETSTATE pThis = PDMDEVINS_2_DATA(pDevIns, PPCNETSTATE);
4476	PCPDMDEVHLPR3 pHlp = pDevIns->pHlpR3;
4477
4478	int rc = PDMDevHlpCritSectEnter(pDevIns, &pThis->CritSect, VERR_SEM_BUSY);
4479	AssertRC(rc);
4480
4481	uint32_t uVer = pHlp->pfnSSMHandleVersion(pSSM);
4482	if ( uVer < VBOX_FULL_VERSION_MAKE(4, 3, 6)
4483	\|\| ( uVer >= VBOX_FULL_VERSION_MAKE(4, 3, 51)
4484	&& uVer < VBOX_FULL_VERSION_MAKE(4, 3, 53)))
4485	{
4486	/* older saved states contain the shared memory region which was never used for ages. */
4487	void *pvSharedMMIOR3;
4488	rc = PDMDevHlpMmio2Create(pDevIns, pDevIns->apPciDevs[0], 2, _512K, 0, "PCnetSh", &pvSharedMMIOR3, &pThis->hMmio2Shared);
4489	if (RT_FAILURE(rc))
4490	rc = PDMDevHlpVMSetError(pDevIns, rc, RT_SRC_POS,
4491	N_("Failed to allocate the dummy shmem region for the PCnet device"));
4492	}
4493
4494	PDMDevHlpCritSectLeave(pDevIns, &pThis->CritSect);
4495	return rc;
4496	}
4497
4498
4499	/**
4500	* @callback_method_impl{FNSSMDEVLOADEXEC}
4501	*/
4502	static DECLCALLBACK(int) pcnetR3LoadExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
4503	{
4504	PPCNETSTATE pThis = PDMDEVINS_2_DATA(pDevIns, PPCNETSTATE);
4505	PPCNETSTATECC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PPCNETSTATECC);
4506	PCPDMDEVHLPR3 pHlp = pDevIns->pHlpR3;
4507
4508	if ( SSM_VERSION_MAJOR_CHANGED(uVersion, PCNET_SAVEDSTATE_VERSION)
4509	\|\| SSM_VERSION_MINOR(uVersion) < 7)
4510	return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
4511
4512	if (uPass == SSM_PASS_FINAL)
4513	{
4514	/* restore data */
4515	pHlp->pfnSSMGetBool(pSSM, &pThis->fLinkUp);
4516	int rc = pHlp->pfnSSMGetU32(pSSM, &pThis->u32RAP);
4517	AssertRCReturn(rc, rc);
4518	AssertLogRelMsgReturn(pThis->u32RAP < RT_ELEMENTS(pThis->aCSR), ("%#x\n", pThis->u32RAP), VERR_SSM_LOAD_CONFIG_MISMATCH);
4519	pHlp->pfnSSMGetS32(pSSM, &pThis->iISR);
4520	pHlp->pfnSSMGetU32(pSSM, &pThis->u32Lnkst);
4521	if ( SSM_VERSION_MAJOR(uVersion) > 0
4522	\|\| SSM_VERSION_MINOR(uVersion) >= 9)
4523	{
4524	bool fPrivIfEnabled = false;
4525	pHlp->pfnSSMGetBool(pSSM, &fPrivIfEnabled);
4526	if (fPrivIfEnabled)
4527	{
4528	/* no longer implemented */
4529	LogRel(("PCnet#%d: Cannot enable private interface!\n", PCNET_INST_NR));
4530	return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
4531	}
4532	}
4533	if ( SSM_VERSION_MAJOR(uVersion) > 0
4534	\|\| SSM_VERSION_MINOR(uVersion) >= 10)
4535	pHlp->pfnSSMGetBool(pSSM, &pThis->fSignalRxMiss);
4536	pHlp->pfnSSMGetGCPhys32(pSSM, &pThis->GCRDRA);
4537	pHlp->pfnSSMGetGCPhys32(pSSM, &pThis->GCTDRA);
4538	pHlp->pfnSSMGetMem(pSSM, &pThis->aPROM, sizeof(pThis->aPROM));
4539	pHlp->pfnSSMGetMem(pSSM, &pThis->aCSR, sizeof(pThis->aCSR));
4540	pHlp->pfnSSMGetMem(pSSM, &pThis->aBCR, sizeof(pThis->aBCR));
4541	pHlp->pfnSSMGetMem(pSSM, &pThis->aMII, sizeof(pThis->aMII));
4542	pHlp->pfnSSMGetU16(pSSM, &pThis->u16CSR0LastSeenByGuest);
4543	pHlp->pfnSSMGetU64(pSSM, &pThis->u64LastPoll);
4544	}
4545
4546	/* check config */
4547	RTMAC Mac;
4548	int rc = pHlp->pfnSSMGetMem(pSSM, &Mac, sizeof(Mac));
4549	AssertRCReturn(rc, rc);
4550	if ( memcmp(&Mac, &pThis->MacConfigured, sizeof(Mac))
4551	&& (uPass == 0 \|\| !PDMDevHlpVMTeleportedAndNotFullyResumedYet(pDevIns)) )
4552	LogRel(("PCnet#%u: The mac address differs: config=%RTmac saved=%RTmac\n", PCNET_INST_NR, &pThis->MacConfigured, &Mac));
4553
4554	uint8_t uDevType;
4555	rc = pHlp->pfnSSMGetU8(pSSM, &uDevType);
4556	AssertRCReturn(rc, rc);
4557	if (pThis->uDevType != uDevType)
4558	return pHlp->pfnSSMSetCfgError(pSSM, RT_SRC_POS, N_("The uDevType setting differs: config=%u saved=%u"), pThis->uDevType, uDevType);
4559
4560	uint32_t u32LinkSpeed;
4561	rc = pHlp->pfnSSMGetU32(pSSM, &u32LinkSpeed);
4562	AssertRCReturn(rc, rc);
4563	if ( pThis->u32LinkSpeed != u32LinkSpeed
4564	&& (uPass == 0 \|\| !PDMDevHlpVMTeleportedAndNotFullyResumedYet(pDevIns)) )
4565	LogRel(("PCnet#%u: The mac link speed differs: config=%u saved=%u\n", PCNET_INST_NR, pThis->u32LinkSpeed, u32LinkSpeed));
4566
4567	if (uPass == SSM_PASS_FINAL)
4568	{
4569	/* restore timers and stuff */
4570	#ifndef PCNET_NO_POLLING
4571	PDMDevHlpTimerLoad(pDevIns, pThis->hTimerPoll, pSSM);
4572	#endif
4573	if (pThis->uDevType == DEV_AM79C973)
4574	{
4575	if ( SSM_VERSION_MAJOR(uVersion) > 0
4576	\|\| SSM_VERSION_MINOR(uVersion) >= 8)
4577	PDMDevHlpTimerLoad(pDevIns, pThis->hTimerSoftInt, pSSM);
4578	}
4579
4580	pThis->iLog2DescSize = BCR_SWSTYLE(pThis)
4581	? 4
4582	: 3;
4583	pThis->GCUpperPhys = BCR_SSIZE32(pThis)
4584	? 0
4585	: (0xff00 & (uint32_t)pThis->aCSR[2]) << 16;
4586
4587	/* update promiscuous mode. */
4588	if (pThisCC->pDrv)
4589	pThisCC->pDrv->pfnSetPromiscuousMode(pThisCC->pDrv, CSR_PROM(pThis));
4590
4591	#ifdef PCNET_NO_POLLING
4592	/* Enable physical monitoring again (!) */
4593	pcnetR3UpdateRingHandlers(pThis);
4594	#endif
4595	/* Indicate link down to the guest OS that all network connections have
4596	been lost, unless we've been teleported here. */
4597	if (!PDMDevHlpVMTeleportedAndNotFullyResumedYet(pDevIns))
4598	pcnetR3TempLinkDown(pDevIns, pThis);
4599	}
4600
4601	return VINF_SUCCESS;
4602	}
4603
4604	/**
4605	* @callback_method_impl{FNSSMDEVLOADDONE}
4606	*/
4607	static DECLCALLBACK(int) pcnetR3LoadDone(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
4608	{
4609	RT_NOREF(pSSM);
4610	PPCNETSTATE pThis = PDMDEVINS_2_DATA(pDevIns, PPCNETSTATE);
4611	int rc = VINF_SUCCESS;
4612	if (pThis->hMmio2Shared != NIL_PGMMMIO2HANDLE)
4613	{
4614	/* drop this dummy region */
4615	rc = pDevIns->pHlpR3->pfnMmio2Destroy(pDevIns, pThis->hMmio2Shared);
4616	AssertLogRelRC(rc);
4617	pThis->hMmio2Shared = NIL_PGMMMIO2HANDLE;
4618	}
4619	return rc;
4620	}
4621
4622	/* -=-=-=-=-=- PCNETSTATE::INetworkDown -=-=-=-=-=- */
4623
4624	/**
4625	* Check if the device/driver can receive data now.
4626	*
4627	* Worker for pcnetR3NetworkDown_WaitReceiveAvail(). This must be called before
4628	* the pfnRecieve() method is called.
4629	*
4630	* @returns VBox status code.
4631	* @param pDevIns The device instance.
4632	* @param pThis The PCnet shared instance data.
4633	*/
4634	static int pcnetR3CanReceive(PPDMDEVINS pDevIns, PPCNETSTATE pThis)
4635	{
4636	int rc = PDMDevHlpCritSectEnter(pDevIns, &pThis->CritSect, VERR_SEM_BUSY);
4637	AssertReleaseRC(rc);
4638
4639	rc = VERR_NET_NO_BUFFER_SPACE;
4640
4641	if (RT_LIKELY(!CSR_DRX(pThis) && !CSR_STOP(pThis) && !CSR_SPND(pThis)))
4642	{
4643	if (HOST_IS_OWNER(CSR_CRST(pThis)) && pThis->GCRDRA)
4644	pcnetRdtePoll(pDevIns, pThis);
4645
4646	if (RT_UNLIKELY(HOST_IS_OWNER(CSR_CRST(pThis))))
4647	{
4648	/** @todo Notify the guest _now_. Will potentially increase the interrupt load */
4649	if (pThis->fSignalRxMiss)
4650	pThis->aCSR[0] \|= 0x1000; /* Set MISS flag */
4651	}
4652	else
4653	rc = VINF_SUCCESS;
4654	}
4655
4656	PDMDevHlpCritSectLeave(pDevIns, &pThis->CritSect);
4657	return rc;
4658	}
4659
4660
4661	/**
4662	* @interface_method_impl{PDMINETWORKDOWN,pfnWaitReceiveAvail}
4663	*/
4664	static DECLCALLBACK(int) pcnetR3NetworkDown_WaitReceiveAvail(PPDMINETWORKDOWN pInterface, RTMSINTERVAL cMillies)
4665	{
4666	PPCNETSTATECC pThisCC = RT_FROM_MEMBER(pInterface, PCNETSTATECC, INetworkDown);
4667	PPDMDEVINS pDevIns = pThisCC->pDevIns;
4668	PPCNETSTATE pThis = PDMDEVINS_2_DATA(pDevIns, PPCNETSTATE);
4669
4670	int rc = pcnetR3CanReceive(pDevIns, pThis);
4671	if (RT_SUCCESS(rc))
4672	return VINF_SUCCESS;
4673	if (RT_UNLIKELY(cMillies == 0))
4674	return VERR_NET_NO_BUFFER_SPACE;
4675
4676	rc = VERR_INTERRUPTED;
4677	ASMAtomicXchgBool(&pThis->fMaybeOutOfSpace, true);
4678	STAM_PROFILE_START(&pThis->StatRxOverflow, a);
4679	VMSTATE enmVMState;
4680	while (RT_LIKELY( (enmVMState = PDMDevHlpVMState(pDevIns)) == VMSTATE_RUNNING
4681	\|\| enmVMState == VMSTATE_RUNNING_LS))
4682	{
4683	int rc2 = pcnetR3CanReceive(pDevIns, pThis);
4684	if (RT_SUCCESS(rc2))
4685	{
4686	rc = VINF_SUCCESS;
4687	break;
4688	}
4689	LogFlow(("pcnetR3NetworkDown_WaitReceiveAvail: waiting cMillies=%u...\n", cMillies));
4690	/* Start the poll timer once which will remain active as long fMaybeOutOfSpace
4691	* is true -- even if (transmit) polling is disabled (CSR_DPOLL). */
4692	rc2 = PDMDevHlpCritSectEnter(pDevIns, &pThis->CritSect, VERR_SEM_BUSY);
4693	AssertReleaseRC(rc2);
4694	#ifndef PCNET_NO_POLLING
4695	pcnetPollTimerStart(pDevIns, pThis);
4696	#endif
4697	PDMDevHlpCritSectLeave(pDevIns, &pThis->CritSect);
4698	PDMDevHlpSUPSemEventWaitNoResume(pDevIns, pThis->hEventOutOfRxSpace, cMillies);
4699	}
4700	STAM_PROFILE_STOP(&pThis->StatRxOverflow, a);
4701	ASMAtomicXchgBool(&pThis->fMaybeOutOfSpace, false);
4702
4703	return rc;
4704	}
4705
4706
4707	/**
4708	* @interface_method_impl{PDMINETWORKDOWN,pfnReceive}
4709	*/
4710	static DECLCALLBACK(int) pcnetR3NetworkDown_Receive(PPDMINETWORKDOWN pInterface, const void *pvBuf, size_t cb)
4711	{
4712	PPCNETSTATECC pThisCC = RT_FROM_MEMBER(pInterface, PCNETSTATECC, INetworkDown);
4713	PPDMDEVINS pDevIns = pThisCC->pDevIns;
4714	PPCNETSTATE pThis = PDMDEVINS_2_DATA(pDevIns, PPCNETSTATE);
4715
4716	STAM_PROFILE_ADV_START(&pThis->StatReceive, a);
4717	int rc = PDMDevHlpCritSectEnter(pDevIns, &pThis->CritSect, VERR_SEM_BUSY);
4718	AssertReleaseRC(rc);
4719
4720	/*
4721	* Check for the max ethernet frame size, taking the IEEE 802.1Q (VLAN) tag into
4722	* account. Note that the CRC Checksum is optional.
4723	* Ethernet frames consist of a 14-byte header [+ 4-byte vlan tag] + a 1500-byte body [+ 4-byte CRC].
4724	*/
4725	if (RT_LIKELY( cb <= 1518
4726	\|\| ( cb <= 1522
4727	&& ((PCRTNETETHERHDR)pvBuf)->EtherType == RT_H2BE_U16_C(RTNET_ETHERTYPE_VLAN))))
4728	{
4729	bool fAddFCS = cb <= 1514
4730	\|\| ( cb <= 1518
4731	&& ((PCRTNETETHERHDR)pvBuf)->EtherType == RT_H2BE_U16_C(RTNET_ETHERTYPE_VLAN));
4732	if (cb > 70) /* unqualified guess */
4733	pThis->Led.Asserted.s.fReading = pThis->Led.Actual.s.fReading = 1;
4734	pcnetReceiveNoSync(pDevIns, pThis, pThisCC, (const uint8_t *)pvBuf, cb, fAddFCS, false);
4735	pThis->Led.Actual.s.fReading = 0;
4736	}
4737	#ifdef LOG_ENABLED
4738	else
4739	{
4740	static bool s_fFirstBigFrameLoss = true;
4741	unsigned cbMaxFrame = ((PCRTNETETHERHDR)pvBuf)->EtherType == RT_H2BE_U16_C(RTNET_ETHERTYPE_VLAN)
4742	? 1522 : 1518;
4743	if (s_fFirstBigFrameLoss)
4744	{
4745	s_fFirstBigFrameLoss = false;
4746	Log(("PCnet#%d: Received giant frame %zu, max %u. (Further giants will be reported at level5.)\n",
4747	PCNET_INST_NR, cb, cbMaxFrame));
4748	}
4749	else
4750	Log5(("PCnet#%d: Received giant frame %zu bytes, max %u.\n",
4751	PCNET_INST_NR, cb, cbMaxFrame));
4752	}
4753	#endif /* LOG_ENABLED */
4754
4755	PDMDevHlpCritSectLeave(pDevIns, &pThis->CritSect);
4756	STAM_PROFILE_ADV_STOP(&pThis->StatReceive, a);
4757
4758	return VINF_SUCCESS;
4759	}
4760
4761
4762	/**
4763	* @interface_method_impl{PDMINETWORKDOWN,pfnXmitPending}
4764	*/
4765	static DECLCALLBACK(void) pcnetR3NetworkDown_XmitPending(PPDMINETWORKDOWN pInterface)
4766	{
4767	PPCNETSTATECC pThisCC = RT_FROM_MEMBER(pInterface, PCNETSTATECC, INetworkDown);
4768	PPDMDEVINS pDevIns = pThisCC->pDevIns;
4769	PPCNETSTATE pThis = PDMDEVINS_2_DATA(pDevIns, PPCNETSTATE);
4770	pcnetXmitPending(pDevIns, pThis, pThisCC, true /fOnWorkerThread/);
4771	}
4772
4773
4774	/* -=-=-=-=-=- PCNETSTATE::INetworkConfig -=-=-=-=-=- */
4775
4776	/**
4777	* @interface_method_impl{PDMINETWORKCONFIG,pfnGetMac}
4778	*/
4779	static DECLCALLBACK(int) pcnetR3NetworkConfig_GetMac(PPDMINETWORKCONFIG pInterface, PRTMAC pMac)
4780	{
4781	PPCNETSTATECC pThisCC = RT_FROM_MEMBER(pInterface, PCNETSTATECC, INetworkConfig);
4782	PPDMDEVINS pDevIns = pThisCC->pDevIns;
4783	PPCNETSTATE pThis = PDMDEVINS_2_DATA(pDevIns, PPCNETSTATE);
4784	memcpy(pMac, pThis->aPROM, sizeof(*pMac));
4785	return VINF_SUCCESS;
4786	}
4787
4788
4789	/**
4790	* @interface_method_impl{PDMINETWORKCONFIG,pfnGetLinkState}
4791	*/
4792	static DECLCALLBACK(PDMNETWORKLINKSTATE) pcnetR3NetworkConfig_GetLinkState(PPDMINETWORKCONFIG pInterface)
4793	{
4794	PPCNETSTATECC pThisCC = RT_FROM_MEMBER(pInterface, PCNETSTATECC, INetworkConfig);
4795	PPDMDEVINS pDevIns = pThisCC->pDevIns;
4796	PPCNETSTATE pThis = PDMDEVINS_2_DATA(pDevIns, PPCNETSTATE);
4797	if (pThis->fLinkUp && !pThis->fLinkTempDown)
4798	return PDMNETWORKLINKSTATE_UP;
4799	if (!pThis->fLinkUp)
4800	return PDMNETWORKLINKSTATE_DOWN;
4801	if (pThis->fLinkTempDown)
4802	return PDMNETWORKLINKSTATE_DOWN_RESUME;
4803	AssertMsgFailed(("Invalid link state!\n"));
4804	return PDMNETWORKLINKSTATE_INVALID;
4805	}
4806
4807
4808	/**
4809	* @interface_method_impl{PDMINETWORKCONFIG,pfnSetLinkState}
4810	*/
4811	static DECLCALLBACK(int) pcnetR3NetworkConfig_SetLinkState(PPDMINETWORKCONFIG pInterface, PDMNETWORKLINKSTATE enmState)
4812	{
4813	PPCNETSTATECC pThisCC = RT_FROM_MEMBER(pInterface, PCNETSTATECC, INetworkConfig);
4814	PPDMDEVINS pDevIns = pThisCC->pDevIns;
4815	PPCNETSTATE pThis = PDMDEVINS_2_DATA(pDevIns, PPCNETSTATE);
4816	bool fLinkUp;
4817
4818	AssertMsgReturn(enmState > PDMNETWORKLINKSTATE_INVALID && enmState <= PDMNETWORKLINKSTATE_DOWN_RESUME,
4819	("Invalid link state: enmState=%d\n", enmState), VERR_INVALID_PARAMETER);
4820
4821	if (enmState == PDMNETWORKLINKSTATE_DOWN_RESUME)
4822	{
4823	pcnetR3TempLinkDown(pDevIns, pThis);
4824	/*
4825	* Note that we do not notify the driver about the link state change because
4826	* the change is only temporary and can be disregarded from the driver's
4827	* point of view (see @bugref{7057}).
4828	*/
4829	return VINF_SUCCESS;
4830	}
4831	/* has the state changed? */
4832	fLinkUp = enmState == PDMNETWORKLINKSTATE_UP;
4833	if (pThis->fLinkUp != fLinkUp)
4834	{
4835	pThis->fLinkUp = fLinkUp;
4836	if (fLinkUp)
4837	{
4838	/* Connect with a configured delay. */
4839	pThis->fLinkTempDown = true;
4840	pThis->cLinkDownReported = 0;
4841	pThis->aCSR[0] \|= RT_BIT(15) \| RT_BIT(13); /* ERR \| CERR (this is probably wrong) */
4842	pThis->Led.Asserted.s.fError = pThis->Led.Actual.s.fError = 1;
4843	int rc = PDMDevHlpTimerSetMillies(pDevIns, pThis->hTimerRestore, pThis->cMsLinkUpDelay);
4844	AssertRC(rc);
4845	}
4846	else
4847	{
4848	/* disconnect */
4849	pThis->cLinkDownReported = 0;
4850	pThis->aCSR[0] \|= RT_BIT(15) \| RT_BIT(13); /* ERR \| CERR (this is probably wrong) */
4851	pThis->Led.Asserted.s.fError = pThis->Led.Actual.s.fError = 1;
4852	}
4853	Assert(!PDMDevHlpCritSectIsOwner(pDevIns, &pThis->CritSect));
4854	if (pThisCC->pDrv)
4855	pThisCC->pDrv->pfnNotifyLinkChanged(pThisCC->pDrv, enmState);
4856	}
4857	return VINF_SUCCESS;
4858	}
4859
4860
4861	/* -=-=-=-=-=- PCNETSTATE::ILeds (LUN#0) -=-=-=-=-=- */
4862
4863	/**
4864	* @interface_method_impl{PDMILEDPORTS,pfnQueryStatusLed}
4865	*/
4866	static DECLCALLBACK(int) pcnetQueryStatusLed(PPDMILEDPORTS pInterface, unsigned iLUN, PPDMLED *ppLed)
4867	{
4868	PPCNETSTATECC pThisCC = RT_FROM_MEMBER(pInterface, PCNETSTATECC, ILeds);
4869	PPDMDEVINS pDevIns = pThisCC->pDevIns;
4870	PPCNETSTATE pThis = PDMDEVINS_2_DATA(pDevIns, PPCNETSTATE);
4871	if (iLUN == 0)
4872	{
4873	*ppLed = &pThis->Led;
4874	return VINF_SUCCESS;
4875	}
4876	return VERR_PDM_LUN_NOT_FOUND;
4877	}
4878
4879
4880	/* -=-=-=-=-=- PCNETSTATE::IBase (LUN#0) -=-=-=-=-=- */
4881
4882	/**
4883	* @interface_method_impl{PDMIBASE,pfnQueryInterface}
4884	*/
4885	static DECLCALLBACK(void ) pcnetQueryInterface(struct PDMIBASE pInterface, const char *pszIID)
4886	{
4887	PPCNETSTATECC pThisCC = RT_FROM_MEMBER(pInterface, PCNETSTATECC, IBase);
4888	Assert(&pThisCC->IBase == pInterface);
4889	PDMIBASE_RETURN_INTERFACE(pszIID, PDMIBASE, &pThisCC->IBase);
4890	PDMIBASE_RETURN_INTERFACE(pszIID, PDMINETWORKDOWN, &pThisCC->INetworkDown);
4891	PDMIBASE_RETURN_INTERFACE(pszIID, PDMINETWORKCONFIG, &pThisCC->INetworkConfig);
4892	PDMIBASE_RETURN_INTERFACE(pszIID, PDMILEDPORTS, &pThisCC->ILeds);
4893	return NULL;
4894	}
4895
4896
4897	/* -=-=-=-=-=- PDMDEVREG -=-=-=-=-=- */
4898
4899	/**
4900	* @interface_method_impl{PDMDEVREG,pfnPowerOff}
4901	*/
4902	static DECLCALLBACK(void) pcnetR3PowerOff(PPDMDEVINS pDevIns)
4903	{
4904	/* Poke thread waiting for buffer space. */
4905	pcnetWakeupReceive(pDevIns);
4906	}
4907
4908
4909	/**
4910	* @interface_method_impl{PDMDEVREG,pfnDetach}
4911	*
4912	* One port on the network card has been disconnected from the network.
4913	*/
4914	static DECLCALLBACK(void) pcnetR3Detach(PPDMDEVINS pDevIns, unsigned iLUN, uint32_t fFlags)
4915	{
4916	PPCNETSTATE pThis = PDMDEVINS_2_DATA(pDevIns, PPCNETSTATE);
4917	PPCNETSTATECC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PPCNETSTATECC);
4918	Log(("#%d pcnetR3Detach:\n", PCNET_INST_NR));
4919	RT_NOREF(fFlags);
4920
4921	AssertLogRelReturnVoid(iLUN == 0);
4922
4923	PDMDevHlpCritSectEnter(pDevIns, &pThis->CritSect, VERR_SEM_BUSY);
4924
4925	/** @todo r=pritesh still need to check if i missed
4926	* to clean something in this function
4927	*/
4928
4929	/*
4930	* Zero some important members.
4931	*/
4932	pThis->fDriverAttached = false;
4933	pThisCC->pDrvBase = NULL;
4934	pThisCC->pDrv = NULL;
4935	/// @todo figure this out
4936	//pThis->pDrvR0 = NIL_RTR0PTR;
4937	//pThis->pDrvRC = NIL_RTRCPTR;
4938
4939	PDMDevHlpCritSectLeave(pDevIns, &pThis->CritSect);
4940	}
4941
4942
4943	/**
4944	* @interface_method_impl{PDMDEVREG,pfnAttach}
4945	* One port on the network card has been connected to a network.
4946	*/
4947	static DECLCALLBACK(int) pcnetR3Attach(PPDMDEVINS pDevIns, unsigned iLUN, uint32_t fFlags)
4948	{
4949	PPCNETSTATE pThis = PDMDEVINS_2_DATA(pDevIns, PPCNETSTATE);
4950	PPCNETSTATECC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PPCNETSTATECC);
4951	LogFlow(("#%d pcnetR3Attach:\n", PCNET_INST_NR));
4952	RT_NOREF(fFlags);
4953
4954	AssertLogRelReturn(iLUN == 0, VERR_PDM_NO_SUCH_LUN);
4955
4956	PDMDevHlpCritSectEnter(pDevIns, &pThis->CritSect, VERR_SEM_BUSY);
4957
4958	/*
4959	* Attach the driver.
4960	*/
4961	int rc = PDMDevHlpDriverAttach(pDevIns, 0, &pThisCC->IBase, &pThisCC->pDrvBase, "Network Port");
4962	if (RT_SUCCESS(rc))
4963	{
4964	pThisCC->pDrv = PDMIBASE_QUERY_INTERFACE(pThisCC->pDrvBase, PDMINETWORKUP);
4965	AssertMsgStmt(pThisCC->pDrv, ("Failed to obtain the PDMINETWORKUP interface!\n"),
4966	rc = VERR_PDM_MISSING_INTERFACE_BELOW);
4967	pThis->fDriverAttached = true;
4968	/// @todo figoure out this
4969	//pThis->pDrvR0 = PDMIBASER0_QUERY_INTERFACE(PDMIBASE_QUERY_INTERFACE(pThis->pDrvBase, PDMIBASER0), PDMINETWORKUP);
4970	//pThis->pDrvRC = PDMIBASERC_QUERY_INTERFACE(PDMIBASE_QUERY_INTERFACE(pThis->pDrvBase, PDMIBASERC), PDMINETWORKUP);
4971	}
4972	else if ( rc == VERR_PDM_NO_ATTACHED_DRIVER
4973	\|\| rc == VERR_PDM_CFG_MISSING_DRIVER_NAME)
4974	{
4975	/* This should never happen because this function is not called
4976	* if there is no driver to attach! */
4977	Log(("#%d No attached driver!\n", PCNET_INST_NR));
4978	}
4979
4980	/*
4981	* Temporary set the link down if it was up so that the guest
4982	* will know that we have change the configuration of the
4983	* network card
4984	*/
4985	if (RT_SUCCESS(rc))
4986	pcnetR3TempLinkDown(pDevIns, pThis);
4987
4988	PDMDevHlpCritSectLeave(pDevIns, &pThis->CritSect);
4989	return rc;
4990
4991	}
4992
4993
4994	/**
4995	* @interface_method_impl{PDMDEVREG,pfnSuspend}
4996	*/
4997	static DECLCALLBACK(void) pcnetR3Suspend(PPDMDEVINS pDevIns)
4998	{
4999	/* Poke thread waiting for buffer space. */
5000	pcnetWakeupReceive(pDevIns);
5001	}
5002
5003
5004	/**
5005	* @interface_method_impl{PDMDEVREG,pfnReset}
5006	*/
5007	static DECLCALLBACK(void) pcnetR3Reset(PPDMDEVINS pDevIns)
5008	{
5009	PPCNETSTATE pThis = PDMDEVINS_2_DATA(pDevIns, PPCNETSTATE);
5010	if (pThis->fLinkTempDown)
5011	{
5012	pThis->cLinkDownReported = 0x10000;
5013	PDMDevHlpTimerStop(pDevIns, pThis->hTimerRestore);
5014	pcnetR3TimerRestore(pDevIns, NULL /* pTimer - not used */, pThis);
5015	}
5016
5017	/** @todo How to flush the queues? */
5018	pcnetR3HardReset(pDevIns, pThis);
5019	}
5020
5021
5022	/**
5023	* @interface_method_impl{PDMDEVREG,pfnRelocate}
5024	*/
5025	static DECLCALLBACK(void) pcnetR3Relocate(PPDMDEVINS pDevIns, RTGCINTPTR offDelta)
5026	{
5027	PPCNETSTATERC pThisRC = PDMINS_2_DATA_RC(pDevIns, PPCNETSTATERC);
5028	pThisRC->pDrv += offDelta;
5029	#ifdef PCNET_NO_POLLING
5030	pThisRC->pfnEMInterpretInstructionRC += offDelta;
5031	#endif
5032	}
5033
5034
5035	/**
5036	* @interface_method_impl{PDMDEVREG,pfnDestruct}
5037	*/
5038	static DECLCALLBACK(int) pcnetR3Destruct(PPDMDEVINS pDevIns)
5039	{
5040	PDMDEV_CHECK_VERSIONS_RETURN_QUIET(pDevIns);
5041	PPCNETSTATE pThis = PDMDEVINS_2_DATA(pDevIns, PPCNETSTATE);
5042
5043	if (pThis->hEventOutOfRxSpace == NIL_SUPSEMEVENT)
5044	{
5045	PDMDevHlpSUPSemEventSignal(pDevIns, pThis->hEventOutOfRxSpace);
5046	PDMDevHlpSUPSemEventClose(pDevIns, pThis->hEventOutOfRxSpace);
5047	pThis->hEventOutOfRxSpace = NIL_SUPSEMEVENT;
5048	}
5049
5050	if (PDMDevHlpCritSectIsInitialized(pDevIns, &pThis->CritSect))
5051	PDMDevHlpCritSectDelete(pDevIns, &pThis->CritSect);
5052	return VINF_SUCCESS;
5053	}
5054
5055
5056	/**
5057	* @interface_method_impl{PDMDEVREG,pfnConstruct}
5058	*/
5059	static DECLCALLBACK(int) pcnetR3Construct(PPDMDEVINS pDevIns, int iInstance, PCFGMNODE pCfg)
5060	{
5061	PDMDEV_CHECK_VERSIONS_RETURN(pDevIns);
5062	PPCNETSTATE pThis = PDMDEVINS_2_DATA(pDevIns, PPCNETSTATE);
5063	PPCNETSTATECC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PPCNETSTATECC);
5064	PCPDMDEVHLPR3 pHlp = pDevIns->pHlpR3;
5065	PPDMIBASE pBase;
5066	char szTmp[128];
5067	int rc;
5068
5069	Assert(RT_ELEMENTS(pThis->aBCR) == BCR_MAX_RAP);
5070	Assert(RT_ELEMENTS(pThis->aMII) == MII_MAX_REG);
5071	Assert(sizeof(pThis->abLoopBuf) == RT_ALIGN_Z(sizeof(pThis->abLoopBuf), 16));
5072
5073	/*
5074	* Init what's required to make the destructor safe.
5075	*/
5076	pThis->iInstance = iInstance;
5077	pThis->hEventOutOfRxSpace = NIL_SUPSEMEVENT;
5078	pThis->hIoPortsPci = NIL_IOMIOPORTHANDLE;
5079	pThis->hIoPortsPciAProm = NIL_IOMIOPORTHANDLE;
5080	pThis->hIoPortsIsa = NIL_IOMIOPORTHANDLE;
5081	pThis->hIoPortsIsaAProm = NIL_IOMIOPORTHANDLE;
5082	pThis->hMmio2Shared = NIL_PGMMMIO2HANDLE;
5083	pThisCC->pDevIns = pDevIns;
5084
5085	/*
5086	* Validate configuration.
5087	*/
5088	PDMDEV_VALIDATE_CONFIG_RETURN(pDevIns,
5089	"MAC\|CableConnected\|Am79C973\|ChipType\|Port\|IRQ\|LineSpeed\|PrivIfEnabled\|LinkUpDelay\|StatNo",
5090	"");
5091	/*
5092	* Read the configuration.
5093	*/
5094	rc = pHlp->pfnCFGMQueryBytes(pCfg, "MAC", &pThis->MacConfigured, sizeof(pThis->MacConfigured));
5095	if (RT_FAILURE(rc))
5096	return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to get the \"MAC\" value"));
5097	rc = pHlp->pfnCFGMQueryBoolDef(pCfg, "CableConnected", &pThis->fLinkUp, true);
5098	if (RT_FAILURE(rc))
5099	return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to get the \"CableConnected\" value"));
5100
5101	/*
5102	* Determine the model.
5103	*/
5104	char szChipType[16];
5105	rc = pHlp->pfnCFGMQueryStringDef(pCfg, "ChipType", &szChipType[0], sizeof(szChipType), "Am79C970A");
5106	if (RT_FAILURE(rc))
5107	return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Querying \"ChipType\" as string failed"));
5108
5109	if (!strcmp(szChipType, "Am79C970A"))
5110	pThis->uDevType = DEV_AM79C970A; /* 10 Mbps PCnet-PCI II. */
5111	else if (!strcmp(szChipType, "Am79C973"))
5112	pThis->uDevType = DEV_AM79C973; /* 10/100 Mbps PCnet-FAST III. */
5113	else if (!strcmp(szChipType, "Am79C960"))
5114	pThis->uDevType = DEV_AM79C960; /* 10 Mbps PCnet-ISA, NE2100/Am2100 compatible. */
5115	else if (!strcmp(szChipType, "Am79C960_EB"))
5116	{
5117	pThis->uDevType = DEV_AM79C960_EB; /* 10 Mbps PCnet-ISA, Racal InterLink NI6510 EtherBlaster compatible. */
5118	/* NI6510 drivers (at least Racal's and Linux) require the OUI to be InterLan's (Racal-Datacom).
5119	* Refuse loading if OUI doesn't match, because otherwise drivers won't load in the guest. */
5120	if (memcmp(&pThis->MacConfigured, "\x02\x07\x01", 3))
5121	return PDMDevHlpVMSetError(pDevIns, VERR_PDM_DEVINS_UNKNOWN_CFG_VALUES, RT_SRC_POS,
5122	N_("Configuration error: MAC address OUI for EtherBlaster must be 02 07 01"));
5123	}
5124	else
5125	return PDMDevHlpVMSetError(pDevIns, VERR_PDM_DEVINS_UNKNOWN_CFG_VALUES, RT_SRC_POS,
5126	N_("Configuration error: The \"ChipType\" value \"%s\" is unsupported"),
5127	szChipType);
5128
5129
5130	/*
5131	* Process the old model configuration. If present, it must take precedence for saved state compatibility.
5132	*/
5133	bool fAm79C973;
5134	rc = pHlp->pfnCFGMQueryBoolDef(pCfg, "Am79C973", &fAm79C973, false);
5135	if (RT_FAILURE(rc))
5136	return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to get the \"Am79C973\" value"));
5137	if (fAm79C973)
5138	pThis->uDevType = DEV_AM79C973;
5139
5140	/*
5141	* Process ISA configuration options. The defaults are chosen to be NE2100/Am2100 compatible.
5142	*/
5143	rc = pHlp->pfnCFGMQueryPortDef(pCfg, "Port", &pThis->IOPortBase, 0x300);
5144	if (RT_FAILURE(rc))
5145	return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to get the \"Port\" value"));
5146
5147	rc = pHlp->pfnCFGMQueryU8Def(pCfg, "IRQ", &pThis->uIsaIrq, 3);
5148	if (RT_FAILURE(rc))
5149	return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to get the \"IRQ\" value"));
5150
5151	rc = pHlp->pfnCFGMQueryU32Def(pCfg, "LineSpeed", &pThis->u32LinkSpeed, 1000000); /* 1GBit/s (in kbps units)*/
5152	if (RT_FAILURE(rc))
5153	return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to get the \"LineSpeed\" value"));
5154
5155	rc = pHlp->pfnCFGMQueryU32Def(pCfg, "LinkUpDelay", (uint32_t)&pThis->cMsLinkUpDelay, 5000); / ms */
5156	if (RT_FAILURE(rc))
5157	return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to get the value of 'LinkUpDelay'"));
5158	Assert(pThis->cMsLinkUpDelay <= 300000); /* less than 5 minutes */
5159	if (pThis->cMsLinkUpDelay > 5000 \|\| pThis->cMsLinkUpDelay < 100)
5160	LogRel(("PCnet#%d WARNING! Link up delay is set to %u seconds!\n", iInstance, pThis->cMsLinkUpDelay / 1000));
5161	Log(("#%d Link up delay is set to %u seconds\n", iInstance, pThis->cMsLinkUpDelay / 1000));
5162
5163	uint32_t uStatNo = iInstance;
5164	rc = pHlp->pfnCFGMQueryU32Def(pCfg, "StatNo", &uStatNo, iInstance);
5165	if (RT_FAILURE(rc))
5166	return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to get the \"StatNo\" value"));
5167
5168	/*
5169	* Initialize data (most of it anyway).
5170	*/
5171	pThis->Led.u32Magic = PDMLED_MAGIC;
5172	/* IBase */
5173	pThisCC->IBase.pfnQueryInterface = pcnetQueryInterface;
5174	/* INeworkPort */
5175	pThisCC->INetworkDown.pfnWaitReceiveAvail = pcnetR3NetworkDown_WaitReceiveAvail;
5176	pThisCC->INetworkDown.pfnReceive = pcnetR3NetworkDown_Receive;
5177	pThisCC->INetworkDown.pfnXmitPending = pcnetR3NetworkDown_XmitPending;
5178	/* INetworkConfig */
5179	pThisCC->INetworkConfig.pfnGetMac = pcnetR3NetworkConfig_GetMac;
5180	pThisCC->INetworkConfig.pfnGetLinkState = pcnetR3NetworkConfig_GetLinkState;
5181	pThisCC->INetworkConfig.pfnSetLinkState = pcnetR3NetworkConfig_SetLinkState;
5182	/* ILeds */
5183	pThisCC->ILeds.pfnQueryStatusLed = pcnetQueryStatusLed;
5184
5185	/* PCI Device */
5186	PPDMPCIDEV pPciDev = pDevIns->apPciDevs[0];
5187	PDMPCIDEV_ASSERT_VALID(pDevIns, pPciDev);
5188
5189	PDMPciDevSetVendorId(pPciDev, 0x1022);
5190	PDMPciDevSetDeviceId(pPciDev, 0x2000);
5191	PDMPciDevSetByte(pPciDev, 0x04, 0x07); /* command */
5192	PDMPciDevSetByte(pPciDev, 0x05, 0x00);
5193	PDMPciDevSetByte(pPciDev, 0x06, 0x80); /* status */
5194	PDMPciDevSetByte(pPciDev, 0x07, 0x02);
5195	PDMPciDevSetByte(pPciDev, 0x08, pThis->uDevType == DEV_AM79C973 ? 0x40 : 0x10); /* revision */
5196	PDMPciDevSetByte(pPciDev, 0x09, 0x00);
5197	PDMPciDevSetByte(pPciDev, 0x0a, 0x00); /* ethernet network controller */
5198	PDMPciDevSetByte(pPciDev, 0x0b, 0x02);
5199	PDMPciDevSetByte(pPciDev, 0x0e, 0x00); /* header_type */
5200	PDMPciDevSetByte(pPciDev, 0x10, 0x01); /* IO Base */
5201	PDMPciDevSetByte(pPciDev, 0x11, 0x00);
5202	PDMPciDevSetByte(pPciDev, 0x12, 0x00);
5203	PDMPciDevSetByte(pPciDev, 0x13, 0x00);
5204	PDMPciDevSetByte(pPciDev, 0x14, 0x00); /* MMIO Base */
5205	PDMPciDevSetByte(pPciDev, 0x15, 0x00);
5206	PDMPciDevSetByte(pPciDev, 0x16, 0x00);
5207	PDMPciDevSetByte(pPciDev, 0x17, 0x00);
5208
5209	/* subsystem and subvendor IDs */
5210	PDMPciDevSetByte(pPciDev, 0x2c, 0x22); /* subsystem vendor id */
5211	PDMPciDevSetByte(pPciDev, 0x2d, 0x10);
5212	PDMPciDevSetByte(pPciDev, 0x2e, 0x00); /* subsystem id */
5213	PDMPciDevSetByte(pPciDev, 0x2f, 0x20);
5214	PDMPciDevSetByte(pPciDev, 0x3d, 1); /* interrupt pin 0 */
5215	PDMPciDevSetByte(pPciDev, 0x3e, 0x06);
5216	PDMPciDevSetByte(pPciDev, 0x3f, 0xff);
5217
5218	/*
5219	* We use our own critical section (historical reasons).
5220	*/
5221	rc = PDMDevHlpCritSectInit(pDevIns, &pThis->CritSect, RT_SRC_POS, "PCnet#%u", iInstance);
5222	AssertRCReturn(rc, rc);
5223	rc = PDMDevHlpSetDeviceCritSect(pDevIns, &pThis->CritSect);
5224	AssertRCReturn(rc, rc);
5225
5226	/*
5227	* Register the PCI device, its I/O regions, the timer and the saved state item.
5228	*/
5229	Assert(PCNET_IS_PCI(pThis) != PCNET_IS_ISA(pThis)); /* IOPortBase is shared, so it's either one or the other! */
5230
5231	if (PCNET_IS_PCI(pThis))
5232	{
5233	rc = PDMDevHlpPCIRegister(pDevIns, pPciDev);
5234	AssertRCReturn(rc, rc);
5235
5236	/* Region #0: I/O ports - two handlers: */
5237	rc = PDMDevHlpIoPortCreate(pDevIns, 0x10 /cPorts/, pPciDev, 0 /iPciRegion/,
5238	pcnetIoPortAPromWrite, pcnetIOPortAPromRead, NULL /pvUser/,
5239	"PCnet APROM", NULL /paExtDescs/, &pThis->hIoPortsPciAProm);
5240	AssertRCReturn(rc, rc);
5241	rc = PDMDevHlpIoPortCreate(pDevIns, 0x10 /cPorts/, pPciDev, 0 /iPciRegion/,
5242	pcnetIoPortWrite, pcnetIoPortRead, NULL /pvUser/,
5243	"PCnet", NULL /paExtDescs/, &pThis->hIoPortsPci);
5244	AssertRCReturn(rc, rc);
5245	rc = PDMDevHlpPCIIORegionRegisterIoCustom(pDevIns, 0, PCNET_IOPORT_SIZE, pcnetR3PciMapUnmapIoPorts);
5246	AssertRCReturn(rc, rc);
5247
5248	/* Region #1: MMIO */
5249	rc = PDMDevHlpPCIIORegionCreateMmio(pDevIns, 1 /iPciRegion/, PCNET_PNPMMIO_SIZE, PCI_ADDRESS_SPACE_MEM,
5250	pcnetR3MmioWrite, pcnetR3MmioRead, NULL /pvUser/,
5251	IOMMMIO_FLAGS_READ_PASSTHRU \| IOMMMIO_FLAGS_WRITE_PASSTHRU,
5252	"PCnet", &pThis->hMmioPci);
5253	AssertRCReturn(rc, rc);
5254	}
5255
5256	/*
5257	* Register ISA I/O ranges for PCnet-ISA.
5258	*/
5259	if (PCNET_IS_ISA(pThis))
5260	{
5261	rc = PDMDevHlpIoPortCreateAndMap(pDevIns, pThis->IOPortBase, 0x10 /cPorts/, pcnetIoPortAPromWrite, pcnetIOPortAPromRead,
5262	"PCnet APROM", NULL /paExtDesc/, &pThis->hIoPortsIsaAProm);
5263	AssertRCReturn(rc, rc);
5264	rc = PDMDevHlpIoPortCreateAndMap(pDevIns, pThis->IOPortBase + 0x10, 0x10 /cPorts/, pcnetIoPortWrite, pcnetIoPortRead,
5265	"PCnet", NULL /paExtDesc/, &pThis->hIoPortsIsa);
5266	AssertRCReturn(rc, rc);
5267	}
5268
5269
5270	#ifdef PCNET_NO_POLLING
5271	/*
5272	* Resolve the R0 and RC handlers.
5273	*/
5274	rc = PDMR3LdrGetSymbolR0Lazy(PDMDevHlpGetVM(pDevIns), NULL, NULL, "EMInterpretInstruction", &pThis->pfnEMInterpretInstructionR0);
5275	if (RT_SUCCESS(rc))
5276	rc = PDMR3LdrGetSymbolRCLazy(PDMDevHlpGetVM(pDevIns), NULL, NULL, "EMInterpretInstruction", &pThis->pfnEMInterpretInstructionRC);
5277	AssertLogRelMsgRCReturn(rc, ("PDMR3LdrGetSymbolRCLazy(EMInterpretInstruction) -> %Rrc\n", rc), rc);
5278
5279	rc = PGMR3HandlerPhysicalTypeRegister(PDMDevHlpGetVM(pDevIns), PGMPHYSHANDLERKIND_WRITE,
5280	pcnetHandleRingWrite,
5281	g_DevicePCNet.szR0Mod, NULL, "pcnetHandleRingWritePf",
5282	g_DevicePCNet.szRCMod, NULL, "pcnetHandleRingWritePf",
5283	"PCnet ring write access handler",
5284	&pThis->hNoPollingHandlerType);
5285	AssertRCReturn(rc, rc);
5286
5287	#else
5288	rc = PDMDevHlpTimerCreate(pDevIns, TMCLOCK_VIRTUAL, pcnetR3Timer, NULL, TMTIMER_FLAGS_NO_CRIT_SECT,
5289	"PCnet Poll Timer", &pThis->hTimerPoll);
5290	AssertRCReturn(rc, rc);
5291	rc = PDMDevHlpTimerSetCritSect(pDevIns, pThis->hTimerPoll, &pThis->CritSect);
5292	AssertRCReturn(rc, rc);
5293	#endif
5294	if (pThis->uDevType == DEV_AM79C973)
5295	{
5296	/* Software Interrupt timer */
5297	rc = PDMDevHlpTimerCreate(pDevIns, TMCLOCK_VIRTUAL, pcnetR3TimerSoftInt, NULL, TMTIMER_FLAGS_NO_CRIT_SECT,
5298	"PCnet SoftInt Timer", &pThis->hTimerSoftInt);
5299	AssertRCReturn(rc, rc);
5300	rc = PDMDevHlpTimerSetCritSect(pDevIns, pThis->hTimerSoftInt, &pThis->CritSect);
5301	AssertRCReturn(rc, rc);
5302	}
5303	rc = PDMDevHlpTimerCreate(pDevIns, TMCLOCK_VIRTUAL, pcnetR3TimerRestore, pThis, TMTIMER_FLAGS_NO_CRIT_SECT,
5304	"PCnet Restore Timer", &pThis->hTimerRestore);
5305	AssertRCReturn(rc, rc);
5306
5307	rc = PDMDevHlpSSMRegisterEx(pDevIns, PCNET_SAVEDSTATE_VERSION, sizeof(*pThis), NULL,
5308	NULL, pcnetR3LiveExec, NULL,
5309	pcnetR3SavePrep, pcnetR3SaveExec, NULL,
5310	pcnetR3LoadPrep, pcnetR3LoadExec, pcnetR3LoadDone);
5311	AssertRCReturn(rc, rc);
5312
5313	/*
5314	* Create the transmit queue.
5315	*/
5316	rc = PDMDevHlpTaskCreate(pDevIns, PDMTASK_F_RZ, "PCnet-Xmit", pcnetR3XmitTaskCallback, NULL /pvUser/, &pThis->hXmitTask);
5317	AssertRCReturn(rc, rc);
5318
5319	/*
5320	* Create the RX notifier semaphore.
5321	*/
5322	rc = PDMDevHlpSUPSemEventCreate(pDevIns, &pThis->hEventOutOfRxSpace);
5323	AssertRCReturn(rc, rc);
5324
5325	/*
5326	* Attach status driver (optional).
5327	*/
5328	rc = PDMDevHlpDriverAttach(pDevIns, PDM_STATUS_LUN, &pThisCC->IBase, &pBase, "Status Port");
5329	if (RT_SUCCESS(rc))
5330	pThisCC->pLedsConnector = PDMIBASE_QUERY_INTERFACE(pBase, PDMILEDCONNECTORS);
5331	else
5332	AssertMsgReturn( rc == VERR_PDM_NO_ATTACHED_DRIVER
5333	\|\| rc == VERR_PDM_CFG_MISSING_DRIVER_NAME,
5334	("Failed to attach to status driver. rc=%Rrc\n", rc),
5335	rc);
5336
5337	/*
5338	* Attach driver.
5339	*/
5340	rc = PDMDevHlpDriverAttach(pDevIns, 0, &pThisCC->IBase, &pThisCC->pDrvBase, "Network Port");
5341	if (RT_SUCCESS(rc))
5342	{
5343	pThisCC->pDrv = PDMIBASE_QUERY_INTERFACE(pThisCC->pDrvBase, PDMINETWORKUP);
5344	AssertMsgReturn(pThisCC->pDrv, ("Failed to obtain the PDMINETWORKUP interface!\n"),
5345	VERR_PDM_MISSING_INTERFACE_BELOW);
5346	pThis->fDriverAttached = true;
5347	/// @todo figure out this!
5348	//pThis->pDrvR0 = PDMIBASER0_QUERY_INTERFACE(PDMIBASE_QUERY_INTERFACE(pThis->pDrvBase, PDMIBASER0), PDMINETWORKUP);
5349	//pThis->pDrvRC = PDMIBASERC_QUERY_INTERFACE(PDMIBASE_QUERY_INTERFACE(pThis->pDrvBase, PDMIBASERC), PDMINETWORKUP);
5350	}
5351	else if ( rc == VERR_PDM_NO_ATTACHED_DRIVER
5352	\|\| rc == VERR_PDM_CFG_MISSING_DRIVER_NAME)
5353	{
5354	/* No error! */
5355	Log(("No attached driver!\n"));
5356	}
5357	else
5358	return rc;
5359
5360	/*
5361	* Reset the device state. (Do after attaching.)
5362	*/
5363	pcnetR3HardReset(pDevIns, pThis);
5364
5365	/*
5366	* Register the info item.
5367	*/
5368	RTStrPrintf(szTmp, sizeof(szTmp), "pcnet%d", pDevIns->iInstance);
5369	PDMDevHlpDBGFInfoRegister(pDevIns, szTmp, "PCNET info.", pcnetR3Info);
5370
5371	/*
5372	* Register statistics.
5373	* The /Public/ bits are official and used by session info in the GUI.
5374	*/
5375	PDMDevHlpSTAMRegisterF(pDevIns, &pThis->StatReceiveBytes, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_BYTES,
5376	"Amount of data received", "/Public/NetAdapter/%u/BytesReceived", uStatNo);
5377	PDMDevHlpSTAMRegisterF(pDevIns, &pThis->StatTransmitBytes, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_BYTES,
5378	"Amount of data transmitted", "/Public/NetAdapter/%u/BytesTransmitted", uStatNo);
5379	PDMDevHlpSTAMRegisterF(pDevIns, &pDevIns->iInstance, STAMTYPE_U32, STAMVISIBILITY_ALWAYS, STAMUNIT_NONE,
5380	"Device instance number", "/Public/NetAdapter/%u/%s", uStatNo, pDevIns->pReg->szName);
5381
5382	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatReceiveBytes, STAMTYPE_COUNTER, "ReceiveBytes", STAMUNIT_BYTES, "Amount of data received");
5383	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatTransmitBytes, STAMTYPE_COUNTER, "TransmitBytes", STAMUNIT_BYTES, "Amount of data transmitted");
5384
5385	#ifdef VBOX_WITH_STATISTICS
5386	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMMIOReadRZ, STAMTYPE_PROFILE, "MMIO/ReadRZ", STAMUNIT_TICKS_PER_CALL, "Profiling MMIO reads in RZ");
5387	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMMIOReadR3, STAMTYPE_PROFILE, "MMIO/ReadR3", STAMUNIT_TICKS_PER_CALL, "Profiling MMIO reads in R3");
5388	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMMIOWriteRZ, STAMTYPE_PROFILE, "MMIO/WriteRZ", STAMUNIT_TICKS_PER_CALL, "Profiling MMIO writes in RZ");
5389	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMMIOWriteR3, STAMTYPE_PROFILE, "MMIO/WriteR3", STAMUNIT_TICKS_PER_CALL, "Profiling MMIO writes in R3");
5390	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatAPROMRead, STAMTYPE_PROFILE, "IO/APROMRead", STAMUNIT_TICKS_PER_CALL, "Profiling APROM reads");
5391	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatAPROMWrite, STAMTYPE_PROFILE, "IO/APROMWrite", STAMUNIT_TICKS_PER_CALL, "Profiling APROM writes");
5392	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatIOReadRZ, STAMTYPE_PROFILE, "IO/ReadRZ", STAMUNIT_TICKS_PER_CALL, "Profiling IO reads in RZ");
5393	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatIOReadR3, STAMTYPE_PROFILE, "IO/ReadR3", STAMUNIT_TICKS_PER_CALL, "Profiling IO reads in R3");
5394	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatIOWriteRZ, STAMTYPE_PROFILE, "IO/WriteRZ", STAMUNIT_TICKS_PER_CALL, "Profiling IO writes in RZ");
5395	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatIOWriteR3, STAMTYPE_PROFILE, "IO/WriteR3", STAMUNIT_TICKS_PER_CALL, "Profiling IO writes in R3");
5396	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatTimer, STAMTYPE_PROFILE, "Timer", STAMUNIT_TICKS_PER_CALL, "Profiling Timer");
5397	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatReceive, STAMTYPE_PROFILE, "Receive", STAMUNIT_TICKS_PER_CALL, "Profiling receive");
5398	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatRxOverflow, STAMTYPE_PROFILE, "RxOverflow", STAMUNIT_TICKS_PER_OCCURENCE, "Profiling RX overflows");
5399	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatRxOverflowWakeup, STAMTYPE_PROFILE, "RxOverflowWakeup", STAMUNIT_TICKS_PER_OCCURENCE, "Nr of RX overflow wakeups");
5400	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatTransmitCase1, STAMTYPE_COUNTER, "Transmit/Case1", STAMUNIT_OCCURENCES, "Single descriptor transmit");
5401	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatTransmitCase2, STAMTYPE_COUNTER, "Transmit/Case2", STAMUNIT_OCCURENCES, "Multi descriptor transmit");
5402	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatTransmitRZ, STAMTYPE_PROFILE, "Transmit/TotalRZ", STAMUNIT_TICKS_PER_CALL, "Profiling transmits in RZ");
5403	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatTransmitR3, STAMTYPE_PROFILE, "Transmit/TotalR3", STAMUNIT_TICKS_PER_CALL, "Profiling transmits in R3");
5404	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatTransmitSendRZ, STAMTYPE_PROFILE, "Transmit/SendRZ", STAMUNIT_TICKS_PER_CALL, "Profiling PCnet send transmit in RZ");
5405	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatTransmitSendR3, STAMTYPE_PROFILE, "Transmit/SendR3", STAMUNIT_TICKS_PER_CALL, "Profiling PCnet send transmit in R3");
5406	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatTxLenCalcRZ, STAMTYPE_PROFILE, "Transmit/LenCalcRZ", STAMUNIT_TICKS_PER_CALL, "Profiling PCnet TX len calc in RZ");
5407	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatTxLenCalcR3, STAMTYPE_PROFILE, "Transmit/LenCalcR3", STAMUNIT_TICKS_PER_CALL, "Profiling PCnet TX len calc in R3");
5408	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatTdtePollRZ, STAMTYPE_PROFILE, "TdtePollRZ", STAMUNIT_TICKS_PER_CALL, "Profiling PCnet TdtePoll in RZ");
5409	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatTdtePollR3, STAMTYPE_PROFILE, "TdtePollR3", STAMUNIT_TICKS_PER_CALL, "Profiling PCnet TdtePoll in R3");
5410	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatRdtePollRZ, STAMTYPE_PROFILE, "RdtePollRZ", STAMUNIT_TICKS_PER_CALL, "Profiling PCnet RdtePoll in RZ");
5411	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatRdtePollR3, STAMTYPE_PROFILE, "RdtePollR3", STAMUNIT_TICKS_PER_CALL, "Profiling PCnet RdtePoll in R3");
5412
5413	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatTmdStoreRZ, STAMTYPE_PROFILE, "TmdStoreRZ", STAMUNIT_TICKS_PER_CALL, "Profiling PCnet TmdStore in RZ");
5414	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatTmdStoreR3, STAMTYPE_PROFILE, "TmdStoreR3", STAMUNIT_TICKS_PER_CALL, "Profiling PCnet TmdStore in R3");
5415
5416	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatXmitSkipCurrent, STAMTYPE_COUNTER, "Xmit/Skipped", STAMUNIT_OCCURENCES, "");
5417
5418	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatInterrupt, STAMTYPE_PROFILE, "UpdateIRQ", STAMUNIT_TICKS_PER_CALL, "Profiling interrupt checks");
5419	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatPollTimer, STAMTYPE_PROFILE, "PollTimer", STAMUNIT_TICKS_PER_CALL, "Profiling poll timer");
5420	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMIIReads, STAMTYPE_COUNTER, "MIIReads", STAMUNIT_OCCURENCES, "Number of MII reads");
5421	# ifdef PCNET_NO_POLLING
5422	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatRCVRingWrite, STAMTYPE_COUNTER, "Ring/RCVWrites", STAMUNIT_OCCURENCES, "Nr of receive ring writes");
5423	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatTXRingWrite, STAMTYPE_COUNTER, "Ring/TXWrites", STAMUNIT_OCCURENCES, "Nr of transmit ring writes");
5424	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatRingWriteR3, STAMTYPE_COUNTER, "Ring/R3/Writes", STAMUNIT_OCCURENCES, "Nr of monitored ring page writes");
5425	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatRingWriteR0, STAMTYPE_COUNTER, "Ring/R0/Writes", STAMUNIT_OCCURENCES, "Nr of monitored ring page writes");
5426	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatRingWriteRC, STAMTYPE_COUNTER, "Ring/RC/Writes", STAMUNIT_OCCURENCES, "Nr of monitored ring page writes");
5427	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatRingWriteFailedR3, STAMTYPE_COUNTER, "Ring/R3/Failed", STAMUNIT_OCCURENCES, "Nr of failed ring page writes");
5428	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatRingWriteFailedR0, STAMTYPE_COUNTER, "Ring/R0/Failed", STAMUNIT_OCCURENCES, "Nr of failed ring page writes");
5429	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatRingWriteFailedRC, STAMTYPE_COUNTER, "Ring/RC/Failed", STAMUNIT_OCCURENCES, "Nr of failed ring page writes");
5430	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatRingWriteOutsideR3, STAMTYPE_COUNTER, "Ring/R3/Outside", STAMUNIT_OCCURENCES, "Nr of monitored writes outside ring");
5431	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatRingWriteOutsideR0, STAMTYPE_COUNTER, "Ring/R0/Outside", STAMUNIT_OCCURENCES, "Nr of monitored writes outside ring");
5432	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatRingWriteOutsideRC, STAMTYPE_COUNTER, "Ring/RC/Outside", STAMUNIT_OCCURENCES, "Nr of monitored writes outside ring");
5433	# endif /* PCNET_NO_POLLING */
5434	unsigned i;
5435	for (i = 0; i < RT_ELEMENTS(pThis->aStatXmitFlush) - 1; i++)
5436	PDMDevHlpSTAMRegisterF(pDevIns, &pThis->aStatXmitFlush[i], STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES,
5437	"", "XmitFlushIrq/%02u", i + 1);
5438	PDMDevHlpSTAMRegisterF(pDevIns, &pThis->aStatXmitFlush[i], STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES,
5439	"", "XmitFlushIrq/%02u-inf", i + 1);
5440
5441	for (i = 0; i < RT_ELEMENTS(pThis->aStatXmitChainCounts) - 1; i++)
5442	PDMDevHlpSTAMRegisterF(pDevIns, &pThis->aStatXmitChainCounts[i], STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES,
5443	"", "XmitChainCounts/%02u", i + 1);
5444	PDMDevHlpSTAMRegisterF(pDevIns, &pThis->aStatXmitChainCounts[i], STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES,
5445	"", "XmitChainCounts/%02u-inf", i + 1);
5446	#endif /* VBOX_WITH_STATISTICS */
5447
5448	return VINF_SUCCESS;
5449	}
5450
5451	#else /* !IN_RING3 */
5452
5453	/**
5454	* @callback_method_impl{PDMDEVREGR0,pfnConstruct}
5455	*/
5456	static DECLCALLBACK(int) pcnetRZConstruct(PPDMDEVINS pDevIns)
5457	{
5458	PDMDEV_CHECK_VERSIONS_RETURN(pDevIns);
5459	PPCNETSTATE pThis = PDMDEVINS_2_DATA(pDevIns, PPCNETSTATE);
5460
5461	/* Critical section setup: */
5462	int rc = PDMDevHlpSetDeviceCritSect(pDevIns, &pThis->CritSect);
5463	AssertRCReturn(rc, rc);
5464
5465	/* PCI I/O ports: */
5466	if (pThis->hIoPortsPciAProm != NIL_IOMIOPORTHANDLE)
5467	{
5468	rc = PDMDevHlpIoPortSetUpContext(pDevIns, pThis->hIoPortsPciAProm, pcnetIoPortAPromWrite, pcnetIOPortAPromRead, NULL /pvUser/);
5469	AssertRCReturn(rc, rc);
5470	rc = PDMDevHlpIoPortSetUpContext(pDevIns, pThis->hIoPortsPci, pcnetIoPortWrite, pcnetIoPortRead, NULL /pvUser/);
5471	AssertRCReturn(rc, rc);
5472	}
5473	else
5474	Assert(pThis->hIoPortsPci == NIL_IOMIOPORTHANDLE);
5475
5476	/** @todo PCI MMIO */
5477
5478	/* ISA I/O ports: */
5479	if (pThis->hIoPortsIsaAProm != NIL_IOMIOPORTHANDLE)
5480	{
5481	rc = PDMDevHlpIoPortSetUpContext(pDevIns, pThis->hIoPortsIsaAProm, pcnetIoPortAPromWrite, pcnetIOPortAPromRead, NULL /pvUser/);
5482	AssertRCReturn(rc, rc);
5483	rc = PDMDevHlpIoPortSetUpContext(pDevIns, pThis->hIoPortsIsa, pcnetIoPortWrite, pcnetIoPortRead, NULL /pvUser/);
5484	AssertRCReturn(rc, rc);
5485	}
5486	else
5487	Assert(pThis->hIoPortsIsa == NIL_IOMIOPORTHANDLE);
5488
5489	return VINF_SUCCESS;
5490	}
5491
5492	#endif /* !IN_RING3 */
5493
5494	/**
5495	* The device registration structure.
5496	*/
5497	const PDMDEVREG g_DevicePCNet =
5498	{
5499	/* .u32Version = */ PDM_DEVREG_VERSION,
5500	/* .uReserved0 = */ 0,
5501	/* .szName = */ "pcnet",
5502	#ifdef PCNET_GC_ENABLED
5503	/* .fFlags = */ PDM_DEVREG_FLAGS_DEFAULT_BITS \| PDM_DEVREG_FLAGS_RZ \| PDM_DEVREG_FLAGS_NEW_STYLE,
5504	#else
5505	/* .fFlags = */ PDM_DEVREG_FLAGS_DEFAULT_BITS,
5506	#endif
5507	/* .fClass = */ PDM_DEVREG_CLASS_NETWORK,
5508	/* .cMaxInstances = */ ~0U,
5509	/* .uSharedVersion = */ 42,
5510	/* .cbInstanceShared = */ sizeof(PCNETSTATE),
5511	/* .cbInstanceCC = */ sizeof(PCNETSTATECC),
5512	/* .cbInstanceRC = */ sizeof(PCNETSTATERC),
5513	/* .cMaxPciDevices = */ 1,
5514	/* .cMaxMsixVectors = */ 0,
5515	/* .pszDescription = */ "AMD PCnet Ethernet controller.\n",
5516	#if defined(IN_RING3)
5517	/* .pszRCMod = */ "VBoxDDRC.rc",
5518	/* .pszR0Mod = */ "VBoxDDR0.r0",
5519	/* .pfnConstruct = */ pcnetR3Construct,
5520	/* .pfnDestruct = */ pcnetR3Destruct,
5521	/* .pfnRelocate = */ pcnetR3Relocate,
5522	/* .pfnMemSetup = */ NULL,
5523	/* .pfnPowerOn = */ NULL,
5524	/* .pfnReset = */ pcnetR3Reset,
5525	/* .pfnSuspend = */ pcnetR3Suspend,
5526	/* .pfnResume = */ NULL,
5527	/* .pfnAttach = */ pcnetR3Attach,
5528	/* .pfnDetach = */ pcnetR3Detach,
5529	/* .pfnQueryInterface = */ NULL,
5530	/* .pfnInitComplete = */ NULL,
5531	/* .pfnPowerOff = */ pcnetR3PowerOff,
5532	/* .pfnSoftReset = */ NULL,
5533	/* .pfnReserved0 = */ NULL,
5534	/* .pfnReserved1 = */ NULL,
5535	/* .pfnReserved2 = */ NULL,
5536	/* .pfnReserved3 = */ NULL,
5537	/* .pfnReserved4 = */ NULL,
5538	/* .pfnReserved5 = */ NULL,
5539	/* .pfnReserved6 = */ NULL,
5540	/* .pfnReserved7 = */ NULL,
5541	#elif defined(IN_RING0)
5542	/* .pfnEarlyConstruct = */ NULL,
5543	/* .pfnConstruct = */ pcnetRZConstruct,
5544	/* .pfnDestruct = */ NULL,
5545	/* .pfnFinalDestruct = */ NULL,
5546	/* .pfnRequest = */ NULL,
5547	/* .pfnReserved0 = */ NULL,
5548	/* .pfnReserved1 = */ NULL,
5549	/* .pfnReserved2 = */ NULL,
5550	/* .pfnReserved3 = */ NULL,
5551	/* .pfnReserved4 = */ NULL,
5552	/* .pfnReserved5 = */ NULL,
5553	/* .pfnReserved6 = */ NULL,
5554	/* .pfnReserved7 = */ NULL,
5555	#elif defined(IN_RC)
5556	/* .pfnConstruct = */ pcnetRZConstruct,
5557	/* .pfnReserved0 = */ NULL,
5558	/* .pfnReserved1 = */ NULL,
5559	/* .pfnReserved2 = */ NULL,
5560	/* .pfnReserved3 = */ NULL,
5561	/* .pfnReserved4 = */ NULL,
5562	/* .pfnReserved5 = */ NULL,
5563	/* .pfnReserved6 = */ NULL,
5564	/* .pfnReserved7 = */ NULL,
5565	#else
5566	# error "Not in IN_RING3, IN_RING0 or IN_RC!"
5567	#endif
5568	/* .u32VersionEnd = */ PDM_DEVREG_VERSION
5569	};
5570
5571	#endif /* !VBOX_DEVICE_STRUCT_TESTCASE */
5572

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source: vbox/trunk/src/VBox/Devices/Network/DevPCNet.cpp@ 82254

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