DevPCNet.cpp@ 27856

Last change on this file since 27856 was 27844, checked in by vboxsync, 15 years ago
DevPCNet.cpp: Use the buffered network driver interface.
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1	/* $Id: DevPCNet.cpp 27844 2010-03-30 21:02:49Z vboxsync $ */
2	/** @file
3	* DevPCNet - AMD PCnet-PCI II / PCnet-FAST III (Am79C970A / Am79C973) Ethernet Controller Emulation.
4	*
5	* This software was written to be compatible with the specifications:
6	* AMD Am79C970A PCnet-PCI II Ethernet Controller Data-Sheet
7	* AMD Publication# 19436 Rev:E Amendment/0 Issue Date: June 2000
8	* and
9	* todo
10	*/
11
12	/*
13	* Copyright (C) 2006-2008 Sun Microsystems, Inc.
14	*
15	* This file is part of VirtualBox Open Source Edition (OSE), as
16	* available from http://www.virtualbox.org. This file is free software;
17	* you can redistribute it and/or modify it under the terms of the GNU
18	* General Public License (GPL) as published by the Free Software
19	* Foundation, in version 2 as it comes in the "COPYING" file of the
20	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
21	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
22	*
23	* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
24	* Clara, CA 95054 USA or visit http://www.sun.com if you need
25	* additional information or have any questions.
26	* --------------------------------------------------------------------
27	*
28	* This code is based on:
29	*
30	* AMD PC-Net II (Am79C970A) emulation
31	*
32	* Copyright (c) 2004 Antony T Curtis
33	*
34	* Permission is hereby granted, free of charge, to any person obtaining a copy
35	* of this software and associated documentation files (the "Software"), to deal
36	* in the Software without restriction, including without limitation the rights
37	* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
38	* copies of the Software, and to permit persons to whom the Software is
39	* furnished to do so, subject to the following conditions:
40	*
41	* The above copyright notice and this permission notice shall be included in
42	* all copies or substantial portions of the Software.
43	*
44	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
45	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
46	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
47	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
48	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
49	* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
50	* THE SOFTWARE.
51	*/
52	#define VBOX_WITH_TX_THREAD_IN_NET_DEVICES 1 //debug, bird, remove
53
54	/*******************************************************************************
55	* Header Files *
56	*******************************************************************************/
57	#define LOG_GROUP LOG_GROUP_DEV_PCNET
58	#include <VBox/pdmdev.h>
59	#include <VBox/pdmnetifs.h>
60	#include <VBox/pgm.h>
61	#include <VBox/DevPCNet.h>
62	#include <iprt/asm.h>
63	#include <iprt/assert.h>
64	#include <iprt/critsect.h>
65	#include <iprt/net.h>
66	#include <iprt/string.h>
67	#include <iprt/time.h>
68	#ifdef IN_RING3
69	# include <iprt/mem.h>
70	# include <iprt/semaphore.h>
71	# include <iprt/uuid.h>
72	#endif
73
74	#include "../Builtins.h"
75
76	/* Enable this to catch writes to the ring descriptors instead of using excessive polling */
77	/* #define PCNET_NO_POLLING */
78
79	/* Enable to handle frequent io reads in the guest context (recommended) */
80	#define PCNET_GC_ENABLED
81
82	#if defined(LOG_ENABLED)
83	#define PCNET_DEBUG_IO
84	#define PCNET_DEBUG_BCR
85	#define PCNET_DEBUG_CSR
86	#define PCNET_DEBUG_RMD
87	#define PCNET_DEBUG_TMD
88	#define PCNET_DEBUG_MATCH
89	#define PCNET_DEBUG_MII
90	#endif
91
92	#define PCNET_IOPORT_SIZE 0x20
93	#define PCNET_PNPMMIO_SIZE 0x20
94
95	#define PCNET_SAVEDSTATE_VERSION 10
96
97	#define BCR_MAX_RAP 50
98	#define MII_MAX_REG 32
99	#define CSR_MAX_REG 128
100
101	/* Maximum number of times we report a link down to the guest (failure to send frame) */
102	#define PCNET_MAX_LINKDOWN_REPORTED 3
103
104	/* Maximum frame size we handle */
105	#define MAX_FRAME 1536
106
107
108	typedef struct PCNetState_st PCNetState;
109
110	/**
111	* PCNET state.
112	*
113	* @extends PCIDEVICE
114	* @implements PDMIBASE
115	* @implements PDMINETWORKDOWN
116	* @implements PDMINETWORKCONFIG
117	* @implements PDMILEDPORTS
118	*/
119	struct PCNetState_st
120	{
121	PCIDEVICE PciDev;
122	#ifndef PCNET_NO_POLLING
123	/** Poll timer - R3. */
124	PTMTIMERR3 pTimerPollR3;
125	/** Poll timer - R0. */
126	PTMTIMERR0 pTimerPollR0;
127	/** Poll timer - RC. */
128	PTMTIMERRC pTimerPollRC;
129	#endif
130
131	#if HC_ARCH_BITS == 64
132	uint32_t Alignment1;
133	#endif
134
135	/** Software Interrupt timer - R3. */
136	PTMTIMERR3 pTimerSoftIntR3;
137	/** Software Interrupt timer - R0. */
138	PTMTIMERR0 pTimerSoftIntR0;
139	/** Software Interrupt timer - RC. */
140	PTMTIMERRC pTimerSoftIntRC;
141
142	/** Register Address Pointer */
143	uint32_t u32RAP;
144	/** Internal interrupt service */
145	int32_t iISR;
146	/** ??? */
147	uint32_t u32Lnkst;
148	/** Address of the RX descriptor table (ring). Loaded at init. */
149	RTGCPHYS32 GCRDRA;
150	/** Address of the TX descriptor table (ring). Loaded at init. */
151	RTGCPHYS32 GCTDRA;
152	uint8_t aPROM[16];
153	uint16_t aCSR[CSR_MAX_REG];
154	uint16_t aBCR[BCR_MAX_RAP];
155	uint16_t aMII[MII_MAX_REG];
156	uint16_t u16CSR0LastSeenByGuest;
157	uint16_t Alignment2[HC_ARCH_BITS == 32 ? 2 : 4];
158	/** Last time we polled the queues */
159	uint64_t u64LastPoll;
160
161	/** The loopback transmit buffer (avoid stack allocations). */
162	uint8_t abLoopBuf[4096];
163	/** The recv buffer. */
164	uint8_t abRecvBuf[4096];
165
166	/** Unused / padding. */
167	uint32_t u32Unused;
168
169	/** Size of a RX/TX descriptor (8 or 16 bytes according to SWSTYLE */
170	int iLog2DescSize;
171	/** Bits 16..23 in 16-bit mode */
172	RTGCPHYS32 GCUpperPhys;
173
174	/** Transmit signaller - RC. */
175	RCPTRTYPE(PPDMQUEUE) pXmitQueueRC;
176	/** Transmit signaller - R3. */
177	R3PTRTYPE(PPDMQUEUE) pXmitQueueR3;
178	/** Transmit signaller - R0. */
179	R0PTRTYPE(PPDMQUEUE) pXmitQueueR0;
180
181	/** Receive signaller - R3. */
182	R3PTRTYPE(PPDMQUEUE) pCanRxQueueR3;
183	/** Receive signaller - R0. */
184	R0PTRTYPE(PPDMQUEUE) pCanRxQueueR0;
185	/** Receive signaller - RC. */
186	RCPTRTYPE(PPDMQUEUE) pCanRxQueueRC;
187	/** Pointer to the device instance - RC. */
188	PPDMDEVINSRC pDevInsRC;
189	/** Pointer to the device instance - R3. */
190	PPDMDEVINSR3 pDevInsR3;
191	/** Pointer to the device instance - R0. */
192	PPDMDEVINSR0 pDevInsR0;
193	/** Restore timer.
194	* This is used to disconnect and reconnect the link after a restore. */
195	PTMTIMERR3 pTimerRestore;
196	/** Pointer to the connector of the attached network driver. */
197	R3PTRTYPE(PPDMINETWORKUP) pDrvR3;
198	/** Pointer to the attached network driver. */
199	R3PTRTYPE(PPDMIBASE) pDrvBase;
200	/** LUN\#0 + status LUN: The base interface. */
201	PDMIBASE IBase;
202	/** LUN\#0: The network port interface. */
203	PDMINETWORKDOWN INetworkDown;
204	/** LUN\#0: The network config port interface. */
205	PDMINETWORKCONFIG INetworkConfig;
206	/** Base address of the MMIO region. */
207	RTGCPHYS32 MMIOBase;
208	/** Base port of the I/O space region. */
209	RTIOPORT IOPortBase;
210	/** If set the link is currently up. */
211	bool fLinkUp;
212	/** If set the link is temporarily down because of a saved state load. */
213	bool fLinkTempDown;
214
215	/** Number of times we've reported the link down. */
216	RTUINT cLinkDownReported;
217	/** The configured MAC address. */
218	RTMAC MacConfigured;
219	/** Alignment padding. */
220	uint8_t Alignment4[HC_ARCH_BITS == 64 ? 6 : 6];
221
222	/** The LED. */
223	PDMLED Led;
224	/** Status LUN: The LED ports. */
225	PDMILEDPORTS ILeds;
226	/** Partner of ILeds. */
227	R3PTRTYPE(PPDMILEDCONNECTORS) pLedsConnector;
228
229	#ifdef VBOX_WITH_TX_THREAD_IN_NET_DEVICES
230	/** Async send thread */
231	RTSEMEVENT hSendEventSem;
232	/** The Async send thread. */
233	PPDMTHREAD pSendThread;
234	#endif
235
236	/** Access critical section. */
237	PDMCRITSECT CritSect;
238	/** Event semaphore for blocking on receive. */
239	RTSEMEVENT hEventOutOfRxSpace;
240	/** We are waiting/about to start waiting for more receive buffers. */
241	bool volatile fMaybeOutOfSpace;
242	/** True if we signal the guest that RX packets are missing. */
243	bool fSignalRxMiss;
244	uint8_t Alignment5[HC_ARCH_BITS == 64 ? 6 : 2];
245
246	#ifdef PCNET_NO_POLLING
247	RTGCPHYS32 TDRAPhysOld;
248	uint32_t cbTDRAOld;
249
250	RTGCPHYS32 RDRAPhysOld;
251	uint32_t cbRDRAOld;
252
253	DECLRCCALLBACKMEMBER(int, pfnEMInterpretInstructionRC, (PVM pVM, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize));
254	DECLR0CALLBACKMEMBER(int, pfnEMInterpretInstructionR0, (PVM pVM, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize));
255	#endif
256
257	/** The shared memory used for the private interface - R3. */
258	R3PTRTYPE(PPCNETGUESTSHAREDMEMORY) pSharedMMIOR3;
259	/** The shared memory used for the private interface - R0. */
260	R0PTRTYPE(PPCNETGUESTSHAREDMEMORY) pSharedMMIOR0;
261	/** The shared memory used for the private interface - RC. */
262	RCPTRTYPE(PPCNETGUESTSHAREDMEMORY) pSharedMMIORC;
263
264	/** Error counter for bad receive descriptors. */
265	uint32_t uCntBadRMD;
266
267	/** True if host and guest admitted to use the private interface. */
268	bool fPrivIfEnabled;
269	bool fGCEnabled;
270	bool fR0Enabled;
271	bool fAm79C973;
272	uint32_t u32LinkSpeed;
273
274	STAMCOUNTER StatReceiveBytes;
275	STAMCOUNTER StatTransmitBytes;
276	#ifdef VBOX_WITH_STATISTICS
277	STAMPROFILEADV StatMMIOReadGC;
278	STAMPROFILEADV StatMMIOReadHC;
279	STAMPROFILEADV StatMMIOWriteGC;
280	STAMPROFILEADV StatMMIOWriteHC;
281	STAMPROFILEADV StatAPROMRead;
282	STAMPROFILEADV StatAPROMWrite;
283	STAMPROFILEADV StatIOReadGC;
284	STAMPROFILEADV StatIOReadHC;
285	STAMPROFILEADV StatIOWriteGC;
286	STAMPROFILEADV StatIOWriteHC;
287	STAMPROFILEADV StatTimer;
288	STAMPROFILEADV StatReceive;
289	STAMPROFILEADV StatTransmit;
290	STAMCOUNTER StatTransmitCase1;
291	STAMCOUNTER StatTransmitCase2;
292	STAMPROFILE StatTransmitSend;
293	STAMPROFILEADV StatTdtePollGC;
294	STAMPROFILEADV StatTdtePollHC;
295	STAMPROFILEADV StatTmdStoreGC;
296	STAMPROFILEADV StatTmdStoreHC;
297	STAMPROFILEADV StatRdtePollGC;
298	STAMPROFILEADV StatRdtePollHC;
299	STAMPROFILE StatRxOverflow;
300	STAMCOUNTER StatRxOverflowWakeup;
301	STAMCOUNTER aStatXmitFlush[16];
302	STAMCOUNTER aStatXmitChainCounts[16];
303	STAMCOUNTER StatXmitSkipCurrent;
304	STAMPROFILEADV StatInterrupt;
305	STAMPROFILEADV StatPollTimer;
306	STAMCOUNTER StatMIIReads;
307	# ifdef PCNET_NO_POLLING
308	STAMCOUNTER StatRCVRingWrite;
309	STAMCOUNTER StatTXRingWrite;
310	STAMCOUNTER StatRingWriteHC;
311	STAMCOUNTER StatRingWriteR0;
312	STAMCOUNTER StatRingWriteGC;
313
314	STAMCOUNTER StatRingWriteFailedHC;
315	STAMCOUNTER StatRingWriteFailedR0;
316	STAMCOUNTER StatRingWriteFailedGC;
317
318	STAMCOUNTER StatRingWriteOutsideHC;
319	STAMCOUNTER StatRingWriteOutsideR0;
320	STAMCOUNTER StatRingWriteOutsideGC;
321	# endif
322	#endif /* VBOX_WITH_STATISTICS */
323	};
324	AssertCompileMemberAlignment(PCNetState, StatReceiveBytes, 8);
325
326	#define PCNETSTATE_2_DEVINS(pPCNet) ((pPCNet)->CTX_SUFF(pDevIns))
327	#define PCIDEV_2_PCNETSTATE(pPciDev) ((PCNetState *)(pPciDev))
328	#define PCNET_INST_NR (PCNETSTATE_2_DEVINS(pThis)->iInstance)
329
330	/* BUS CONFIGURATION REGISTERS */
331	#define BCR_MSRDA 0
332	#define BCR_MSWRA 1
333	#define BCR_MC 2
334	#define BCR_RESERVED3 3
335	#define BCR_LNKST 4
336	#define BCR_LED1 5
337	#define BCR_LED2 6
338	#define BCR_LED3 7
339	#define BCR_RESERVED8 8
340	#define BCR_FDC 9
341	/* 10 - 15 = reserved */
342	#define BCR_IOBASEL 16 /* Reserved */
343	#define BCR_IOBASEU 16 /* Reserved */
344	#define BCR_BSBC 18
345	#define BCR_EECAS 19
346	#define BCR_SWS 20
347	#define BCR_INTCON 21 /* Reserved */
348	#define BCR_PLAT 22
349	#define BCR_PCISVID 23
350	#define BCR_PCISID 24
351	#define BCR_SRAMSIZ 25
352	#define BCR_SRAMB 26
353	#define BCR_SRAMIC 27
354	#define BCR_EBADDRL 28
355	#define BCR_EBADDRU 29
356	#define BCR_EBD 30
357	#define BCR_STVAL 31
358	#define BCR_MIICAS 32
359	#define BCR_MIIADDR 33
360	#define BCR_MIIMDR 34
361	#define BCR_PCIVID 35
362	#define BCR_PMC_A 36
363	#define BCR_DATA0 37
364	#define BCR_DATA1 38
365	#define BCR_DATA2 39
366	#define BCR_DATA3 40
367	#define BCR_DATA4 41
368	#define BCR_DATA5 42
369	#define BCR_DATA6 43
370	#define BCR_DATA7 44
371	#define BCR_PMR1 45
372	#define BCR_PMR2 46
373	#define BCR_PMR3 47
374
375	#define BCR_DWIO(S) !!((S)->aBCR[BCR_BSBC] & 0x0080)
376	#define BCR_SSIZE32(S) !!((S)->aBCR[BCR_SWS ] & 0x0100)
377	#define BCR_SWSTYLE(S) ((S)->aBCR[BCR_SWS ] & 0x00FF)
378
379	#define CSR_INIT(S) !!((S)->aCSR[0] & 0x0001) /*< Init assertion /
380	#define CSR_STRT(S) !!((S)->aCSR[0] & 0x0002) /*< Start assertion /
381	#define CSR_STOP(S) !!((S)->aCSR[0] & 0x0004) /*< Stop assertion /
382	#define CSR_TDMD(S) !!((S)->aCSR[0] & 0x0008) /*< Transmit demand. (perform xmit poll now (readable, settable, not clearable) /
383	#define CSR_TXON(S) !!((S)->aCSR[0] & 0x0010) /*< Transmit on (readonly) /
384	#define CSR_RXON(S) !!((S)->aCSR[0] & 0x0020) /*< Receive On /
385	#define CSR_INEA(S) !!((S)->aCSR[0] & 0x0040) /*< Interrupt Enable /
386	#define CSR_LAPPEN(S) !!((S)->aCSR[3] & 0x0020) /*< Look Ahead Packet Processing Enable /
387	#define CSR_DXSUFLO(S) !!((S)->aCSR[3] & 0x0040) /*< Disable Transmit Stop on Underflow error /
388	#define CSR_ASTRP_RCV(S) !!((S)->aCSR[4] & 0x0400) /*< Auto Strip Receive /
389	#define CSR_DPOLL(S) !!((S)->aCSR[4] & 0x1000) /*< Disable Transmit Polling /
390	#define CSR_SPND(S) !!((S)->aCSR[5] & 0x0001) /*< Suspend /
391	#define CSR_LTINTEN(S) !!((S)->aCSR[5] & 0x4000) /*< Last Transmit Interrupt Enable /
392	#define CSR_TOKINTD(S) !!((S)->aCSR[5] & 0x8000) /*< Transmit OK Interrupt Disable /
393
394	#define CSR_STINT !!((S)->aCSR[7] & 0x0800) /*< Software Timer Interrupt /
395	#define CSR_STINTE !!((S)->aCSR[7] & 0x0400) /*< Software Timer Interrupt Enable /
396
397	#define CSR_DRX(S) !!((S)->aCSR[15] & 0x0001) /*< Disable Receiver /
398	#define CSR_DTX(S) !!((S)->aCSR[15] & 0x0002) /*< Disable Transmit /
399	#define CSR_LOOP(S) !!((S)->aCSR[15] & 0x0004) /*< Loopback Enable /
400	#define CSR_DRCVPA(S) !!((S)->aCSR[15] & 0x2000) /*< Disable Receive Physical Address /
401	#define CSR_DRCVBC(S) !!((S)->aCSR[15] & 0x4000) /*< Disable Receive Broadcast /
402	#define CSR_PROM(S) !!((S)->aCSR[15] & 0x8000) /*< Promiscuous Mode /
403
404	#if !defined(RT_ARCH_X86) && !defined(RT_ARCH_AMD64)
405	#error fix macros (and more in this file) for big-endian machines
406	#endif
407
408	#define CSR_IADR(S) ((uint32_t)((S)->aCSR + 1)) /*< Initialization Block Address /
409	#define CSR_CRBA(S) ((uint32_t)((S)->aCSR + 18)) /*< Current Receive Buffer Address /
410	#define CSR_CXBA(S) ((uint32_t)((S)->aCSR + 20)) /*< Current Transmit Buffer Address /
411	#define CSR_NRBA(S) ((uint32_t)((S)->aCSR + 22)) /*< Next Receive Buffer Address /
412	#define CSR_BADR(S) ((uint32_t)((S)->aCSR + 24)) /*< Base Address of Receive Ring /
413	#define CSR_NRDA(S) ((uint32_t)((S)->aCSR + 26)) /*< Next Receive Descriptor Address /
414	#define CSR_CRDA(S) ((uint32_t)((S)->aCSR + 28)) /*< Current Receive Descriptor Address /
415	#define CSR_BADX(S) ((uint32_t)((S)->aCSR + 30)) /*< Base Address of Transmit Descriptor /
416	#define CSR_NXDA(S) ((uint32_t)((S)->aCSR + 32)) /*< Next Transmit Descriptor Address /
417	#define CSR_CXDA(S) ((uint32_t)((S)->aCSR + 34)) /*< Current Transmit Descriptor Address /
418	#define CSR_NNRD(S) ((uint32_t)((S)->aCSR + 36)) /*< Next Next Receive Descriptor Address /
419	#define CSR_NNXD(S) ((uint32_t)((S)->aCSR + 38)) /*< Next Next Transmit Descriptor Address /
420	#define CSR_CRBC(S) ((S)->aCSR[40]) /*< Current Receive Byte Count /
421	#define CSR_CRST(S) ((S)->aCSR[41]) /*< Current Receive Status /
422	#define CSR_CXBC(S) ((S)->aCSR[42]) /*< Current Transmit Byte Count /
423	#define CSR_CXST(S) ((S)->aCSR[43]) /*< Current transmit status /
424	#define CSR_NRBC(S) ((S)->aCSR[44]) /*< Next Receive Byte Count /
425	#define CSR_NRST(S) ((S)->aCSR[45]) /*< Next Receive Status /
426	#define CSR_POLL(S) ((S)->aCSR[46]) /*< Transmit Poll Time Counter /
427	#define CSR_PINT(S) ((S)->aCSR[47]) /*< Transmit Polling Interval /
428	#define CSR_PXDA(S) ((uint32_t)((S)->aCSR + 60)) /*< Previous Transmit Descriptor Address/
429	#define CSR_PXBC(S) ((S)->aCSR[62]) /*< Previous Transmit Byte Count /
430	#define CSR_PXST(S) ((S)->aCSR[63]) /*< Previous Transmit Status /
431	#define CSR_NXBA(S) ((uint32_t)((S)->aCSR + 64)) /*< Next Transmit Buffer Address /
432	#define CSR_NXBC(S) ((S)->aCSR[66]) /*< Next Transmit Byte Count /
433	#define CSR_NXST(S) ((S)->aCSR[67]) /*< Next Transmit Status /
434	#define CSR_RCVRC(S) ((S)->aCSR[72]) /*< Receive Descriptor Ring Counter /
435	#define CSR_XMTRC(S) ((S)->aCSR[74]) /*< Transmit Descriptor Ring Counter /
436	#define CSR_RCVRL(S) ((S)->aCSR[76]) /*< Receive Descriptor Ring Length /
437	#define CSR_XMTRL(S) ((S)->aCSR[78]) /*< Transmit Descriptor Ring Length /
438	#define CSR_MISSC(S) ((S)->aCSR[112]) /*< Missed Frame Count /
439
440	#define PHYSADDR(S,A) ((A) \| (S)->GCUpperPhys)
441
442	/* Version for the PCnet/FAST III 79C973 card */
443	#define CSR_VERSION_LOW_79C973 0x5003 /* the lower two bits must be 11b for AMD */
444	#define CSR_VERSION_LOW_79C970A 0x1003 /* the lower two bits must be 11b for AMD */
445	#define CSR_VERSION_HIGH 0x0262
446
447	/** @todo All structs: big endian? */
448
449	struct INITBLK16
450	{
451	uint16_t mode; /*< copied into csr15 /
452	uint16_t padr1; /*< MAC 0..15 /
453	uint16_t padr2; /*< MAC 16..32 /
454	uint16_t padr3; /*< MAC 33..47 /
455	uint16_t ladrf1; /*< logical address filter 0..15 /
456	uint16_t ladrf2; /*< logical address filter 16..31 /
457	uint16_t ladrf3; /*< logical address filter 32..47 /
458	uint16_t ladrf4; /*< logical address filter 48..63 /
459	uint32_t rdra:24; /*< address of receive descriptor ring /
460	uint32_t res1:5; /*< reserved /
461	uint32_t rlen:3; /*< number of receive descriptor ring entries /
462	uint32_t tdra:24; /*< address of transmit descriptor ring /
463	uint32_t res2:5; /*< reserved /
464	uint32_t tlen:3; /*< number of transmit descriptor ring entries /
465	};
466	AssertCompileSize(INITBLK16, 24);
467
468	/** bird: I've changed the type for the bitfields. They should only be 16-bit all together.
469	* frank: I've changed the bitfiled types to uint32_t to prevent compiler warnings. */
470	struct INITBLK32
471	{
472	uint16_t mode; /*< copied into csr15 /
473	uint16_t res1:4; /*< reserved /
474	uint16_t rlen:4; /*< number of receive descriptor ring entries /
475	uint16_t res2:4; /*< reserved /
476	uint16_t tlen:4; /*< number of transmit descriptor ring entries /
477	uint16_t padr1; /*< MAC 0..15 /
478	uint16_t padr2; /*< MAC 16..31 /
479	uint16_t padr3; /*< MAC 32..47 /
480	uint16_t res3; /*< reserved /
481	uint16_t ladrf1; /*< logical address filter 0..15 /
482	uint16_t ladrf2; /*< logical address filter 16..31 /
483	uint16_t ladrf3; /*< logibal address filter 32..47 /
484	uint16_t ladrf4; /*< logical address filter 48..63 /
485	uint32_t rdra; /*< address of receive descriptor ring /
486	uint32_t tdra; /*< address of transmit descriptor ring /
487	};
488	AssertCompileSize(INITBLK32, 28);
489
490	/** Transmit Message Descriptor */
491	typedef struct TMD
492	{
493	struct
494	{
495	uint32_t tbadr; /*< transmit buffer address /
496	} tmd0;
497	struct
498	{
499	uint32_t bcnt:12; /*< buffer byte count (two's complement) /
500	uint32_t ones:4; /*< must be 1111b /
501	uint32_t res:7; /*< reserved /
502	uint32_t bpe:1; /*< bus parity error /
503	uint32_t enp:1; /*< end of packet /
504	uint32_t stp:1; /*< start of packet /
505	uint32_t def:1; /*< deferred /
506	uint32_t one:1; /*< exactly one retry was needed to transmit a frame /
507	uint32_t ltint:1; /*< suppress interrupts after successful transmission /
508	uint32_t nofcs:1; /**< when set, the state of DXMTFCS is ignored and
509	transmitter FCS generation is activated. */
510	uint32_t err:1; /*< error occurred /
511	uint32_t own:1; /*< 0=owned by guest driver, 1=owned by controller /
512	} tmd1;
513	struct
514	{
515	uint32_t trc:4; /*< transmit retry count /
516	uint32_t res:12; /*< reserved /
517	uint32_t tdr:10; /*< ??? /
518	uint32_t rtry:1; /*< retry error /
519	uint32_t lcar:1; /*< loss of carrier /
520	uint32_t lcol:1; /*< late collision /
521	uint32_t exdef:1; /*< excessive deferral /
522	uint32_t uflo:1; /*< underflow error /
523	uint32_t buff:1; /*< out of buffers (ENP not found) /
524	} tmd2;
525	struct
526	{
527	uint32_t res; /*< reserved for user defined space /
528	} tmd3;
529	} TMD;
530	AssertCompileSize(TMD, 16);
531
532	/** Receive Message Descriptor */
533	typedef struct RMD
534	{
535	struct
536	{
537	uint32_t rbadr; /*< receive buffer address /
538	} rmd0;
539	struct
540	{
541	uint32_t bcnt:12; /*< buffer byte count (two's complement) /
542	uint32_t ones:4; /*< must be 1111b /
543	uint32_t res:4; /*< reserved /
544	uint32_t bam:1; /*< broadcast address match /
545	uint32_t lafm:1; /*< logical filter address match /
546	uint32_t pam:1; /*< physcial address match /
547	uint32_t bpe:1; /*< bus parity error /
548	uint32_t enp:1; /*< end of packet /
549	uint32_t stp:1; /*< start of packet /
550	uint32_t buff:1; /*< buffer error /
551	uint32_t crc:1; /*< crc error on incoming frame /
552	uint32_t oflo:1; /*< overflow error (lost all or part of incoming frame) /
553	uint32_t fram:1; /*< frame error /
554	uint32_t err:1; /*< error occurred /
555	uint32_t own:1; /*< 0=owned by guest driver, 1=owned by controller /
556	} rmd1;
557	struct
558	{
559	uint32_t mcnt:12; /*< message byte count /
560	uint32_t zeros:4; /*< 0000b /
561	uint32_t rpc:8; /*< receive frame tag /
562	uint32_t rcc:8; /*< receive frame tag + reserved /
563	} rmd2;
564	struct
565	{
566	uint32_t res; /*< reserved for user defined space /
567	} rmd3;
568	} RMD;
569	AssertCompileSize(RMD, 16);
570
571
572	#ifndef VBOX_DEVICE_STRUCT_TESTCASE
573	/*******************************************************************************
574	* Internal Functions *
575	*******************************************************************************/
576	#define PRINT_TMD(T) Log2(( \
577	"TMD0 : TBADR=%#010x\n" \
578	"TMD1 : OWN=%d, ERR=%d, FCS=%d, LTI=%d, " \
579	"ONE=%d, DEF=%d, STP=%d, ENP=%d,\n" \
580	" BPE=%d, BCNT=%d\n" \
581	"TMD2 : BUF=%d, UFL=%d, EXD=%d, LCO=%d, " \
582	"LCA=%d, RTR=%d,\n" \
583	" TDR=%d, TRC=%d\n", \
584	(T)->tmd0.tbadr, \
585	(T)->tmd1.own, (T)->tmd1.err, (T)->tmd1.nofcs, \
586	(T)->tmd1.ltint, (T)->tmd1.one, (T)->tmd1.def, \
587	(T)->tmd1.stp, (T)->tmd1.enp, (T)->tmd1.bpe, \
588	4096-(T)->tmd1.bcnt, \
589	(T)->tmd2.buff, (T)->tmd2.uflo, (T)->tmd2.exdef,\
590	(T)->tmd2.lcol, (T)->tmd2.lcar, (T)->tmd2.rtry, \
591	(T)->tmd2.tdr, (T)->tmd2.trc))
592
593	#define PRINT_RMD(R) Log2(( \
594	"RMD0 : RBADR=%#010x\n" \
595	"RMD1 : OWN=%d, ERR=%d, FRAM=%d, OFLO=%d, " \
596	"CRC=%d, BUFF=%d, STP=%d, ENP=%d,\n " \
597	"BPE=%d, PAM=%d, LAFM=%d, BAM=%d, ONES=%d, BCNT=%d\n" \
598	"RMD2 : RCC=%d, RPC=%d, MCNT=%d, ZEROS=%d\n", \
599	(R)->rmd0.rbadr, \
600	(R)->rmd1.own, (R)->rmd1.err, (R)->rmd1.fram, \
601	(R)->rmd1.oflo, (R)->rmd1.crc, (R)->rmd1.buff, \
602	(R)->rmd1.stp, (R)->rmd1.enp, (R)->rmd1.bpe, \
603	(R)->rmd1.pam, (R)->rmd1.lafm, (R)->rmd1.bam, \
604	(R)->rmd1.ones, 4096-(R)->rmd1.bcnt, \
605	(R)->rmd2.rcc, (R)->rmd2.rpc, (R)->rmd2.mcnt, \
606	(R)->rmd2.zeros))
607
608	static void pcnetPollTimerStart(PCNetState *pThis);
609
610	/**
611	* Checks if the link is up.
612	* @returns true if the link is up.
613	* @returns false if the link is down.
614	*/
615	DECLINLINE(bool) pcnetIsLinkUp(PCNetState *pThis)
616	{
617	return pThis->pDrvR3 && !pThis->fLinkTempDown && pThis->fLinkUp;
618	}
619
620	/**
621	* Load transmit message descriptor
622	* Make sure we read the own flag first.
623	*
624	* @param pThis adapter private data
625	* @param addr physical address of the descriptor
626	* @param fRetIfNotOwn return immediately after reading the own flag if we don't own the descriptor
627	* @return true if we own the descriptor, false otherwise
628	*/
629	DECLINLINE(bool) pcnetTmdLoad(PCNetState pThis, TMD tmd, RTGCPHYS32 addr, bool fRetIfNotOwn)
630	{
631	PPDMDEVINS pDevIns = PCNETSTATE_2_DEVINS(pThis);
632	uint8_t ownbyte;
633
634	if (pThis->fPrivIfEnabled)
635	{
636	/* RX/TX descriptors shared between host and guest => direct copy */
637	uint8_t pv = (uint8_t)pThis->CTX_SUFF(pSharedMMIO)
638	+ (addr - pThis->GCTDRA)
639	+ pThis->CTX_SUFF(pSharedMMIO)->V.V1.offTxDescriptors;
640	if (!(pv[7] & 0x80) && fRetIfNotOwn)
641	return false;
642	memcpy(tmd, pv, 16);
643	return true;
644	}
645	else if (RT_UNLIKELY(BCR_SWSTYLE(pThis) == 0))
646	{
647	uint16_t xda[4];
648
649	PDMDevHlpPhysRead(pDevIns, addr+3, &ownbyte, 1);
650	if (!(ownbyte & 0x80) && fRetIfNotOwn)
651	return false;
652	PDMDevHlpPhysRead(pDevIns, addr, (void*)&xda[0], sizeof(xda));
653	((uint32_t *)tmd)[0] = (uint32_t)xda[0] \| ((uint32_t)(xda[1] & 0x00ff) << 16);
654	((uint32_t *)tmd)[1] = (uint32_t)xda[2] \| ((uint32_t)(xda[1] & 0xff00) << 16);
655	((uint32_t *)tmd)[2] = (uint32_t)xda[3] << 16;
656	((uint32_t *)tmd)[3] = 0;
657	}
658	else if (RT_LIKELY(BCR_SWSTYLE(pThis) != 3))
659	{
660	PDMDevHlpPhysRead(pDevIns, addr+7, &ownbyte, 1);
661	if (!(ownbyte & 0x80) && fRetIfNotOwn)
662	return false;
663	PDMDevHlpPhysRead(pDevIns, addr, (void*)tmd, 16);
664	}
665	else
666	{
667	uint32_t xda[4];
668	PDMDevHlpPhysRead(pDevIns, addr+7, &ownbyte, 1);
669	if (!(ownbyte & 0x80) && fRetIfNotOwn)
670	return false;
671	PDMDevHlpPhysRead(pDevIns, addr, (void*)&xda[0], sizeof(xda));
672	((uint32_t *)tmd)[0] = xda[2];
673	((uint32_t *)tmd)[1] = xda[1];
674	((uint32_t *)tmd)[2] = xda[0];
675	((uint32_t *)tmd)[3] = xda[3];
676	}
677	/* Double check the own bit; guest drivers might be buggy and lock prefixes in the recompiler are ignored by other threads. */
678	#ifdef DEBUG
679	if (tmd->tmd1.own == 1 && !(ownbyte & 0x80))
680	Log(("pcnetTmdLoad: own bit flipped while reading!!\n"));
681	#endif
682	if (!(ownbyte & 0x80))
683	tmd->tmd1.own = 0;
684
685	return !!tmd->tmd1.own;
686	}
687
688	/**
689	* Store transmit message descriptor and hand it over to the host (the VM guest).
690	* Make sure that all data are transmitted before we clear the own flag.
691	*/
692	DECLINLINE(void) pcnetTmdStorePassHost(PCNetState pThis, TMD tmd, RTGCPHYS32 addr)
693	{
694	STAM_PROFILE_ADV_START(&pThis->CTXSUFF(StatTmdStore), a);
695	PPDMDEVINS pDevIns = PCNETSTATE_2_DEVINS(pThis);
696	if (pThis->fPrivIfEnabled)
697	{
698	/* RX/TX descriptors shared between host and guest => direct copy */
699	uint8_t pv = (uint8_t)pThis->CTX_SUFF(pSharedMMIO)
700	+ (addr - pThis->GCTDRA)
701	+ pThis->CTX_SUFF(pSharedMMIO)->V.V1.offTxDescriptors;
702	memcpy(pv, tmd, 16);
703	pv[7] &= ~0x80;
704	}
705	else if (RT_UNLIKELY(BCR_SWSTYLE(pThis) == 0))
706	{
707	uint16_t xda[4];
708	xda[0] = ((uint32_t *)tmd)[0] & 0xffff;
709	xda[1] = ((((uint32_t )tmd)[0] >> 16) & 0xff) \| ((((uint32_t )tmd)[1]>>16) & 0xff00);
710	xda[2] = ((uint32_t *)tmd)[1] & 0xffff;
711	xda[3] = ((uint32_t *)tmd)[2] >> 16;
712	xda[1] \|= 0x8000;
713	PDMDevHlpPhysWrite(pDevIns, addr, (void*)&xda[0], sizeof(xda));
714	xda[1] &= ~0x8000;
715	PDMDevHlpPhysWrite(pDevIns, addr+3, (uint8_t*)xda + 3, 1);
716	}
717	else if (RT_LIKELY(BCR_SWSTYLE(pThis) != 3))
718	{
719	((uint32_t*)tmd)[1] \|= 0x80000000;
720	PDMDevHlpPhysWrite(pDevIns, addr, (void*)tmd, 16);
721	((uint32_t*)tmd)[1] &= ~0x80000000;
722	PDMDevHlpPhysWrite(pDevIns, addr+7, (uint8_t*)tmd + 7, 1);
723	}
724	else
725	{
726	uint32_t xda[4];
727	xda[0] = ((uint32_t *)tmd)[2];
728	xda[1] = ((uint32_t *)tmd)[1];
729	xda[2] = ((uint32_t *)tmd)[0];
730	xda[3] = ((uint32_t *)tmd)[3];
731	xda[1] \|= 0x80000000;
732	PDMDevHlpPhysWrite(pDevIns, addr, (void*)&xda[0], sizeof(xda));
733	xda[1] &= ~0x80000000;
734	PDMDevHlpPhysWrite(pDevIns, addr+7, (uint8_t*)xda + 7, 1);
735	}
736	STAM_PROFILE_ADV_STOP(&pThis->CTXSUFF(StatTmdStore), a);
737	}
738
739	/**
740	* Load receive message descriptor
741	* Make sure we read the own flag first.
742	*
743	* @param pThis adapter private data
744	* @param addr physical address of the descriptor
745	* @param fRetIfNotOwn return immediately after reading the own flag if we don't own the descriptor
746	* @return true if we own the descriptor, false otherwise
747	*/
748	DECLINLINE(int) pcnetRmdLoad(PCNetState pThis, RMD rmd, RTGCPHYS32 addr, bool fRetIfNotOwn)
749	{
750	PPDMDEVINS pDevIns = PCNETSTATE_2_DEVINS(pThis);
751	uint8_t ownbyte;
752
753	if (pThis->fPrivIfEnabled)
754	{
755	/* RX/TX descriptors shared between host and guest => direct copy */
756	uint8_t pb = (uint8_t)pThis->CTX_SUFF(pSharedMMIO)
757	+ (addr - pThis->GCRDRA)
758	+ pThis->CTX_SUFF(pSharedMMIO)->V.V1.offRxDescriptors;
759	if (!(pb[7] & 0x80) && fRetIfNotOwn)
760	return false;
761	memcpy(rmd, pb, 16);
762	return true;
763	}
764	else if (RT_UNLIKELY(BCR_SWSTYLE(pThis) == 0))
765	{
766	uint16_t rda[4];
767	PDMDevHlpPhysRead(pDevIns, addr+3, &ownbyte, 1);
768	if (!(ownbyte & 0x80) && fRetIfNotOwn)
769	return false;
770	PDMDevHlpPhysRead(pDevIns, addr, (void*)&rda[0], sizeof(rda));
771	((uint32_t *)rmd)[0] = (uint32_t)rda[0] \| ((rda[1] & 0x00ff) << 16);
772	((uint32_t *)rmd)[1] = (uint32_t)rda[2] \| ((rda[1] & 0xff00) << 16);
773	((uint32_t *)rmd)[2] = (uint32_t)rda[3];
774	((uint32_t *)rmd)[3] = 0;
775	}
776	else if (RT_LIKELY(BCR_SWSTYLE(pThis) != 3))
777	{
778	PDMDevHlpPhysRead(pDevIns, addr+7, &ownbyte, 1);
779	if (!(ownbyte & 0x80) && fRetIfNotOwn)
780	return false;
781	PDMDevHlpPhysRead(pDevIns, addr, (void*)rmd, 16);
782	}
783	else
784	{
785	uint32_t rda[4];
786	PDMDevHlpPhysRead(pDevIns, addr+7, &ownbyte, 1);
787	if (!(ownbyte & 0x80) && fRetIfNotOwn)
788	return false;
789	PDMDevHlpPhysRead(pDevIns, addr, (void*)&rda[0], sizeof(rda));
790	((uint32_t *)rmd)[0] = rda[2];
791	((uint32_t *)rmd)[1] = rda[1];
792	((uint32_t *)rmd)[2] = rda[0];
793	((uint32_t *)rmd)[3] = rda[3];
794	}
795	/* Double check the own bit; guest drivers might be buggy and lock prefixes in the recompiler are ignored by other threads. */
796	#ifdef DEBUG
797	if (rmd->rmd1.own == 1 && !(ownbyte & 0x80))
798	Log(("pcnetRmdLoad: own bit flipped while reading!!\n"));
799	#endif
800	if (!(ownbyte & 0x80))
801	rmd->rmd1.own = 0;
802
803	return !!rmd->rmd1.own;
804	}
805
806	#ifdef IN_RING3
807
808	/**
809	* Store receive message descriptor and hand it over to the host (the VM guest).
810	* Make sure that all data are transmitted before we clear the own flag.
811	*/
812	DECLINLINE(void) pcnetRmdStorePassHost(PCNetState pThis, RMD rmd, RTGCPHYS32 addr)
813	{
814	PPDMDEVINS pDevIns = PCNETSTATE_2_DEVINS(pThis);
815	if (pThis->fPrivIfEnabled)
816	{
817	/* RX/TX descriptors shared between host and guest => direct copy */
818	uint8_t pv = (uint8_t)pThis->CTX_SUFF(pSharedMMIO)
819	+ (addr - pThis->GCRDRA)
820	+ pThis->CTX_SUFF(pSharedMMIO)->V.V1.offRxDescriptors;
821	memcpy(pv, rmd, 16);
822	pv[7] &= ~0x80;
823	}
824	else if (RT_UNLIKELY(BCR_SWSTYLE(pThis) == 0))
825	{
826	uint16_t rda[4];
827	rda[0] = ((uint32_t *)rmd)[0] & 0xffff;
828	rda[1] = ((((uint32_t )rmd)[0]>>16) & 0xff) \| ((((uint32_t )rmd)[1]>>16) & 0xff00);
829	rda[2] = ((uint32_t *)rmd)[1] & 0xffff;
830	rda[3] = ((uint32_t *)rmd)[2] & 0xffff;
831	rda[1] \|= 0x8000;
832	PDMDevHlpPhysWrite(pDevIns, addr, (void*)&rda[0], sizeof(rda));
833	rda[1] &= ~0x8000;
834	PDMDevHlpPhysWrite(pDevIns, addr+3, (uint8_t*)rda + 3, 1);
835	}
836	else if (RT_LIKELY(BCR_SWSTYLE(pThis) != 3))
837	{
838	((uint32_t*)rmd)[1] \|= 0x80000000;
839	PDMDevHlpPhysWrite(pDevIns, addr, (void*)rmd, 16);
840	((uint32_t*)rmd)[1] &= ~0x80000000;
841	PDMDevHlpPhysWrite(pDevIns, addr+7, (uint8_t*)rmd + 7, 1);
842	}
843	else
844	{
845	uint32_t rda[4];
846	rda[0] = ((uint32_t *)rmd)[2];
847	rda[1] = ((uint32_t *)rmd)[1];
848	rda[2] = ((uint32_t *)rmd)[0];
849	rda[3] = ((uint32_t *)rmd)[3];
850	rda[1] \|= 0x80000000;
851	PDMDevHlpPhysWrite(pDevIns, addr, (void*)&rda[0], sizeof(rda));
852	rda[1] &= ~0x80000000;
853	PDMDevHlpPhysWrite(pDevIns, addr+7, (uint8_t*)rda + 7, 1);
854	}
855	}
856
857	/**
858	* Read+Write a TX/RX descriptor to prevent PDMDevHlpPhysWrite() allocating
859	* pages later when we shouldn't schedule to EMT. Temporarily hack.
860	*/
861	static void pcnetDescTouch(PCNetState *pThis, RTGCPHYS32 addr)
862	{
863	PPDMDEVINS pDevIns = PCNETSTATE_2_DEVINS(pThis);
864
865	if (!pThis->fPrivIfEnabled)
866	{
867	uint8_t aBuf[16];
868	size_t cbDesc;
869	if (RT_UNLIKELY(BCR_SWSTYLE(pThis) == 0))
870	cbDesc = 8;
871	else
872	cbDesc = 16;
873	PDMDevHlpPhysRead(pDevIns, addr, aBuf, cbDesc);
874	PDMDevHlpPhysWrite(pDevIns, addr, aBuf, cbDesc);
875	}
876	}
877
878	#endif /* IN_RING3 */
879
880	/** Checks if it's a bad (as in invalid) RMD.*/
881	#define IS_RMD_BAD(rmd) ((rmd).rmd1.ones != 15 \|\| (rmd).rmd2.zeros != 0)
882
883	/** The network card is the owner of the RDTE/TDTE, actually it is this driver */
884	#define CARD_IS_OWNER(desc) (((desc) & 0x8000))
885
886	/** The host is the owner of the RDTE/TDTE -- actually the VM guest. */
887	#define HOST_IS_OWNER(desc) (!((desc) & 0x8000))
888
889	#ifndef ETHER_IS_MULTICAST /* Net/Open BSD macro it seems */
890	#define ETHER_IS_MULTICAST(a) (((uint8_t )(a)) & 1)
891	#endif
892
893	#define ETHER_ADDR_LEN ETH_ALEN
894	#define ETH_ALEN 6
895	#pragma pack(1)
896	struct ether_header /** @todo Use RTNETETHERHDR */
897	{
898	uint8_t ether_dhost[ETH_ALEN]; /*< destination ethernet address /
899	uint8_t ether_shost[ETH_ALEN]; /*< source ethernet address /
900	uint16_t ether_type; /*< packet type ID field /
901	};
902	#pragma pack()
903
904	#define PRINT_PKTHDR(BUF) do { \
905	struct ether_header hdr = (struct ether_header )(BUF); \
906	Log(("#%d packet dhost=%02x:%02x:%02x:%02x:%02x:%02x, " \
907	"shost=%02x:%02x:%02x:%02x:%02x:%02x, " \
908	"type=%#06x (bcast=%d)\n", PCNET_INST_NR, \
909	hdr->ether_dhost[0],hdr->ether_dhost[1],hdr->ether_dhost[2], \
910	hdr->ether_dhost[3],hdr->ether_dhost[4],hdr->ether_dhost[5], \
911	hdr->ether_shost[0],hdr->ether_shost[1],hdr->ether_shost[2], \
912	hdr->ether_shost[3],hdr->ether_shost[4],hdr->ether_shost[5], \
913	htons(hdr->ether_type), \
914	!!ETHER_IS_MULTICAST(hdr->ether_dhost))); \
915	} while (0)
916
917
918	#ifdef IN_RING3
919
920	/**
921	* Initialize the shared memory for the private guest interface.
922	*
923	* @note Changing this layout will break SSM for guests using the private guest interface!
924	*/
925	static void pcnetInitSharedMemory(PCNetState *pThis)
926	{
927	/* Clear the entire block for pcnetReset usage. */
928	memset(pThis->pSharedMMIOR3, 0, PCNET_GUEST_SHARED_MEMORY_SIZE);
929
930	pThis->pSharedMMIOR3->u32Version = PCNET_GUEST_INTERFACE_VERSION;
931	uint32_t off = 2048; /* Leave some space for more fields within the header */
932
933	/*
934	* The Descriptor arrays.
935	*/
936	pThis->pSharedMMIOR3->V.V1.offTxDescriptors = off;
937	off = RT_ALIGN(off + PCNET_GUEST_TX_DESCRIPTOR_SIZE * PCNET_GUEST_MAX_TX_DESCRIPTORS, 32);
938
939	pThis->pSharedMMIOR3->V.V1.offRxDescriptors = off;
940	off = RT_ALIGN(off + PCNET_GUEST_RX_DESCRIPTOR_SIZE * PCNET_GUEST_MAX_RX_DESCRIPTORS, 32);
941
942	/* Make sure all the descriptors are mapped into HMA space (and later ring-0). The 8192
943	bytes limit is hardcoded in the PDMDevHlpMMHyperMapMMIO2 call down in pcnetConstruct. */
944	AssertRelease(off <= 8192);
945
946	/*
947	* The buffer arrays.
948	*/
949	#if 0
950	/* Don't allocate TX buffers since Windows guests cannot use it */
951	pThis->pSharedMMIOR3->V.V1.offTxBuffers = off;
952	off = RT_ALIGN(off + PCNET_GUEST_NIC_BUFFER_SIZE * PCNET_GUEST_MAX_TX_DESCRIPTORS, 32);
953	#endif
954
955	pThis->pSharedMMIOR3->V.V1.offRxBuffers = off;
956	pThis->pSharedMMIOR3->fFlags = PCNET_GUEST_FLAGS_ADMIT_HOST;
957	off = RT_ALIGN(off + PCNET_GUEST_NIC_BUFFER_SIZE * PCNET_GUEST_MAX_RX_DESCRIPTORS, 32);
958	AssertRelease(off <= PCNET_GUEST_SHARED_MEMORY_SIZE);
959
960	/* Update the header with the final size. */
961	pThis->pSharedMMIOR3->cbUsed = off;
962	}
963
964	#define MULTICAST_FILTER_LEN 8
965
966	DECLINLINE(uint32_t) lnc_mchash(const uint8_t *ether_addr)
967	{
968	#define LNC_POLYNOMIAL 0xEDB88320UL
969	uint32_t crc = 0xFFFFFFFF;
970	int idx, bit;
971	uint8_t data;
972
973	for (idx = 0; idx < ETHER_ADDR_LEN; idx++)
974	{
975	for (data = *ether_addr++, bit = 0; bit < MULTICAST_FILTER_LEN; bit++)
976	{
977	crc = (crc >> 1) ^ (((crc ^ data) & 1) ? LNC_POLYNOMIAL : 0);
978	data >>= 1;
979	}
980	}
981	return crc;
982	#undef LNC_POLYNOMIAL
983	}
984
985	#define CRC(crc, ch) (crc = (crc >> 8) ^ crctab[(crc ^ (ch)) & 0xff])
986
987	/* generated using the AUTODIN II polynomial
988	* x^32 + x^26 + x^23 + x^22 + x^16 +
989	* x^12 + x^11 + x^10 + x^8 + x^7 + x^5 + x^4 + x^2 + x^1 + 1
990	*/
991	static const uint32_t crctab[256] =
992	{
993	0x00000000, 0x77073096, 0xee0e612c, 0x990951ba,
994	0x076dc419, 0x706af48f, 0xe963a535, 0x9e6495a3,
995	0x0edb8832, 0x79dcb8a4, 0xe0d5e91e, 0x97d2d988,
996	0x09b64c2b, 0x7eb17cbd, 0xe7b82d07, 0x90bf1d91,
997	0x1db71064, 0x6ab020f2, 0xf3b97148, 0x84be41de,
998	0x1adad47d, 0x6ddde4eb, 0xf4d4b551, 0x83d385c7,
999	0x136c9856, 0x646ba8c0, 0xfd62f97a, 0x8a65c9ec,
1000	0x14015c4f, 0x63066cd9, 0xfa0f3d63, 0x8d080df5,
1001	0x3b6e20c8, 0x4c69105e, 0xd56041e4, 0xa2677172,
1002	0x3c03e4d1, 0x4b04d447, 0xd20d85fd, 0xa50ab56b,
1003	0x35b5a8fa, 0x42b2986c, 0xdbbbc9d6, 0xacbcf940,
1004	0x32d86ce3, 0x45df5c75, 0xdcd60dcf, 0xabd13d59,
1005	0x26d930ac, 0x51de003a, 0xc8d75180, 0xbfd06116,
1006	0x21b4f4b5, 0x56b3c423, 0xcfba9599, 0xb8bda50f,
1007	0x2802b89e, 0x5f058808, 0xc60cd9b2, 0xb10be924,
1008	0x2f6f7c87, 0x58684c11, 0xc1611dab, 0xb6662d3d,
1009	0x76dc4190, 0x01db7106, 0x98d220bc, 0xefd5102a,
1010	0x71b18589, 0x06b6b51f, 0x9fbfe4a5, 0xe8b8d433,
1011	0x7807c9a2, 0x0f00f934, 0x9609a88e, 0xe10e9818,
1012	0x7f6a0dbb, 0x086d3d2d, 0x91646c97, 0xe6635c01,
1013	0x6b6b51f4, 0x1c6c6162, 0x856530d8, 0xf262004e,
1014	0x6c0695ed, 0x1b01a57b, 0x8208f4c1, 0xf50fc457,
1015	0x65b0d9c6, 0x12b7e950, 0x8bbeb8ea, 0xfcb9887c,
1016	0x62dd1ddf, 0x15da2d49, 0x8cd37cf3, 0xfbd44c65,
1017	0x4db26158, 0x3ab551ce, 0xa3bc0074, 0xd4bb30e2,
1018	0x4adfa541, 0x3dd895d7, 0xa4d1c46d, 0xd3d6f4fb,
1019	0x4369e96a, 0x346ed9fc, 0xad678846, 0xda60b8d0,
1020	0x44042d73, 0x33031de5, 0xaa0a4c5f, 0xdd0d7cc9,
1021	0x5005713c, 0x270241aa, 0xbe0b1010, 0xc90c2086,
1022	0x5768b525, 0x206f85b3, 0xb966d409, 0xce61e49f,
1023	0x5edef90e, 0x29d9c998, 0xb0d09822, 0xc7d7a8b4,
1024	0x59b33d17, 0x2eb40d81, 0xb7bd5c3b, 0xc0ba6cad,
1025	0xedb88320, 0x9abfb3b6, 0x03b6e20c, 0x74b1d29a,
1026	0xead54739, 0x9dd277af, 0x04db2615, 0x73dc1683,
1027	0xe3630b12, 0x94643b84, 0x0d6d6a3e, 0x7a6a5aa8,
1028	0xe40ecf0b, 0x9309ff9d, 0x0a00ae27, 0x7d079eb1,
1029	0xf00f9344, 0x8708a3d2, 0x1e01f268, 0x6906c2fe,
1030	0xf762575d, 0x806567cb, 0x196c3671, 0x6e6b06e7,
1031	0xfed41b76, 0x89d32be0, 0x10da7a5a, 0x67dd4acc,
1032	0xf9b9df6f, 0x8ebeeff9, 0x17b7be43, 0x60b08ed5,
1033	0xd6d6a3e8, 0xa1d1937e, 0x38d8c2c4, 0x4fdff252,
1034	0xd1bb67f1, 0xa6bc5767, 0x3fb506dd, 0x48b2364b,
1035	0xd80d2bda, 0xaf0a1b4c, 0x36034af6, 0x41047a60,
1036	0xdf60efc3, 0xa867df55, 0x316e8eef, 0x4669be79,
1037	0xcb61b38c, 0xbc66831a, 0x256fd2a0, 0x5268e236,
1038	0xcc0c7795, 0xbb0b4703, 0x220216b9, 0x5505262f,
1039	0xc5ba3bbe, 0xb2bd0b28, 0x2bb45a92, 0x5cb36a04,
1040	0xc2d7ffa7, 0xb5d0cf31, 0x2cd99e8b, 0x5bdeae1d,
1041	0x9b64c2b0, 0xec63f226, 0x756aa39c, 0x026d930a,
1042	0x9c0906a9, 0xeb0e363f, 0x72076785, 0x05005713,
1043	0x95bf4a82, 0xe2b87a14, 0x7bb12bae, 0x0cb61b38,
1044	0x92d28e9b, 0xe5d5be0d, 0x7cdcefb7, 0x0bdbdf21,
1045	0x86d3d2d4, 0xf1d4e242, 0x68ddb3f8, 0x1fda836e,
1046	0x81be16cd, 0xf6b9265b, 0x6fb077e1, 0x18b74777,
1047	0x88085ae6, 0xff0f6a70, 0x66063bca, 0x11010b5c,
1048	0x8f659eff, 0xf862ae69, 0x616bffd3, 0x166ccf45,
1049	0xa00ae278, 0xd70dd2ee, 0x4e048354, 0x3903b3c2,
1050	0xa7672661, 0xd06016f7, 0x4969474d, 0x3e6e77db,
1051	0xaed16a4a, 0xd9d65adc, 0x40df0b66, 0x37d83bf0,
1052	0xa9bcae53, 0xdebb9ec5, 0x47b2cf7f, 0x30b5ffe9,
1053	0xbdbdf21c, 0xcabac28a, 0x53b39330, 0x24b4a3a6,
1054	0xbad03605, 0xcdd70693, 0x54de5729, 0x23d967bf,
1055	0xb3667a2e, 0xc4614ab8, 0x5d681b02, 0x2a6f2b94,
1056	0xb40bbe37, 0xc30c8ea1, 0x5a05df1b, 0x2d02ef8d,
1057	};
1058
1059	DECLINLINE(int) padr_match(PCNetState pThis, const uint8_t buf, size_t size)
1060	{
1061	struct ether_header hdr = (struct ether_header )buf;
1062	int result;
1063	#if (defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)) && !defined(PCNET_DEBUG_MATCH)
1064	result = !CSR_DRCVPA(pThis) && !memcmp(hdr->ether_dhost, pThis->aCSR + 12, 6);
1065	#else
1066	uint8_t padr[6];
1067	padr[0] = pThis->aCSR[12] & 0xff;
1068	padr[1] = pThis->aCSR[12] >> 8;
1069	padr[2] = pThis->aCSR[13] & 0xff;
1070	padr[3] = pThis->aCSR[13] >> 8;
1071	padr[4] = pThis->aCSR[14] & 0xff;
1072	padr[5] = pThis->aCSR[14] >> 8;
1073	result = !CSR_DRCVPA(pThis) && !memcmp(hdr->ether_dhost, padr, 6);
1074	#endif
1075
1076	#ifdef PCNET_DEBUG_MATCH
1077	Log(("#%d packet dhost=%02x:%02x:%02x:%02x:%02x:%02x, "
1078	"padr=%02x:%02x:%02x:%02x:%02x:%02x => %d\n", PCNET_INST_NR,
1079	hdr->ether_dhost[0],hdr->ether_dhost[1],hdr->ether_dhost[2],
1080	hdr->ether_dhost[3],hdr->ether_dhost[4],hdr->ether_dhost[5],
1081	padr[0],padr[1],padr[2],padr[3],padr[4],padr[5], result));
1082	#endif
1083	return result;
1084	}
1085
1086	DECLINLINE(int) padr_bcast(PCNetState pThis, const uint8_t buf, size_t size)
1087	{
1088	static uint8_t aBCAST[6] = { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff };
1089	struct ether_header hdr = (struct ether_header )buf;
1090	int result = !CSR_DRCVBC(pThis) && !memcmp(hdr->ether_dhost, aBCAST, 6);
1091	#ifdef PCNET_DEBUG_MATCH
1092	Log(("#%d padr_bcast result=%d\n", PCNET_INST_NR, result));
1093	#endif
1094	return result;
1095	}
1096
1097	static int ladr_match(PCNetState pThis, const uint8_t buf, size_t size)
1098	{
1099	struct ether_header hdr = (struct ether_header )buf;
1100	if (RT_UNLIKELY(hdr->ether_dhost[0] & 0x01) && ((uint64_t *)&pThis->aCSR[8])[0] != 0LL)
1101	{
1102	int index;
1103	#if defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)
1104	index = lnc_mchash(hdr->ether_dhost) >> 26;
1105	return ((uint8_t*)(pThis->aCSR + 8))[index >> 3] & (1 << (index & 7));
1106	#else
1107	uint8_t ladr[8];
1108	ladr[0] = pThis->aCSR[8] & 0xff;
1109	ladr[1] = pThis->aCSR[8] >> 8;
1110	ladr[2] = pThis->aCSR[9] & 0xff;
1111	ladr[3] = pThis->aCSR[9] >> 8;
1112	ladr[4] = pThis->aCSR[10] & 0xff;
1113	ladr[5] = pThis->aCSR[10] >> 8;
1114	ladr[6] = pThis->aCSR[11] & 0xff;
1115	ladr[7] = pThis->aCSR[11] >> 8;
1116	index = lnc_mchash(hdr->ether_dhost) >> 26;
1117	return (ladr[index >> 3] & (1 << (index & 7)));
1118	#endif
1119	}
1120	return 0;
1121	}
1122
1123	#endif /* IN_RING3 */
1124
1125	/**
1126	* Get the receive descriptor ring address with a given index.
1127	*/
1128	DECLINLINE(RTGCPHYS32) pcnetRdraAddr(PCNetState *pThis, int idx)
1129	{
1130	return pThis->GCRDRA + ((CSR_RCVRL(pThis) - idx) << pThis->iLog2DescSize);
1131	}
1132
1133	/**
1134	* Get the transmit descriptor ring address with a given index.
1135	*/
1136	DECLINLINE(RTGCPHYS32) pcnetTdraAddr(PCNetState *pThis, int idx)
1137	{
1138	return pThis->GCTDRA + ((CSR_XMTRL(pThis) - idx) << pThis->iLog2DescSize);
1139	}
1140
1141	RT_C_DECLS_BEGIN
1142	PDMBOTHCBDECL(int) pcnetIOPortRead(PPDMDEVINS pDevIns, void *pvUser,
1143	RTIOPORT Port, uint32_t *pu32, unsigned cb);
1144	PDMBOTHCBDECL(int) pcnetIOPortWrite(PPDMDEVINS pDevIns, void *pvUser,
1145	RTIOPORT Port, uint32_t u32, unsigned cb);
1146	PDMBOTHCBDECL(int) pcnetIOPortAPromWrite(PPDMDEVINS pDevIns, void *pvUser,
1147	RTIOPORT Port, uint32_t u32, unsigned cb);
1148	PDMBOTHCBDECL(int) pcnetIOPortAPromRead(PPDMDEVINS pDevIns, void *pvUser,
1149	RTIOPORT Port, uint32_t *pu32, unsigned cb);
1150	PDMBOTHCBDECL(int) pcnetMMIORead(PPDMDEVINS pDevIns, void *pvUser,
1151	RTGCPHYS GCPhysAddr, void *pv, unsigned cb);
1152	PDMBOTHCBDECL(int) pcnetMMIOWrite(PPDMDEVINS pDevIns, void *pvUser,
1153	RTGCPHYS GCPhysAddr, void *pv, unsigned cb);
1154	#ifndef IN_RING3
1155	DECLEXPORT(int) pcnetHandleRingWrite(PVM pVM, RTGCUINT uErrorCode, PCPUMCTXCORE pRegFrame,
1156	RTGCPTR pvFault, RTGCPHYS GCPhysFault, void *pvUser);
1157	#endif
1158	RT_C_DECLS_END
1159
1160	#undef htonl
1161	#define htonl(x) ASMByteSwapU32(x)
1162	#undef htons
1163	#define htons(x) ( (((x) & 0xff00) >> 8) \| (((x) & 0x00ff) << 8) )
1164
1165	static void pcnetPollRxTx(PCNetState *pThis);
1166	static void pcnetPollTimer(PCNetState *pThis);
1167	static void pcnetUpdateIrq(PCNetState *pThis);
1168	static uint32_t pcnetBCRReadU16(PCNetState *pThis, uint32_t u32RAP);
1169	static int pcnetBCRWriteU16(PCNetState *pThis, uint32_t u32RAP, uint32_t val);
1170
1171
1172	#ifdef PCNET_NO_POLLING
1173	# ifndef IN_RING3
1174
1175	/**
1176	* #PF Virtual Handler callback for Guest write access to the ring descriptor page(pThis)
1177	*
1178	* @return VBox status code (appropriate for trap handling and GC return).
1179	* @param pVM VM Handle.
1180	* @param uErrorCode CPU Error code.
1181	* @param pRegFrame Trap register frame.
1182	* @param pvFault The fault address (cr2).
1183	* @param GCPhysFault The GC physical address corresponding to pvFault.
1184	* @param pvUser User argument.
1185	*/
1186	DECLEXPORT(int) pcnetHandleRingWrite(PVM pVM, RTGCUINT uErrorCode, PCPUMCTXCORE pRegFrame,
1187	RTGCPTR pvFault, RTGCPHYS GCPhysFault, void *pvUser)
1188	{
1189	PCNetState pThis = (PCNetState )pvUser;
1190
1191	Log(("#%d pcnetHandleRingWriteGC: write to %#010x\n", PCNET_INST_NR, GCPhysFault));
1192
1193	uint32_t cb;
1194	int rc = CTXALLSUFF(pThis->pfnEMInterpretInstruction)(pVM, pRegFrame, pvFault, &cb);
1195	if (RT_SUCCESS(rc) && cb)
1196	{
1197	if ( (GCPhysFault >= pThis->GCTDRA && GCPhysFault + cb < pcnetTdraAddr(pThis, 0))
1198	#ifdef PCNET_MONITOR_RECEIVE_RING
1199	\|\| (GCPhysFault >= pThis->GCRDRA && GCPhysFault + cb < pcnetRdraAddr(pThis, 0))
1200	#endif
1201	)
1202	{
1203	uint32_t offsetTDRA = (GCPhysFault - pThis->GCTDRA);
1204
1205	int rc = PDMCritSectEnter(&pThis->CritSect, VERR_SEM_BUSY);
1206	if (RT_SUCCESS(rc))
1207	{
1208	STAM_COUNTER_INC(&CTXALLSUFF(pThis->StatRingWrite)); ;
1209
1210	/* Check if we can do something now */
1211	pcnetPollRxTx(pThis);
1212	pcnetUpdateIrq(pThis);
1213
1214	PDMCritSectLeave(&pThis->CritSect);
1215	return VINF_SUCCESS;
1216	}
1217	}
1218	else
1219	{
1220	STAM_COUNTER_INC(&CTXALLSUFF(pThis->StatRingWriteOutside)); ;
1221	return VINF_SUCCESS; /* outside of the ring range */
1222	}
1223	}
1224	STAM_COUNTER_INC(&CTXALLSUFF(pThis->StatRingWriteFailed)); ;
1225	return VINF_IOM_HC_MMIO_WRITE; /* handle in ring3 */
1226	}
1227
1228	# else /* IN_RING3 */
1229
1230	/**
1231	* #PF Handler callback for physical access handler ranges (MMIO among others) in HC.
1232	*
1233	* The handler can not raise any faults, it's mainly for monitoring write access
1234	* to certain pages.
1235	*
1236	* @returns VINF_SUCCESS if the handler have carried out the operation.
1237	* @returns VINF_PGM_HANDLER_DO_DEFAULT if the caller should carry out the access operation.
1238	* @param pVM VM Handle.
1239	* @param GCPhys The physical address the guest is writing to.
1240	* @param pvPhys The HC mapping of that address.
1241	* @param pvBuf What the guest is reading/writing.
1242	* @param cbBuf How much it's reading/writing.
1243	* @param enmAccessType The access type.
1244	* @param pvUser User argument.
1245	*/
1246	static DECLCALLBACK(int) pcnetHandleRingWrite(PVM pVM, RTGCPHYS GCPhys, void pvPhys, void pvBuf,
1247	size_t cbBuf, PGMACCESSTYPE enmAccessType, void *pvUser)
1248	{
1249	PPDMDEVINS pDevIns = (PPDMDEVINS)pvUser;
1250	PCNetState pThis = PDMINS_2_DATA(pDevIns, PCNetState );
1251
1252	Log(("#%d pcnetHandleRingWrite: write to %#010x\n", PCNET_INST_NR, GCPhys));
1253	#ifdef VBOX_WITH_STATISTICS
1254	STAM_COUNTER_INC(&CTXSUFF(pThis->StatRingWrite));
1255	if (GCPhys >= pThis->GCRDRA && GCPhys < pcnetRdraAddr(pThis, 0))
1256	STAM_COUNTER_INC(&pThis->StatRCVRingWrite);
1257	else if (GCPhys >= pThis->GCTDRA && GCPhys < pcnetTdraAddr(pThis, 0))
1258	STAM_COUNTER_INC(&pThis->StatTXRingWrite);
1259	#endif
1260	/* Perform the actual write */
1261	memcpy((char *)pvPhys, pvBuf, cbBuf);
1262
1263	/* Writes done by our code don't require polling of course */
1264	if (PDMCritSectIsOwner(&pThis->CritSect) == false)
1265	{
1266	if ( (GCPhys >= pThis->GCTDRA && GCPhys + cbBuf < pcnetTdraAddr(pThis, 0))
1267	#ifdef PCNET_MONITOR_RECEIVE_RING
1268	\|\| (GCPhys >= pThis->GCRDRA && GCPhys + cbBuf < pcnetRdraAddr(pThis, 0))
1269	#endif
1270	)
1271	{
1272	int rc = PDMCritSectEnter(&pThis->CritSect, VERR_SEM_BUSY);
1273	AssertReleaseRC(rc);
1274	/* Check if we can do something now */
1275	pcnetPollRxTx(pThis);
1276	pcnetUpdateIrq(pThis);
1277	PDMCritSectLeave(&pThis->CritSect);
1278	}
1279	}
1280	return VINF_SUCCESS;
1281	}
1282	# endif /* !IN_RING3 */
1283	#endif /* PCNET_NO_POLLING */
1284
1285	static void pcnetSoftReset(PCNetState *pThis)
1286	{
1287	Log(("#%d pcnetSoftReset:\n", PCNET_INST_NR));
1288
1289	pThis->u32Lnkst = 0x40;
1290	pThis->GCRDRA = 0;
1291	pThis->GCTDRA = 0;
1292	pThis->u32RAP = 0;
1293
1294	pThis->aCSR[0] = 0x0004;
1295	pThis->aCSR[3] = 0x0000;
1296	pThis->aCSR[4] = 0x0115;
1297	pThis->aCSR[5] = 0x0000;
1298	pThis->aCSR[6] = 0x0000;
1299	pThis->aCSR[8] = 0;
1300	pThis->aCSR[9] = 0;
1301	pThis->aCSR[10] = 0;
1302	pThis->aCSR[11] = 0;
1303	pThis->aCSR[12] = RT_LE2H_U16(((uint16_t *)&pThis->aPROM[0])[0]);
1304	pThis->aCSR[13] = RT_LE2H_U16(((uint16_t *)&pThis->aPROM[0])[1]);
1305	pThis->aCSR[14] = RT_LE2H_U16(((uint16_t *)&pThis->aPROM[0])[2]);
1306	pThis->aCSR[15] &= 0x21c4;
1307	CSR_RCVRC(pThis) = 1;
1308	CSR_XMTRC(pThis) = 1;
1309	CSR_RCVRL(pThis) = 1;
1310	CSR_XMTRL(pThis) = 1;
1311	pThis->aCSR[80] = 0x1410;
1312	pThis->aCSR[88] = pThis->fAm79C973 ? CSR_VERSION_LOW_79C973 : CSR_VERSION_LOW_79C970A;
1313	pThis->aCSR[89] = CSR_VERSION_HIGH;
1314	pThis->aCSR[94] = 0x0000;
1315	pThis->aCSR[100] = 0x0200;
1316	pThis->aCSR[103] = 0x0105;
1317	pThis->aCSR[103] = 0x0105;
1318	CSR_MISSC(pThis) = 0;
1319	pThis->aCSR[114] = 0x0000;
1320	pThis->aCSR[122] = 0x0000;
1321	pThis->aCSR[124] = 0x0000;
1322	}
1323
1324	/**
1325	* Check if we have to send an interrupt to the guest. An interrupt can occur on
1326	* - csr0 (written quite often)
1327	* - csr4 (only written by pcnetSoftReset(), pcnetStop() or by the guest driver)
1328	* - csr5 (only written by pcnetSoftReset(), pcnetStop or by the driver guest)
1329	*/
1330	static void pcnetUpdateIrq(PCNetState *pThis)
1331	{
1332	register int iISR = 0;
1333	register uint16_t csr0 = pThis->aCSR[0];
1334
1335	csr0 &= ~0x0080; /* clear INTR */
1336
1337	STAM_PROFILE_ADV_START(&pThis->StatInterrupt, a);
1338
1339	/* Linux guests set csr4=0x0915
1340	* W2k guests set csr3=0x4940 (disable BABL, MERR, IDON, DXSUFLO */
1341
1342	#if 1
1343	if ( ( (csr0 & ~pThis->aCSR[3]) & 0x5f00)
1344	\|\| (((pThis->aCSR[4]>>1) & ~pThis->aCSR[4]) & 0x0115)
1345	\|\| (((pThis->aCSR[5]>>1) & pThis->aCSR[5]) & 0x0048))
1346	#else
1347	if ( ( !(pThis->aCSR[3] & 0x4000) && !!(csr0 & 0x4000)) /* BABL */
1348	\|\|( !(pThis->aCSR[3] & 0x1000) && !!(csr0 & 0x1000)) /* MISS */
1349	\|\|( !(pThis->aCSR[3] & 0x0100) && !!(csr0 & 0x0100)) /* IDON */
1350	\|\|( !(pThis->aCSR[3] & 0x0200) && !!(csr0 & 0x0200)) /* TINT */
1351	\|\|( !(pThis->aCSR[3] & 0x0400) && !!(csr0 & 0x0400)) /* RINT */
1352	\|\|( !(pThis->aCSR[3] & 0x0800) && !!(csr0 & 0x0800)) /* MERR */
1353	\|\|( !(pThis->aCSR[4] & 0x0001) && !!(pThis->aCSR[4] & 0x0002)) /* JAB */
1354	\|\|( !(pThis->aCSR[4] & 0x0004) && !!(pThis->aCSR[4] & 0x0008)) /* TXSTRT */
1355	\|\|( !(pThis->aCSR[4] & 0x0010) && !!(pThis->aCSR[4] & 0x0020)) /* RCVO */
1356	\|\|( !(pThis->aCSR[4] & 0x0100) && !!(pThis->aCSR[4] & 0x0200)) /* MFCO */
1357	\|\|(!!(pThis->aCSR[5] & 0x0040) && !!(pThis->aCSR[5] & 0x0080)) /* EXDINT */
1358	\|\|(!!(pThis->aCSR[5] & 0x0008) && !!(pThis->aCSR[5] & 0x0010)) /* MPINT */)
1359	#endif
1360	{
1361	iISR = !!(csr0 & 0x0040); /* CSR_INEA */
1362	csr0 \|= 0x0080; /* set INTR */
1363	}
1364
1365	#ifdef VBOX
1366	if (pThis->aCSR[4] & 0x0080) /* UINTCMD */
1367	{
1368	pThis->aCSR[4] &= ~0x0080; /* clear UINTCMD */
1369	pThis->aCSR[4] \|= 0x0040; /* set UINT */
1370	Log(("#%d user int\n", PCNET_INST_NR));
1371	}
1372	if (pThis->aCSR[4] & csr0 & 0x0040 /* CSR_INEA */)
1373	{
1374	csr0 \|= 0x0080; /* set INTR */
1375	iISR = 1;
1376	}
1377	#else /* !VBOX */
1378	if (!!(pThis->aCSR[4] & 0x0080) && CSR_INEA(pThis)) /* UINTCMD */
1379	{
1380	pThis->aCSR[4] &= ~0x0080;
1381	pThis->aCSR[4] \|= 0x0040; /* set UINT */
1382	csr0 \|= 0x0080; /* set INTR */
1383	iISR = 1;
1384	Log(("#%d user int\n", PCNET_INST_NR));
1385	}
1386	#endif /* !VBOX */
1387
1388	#if 1
1389	if (((pThis->aCSR[5]>>1) & pThis->aCSR[5]) & 0x0500)
1390	#else
1391	if ( (!!(pThis->aCSR[5] & 0x0400) && !!(pThis->aCSR[5] & 0x0800)) /* SINT */
1392	\|\|(!!(pThis->aCSR[5] & 0x0100) && !!(pThis->aCSR[5] & 0x0200)) /* SLPINT */)
1393	#endif
1394	{
1395	iISR = 1;
1396	csr0 \|= 0x0080; /* INTR */
1397	}
1398
1399	if ((pThis->aCSR[7] & 0x0C00) == 0x0C00) /* STINT + STINTE */
1400	iISR = 1;
1401
1402	pThis->aCSR[0] = csr0;
1403
1404	Log2(("#%d set irq iISR=%d\n", PCNET_INST_NR, iISR));
1405
1406	/* normal path is to _not_ change the IRQ status */
1407	if (RT_UNLIKELY(iISR != pThis->iISR))
1408	{
1409	Log(("#%d INTA=%d\n", PCNET_INST_NR, iISR));
1410	PDMDevHlpPCISetIrqNoWait(PCNETSTATE_2_DEVINS(pThis), 0, iISR);
1411	pThis->iISR = iISR;
1412	}
1413	STAM_PROFILE_ADV_STOP(&pThis->StatInterrupt, a);
1414	}
1415
1416	/**
1417	* Enable/disable the private guest interface.
1418	*/
1419	static void pcnetEnablePrivateIf(PCNetState *pThis)
1420	{
1421	bool fPrivIfEnabled = pThis->pSharedMMIOR3
1422	&& !!(pThis->CTX_SUFF(pSharedMMIO)->fFlags & PCNET_GUEST_FLAGS_ADMIT_GUEST);
1423	if (fPrivIfEnabled != pThis->fPrivIfEnabled)
1424	{
1425	pThis->fPrivIfEnabled = fPrivIfEnabled;
1426	LogRel(("PCNet#%d: %s private interface\n", PCNET_INST_NR, fPrivIfEnabled ? "Enabling" : "Disabling"));
1427	}
1428	}
1429
1430	#ifdef IN_RING3
1431	#ifdef PCNET_NO_POLLING
1432	static void pcnetUpdateRingHandlers(PCNetState *pThis)
1433	{
1434	PPDMDEVINS pDevIns = PCNETSTATE_2_DEVINS(pThis);
1435	int rc;
1436
1437	Log(("pcnetUpdateRingHandlers TD %RX32 size %#x -> %RX32 ?size? %#x\n", pThis->TDRAPhysOld, pThis->cbTDRAOld, pThis->GCTDRA, pcnetTdraAddr(pThis, 0)));
1438	Log(("pcnetUpdateRingHandlers RX %RX32 size %#x -> %RX32 ?size? %#x\n", pThis->RDRAPhysOld, pThis->cbRDRAOld, pThis->GCRDRA, pcnetRdraAddr(pThis, 0)));
1439
1440	/** @todo unregister order not correct! */
1441
1442	#ifdef PCNET_MONITOR_RECEIVE_RING
1443	if (pThis->GCRDRA != pThis->RDRAPhysOld \|\| CSR_RCVRL(pThis) != pThis->cbRDRAOld)
1444	{
1445	if (pThis->RDRAPhysOld != 0)
1446	PGMHandlerPhysicalDeregister(PDMDevHlpGetVM(pDevIns),
1447	pThis->RDRAPhysOld & ~PAGE_OFFSET_MASK);
1448
1449	rc = PGMR3HandlerPhysicalRegister(PDMDevHlpGetVM(pDevIns),
1450	PGMPHYSHANDLERTYPE_PHYSICAL_WRITE,
1451	pThis->GCRDRA & ~PAGE_OFFSET_MASK,
1452	RT_ALIGN(pcnetRdraAddr(pThis, 0), PAGE_SIZE) - 1,
1453	pcnetHandleRingWrite, pDevIns,
1454	g_DevicePCNet.szR0Mod, "pcnetHandleRingWrite",
1455	pThis->pDevInsHC->pvInstanceDataHC,
1456	g_DevicePCNet.szRCMod, "pcnetHandleRingWrite",
1457	pThis->pDevInsHC->pvInstanceDataRC,
1458	"PCNet receive ring write access handler");
1459	AssertRC(rc);
1460
1461	pThis->RDRAPhysOld = pThis->GCRDRA;
1462	pThis->cbRDRAOld = pcnetRdraAddr(pThis, 0);
1463	}
1464	#endif /* PCNET_MONITOR_RECEIVE_RING */
1465
1466	#ifdef PCNET_MONITOR_RECEIVE_RING
1467	/* 3 possibilities:
1468	* 1) TDRA on different physical page as RDRA
1469	* 2) TDRA completely on same physical page as RDRA
1470	* 3) TDRA & RDRA overlap partly with different physical pages
1471	*/
1472	RTGCPHYS32 RDRAPageStart = pThis->GCRDRA & ~PAGE_OFFSET_MASK;
1473	RTGCPHYS32 RDRAPageEnd = (pcnetRdraAddr(pThis, 0) - 1) & ~PAGE_OFFSET_MASK;
1474	RTGCPHYS32 TDRAPageStart = pThis->GCTDRA & ~PAGE_OFFSET_MASK;
1475	RTGCPHYS32 TDRAPageEnd = (pcnetTdraAddr(pThis, 0) - 1) & ~PAGE_OFFSET_MASK;
1476
1477	if ( RDRAPageStart > TDRAPageEnd
1478	\|\| TDRAPageStart > RDRAPageEnd)
1479	{
1480	#endif /* PCNET_MONITOR_RECEIVE_RING */
1481	/* 1) */
1482	if (pThis->GCTDRA != pThis->TDRAPhysOld \|\| CSR_XMTRL(pThis) != pThis->cbTDRAOld)
1483	{
1484	if (pThis->TDRAPhysOld != 0)
1485	PGMHandlerPhysicalDeregister(PDMDevHlpGetVM(pDevIns),
1486	pThis->TDRAPhysOld & ~PAGE_OFFSET_MASK);
1487
1488	rc = PGMR3HandlerPhysicalRegister(PDMDevHlpGetVM(pDevIns),
1489	PGMPHYSHANDLERTYPE_PHYSICAL_WRITE,
1490	pThis->GCTDRA & ~PAGE_OFFSET_MASK,
1491	RT_ALIGN(pcnetTdraAddr(pThis, 0), PAGE_SIZE) - 1,
1492	pcnetHandleRingWrite, pDevIns,
1493	g_DevicePCNet.szR0Mod, "pcnetHandleRingWrite",
1494	pThis->pDevInsHC->pvInstanceDataHC,
1495	g_DevicePCNet.szRCMod, "pcnetHandleRingWrite",
1496	pThis->pDevInsHC->pvInstanceDataRC,
1497	"PCNet transmit ring write access handler");
1498	AssertRC(rc);
1499
1500	pThis->TDRAPhysOld = pThis->GCTDRA;
1501	pThis->cbTDRAOld = pcnetTdraAddr(pThis, 0);
1502	}
1503	#ifdef PCNET_MONITOR_RECEIVE_RING
1504	}
1505	else
1506	if ( RDRAPageStart != TDRAPageStart
1507	&& ( TDRAPageStart == RDRAPageEnd
1508	\|\| TDRAPageEnd == RDRAPageStart
1509	)
1510	)
1511	{
1512	/* 3) */
1513	AssertFailed();
1514	}
1515	/* else 2) */
1516	#endif
1517	}
1518	#endif /* PCNET_NO_POLLING */
1519
1520	static void pcnetInit(PCNetState *pThis)
1521	{
1522	PPDMDEVINS pDevIns = PCNETSTATE_2_DEVINS(pThis);
1523	Log(("#%d pcnetInit: init_addr=%#010x\n", PCNET_INST_NR, PHYSADDR(pThis, CSR_IADR(pThis))));
1524
1525	/** @todo Documentation says that RCVRL and XMTRL are stored as two's complement!
1526	* Software is allowed to write these registers directly. */
1527	#define PCNET_INIT() do { \
1528	PDMDevHlpPhysRead(pDevIns, PHYSADDR(pThis, CSR_IADR(pThis)), \
1529	(uint8_t *)&initblk, sizeof(initblk)); \
1530	pThis->aCSR[15] = RT_LE2H_U16(initblk.mode); \
1531	CSR_RCVRL(pThis) = (initblk.rlen < 9) ? (1 << initblk.rlen) : 512; \
1532	CSR_XMTRL(pThis) = (initblk.tlen < 9) ? (1 << initblk.tlen) : 512; \
1533	pThis->aCSR[ 6] = (initblk.tlen << 12) \| (initblk.rlen << 8); \
1534	pThis->aCSR[ 8] = RT_LE2H_U16(initblk.ladrf1); \
1535	pThis->aCSR[ 9] = RT_LE2H_U16(initblk.ladrf2); \
1536	pThis->aCSR[10] = RT_LE2H_U16(initblk.ladrf3); \
1537	pThis->aCSR[11] = RT_LE2H_U16(initblk.ladrf4); \
1538	pThis->aCSR[12] = RT_LE2H_U16(initblk.padr1); \
1539	pThis->aCSR[13] = RT_LE2H_U16(initblk.padr2); \
1540	pThis->aCSR[14] = RT_LE2H_U16(initblk.padr3); \
1541	pThis->GCRDRA = PHYSADDR(pThis, initblk.rdra); \
1542	pThis->GCTDRA = PHYSADDR(pThis, initblk.tdra); \
1543	} while (0)
1544
1545	pcnetEnablePrivateIf(pThis);
1546
1547	if (BCR_SSIZE32(pThis))
1548	{
1549	struct INITBLK32 initblk;
1550	pThis->GCUpperPhys = 0;
1551	PCNET_INIT();
1552	Log(("#%d initblk.rlen=%#04x, initblk.tlen=%#04x\n",
1553	PCNET_INST_NR, initblk.rlen, initblk.tlen));
1554	}
1555	else
1556	{
1557	struct INITBLK16 initblk;
1558	pThis->GCUpperPhys = (0xff00 & (uint32_t)pThis->aCSR[2]) << 16;
1559	PCNET_INIT();
1560	Log(("#%d initblk.rlen=%#04x, initblk.tlen=%#04x\n",
1561	PCNET_INST_NR, initblk.rlen, initblk.tlen));
1562	}
1563
1564	#undef PCNET_INIT
1565
1566	size_t cbRxBuffers = 0;
1567	for (int i = CSR_RCVRL(pThis); i >= 1; i--)
1568	{
1569	RMD rmd;
1570	RTGCPHYS32 rdaddr = PHYSADDR(pThis, pcnetRdraAddr(pThis, i));
1571
1572	pcnetDescTouch(pThis, rdaddr);
1573	/* At this time it is not guaranteed that the buffers are already initialized. */
1574	if (pcnetRmdLoad(pThis, &rmd, rdaddr, false))
1575	{
1576	uint32_t cbBuf = 4096U-rmd.rmd1.bcnt;
1577	cbRxBuffers += cbBuf;
1578	}
1579	}
1580
1581	for (int i = CSR_XMTRL(pThis); i >= 1; i--)
1582	{
1583	RTGCPHYS32 tdaddr = PHYSADDR(pThis, pcnetTdraAddr(pThis, i));
1584
1585	pcnetDescTouch(pThis, tdaddr);
1586	}
1587
1588	/*
1589	* Heuristics: The Solaris pcn driver allocates too few RX buffers (128 buffers of a
1590	* size of 128 bytes are 16KB in summary) leading to frequent RX buffer overflows. In
1591	* that case we don't signal RX overflows through the CSR0_MISS flag as the driver
1592	* re-initializes the device on every miss. Other guests use at least 32 buffers of
1593	* usually 1536 bytes and should therefore not run into condition. If they are still
1594	* short in RX buffers we notify this condition.
1595	*/
1596	pThis->fSignalRxMiss = (cbRxBuffers == 0 \|\| cbRxBuffers >= 32*_1K);
1597
1598	if (pThis->pDrvR3)
1599	pThis->pDrvR3->pfnSetPromiscuousMode(pThis->pDrvR3, CSR_PROM(pThis));
1600
1601	CSR_RCVRC(pThis) = CSR_RCVRL(pThis);
1602	CSR_XMTRC(pThis) = CSR_XMTRL(pThis);
1603
1604	#ifdef PCNET_NO_POLLING
1605	pcnetUpdateRingHandlers(pThis);
1606	#endif
1607
1608	/* Reset cached RX and TX states */
1609	CSR_CRST(pThis) = CSR_CRBC(pThis) = CSR_NRST(pThis) = CSR_NRBC(pThis) = 0;
1610	CSR_CXST(pThis) = CSR_CXBC(pThis) = CSR_NXST(pThis) = CSR_NXBC(pThis) = 0;
1611
1612	LogRel(("PCNet#%d: Init: ss32=%d GCRDRA=%#010x[%d] GCTDRA=%#010x[%d]%s\n",
1613	PCNET_INST_NR, BCR_SSIZE32(pThis),
1614	pThis->GCRDRA, CSR_RCVRL(pThis), pThis->GCTDRA, CSR_XMTRL(pThis),
1615	!pThis->fSignalRxMiss ? " (CSR0_MISS disabled)" : ""));
1616
1617	pThis->aCSR[0] \|= 0x0101; /* Initialization done */
1618	pThis->aCSR[0] &= ~0x0004; /* clear STOP bit */
1619	}
1620	#endif /* IN_RING3 */
1621
1622	/**
1623	* Start RX/TX operation.
1624	*/
1625	static void pcnetStart(PCNetState *pThis)
1626	{
1627	Log(("#%d pcnetStart:\n", PCNET_INST_NR));
1628	if (!CSR_DTX(pThis))
1629	pThis->aCSR[0] \|= 0x0010; /* set TXON */
1630	if (!CSR_DRX(pThis))
1631	pThis->aCSR[0] \|= 0x0020; /* set RXON */
1632	pcnetEnablePrivateIf(pThis);
1633	pThis->aCSR[0] &= ~0x0004; /* clear STOP bit */
1634	pThis->aCSR[0] \|= 0x0002; /* STRT */
1635	pcnetPollTimerStart(pThis); /* start timer if it was stopped */
1636	}
1637
1638	/**
1639	* Stop RX/TX operation.
1640	*/
1641	static void pcnetStop(PCNetState *pThis)
1642	{
1643	Log(("#%d pcnetStop:\n", PCNET_INST_NR));
1644	pThis->aCSR[0] &= ~0x7feb;
1645	pThis->aCSR[0] \|= 0x0014;
1646	pThis->aCSR[4] &= ~0x02c2;
1647	pThis->aCSR[5] &= ~0x0011;
1648	pcnetEnablePrivateIf(pThis);
1649	pcnetPollTimer(pThis);
1650	}
1651
1652	#ifdef IN_RING3
1653	static DECLCALLBACK(void) pcnetWakeupReceive(PPDMDEVINS pDevIns)
1654	{
1655	PCNetState pThis = PDMINS_2_DATA(pDevIns, PCNetState );
1656	STAM_COUNTER_INC(&pThis->StatRxOverflowWakeup);
1657	if (pThis->hEventOutOfRxSpace != NIL_RTSEMEVENT)
1658	RTSemEventSignal(pThis->hEventOutOfRxSpace);
1659	}
1660
1661	static DECLCALLBACK(bool) pcnetCanRxQueueConsumer(PPDMDEVINS pDevIns, PPDMQUEUEITEMCORE pItem)
1662	{
1663	pcnetWakeupReceive(pDevIns);
1664	return true;
1665	}
1666	#endif /* IN_RING3 */
1667
1668
1669	/**
1670	* Poll Receive Descriptor Table Entry and cache the results in the appropriate registers.
1671	* Note: Once a descriptor belongs to the network card (this driver), it cannot be changed
1672	* by the host (the guest driver) anymore. Well, it could but the results are undefined by
1673	* definition.
1674	* @param fSkipCurrent if true, don't scan the current RDTE.
1675	*/
1676	static void pcnetRdtePoll(PCNetState *pThis, bool fSkipCurrent=false)
1677	{
1678	STAM_PROFILE_ADV_START(&pThis->CTXSUFF(StatRdtePoll), a);
1679	/* assume lack of a next receive descriptor */
1680	CSR_NRST(pThis) = 0;
1681
1682	if (RT_LIKELY(pThis->GCRDRA))
1683	{
1684	/*
1685	* The current receive message descriptor.
1686	*/
1687	RMD rmd;
1688	int i = CSR_RCVRC(pThis);
1689	RTGCPHYS32 addr;
1690
1691	if (i < 1)
1692	i = CSR_RCVRL(pThis);
1693
1694	if (!fSkipCurrent)
1695	{
1696	addr = pcnetRdraAddr(pThis, i);
1697	CSR_CRDA(pThis) = CSR_CRBA(pThis) = 0;
1698	CSR_CRBC(pThis) = CSR_CRST(pThis) = 0;
1699	if (!pcnetRmdLoad(pThis, &rmd, PHYSADDR(pThis, addr), true))
1700	{
1701	STAM_PROFILE_ADV_STOP(&pThis->CTXSUFF(StatRdtePoll), a);
1702	return;
1703	}
1704	if (RT_LIKELY(!IS_RMD_BAD(rmd)))
1705	{
1706	CSR_CRDA(pThis) = addr; /* Receive Descriptor Address */
1707	CSR_CRBA(pThis) = rmd.rmd0.rbadr; /* Receive Buffer Address */
1708	CSR_CRBC(pThis) = rmd.rmd1.bcnt; /* Receive Byte Count */
1709	CSR_CRST(pThis) = ((uint32_t )&rmd)[1] >> 16; / Receive Status */
1710	if (pThis->fMaybeOutOfSpace)
1711	{
1712	#ifdef IN_RING3
1713	pcnetWakeupReceive(PCNETSTATE_2_DEVINS(pThis));
1714	#else
1715	PPDMQUEUEITEMCORE pItem = PDMQueueAlloc(pThis->CTX_SUFF(pCanRxQueue));
1716	if (pItem)
1717	PDMQueueInsert(pThis->CTX_SUFF(pCanRxQueue), pItem);
1718	#endif
1719	}
1720	}
1721	else
1722	{
1723	STAM_PROFILE_ADV_STOP(&pThis->CTXSUFF(StatRdtePoll), a);
1724	/* This is not problematic since we don't own the descriptor
1725	* We actually do own it, otherwise pcnetRmdLoad would have returned false.
1726	* Don't flood the release log with errors.
1727	*/
1728	if (++pThis->uCntBadRMD < 50)
1729	LogRel(("PCNet#%d: BAD RMD ENTRIES AT %#010x (i=%d)\n",
1730	PCNET_INST_NR, addr, i));
1731	return;
1732	}
1733	}
1734
1735	/*
1736	* The next descriptor.
1737	*/
1738	if (--i < 1)
1739	i = CSR_RCVRL(pThis);
1740	addr = pcnetRdraAddr(pThis, i);
1741	CSR_NRDA(pThis) = CSR_NRBA(pThis) = 0;
1742	CSR_NRBC(pThis) = 0;
1743	if (!pcnetRmdLoad(pThis, &rmd, PHYSADDR(pThis, addr), true))
1744	{
1745	STAM_PROFILE_ADV_STOP(&pThis->CTXSUFF(StatRdtePoll), a);
1746	return;
1747	}
1748	if (RT_LIKELY(!IS_RMD_BAD(rmd)))
1749	{
1750	CSR_NRDA(pThis) = addr; /* Receive Descriptor Address */
1751	CSR_NRBA(pThis) = rmd.rmd0.rbadr; /* Receive Buffer Address */
1752	CSR_NRBC(pThis) = rmd.rmd1.bcnt; /* Receive Byte Count */
1753	CSR_NRST(pThis) = ((uint32_t )&rmd)[1] >> 16; / Receive Status */
1754	}
1755	else
1756	{
1757	STAM_PROFILE_ADV_STOP(&pThis->CTXSUFF(StatRdtePoll), a);
1758	/* This is not problematic since we don't own the descriptor
1759	* We actually do own it, otherwise pcnetRmdLoad would have returned false.
1760	* Don't flood the release log with errors.
1761	*/
1762	if (++pThis->uCntBadRMD < 50)
1763	LogRel(("PCNet#%d: BAD RMD ENTRIES + AT %#010x (i=%d)\n",
1764	PCNET_INST_NR, addr, i));
1765	return;
1766	}
1767
1768	/**
1769	* @todo NNRD
1770	*/
1771	}
1772	else
1773	{
1774	CSR_CRDA(pThis) = CSR_CRBA(pThis) = CSR_NRDA(pThis) = CSR_NRBA(pThis) = 0;
1775	CSR_CRBC(pThis) = CSR_NRBC(pThis) = CSR_CRST(pThis) = 0;
1776	}
1777	STAM_PROFILE_ADV_STOP(&pThis->CTXSUFF(StatRdtePoll), a);
1778	}
1779
1780	/**
1781	* Poll Transmit Descriptor Table Entry
1782	* @return true if transmit descriptors available
1783	*/
1784	static int pcnetTdtePoll(PCNetState pThis, TMD tmd)
1785	{
1786	STAM_PROFILE_ADV_START(&pThis->CTXSUFF(StatTdtePoll), a);
1787	if (RT_LIKELY(pThis->GCTDRA))
1788	{
1789	RTGCPHYS32 cxda = pcnetTdraAddr(pThis, CSR_XMTRC(pThis));
1790
1791	if (!pcnetTmdLoad(pThis, tmd, PHYSADDR(pThis, cxda), true))
1792	{
1793	STAM_PROFILE_ADV_STOP(&pThis->CTXSUFF(StatTdtePoll), a);
1794	return 0;
1795	}
1796
1797	if (RT_UNLIKELY(tmd->tmd1.ones != 15))
1798	{
1799	STAM_PROFILE_ADV_STOP(&pThis->CTXSUFF(StatTdtePoll), a);
1800	LogRel(("PCNet#%d: BAD TMD XDA=%#010x\n",
1801	PCNET_INST_NR, PHYSADDR(pThis, cxda)));
1802	return 0;
1803	}
1804
1805	/* previous xmit descriptor */
1806	CSR_PXDA(pThis) = CSR_CXDA(pThis);
1807	CSR_PXBC(pThis) = CSR_CXBC(pThis);
1808	CSR_PXST(pThis) = CSR_CXST(pThis);
1809
1810	/* set current trasmit decriptor. */
1811	CSR_CXDA(pThis) = cxda;
1812	CSR_CXBC(pThis) = tmd->tmd1.bcnt;
1813	CSR_CXST(pThis) = ((uint32_t *)tmd)[1] >> 16;
1814	STAM_PROFILE_ADV_STOP(&pThis->CTXSUFF(StatTdtePoll), a);
1815	return CARD_IS_OWNER(CSR_CXST(pThis));
1816	}
1817	else
1818	{
1819	/** @todo consistency with previous receive descriptor */
1820	CSR_CXDA(pThis) = 0;
1821	CSR_CXBC(pThis) = CSR_CXST(pThis) = 0;
1822	STAM_PROFILE_ADV_STOP(&pThis->CTXSUFF(StatTdtePoll), a);
1823	return 0;
1824	}
1825	}
1826
1827
1828	#ifdef IN_RING3
1829
1830	/**
1831	* Write data into guest receive buffers.
1832	*/
1833	static void pcnetReceiveNoSync(PCNetState pThis, const uint8_t buf, size_t cbToRecv)
1834	{
1835	PPDMDEVINS pDevIns = PCNETSTATE_2_DEVINS(pThis);
1836	int is_padr = 0, is_bcast = 0, is_ladr = 0;
1837	unsigned iRxDesc;
1838	int cbPacket;
1839
1840	if (RT_UNLIKELY(CSR_DRX(pThis) \|\| CSR_STOP(pThis) \|\| CSR_SPND(pThis) \|\| !cbToRecv))
1841	return;
1842
1843	/*
1844	* Drop packets if the VM is not running yet/anymore.
1845	*/
1846	VMSTATE enmVMState = PDMDevHlpVMState(pDevIns);
1847	if ( enmVMState != VMSTATE_RUNNING
1848	&& enmVMState != VMSTATE_RUNNING_LS)
1849	return;
1850
1851	/*
1852	* Drop packets if the cable is not connected
1853	*/
1854	if (!pcnetIsLinkUp(pThis))
1855	return;
1856
1857	Log(("#%d pcnetReceiveNoSync: size=%d\n", PCNET_INST_NR, cbToRecv));
1858
1859	/*
1860	* Perform address matching.
1861	*/
1862	if ( CSR_PROM(pThis)
1863	\|\| (is_padr = padr_match(pThis, buf, cbToRecv))
1864	\|\| (is_bcast = padr_bcast(pThis, buf, cbToRecv))
1865	\|\| (is_ladr = ladr_match(pThis, buf, cbToRecv)))
1866	{
1867	if (HOST_IS_OWNER(CSR_CRST(pThis)))
1868	pcnetRdtePoll(pThis);
1869	if (RT_UNLIKELY(HOST_IS_OWNER(CSR_CRST(pThis))))
1870	{
1871	/* Not owned by controller. This should not be possible as
1872	* we already called pcnetCanReceive(). */
1873	LogRel(("PCNet#%d: no buffer: RCVRC=%d\n",
1874	PCNET_INST_NR, CSR_RCVRC(pThis)));
1875	/* Dump the status of all RX descriptors */
1876	const unsigned cb = 1 << pThis->iLog2DescSize;
1877	RTGCPHYS32 GCPhys = pThis->GCRDRA;
1878	iRxDesc = CSR_RCVRL(pThis);
1879	while (iRxDesc-- > 0)
1880	{
1881	RMD rmd;
1882	pcnetRmdLoad(pThis, &rmd, PHYSADDR(pThis, GCPhys), false);
1883	LogRel((" %#010x\n", rmd.rmd1));
1884	GCPhys += cb;
1885	}
1886	pThis->aCSR[0] \|= 0x1000; /* Set MISS flag */
1887	CSR_MISSC(pThis)++;
1888	}
1889	else
1890	{
1891	uint8_t *src = &pThis->abRecvBuf[8];
1892	RTGCPHYS32 crda = CSR_CRDA(pThis);
1893	RTGCPHYS32 next_crda;
1894	RMD rmd, next_rmd;
1895
1896	memcpy(src, buf, cbToRecv);
1897	if (!CSR_ASTRP_RCV(pThis))
1898	{
1899	uint32_t fcs = ~0;
1900	uint8_t *p = src;
1901
1902	while (cbToRecv < 60)
1903	src[cbToRecv++] = 0;
1904	while (p != &src[cbToRecv])
1905	CRC(fcs, *p++);
1906	((uint32_t *)&src[cbToRecv])[0] = htonl(fcs);
1907	/* FCS at end of packet */
1908	}
1909	cbToRecv += 4;
1910	cbPacket = (int)cbToRecv; Assert((size_t)cbPacket == cbToRecv);
1911
1912	#ifdef PCNET_DEBUG_MATCH
1913	PRINT_PKTHDR(buf);
1914	#endif
1915
1916	pcnetRmdLoad(pThis, &rmd, PHYSADDR(pThis, crda), false);
1917	/if (!CSR_LAPPEN(pThis))/
1918	rmd.rmd1.stp = 1;
1919
1920	size_t cbBuf = RT_MIN(4096 - (size_t)rmd.rmd1.bcnt, cbToRecv);
1921	RTGCPHYS32 rbadr = PHYSADDR(pThis, rmd.rmd0.rbadr);
1922
1923	/* save the old value to check if it was changed as long as we didn't
1924	* hold the critical section */
1925	iRxDesc = CSR_RCVRC(pThis);
1926
1927	/* We have to leave the critical section here or we risk deadlocking
1928	* with EMT when the write is to an unallocated page or has an access
1929	* handler associated with it.
1930	*
1931	* This shouldn't be a problem because:
1932	* - any modification to the RX descriptor by the driver is
1933	* forbidden as long as it is owned by the device
1934	* - we don't cache any register state beyond this point
1935	*/
1936	PDMCritSectLeave(&pThis->CritSect);
1937	PDMDevHlpPhysWrite(pDevIns, rbadr, src, cbBuf);
1938	int rc = PDMCritSectEnter(&pThis->CritSect, VERR_SEM_BUSY);
1939	AssertReleaseRC(rc);
1940
1941	/* RX disabled in the meantime? If so, abort RX. */
1942	if (RT_UNLIKELY(CSR_DRX(pThis) \|\| CSR_STOP(pThis) \|\| CSR_SPND(pThis)))
1943	return;
1944
1945	/* Was the register modified in the meantime? If so, don't touch the
1946	* register but still update the RX descriptor. */
1947	if (RT_LIKELY(iRxDesc == CSR_RCVRC(pThis)))
1948	{
1949	if (iRxDesc-- < 2)
1950	iRxDesc = CSR_RCVRL(pThis);
1951	CSR_RCVRC(pThis) = iRxDesc;
1952	}
1953	else
1954	iRxDesc = CSR_RCVRC(pThis);
1955
1956	src += cbBuf;
1957	cbToRecv -= cbBuf;
1958
1959	while (cbToRecv > 0)
1960	{
1961	/* Read the entire next descriptor as we're likely to need it. */
1962	next_crda = pcnetRdraAddr(pThis, iRxDesc);
1963
1964	/* Check next descriptor's own bit. If we don't own it, we have
1965	* to quit and write error status into the last descriptor we own.
1966	*/
1967	if (!pcnetRmdLoad(pThis, &next_rmd, PHYSADDR(pThis, next_crda), true))
1968	break;
1969
1970	/* Write back current descriptor, clear the own bit. */
1971	pcnetRmdStorePassHost(pThis, &rmd, PHYSADDR(pThis, crda));
1972
1973	/* Switch to the next descriptor */
1974	crda = next_crda;
1975	rmd = next_rmd;
1976
1977	cbBuf = RT_MIN(4096 - (size_t)rmd.rmd1.bcnt, cbToRecv);
1978	RTGCPHYS32 rbadr2 = PHYSADDR(pThis, rmd.rmd0.rbadr);
1979
1980	/* We have to leave the critical section here or we risk deadlocking
1981	* with EMT when the write is to an unallocated page or has an access
1982	* handler associated with it. See above for additional comments. */
1983	PDMCritSectLeave(&pThis->CritSect);
1984	PDMDevHlpPhysWrite(pDevIns, rbadr2, src, cbBuf);
1985	rc = PDMCritSectEnter(&pThis->CritSect, VERR_SEM_BUSY);
1986	AssertReleaseRC(rc);
1987
1988	/* RX disabled in the meantime? If so, abort RX. */
1989	if (RT_UNLIKELY(CSR_DRX(pThis) \|\| CSR_STOP(pThis) \|\| CSR_SPND(pThis)))
1990	return;
1991
1992	/* Was the register modified in the meantime? If so, don't touch the
1993	* register but still update the RX descriptor. */
1994	if (RT_LIKELY(iRxDesc == CSR_RCVRC(pThis)))
1995	{
1996	if (iRxDesc-- < 2)
1997	iRxDesc = CSR_RCVRL(pThis);
1998	CSR_RCVRC(pThis) = iRxDesc;
1999	}
2000	else
2001	iRxDesc = CSR_RCVRC(pThis);
2002
2003	src += cbBuf;
2004	cbToRecv -= cbBuf;
2005	}
2006
2007	if (RT_LIKELY(cbToRecv == 0))
2008	{
2009	rmd.rmd1.enp = 1;
2010	rmd.rmd1.pam = !CSR_PROM(pThis) && is_padr;
2011	rmd.rmd1.lafm = !CSR_PROM(pThis) && is_ladr;
2012	rmd.rmd1.bam = !CSR_PROM(pThis) && is_bcast;
2013	rmd.rmd2.mcnt = cbPacket;
2014
2015	STAM_REL_COUNTER_ADD(&pThis->StatReceiveBytes, cbPacket);
2016	}
2017	else
2018	{
2019	Log(("#%d: Overflow by %ubytes\n", PCNET_INST_NR, cbToRecv));
2020	rmd.rmd1.oflo = 1;
2021	rmd.rmd1.buff = 1;
2022	rmd.rmd1.err = 1;
2023	}
2024
2025	/* write back, clear the own bit */
2026	pcnetRmdStorePassHost(pThis, &rmd, PHYSADDR(pThis, crda));
2027
2028	pThis->aCSR[0] \|= 0x0400;
2029
2030	Log(("#%d RCVRC=%d CRDA=%#010x\n", PCNET_INST_NR,
2031	CSR_RCVRC(pThis), PHYSADDR(pThis, CSR_CRDA(pThis))));
2032	#ifdef PCNET_DEBUG_RMD
2033	PRINT_RMD(&rmd);
2034	#endif
2035
2036	/* guest driver is owner: force repoll of current and next RDTEs */
2037	CSR_CRST(pThis) = 0;
2038	}
2039	}
2040
2041	/* see description of TXDPOLL:
2042	* ``transmit polling will take place following receive activities'' */
2043	pcnetPollRxTx(pThis);
2044	pcnetUpdateIrq(pThis);
2045	}
2046
2047
2048	/**
2049	* Transmit queue consumer
2050	* This is just a very simple way of delaying sending to R3.
2051	*
2052	* @returns Success indicator.
2053	* If false the item will not be removed and the flushing will stop.
2054	* @param pDevIns The device instance.
2055	* @param pItem The item to consume. Upon return this item will be freed.
2056	*/
2057	static DECLCALLBACK(bool) pcnetXmitQueueConsumer(PPDMDEVINS pDevIns, PPDMQUEUEITEMCORE pItem)
2058	{
2059	PCNetState pThis = PDMINS_2_DATA(pDevIns, PCNetState );
2060	NOREF(pItem);
2061
2062	/* Clear counter .*/
2063	#ifndef VBOX_WITH_TX_THREAD_IN_NET_DEVICES
2064	int rc = PDMCritSectEnter(&pThis->CritSect, VERR_SEM_BUSY);
2065	AssertReleaseRC(rc);
2066
2067	pcnetAsyncTransmit(pThis, false /fOnWorkerThread/);
2068
2069	PDMCritSectLeave(&pThis->CritSect);
2070	#else
2071	int rc = RTSemEventSignal(pThis->hSendEventSem);
2072	AssertRC(rc);
2073	#endif
2074	return true;
2075	}
2076
2077
2078	/**
2079	* Allocates a scatter/gather buffer for a transfer.
2080	*
2081	* @returns See PPDMINETWORKUP::pfnAllocBuf.
2082	* @param pThis The device instance.
2083	* @param cbMin The minimum buffer size.
2084	* @param fLoopback Set if we're in loopback mode.
2085	* @param pSgLoop Pointer to stack storage for the loopback SG.
2086	* @param ppSgBuf Where to return the SG buffer descriptor on success.
2087	* Always set.
2088	*/
2089	DECLINLINE(int) pcnetXmitAllocBuf(PCNetState *pThis, size_t cbMin, bool fLoopback,
2090	PPDMSCATTERGATHER pSgLoop, PPPDMSCATTERGATHER ppSgBuf)
2091	{
2092	int rc;
2093
2094	if (RT_UNLIKELY(fLoopback)) /* hope that loopback mode is rare */
2095	{
2096	pSgLoop->fFlags = PDMSCATTERGATHER_FLAGS_MAGIC \| PDMSCATTERGATHER_FLAGS_OWNER_1;
2097	pSgLoop->cbUsed = 0;
2098	pSgLoop->cbAvailable = sizeof(pThis->abLoopBuf);
2099	pSgLoop->pvAllocator = pThis;
2100	pSgLoop->pvUser = NULL;
2101	pSgLoop->cSegs = 1;
2102	pSgLoop->aSegs[0].cbSeg = sizeof(pThis->abLoopBuf);
2103	pSgLoop->aSegs[0].pvSeg = pThis->abLoopBuf;
2104	*ppSgBuf = pSgLoop;
2105	rc = VINF_SUCCESS;
2106	}
2107	else
2108	{
2109	PPDMINETWORKUP pDrv = pThis->pDrvR3;
2110	if (RT_LIKELY(pDrv))
2111	{
2112	rc = pDrv->pfnAllocBuf(pDrv, cbMin, ppSgBuf);
2113	AssertMsg(rc == VINF_SUCCESS \|\| rc == VERR_TRY_AGAIN \|\| rc == VERR_NET_DOWN \|\| rc == VERR_NO_MEMORY, ("%Rrc\n", rc));
2114	if (RT_FAILURE(rc))
2115	*ppSgBuf = NULL;
2116	}
2117	else
2118	{
2119	rc = VERR_NET_DOWN;
2120	*ppSgBuf = NULL;
2121	}
2122	}
2123	return rc;
2124	}
2125
2126
2127	/**
2128	* Frees an unsent buffer.
2129	*
2130	* @param pThis The device instance.
2131	* @param fLoopback Set if we're in loopback mode.
2132	* @param pSgBuf The SG to free. Can be NULL.
2133	*/
2134	DECLINLINE(void) pcnetXmitFreeBuf(PCNetState *pThis, bool fLoopback, PPDMSCATTERGATHER pSgBuf)
2135	{
2136	if (pSgBuf)
2137	{
2138	if (RT_UNLIKELY(fLoopback))
2139	pSgBuf->pvAllocator = NULL;
2140	else
2141	{
2142	PPDMINETWORKUP pDrv = pThis->pDrvR3;
2143	if (RT_LIKELY(pDrv))
2144	pDrv->pfnFreeBuf(pDrv, pSgBuf);
2145	}
2146	}
2147	}
2148
2149
2150	/**
2151	* Sends the scatter/gather buffer.
2152	*
2153	* Wrapper around PDMINETWORKUP::pfnSendBuf, so check it out for the fine print.
2154	*
2155	* @returns See PDMINETWORKUP::pfnSendBuf.
2156	* @param pThis The device instance.
2157	* @param fLoopback Set if we're in loopback mode.
2158	* @param pSgBuf The SG to send.
2159	* @param fOnWorkerThread Set if we're being called on a work thread. Clear
2160	* if an EMT.
2161	*/
2162	DECLINLINE(int) pcnetXmitSendBuf(PCNetState *pThis, bool fLoopback, PPDMSCATTERGATHER pSgBuf, bool fOnWorkerThread)
2163	{
2164	int rc;
2165	STAM_REL_COUNTER_ADD(&pThis->StatTransmitBytes, pSgBuf->cbUsed);
2166	if (RT_UNLIKELY(fLoopback)) /* hope that loopback mode is rare */
2167	{
2168	Assert(pSgBuf->pvAllocator == (void *)pThis);
2169	pThis->Led.Asserted.s.fReading = pThis->Led.Actual.s.fReading = 1;
2170	if (HOST_IS_OWNER(CSR_CRST(pThis)))
2171	pcnetRdtePoll(pThis);
2172
2173	pcnetReceiveNoSync(pThis, pThis->abLoopBuf, pSgBuf->cbUsed);
2174	pThis->Led.Actual.s.fReading = 0;
2175	rc = VINF_SUCCESS;
2176	}
2177	else
2178	{
2179	/** @todo We used to leave the critsect here, not sure if that's necessary any
2180	* longer. If we could avoid that we could cache a bit more info in
2181	* the loop and make it part of the driver<->device contract, saving
2182	* critsect mess down in DrvIntNet. */
2183	STAM_PROFILE_START(&pThis->StatTransmitSend, a);
2184	if (pSgBuf->cbUsed > 70) /* unqualified guess */
2185	pThis->Led.Asserted.s.fWriting = pThis->Led.Actual.s.fWriting = 1;
2186
2187	PPDMINETWORKUP pDrv = pThis->pDrvR3;
2188	if (RT_LIKELY(pDrv))
2189	{
2190	rc = pDrv->pfnSendBuf(pDrv, pSgBuf, fOnWorkerThread);
2191	AssertMsg(rc == VINF_SUCCESS \|\| rc == VERR_NET_DOWN \|\| rc == VERR_NET_NO_BUFFER_SPACE, ("%Rrc\n", rc));
2192	}
2193	else
2194	rc = VERR_NET_DOWN;
2195
2196	pThis->Led.Actual.s.fWriting = 0;
2197	STAM_PROFILE_STOP(&pThis->StatTransmitSend, a);
2198	}
2199	return rc;
2200	}
2201
2202
2203	/**
2204	* pcnetXmitRead1st worker that handles the unlikely + slower segmented code
2205	* path.
2206	*/
2207	static void pcnetXmitRead1stSlow(PCNetState *pThis, RTGCPHYS32 GCPhysFrame, unsigned cbFrame,
2208	PPDMSCATTERGATHER pSgBuf)
2209	{
2210	AssertFailed(); /* This path is not suppost to be taken atm */
2211
2212	pSgBuf->cbUsed = cbFrame;
2213	for (uint32_t iSeg = 0; ; iSeg++)
2214	{
2215	Assert(iSeg < pSgBuf->cSegs);
2216	size_t cbRead = RT_MIN(cbFrame, pSgBuf->aSegs[iSeg].cbSeg);
2217	PDMDevHlpPhysRead(pThis->CTX_SUFF(pDevIns), GCPhysFrame, pSgBuf->aSegs[iSeg].pvSeg, cbRead);
2218	cbFrame -= cbRead;
2219	if (!cbFrame)
2220	return;
2221	GCPhysFrame += cbRead;
2222	}
2223	}
2224
2225
2226	/**
2227	* pcnetXmitSgReadMore worker that handles the unlikely + slower segmented code
2228	* path.
2229	*/
2230	static void pcnetXmitReadMoreSlow(PCNetState *pThis, RTGCPHYS32 GCPhysFrame, unsigned cbFrame,
2231	PPDMSCATTERGATHER pSgBuf)
2232	{
2233	AssertFailed(); /* This path is not suppost to be taken atm */
2234
2235	/* Find the segment which we'll put the next byte into. */
2236	size_t off = pSgBuf->cbUsed;
2237	size_t offSeg = 0;
2238	uint32_t iSeg = 0;
2239	while (offSeg + pSgBuf->aSegs[iSeg].cbSeg <= off)
2240	{
2241	offSeg += pSgBuf->aSegs[iSeg].cbSeg;
2242	iSeg++;
2243	Assert(iSeg < pSgBuf->cSegs);
2244	}
2245
2246	/* Commit before we start copying so we can decrement cbFrame. */
2247	pSgBuf->cbUsed = off + cbFrame;
2248
2249	/* Deal with the first segment if we at an offset into it. */
2250	if (off != offSeg)
2251	{
2252	size_t offIntoSeg = off - offSeg;
2253	size_t cbRead = RT_MIN(pSgBuf->aSegs[iSeg].cbSeg - offIntoSeg, cbFrame);
2254	PDMDevHlpPhysRead(pThis->CTX_SUFF(pDevIns), GCPhysFrame,
2255	(uint8_t *)pSgBuf->aSegs[iSeg].pvSeg + offIntoSeg, cbRead);
2256	cbFrame -= cbRead;
2257	if (!cbFrame)
2258	return;
2259	GCPhysFrame += cbRead;
2260	iSeg++;
2261	}
2262
2263	/* For the remainder, we've got whole segments. */
2264	for (;; iSeg++)
2265	{
2266	Assert(iSeg < pSgBuf->cSegs);
2267
2268	size_t cbRead = RT_MIN(pSgBuf->aSegs[iSeg].cbSeg, cbFrame);
2269	PDMDevHlpPhysRead(pThis->CTX_SUFF(pDevIns), GCPhysFrame, pSgBuf->aSegs[iSeg].pvSeg, cbRead);
2270	cbFrame -= cbRead;
2271	if (!cbFrame)
2272	return;
2273	GCPhysFrame += cbFrame;
2274	}
2275	}
2276
2277
2278	/**
2279	* Reads the first part of a frame into the scatter gather buffer.
2280	*/
2281	DECLINLINE(void) pcnetXmitRead1st(PCNetState *pThis, RTGCPHYS32 GCPhysFrame, const unsigned cbFrame,
2282	PPDMSCATTERGATHER pSgBuf)
2283	{
2284	Assert(PDMCritSectIsOwner(&pThis->CritSect));
2285	Assert(pSgBuf->cbAvailable >= cbFrame);
2286
2287	if (RT_LIKELY(pSgBuf->aSegs[0].cbSeg >= cbFrame)) /* justification: all drivers returns a single segment atm. */
2288	{
2289	pSgBuf->cbUsed = cbFrame;
2290	PDMDevHlpPhysRead(pThis->CTX_SUFF(pDevIns), GCPhysFrame, pSgBuf->aSegs[0].pvSeg, cbFrame);
2291	}
2292	else
2293	pcnetXmitRead1stSlow(pThis, GCPhysFrame, cbFrame, pSgBuf);
2294	}
2295
2296	/**
2297	* Reads more into the current frame.
2298	*/
2299	DECLINLINE(void) pcnetXmitReadMore(PCNetState *pThis, RTGCPHYS32 GCPhysFrame, const unsigned cbFrame,
2300	PPDMSCATTERGATHER pSgBuf)
2301	{
2302	size_t off = pSgBuf->cbUsed;
2303	Assert(pSgBuf->cbAvailable >= cbFrame + off);
2304
2305	if (RT_LIKELY(pSgBuf->aSegs[0].cbSeg >= cbFrame + off))
2306	{
2307	pSgBuf->cbUsed = cbFrame + off;
2308	PDMDevHlpPhysRead(pThis->CTX_SUFF(pDevIns), GCPhysFrame,
2309	(uint8_t *)pSgBuf->aSegs[0].pvSeg + off, cbFrame);
2310	}
2311	else
2312	pcnetXmitReadMoreSlow(pThis, GCPhysFrame, cbFrame, pSgBuf);
2313	}
2314
2315
2316	/**
2317	* Fails a TMD with a link down error.
2318	*/
2319	static void pcnetXmitFailTMDLinkDown(PCNetState pThis, TMD pTmd)
2320	{
2321	/* make carrier error - hope this is correct. */
2322	pThis->cLinkDownReported++;
2323	pTmd->tmd2.lcar = pTmd->tmd1.err = 1;
2324	pThis->aCSR[0] \|= RT_BIT(15) \| RT_BIT(13); /* ERR \| CERR */
2325	pThis->Led.Asserted.s.fError = pThis->Led.Actual.s.fError = 1;
2326	Log(("#%d pcnetTransmit: Signaling send error. swstyle=%#x\n",
2327	PCNET_INST_NR, pThis->aBCR[BCR_SWS]));
2328	}
2329
2330	/**
2331	* Fails a TMD with a generic error.
2332	*/
2333	static void pcnetXmitFailTMDGeneric(PCNetState pThis, TMD pTmd)
2334	{
2335	/* make carrier error - hope this is correct. */
2336	pTmd->tmd2.lcar = pTmd->tmd1.err = 1;
2337	pThis->aCSR[0] \|= RT_BIT(15) \| RT_BIT(13); /* ERR \| CERR */
2338	pThis->Led.Asserted.s.fError = pThis->Led.Actual.s.fError = 1;
2339	Log(("#%d pcnetTransmit: Signaling send error. swstyle=%#x\n",
2340	PCNET_INST_NR, pThis->aBCR[BCR_SWS]));
2341	}
2342
2343
2344	/**
2345	* Flushes queued frames.
2346	*/
2347	DECLINLINE(void) pcnetXmitFlushFrames(PCNetState *pThis)
2348	{
2349	pcnetXmitQueueConsumer(pThis->CTX_SUFF(pDevIns), NULL);
2350	}
2351
2352	#endif /* IN_RING3 */
2353
2354
2355
2356	/**
2357	* Try to transmit frames
2358	*/
2359	static void pcnetTransmit(PCNetState *pThis)
2360	{
2361	if (RT_UNLIKELY(!CSR_TXON(pThis)))
2362	{
2363	pThis->aCSR[0] &= ~0x0008; /* Clear TDMD */
2364	return;
2365	}
2366
2367	/*
2368	* Check the current transmit descriptors.
2369	*/
2370	TMD tmd;
2371	if (!pcnetTdtePoll(pThis, &tmd))
2372	return;
2373
2374	/*
2375	* Clear TDMD.
2376	*/
2377	pThis->aCSR[0] &= ~0x0008;
2378
2379	/*
2380	* If we're in Ring-3 we should flush the queue now, in GC/R0 we'll queue a flush job.
2381	*/
2382	#ifdef IN_RING3
2383	pcnetXmitFlushFrames(pThis);
2384	#else
2385	PPDMQUEUEITEMCORE pItem = PDMQueueAlloc(pThis->CTX_SUFF(pXmitQueue));
2386	if (RT_UNLIKELY(pItem))
2387	PDMQueueInsert(pThis->CTX_SUFF(pXmitQueue), pItem);
2388	#endif
2389	}
2390
2391	#ifdef IN_RING3
2392
2393	/**
2394	* Actually try transmit frames.
2395	*
2396	* @threads TX or EMT.
2397	*/
2398	static int pcnetAsyncTransmit(PCNetState *pThis, bool fOnWorkerThread)
2399	{
2400	Assert(PDMCritSectIsOwner(&pThis->CritSect));
2401
2402	/*
2403	* Just cleard transmit demand if the transmitter is off.
2404	*/
2405	if (RT_UNLIKELY(!CSR_TXON(pThis)))
2406	{
2407	pThis->aCSR[0] &= ~0x0008; /* Clear TDMD */
2408	return VINF_SUCCESS;
2409	}
2410
2411	/*
2412	* Iterate the transmit descriptors.
2413	*/
2414	int rc;
2415	unsigned cFlushIrq = 0;
2416	STAM_PROFILE_ADV_START(&pThis->StatTransmit, a);
2417	do
2418	{
2419	#ifdef VBOX_WITH_STATISTICS
2420	unsigned cBuffers = 1;
2421	#endif
2422	TMD tmd;
2423	if (!pcnetTdtePoll(pThis, &tmd))
2424	break;
2425
2426	/* Don't continue sending packets when the link is down. */
2427	if (RT_UNLIKELY( !pcnetIsLinkUp(pThis)
2428	&& pThis->cLinkDownReported > PCNET_MAX_LINKDOWN_REPORTED)
2429	)
2430	break;
2431
2432	#ifdef PCNET_DEBUG_TMD
2433	Log2(("#%d TMDLOAD %#010x\n", PCNET_INST_NR, PHYSADDR(pThis, CSR_CXDA(pThis))));
2434	PRINT_TMD(&tmd);
2435	#endif
2436	bool const fLoopback = CSR_LOOP(pThis);
2437	PDMSCATTERGATHER SgLoop;
2438	PPDMSCATTERGATHER pSgBuf;
2439
2440	/*
2441	* The typical case - a complete packet.
2442	*/
2443	if (tmd.tmd1.stp && tmd.tmd1.enp)
2444	{
2445	const unsigned cb = 4096 - tmd.tmd1.bcnt;
2446	Log(("#%d pcnetAsyncTransmit: stp&enp: cb=%d xmtrc=%#x\n", PCNET_INST_NR, cb, CSR_XMTRC(pThis)));
2447	STAM_COUNTER_INC(&pThis->StatTransmitCase1);
2448
2449	if (RT_LIKELY(pcnetIsLinkUp(pThis) \|\| fLoopback))
2450	{
2451	/* From the manual: ``A zero length buffer is acceptable as
2452	* long as it is not the last buffer in a chain (STP = 0 and
2453	* ENP = 1).'' That means that the first buffer might have a
2454	* zero length if it is not the last one in the chain. */
2455	if (RT_LIKELY(cb <= MAX_FRAME))
2456	{
2457	rc = pcnetXmitAllocBuf(pThis, cb, fLoopback, &SgLoop, &pSgBuf);
2458	if (RT_SUCCESS(rc))
2459	{
2460	pcnetXmitRead1st(pThis, PHYSADDR(pThis, tmd.tmd0.tbadr), cb, pSgBuf);
2461	rc = pcnetXmitSendBuf(pThis, fLoopback, pSgBuf, fOnWorkerThread);
2462	}
2463	else if (rc == VERR_TRY_AGAIN)
2464	{
2465	STAM_PROFILE_ADV_STOP(&pThis->StatTransmit, a);
2466	return VINF_SUCCESS;
2467	}
2468	if (RT_FAILURE(rc))
2469	pcnetXmitFailTMDLinkDown(pThis, &tmd);
2470	}
2471	else if (cb == 4096)
2472	{
2473	/* The Windows NT4 pcnet driver sometimes marks the first
2474	* unused descriptor as owned by us. Ignore that (by
2475	* passing it back). Do not update the ring counter in this
2476	* case (otherwise that driver becomes even more confused,
2477	* which causes transmit to stall for about 10 seconds).
2478	* This is just a workaround, not a final solution. */
2479	/* r=frank: IMHO this is the correct implementation. The
2480	* manual says: ``If the OWN bit is set and the buffer
2481	* length is 0, the OWN bit will be cleared. In the C-LANCE
2482	* the buffer length of 0 is interpreted as a 4096-byte
2483	* buffer.'' */
2484	LogRel(("PCNet#%d: pcnetAsyncTransmit: illegal 4kb frame -> ignoring\n", PCNET_INST_NR));
2485	pcnetTmdStorePassHost(pThis, &tmd, PHYSADDR(pThis, CSR_CXDA(pThis)));
2486	break;
2487	}
2488	else
2489	{
2490	/* Signal error, as this violates the Ethernet specs. */
2491	/** @todo check if the correct error is generated. */
2492	LogRel(("PCNet#%d: pcnetAsyncTransmit: illegal 4kb frame -> signalling error\n", PCNET_INST_NR));
2493
2494	pcnetXmitFailTMDGeneric(pThis, &tmd);
2495	}
2496	}
2497	else
2498	pcnetXmitFailTMDLinkDown(pThis, &tmd);
2499
2500	/* Write back the TMD and pass it to the host (clear own bit). */
2501	pcnetTmdStorePassHost(pThis, &tmd, PHYSADDR(pThis, CSR_CXDA(pThis)));
2502
2503	/* advance the ring counter register */
2504	if (CSR_XMTRC(pThis) < 2)
2505	CSR_XMTRC(pThis) = CSR_XMTRL(pThis);
2506	else
2507	CSR_XMTRC(pThis)--;
2508	}
2509	else if (tmd.tmd1.stp)
2510	{
2511	STAM_COUNTER_INC(&pThis->StatTransmitCase2);
2512
2513	/*
2514	* Read TMDs until end-of-packet or tdte poll fails (underflow).
2515	*
2516	* We allocate a maximum sized buffer here since we do not wish to
2517	* waste time finding out how much space we actually need even if
2518	* we could reliably do that on SMP guests.
2519	*/
2520	unsigned cb = 4096 - tmd.tmd1.bcnt;
2521	rc = pcnetXmitAllocBuf(pThis, RT_MAX(MAX_FRAME, cb), fLoopback, &SgLoop, &pSgBuf);
2522	if (rc == VERR_TRY_AGAIN)
2523	{
2524	STAM_PROFILE_ADV_STOP(&pThis->StatTransmit, a);
2525	return VINF_SUCCESS;
2526	}
2527
2528	bool fDropFrame = RT_FAILURE(rc);
2529	if (!fDropFrame)
2530	pcnetXmitRead1st(pThis, PHYSADDR(pThis, tmd.tmd0.tbadr), cb, pSgBuf);
2531
2532	for (;;)
2533	{
2534	/*
2535	* Advance the ring counter register and check the next tmd.
2536	*/
2537	#ifdef LOG_ENABLED
2538	const uint32_t iStart = CSR_XMTRC(pThis);
2539	#endif
2540	const uint32_t GCPhysPrevTmd = PHYSADDR(pThis, CSR_CXDA(pThis));
2541	if (CSR_XMTRC(pThis) < 2)
2542	CSR_XMTRC(pThis) = CSR_XMTRL(pThis);
2543	else
2544	CSR_XMTRC(pThis)--;
2545
2546	TMD dummy;
2547	if (!pcnetTdtePoll(pThis, &dummy))
2548	{
2549	/*
2550	* Underflow!
2551	*/
2552	tmd.tmd2.buff = tmd.tmd2.uflo = tmd.tmd1.err = 1;
2553	pThis->aCSR[0] \|= 0x0200; /* set TINT */
2554	if (!CSR_DXSUFLO(pThis)) /* stop on xmit underflow */
2555	pThis->aCSR[0] &= ~0x0010; /* clear TXON */
2556	pcnetTmdStorePassHost(pThis, &tmd, GCPhysPrevTmd);
2557	AssertMsgFailed(("pcnetAsyncTransmit: Underflow!!!\n"));
2558	pcnetXmitFreeBuf(pThis, fLoopback, pSgBuf);
2559	break;
2560	}
2561
2562	/* release & save the previous tmd, pass it to the host */
2563	pcnetTmdStorePassHost(pThis, &tmd, GCPhysPrevTmd);
2564
2565	/*
2566	* The next tmd.
2567	*/
2568	#ifdef VBOX_WITH_STATISTICS
2569	cBuffers++;
2570	#endif
2571	pcnetTmdLoad(pThis, &tmd, PHYSADDR(pThis, CSR_CXDA(pThis)), false);
2572	cb = 4096 - tmd.tmd1.bcnt;
2573	if ( !fDropFrame
2574	&& pSgBuf->cbUsed + cb <= MAX_FRAME) /** @todo this used to be ... + cb < MAX_FRAME. */
2575	pcnetXmitReadMore(pThis, PHYSADDR(pThis, tmd.tmd0.tbadr), cb, pSgBuf);
2576	else
2577	{
2578	AssertMsg(fDropFrame, ("pcnetAsyncTransmit: Frame is too big!!! %d bytes\n", pSgBuf->cbUsed + cb));
2579	fDropFrame = true;
2580	}
2581
2582	/*
2583	* Done already?
2584	*/
2585	if (tmd.tmd1.enp)
2586	{
2587	Log(("#%d pcnetAsyncTransmit: stp: cb=%d xmtrc=%#x-%#x\n", PCNET_INST_NR,
2588	pSgBuf ? pSgBuf->cbUsed : 0, iStart, CSR_XMTRC(pThis)));
2589	if (!fDropFrame && (pcnetIsLinkUp(pThis) \|\| fLoopback))
2590	{
2591	rc = pcnetXmitSendBuf(pThis, fLoopback, pSgBuf, fOnWorkerThread);
2592	fDropFrame = RT_FAILURE(rc);
2593	}
2594	else
2595	pcnetXmitFreeBuf(pThis, fLoopback, pSgBuf);
2596	if (fDropFrame)
2597	pcnetXmitFailTMDLinkDown(pThis, &tmd);
2598
2599	/* Write back the TMD, pass it to the host */
2600	pcnetTmdStorePassHost(pThis, &tmd, PHYSADDR(pThis, CSR_CXDA(pThis)));
2601
2602	/* advance the ring counter register */
2603	if (CSR_XMTRC(pThis) < 2)
2604	CSR_XMTRC(pThis) = CSR_XMTRL(pThis);
2605	else
2606	CSR_XMTRC(pThis)--;
2607	break;
2608	}
2609	} /* the loop */
2610	}
2611	else
2612	{
2613	/*
2614	* We underflowed in a previous transfer, or the driver is giving us shit.
2615	* Simply stop the transmitting for now.
2616	*/
2617	/** @todo according to the specs we're supposed to clear the own bit and move on to the next one. */
2618	Log(("#%d pcnetAsyncTransmit: guest is giving us shit!\n", PCNET_INST_NR));
2619	break;
2620	}
2621	/* Update TDMD, TXSTRT and TINT. */
2622	pThis->aCSR[0] &= ~0x0008; /* clear TDMD */
2623
2624	pThis->aCSR[4] \|= 0x0008; /* set TXSTRT */
2625	if ( !CSR_TOKINTD(pThis) /* Transmit OK Interrupt Disable, no infl. on errors. */
2626	\|\| (CSR_LTINTEN(pThis) && tmd.tmd1.ltint)
2627	\|\| tmd.tmd1.err)
2628	{
2629	cFlushIrq++;
2630	}
2631
2632	/** @todo should we continue after an error (tmd.tmd1.err) or not? */
2633
2634	STAM_COUNTER_INC(&pThis->aStatXmitChainCounts[RT_MIN(cBuffers,
2635	RT_ELEMENTS(pThis->aStatXmitChainCounts)) - 1]);
2636	} while (CSR_TXON(pThis)); /* transfer on */
2637
2638	if (cFlushIrq)
2639	{
2640	STAM_COUNTER_INC(&pThis->aStatXmitFlush[RT_MIN(cFlushIrq, RT_ELEMENTS(pThis->aStatXmitFlush)) - 1]);
2641	pThis->aCSR[0] \|= 0x0200; /* set TINT */
2642	pcnetUpdateIrq(pThis);
2643	}
2644
2645	STAM_PROFILE_ADV_STOP(&pThis->StatTransmit, a);
2646
2647	return VINF_SUCCESS;
2648	}
2649
2650	#ifdef VBOX_WITH_TX_THREAD_IN_NET_DEVICES
2651
2652	/**
2653	* Async I/O thread for delayed sending of packets.
2654	*
2655	* @returns VBox status code. Returning failure will naturally terminate the thread.
2656	* @param pDevIns The pcnet device instance.
2657	* @param pThread The thread.
2658	*/
2659	static DECLCALLBACK(int) pcnetAsyncSendThread(PPDMDEVINS pDevIns, PPDMTHREAD pThread)
2660	{
2661	PCNetState pThis = PDMINS_2_DATA(pDevIns, PCNetState );
2662
2663	/*
2664	* We can enter this function in two states, initializing or resuming.
2665	*
2666	* The idea about the initializing bit is that we can do per-thread
2667	* initialization while the creator thread can still pick up errors.
2668	* At present, there is nothing to init, or at least nothing that
2669	* need initing in the thread.
2670	*/
2671	if (pThread->enmState == PDMTHREADSTATE_INITIALIZING)
2672	return VINF_SUCCESS;
2673
2674	/*
2675	* Stay in the run-loop until we're supposed to leave the
2676	* running state. If something really bad happens, we'll
2677	* quit the loop while in the running state and return
2678	* an error status to PDM and let it terminate the thread.
2679	*/
2680	while (pThread->enmState == PDMTHREADSTATE_RUNNING)
2681	{
2682	/*
2683	* Block until we've got something to send or is supposed
2684	* to leave the running state.
2685	*/
2686	int rc = RTSemEventWait(pThis->hSendEventSem, RT_INDEFINITE_WAIT);
2687	AssertRCReturn(rc, rc);
2688	if (RT_UNLIKELY(pThread->enmState != PDMTHREADSTATE_RUNNING))
2689	break;
2690
2691	/*
2692	* Perform async send. Mind that we might be requested to
2693	* suspended while waiting for the critical section.
2694	*/
2695	rc = PDMCritSectEnter(&pThis->CritSect, VERR_SEM_BUSY);
2696	AssertReleaseRCReturn(rc, rc);
2697
2698	if (pThread->enmState == PDMTHREADSTATE_RUNNING)
2699	{
2700	rc = pcnetAsyncTransmit(pThis, true /fOnWorkerThread/);
2701	AssertReleaseRC(rc);
2702	}
2703
2704	PDMCritSectLeave(&pThis->CritSect);
2705	}
2706
2707	/* The thread is being suspended or terminated. */
2708	return VINF_SUCCESS;
2709	}
2710
2711
2712	/**
2713	* Unblock the send thread so it can respond to a state change.
2714	*
2715	* @returns VBox status code.
2716	* @param pDevIns The pcnet device instance.
2717	* @param pThread The send thread.
2718	*/
2719	static DECLCALLBACK(int) pcnetAsyncSendThreadWakeUp(PPDMDEVINS pDevIns, PPDMTHREAD pThread)
2720	{
2721	PCNetState pThis = PDMINS_2_DATA(pDevIns, PCNetState );
2722	return RTSemEventSignal(pThis->hSendEventSem);
2723	}
2724
2725	# endif /* VBOX_WITH_TX_THREAD_IN_NET_DEVICES*/
2726	#endif /* IN_RING3 */
2727
2728	/**
2729	* Poll for changes in RX and TX descriptor rings.
2730	*/
2731	static void pcnetPollRxTx(PCNetState *pThis)
2732	{
2733	if (CSR_RXON(pThis))
2734	{
2735	/*
2736	* The second case is important for pcnetWaitReceiveAvail(): If CSR_CRST(pThis) was
2737	* true but pcnetCanReceive() returned false for some other reason we need to check
2738	* _now_ if we have to wakeup pcnetWaitReceiveAvail().
2739	*/
2740	if ( HOST_IS_OWNER(CSR_CRST(pThis)) /* only poll RDTEs if none available or ... */
2741	\|\| pThis->fMaybeOutOfSpace) /* ... for waking up pcnetWaitReceiveAvail() */
2742	pcnetRdtePoll(pThis);
2743	}
2744
2745	if (CSR_TDMD(pThis) \|\| (CSR_TXON(pThis) && !CSR_DPOLL(pThis)))
2746	pcnetTransmit(pThis);
2747	}
2748
2749
2750	/**
2751	* Start the poller timer.
2752	* Poll timer interval is fixed to 500Hz. Don't stop it.
2753	* @thread EMT, TAP.
2754	*/
2755	static void pcnetPollTimerStart(PCNetState *pThis)
2756	{
2757	TMTimerSetMillies(pThis->CTX_SUFF(pTimerPoll), 2);
2758	}
2759
2760
2761	/**
2762	* Update the poller timer.
2763	* @thread EMT.
2764	*/
2765	static void pcnetPollTimer(PCNetState *pThis)
2766	{
2767	STAM_PROFILE_ADV_START(&pThis->StatPollTimer, a);
2768
2769	#ifdef LOG_ENABLED
2770	TMD dummy;
2771	if (CSR_STOP(pThis) \|\| CSR_SPND(pThis))
2772	Log2(("#%d pcnetPollTimer time=%#010llx CSR_STOP=%d CSR_SPND=%d\n",
2773	PCNET_INST_NR, RTTimeMilliTS(), CSR_STOP(pThis), CSR_SPND(pThis)));
2774	else
2775	Log2(("#%d pcnetPollTimer time=%#010llx TDMD=%d TXON=%d POLL=%d TDTE=%d TDRA=%#x\n",
2776	PCNET_INST_NR, RTTimeMilliTS(), CSR_TDMD(pThis), CSR_TXON(pThis),
2777	!CSR_DPOLL(pThis), pcnetTdtePoll(pThis, &dummy), pThis->GCTDRA));
2778	Log2(("#%d pcnetPollTimer: CSR_CXDA=%#x CSR_XMTRL=%d CSR_XMTRC=%d\n",
2779	PCNET_INST_NR, CSR_CXDA(pThis), CSR_XMTRL(pThis), CSR_XMTRC(pThis)));
2780	#endif
2781	#ifdef PCNET_DEBUG_TMD
2782	if (CSR_CXDA(pThis))
2783	{
2784	TMD tmd;
2785	pcnetTmdLoad(pThis, &tmd, PHYSADDR(pThis, CSR_CXDA(pThis)), false);
2786	Log2(("#%d pcnetPollTimer: TMDLOAD %#010x\n", PCNET_INST_NR, PHYSADDR(pThis, CSR_CXDA(pThis))));
2787	PRINT_TMD(&tmd);
2788	}
2789	#endif
2790	if (CSR_TDMD(pThis))
2791	pcnetTransmit(pThis);
2792
2793	pcnetUpdateIrq(pThis);
2794
2795	/* If the receive thread is waiting for new descriptors, poll TX/RX even if polling
2796	* disabled. We wouldn't need to poll for new TX descriptors in that case but it will
2797	* not hurt as waiting for RX descriptors should happen very seldom */
2798	if (RT_LIKELY( !CSR_STOP(pThis)
2799	&& !CSR_SPND(pThis)
2800	&& ( !CSR_DPOLL(pThis)
2801	\|\| pThis->fMaybeOutOfSpace)))
2802	{
2803	/* We ensure that we poll at least every 2ms (500Hz) but not more often than
2804	* 5000 times per second. This way we completely prevent the overhead from
2805	* heavy reprogramming the timer which turned out to be very CPU-intensive.
2806	* The drawback is that csr46 and csr47 are not updated properly anymore
2807	* but so far I have not seen any guest depending on these values. The 2ms
2808	* interval is the default polling interval of the PCNet card (65536/33MHz). */
2809	#ifdef PCNET_NO_POLLING
2810	pcnetPollRxTx(pThis);
2811	#else
2812	uint64_t u64Now = TMTimerGet(pThis->CTX_SUFF(pTimerPoll));
2813	if (RT_UNLIKELY(u64Now - pThis->u64LastPoll > 200000))
2814	{
2815	pThis->u64LastPoll = u64Now;
2816	pcnetPollRxTx(pThis);
2817	}
2818	if (!TMTimerIsActive(pThis->CTX_SUFF(pTimerPoll)))
2819	pcnetPollTimerStart(pThis);
2820	#endif
2821	}
2822	STAM_PROFILE_ADV_STOP(&pThis->StatPollTimer, a);
2823	}
2824
2825
2826	static int pcnetCSRWriteU16(PCNetState *pThis, uint32_t u32RAP, uint32_t val)
2827	{
2828	int rc = VINF_SUCCESS;
2829	#ifdef PCNET_DEBUG_CSR
2830	Log(("#%d pcnetCSRWriteU16: rap=%d val=%#06x\n", PCNET_INST_NR, u32RAP, val));
2831	#endif
2832	switch (u32RAP)
2833	{
2834	case 0:
2835	{
2836	uint16_t csr0 = pThis->aCSR[0];
2837	/* Clear any interrupt flags.
2838	* Don't clear an interrupt flag which was not seen by the guest yet. */
2839	csr0 &= ~(val & 0x7f00 & pThis->u16CSR0LastSeenByGuest);
2840	csr0 = (csr0 & ~0x0040) \| (val & 0x0048);
2841	val = (val & 0x007f) \| (csr0 & 0x7f00);
2842
2843	/* Iff STOP, STRT and INIT are set, clear STRT and INIT */
2844	if ((val & 7) == 7)
2845	val &= ~3;
2846
2847	Log(("#%d CSR0: old=%#06x new=%#06x\n", PCNET_INST_NR, pThis->aCSR[0], csr0));
2848
2849	#ifndef IN_RING3
2850	if (!(csr0 & 0x0001/init/) && (val & 1))
2851	{
2852	Log(("#%d pcnetCSRWriteU16: pcnetInit requested => HC\n", PCNET_INST_NR));
2853	return VINF_IOM_HC_IOPORT_WRITE;
2854	}
2855	#endif
2856	pThis->aCSR[0] = csr0;
2857
2858	if (!CSR_STOP(pThis) && (val & 4))
2859	pcnetStop(pThis);
2860
2861	#ifdef IN_RING3
2862	if (!CSR_INIT(pThis) && (val & 1))
2863	pcnetInit(pThis);
2864	#endif
2865
2866	if (!CSR_STRT(pThis) && (val & 2))
2867	pcnetStart(pThis);
2868
2869	if (CSR_TDMD(pThis))
2870	pcnetTransmit(pThis);
2871
2872	return rc;
2873	}
2874	case 1: /* IADRL */
2875	case 2: /* IADRH */
2876	case 8: /* LADRF 0..15 */
2877	case 9: /* LADRF 16..31 */
2878	case 10: /* LADRF 32..47 */
2879	case 11: /* LADRF 48..63 */
2880	case 12: /* PADR 0..15 */
2881	case 13: /* PADR 16..31 */
2882	case 14: /* PADR 32..47 */
2883	case 18: /* CRBAL */
2884	case 19: /* CRBAU */
2885	case 20: /* CXBAL */
2886	case 21: /* CXBAU */
2887	case 22: /* NRBAL */
2888	case 23: /* NRBAU */
2889	case 26: /* NRDAL */
2890	case 27: /* NRDAU */
2891	case 28: /* CRDAL */
2892	case 29: /* CRDAU */
2893	case 32: /* NXDAL */
2894	case 33: /* NXDAU */
2895	case 34: /* CXDAL */
2896	case 35: /* CXDAU */
2897	case 36: /* NNRDL */
2898	case 37: /* NNRDU */
2899	case 38: /* NNXDL */
2900	case 39: /* NNXDU */
2901	case 40: /* CRBCL */
2902	case 41: /* CRBCU */
2903	case 42: /* CXBCL */
2904	case 43: /* CXBCU */
2905	case 44: /* NRBCL */
2906	case 45: /* NRBCU */
2907	case 46: /* POLL */
2908	case 47: /* POLLINT */
2909	case 72: /* RCVRC */
2910	case 74: /* XMTRC */
2911	case 112: /* MISSC */
2912	if (CSR_STOP(pThis) \|\| CSR_SPND(pThis))
2913	break;
2914	case 3: /* Interrupt Mask and Deferral Control */
2915	break;
2916	case 4: /* Test and Features Control */
2917	pThis->aCSR[4] &= ~(val & 0x026a);
2918	val &= ~0x026a;
2919	val \|= pThis->aCSR[4] & 0x026a;
2920	break;
2921	case 5: /* Extended Control and Interrupt 1 */
2922	pThis->aCSR[5] &= ~(val & 0x0a90);
2923	val &= ~0x0a90;
2924	val \|= pThis->aCSR[5] & 0x0a90;
2925	break;
2926	case 7: /* Extended Control and Interrupt 2 */
2927	{
2928	uint16_t csr7 = pThis->aCSR[7];
2929	csr7 &= ~0x0400 ;
2930	csr7 &= ~(val & 0x0800);
2931	csr7 \|= (val & 0x0400);
2932	pThis->aCSR[7] = csr7;
2933	return rc;
2934	}
2935	case 15: /* Mode */
2936	if ((pThis->aCSR[15] & 0x8000) != (uint16_t)(val & 0x8000) && pThis->pDrvR3)
2937	{
2938	Log(("#%d: promiscuous mode changed to %d\n", PCNET_INST_NR, !!(val & 0x8000)));
2939	#ifndef IN_RING3
2940	return VINF_IOM_HC_IOPORT_WRITE;
2941	#else
2942	/* check for promiscuous mode change */
2943	if (pThis->pDrvR3)
2944	pThis->pDrvR3->pfnSetPromiscuousMode(pThis->pDrvR3, !!(val & 0x8000));
2945	#endif
2946	}
2947	break;
2948	case 16: /* IADRL */
2949	return pcnetCSRWriteU16(pThis, 1, val);
2950	case 17: /* IADRH */
2951	return pcnetCSRWriteU16(pThis, 2, val);
2952
2953	/*
2954	* 24 and 25 are the Base Address of Receive Descriptor.
2955	* We combine and mirror these in GCRDRA.
2956	*/
2957	case 24: /* BADRL */
2958	case 25: /* BADRU */
2959	if (!CSR_STOP(pThis) && !CSR_SPND(pThis))
2960	{
2961	Log(("#%d: WRITE CSR%d, %#06x !!\n", PCNET_INST_NR, u32RAP, val));
2962	return rc;
2963	}
2964	if (u32RAP == 24)
2965	pThis->GCRDRA = (pThis->GCRDRA & 0xffff0000) \| (val & 0x0000ffff);
2966	else
2967	pThis->GCRDRA = (pThis->GCRDRA & 0x0000ffff) \| ((val & 0x0000ffff) << 16);
2968	Log(("#%d: WRITE CSR%d, %#06x => GCRDRA=%08x (alt init)\n", PCNET_INST_NR, u32RAP, val, pThis->GCRDRA));
2969	break;
2970
2971	/*
2972	* 30 & 31 are the Base Address of Transmit Descriptor.
2973	* We combine and mirrorthese in GCTDRA.
2974	*/
2975	case 30: /* BADXL */
2976	case 31: /* BADXU */
2977	if (!CSR_STOP(pThis) && !CSR_SPND(pThis))
2978	{
2979	Log(("#%d: WRITE CSR%d, %#06x !!\n", PCNET_INST_NR, u32RAP, val));
2980	return rc;
2981	}
2982	if (u32RAP == 30)
2983	pThis->GCTDRA = (pThis->GCTDRA & 0xffff0000) \| (val & 0x0000ffff);
2984	else
2985	pThis->GCTDRA = (pThis->GCTDRA & 0x0000ffff) \| ((val & 0x0000ffff) << 16);
2986	Log(("#%d: WRITE CSR%d, %#06x => GCTDRA=%08x (alt init)\n", PCNET_INST_NR, u32RAP, val, pThis->GCTDRA));
2987	break;
2988
2989	case 58: /* Software Style */
2990	rc = pcnetBCRWriteU16(pThis, BCR_SWS, val);
2991	break;
2992
2993	/*
2994	* Registers 76 and 78 aren't stored correctly (see todos), but I'm don't dare
2995	* try fix that right now. So, as a quick hack for 'alt init' I'll just correct them here.
2996	*/
2997	case 76: /* RCVRL / /* @todo call pcnetUpdateRingHandlers */
2998	/** @todo receive ring length is stored in two's complement! */
2999	case 78: /* XMTRL / /* @todo call pcnetUpdateRingHandlers */
3000	/** @todo transmit ring length is stored in two's complement! */
3001	if (!CSR_STOP(pThis) && !CSR_SPND(pThis))
3002	{
3003	Log(("#%d: WRITE CSR%d, %#06x !!\n", PCNET_INST_NR, u32RAP, val));
3004	return rc;
3005	}
3006	Log(("#%d: WRITE CSR%d, %#06x (hacked %#06x) (alt init)\n", PCNET_INST_NR,
3007	u32RAP, val, 1 + ~(uint16_t)val));
3008	val = 1 + ~(uint16_t)val;
3009
3010	/*
3011	* HACK ALERT! Set the counter registers too.
3012	*/
3013	pThis->aCSR[u32RAP - 4] = val;
3014	break;
3015
3016	default:
3017	return rc;
3018	}
3019	pThis->aCSR[u32RAP] = val;
3020	return rc;
3021	}
3022
3023	/**
3024	* Encode a 32-bit link speed into a custom 16-bit floating-point value
3025	*/
3026	static uint32_t pcnetLinkSpd(uint32_t speed)
3027	{
3028	unsigned exp = 0;
3029
3030	while (speed & 0xFFFFE000)
3031	{
3032	speed /= 10;
3033	++exp;
3034	}
3035	return (exp << 13) \| speed;
3036	}
3037
3038	static uint32_t pcnetCSRReadU16(PCNetState *pThis, uint32_t u32RAP)
3039	{
3040	uint32_t val;
3041	switch (u32RAP)
3042	{
3043	case 0:
3044	pcnetUpdateIrq(pThis);
3045	val = pThis->aCSR[0];
3046	val \|= (val & 0x7800) ? 0x8000 : 0;
3047	pThis->u16CSR0LastSeenByGuest = val;
3048	break;
3049	case 16:
3050	return pcnetCSRReadU16(pThis, 1);
3051	case 17:
3052	return pcnetCSRReadU16(pThis, 2);
3053	case 58:
3054	return pcnetBCRReadU16(pThis, BCR_SWS);
3055	case 68: /* Custom register to pass link speed to driver */
3056	return pcnetLinkSpd(pThis->u32LinkSpeed);
3057	case 88:
3058	val = pThis->aCSR[89];
3059	val <<= 16;
3060	val \|= pThis->aCSR[88];
3061	break;
3062	default:
3063	val = pThis->aCSR[u32RAP];
3064	}
3065	#ifdef PCNET_DEBUG_CSR
3066	Log(("#%d pcnetCSRReadU16: rap=%d val=%#06x\n", PCNET_INST_NR, u32RAP, val));
3067	#endif
3068	return val;
3069	}
3070
3071	static int pcnetBCRWriteU16(PCNetState *pThis, uint32_t u32RAP, uint32_t val)
3072	{
3073	int rc = VINF_SUCCESS;
3074	u32RAP &= 0x7f;
3075	#ifdef PCNET_DEBUG_BCR
3076	Log2(("#%d pcnetBCRWriteU16: rap=%d val=%#06x\n", PCNET_INST_NR, u32RAP, val));
3077	#endif
3078	switch (u32RAP)
3079	{
3080	case BCR_SWS:
3081	if (!(CSR_STOP(pThis) \|\| CSR_SPND(pThis)))
3082	return rc;
3083	val &= ~0x0300;
3084	switch (val & 0x00ff)
3085	{
3086	default:
3087	Log(("#%d Bad SWSTYLE=%#04x\n", PCNET_INST_NR, val & 0xff));
3088	// fall through
3089	case 0:
3090	val \|= 0x0200; /* 16 bit */
3091	pThis->iLog2DescSize = 3;
3092	pThis->GCUpperPhys = (0xff00 & (uint32_t)pThis->aCSR[2]) << 16;
3093	break;
3094	case 1:
3095	val \|= 0x0100; /* 32 bit */
3096	pThis->iLog2DescSize = 4;
3097	pThis->GCUpperPhys = 0;
3098	break;
3099	case 2:
3100	case 3:
3101	val \|= 0x0300; /* 32 bit */
3102	pThis->iLog2DescSize = 4;
3103	pThis->GCUpperPhys = 0;
3104	break;
3105	}
3106	Log(("#%d BCR_SWS=%#06x\n", PCNET_INST_NR, val));
3107	pThis->aCSR[58] = val;
3108	/* fall through */
3109	case BCR_LNKST:
3110	case BCR_LED1:
3111	case BCR_LED2:
3112	case BCR_LED3:
3113	case BCR_MC:
3114	case BCR_FDC:
3115	case BCR_BSBC:
3116	case BCR_EECAS:
3117	case BCR_PLAT:
3118	case BCR_MIICAS:
3119	case BCR_MIIADDR:
3120	pThis->aBCR[u32RAP] = val;
3121	break;
3122
3123	case BCR_STVAL:
3124	val &= 0xffff;
3125	pThis->aBCR[BCR_STVAL] = val;
3126	if (pThis->fAm79C973)
3127	TMTimerSetNano(pThis->CTX_SUFF(pTimerSoftInt), 12800U * val);
3128	break;
3129
3130	case BCR_MIIMDR:
3131	pThis->aMII[pThis->aBCR[BCR_MIIADDR] & 0x1f] = val;
3132	#ifdef PCNET_DEBUG_MII
3133	Log(("#%d pcnet: mii write %d <- %#x\n", PCNET_INST_NR, pThis->aBCR[BCR_MIIADDR] & 0x1f, val));
3134	#endif
3135	break;
3136
3137	default:
3138	break;
3139	}
3140	return rc;
3141	}
3142
3143	static uint32_t pcnetMIIReadU16(PCNetState *pThis, uint32_t miiaddr)
3144	{
3145	uint32_t val;
3146	bool autoneg, duplex, fast;
3147	STAM_COUNTER_INC(&pThis->StatMIIReads);
3148
3149	autoneg = (pThis->aBCR[BCR_MIICAS] & 0x20) != 0;
3150	duplex = (pThis->aBCR[BCR_MIICAS] & 0x10) != 0;
3151	fast = (pThis->aBCR[BCR_MIICAS] & 0x08) != 0;
3152
3153	switch (miiaddr)
3154	{
3155	case 0:
3156	/* MII basic mode control register. */
3157	val = 0;
3158	if (autoneg)
3159	val \|= 0x1000; /* Enable auto negotiation. */
3160	if (fast)
3161	val \|= 0x2000; /* 100 Mbps */
3162	if (duplex) /* Full duplex forced */
3163	val \|= 0x0100; /* Full duplex */
3164	break;
3165
3166	case 1:
3167	/* MII basic mode status register. */
3168	val = 0x7800 /* Can do 100mbps FD/HD and 10mbps FD/HD. */
3169	\| 0x0040 /* Mgmt frame preamble not required. */
3170	\| 0x0020 /* Auto-negotiation complete. */
3171	\| 0x0008 /* Able to do auto-negotiation. */
3172	\| 0x0004 /* Link up. */
3173	\| 0x0001; /* Extended Capability, i.e. registers 4+ valid. */
3174	if (!pThis->fLinkUp \|\| pThis->fLinkTempDown) {
3175	val &= ~(0x0020 \| 0x0004);
3176	pThis->cLinkDownReported++;
3177	}
3178	if (!autoneg) {
3179	/* Auto-negotiation disabled. */
3180	val &= ~(0x0020 \| 0x0008);
3181	if (duplex)
3182	/* Full duplex forced. */
3183	val &= ~0x2800;
3184	else
3185	/* Half duplex forced. */
3186	val &= ~0x5000;
3187
3188	if (fast)
3189	/* 100 Mbps forced */
3190	val &= ~0x1800;
3191	else
3192	/* 10 Mbps forced */
3193	val &= ~0x6000;
3194	}
3195	break;
3196
3197	case 2:
3198	/* PHY identifier 1. */
3199	val = 0x22; /* Am79C874 PHY */
3200	break;
3201
3202	case 3:
3203	/* PHY identifier 2. */
3204	val = 0x561b; /* Am79C874 PHY */
3205	break;
3206
3207	case 4:
3208	/* Advertisement control register. */
3209	val = 0x01e0 /* Try 100mbps FD/HD and 10mbps FD/HD. */
3210	#if 0
3211	// Advertising flow control is a) not the default, and b) confuses
3212	// the link speed detection routine in Windows PCnet driver
3213	\| 0x0400 /* Try flow control. */
3214	#endif
3215	\| 0x0001; /* CSMA selector. */
3216	break;
3217
3218	case 5:
3219	/* Link partner ability register. */
3220	if (pThis->fLinkUp && !pThis->fLinkTempDown)
3221	val = 0x8000 /* Next page bit. */
3222	\| 0x4000 /* Link partner acked us. */
3223	\| 0x0400 /* Can do flow control. */
3224	\| 0x01e0 /* Can do 100mbps FD/HD and 10mbps FD/HD. */
3225	\| 0x0001; /* Use CSMA selector. */
3226	else
3227	{
3228	val = 0;
3229	pThis->cLinkDownReported++;
3230	}
3231	break;
3232
3233	case 6:
3234	/* Auto negotiation expansion register. */
3235	if (pThis->fLinkUp && !pThis->fLinkTempDown)
3236	val = 0x0008 /* Link partner supports npage. */
3237	\| 0x0004 /* Enable npage words. */
3238	\| 0x0001; /* Can do N-way auto-negotiation. */
3239	else
3240	{
3241	val = 0;
3242	pThis->cLinkDownReported++;
3243	}
3244	break;
3245
3246	default:
3247	val = 0;
3248	break;
3249	}
3250
3251	#ifdef PCNET_DEBUG_MII
3252	Log(("#%d pcnet: mii read %d -> %#x\n", PCNET_INST_NR, miiaddr, val));
3253	#endif
3254	return val;
3255	}
3256
3257	static uint32_t pcnetBCRReadU16(PCNetState *pThis, uint32_t u32RAP)
3258	{
3259	uint32_t val;
3260	u32RAP &= 0x7f;
3261	switch (u32RAP)
3262	{
3263	case BCR_LNKST:
3264	case BCR_LED1:
3265	case BCR_LED2:
3266	case BCR_LED3:
3267	val = pThis->aBCR[u32RAP] & ~0x8000;
3268	/* Clear LNKSTE if we're not connected or if we've just loaded a VM state. */
3269	if (!pThis->pDrvR3 \|\| pThis->fLinkTempDown \|\| !pThis->fLinkUp)
3270	{
3271	if (u32RAP == 4)
3272	pThis->cLinkDownReported++;
3273	val &= ~0x40;
3274	}
3275	val \|= (val & 0x017f & pThis->u32Lnkst) ? 0x8000 : 0;
3276	break;
3277
3278	case BCR_MIIMDR:
3279	if (pThis->fAm79C973 && (pThis->aBCR[BCR_MIIADDR] >> 5 & 0x1f) == 0)
3280	{
3281	uint32_t miiaddr = pThis->aBCR[BCR_MIIADDR] & 0x1f;
3282	val = pcnetMIIReadU16(pThis, miiaddr);
3283	}
3284	else
3285	val = 0xffff;
3286	break;
3287
3288	default:
3289	val = u32RAP < BCR_MAX_RAP ? pThis->aBCR[u32RAP] : 0;
3290	break;
3291	}
3292	#ifdef PCNET_DEBUG_BCR
3293	Log2(("#%d pcnetBCRReadU16: rap=%d val=%#06x\n", PCNET_INST_NR, u32RAP, val));
3294	#endif
3295	return val;
3296	}
3297
3298	#ifdef IN_RING3 /* move down */
3299	static void pcnetHardReset(PCNetState *pThis)
3300	{
3301	int i;
3302	uint16_t checksum;
3303
3304	/* Initialize the PROM */
3305	Assert(sizeof(pThis->MacConfigured) == 6);
3306	memcpy(pThis->aPROM, &pThis->MacConfigured, sizeof(pThis->MacConfigured));
3307	pThis->aPROM[ 8] = 0x00;
3308	pThis->aPROM[ 9] = 0x11;
3309	pThis->aPROM[12] = pThis->aPROM[13] = 0x00;
3310	pThis->aPROM[14] = pThis->aPROM[15] = 0x57;
3311
3312	for (i = 0, checksum = 0; i < 16; i++)
3313	checksum += pThis->aPROM[i];
3314	(uint16_t )&pThis->aPROM[12] = RT_H2LE_U16(checksum);
3315
3316	pThis->aBCR[BCR_MSRDA] = 0x0005;
3317	pThis->aBCR[BCR_MSWRA] = 0x0005;
3318	pThis->aBCR[BCR_MC ] = 0x0002;
3319	pThis->aBCR[BCR_LNKST] = 0x00c0;
3320	pThis->aBCR[BCR_LED1 ] = 0x0084;
3321	pThis->aBCR[BCR_LED2 ] = 0x0088;
3322	pThis->aBCR[BCR_LED3 ] = 0x0090;
3323	pThis->aBCR[BCR_FDC ] = 0x0000;
3324	pThis->aBCR[BCR_BSBC ] = 0x9001;
3325	pThis->aBCR[BCR_EECAS] = 0x0002;
3326	pThis->aBCR[BCR_STVAL] = 0xffff;
3327	pThis->aCSR[58 ] = /* CSR58 is an alias for BCR20 */
3328	pThis->aBCR[BCR_SWS ] = 0x0200;
3329	pThis->iLog2DescSize = 3;
3330	pThis->aBCR[BCR_PLAT ] = 0xff06;
3331	pThis->aBCR[BCR_MIIADDR ] = 0; /* Internal PHY on Am79C973 would be (0x1e << 5) */
3332	pThis->aBCR[BCR_PCIVID] = PCIDevGetVendorId(&pThis->PciDev);
3333	pThis->aBCR[BCR_PCISID] = PCIDevGetSubSystemId(&pThis->PciDev);
3334	pThis->aBCR[BCR_PCISVID] = PCIDevGetSubSystemVendorId(&pThis->PciDev);
3335
3336	/* Reset the error counter. */
3337	pThis->uCntBadRMD = 0;
3338
3339	pcnetSoftReset(pThis);
3340	}
3341	#endif /* IN_RING3 */
3342
3343	static void pcnetAPROMWriteU8(PCNetState *pThis, uint32_t addr, uint32_t val)
3344	{
3345	addr &= 0x0f;
3346	val &= 0xff;
3347	Log(("#%d pcnetAPROMWriteU8: addr=%#010x val=%#04x\n", PCNET_INST_NR, addr, val));
3348	/* Check APROMWE bit to enable write access */
3349	if (pcnetBCRReadU16(pThis, 2) & 0x80)
3350	pThis->aPROM[addr] = val;
3351	}
3352
3353	static uint32_t pcnetAPROMReadU8(PCNetState *pThis, uint32_t addr)
3354	{
3355	uint32_t val = pThis->aPROM[addr &= 0x0f];
3356	Log(("#%d pcnetAPROMReadU8: addr=%#010x val=%#04x\n", PCNET_INST_NR, addr, val));
3357	return val;
3358	}
3359
3360	static int pcnetIoportWriteU8(PCNetState *pThis, uint32_t addr, uint32_t val)
3361	{
3362	int rc = VINF_SUCCESS;
3363
3364	#ifdef PCNET_DEBUG_IO
3365	Log2(("#%d pcnetIoportWriteU8: addr=%#010x val=%#06x\n", PCNET_INST_NR,
3366	addr, val));
3367	#endif
3368	if (RT_LIKELY(!BCR_DWIO(pThis)))
3369	{
3370	switch (addr & 0x0f)
3371	{
3372	case 0x04: /* RESET */
3373	break;
3374	}
3375	}
3376	else
3377	Log(("#%d pcnetIoportWriteU8: addr=%#010x val=%#06x BCR_DWIO !!\n", PCNET_INST_NR, addr, val));
3378
3379	return rc;
3380	}
3381
3382	static uint32_t pcnetIoportReadU8(PCNetState pThis, uint32_t addr, int pRC)
3383	{
3384	uint32_t val = ~0U;
3385
3386	*pRC = VINF_SUCCESS;
3387
3388	if (RT_LIKELY(!BCR_DWIO(pThis)))
3389	{
3390	switch (addr & 0x0f)
3391	{
3392	case 0x04: /* RESET */
3393	pcnetSoftReset(pThis);
3394	val = 0;
3395	break;
3396	}
3397	}
3398	else
3399	Log(("#%d pcnetIoportReadU8: addr=%#010x val=%#06x BCR_DWIO !!\n", PCNET_INST_NR, addr, val & 0xff));
3400
3401	pcnetUpdateIrq(pThis);
3402
3403	#ifdef PCNET_DEBUG_IO
3404	Log2(("#%d pcnetIoportReadU8: addr=%#010x val=%#06x\n", PCNET_INST_NR, addr, val & 0xff));
3405	#endif
3406	return val;
3407	}
3408
3409	static int pcnetIoportWriteU16(PCNetState *pThis, uint32_t addr, uint32_t val)
3410	{
3411	int rc = VINF_SUCCESS;
3412
3413	#ifdef PCNET_DEBUG_IO
3414	Log2(("#%d pcnetIoportWriteU16: addr=%#010x val=%#06x\n", PCNET_INST_NR,
3415	addr, val));
3416	#endif
3417	if (RT_LIKELY(!BCR_DWIO(pThis)))
3418	{
3419	switch (addr & 0x0f)
3420	{
3421	case 0x00: /* RDP */
3422	pcnetPollTimer(pThis);
3423	rc = pcnetCSRWriteU16(pThis, pThis->u32RAP, val);
3424	pcnetUpdateIrq(pThis);
3425	break;
3426	case 0x02: /* RAP */
3427	pThis->u32RAP = val & 0x7f;
3428	break;
3429	case 0x06: /* BDP */
3430	rc = pcnetBCRWriteU16(pThis, pThis->u32RAP, val);
3431	break;
3432	}
3433	}
3434	else
3435	Log(("#%d pcnetIoportWriteU16: addr=%#010x val=%#06x BCR_DWIO !!\n", PCNET_INST_NR, addr, val));
3436
3437	return rc;
3438	}
3439
3440	static uint32_t pcnetIoportReadU16(PCNetState pThis, uint32_t addr, int pRC)
3441	{
3442	uint32_t val = ~0U;
3443
3444	*pRC = VINF_SUCCESS;
3445
3446	if (RT_LIKELY(!BCR_DWIO(pThis)))
3447	{
3448	switch (addr & 0x0f)
3449	{
3450	case 0x00: /* RDP */
3451	/** @note if we're not polling, then the guest will tell us when to poll by setting TDMD in CSR0 */
3452	/** Polling is then useless here and possibly expensive. */
3453	if (!CSR_DPOLL(pThis))
3454	pcnetPollTimer(pThis);
3455
3456	val = pcnetCSRReadU16(pThis, pThis->u32RAP);
3457	if (pThis->u32RAP == 0) // pcnetUpdateIrq() already called by pcnetCSRReadU16()
3458	goto skip_update_irq;
3459	break;
3460	case 0x02: /* RAP */
3461	val = pThis->u32RAP;
3462	goto skip_update_irq;
3463	case 0x04: /* RESET */
3464	pcnetSoftReset(pThis);
3465	val = 0;
3466	break;
3467	case 0x06: /* BDP */
3468	val = pcnetBCRReadU16(pThis, pThis->u32RAP);
3469	break;
3470	}
3471	}
3472	else
3473	Log(("#%d pcnetIoportReadU16: addr=%#010x val=%#06x BCR_DWIO !!\n", PCNET_INST_NR, addr, val & 0xffff));
3474
3475	pcnetUpdateIrq(pThis);
3476
3477	skip_update_irq:
3478	#ifdef PCNET_DEBUG_IO
3479	Log2(("#%d pcnetIoportReadU16: addr=%#010x val=%#06x\n", PCNET_INST_NR, addr, val & 0xffff));
3480	#endif
3481	return val;
3482	}
3483
3484	static int pcnetIoportWriteU32(PCNetState *pThis, uint32_t addr, uint32_t val)
3485	{
3486	int rc = VINF_SUCCESS;
3487
3488	#ifdef PCNET_DEBUG_IO
3489	Log2(("#%d pcnetIoportWriteU32: addr=%#010x val=%#010x\n", PCNET_INST_NR,
3490	addr, val));
3491	#endif
3492	if (RT_LIKELY(BCR_DWIO(pThis)))
3493	{
3494	switch (addr & 0x0f)
3495	{
3496	case 0x00: /* RDP */
3497	pcnetPollTimer(pThis);
3498	rc = pcnetCSRWriteU16(pThis, pThis->u32RAP, val & 0xffff);
3499	pcnetUpdateIrq(pThis);
3500	break;
3501	case 0x04: /* RAP */
3502	pThis->u32RAP = val & 0x7f;
3503	break;
3504	case 0x0c: /* BDP */
3505	rc = pcnetBCRWriteU16(pThis, pThis->u32RAP, val & 0xffff);
3506	break;
3507	}
3508	}
3509	else if ((addr & 0x0f) == 0)
3510	{
3511	/* switch device to dword I/O mode */
3512	pcnetBCRWriteU16(pThis, BCR_BSBC, pcnetBCRReadU16(pThis, BCR_BSBC) \| 0x0080);
3513	#ifdef PCNET_DEBUG_IO
3514	Log2(("device switched into dword i/o mode\n"));
3515	#endif
3516	}
3517	else
3518	Log(("#%d pcnetIoportWriteU32: addr=%#010x val=%#010x !BCR_DWIO !!\n", PCNET_INST_NR, addr, val));
3519
3520	return rc;
3521	}
3522
3523	static uint32_t pcnetIoportReadU32(PCNetState pThis, uint32_t addr, int pRC)
3524	{
3525	uint32_t val = ~0U;
3526
3527	*pRC = VINF_SUCCESS;
3528
3529	if (RT_LIKELY(BCR_DWIO(pThis)))
3530	{
3531	switch (addr & 0x0f)
3532	{
3533	case 0x00: /* RDP */
3534	/** @note if we're not polling, then the guest will tell us when to poll by setting TDMD in CSR0 */
3535	/** Polling is then useless here and possibly expensive. */
3536	if (!CSR_DPOLL(pThis))
3537	pcnetPollTimer(pThis);
3538
3539	val = pcnetCSRReadU16(pThis, pThis->u32RAP);
3540	if (pThis->u32RAP == 0) // pcnetUpdateIrq() already called by pcnetCSRReadU16()
3541	goto skip_update_irq;
3542	break;
3543	case 0x04: /* RAP */
3544	val = pThis->u32RAP;
3545	goto skip_update_irq;
3546	case 0x08: /* RESET */
3547	pcnetSoftReset(pThis);
3548	val = 0;
3549	break;
3550	case 0x0c: /* BDP */
3551	val = pcnetBCRReadU16(pThis, pThis->u32RAP);
3552	break;
3553	}
3554	}
3555	else
3556	Log(("#%d pcnetIoportReadU32: addr=%#010x val=%#010x !BCR_DWIO !!\n", PCNET_INST_NR, addr, val));
3557	pcnetUpdateIrq(pThis);
3558
3559	skip_update_irq:
3560	#ifdef PCNET_DEBUG_IO
3561	Log2(("#%d pcnetIoportReadU32: addr=%#010x val=%#010x\n", PCNET_INST_NR, addr, val));
3562	#endif
3563	return val;
3564	}
3565
3566	static void pcnetMMIOWriteU8(PCNetState *pThis, RTGCPHYS addr, uint32_t val)
3567	{
3568	#ifdef PCNET_DEBUG_IO
3569	Log2(("#%d pcnetMMIOWriteU8: addr=%#010x val=%#04x\n", PCNET_INST_NR, addr, val));
3570	#endif
3571	if (!(addr & 0x10))
3572	pcnetAPROMWriteU8(pThis, addr, val);
3573	}
3574
3575	static uint32_t pcnetMMIOReadU8(PCNetState *pThis, RTGCPHYS addr)
3576	{
3577	uint32_t val = ~0U;
3578	if (!(addr & 0x10))
3579	val = pcnetAPROMReadU8(pThis, addr);
3580	#ifdef PCNET_DEBUG_IO
3581	Log2(("#%d pcnetMMIOReadU8: addr=%#010x val=%#04x\n", PCNET_INST_NR, addr, val & 0xff));
3582	#endif
3583	return val;
3584	}
3585
3586	static void pcnetMMIOWriteU16(PCNetState *pThis, RTGCPHYS addr, uint32_t val)
3587	{
3588	#ifdef PCNET_DEBUG_IO
3589	Log2(("#%d pcnetMMIOWriteU16: addr=%#010x val=%#06x\n", PCNET_INST_NR, addr, val));
3590	#endif
3591	if (addr & 0x10)
3592	pcnetIoportWriteU16(pThis, addr & 0x0f, val);
3593	else
3594	{
3595	pcnetAPROMWriteU8(pThis, addr, val );
3596	pcnetAPROMWriteU8(pThis, addr+1, val >> 8);
3597	}
3598	}
3599
3600	static uint32_t pcnetMMIOReadU16(PCNetState *pThis, RTGCPHYS addr)
3601	{
3602	uint32_t val = ~0U;
3603	int rc;
3604
3605	if (addr & 0x10)
3606	val = pcnetIoportReadU16(pThis, addr & 0x0f, &rc);
3607	else
3608	{
3609	val = pcnetAPROMReadU8(pThis, addr+1);
3610	val <<= 8;
3611	val \|= pcnetAPROMReadU8(pThis, addr);
3612	}
3613	#ifdef PCNET_DEBUG_IO
3614	Log2(("#%d pcnetMMIOReadU16: addr=%#010x val = %#06x\n", PCNET_INST_NR, addr, val & 0xffff));
3615	#endif
3616	return val;
3617	}
3618
3619	static void pcnetMMIOWriteU32(PCNetState *pThis, RTGCPHYS addr, uint32_t val)
3620	{
3621	#ifdef PCNET_DEBUG_IO
3622	Log2(("#%d pcnetMMIOWriteU32: addr=%#010x val=%#010x\n", PCNET_INST_NR, addr, val));
3623	#endif
3624	if (addr & 0x10)
3625	pcnetIoportWriteU32(pThis, addr & 0x0f, val);
3626	else
3627	{
3628	pcnetAPROMWriteU8(pThis, addr, val );
3629	pcnetAPROMWriteU8(pThis, addr+1, val >> 8);
3630	pcnetAPROMWriteU8(pThis, addr+2, val >> 16);
3631	pcnetAPROMWriteU8(pThis, addr+3, val >> 24);
3632	}
3633	}
3634
3635	static uint32_t pcnetMMIOReadU32(PCNetState *pThis, RTGCPHYS addr)
3636	{
3637	uint32_t val;
3638	int rc;
3639
3640	if (addr & 0x10)
3641	val = pcnetIoportReadU32(pThis, addr & 0x0f, &rc);
3642	else
3643	{
3644	val = pcnetAPROMReadU8(pThis, addr+3);
3645	val <<= 8;
3646	val \|= pcnetAPROMReadU8(pThis, addr+2);
3647	val <<= 8;
3648	val \|= pcnetAPROMReadU8(pThis, addr+1);
3649	val <<= 8;
3650	val \|= pcnetAPROMReadU8(pThis, addr );
3651	}
3652	#ifdef PCNET_DEBUG_IO
3653	Log2(("#%d pcnetMMIOReadU32: addr=%#010x val=%#010x\n", PCNET_INST_NR, addr, val));
3654	#endif
3655	return val;
3656	}
3657
3658
3659	/**
3660	* Port I/O Handler for IN operations.
3661	*
3662	* @returns VBox status code.
3663	*
3664	* @param pDevIns The device instance.
3665	* @param pvUser User argument.
3666	* @param Port Port number used for the IN operation.
3667	* @param pu32 Where to store the result.
3668	* @param cb Number of bytes read.
3669	*/
3670	PDMBOTHCBDECL(int) pcnetIOPortAPromRead(PPDMDEVINS pDevIns, void *pvUser,
3671	RTIOPORT Port, uint32_t *pu32, unsigned cb)
3672	{
3673	PCNetState pThis = PDMINS_2_DATA(pDevIns, PCNetState );
3674	int rc;
3675
3676	STAM_PROFILE_ADV_START(&pThis->StatAPROMRead, a);
3677	rc = PDMCritSectEnter(&pThis->CritSect, VINF_IOM_HC_IOPORT_WRITE);
3678	if (rc == VINF_SUCCESS)
3679	{
3680
3681	/* FreeBSD is accessing in dwords. */
3682	if (cb == 1)
3683	*pu32 = pcnetAPROMReadU8(pThis, Port);
3684	else if (cb == 2 && !BCR_DWIO(pThis))
3685	*pu32 = pcnetAPROMReadU8(pThis, Port)
3686	\| (pcnetAPROMReadU8(pThis, Port + 1) << 8);
3687	else if (cb == 4 && BCR_DWIO(pThis))
3688	*pu32 = pcnetAPROMReadU8(pThis, Port)
3689	\| (pcnetAPROMReadU8(pThis, Port + 1) << 8)
3690	\| (pcnetAPROMReadU8(pThis, Port + 2) << 16)
3691	\| (pcnetAPROMReadU8(pThis, Port + 3) << 24);
3692	else
3693	{
3694	Log(("#%d pcnetIOPortAPromRead: Port=%RTiop cb=%d BCR_DWIO !!\n", PCNET_INST_NR, Port, cb));
3695	rc = VERR_IOM_IOPORT_UNUSED;
3696	}
3697	PDMCritSectLeave(&pThis->CritSect);
3698	}
3699	STAM_PROFILE_ADV_STOP(&pThis->StatAPROMRead, a);
3700	LogFlow(("#%d pcnetIOPortAPromRead: Port=%RTiop pu32=%#RX32 cb=%d rc=%Rrc\n", PCNET_INST_NR, Port, pu32, cb, rc));
3701	return rc;
3702	}
3703
3704
3705	/**
3706	* Port I/O Handler for OUT operations.
3707	*
3708	* @returns VBox status code.
3709	*
3710	* @param pDevIns The device instance.
3711	* @param pvUser User argument.
3712	* @param Port Port number used for the IN operation.
3713	* @param u32 The value to output.
3714	* @param cb The value size in bytes.
3715	*/
3716	PDMBOTHCBDECL(int) pcnetIOPortAPromWrite(PPDMDEVINS pDevIns, void *pvUser,
3717	RTIOPORT Port, uint32_t u32, unsigned cb)
3718	{
3719	PCNetState pThis = PDMINS_2_DATA(pDevIns, PCNetState );
3720	int rc;
3721
3722	if (cb == 1)
3723	{
3724	STAM_PROFILE_ADV_START(&pThis->StatAPROMWrite, a);
3725	rc = PDMCritSectEnter(&pThis->CritSect, VINF_IOM_HC_IOPORT_WRITE);
3726	if (RT_LIKELY(rc == VINF_SUCCESS))
3727	{
3728	pcnetAPROMWriteU8(pThis, Port, u32);
3729	PDMCritSectLeave(&pThis->CritSect);
3730	}
3731	STAM_PROFILE_ADV_STOP(&pThis->StatAPROMWrite, a);
3732	}
3733	else
3734	{
3735	AssertMsgFailed(("Port=%#x cb=%d u32=%#x\n", Port, cb, u32));
3736	rc = VINF_SUCCESS;
3737	}
3738	LogFlow(("#%d pcnetIOPortAPromWrite: Port=%RTiop u32=%#RX32 cb=%d rc=%Rrc\n", PCNET_INST_NR, Port, u32, cb, rc));
3739	#ifdef LOG_ENABLED
3740	if (rc == VINF_IOM_HC_IOPORT_WRITE)
3741	LogFlow(("#%d => HC\n", PCNET_INST_NR));
3742	#endif
3743	return rc;
3744	}
3745
3746
3747	/**
3748	* Port I/O Handler for IN operations.
3749	*
3750	* @returns VBox status code.
3751	*
3752	* @param pDevIns The device instance.
3753	* @param pvUser User argument.
3754	* @param Port Port number used for the IN operation.
3755	* @param pu32 Where to store the result.
3756	* @param cb Number of bytes read.
3757	*/
3758	PDMBOTHCBDECL(int) pcnetIOPortRead(PPDMDEVINS pDevIns, void *pvUser,
3759	RTIOPORT Port, uint32_t *pu32, unsigned cb)
3760	{
3761	PCNetState pThis = PDMINS_2_DATA(pDevIns, PCNetState );
3762	int rc = VINF_SUCCESS;
3763
3764	STAM_PROFILE_ADV_START(&pThis->CTXSUFF(StatIORead), a);
3765	rc = PDMCritSectEnter(&pThis->CritSect, VINF_IOM_HC_IOPORT_READ);
3766	if (RT_LIKELY(rc == VINF_SUCCESS))
3767	{
3768	switch (cb)
3769	{
3770	case 1: *pu32 = pcnetIoportReadU8(pThis, Port, &rc); break;
3771	case 2: *pu32 = pcnetIoportReadU16(pThis, Port, &rc); break;
3772	case 4: *pu32 = pcnetIoportReadU32(pThis, Port, &rc); break;
3773	default:
3774	rc = PDMDevHlpDBGFStop(pThis->CTX_SUFF(pDevIns), RT_SRC_POS,
3775	"pcnetIOPortRead: unsupported op size: offset=%#10x cb=%u\n",
3776	Port, cb);
3777	}
3778	PDMCritSectLeave(&pThis->CritSect);
3779	}
3780	STAM_PROFILE_ADV_STOP(&pThis->CTXSUFF(StatIORead), a);
3781	Log2(("#%d pcnetIOPortRead: Port=%RTiop pu32=%#RX32 cb=%d rc=%Rrc\n", PCNET_INST_NR, Port, pu32, cb, rc));
3782	#ifdef LOG_ENABLED
3783	if (rc == VINF_IOM_HC_IOPORT_READ)
3784	LogFlow(("#%d pcnetIOPortRead/critsect failed in GC => HC\n", PCNET_INST_NR));
3785	#endif
3786	return rc;
3787	}
3788
3789
3790	/**
3791	* Port I/O Handler for OUT operations.
3792	*
3793	* @returns VBox status code.
3794	*
3795	* @param pDevIns The device instance.
3796	* @param pvUser User argument.
3797	* @param Port Port number used for the IN operation.
3798	* @param u32 The value to output.
3799	* @param cb The value size in bytes.
3800	*/
3801	PDMBOTHCBDECL(int) pcnetIOPortWrite(PPDMDEVINS pDevIns, void *pvUser,
3802	RTIOPORT Port, uint32_t u32, unsigned cb)
3803	{
3804	PCNetState pThis = PDMINS_2_DATA(pDevIns, PCNetState );
3805	int rc = VINF_SUCCESS;
3806
3807	STAM_PROFILE_ADV_START(&pThis->CTXSUFF(StatIOWrite), a);
3808	rc = PDMCritSectEnter(&pThis->CritSect, VINF_IOM_HC_IOPORT_WRITE);
3809	if (RT_LIKELY(rc == VINF_SUCCESS))
3810	{
3811	switch (cb)
3812	{
3813	case 1: rc = pcnetIoportWriteU8(pThis, Port, u32); break;
3814	case 2: rc = pcnetIoportWriteU16(pThis, Port, u32); break;
3815	case 4: rc = pcnetIoportWriteU32(pThis, Port, u32); break;
3816	default:
3817	rc = PDMDevHlpDBGFStop(pThis->CTX_SUFF(pDevIns), RT_SRC_POS,
3818	"pcnetIOPortWrite: unsupported op size: offset=%#10x cb=%u\n",
3819	Port, cb);
3820	}
3821	PDMCritSectLeave(&pThis->CritSect);
3822	}
3823	STAM_PROFILE_ADV_STOP(&pThis->CTXSUFF(StatIOWrite), a);
3824	Log2(("#%d pcnetIOPortWrite: Port=%RTiop u32=%#RX32 cb=%d rc=%Rrc\n", PCNET_INST_NR, Port, u32, cb, rc));
3825	#ifdef LOG_ENABLED
3826	if (rc == VINF_IOM_HC_IOPORT_WRITE)
3827	LogFlow(("#%d pcnetIOPortWrite/critsect failed in GC => HC\n", PCNET_INST_NR));
3828	#endif
3829	return rc;
3830	}
3831
3832
3833	/**
3834	* Memory mapped I/O Handler for read operations.
3835	*
3836	* @returns VBox status code.
3837	*
3838	* @param pDevIns The device instance.
3839	* @param pvUser User argument.
3840	* @param GCPhysAddr Physical address (in GC) where the read starts.
3841	* @param pv Where to store the result.
3842	* @param cb Number of bytes read.
3843	*/
3844	PDMBOTHCBDECL(int) pcnetMMIORead(PPDMDEVINS pDevIns, void *pvUser,
3845	RTGCPHYS GCPhysAddr, void *pv, unsigned cb)
3846	{
3847	PCNetState pThis = (PCNetState )pvUser;
3848	int rc = VINF_SUCCESS;
3849
3850	/*
3851	* We have to check the range, because we're page aligning the MMIO stuff presently.
3852	*/
3853	if (GCPhysAddr - pThis->MMIOBase < PCNET_PNPMMIO_SIZE)
3854	{
3855	STAM_PROFILE_ADV_START(&pThis->CTXSUFF(StatMMIORead), a);
3856	rc = PDMCritSectEnter(&pThis->CritSect, VINF_IOM_HC_MMIO_READ);
3857	if (RT_LIKELY(rc == VINF_SUCCESS))
3858	{
3859	switch (cb)
3860	{
3861	case 1: (uint8_t )pv = pcnetMMIOReadU8 (pThis, GCPhysAddr); break;
3862	case 2: (uint16_t )pv = pcnetMMIOReadU16(pThis, GCPhysAddr); break;
3863	case 4: (uint32_t )pv = pcnetMMIOReadU32(pThis, GCPhysAddr); break;
3864	default:
3865	rc = PDMDevHlpDBGFStop(pThis->CTX_SUFF(pDevIns), RT_SRC_POS,
3866	"pcnetMMIORead: unsupported op size: address=%RGp cb=%u\n",
3867	GCPhysAddr, cb);
3868	}
3869	PDMCritSectLeave(&pThis->CritSect);
3870	}
3871	STAM_PROFILE_ADV_STOP(&pThis->CTXSUFF(StatMMIORead), a);
3872	}
3873	else
3874	memset(pv, 0, cb);
3875
3876	LogFlow(("#%d pcnetMMIORead: pvUser=%p:{%.*Rhxs} cb=%d GCPhysAddr=%RGp rc=%Rrc\n",
3877	PCNET_INST_NR, pv, cb, pv, cb, GCPhysAddr, rc));
3878	#ifdef LOG_ENABLED
3879	if (rc == VINF_IOM_HC_MMIO_READ)
3880	LogFlow(("#%d => HC\n", PCNET_INST_NR));
3881	#endif
3882	return rc;
3883	}
3884
3885
3886	/**
3887	* Port I/O Handler for write operations.
3888	*
3889	* @returns VBox status code.
3890	*
3891	* @param pDevIns The device instance.
3892	* @param pvUser User argument.
3893	* @param GCPhysAddr Physical address (in GC) where the read starts.
3894	* @param pv Where to fetch the result.
3895	* @param cb Number of bytes to write.
3896	*/
3897	PDMBOTHCBDECL(int) pcnetMMIOWrite(PPDMDEVINS pDevIns, void *pvUser,
3898	RTGCPHYS GCPhysAddr, void *pv, unsigned cb)
3899	{
3900	PCNetState pThis = (PCNetState )pvUser;
3901	int rc = VINF_SUCCESS;
3902
3903	/*
3904	* We have to check the range, because we're page aligning the MMIO stuff presently.
3905	*/
3906	if (GCPhysAddr - pThis->MMIOBase < PCNET_PNPMMIO_SIZE)
3907	{
3908	STAM_PROFILE_ADV_START(&pThis->CTXSUFF(StatMMIOWrite), a);
3909	rc = PDMCritSectEnter(&pThis->CritSect, VINF_IOM_HC_MMIO_WRITE);
3910	if (RT_LIKELY(rc == VINF_SUCCESS))
3911	{
3912	switch (cb)
3913	{
3914	case 1: pcnetMMIOWriteU8 (pThis, GCPhysAddr, (uint8_t )pv); break;
3915	case 2: pcnetMMIOWriteU16(pThis, GCPhysAddr, (uint16_t )pv); break;
3916	case 4: pcnetMMIOWriteU32(pThis, GCPhysAddr, (uint32_t )pv); break;
3917	default:
3918	rc = PDMDevHlpDBGFStop(pThis->CTX_SUFF(pDevIns), RT_SRC_POS,
3919	"pcnetMMIOWrite: unsupported op size: address=%RGp cb=%u\n",
3920	GCPhysAddr, cb);
3921	}
3922	PDMCritSectLeave(&pThis->CritSect);
3923	}
3924	// else rc == VINF_IOM_HC_MMIO_WRITE => handle in ring3
3925
3926	STAM_PROFILE_ADV_STOP(&pThis->CTXSUFF(StatMMIOWrite), a);
3927	}
3928	LogFlow(("#%d pcnetMMIOWrite: pvUser=%p:{%.*Rhxs} cb=%d GCPhysAddr=%RGp rc=%Rrc\n",
3929	PCNET_INST_NR, pv, cb, pv, cb, GCPhysAddr, rc));
3930	#ifdef LOG_ENABLED
3931	if (rc == VINF_IOM_HC_MMIO_WRITE)
3932	LogFlow(("#%d => HC\n", PCNET_INST_NR));
3933	#endif
3934	return rc;
3935	}
3936
3937
3938	#ifdef IN_RING3
3939	/**
3940	* Device timer callback function.
3941	*
3942	* @param pDevIns Device instance of the device which registered the timer.
3943	* @param pTimer The timer handle.
3944	* @thread EMT
3945	*/
3946	static DECLCALLBACK(void) pcnetTimer(PPDMDEVINS pDevIns, PTMTIMER pTimer, void *pvUser)
3947	{
3948	PCNetState pThis = (PCNetState )pvUser;
3949	STAM_PROFILE_ADV_START(&pThis->StatTimer, a);
3950	pcnetPollTimer(pThis);
3951	STAM_PROFILE_ADV_STOP(&pThis->StatTimer, a);
3952	}
3953
3954
3955	/**
3956	* Software interrupt timer callback function.
3957	*
3958	* @param pDevIns Device instance of the device which registered the timer.
3959	* @param pTimer The timer handle.
3960	* @thread EMT
3961	*/
3962	static DECLCALLBACK(void) pcnetTimerSoftInt(PPDMDEVINS pDevIns, PTMTIMER pTimer, void *pvUser)
3963	{
3964	PCNetState pThis = (PCNetState )pvUser;
3965
3966	/** @todo why aren't we taking any critsect here?!? */
3967	pThis->aCSR[7] \|= 0x0800; /* STINT */
3968	pcnetUpdateIrq(pThis);
3969	TMTimerSetNano(pThis->CTX_SUFF(pTimerSoftInt), 12800U * (pThis->aBCR[BCR_STVAL] & 0xffff));
3970	}
3971
3972
3973	/**
3974	* Restore timer callback.
3975	*
3976	* This is only called when've restored a saved state and temporarily
3977	* disconnected the network link to inform the guest that network connections
3978	* should be considered lost.
3979	*
3980	* @param pDevIns Device instance of the device which registered the timer.
3981	* @param pTimer The timer handle.
3982	*/
3983	static DECLCALLBACK(void) pcnetTimerRestore(PPDMDEVINS pDevIns, PTMTIMER pTimer, void *pvUser)
3984	{
3985	PCNetState pThis = PDMINS_2_DATA(pDevIns, PCNetState );
3986	int rc = PDMCritSectEnter(&pThis->CritSect, VERR_SEM_BUSY);
3987	AssertReleaseRC(rc);
3988
3989	rc = VERR_GENERAL_FAILURE;
3990	if (pThis->cLinkDownReported <= PCNET_MAX_LINKDOWN_REPORTED)
3991	rc = TMTimerSetMillies(pThis->pTimerRestore, 1500);
3992	if (RT_FAILURE(rc))
3993	{
3994	pThis->fLinkTempDown = false;
3995	if (pThis->fLinkUp)
3996	{
3997	LogRel(("PCNet#%d: The link is back up again after the restore.\n",
3998	pDevIns->iInstance));
3999	Log(("#%d pcnetTimerRestore: Clearing ERR and CERR after load. cLinkDownReported=%d\n",
4000	pDevIns->iInstance, pThis->cLinkDownReported));
4001	pThis->aCSR[0] &= ~(RT_BIT(15) \| RT_BIT(13)); /* ERR \| CERR - probably not 100% correct either... */
4002	pThis->Led.Actual.s.fError = 0;
4003	}
4004	}
4005	else
4006	Log(("#%d pcnetTimerRestore: cLinkDownReported=%d, wait another 1500ms...\n",
4007	pDevIns->iInstance, pThis->cLinkDownReported));
4008
4009	PDMCritSectLeave(&pThis->CritSect);
4010	}
4011
4012	/**
4013	* Callback function for mapping an PCI I/O region.
4014	*
4015	* @return VBox status code.
4016	* @param pPciDev Pointer to PCI device. Use pPciDev->pDevIns to get the device instance.
4017	* @param iRegion The region number.
4018	* @param GCPhysAddress Physical address of the region. If iType is PCI_ADDRESS_SPACE_IO, this is an
4019	* I/O port, else it's a physical address.
4020	* This address is NOT relative to pci_mem_base like earlier!
4021	* @param cb Region size.
4022	* @param enmType One of the PCI_ADDRESS_SPACE_* values.
4023	*/
4024	static DECLCALLBACK(int) pcnetIOPortMap(PPCIDEVICE pPciDev, /unsigned/ int iRegion,
4025	RTGCPHYS GCPhysAddress, uint32_t cb, PCIADDRESSSPACE enmType)
4026	{
4027	int rc;
4028	PPDMDEVINS pDevIns = pPciDev->pDevIns;
4029	RTIOPORT Port = (RTIOPORT)GCPhysAddress;
4030	PCNetState *pThis = PCIDEV_2_PCNETSTATE(pPciDev);
4031
4032	Assert(enmType == PCI_ADDRESS_SPACE_IO);
4033	Assert(cb >= 0x20);
4034
4035	rc = PDMDevHlpIOPortRegister(pDevIns, Port, 0x10, 0, pcnetIOPortAPromWrite,
4036	pcnetIOPortAPromRead, NULL, NULL, "PCNet ARPOM");
4037	if (RT_FAILURE(rc))
4038	return rc;
4039	rc = PDMDevHlpIOPortRegister(pDevIns, Port + 0x10, 0x10, 0, pcnetIOPortWrite,
4040	pcnetIOPortRead, NULL, NULL, "PCNet");
4041	if (RT_FAILURE(rc))
4042	return rc;
4043
4044	if (pThis->fGCEnabled)
4045	{
4046	rc = PDMDevHlpIOPortRegisterRC(pDevIns, Port, 0x10, 0, "pcnetIOPortAPromWrite",
4047	"pcnetIOPortAPromRead", NULL, NULL, "PCNet aprom");
4048	if (RT_FAILURE(rc))
4049	return rc;
4050	rc = PDMDevHlpIOPortRegisterRC(pDevIns, Port + 0x10, 0x10, 0, "pcnetIOPortWrite",
4051	"pcnetIOPortRead", NULL, NULL, "PCNet");
4052	if (RT_FAILURE(rc))
4053	return rc;
4054	}
4055	if (pThis->fR0Enabled)
4056	{
4057	rc = PDMDevHlpIOPortRegisterR0(pDevIns, Port, 0x10, 0, "pcnetIOPortAPromWrite",
4058	"pcnetIOPortAPromRead", NULL, NULL, "PCNet aprom");
4059	if (RT_FAILURE(rc))
4060	return rc;
4061	rc = PDMDevHlpIOPortRegisterR0(pDevIns, Port + 0x10, 0x10, 0, "pcnetIOPortWrite",
4062	"pcnetIOPortRead", NULL, NULL, "PCNet");
4063	if (RT_FAILURE(rc))
4064	return rc;
4065	}
4066
4067	pThis->IOPortBase = Port;
4068	return VINF_SUCCESS;
4069	}
4070
4071
4072	/**
4073	* Callback function for mapping the MMIO region.
4074	*
4075	* @return VBox status code.
4076	* @param pPciDev Pointer to PCI device. Use pPciDev->pDevIns to get the device instance.
4077	* @param iRegion The region number.
4078	* @param GCPhysAddress Physical address of the region. If iType is PCI_ADDRESS_SPACE_IO, this is an
4079	* I/O port, else it's a physical address.
4080	* This address is NOT relative to pci_mem_base like earlier!
4081	* @param cb Region size.
4082	* @param enmType One of the PCI_ADDRESS_SPACE_* values.
4083	*/
4084	static DECLCALLBACK(int) pcnetMMIOMap(PPCIDEVICE pPciDev, /unsigned/ int iRegion,
4085	RTGCPHYS GCPhysAddress, uint32_t cb, PCIADDRESSSPACE enmType)
4086	{
4087	PCNetState *pThis = PCIDEV_2_PCNETSTATE(pPciDev);
4088	int rc;
4089
4090	Assert(enmType == PCI_ADDRESS_SPACE_MEM);
4091	Assert(cb >= PCNET_PNPMMIO_SIZE);
4092
4093	/* We use the assigned size here, because we currently only support page aligned MMIO ranges. */
4094	rc = PDMDevHlpMMIORegister(pPciDev->pDevIns, GCPhysAddress, cb, pThis,
4095	pcnetMMIOWrite, pcnetMMIORead, NULL, "PCNet");
4096	if (RT_FAILURE(rc))
4097	return rc;
4098	pThis->MMIOBase = GCPhysAddress;
4099	return rc;
4100	}
4101
4102
4103	/**
4104	* Callback function for mapping the MMIO region.
4105	*
4106	* @return VBox status code.
4107	* @param pPciDev Pointer to PCI device. Use pPciDev->pDevIns to get the device instance.
4108	* @param iRegion The region number.
4109	* @param GCPhysAddress Physical address of the region. If iType is PCI_ADDRESS_SPACE_IO, this is an
4110	* I/O port, else it's a physical address.
4111	* This address is NOT relative to pci_mem_base like earlier!
4112	* @param cb Region size.
4113	* @param enmType One of the PCI_ADDRESS_SPACE_* values.
4114	*/
4115	static DECLCALLBACK(int) pcnetMMIOSharedMap(PPCIDEVICE pPciDev, /unsigned/ int iRegion,
4116	RTGCPHYS GCPhysAddress, uint32_t cb, PCIADDRESSSPACE enmType)
4117	{
4118	if (GCPhysAddress != NIL_RTGCPHYS)
4119	return PDMDevHlpMMIO2Map(pPciDev->pDevIns, iRegion, GCPhysAddress);
4120
4121	/* nothing to clean up */
4122	return VINF_SUCCESS;
4123	}
4124
4125
4126	/**
4127	* PCNET status info callback.
4128	*
4129	* @param pDevIns The device instance.
4130	* @param pHlp The output helpers.
4131	* @param pszArgs The arguments.
4132	*/
4133	static DECLCALLBACK(void) pcnetInfo(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
4134	{
4135	PCNetState pThis = PDMINS_2_DATA(pDevIns, PCNetState );
4136	bool fRcvRing = false;
4137	bool fXmtRing = false;
4138
4139	/*
4140	* Parse args.
4141	*/
4142	if (pszArgs)
4143	{
4144	fRcvRing = strstr(pszArgs, "verbose") \|\| strstr(pszArgs, "rcv");
4145	fXmtRing = strstr(pszArgs, "verbose") \|\| strstr(pszArgs, "xmt");
4146	}
4147
4148	/*
4149	* Show info.
4150	*/
4151	pHlp->pfnPrintf(pHlp,
4152	"pcnet #%d: port=%RTiop mmio=%RX32 mac-cfg=%RTmac %s\n",
4153	pDevIns->iInstance,
4154	pThis->IOPortBase, pThis->MMIOBase, &pThis->MacConfigured,
4155	pThis->fAm79C973 ? "Am79C973" : "Am79C970A", pThis->fGCEnabled ? " GC" : "", pThis->fR0Enabled ? " R0" : "");
4156
4157	PDMCritSectEnter(&pThis->CritSect, VERR_INTERNAL_ERROR); /* Take it here so we know why we're hanging... */
4158
4159	pHlp->pfnPrintf(pHlp,
4160	"CSR0=%#06x:\n",
4161	pThis->aCSR[0]);
4162
4163	pHlp->pfnPrintf(pHlp,
4164	"CSR1=%#06x:\n",
4165	pThis->aCSR[1]);
4166
4167	pHlp->pfnPrintf(pHlp,
4168	"CSR2=%#06x:\n",
4169	pThis->aCSR[2]);
4170
4171	pHlp->pfnPrintf(pHlp,
4172	"CSR3=%#06x: BSWP=%d EMBA=%d DXMT2PD=%d LAPPEN=%d DXSUFLO=%d IDONM=%d TINTM=%d RINTM=%d MERRM=%d MISSM=%d BABLM=%d\n",
4173	pThis->aCSR[3],
4174	!!(pThis->aCSR[3] & RT_BIT(2)), !!(pThis->aCSR[3] & RT_BIT(3)), !!(pThis->aCSR[3] & RT_BIT(4)), CSR_LAPPEN(pThis),
4175	CSR_DXSUFLO(pThis), !!(pThis->aCSR[3] & RT_BIT(8)), !!(pThis->aCSR[3] & RT_BIT(9)), !!(pThis->aCSR[3] & RT_BIT(10)),
4176	!!(pThis->aCSR[3] & RT_BIT(11)), !!(pThis->aCSR[3] & RT_BIT(12)), !!(pThis->aCSR[3] & RT_BIT(14)));
4177
4178	pHlp->pfnPrintf(pHlp,
4179	"CSR4=%#06x: JABM=%d JAB=%d TXSTRM=%d TXSTRT=%d RCVCOOM=%d RCVCCO=%d UINT=%d UINTCMD=%d\n"
4180	" MFCOM=%d MFCO=%d ASTRP_RCV=%d APAD_XMT=%d DPOLL=%d TIMER=%d EMAPLUS=%d EN124=%d\n",
4181	pThis->aCSR[4],
4182	!!(pThis->aCSR[4] & RT_BIT( 0)), !!(pThis->aCSR[4] & RT_BIT( 1)), !!(pThis->aCSR[4] & RT_BIT( 2)), !!(pThis->aCSR[4] & RT_BIT( 3)),
4183	!!(pThis->aCSR[4] & RT_BIT( 4)), !!(pThis->aCSR[4] & RT_BIT( 5)), !!(pThis->aCSR[4] & RT_BIT( 6)), !!(pThis->aCSR[4] & RT_BIT( 7)),
4184	!!(pThis->aCSR[4] & RT_BIT( 8)), !!(pThis->aCSR[4] & RT_BIT( 9)), !!(pThis->aCSR[4] & RT_BIT(10)), !!(pThis->aCSR[4] & RT_BIT(11)),
4185	!!(pThis->aCSR[4] & RT_BIT(12)), !!(pThis->aCSR[4] & RT_BIT(13)), !!(pThis->aCSR[4] & RT_BIT(14)), !!(pThis->aCSR[4] & RT_BIT(15)));
4186
4187	pHlp->pfnPrintf(pHlp,
4188	"CSR5=%#06x:\n",
4189	pThis->aCSR[5]);
4190
4191	pHlp->pfnPrintf(pHlp,
4192	"CSR6=%#06x: RLEN=%#x* TLEN=%#x* [* encoded]\n",
4193	pThis->aCSR[6],
4194	(pThis->aCSR[6] >> 8) & 0xf, (pThis->aCSR[6] >> 12) & 0xf);
4195
4196	pHlp->pfnPrintf(pHlp,
4197	"CSR8..11=%#06x,%#06x,%#06x,%#06x: LADRF=%#018llx\n",
4198	pThis->aCSR[8], pThis->aCSR[9], pThis->aCSR[10], pThis->aCSR[11],
4199	(uint64_t)(pThis->aCSR[ 8] & 0xffff)
4200	\| (uint64_t)(pThis->aCSR[ 9] & 0xffff) << 16
4201	\| (uint64_t)(pThis->aCSR[10] & 0xffff) << 32
4202	\| (uint64_t)(pThis->aCSR[11] & 0xffff) << 48);
4203
4204	pHlp->pfnPrintf(pHlp,
4205	"CSR12..14=%#06x,%#06x,%#06x: PADR=%02x:%02x:%02x:%02x:%02x:%02x (Current MAC Address)\n",
4206	pThis->aCSR[12], pThis->aCSR[13], pThis->aCSR[14],
4207	pThis->aCSR[12] & 0xff,
4208	(pThis->aCSR[12] >> 8) & 0xff,
4209	pThis->aCSR[13] & 0xff,
4210	(pThis->aCSR[13] >> 8) & 0xff,
4211	pThis->aCSR[14] & 0xff,
4212	(pThis->aCSR[14] >> 8) & 0xff);
4213
4214	pHlp->pfnPrintf(pHlp,
4215	"CSR15=%#06x: DXR=%d DTX=%d LOOP=%d DXMTFCS=%d FCOLL=%d DRTY=%d INTL=%d PORTSEL=%d LTR=%d\n"
4216	" MENDECL=%d DAPC=%d DLNKTST=%d DRCVPV=%d DRCVBC=%d PROM=%d\n",
4217	pThis->aCSR[15],
4218	!!(pThis->aCSR[15] & RT_BIT( 0)), !!(pThis->aCSR[15] & RT_BIT( 1)), !!(pThis->aCSR[15] & RT_BIT( 2)), !!(pThis->aCSR[15] & RT_BIT( 3)),
4219	!!(pThis->aCSR[15] & RT_BIT( 4)), !!(pThis->aCSR[15] & RT_BIT( 5)), !!(pThis->aCSR[15] & RT_BIT( 6)), (pThis->aCSR[15] >> 7) & 3,
4220	!!(pThis->aCSR[15] & RT_BIT( 9)), !!(pThis->aCSR[15] & RT_BIT(10)), !!(pThis->aCSR[15] & RT_BIT(11)),
4221	!!(pThis->aCSR[15] & RT_BIT(12)), !!(pThis->aCSR[15] & RT_BIT(13)), !!(pThis->aCSR[15] & RT_BIT(14)), !!(pThis->aCSR[15] & RT_BIT(15)));
4222
4223	pHlp->pfnPrintf(pHlp,
4224	"CSR46=%#06x: POLL=%#06x (Poll Time Counter)\n",
4225	pThis->aCSR[46], pThis->aCSR[46] & 0xffff);
4226
4227	pHlp->pfnPrintf(pHlp,
4228	"CSR47=%#06x: POLLINT=%#06x (Poll Time Interval)\n",
4229	pThis->aCSR[47], pThis->aCSR[47] & 0xffff);
4230
4231	pHlp->pfnPrintf(pHlp,
4232	"CSR58=%#06x: SWSTYLE=%d %s SSIZE32=%d CSRPCNET=%d APERRENT=%d\n",
4233	pThis->aCSR[58],
4234	pThis->aCSR[58] & 0x7f,
4235	(pThis->aCSR[58] & 0x7f) == 0 ? "C-LANCE / PCnet-ISA"
4236	: (pThis->aCSR[58] & 0x7f) == 1 ? "ILACC"
4237	: (pThis->aCSR[58] & 0x7f) == 2 ? "PCNet-PCI II"
4238	: (pThis->aCSR[58] & 0x7f) == 3 ? "PCNet-PCI II controller"
4239	: "!!reserved!!",
4240	!!(pThis->aCSR[58] & RT_BIT(8)), !!(pThis->aCSR[58] & RT_BIT(9)), !!(pThis->aCSR[58] & RT_BIT(10)));
4241
4242	pHlp->pfnPrintf(pHlp,
4243	"CSR112=%04RX32: MFC=%04x (Missed receive Frame Count)\n",
4244	pThis->aCSR[112], pThis->aCSR[112] & 0xffff);
4245
4246	pHlp->pfnPrintf(pHlp,
4247	"CSR122=%04RX32: RCVALGN=%04x (Receive Frame Align)\n",
4248	pThis->aCSR[122], !!(pThis->aCSR[122] & RT_BIT(0)));
4249
4250	pHlp->pfnPrintf(pHlp,
4251	"CSR124=%04RX32: RPA=%04x (Runt Packet Accept)\n",
4252	pThis->aCSR[122], !!(pThis->aCSR[122] & RT_BIT(3)));
4253
4254
4255	/*
4256	* Dump the receive ring.
4257	*/
4258	pHlp->pfnPrintf(pHlp,
4259	"RCVRL=%04x RCVRC=%04x GCRDRA=%RX32 \n"
4260	"CRDA=%08RX32 CRBA=%08RX32 CRBC=%03x CRST=%04x\n"
4261	"NRDA=%08RX32 NRBA=%08RX32 NRBC=%03x NRST=%04x\n"
4262	"NNRDA=%08RX32\n"
4263	,
4264	CSR_RCVRL(pThis), CSR_RCVRC(pThis), pThis->GCRDRA,
4265	CSR_CRDA(pThis), CSR_CRBA(pThis), CSR_CRBC(pThis), CSR_CRST(pThis),
4266	CSR_NRDA(pThis), CSR_NRBA(pThis), CSR_NRBC(pThis), CSR_NRST(pThis),
4267	CSR_NNRD(pThis));
4268	if (fRcvRing)
4269	{
4270	const unsigned cb = 1 << pThis->iLog2DescSize;
4271	RTGCPHYS32 GCPhys = pThis->GCRDRA;
4272	unsigned i = CSR_RCVRL(pThis);
4273	while (i-- > 0)
4274	{
4275	RMD rmd;
4276	pcnetRmdLoad(pThis, &rmd, PHYSADDR(pThis, GCPhys), false);
4277	pHlp->pfnPrintf(pHlp,
4278	"%04x %RX32:%c%c RBADR=%08RX32 BCNT=%03x MCNT=%03x "
4279	"OWN=%d ERR=%d FRAM=%d OFLO=%d CRC=%d BUFF=%d STP=%d ENP=%d BPE=%d "
4280	"PAM=%d LAFM=%d BAM=%d RCC=%02x RPC=%02x ONES=%#x ZEROS=%d\n",
4281	i, GCPhys, i + 1 == CSR_RCVRC(pThis) ? '' : ' ', GCPhys == CSR_CRDA(pThis) ? '' : ' ',
4282	rmd.rmd0.rbadr, 4096 - rmd.rmd1.bcnt, rmd.rmd2.mcnt,
4283	rmd.rmd1.own, rmd.rmd1.err, rmd.rmd1.fram, rmd.rmd1.oflo, rmd.rmd1.crc, rmd.rmd1.buff,
4284	rmd.rmd1.stp, rmd.rmd1.enp, rmd.rmd1.bpe,
4285	rmd.rmd1.pam, rmd.rmd1.lafm, rmd.rmd1.bam, rmd.rmd2.rcc, rmd.rmd2.rpc,
4286	rmd.rmd1.ones, rmd.rmd2.zeros);
4287
4288	GCPhys += cb;
4289	}
4290	}
4291
4292	/*
4293	* Dump the transmit ring.
4294	*/
4295	pHlp->pfnPrintf(pHlp,
4296	"XMTRL=%04x XMTRC=%04x GCTDRA=%08RX32 BADX=%08RX32\n"
4297	"PXDA=%08RX32 PXBC=%03x PXST=%04x\n"
4298	"CXDA=%08RX32 CXBA=%08RX32 CXBC=%03x CXST=%04x\n"
4299	"NXDA=%08RX32 NXBA=%08RX32 NXBC=%03x NXST=%04x\n"
4300	"NNXDA=%08RX32\n"
4301	,
4302	CSR_XMTRL(pThis), CSR_XMTRC(pThis),
4303	pThis->GCTDRA, CSR_BADX(pThis),
4304	CSR_PXDA(pThis), CSR_PXBC(pThis), CSR_PXST(pThis),
4305	CSR_CXDA(pThis), CSR_CXBA(pThis), CSR_CXBC(pThis), CSR_CXST(pThis),
4306	CSR_NXDA(pThis), CSR_NXBA(pThis), CSR_NXBC(pThis), CSR_NXST(pThis),
4307	CSR_NNXD(pThis));
4308	if (fXmtRing)
4309	{
4310	const unsigned cb = 1 << pThis->iLog2DescSize;
4311	RTGCPHYS32 GCPhys = pThis->GCTDRA;
4312	unsigned i = CSR_XMTRL(pThis);
4313	while (i-- > 0)
4314	{
4315	TMD tmd;
4316	pcnetTmdLoad(pThis, &tmd, PHYSADDR(pThis, GCPhys), false);
4317	pHlp->pfnPrintf(pHlp,
4318	"%04x %RX32:%c%c TBADR=%08RX32 BCNT=%03x OWN=%d "
4319	"ERR=%d NOFCS=%d LTINT=%d ONE=%d DEF=%d STP=%d ENP=%d BPE=%d "
4320	"BUFF=%d UFLO=%d EXDEF=%d LCOL=%d LCAR=%d RTRY=%d TDR=%03x TRC=%#x ONES=%#x\n"
4321	,
4322	i, GCPhys, i + 1 == CSR_XMTRC(pThis) ? '' : ' ', GCPhys == CSR_CXDA(pThis) ? '' : ' ',
4323	tmd.tmd0.tbadr, 4096 - tmd.tmd1.bcnt,
4324	tmd.tmd2.tdr,
4325	tmd.tmd2.trc,
4326	tmd.tmd1.own,
4327	tmd.tmd1.err,
4328	tmd.tmd1.nofcs,
4329	tmd.tmd1.ltint,
4330	tmd.tmd1.one,
4331	tmd.tmd1.def,
4332	tmd.tmd1.stp,
4333	tmd.tmd1.enp,
4334	tmd.tmd1.bpe,
4335	tmd.tmd2.buff,
4336	tmd.tmd2.uflo,
4337	tmd.tmd2.exdef,
4338	tmd.tmd2.lcol,
4339	tmd.tmd2.lcar,
4340	tmd.tmd2.rtry,
4341	tmd.tmd2.tdr,
4342	tmd.tmd2.trc,
4343	tmd.tmd1.ones);
4344
4345	GCPhys += cb;
4346	}
4347	}
4348
4349	PDMCritSectLeave(&pThis->CritSect);
4350	}
4351
4352
4353	/**
4354	* Takes down the link temporarily if it's current status is up.
4355	*
4356	* This is used during restore and when replumbing the network link.
4357	*
4358	* The temporary link outage is supposed to indicate to the OS that all network
4359	* connections have been lost and that it for instance is appropriate to
4360	* renegotiate any DHCP lease.
4361	*
4362	* @param pThis The PCNet instance data.
4363	*/
4364	static void pcnetTempLinkDown(PCNetState *pThis)
4365	{
4366	if (pThis->fLinkUp)
4367	{
4368	pThis->fLinkTempDown = true;
4369	pThis->cLinkDownReported = 0;
4370	pThis->aCSR[0] \|= RT_BIT(15) \| RT_BIT(13); /* ERR \| CERR (this is probably wrong) */
4371	pThis->Led.Asserted.s.fError = pThis->Led.Actual.s.fError = 1;
4372	int rc = TMTimerSetMillies(pThis->pTimerRestore, 5000);
4373	AssertRC(rc);
4374	}
4375	}
4376
4377
4378	/**
4379	* Saves the configuration.
4380	*
4381	* @param pThis The PCNet instance data.
4382	* @param pSSM The saved state handle.
4383	*/
4384	static void pcnetSaveConfig(PCNetState *pThis, PSSMHANDLE pSSM)
4385	{
4386	SSMR3PutMem(pSSM, &pThis->MacConfigured, sizeof(pThis->MacConfigured));
4387	SSMR3PutBool(pSSM, pThis->fAm79C973); /* >= If version 0.8 */
4388	SSMR3PutU32(pSSM, pThis->u32LinkSpeed);
4389	}
4390
4391
4392	/**
4393	* Live Save, pass 0.
4394	*
4395	* @returns VBox status code.
4396	* @param pDevIns The device instance.
4397	* @param pSSM The saved state handle.
4398	* @param uPass The pass number.
4399	*/
4400	static DECLCALLBACK(int) pcnetLiveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t uPass)
4401	{
4402	PCNetState pThis = PDMINS_2_DATA(pDevIns, PCNetState );
4403	pcnetSaveConfig(pThis, pSSM);
4404	return VINF_SSM_DONT_CALL_AGAIN;
4405	}
4406
4407
4408	/**
4409	* Serializes the receive thread, it may be working inside the critsect.
4410	*
4411	* @returns VBox status code.
4412	* @param pDevIns The device instance.
4413	* @param pSSM The saved state handle.
4414	*/
4415	static DECLCALLBACK(int) pcnetSavePrep(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
4416	{
4417	PCNetState pThis = PDMINS_2_DATA(pDevIns, PCNetState );
4418
4419	int rc = PDMCritSectEnter(&pThis->CritSect, VERR_SEM_BUSY);
4420	AssertRC(rc);
4421	PDMCritSectLeave(&pThis->CritSect);
4422
4423	return VINF_SUCCESS;
4424	}
4425
4426
4427	/**
4428	* Saves a state of the PC-Net II device.
4429	*
4430	* @returns VBox status code.
4431	* @param pDevIns The device instance.
4432	* @param pSSM The saved state handle.
4433	*/
4434	static DECLCALLBACK(int) pcnetSaveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
4435	{
4436	PCNetState pThis = PDMINS_2_DATA(pDevIns, PCNetState );
4437
4438	SSMR3PutBool(pSSM, pThis->fLinkUp);
4439	SSMR3PutU32(pSSM, pThis->u32RAP);
4440	SSMR3PutS32(pSSM, pThis->iISR);
4441	SSMR3PutU32(pSSM, pThis->u32Lnkst);
4442	SSMR3PutBool(pSSM, pThis->fPrivIfEnabled); /* >= If version 0.9 */
4443	SSMR3PutBool(pSSM, pThis->fSignalRxMiss); /* >= If version 0.10 */
4444	SSMR3PutGCPhys32(pSSM, pThis->GCRDRA);
4445	SSMR3PutGCPhys32(pSSM, pThis->GCTDRA);
4446	SSMR3PutMem(pSSM, pThis->aPROM, sizeof(pThis->aPROM));
4447	SSMR3PutMem(pSSM, pThis->aCSR, sizeof(pThis->aCSR));
4448	SSMR3PutMem(pSSM, pThis->aBCR, sizeof(pThis->aBCR));
4449	SSMR3PutMem(pSSM, pThis->aMII, sizeof(pThis->aMII));
4450	SSMR3PutU16(pSSM, pThis->u16CSR0LastSeenByGuest);
4451	SSMR3PutU64(pSSM, pThis->u64LastPoll);
4452	pcnetSaveConfig(pThis, pSSM);
4453
4454	int rc = VINF_SUCCESS;
4455	#ifndef PCNET_NO_POLLING
4456	rc = TMR3TimerSave(pThis->CTX_SUFF(pTimerPoll), pSSM);
4457	if (RT_FAILURE(rc))
4458	return rc;
4459	#endif
4460	if (pThis->fAm79C973)
4461	rc = TMR3TimerSave(pThis->CTX_SUFF(pTimerSoftInt), pSSM);
4462	return rc;
4463	}
4464
4465
4466	/**
4467	* Serializes the receive thread, it may be working inside the critsect.
4468	*
4469	* @returns VBox status code.
4470	* @param pDevIns The device instance.
4471	* @param pSSM The saved state handle.
4472	*/
4473	static DECLCALLBACK(int) pcnetLoadPrep(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
4474	{
4475	PCNetState pThis = PDMINS_2_DATA(pDevIns, PCNetState );
4476
4477	int rc = PDMCritSectEnter(&pThis->CritSect, VERR_SEM_BUSY);
4478	AssertRC(rc);
4479	PDMCritSectLeave(&pThis->CritSect);
4480
4481	return VINF_SUCCESS;
4482	}
4483
4484
4485	/**
4486	* Loads a saved PC-Net II device state.
4487	*
4488	* @returns VBox status code.
4489	* @param pDevIns The device instance.
4490	* @param pSSM The handle to the saved state.
4491	* @param uVersion The data unit version number.
4492	* @param uPass The data pass.
4493	*/
4494	static DECLCALLBACK(int) pcnetLoadExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
4495	{
4496	PCNetState pThis = PDMINS_2_DATA(pDevIns, PCNetState );
4497
4498	if ( SSM_VERSION_MAJOR_CHANGED(uVersion, PCNET_SAVEDSTATE_VERSION)
4499	\|\| SSM_VERSION_MINOR(uVersion) < 7)
4500	return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
4501
4502	if (uPass == SSM_PASS_FINAL)
4503	{
4504	/* restore data */
4505	SSMR3GetBool(pSSM, &pThis->fLinkUp);
4506	SSMR3GetU32(pSSM, &pThis->u32RAP);
4507	SSMR3GetS32(pSSM, &pThis->iISR);
4508	SSMR3GetU32(pSSM, &pThis->u32Lnkst);
4509	if ( SSM_VERSION_MAJOR(uVersion) > 0
4510	\|\| SSM_VERSION_MINOR(uVersion) >= 9)
4511	{
4512	SSMR3GetBool(pSSM, &pThis->fPrivIfEnabled);
4513	if (pThis->fPrivIfEnabled)
4514	LogRel(("PCNet#%d: Enabling private interface\n", PCNET_INST_NR));
4515	}
4516	if ( SSM_VERSION_MAJOR(uVersion) > 0
4517	\|\| SSM_VERSION_MINOR(uVersion) >= 10)
4518	{
4519	SSMR3GetBool(pSSM, &pThis->fSignalRxMiss);
4520	}
4521	SSMR3GetGCPhys32(pSSM, &pThis->GCRDRA);
4522	SSMR3GetGCPhys32(pSSM, &pThis->GCTDRA);
4523	SSMR3GetMem(pSSM, &pThis->aPROM, sizeof(pThis->aPROM));
4524	SSMR3GetMem(pSSM, &pThis->aCSR, sizeof(pThis->aCSR));
4525	SSMR3GetMem(pSSM, &pThis->aBCR, sizeof(pThis->aBCR));
4526	SSMR3GetMem(pSSM, &pThis->aMII, sizeof(pThis->aMII));
4527	SSMR3GetU16(pSSM, &pThis->u16CSR0LastSeenByGuest);
4528	SSMR3GetU64(pSSM, &pThis->u64LastPoll);
4529	}
4530
4531	/* check config */
4532	RTMAC Mac;
4533	int rc = SSMR3GetMem(pSSM, &Mac, sizeof(Mac));
4534	AssertRCReturn(rc, rc);
4535	if ( memcmp(&Mac, &pThis->MacConfigured, sizeof(Mac))
4536	&& (uPass == 0 \|\| !PDMDevHlpVMTeleportedAndNotFullyResumedYet(pDevIns)) )
4537	LogRel(("PCNet#%u: The mac address differs: config=%RTmac saved=%RTmac\n", PCNET_INST_NR, &pThis->MacConfigured, &Mac));
4538
4539	bool fAm79C973;
4540	rc = SSMR3GetBool(pSSM, &fAm79C973);
4541	AssertRCReturn(rc, rc);
4542	if (pThis->fAm79C973 != fAm79C973)
4543	return SSMR3SetCfgError(pSSM, RT_SRC_POS, N_("The fAm79C973 flag differs: config=%RTbool saved=%RTbool"), pThis->fAm79C973, fAm79C973);
4544
4545	uint32_t u32LinkSpeed;
4546	rc = SSMR3GetU32(pSSM, &u32LinkSpeed);
4547	AssertRCReturn(rc, rc);
4548	if ( pThis->u32LinkSpeed != u32LinkSpeed
4549	&& (uPass == 0 \|\| !PDMDevHlpVMTeleportedAndNotFullyResumedYet(pDevIns)) )
4550	LogRel(("PCNet#%u: The mac link speed differs: config=%u saved=%u\n", PCNET_INST_NR, pThis->u32LinkSpeed, u32LinkSpeed));
4551
4552	if (uPass == SSM_PASS_FINAL)
4553	{
4554	/* restore timers and stuff */
4555	#ifndef PCNET_NO_POLLING
4556	TMR3TimerLoad(pThis->CTX_SUFF(pTimerPoll), pSSM);
4557	#endif
4558	if (pThis->fAm79C973)
4559	{
4560	if ( SSM_VERSION_MAJOR(uVersion) > 0
4561	\|\| SSM_VERSION_MINOR(uVersion) >= 8)
4562	TMR3TimerLoad(pThis->CTX_SUFF(pTimerSoftInt), pSSM);
4563	}
4564
4565	pThis->iLog2DescSize = BCR_SWSTYLE(pThis)
4566	? 4
4567	: 3;
4568	pThis->GCUpperPhys = BCR_SSIZE32(pThis)
4569	? 0
4570	: (0xff00 & (uint32_t)pThis->aCSR[2]) << 16;
4571
4572	/* update promiscuous mode. */
4573	if (pThis->pDrvR3)
4574	pThis->pDrvR3->pfnSetPromiscuousMode(pThis->pDrvR3, CSR_PROM(pThis));
4575
4576	#ifdef PCNET_NO_POLLING
4577	/* Enable physical monitoring again (!) */
4578	pcnetUpdateRingHandlers(pThis);
4579	#endif
4580	/* Indicate link down to the guest OS that all network connections have
4581	been lost, unless we've been teleported here. */
4582	if (!PDMDevHlpVMTeleportedAndNotFullyResumedYet(pDevIns))
4583	pcnetTempLinkDown(pThis);
4584	}
4585
4586	return VINF_SUCCESS;
4587	}
4588
4589
4590	/**
4591	* @interface_method_impl{PDMIBASE,pfnQueryInterface}
4592	*/
4593	static DECLCALLBACK(void ) pcnetQueryInterface(struct PDMIBASE pInterface, const char *pszIID)
4594	{
4595	PCNetState *pThis = RT_FROM_MEMBER(pInterface, PCNetState, IBase);
4596	Assert(&pThis->IBase == pInterface);
4597	PDMIBASE_RETURN_INTERFACE(pszIID, PDMIBASE, &pThis->IBase);
4598	PDMIBASE_RETURN_INTERFACE(pszIID, PDMINETWORKDOWN, &pThis->INetworkDown);
4599	PDMIBASE_RETURN_INTERFACE(pszIID, PDMINETWORKCONFIG, &pThis->INetworkConfig);
4600	PDMIBASE_RETURN_INTERFACE(pszIID, PDMILEDPORTS, &pThis->ILeds);
4601	return NULL;
4602	}
4603
4604	/** Converts a pointer to PCNetState::INetworkDown to a PCNetState pointer. */
4605	#define INETWORKPORT_2_DATA(pInterface) ( (PCNetState *)((uintptr_t)pInterface - RT_OFFSETOF(PCNetState, INetworkDown)) )
4606
4607
4608	/**
4609	* Check if the device/driver can receive data now.
4610	* This must be called before the pfnRecieve() method is called.
4611	*
4612	* @returns VBox status code.
4613	* @param pInterface Pointer to the interface structure containing the called function pointer.
4614	*/
4615	static int pcnetCanReceive(PCNetState *pThis)
4616	{
4617	int rc = PDMCritSectEnter(&pThis->CritSect, VERR_SEM_BUSY);
4618	AssertReleaseRC(rc);
4619
4620	rc = VERR_NET_NO_BUFFER_SPACE;
4621
4622	if (RT_LIKELY(!CSR_DRX(pThis) && !CSR_STOP(pThis) && !CSR_SPND(pThis)))
4623	{
4624	if (HOST_IS_OWNER(CSR_CRST(pThis)) && pThis->GCRDRA)
4625	pcnetRdtePoll(pThis);
4626
4627	if (RT_UNLIKELY(HOST_IS_OWNER(CSR_CRST(pThis))))
4628	{
4629	/** @todo Notify the guest _now_. Will potentially increase the interrupt load */
4630	if (pThis->fSignalRxMiss)
4631	pThis->aCSR[0] \|= 0x1000; /* Set MISS flag */
4632	}
4633	else
4634	rc = VINF_SUCCESS;
4635	}
4636
4637	PDMCritSectLeave(&pThis->CritSect);
4638	return rc;
4639	}
4640
4641
4642	/**
4643	*
4644	*/
4645	static DECLCALLBACK(int) pcnetWaitReceiveAvail(PPDMINETWORKDOWN pInterface, RTMSINTERVAL cMillies)
4646	{
4647	PCNetState *pThis = INETWORKPORT_2_DATA(pInterface);
4648
4649	int rc = pcnetCanReceive(pThis);
4650	if (RT_SUCCESS(rc))
4651	return VINF_SUCCESS;
4652	if (RT_UNLIKELY(cMillies == 0))
4653	return VERR_NET_NO_BUFFER_SPACE;
4654
4655	rc = VERR_INTERRUPTED;
4656	ASMAtomicXchgBool(&pThis->fMaybeOutOfSpace, true);
4657	STAM_PROFILE_START(&pThis->StatRxOverflow, a);
4658	VMSTATE enmVMState;
4659	while (RT_LIKELY( (enmVMState = PDMDevHlpVMState(pThis->CTX_SUFF(pDevIns))) == VMSTATE_RUNNING
4660	\|\| enmVMState == VMSTATE_RUNNING_LS))
4661	{
4662	int rc2 = pcnetCanReceive(pThis);
4663	if (RT_SUCCESS(rc2))
4664	{
4665	rc = VINF_SUCCESS;
4666	break;
4667	}
4668	LogFlow(("pcnetWaitReceiveAvail: waiting cMillies=%u...\n", cMillies));
4669	/* Start the poll timer once which will remain active as long fMaybeOutOfSpace
4670	* is true -- even if (transmit) polling is disabled (CSR_DPOLL). */
4671	rc2 = PDMCritSectEnter(&pThis->CritSect, VERR_SEM_BUSY);
4672	AssertReleaseRC(rc2);
4673	pcnetPollTimerStart(pThis);
4674	PDMCritSectLeave(&pThis->CritSect);
4675	RTSemEventWait(pThis->hEventOutOfRxSpace, cMillies);
4676	}
4677	STAM_PROFILE_STOP(&pThis->StatRxOverflow, a);
4678	ASMAtomicXchgBool(&pThis->fMaybeOutOfSpace, false);
4679
4680	return rc;
4681	}
4682
4683
4684	/**
4685	* Receive data from the network.
4686	*
4687	* @returns VBox status code.
4688	* @param pInterface Pointer to the interface structure containing the called function pointer.
4689	* @param pvBuf The available data.
4690	* @param cb Number of bytes available in the buffer.
4691	* @thread EMT
4692	*/
4693	static DECLCALLBACK(int) pcnetReceive(PPDMINETWORKDOWN pInterface, const void *pvBuf, size_t cb)
4694	{
4695	PCNetState *pThis = INETWORKPORT_2_DATA(pInterface);
4696	int rc;
4697
4698	STAM_PROFILE_ADV_START(&pThis->StatReceive, a);
4699	rc = PDMCritSectEnter(&pThis->CritSect, VERR_SEM_BUSY);
4700	AssertReleaseRC(rc);
4701
4702	/*
4703	* Check for the max ethernet frame size, taking the IEEE 802.1Q (VLAN) tag into
4704	* account. Note that we are not expecting the CRC Checksum.
4705	* Ethernet frames consists of a 14-byte header [+ 4-byte vlan tag] + a 1500-byte body.
4706	*/
4707	if (RT_LIKELY( cb <= 1514
4708	\|\| ( cb <= 1518
4709	&& ((PCRTNETETHERHDR)pvBuf)->EtherType == RT_H2BE_U16_C(RTNET_ETHERTYPE_VLAN))))
4710	{
4711	if (cb > 70) /* unqualified guess */
4712	pThis->Led.Asserted.s.fReading = pThis->Led.Actual.s.fReading = 1;
4713	pcnetReceiveNoSync(pThis, (const uint8_t *)pvBuf, cb);
4714	pThis->Led.Actual.s.fReading = 0;
4715	}
4716	#ifdef LOG_ENABLED
4717	else
4718	{
4719	static bool s_fFirstBigFrameLoss = true;
4720	unsigned cbMaxFrame = ((PCRTNETETHERHDR)pvBuf)->EtherType == RT_H2BE_U16_C(RTNET_ETHERTYPE_VLAN)
4721	? 1518 : 1514;
4722	if (s_fFirstBigFrameLoss)
4723	{
4724	s_fFirstBigFrameLoss = false;
4725	Log(("PCNet#%d: Received giant frame %zu, max %u. (Further giants will be reported at level5.)\n",
4726	PCNET_INST_NR, cb, cbMaxFrame));
4727	}
4728	else
4729	Log5(("PCNet#%d: Received giant frame %zu bytes, max %u.\n",
4730	PCNET_INST_NR, cb, cbMaxFrame));
4731	}
4732	#endif /* LOG_ENABLED */
4733
4734	PDMCritSectLeave(&pThis->CritSect);
4735	STAM_PROFILE_ADV_STOP(&pThis->StatReceive, a);
4736
4737	return VINF_SUCCESS;
4738	}
4739
4740	/** Converts a pointer to PCNetState::INetworkConfig to a PCNetState pointer. */
4741	#define INETWORKCONFIG_2_DATA(pInterface) ( (PCNetState *)((uintptr_t)pInterface - RT_OFFSETOF(PCNetState, INetworkConfig)) )
4742
4743
4744	/**
4745	* Gets the current Media Access Control (MAC) address.
4746	*
4747	* @returns VBox status code.
4748	* @param pInterface Pointer to the interface structure containing the called function pointer.
4749	* @param pMac Where to store the MAC address.
4750	* @thread EMT
4751	*/
4752	static DECLCALLBACK(int) pcnetGetMac(PPDMINETWORKCONFIG pInterface, PRTMAC pMac)
4753	{
4754	PCNetState *pThis = INETWORKCONFIG_2_DATA(pInterface);
4755	memcpy(pMac, pThis->aPROM, sizeof(*pMac));
4756	return VINF_SUCCESS;
4757	}
4758
4759
4760	/**
4761	* Gets the new link state.
4762	*
4763	* @returns The current link state.
4764	* @param pInterface Pointer to the interface structure containing the called function pointer.
4765	* @thread EMT
4766	*/
4767	static DECLCALLBACK(PDMNETWORKLINKSTATE) pcnetGetLinkState(PPDMINETWORKCONFIG pInterface)
4768	{
4769	PCNetState *pThis = INETWORKCONFIG_2_DATA(pInterface);
4770	if (pThis->fLinkUp && !pThis->fLinkTempDown)
4771	return PDMNETWORKLINKSTATE_UP;
4772	if (!pThis->fLinkUp)
4773	return PDMNETWORKLINKSTATE_DOWN;
4774	if (pThis->fLinkTempDown)
4775	return PDMNETWORKLINKSTATE_DOWN_RESUME;
4776	AssertMsgFailed(("Invalid link state!\n"));
4777	return PDMNETWORKLINKSTATE_INVALID;
4778	}
4779
4780
4781	/**
4782	* Sets the new link state.
4783	*
4784	* @returns VBox status code.
4785	* @param pInterface Pointer to the interface structure containing the called function pointer.
4786	* @param enmState The new link state
4787	* @thread EMT
4788	*/
4789	static DECLCALLBACK(int) pcnetSetLinkState(PPDMINETWORKCONFIG pInterface, PDMNETWORKLINKSTATE enmState)
4790	{
4791	PCNetState *pThis = INETWORKCONFIG_2_DATA(pInterface);
4792	bool fLinkUp;
4793	if ( enmState != PDMNETWORKLINKSTATE_DOWN
4794	&& enmState != PDMNETWORKLINKSTATE_UP)
4795	{
4796	AssertMsgFailed(("Invalid parameter enmState=%d\n", enmState));
4797	return VERR_INVALID_PARAMETER;
4798	}
4799
4800	/* has the state changed? */
4801	fLinkUp = enmState == PDMNETWORKLINKSTATE_UP;
4802	if (pThis->fLinkUp != fLinkUp)
4803	{
4804	pThis->fLinkUp = fLinkUp;
4805	if (fLinkUp)
4806	{
4807	/* connect with a delay of 5 seconds */
4808	pThis->fLinkTempDown = true;
4809	pThis->cLinkDownReported = 0;
4810	pThis->aCSR[0] \|= RT_BIT(15) \| RT_BIT(13); /* ERR \| CERR (this is probably wrong) */
4811	pThis->Led.Asserted.s.fError = pThis->Led.Actual.s.fError = 1;
4812	int rc = TMTimerSetMillies(pThis->pTimerRestore, 5000);
4813	AssertRC(rc);
4814	}
4815	else
4816	{
4817	/* disconnect */
4818	pThis->cLinkDownReported = 0;
4819	pThis->aCSR[0] \|= RT_BIT(15) \| RT_BIT(13); /* ERR \| CERR (this is probably wrong) */
4820	pThis->Led.Asserted.s.fError = pThis->Led.Actual.s.fError = 1;
4821	}
4822	Assert(!PDMCritSectIsOwner(&pThis->CritSect));
4823	if (pThis->pDrvR3)
4824	pThis->pDrvR3->pfnNotifyLinkChanged(pThis->pDrvR3, enmState);
4825	}
4826	return VINF_SUCCESS;
4827	}
4828
4829
4830	/**
4831	* Gets the pointer to the status LED of a unit.
4832	*
4833	* @returns VBox status code.
4834	* @param pInterface Pointer to the interface structure containing the called function pointer.
4835	* @param iLUN The unit which status LED we desire.
4836	* @param ppLed Where to store the LED pointer.
4837	*/
4838	static DECLCALLBACK(int) pcnetQueryStatusLed(PPDMILEDPORTS pInterface, unsigned iLUN, PPDMLED *ppLed)
4839	{
4840	PCNetState pThis = (PCNetState )( (uintptr_t)pInterface - RT_OFFSETOF(PCNetState, ILeds) );
4841	if (iLUN == 0)
4842	{
4843	*ppLed = &pThis->Led;
4844	return VINF_SUCCESS;
4845	}
4846	return VERR_PDM_LUN_NOT_FOUND;
4847	}
4848
4849
4850	/**
4851	* @copydoc FNPDMDEVPOWEROFF
4852	*/
4853	static DECLCALLBACK(void) pcnetPowerOff(PPDMDEVINS pDevIns)
4854	{
4855	/* Poke thread waiting for buffer space. */
4856	pcnetWakeupReceive(pDevIns);
4857	}
4858
4859	#ifdef VBOX_DYNAMIC_NET_ATTACH
4860
4861	/**
4862	* Detach notification.
4863	*
4864	* One port on the network card has been disconnected from the network.
4865	*
4866	* @param pDevIns The device instance.
4867	* @param iLUN The logical unit which is being detached.
4868	* @param fFlags Flags, combination of the PDMDEVATT_FLAGS_* \#defines.
4869	*/
4870	static DECLCALLBACK(void) pcnetDetach(PPDMDEVINS pDevIns, unsigned iLUN, uint32_t fFlags)
4871	{
4872	PCNetState pThis = PDMINS_2_DATA(pDevIns, PCNetState );
4873	Log(("#%d pcnetDetach:\n", PCNET_INST_NR));
4874
4875	AssertLogRelReturnVoid(iLUN == 0);
4876
4877	PDMCritSectEnter(&pThis->CritSect, VERR_SEM_BUSY);
4878
4879	/** @todo: r=pritesh still need to check if i missed
4880	* to clean something in this function
4881	*/
4882
4883	/*
4884	* Zero some important members.
4885	*/
4886	pThis->pDrvBase = NULL;
4887	pThis->pDrvR3 = NULL;
4888
4889	PDMCritSectLeave(&pThis->CritSect);
4890	}
4891
4892
4893	/**
4894	* Attach the Network attachment.
4895	*
4896	* One port on the network card has been connected to a network.
4897	*
4898	* @returns VBox status code.
4899	* @param pDevIns The device instance.
4900	* @param iLUN The logical unit which is being attached.
4901	* @param fFlags Flags, combination of the PDMDEVATT_FLAGS_* \#defines.
4902	*
4903	* @remarks This code path is not used during construction.
4904	*/
4905	static DECLCALLBACK(int) pcnetAttach(PPDMDEVINS pDevIns, unsigned iLUN, uint32_t fFlags)
4906	{
4907	PCNetState pThis = PDMINS_2_DATA(pDevIns, PCNetState );
4908	LogFlow(("#%d pcnetAttach:\n", PCNET_INST_NR));
4909
4910	AssertLogRelReturn(iLUN == 0, VERR_PDM_NO_SUCH_LUN);
4911
4912	PDMCritSectEnter(&pThis->CritSect, VERR_SEM_BUSY);
4913
4914	/*
4915	* Attach the driver.
4916	*/
4917	int rc = PDMDevHlpDriverAttach(pDevIns, 0, &pThis->IBase, &pThis->pDrvBase, "Network Port");
4918	if (RT_SUCCESS(rc))
4919	{
4920	if (rc == VINF_NAT_DNS)
4921	{
4922	#ifdef RT_OS_LINUX
4923	PDMDevHlpVMSetRuntimeError(pDevIns, 0 /fFlags/, "NoDNSforNAT",
4924	N_("A Domain Name Server (DNS) for NAT networking could not be determined. Please check your /etc/resolv.conf for <tt>nameserver</tt> entries. Either add one manually (<i>man resolv.conf</i>) or ensure that your host is correctly connected to an ISP. If you ignore this warning the guest will not be able to perform nameserver lookups and it will probably observe delays if trying so"));
4925	#else
4926	PDMDevHlpVMSetRuntimeError(pDevIns, 0 /fFlags/, "NoDNSforNAT",
4927	N_("A Domain Name Server (DNS) for NAT networking could not be determined. Ensure that your host is correctly connected to an ISP. If you ignore this warning the guest will not be able to perform nameserver lookups and it will probably observe delays if trying so"));
4928	#endif
4929	}
4930	pThis->pDrvR3 = PDMIBASE_QUERY_INTERFACE(pThis->pDrvBase, PDMINETWORKUP);
4931	AssertMsgStmt(pThis->pDrvR3, ("Failed to obtain the PDMINETWORKUP interface!\n"),
4932	rc = VERR_PDM_MISSING_INTERFACE_BELOW);
4933	}
4934	else if (rc == VERR_PDM_NO_ATTACHED_DRIVER)
4935	Log(("#%d No attached driver!\n", PCNET_INST_NR));
4936
4937
4938	/*
4939	* Temporary set the link down if it was up so that the guest
4940	* will know that we have change the configuration of the
4941	* network card
4942	*/
4943	if (RT_SUCCESS(rc))
4944	pcnetTempLinkDown(pThis);
4945
4946	PDMCritSectLeave(&pThis->CritSect);
4947	return rc;
4948
4949	}
4950
4951	#endif /* VBOX_DYNAMIC_NET_ATTACH */
4952
4953	/**
4954	* @copydoc FNPDMDEVSUSPEND
4955	*/
4956	static DECLCALLBACK(void) pcnetSuspend(PPDMDEVINS pDevIns)
4957	{
4958	/* Poke thread waiting for buffer space. */
4959	pcnetWakeupReceive(pDevIns);
4960	}
4961
4962
4963	/**
4964	* @copydoc FNPDMDEVRESET
4965	*/
4966	static DECLCALLBACK(void) pcnetReset(PPDMDEVINS pDevIns)
4967	{
4968	PCNetState pThis = PDMINS_2_DATA(pDevIns, PCNetState );
4969	if (pThis->fLinkTempDown)
4970	{
4971	pThis->cLinkDownReported = 0x10000;
4972	TMTimerStop(pThis->pTimerRestore);
4973	pcnetTimerRestore(pDevIns, pThis->pTimerRestore, pThis);
4974	}
4975	if (pThis->pSharedMMIOR3)
4976	pcnetInitSharedMemory(pThis);
4977
4978	/** @todo How to flush the queues? */
4979	pcnetHardReset(pThis);
4980	}
4981
4982
4983	/**
4984	* @copydoc FNPDMDEVRELOCATE
4985	*/
4986	static DECLCALLBACK(void) pcnetRelocate(PPDMDEVINS pDevIns, RTGCINTPTR offDelta)
4987	{
4988	PCNetState pThis = PDMINS_2_DATA(pDevIns, PCNetState );
4989	pThis->pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
4990	pThis->pXmitQueueRC = PDMQueueRCPtr(pThis->pXmitQueueR3);
4991	pThis->pCanRxQueueRC = PDMQueueRCPtr(pThis->pCanRxQueueR3);
4992	if (pThis->pSharedMMIOR3)
4993	pThis->pSharedMMIORC += offDelta;
4994	#ifdef PCNET_NO_POLLING
4995	pThis->pfnEMInterpretInstructionRC += offDelta;
4996	#else
4997	pThis->pTimerPollRC = TMTimerRCPtr(pThis->pTimerPollR3);
4998	#endif
4999	if (pThis->fAm79C973)
5000	pThis->pTimerSoftIntRC = TMTimerRCPtr(pThis->pTimerSoftIntR3);
5001	}
5002
5003
5004	/**
5005	* Destruct a device instance.
5006	*
5007	* Most VM resources are freed by the VM. This callback is provided so that any non-VM
5008	* resources can be freed correctly.
5009	*
5010	* @returns VBox status.
5011	* @param pDevIns The device instance data.
5012	*/
5013	static DECLCALLBACK(int) pcnetDestruct(PPDMDEVINS pDevIns)
5014	{
5015	PCNetState pThis = PDMINS_2_DATA(pDevIns, PCNetState );
5016	PDMDEV_CHECK_VERSIONS_RETURN_QUIET(pDevIns);
5017
5018	if (PDMCritSectIsInitialized(&pThis->CritSect))
5019	{
5020	/*
5021	* At this point the send thread is suspended and will not enter
5022	* this module again. So, no coordination is needed here and PDM
5023	* will take care of terminating and cleaning up the thread.
5024	*/
5025	RTSemEventDestroy(pThis->hSendEventSem);
5026	pThis->hSendEventSem = NIL_RTSEMEVENT;
5027	RTSemEventSignal(pThis->hEventOutOfRxSpace);
5028	RTSemEventDestroy(pThis->hEventOutOfRxSpace);
5029	pThis->hEventOutOfRxSpace = NIL_RTSEMEVENT;
5030	PDMR3CritSectDelete(&pThis->CritSect);
5031	}
5032	return VINF_SUCCESS;
5033	}
5034
5035
5036	/**
5037	* @interface_method_impl{PDMDEVREG,pfnConstruct}
5038	*/
5039	static DECLCALLBACK(int) pcnetConstruct(PPDMDEVINS pDevIns, int iInstance, PCFGMNODE pCfg)
5040	{
5041	PCNetState pThis = PDMINS_2_DATA(pDevIns, PCNetState );
5042	PPDMIBASE pBase;
5043	char szTmp[128];
5044	int rc;
5045
5046	/* up to eight instances are supported */
5047	Assert((iInstance >= 0) && (iInstance < 8));
5048
5049	PDMDEV_CHECK_VERSIONS_RETURN(pDevIns);
5050	Assert(RT_ELEMENTS(pThis->aBCR) == BCR_MAX_RAP);
5051	Assert(RT_ELEMENTS(pThis->aMII) == MII_MAX_REG);
5052	Assert(sizeof(pThis->abLoopBuf) == RT_ALIGN_Z(sizeof(pThis->abLoopBuf), 16));
5053
5054	/*
5055	* Init what's required to make the destructor safe.
5056	*/
5057	pThis->hEventOutOfRxSpace = NIL_RTSEMEVENT;
5058	pThis->hSendEventSem = NIL_RTSEMEVENT;
5059
5060	/*
5061	* Validate configuration.
5062	*/
5063	if (!CFGMR3AreValuesValid(pCfg, "MAC\0" "CableConnected\0" "Am79C973\0" "LineSpeed\0" "GCEnabled\0" "R0Enabled\0" "PrivIfEnabled\0"))
5064	return PDMDEV_SET_ERROR(pDevIns, VERR_PDM_DEVINS_UNKNOWN_CFG_VALUES,
5065	N_("Invalid configuration for pcnet device"));
5066
5067	/*
5068	* Read the configuration.
5069	*/
5070	rc = CFGMR3QueryBytes(pCfg, "MAC", &pThis->MacConfigured, sizeof(pThis->MacConfigured));
5071	if (RT_FAILURE(rc))
5072	return PDMDEV_SET_ERROR(pDevIns, rc,
5073	N_("Configuration error: Failed to get the \"MAC\" value"));
5074	rc = CFGMR3QueryBoolDef(pCfg, "CableConnected", &pThis->fLinkUp, true);
5075	if (RT_FAILURE(rc))
5076	return PDMDEV_SET_ERROR(pDevIns, rc,
5077	N_("Configuration error: Failed to get the \"CableConnected\" value"));
5078
5079	rc = CFGMR3QueryBoolDef(pCfg, "Am79C973", &pThis->fAm79C973, false);
5080	if (RT_FAILURE(rc))
5081	return PDMDEV_SET_ERROR(pDevIns, rc,
5082	N_("Configuration error: Failed to get the \"Am79C973\" value"));
5083
5084	rc = CFGMR3QueryU32Def(pCfg, "LineSpeed", &pThis->u32LinkSpeed, 1000000); /* 1GBit/s (in kbps units)*/
5085	if (RT_FAILURE(rc))
5086	return PDMDEV_SET_ERROR(pDevIns, rc,
5087	N_("Configuration error: Failed to get the \"LineSpeed\" value"));
5088
5089	#ifdef PCNET_GC_ENABLED
5090	rc = CFGMR3QueryBoolDef(pCfg, "GCEnabled", &pThis->fGCEnabled, true);
5091	if (RT_FAILURE(rc))
5092	return PDMDEV_SET_ERROR(pDevIns, rc,
5093	N_("Configuration error: Failed to get the \"GCEnabled\" value"));
5094
5095	rc = CFGMR3QueryBoolDef(pCfg, "R0Enabled", &pThis->fR0Enabled, true);
5096	if (RT_FAILURE(rc))
5097	return PDMDEV_SET_ERROR(pDevIns, rc,
5098	N_("Configuration error: Failed to get the \"R0Enabled\" value"));
5099
5100	#else /* !PCNET_GC_ENABLED */
5101	pThis->fGCEnabled = false;
5102	pThis->fR0Enabled = false;
5103	#endif /* !PCNET_GC_ENABLED */
5104
5105
5106	/*
5107	* Initialize data (most of it anyway).
5108	*/
5109	pThis->pDevInsR3 = pDevIns;
5110	pThis->pDevInsR0 = PDMDEVINS_2_R0PTR(pDevIns);
5111	pThis->pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
5112	pThis->Led.u32Magic = PDMLED_MAGIC;
5113	/* IBase */
5114	pThis->IBase.pfnQueryInterface = pcnetQueryInterface;
5115	/* INeworkPort */
5116	pThis->INetworkDown.pfnWaitReceiveAvail = pcnetWaitReceiveAvail;
5117	pThis->INetworkDown.pfnReceive = pcnetReceive;
5118	/* INetworkConfig */
5119	pThis->INetworkConfig.pfnGetMac = pcnetGetMac;
5120	pThis->INetworkConfig.pfnGetLinkState = pcnetGetLinkState;
5121	pThis->INetworkConfig.pfnSetLinkState = pcnetSetLinkState;
5122	/* ILeds */
5123	pThis->ILeds.pfnQueryStatusLed = pcnetQueryStatusLed;
5124
5125	/* PCI Device */
5126	PCIDevSetVendorId(&pThis->PciDev, 0x1022);
5127	PCIDevSetDeviceId(&pThis->PciDev, 0x2000);
5128	pThis->PciDev.config[0x04] = 0x07; /* command */
5129	pThis->PciDev.config[0x05] = 0x00;
5130	pThis->PciDev.config[0x06] = 0x80; /* status */
5131	pThis->PciDev.config[0x07] = 0x02;
5132	pThis->PciDev.config[0x08] = pThis->fAm79C973 ? 0x40 : 0x10; /* revision */
5133	pThis->PciDev.config[0x09] = 0x00;
5134	pThis->PciDev.config[0x0a] = 0x00; /* ethernet network controller */
5135	pThis->PciDev.config[0x0b] = 0x02;
5136	pThis->PciDev.config[0x0e] = 0x00; /* header_type */
5137
5138	pThis->PciDev.config[0x10] = 0x01; /* IO Base */
5139	pThis->PciDev.config[0x11] = 0x00;
5140	pThis->PciDev.config[0x12] = 0x00;
5141	pThis->PciDev.config[0x13] = 0x00;
5142	pThis->PciDev.config[0x14] = 0x00; /* MMIO Base */
5143	pThis->PciDev.config[0x15] = 0x00;
5144	pThis->PciDev.config[0x16] = 0x00;
5145	pThis->PciDev.config[0x17] = 0x00;
5146
5147	/* subsystem and subvendor IDs */
5148	pThis->PciDev.config[0x2c] = 0x22; /* subsystem vendor id */
5149	pThis->PciDev.config[0x2d] = 0x10;
5150	pThis->PciDev.config[0x2e] = 0x00; /* subsystem id */
5151	pThis->PciDev.config[0x2f] = 0x20;
5152	pThis->PciDev.config[0x3d] = 1; /* interrupt pin 0 */
5153	pThis->PciDev.config[0x3e] = 0x06;
5154	pThis->PciDev.config[0x3f] = 0xff;
5155
5156	/*
5157	* Register the PCI device, its I/O regions, the timer and the saved state item.
5158	*/
5159	rc = PDMDevHlpPCIRegister(pDevIns, &pThis->PciDev);
5160	if (RT_FAILURE(rc))
5161	return rc;
5162	rc = PDMDevHlpPCIIORegionRegister(pDevIns, 0, PCNET_IOPORT_SIZE,
5163	PCI_ADDRESS_SPACE_IO, pcnetIOPortMap);
5164	if (RT_FAILURE(rc))
5165	return rc;
5166	rc = PDMDevHlpPCIIORegionRegister(pDevIns, 1, PCNET_PNPMMIO_SIZE,
5167	PCI_ADDRESS_SPACE_MEM, pcnetMMIOMap);
5168	if (RT_FAILURE(rc))
5169	return rc;
5170
5171	bool fPrivIfEnabled;
5172	rc = CFGMR3QueryBool(pCfg, "PrivIfEnabled", &fPrivIfEnabled);
5173	if (rc == VERR_CFGM_VALUE_NOT_FOUND)
5174	fPrivIfEnabled = true;
5175	else if (RT_FAILURE(rc))
5176	return PDMDEV_SET_ERROR(pDevIns, rc,
5177	N_("Configuration error: Failed to get the \"PrivIfEnabled\" value"));
5178
5179	if (fPrivIfEnabled)
5180	{
5181	/*
5182	* Initialize shared memory between host and guest for descriptors and RX buffers. Most guests
5183	* should not care if there is an additional PCI ressource but just in case we made this configurable.
5184	*/
5185	rc = PDMDevHlpMMIO2Register(pDevIns, 2, PCNET_GUEST_SHARED_MEMORY_SIZE, 0, (void **)&pThis->pSharedMMIOR3, "PCNetShMem");
5186	if (RT_FAILURE(rc))
5187	return PDMDevHlpVMSetError(pDevIns, rc, RT_SRC_POS,
5188	N_("Failed to allocate %u bytes of memory for the PCNet device"), PCNET_GUEST_SHARED_MEMORY_SIZE);
5189	rc = PDMDevHlpMMHyperMapMMIO2(pDevIns, 2, 0, 8192, "PCNetShMem", &pThis->pSharedMMIORC);
5190	if (RT_FAILURE(rc))
5191	return PDMDevHlpVMSetError(pDevIns, rc, RT_SRC_POS,
5192	N_("Failed to map 8192 bytes of memory for the PCNet device into the hyper memory"));
5193	pThis->pSharedMMIOR0 = (uintptr_t)pThis->pSharedMMIOR3; /** @todo #1865: Map MMIO2 into ring-0. */
5194
5195	pcnetInitSharedMemory(pThis);
5196	rc = PDMDevHlpPCIIORegionRegister(pDevIns, 2, PCNET_GUEST_SHARED_MEMORY_SIZE,
5197	PCI_ADDRESS_SPACE_MEM, pcnetMMIOSharedMap);
5198	if (RT_FAILURE(rc))
5199	return rc;
5200	}
5201
5202	/*
5203	* Initialize critical section.
5204	* This must be done before register the critsect with the timer code, and also before
5205	* attaching drivers or anything else that may call us back.
5206	*/
5207	rc = PDMDevHlpCritSectInit(pDevIns, &pThis->CritSect, RT_SRC_POS, "PCNet#%d", iInstance);
5208	if (RT_FAILURE(rc))
5209	return rc;
5210
5211	rc = RTSemEventCreate(&pThis->hEventOutOfRxSpace);
5212	AssertRC(rc);
5213
5214	#ifdef PCNET_NO_POLLING
5215	/*
5216	* Resolve the R0 and RC handlers.
5217	*/
5218	rc = PDMR3LdrGetSymbolR0Lazy(PDMDevHlpGetVM(pDevIns), NULL, "EMInterpretInstruction", &pThis->pfnEMInterpretInstructionR0);
5219	if (RT_SUCCESS(rc))
5220	rc = PDMR3LdrGetSymbolRCLazy(PDMDevHlpGetVM(pDevIns), NULL, "EMInterpretInstruction", (RTGCPTR *)&pThis->pfnEMInterpretInstructionRC);
5221	AssertLogRelMsgRCReturn(rc, ("PDMR3LdrGetSymbolRCLazy(EMInterpretInstruction) -> %Rrc\n", rc), rc);
5222	#else
5223	rc = PDMDevHlpTMTimerCreate(pDevIns, TMCLOCK_VIRTUAL, pcnetTimer, pThis,
5224	TMTIMER_FLAGS_NO_CRIT_SECT, "PCNet Poll Timer", &pThis->pTimerPollR3);
5225	if (RT_FAILURE(rc))
5226	return rc;
5227	pThis->pTimerPollR0 = TMTimerR0Ptr(pThis->pTimerPollR3);
5228	pThis->pTimerPollRC = TMTimerRCPtr(pThis->pTimerPollR3);
5229	TMR3TimerSetCritSect(pThis->pTimerPollR3, &pThis->CritSect);
5230	#endif
5231	if (pThis->fAm79C973)
5232	{
5233	/* Software Interrupt timer */
5234	rc = PDMDevHlpTMTimerCreate(pDevIns, TMCLOCK_VIRTUAL, pcnetTimerSoftInt, pThis, /** @todo r=bird: the locking here looks bogus now with SMP... */
5235	TMTIMER_FLAGS_DEFAULT_CRIT_SECT, "PCNet SoftInt Timer", &pThis->pTimerSoftIntR3);
5236	if (RT_FAILURE(rc))
5237	return rc;
5238	pThis->pTimerSoftIntR0 = TMTimerR0Ptr(pThis->pTimerSoftIntR3);
5239	pThis->pTimerSoftIntRC = TMTimerRCPtr(pThis->pTimerSoftIntR3);
5240	}
5241	rc = PDMDevHlpTMTimerCreate(pDevIns, TMCLOCK_VIRTUAL, pcnetTimerRestore, pThis,
5242	TMTIMER_FLAGS_NO_CRIT_SECT, "PCNet Restore Timer", &pThis->pTimerRestore);
5243	if (RT_FAILURE(rc))
5244	return rc;
5245
5246	rc = PDMDevHlpSSMRegisterEx(pDevIns, PCNET_SAVEDSTATE_VERSION, sizeof(*pThis), NULL,
5247	NULL, pcnetLiveExec, NULL,
5248	pcnetSavePrep, pcnetSaveExec, NULL,
5249	pcnetLoadPrep, pcnetLoadExec, NULL);
5250	if (RT_FAILURE(rc))
5251	return rc;
5252
5253	/*
5254	* Create the transmit queue.
5255	*/
5256	rc = PDMDevHlpQueueCreate(pDevIns, sizeof(PDMQUEUEITEMCORE), 1, 0,
5257	pcnetXmitQueueConsumer, true, "PCNet-Xmit", &pThis->pXmitQueueR3);
5258	if (RT_FAILURE(rc))
5259	return rc;
5260	pThis->pXmitQueueR0 = PDMQueueR0Ptr(pThis->pXmitQueueR3);
5261	pThis->pXmitQueueRC = PDMQueueRCPtr(pThis->pXmitQueueR3);
5262
5263	/*
5264	* Create the RX notifer signaller.
5265	*/
5266	rc = PDMDevHlpQueueCreate(pDevIns, sizeof(PDMQUEUEITEMCORE), 1, 0,
5267	pcnetCanRxQueueConsumer, true, "PCNet-Rcv", &pThis->pCanRxQueueR3);
5268	if (RT_FAILURE(rc))
5269	return rc;
5270	pThis->pCanRxQueueR0 = PDMQueueR0Ptr(pThis->pCanRxQueueR3);
5271	pThis->pCanRxQueueRC = PDMQueueRCPtr(pThis->pCanRxQueueR3);
5272
5273	/*
5274	* Register the info item.
5275	*/
5276	RTStrPrintf(szTmp, sizeof(szTmp), "pcnet%d", pDevIns->iInstance);
5277	PDMDevHlpDBGFInfoRegister(pDevIns, szTmp, "PCNET info.", pcnetInfo);
5278
5279	/*
5280	* Attach status driver (optional).
5281	*/
5282	rc = PDMDevHlpDriverAttach(pDevIns, PDM_STATUS_LUN, &pThis->IBase, &pBase, "Status Port");
5283	if (RT_SUCCESS(rc))
5284	pThis->pLedsConnector = PDMIBASE_QUERY_INTERFACE(pBase, PDMILEDCONNECTORS);
5285	else if (rc != VERR_PDM_NO_ATTACHED_DRIVER)
5286	{
5287	AssertMsgFailed(("Failed to attach to status driver. rc=%Rrc\n", rc));
5288	return rc;
5289	}
5290
5291	/*
5292	* Attach driver.
5293	*/
5294	rc = PDMDevHlpDriverAttach(pDevIns, 0, &pThis->IBase, &pThis->pDrvBase, "Network Port");
5295	if (RT_SUCCESS(rc))
5296	{
5297	if (rc == VINF_NAT_DNS)
5298	{
5299	#ifdef RT_OS_LINUX
5300	PDMDevHlpVMSetRuntimeError(pDevIns, 0 /fFlags/, "NoDNSforNAT",
5301	N_("A Domain Name Server (DNS) for NAT networking could not be determined. Please check your /etc/resolv.conf for <tt>nameserver</tt> entries. Either add one manually (<i>man resolv.conf</i>) or ensure that your host is correctly connected to an ISP. If you ignore this warning the guest will not be able to perform nameserver lookups and it will probably observe delays if trying so"));
5302	#else
5303	PDMDevHlpVMSetRuntimeError(pDevIns, 0 /fFlags/, "NoDNSforNAT",
5304	N_("A Domain Name Server (DNS) for NAT networking could not be determined. Ensure that your host is correctly connected to an ISP. If you ignore this warning the guest will not be able to perform nameserver lookups and it will probably observe delays if trying so"));
5305	#endif
5306	}
5307	pThis->pDrvR3 = PDMIBASE_QUERY_INTERFACE(pThis->pDrvBase, PDMINETWORKUP);
5308	AssertMsgReturn(pThis->pDrvR3, ("Failed to obtain the PDMINETWORKUP interface!\n"),
5309	VERR_PDM_MISSING_INTERFACE_BELOW);
5310	}
5311	else if (rc == VERR_PDM_NO_ATTACHED_DRIVER)
5312	Log(("No attached driver!\n"));
5313	else
5314	return rc;
5315
5316	/*
5317	* Reset the device state. (Do after attaching.)
5318	*/
5319	pcnetHardReset(pThis);
5320
5321	#ifdef VBOX_WITH_TX_THREAD_IN_NET_DEVICES
5322	/* Create send queue for the async send thread. */
5323	rc = RTSemEventCreate(&pThis->hSendEventSem);
5324	AssertRC(rc);
5325
5326	/* Create asynchronous thread */
5327	rc = PDMDevHlpThreadCreate(pDevIns, &pThis->pSendThread, pThis, pcnetAsyncSendThread, pcnetAsyncSendThreadWakeUp, 0, RTTHREADTYPE_IO, "PCNET_TX");
5328	AssertRCReturn(rc, rc);
5329	#endif
5330
5331	#ifdef VBOX_WITH_STATISTICS
5332	PDMDevHlpSTAMRegisterF(pDevIns, &pThis->StatMMIOReadGC, STAMTYPE_PROFILE, STAMVISIBILITY_ALWAYS, STAMUNIT_TICKS_PER_CALL, "Profiling MMIO reads in GC", "/Devices/PCNet%d/MMIO/ReadGC", iInstance);
5333	PDMDevHlpSTAMRegisterF(pDevIns, &pThis->StatMMIOReadHC, STAMTYPE_PROFILE, STAMVISIBILITY_ALWAYS, STAMUNIT_TICKS_PER_CALL, "Profiling MMIO reads in HC", "/Devices/PCNet%d/MMIO/ReadHC", iInstance);
5334	PDMDevHlpSTAMRegisterF(pDevIns, &pThis->StatMMIOWriteGC, STAMTYPE_PROFILE, STAMVISIBILITY_ALWAYS, STAMUNIT_TICKS_PER_CALL, "Profiling MMIO writes in GC", "/Devices/PCNet%d/MMIO/WriteGC", iInstance);
5335	PDMDevHlpSTAMRegisterF(pDevIns, &pThis->StatMMIOWriteHC, STAMTYPE_PROFILE, STAMVISIBILITY_ALWAYS, STAMUNIT_TICKS_PER_CALL, "Profiling MMIO writes in HC", "/Devices/PCNet%d/MMIO/WriteHC", iInstance);
5336	PDMDevHlpSTAMRegisterF(pDevIns, &pThis->StatAPROMRead, STAMTYPE_PROFILE, STAMVISIBILITY_ALWAYS, STAMUNIT_TICKS_PER_CALL, "Profiling APROM reads", "/Devices/PCNet%d/IO/APROMRead", iInstance);
5337	PDMDevHlpSTAMRegisterF(pDevIns, &pThis->StatAPROMWrite, STAMTYPE_PROFILE, STAMVISIBILITY_ALWAYS, STAMUNIT_TICKS_PER_CALL, "Profiling APROM writes", "/Devices/PCNet%d/IO/APROMWrite", iInstance);
5338	PDMDevHlpSTAMRegisterF(pDevIns, &pThis->StatIOReadGC, STAMTYPE_PROFILE, STAMVISIBILITY_ALWAYS, STAMUNIT_TICKS_PER_CALL, "Profiling IO reads in GC", "/Devices/PCNet%d/IO/ReadGC", iInstance);
5339	PDMDevHlpSTAMRegisterF(pDevIns, &pThis->StatIOReadHC, STAMTYPE_PROFILE, STAMVISIBILITY_ALWAYS, STAMUNIT_TICKS_PER_CALL, "Profiling IO reads in HC", "/Devices/PCNet%d/IO/ReadHC", iInstance);
5340	PDMDevHlpSTAMRegisterF(pDevIns, &pThis->StatIOWriteGC, STAMTYPE_PROFILE, STAMVISIBILITY_ALWAYS, STAMUNIT_TICKS_PER_CALL, "Profiling IO writes in GC", "/Devices/PCNet%d/IO/WriteGC", iInstance);
5341	PDMDevHlpSTAMRegisterF(pDevIns, &pThis->StatIOWriteHC, STAMTYPE_PROFILE, STAMVISIBILITY_ALWAYS, STAMUNIT_TICKS_PER_CALL, "Profiling IO writes in HC", "/Devices/PCNet%d/IO/WriteHC", iInstance);
5342	PDMDevHlpSTAMRegisterF(pDevIns, &pThis->StatTimer, STAMTYPE_PROFILE, STAMVISIBILITY_ALWAYS, STAMUNIT_TICKS_PER_CALL, "Profiling Timer", "/Devices/PCNet%d/Timer", iInstance);
5343	PDMDevHlpSTAMRegisterF(pDevIns, &pThis->StatReceive, STAMTYPE_PROFILE, STAMVISIBILITY_ALWAYS, STAMUNIT_TICKS_PER_CALL, "Profiling receive", "/Devices/PCNet%d/Receive", iInstance);
5344	PDMDevHlpSTAMRegisterF(pDevIns, &pThis->StatRxOverflow, STAMTYPE_PROFILE, STAMVISIBILITY_ALWAYS, STAMUNIT_TICKS_PER_OCCURENCE, "Profiling RX overflows", "/Devices/PCNet%d/RxOverflow", iInstance);
5345	PDMDevHlpSTAMRegisterF(pDevIns, &pThis->StatRxOverflowWakeup, STAMTYPE_PROFILE, STAMVISIBILITY_ALWAYS, STAMUNIT_TICKS_PER_OCCURENCE, "Nr of RX overflow wakeups", "/Devices/PCNet%d/RxOverflowWakeup", iInstance);
5346	#endif
5347	PDMDevHlpSTAMRegisterF(pDevIns, &pThis->StatReceiveBytes, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_BYTES, "Amount of data received", "/Devices/PCNet%d/ReceiveBytes", iInstance);
5348	#ifdef VBOX_WITH_STATISTICS
5349	PDMDevHlpSTAMRegisterF(pDevIns, &pThis->StatTransmitCase1, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, "Single descriptor transmit", "/Devices/PCNet%d/Transmit/Case1", iInstance);
5350	PDMDevHlpSTAMRegisterF(pDevIns, &pThis->StatTransmitCase2, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, "Multi descriptor transmit", "/Devices/PCNet%d/Transmit/Case2", iInstance);
5351	PDMDevHlpSTAMRegisterF(pDevIns, &pThis->StatTransmit, STAMTYPE_PROFILE, STAMVISIBILITY_ALWAYS, STAMUNIT_TICKS_PER_CALL, "Profiling transmits in HC", "/Devices/PCNet%d/Transmit/Total", iInstance);
5352	#endif
5353	PDMDevHlpSTAMRegisterF(pDevIns, &pThis->StatTransmitBytes, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_BYTES, "Amount of data transmitted", "/Devices/PCNet%d/TransmitBytes", iInstance);
5354	#ifdef VBOX_WITH_STATISTICS
5355	PDMDevHlpSTAMRegisterF(pDevIns, &pThis->StatTransmitSend, STAMTYPE_PROFILE, STAMVISIBILITY_ALWAYS, STAMUNIT_TICKS_PER_CALL, "Profiling PCNet send transmit in HC","/Devices/PCNet%d/Transmit/Send", iInstance);
5356	PDMDevHlpSTAMRegisterF(pDevIns, &pThis->StatTdtePollGC, STAMTYPE_PROFILE, STAMVISIBILITY_ALWAYS, STAMUNIT_TICKS_PER_CALL, "Profiling PCNet TdtePoll in GC", "/Devices/PCNet%d/TdtePollGC", iInstance);
5357	PDMDevHlpSTAMRegisterF(pDevIns, &pThis->StatTdtePollHC, STAMTYPE_PROFILE, STAMVISIBILITY_ALWAYS, STAMUNIT_TICKS_PER_CALL, "Profiling PCNet TdtePoll in HC", "/Devices/PCNet%d/TdtePollHC", iInstance);
5358	PDMDevHlpSTAMRegisterF(pDevIns, &pThis->StatRdtePollGC, STAMTYPE_PROFILE, STAMVISIBILITY_ALWAYS, STAMUNIT_TICKS_PER_CALL, "Profiling PCNet RdtePoll in GC", "/Devices/PCNet%d/RdtePollGC", iInstance);
5359	PDMDevHlpSTAMRegisterF(pDevIns, &pThis->StatRdtePollHC, STAMTYPE_PROFILE, STAMVISIBILITY_ALWAYS, STAMUNIT_TICKS_PER_CALL, "Profiling PCNet RdtePoll in HC", "/Devices/PCNet%d/RdtePollHC", iInstance);
5360
5361	PDMDevHlpSTAMRegisterF(pDevIns, &pThis->StatTmdStoreGC, STAMTYPE_PROFILE, STAMVISIBILITY_ALWAYS, STAMUNIT_TICKS_PER_CALL, "Profiling PCNet TmdStore in GC", "/Devices/PCNet%d/TmdStoreGC", iInstance);
5362	PDMDevHlpSTAMRegisterF(pDevIns, &pThis->StatTmdStoreHC, STAMTYPE_PROFILE, STAMVISIBILITY_ALWAYS, STAMUNIT_TICKS_PER_CALL, "Profiling PCNet TmdStore in HC", "/Devices/PCNet%d/TmdStoreHC", iInstance);
5363
5364	unsigned i;
5365	for (i = 0; i < RT_ELEMENTS(pThis->aStatXmitFlush) - 1; i++)
5366	PDMDevHlpSTAMRegisterF(pDevIns, &pThis->aStatXmitFlush[i], STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES, "", "/Devices/PCNet%d/XmitFlushIrq/%d", iInstance, i + 1);
5367	PDMDevHlpSTAMRegisterF(pDevIns, &pThis->aStatXmitFlush[i], STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES, "", "/Devices/PCNet%d/XmitFlushIrq/%d+", iInstance, i + 1);
5368
5369	for (i = 0; i < RT_ELEMENTS(pThis->aStatXmitChainCounts) - 1; i++)
5370	PDMDevHlpSTAMRegisterF(pDevIns, &pThis->aStatXmitChainCounts[i], STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES, "", "/Devices/PCNet%d/XmitChainCounts/%d", iInstance, i + 1);
5371	PDMDevHlpSTAMRegisterF(pDevIns, &pThis->aStatXmitChainCounts[i], STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES, "", "/Devices/PCNet%d/XmitChainCounts/%d+", iInstance, i + 1);
5372
5373	PDMDevHlpSTAMRegisterF(pDevIns, &pThis->StatXmitSkipCurrent, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, "", "/Devices/PCNet%d/Xmit/Skipped", iInstance, i + 1);
5374
5375	PDMDevHlpSTAMRegisterF(pDevIns, &pThis->StatInterrupt, STAMTYPE_PROFILE, STAMVISIBILITY_ALWAYS, STAMUNIT_TICKS_PER_CALL, "Profiling interrupt checks", "/Devices/PCNet%d/UpdateIRQ", iInstance);
5376	PDMDevHlpSTAMRegisterF(pDevIns, &pThis->StatPollTimer, STAMTYPE_PROFILE, STAMVISIBILITY_ALWAYS, STAMUNIT_TICKS_PER_CALL, "Profiling poll timer", "/Devices/PCNet%d/PollTimer", iInstance);
5377	PDMDevHlpSTAMRegisterF(pDevIns, &pThis->StatMIIReads, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, "Number of MII reads", "/Devices/PCNet%d/MIIReads", iInstance);
5378	# ifdef PCNET_NO_POLLING
5379	PDMDevHlpSTAMRegisterF(pDevIns, &pThis->StatRCVRingWrite, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, "Nr of receive ring writes", "/Devices/PCNet%d/Ring/RCVWrites", iInstance);
5380	PDMDevHlpSTAMRegisterF(pDevIns, &pThis->StatTXRingWrite, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, "Nr of transmit ring writes", "/Devices/PCNet%d/Ring/TXWrites", iInstance);
5381	PDMDevHlpSTAMRegisterF(pDevIns, &pThis->StatRingWriteHC, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, "Nr of monitored ring page writes", "/Devices/PCNet%d/Ring/HC/Writes", iInstance);
5382	PDMDevHlpSTAMRegisterF(pDevIns, &pThis->StatRingWriteR0, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, "Nr of monitored ring page writes", "/Devices/PCNet%d/Ring/R0/Writes", iInstance);
5383	PDMDevHlpSTAMRegisterF(pDevIns, &pThis->StatRingWriteGC, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, "Nr of monitored ring page writes", "/Devices/PCNet%d/Ring/GC/Writes", iInstance);
5384	PDMDevHlpSTAMRegisterF(pDevIns, &pThis->StatRingWriteFailedHC, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, "Nr of failed ring page writes", "/Devices/PCNet%d/Ring/HC/Failed", iInstance);
5385	PDMDevHlpSTAMRegisterF(pDevIns, &pThis->StatRingWriteFailedR0, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, "Nr of failed ring page writes", "/Devices/PCNet%d/Ring/R0/Failed", iInstance);
5386	PDMDevHlpSTAMRegisterF(pDevIns, &pThis->StatRingWriteFailedGC, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, "Nr of failed ring page writes", "/Devices/PCNet%d/Ring/GC/Failed", iInstance);
5387	PDMDevHlpSTAMRegisterF(pDevIns, &pThis->StatRingWriteOutsideHC, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, "Nr of monitored writes outside ring","/Devices/PCNet%d/Ring/HC/Outside", iInstance);
5388	PDMDevHlpSTAMRegisterF(pDevIns, &pThis->StatRingWriteOutsideR0, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, "Nr of monitored writes outside ring","/Devices/PCNet%d/Ring/R0/Outside", iInstance);
5389	PDMDevHlpSTAMRegisterF(pDevIns, &pThis->StatRingWriteOutsideGC, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, "Nr of monitored writes outside ring","/Devices/PCNet%d/Ring/GC/Outside", iInstance);
5390	# endif /* PCNET_NO_POLLING */
5391	#endif
5392
5393	return VINF_SUCCESS;
5394	}
5395
5396
5397	/**
5398	* The device registration structure.
5399	*/
5400	const PDMDEVREG g_DevicePCNet =
5401	{
5402	/* u32Version */
5403	PDM_DEVREG_VERSION,
5404	/* szName */
5405	"pcnet",
5406	/* szRCMod */
5407	#ifdef PCNET_GC_ENABLED
5408	"VBoxDDGC.gc",
5409	"VBoxDDR0.r0",
5410	#else
5411	"",
5412	"",
5413	#endif
5414	/* pszDescription */
5415	"AMD PC-Net II Ethernet controller.\n",
5416	/* fFlags */
5417	#ifdef PCNET_GC_ENABLED
5418	PDM_DEVREG_FLAGS_DEFAULT_BITS \| PDM_DEVREG_FLAGS_RC \| PDM_DEVREG_FLAGS_R0,
5419	#else
5420	PDM_DEVREG_FLAGS_DEFAULT_BITS,
5421	#endif
5422	/* fClass */
5423	PDM_DEVREG_CLASS_NETWORK,
5424	/* cMaxInstances */
5425	8,
5426	/* cbInstance */
5427	sizeof(PCNetState),
5428	/* pfnConstruct */
5429	pcnetConstruct,
5430	/* pfnDestruct */
5431	pcnetDestruct,
5432	/* pfnRelocate */
5433	pcnetRelocate,
5434	/* pfnIOCtl */
5435	NULL,
5436	/* pfnPowerOn */
5437	NULL,
5438	/* pfnReset */
5439	pcnetReset,
5440	/* pfnSuspend */
5441	pcnetSuspend,
5442	/* pfnResume */
5443	NULL,
5444	#ifdef VBOX_DYNAMIC_NET_ATTACH
5445	/* pfnAttach */
5446	pcnetAttach,
5447	/* pfnDetach */
5448	pcnetDetach,
5449	#else /* !VBOX_DYNAMIC_NET_ATTACH */
5450	/* pfnAttach */
5451	NULL,
5452	/* pfnDetach */
5453	NULL,
5454	#endif /* !VBOX_DYNAMIC_NET_ATTACH */
5455	/* pfnQueryInterface. */
5456	NULL,
5457	/* pfnInitComplete. */
5458	NULL,
5459	/* pfnPowerOff. */
5460	pcnetPowerOff,
5461	/* pfnSoftReset */
5462	NULL,
5463	/* u32VersionEnd */
5464	PDM_DEVREG_VERSION
5465	};
5466
5467	#endif /* IN_RING3 */
5468	#endif /* !VBOX_DEVICE_STRUCT_TESTCASE */
5469

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source: vbox/trunk/src/VBox/Devices/Network/DevPCNet.cpp@ 27856

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