DevE1000Phy.cpp@ 91942

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1	/** $Id: DevE1000Phy.cpp 82968 2020-02-04 10:35:17Z vboxsync $ */
2	/** @file
3	* DevE1000Phy - Intel 82540EM Ethernet Controller Internal PHY Emulation.
4	*
5	* Implemented in accordance with the specification:
6	* PCI/PCI-X Family of Gigabit Ethernet Controllers Software Developer's
7	* Manual 82540EP/EM, 82541xx, 82544GC/EI, 82545GM/EM, 82546GB/EB, and
8	* 82547xx
9	*
10	* 317453-002 Revision 3.5
11	*/
12
13	/*
14	* Copyright (C) 2007-2020 Oracle Corporation
15	*
16	* This file is part of VirtualBox Open Source Edition (OSE), as
17	* available from http://www.virtualbox.org. This file is free software;
18	* you can redistribute it and/or modify it under the terms of the GNU
19	* General Public License (GPL) as published by the Free Software
20	* Foundation, in version 2 as it comes in the "COPYING" file of the
21	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
22	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
23	*/
24
25	#define LOG_GROUP LOG_GROUP_DEV_E1000
26
27	/** @todo Remove me! For now I want asserts to work in release code. */
28	// #ifndef RT_STRICT
29	// #define RT_STRICT
30	#include <iprt/assert.h>
31	// #undef RT_STRICT
32	// #endif
33
34	#include <iprt/errcore.h>
35	#include <VBox/log.h>
36	#ifdef IN_RING3
37	# include <VBox/vmm/pdmdev.h>
38	#endif
39	#include "DevE1000Phy.h"
40
41	/* Little helpers ************************************************************/
42	#ifdef PHY_UNIT_TEST
43	# define SSMR3PutMem(a,b,c)
44	# define SSMR3GetMem(a,b,c)
45	# include <stdio.h>
46	# define PhyLog(a) printf a
47	#else /* PHY_UNIT_TEST */
48	# define PhyLog(a) Log(a)
49	#endif /* PHY_UNIT_TEST */
50
51	#define REG(x) pPhy->au16Regs[x##_IDX]
52
53
54	/* Internals */
55	namespace Phy {
56	#if defined(LOG_ENABLED) && !defined(PHY_UNIT_TEST)
57	/** Retrieves state name by id */
58	static const char * getStateName(uint16_t u16State);
59	#endif
60	/** Look up register index by address. */
61	static int lookupRegister(uint32_t u32Address);
62	/** Software-triggered reset. */
63	static void softReset(PPHY pPhy, PPDMDEVINS pDevIns);
64
65	/** Read callback. */
66	typedef uint16_t FNREAD(PPHY pPhy, uint32_t index, PPDMDEVINS pDevIns);
67	/** Write callback. */
68	typedef void FNWRITE(PPHY pPhy, uint32_t index, uint16_t u16Value, PPDMDEVINS pDevIns);
69
70	/** @name Generic handlers
71	* @{ */
72	static FNREAD regReadDefault;
73	static FNWRITE regWriteDefault;
74	static FNREAD regReadForbidden;
75	static FNWRITE regWriteForbidden;
76	static FNREAD regReadUnimplemented;
77	static FNWRITE regWriteUnimplemented;
78	/** @} */
79	/** @name Register-specific handlers
80	* @{ */
81	static FNWRITE regWritePCTRL;
82	static FNREAD regReadPSTATUS;
83	static FNREAD regReadGSTATUS;
84	/** @} */
85
86	/**
87	* PHY register map table.
88	*
89	* Override pfnRead and pfnWrite to implement register-specific behavior.
90	*/
91	static struct RegMap_st
92	{
93	/** PHY register address. */
94	uint32_t u32Address;
95	/** Read callback. */
96	FNREAD *pfnRead;
97	/** Write callback. */
98	FNWRITE *pfnWrite;
99	/** Abbreviated name. */
100	const char *pszAbbrev;
101	/** Full name. */
102	const char *pszName;
103	} s_regMap[NUM_OF_PHY_REGS] =
104	{
105	/ra read callback write callback abbrev full name /
106	/-- ------------------------- -------------------------- ---------- ------------------------------/
107	{ 0, Phy::regReadDefault , Phy::regWritePCTRL , "PCTRL" , "PHY Control" },
108	{ 1, Phy::regReadPSTATUS , Phy::regWriteForbidden , "PSTATUS" , "PHY Status" },
109	{ 2, Phy::regReadDefault , Phy::regWriteForbidden , "PID" , "PHY Identifier" },
110	{ 3, Phy::regReadDefault , Phy::regWriteForbidden , "EPID" , "Extended PHY Identifier" },
111	{ 4, Phy::regReadDefault , Phy::regWriteDefault , "ANA" , "Auto-Negotiation Advertisement" },
112	{ 5, Phy::regReadDefault , Phy::regWriteForbidden , "LPA" , "Link Partner Ability" },
113	{ 6, Phy::regReadUnimplemented, Phy::regWriteForbidden , "ANE" , "Auto-Negotiation Expansion" },
114	{ 7, Phy::regReadUnimplemented, Phy::regWriteUnimplemented, "NPT" , "Next Page Transmit" },
115	{ 8, Phy::regReadUnimplemented, Phy::regWriteForbidden , "LPN" , "Link Partner Next Page" },
116	{ 9, Phy::regReadDefault , Phy::regWriteUnimplemented, "GCON" , "1000BASE-T Control" },
117	{ 10, Phy::regReadGSTATUS , Phy::regWriteForbidden , "GSTATUS" , "1000BASE-T Status" },
118	{ 15, Phy::regReadUnimplemented, Phy::regWriteForbidden , "EPSTATUS" , "Extended PHY Status" },
119	{ 16, Phy::regReadDefault , Phy::regWriteDefault , "PSCON" , "PHY Specific Control" },
120	{ 17, Phy::regReadDefault , Phy::regWriteForbidden , "PSSTAT" , "PHY Specific Status" },
121	{ 18, Phy::regReadUnimplemented, Phy::regWriteUnimplemented, "PINTE" , "PHY Interrupt Enable" },
122	{ 19, Phy::regReadUnimplemented, Phy::regWriteForbidden , "PINTS" , "PHY Interrupt Status" },
123	{ 20, Phy::regReadUnimplemented, Phy::regWriteUnimplemented, "EPSCON1" , "Extended PHY Specific Control 1" },
124	{ 21, Phy::regReadUnimplemented, Phy::regWriteForbidden , "PREC" , "PHY Receive Error Counter" },
125	{ 26, Phy::regReadUnimplemented, Phy::regWriteUnimplemented, "EPSCON2" , "Extended PHY Specific Control 2" },
126	{ 29, Phy::regReadForbidden , Phy::regWriteUnimplemented, "R30PS" , "MDI Register 30 Page Select" },
127	{ 30, Phy::regReadUnimplemented, Phy::regWriteUnimplemented, "R30AW" , "MDI Register 30 Access Window" }
128	};
129	}
130
131	/**
132	* Default read handler.
133	*
134	* Fetches register value from the state structure.
135	*
136	* @returns Register value
137	*
138	* @param index Register index in register array.
139	*/
140	static uint16_t Phy::regReadDefault(PPHY pPhy, uint32_t index, PPDMDEVINS pDevIns)
141	{
142	RT_NOREF(pDevIns);
143	AssertReturn(index<Phy::NUM_OF_PHY_REGS, 0);
144	return pPhy->au16Regs[index];
145	}
146
147	/**
148	* Default write handler.
149	*
150	* Writes the specified register value to the state structure.
151	*
152	* @param index Register index in register array.
153	* @param value The value to store (ignored).
154	*/
155	static void Phy::regWriteDefault(PPHY pPhy, uint32_t index, uint16_t u16Value, PPDMDEVINS pDevIns)
156	{
157	RT_NOREF(pDevIns);
158	AssertReturnVoid(index < NUM_OF_PHY_REGS);
159	pPhy->au16Regs[index] = u16Value;
160	}
161
162	/**
163	* Read handler for write-only registers.
164	*
165	* Merely reports reads from write-only registers.
166	*
167	* @returns Register value (always 0)
168	*
169	* @param index Register index in register array.
170	*/
171	static uint16_t Phy::regReadForbidden(PPHY pPhy, uint32_t index, PPDMDEVINS pDevIns)
172	{
173	RT_NOREF(pPhy, index, pDevIns);
174	PhyLog(("PHY#%d At %02d read attempted from write-only '%s'\n",
175	pPhy->iInstance, s_regMap[index].u32Address, s_regMap[index].pszName));
176	return 0;
177	}
178
179	/**
180	* Write handler for read-only registers.
181	*
182	* Merely reports writes to read-only registers.
183	*
184	* @param index Register index in register array.
185	* @param value The value to store (ignored).
186	*/
187	static void Phy::regWriteForbidden(PPHY pPhy, uint32_t index, uint16_t u16Value, PPDMDEVINS pDevIns)
188	{
189	RT_NOREF(pPhy, index, u16Value, pDevIns);
190	PhyLog(("PHY#%d At %02d write attempted to read-only '%s'\n",
191	pPhy->iInstance, s_regMap[index].u32Address, s_regMap[index].pszName));
192	}
193
194	/**
195	* Read handler for unimplemented registers.
196	*
197	* Merely reports reads from unimplemented registers.
198	*
199	* @returns Register value (always 0)
200	*
201	* @param index Register index in register array.
202	*/
203	static uint16_t Phy::regReadUnimplemented(PPHY pPhy, uint32_t index, PPDMDEVINS pDevIns)
204	{
205	RT_NOREF(pPhy, index, pDevIns);
206	PhyLog(("PHY#%d At %02d read attempted from unimplemented '%s'\n",
207	pPhy->iInstance, s_regMap[index].u32Address, s_regMap[index].pszName));
208	return 0;
209	}
210
211	/**
212	* Write handler for unimplemented registers.
213	*
214	* Merely reports writes to unimplemented registers.
215	*
216	* @param index Register index in register array.
217	* @param value The value to store (ignored).
218	*/
219	static void Phy::regWriteUnimplemented(PPHY pPhy, uint32_t index, uint16_t u16Value, PPDMDEVINS pDevIns)
220	{
221	RT_NOREF(pPhy, index, u16Value, pDevIns);
222	PhyLog(("PHY#%d At %02d write attempted to unimplemented '%s'\n",
223	pPhy->iInstance, s_regMap[index].u32Address, s_regMap[index].pszName));
224	}
225
226
227	/**
228	* Search PHY register table for register with matching address.
229	*
230	* @returns Index in the register table or -1 if not found.
231	*
232	* @param u32Address Register address.
233	*/
234	static int Phy::lookupRegister(uint32_t u32Address)
235	{
236	unsigned int index;
237
238	for (index = 0; index < RT_ELEMENTS(s_regMap); index++)
239	{
240	if (s_regMap[index].u32Address == u32Address)
241	{
242	return (int)index;
243	}
244	}
245
246	return -1;
247	}
248
249	/**
250	* Read PHY register.
251	*
252	* @returns Value of specified PHY register.
253	*
254	* @param u32Address Register address.
255	*/
256	uint16_t Phy::readRegister(PPHY pPhy, uint32_t u32Address, PPDMDEVINS pDevIns)
257	{
258	int index = Phy::lookupRegister(u32Address);
259	uint16_t u16 = 0;
260
261	if (index >= 0)
262	{
263	u16 = s_regMap[index].pfnRead(pPhy, (uint32_t)index, pDevIns);
264	PhyLog(("PHY#%d At %02d read %04X from %s (%s)\n",
265	pPhy->iInstance, s_regMap[index].u32Address, u16,
266	s_regMap[index].pszAbbrev, s_regMap[index].pszName));
267	}
268	else
269	{
270	PhyLog(("PHY#%d read attempted from non-existing register %08x\n",
271	pPhy->iInstance, u32Address));
272	}
273	return u16;
274	}
275
276	/**
277	* Write to PHY register.
278	*
279	* @param u32Address Register address.
280	* @param u16Value Value to store.
281	*/
282	void Phy::writeRegister(PPHY pPhy, uint32_t u32Address, uint16_t u16Value, PPDMDEVINS pDevIns)
283	{
284	int index = Phy::lookupRegister(u32Address);
285
286	if (index >= 0)
287	{
288	PhyLog(("PHY#%d At %02d write %04X to %s (%s)\n",
289	pPhy->iInstance, s_regMap[index].u32Address, u16Value,
290	s_regMap[index].pszAbbrev, s_regMap[index].pszName));
291	s_regMap[index].pfnWrite(pPhy, (uint32_t)index, u16Value, pDevIns);
292	}
293	else
294	{
295	PhyLog(("PHY#%d write attempted to non-existing register %08x\n",
296	pPhy->iInstance, u32Address));
297	}
298	}
299
300	/**
301	* PHY constructor.
302	*
303	* Stores E1000 instance internally. Triggers PHY hard reset.
304	*
305	* @param iNICInstance Number of network controller instance this PHY is
306	* attached to.
307	* @param u16EPid Extended PHY Id.
308	*/
309	void Phy::init(PPHY pPhy, int iNICInstance, uint16_t u16EPid)
310	{
311	pPhy->iInstance = iNICInstance;
312	/* The PHY identifier composed of bits 3 through 18 of the OUI */
313	/* (Organizationally Unique Identifier). OUI is 0x05043. */
314	REG(PID) = 0x0141;
315	/* Extended PHY identifier */
316	REG(EPID) = u16EPid;
317	hardReset(pPhy);
318	}
319
320	/**
321	* Hardware PHY reset.
322	*
323	* Sets all PHY registers to their initial values.
324	*/
325	void Phy::hardReset(PPHY pPhy)
326	{
327	PhyLog(("PHY#%d Hard reset\n", pPhy->iInstance));
328	REG(PCTRL) = PCTRL_SPDSELM \| PCTRL_DUPMOD \| PCTRL_ANEG;
329	/*
330	* 100 and 10 FD/HD, Extended Status, MF Preamble Suppression,
331	* AUTO NEG AB, EXT CAP
332	*/
333	REG(PSTATUS) = 0x7949;
334	REG(ANA) = 0x01E1;
335	/* No flow control by our link partner, all speeds */
336	REG(LPA) = 0x01E0;
337	REG(ANE) = 0x0000;
338	REG(NPT) = 0x2001;
339	REG(LPN) = 0x0000;
340	REG(GCON) = 0x1E00;
341	REG(GSTATUS) = 0x0000;
342	REG(EPSTATUS) = 0x3000;
343	REG(PSCON) = 0x0068;
344	REG(PSSTAT) = 0x0000;
345	REG(PINTE) = 0x0000;
346	REG(PINTS) = 0x0000;
347	REG(EPSCON1) = 0x0D60;
348	REG(PREC) = 0x0000;
349	REG(EPSCON2) = 0x000C;
350	REG(R30PS) = 0x0000;
351	REG(R30AW) = 0x0000;
352
353	pPhy->u16State = MDIO_IDLE;
354	}
355
356	/**
357	* Software PHY reset.
358	*/
359	static void Phy::softReset(PPHY pPhy, PPDMDEVINS pDevIns)
360	{
361	PhyLog(("PHY#%d Soft reset\n", pPhy->iInstance));
362
363	REG(PCTRL) = REG(PCTRL) & (PCTRL_SPDSELM \| PCTRL_DUPMOD \| PCTRL_ANEG \| PCTRL_SPDSELL);
364	/*
365	* 100 and 10 FD/HD, Extended Status, MF Preamble Suppression,
366	* AUTO NEG AB, EXT CAP
367	*/
368	REG(PSTATUS) = 0x7949;
369	REG(PSSTAT) &= 0xe001;
370	PhyLog(("PHY#%d PSTATUS=%04x PSSTAT=%04x\n", pPhy->iInstance, REG(PSTATUS), REG(PSSTAT)));
371
372	e1kPhyLinkResetCallback(pDevIns);
373	}
374
375	/**
376	* Get the current state of the link.
377	*
378	* @returns true if link is up.
379	*/
380	bool Phy::isLinkUp(PPHY pPhy)
381	{
382	return (REG(PSSTAT) & PSSTAT_LINK) != 0;
383	}
384
385	/**
386	* Set the current state of the link.
387	*
388	* @remarks Link Status bit in PHY Status register is latched-low and does
389	* not change the state when the link goes up.
390	*
391	* @param fLinkIsUp New state of the link.
392	*/
393	void Phy::setLinkStatus(PPHY pPhy, bool fLinkIsUp)
394	{
395	if (fLinkIsUp)
396	{
397	REG(PSSTAT) \|= PSSTAT_LINK_ALL;
398	REG(PSTATUS) \|= PSTATUS_NEGCOMP; /* PSTATUS_LNKSTAT is latched low */
399	}
400	else
401	{
402	REG(PSSTAT) &= ~PSSTAT_LINK_ALL;
403	REG(PSTATUS) &= ~(PSTATUS_LNKSTAT \| PSTATUS_NEGCOMP);
404	}
405	PhyLog(("PHY#%d setLinkStatus: PSTATUS=%04x PSSTAT=%04x\n", pPhy->iInstance, REG(PSTATUS), REG(PSSTAT)));
406	}
407
408	#ifdef IN_RING3
409
410	/**
411	* Save PHY state.
412	*
413	* @remarks Since PHY is aggregated into E1K it does not currently supports
414	* versioning of its own.
415	*
416	* @returns VBox status code.
417	* @param pHlp Device helper table.
418	* @param pSSM The handle to save the state to.
419	* @param pPhy The pointer to this instance.
420	*/
421	int Phy::saveState(PCPDMDEVHLPR3 pHlp, PSSMHANDLE pSSM, PPHY pPhy)
422	{
423	pHlp->pfnSSMPutMem(pSSM, pPhy->au16Regs, sizeof(pPhy->au16Regs));
424	return VINF_SUCCESS;
425	}
426
427	/**
428	* Restore previously saved PHY state.
429	*
430	* @remarks Since PHY is aggregated into E1K it does not currently supports
431	* versioning of its own.
432	*
433	* @returns VBox status code.
434	* @param pHlp Device helper table.
435	* @param pSSM The handle to save the state to.
436	* @param pPhy The pointer to this instance.
437	*/
438	int Phy::loadState(PCPDMDEVHLPR3 pHlp, PSSMHANDLE pSSM, PPHY pPhy)
439	{
440	return pHlp->pfnSSMGetMem(pSSM, pPhy->au16Regs, sizeof(pPhy->au16Regs));
441	}
442
443	#endif /* IN_RING3 */
444
445	/* Register-specific handlers ************************************************/
446
447	/**
448	* Write handler for PHY Control register.
449	*
450	* Handles reset.
451	*
452	* @param index Register index in register array.
453	* @param value The value to store (ignored).
454	*/
455	static void Phy::regWritePCTRL(PPHY pPhy, uint32_t index, uint16_t u16Value, PPDMDEVINS pDevIns)
456	{
457	if (u16Value & PCTRL_RESET)
458	softReset(pPhy, pDevIns);
459	else
460	regWriteDefault(pPhy, index, u16Value, pDevIns);
461	}
462
463	/**
464	* Read handler for PHY Status register.
465	*
466	* Handles Latched-Low Link Status bit.
467	*
468	* @returns Register value
469	*
470	* @param index Register index in register array.
471	*/
472	static uint16_t Phy::regReadPSTATUS(PPHY pPhy, uint32_t index, PPDMDEVINS pDevIns)
473	{
474	RT_NOREF(pPhy, index, pDevIns);
475
476	/* Read latched value */
477	uint16_t u16 = REG(PSTATUS);
478	if (REG(PSSTAT) & PSSTAT_LINK)
479	REG(PSTATUS) \|= PSTATUS_LNKSTAT;
480	else
481	REG(PSTATUS) &= ~PSTATUS_LNKSTAT;
482	return u16;
483	}
484
485	/**
486	* Read handler for 1000BASE-T Status register.
487	*
488	* @returns Register value
489	*
490	* @param index Register index in register array.
491	*/
492	static uint16_t Phy::regReadGSTATUS(PPHY pPhy, uint32_t index, PPDMDEVINS pDevIns)
493	{
494	RT_NOREF(pPhy, index, pDevIns);
495
496	/*
497	* - Link partner is capable of 1000BASE-T half duplex
498	* - Link partner is capable of 1000BASE-T full duplex
499	* - Remote receiver OK
500	* - Local receiver OK
501	* - Local PHY config resolved to SLAVE
502	*/
503	return 0x3C00;
504	}
505
506	#if defined(LOG_ENABLED) && !defined(PHY_UNIT_TEST)
507	static const char * Phy::getStateName(uint16_t u16State)
508	{
509	static const char *pcszState[] =
510	{
511	"MDIO_IDLE",
512	"MDIO_ST",
513	"MDIO_OP_ADR",
514	"MDIO_TA_RD",
515	"MDIO_TA_WR",
516	"MDIO_READ",
517	"MDIO_WRITE"
518	};
519
520	return (u16State < RT_ELEMENTS(pcszState)) ? pcszState[u16State] : "<invalid>";
521	}
522	#endif
523
524	bool Phy::readMDIO(PPHY pPhy)
525	{
526	bool fPin = false;
527
528	switch (pPhy->u16State)
529	{
530	case MDIO_TA_RD:
531	Assert(pPhy->u16Cnt == 1);
532	fPin = false;
533	pPhy->u16State = MDIO_READ;
534	pPhy->u16Cnt = 16;
535	break;
536	case MDIO_READ:
537	/* Bits are shifted out in MSB to LSB order */
538	fPin = (pPhy->u16Acc & 0x8000) != 0;
539	pPhy->u16Acc <<= 1;
540	if (--pPhy->u16Cnt == 0)
541	pPhy->u16State = MDIO_IDLE;
542	break;
543	default:
544	PhyLog(("PHY#%d WARNING! MDIO pin read in %s state\n", pPhy->iInstance, Phy::getStateName(pPhy->u16State)));
545	pPhy->u16State = MDIO_IDLE;
546	}
547	return fPin;
548	}
549
550	/** Set the value of MDIO pin. */
551	void Phy::writeMDIO(PPHY pPhy, bool fPin, PPDMDEVINS pDevIns)
552	{
553	switch (pPhy->u16State)
554	{
555	case MDIO_IDLE:
556	if (!fPin)
557	pPhy->u16State = MDIO_ST;
558	break;
559	case MDIO_ST:
560	if (fPin)
561	{
562	pPhy->u16State = MDIO_OP_ADR;
563	pPhy->u16Cnt = 12; /* OP + PHYADR + REGADR */
564	pPhy->u16Acc = 0;
565	}
566	break;
567	case MDIO_OP_ADR:
568	Assert(pPhy->u16Cnt);
569	/* Shift in 'u16Cnt' bits into accumulator */
570	pPhy->u16Acc <<= 1;
571	if (fPin)
572	pPhy->u16Acc \|= 1;
573	if (--pPhy->u16Cnt == 0)
574	{
575	/* Got OP(2) + PHYADR(5) + REGADR(5) */
576	/* Note: A single PHY is supported, ignore PHYADR */
577	switch (pPhy->u16Acc >> 10)
578	{
579	case MDIO_READ_OP:
580	pPhy->u16Acc = readRegister(pPhy, pPhy->u16Acc & 0x1F, pDevIns);
581	pPhy->u16State = MDIO_TA_RD;
582	pPhy->u16Cnt = 1;
583	break;
584	case MDIO_WRITE_OP:
585	pPhy->u16RegAdr = pPhy->u16Acc & 0x1F;
586	pPhy->u16State = MDIO_TA_WR;
587	pPhy->u16Cnt = 2;
588	break;
589	default:
590	PhyLog(("PHY#%d ERROR! Invalid MDIO op: %d\n", pPhy->iInstance, pPhy->u16Acc >> 10));
591	pPhy->u16State = MDIO_IDLE;
592	break;
593	}
594	}
595	break;
596	case MDIO_TA_WR:
597	Assert(pPhy->u16Cnt <= 2);
598	Assert(pPhy->u16Cnt > 0);
599	if (--pPhy->u16Cnt == 0)
600	{
601	pPhy->u16State = MDIO_WRITE;
602	pPhy->u16Cnt = 16;
603	}
604	break;
605	case MDIO_WRITE:
606	Assert(pPhy->u16Cnt);
607	pPhy->u16Acc <<= 1;
608	if (fPin)
609	pPhy->u16Acc \|= 1;
610	if (--pPhy->u16Cnt == 0)
611	{
612	writeRegister(pPhy, pPhy->u16RegAdr, pPhy->u16Acc, pDevIns);
613	pPhy->u16State = MDIO_IDLE;
614	}
615	break;
616	default:
617	PhyLog(("PHY#%d ERROR! MDIO pin write in %s state\n", pPhy->iInstance, Phy::getStateName(pPhy->u16State)));
618	pPhy->u16State = MDIO_IDLE;
619	break;
620	}
621	}
622

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source: vbox/trunk/src/VBox/Devices/Network/DevE1000Phy.cpp@ 91942

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