DevE1000Phy.cpp@ 82331

Last change on this file since 82331 was 81465, checked in by vboxsync, 5 years ago
DevE1000: Use device helper table for SSM functions rather than importing them from VBoxVMM.dll/dylib/so. bugref:9218
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1	/** $Id: DevE1000Phy.cpp 81465 2019-10-23 01:10:43Z vboxsync $ */
2	/** @file
3	* DevE1000Phy - Intel 82540EM Ethernet Controller Internal PHY Emulation.
4	*
5	* Implemented in accordance with the specification:
6	* PCI/PCI-X Family of Gigabit Ethernet Controllers Software Developer's
7	* Manual 82540EP/EM, 82541xx, 82544GC/EI, 82545GM/EM, 82546GB/EB, and
8	* 82547xx
9	*
10	* 317453-002 Revision 3.5
11	*/
12
13	/*
14	* Copyright (C) 2007-2019 Oracle Corporation
15	*
16	* This file is part of VirtualBox Open Source Edition (OSE), as
17	* available from http://www.virtualbox.org. This file is free software;
18	* you can redistribute it and/or modify it under the terms of the GNU
19	* General Public License (GPL) as published by the Free Software
20	* Foundation, in version 2 as it comes in the "COPYING" file of the
21	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
22	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
23	*/
24
25	#define LOG_GROUP LOG_GROUP_DEV_E1000
26
27	/** @todo Remove me! For now I want asserts to work in release code. */
28	// #ifndef RT_STRICT
29	// #define RT_STRICT
30	#include <iprt/assert.h>
31	// #undef RT_STRICT
32	// #endif
33
34	#include <iprt/errcore.h>
35	#include <VBox/log.h>
36	#ifdef IN_RING3
37	# include <VBox/vmm/pdmdev.h>
38	#endif
39	#include "DevE1000Phy.h"
40
41	/* Little helpers ************************************************************/
42	#ifdef PHY_UNIT_TEST
43	# define SSMR3PutMem(a,b,c)
44	# define SSMR3GetMem(a,b,c)
45	# include <stdio.h>
46	# define PhyLog(a) printf a
47	#else /* PHY_UNIT_TEST */
48	# define PhyLog(a) Log(a)
49	#endif /* PHY_UNIT_TEST */
50
51	#define REG(x) pPhy->au16Regs[x##_IDX]
52
53
54	/* External callback declaration */
55	void e1kPhyLinkResetCallback(PPDMDEVINS pDevIns);
56
57
58	/* Internals */
59	namespace Phy {
60	#if defined(LOG_ENABLED) && !defined(PHY_UNIT_TEST)
61	/** Retrieves state name by id */
62	static const char * getStateName(uint16_t u16State);
63	#endif
64	/** Look up register index by address. */
65	static int lookupRegister(uint32_t u32Address);
66	/** Software-triggered reset. */
67	static void softReset(PPHY pPhy, PPDMDEVINS pDevIns);
68
69	/** Read callback. */
70	typedef uint16_t FNREAD(PPHY pPhy, uint32_t index, PPDMDEVINS pDevIns);
71	/** Write callback. */
72	typedef void FNWRITE(PPHY pPhy, uint32_t index, uint16_t u16Value, PPDMDEVINS pDevIns);
73
74	/** @name Generic handlers
75	* @{ */
76	static FNREAD regReadDefault;
77	static FNWRITE regWriteDefault;
78	static FNREAD regReadForbidden;
79	static FNWRITE regWriteForbidden;
80	static FNREAD regReadUnimplemented;
81	static FNWRITE regWriteUnimplemented;
82	/** @} */
83	/** @name Register-specific handlers
84	* @{ */
85	static FNWRITE regWritePCTRL;
86	static FNREAD regReadPSTATUS;
87	static FNREAD regReadGSTATUS;
88	/** @} */
89
90	/**
91	* PHY register map table.
92	*
93	* Override pfnRead and pfnWrite to implement register-specific behavior.
94	*/
95	static struct RegMap_st
96	{
97	/** PHY register address. */
98	uint32_t u32Address;
99	/** Read callback. */
100	FNREAD *pfnRead;
101	/** Write callback. */
102	FNWRITE *pfnWrite;
103	/** Abbreviated name. */
104	const char *pszAbbrev;
105	/** Full name. */
106	const char *pszName;
107	} s_regMap[NUM_OF_PHY_REGS] =
108	{
109	/ra read callback write callback abbrev full name /
110	/-- ------------------------- -------------------------- ---------- ------------------------------/
111	{ 0, Phy::regReadDefault , Phy::regWritePCTRL , "PCTRL" , "PHY Control" },
112	{ 1, Phy::regReadPSTATUS , Phy::regWriteForbidden , "PSTATUS" , "PHY Status" },
113	{ 2, Phy::regReadDefault , Phy::regWriteForbidden , "PID" , "PHY Identifier" },
114	{ 3, Phy::regReadDefault , Phy::regWriteForbidden , "EPID" , "Extended PHY Identifier" },
115	{ 4, Phy::regReadDefault , Phy::regWriteDefault , "ANA" , "Auto-Negotiation Advertisement" },
116	{ 5, Phy::regReadDefault , Phy::regWriteForbidden , "LPA" , "Link Partner Ability" },
117	{ 6, Phy::regReadUnimplemented, Phy::regWriteForbidden , "ANE" , "Auto-Negotiation Expansion" },
118	{ 7, Phy::regReadUnimplemented, Phy::regWriteUnimplemented, "NPT" , "Next Page Transmit" },
119	{ 8, Phy::regReadUnimplemented, Phy::regWriteForbidden , "LPN" , "Link Partner Next Page" },
120	{ 9, Phy::regReadDefault , Phy::regWriteUnimplemented, "GCON" , "1000BASE-T Control" },
121	{ 10, Phy::regReadGSTATUS , Phy::regWriteForbidden , "GSTATUS" , "1000BASE-T Status" },
122	{ 15, Phy::regReadUnimplemented, Phy::regWriteForbidden , "EPSTATUS" , "Extended PHY Status" },
123	{ 16, Phy::regReadDefault , Phy::regWriteDefault , "PSCON" , "PHY Specific Control" },
124	{ 17, Phy::regReadDefault , Phy::regWriteForbidden , "PSSTAT" , "PHY Specific Status" },
125	{ 18, Phy::regReadUnimplemented, Phy::regWriteUnimplemented, "PINTE" , "PHY Interrupt Enable" },
126	{ 19, Phy::regReadUnimplemented, Phy::regWriteForbidden , "PINTS" , "PHY Interrupt Status" },
127	{ 20, Phy::regReadUnimplemented, Phy::regWriteUnimplemented, "EPSCON1" , "Extended PHY Specific Control 1" },
128	{ 21, Phy::regReadUnimplemented, Phy::regWriteForbidden , "PREC" , "PHY Receive Error Counter" },
129	{ 26, Phy::regReadUnimplemented, Phy::regWriteUnimplemented, "EPSCON2" , "Extended PHY Specific Control 2" },
130	{ 29, Phy::regReadForbidden , Phy::regWriteUnimplemented, "R30PS" , "MDI Register 30 Page Select" },
131	{ 30, Phy::regReadUnimplemented, Phy::regWriteUnimplemented, "R30AW" , "MDI Register 30 Access Window" }
132	};
133	}
134
135	/**
136	* Default read handler.
137	*
138	* Fetches register value from the state structure.
139	*
140	* @returns Register value
141	*
142	* @param index Register index in register array.
143	*/
144	static uint16_t Phy::regReadDefault(PPHY pPhy, uint32_t index, PPDMDEVINS pDevIns)
145	{
146	RT_NOREF(pDevIns);
147	AssertReturn(index<Phy::NUM_OF_PHY_REGS, 0);
148	return pPhy->au16Regs[index];
149	}
150
151	/**
152	* Default write handler.
153	*
154	* Writes the specified register value to the state structure.
155	*
156	* @param index Register index in register array.
157	* @param value The value to store (ignored).
158	*/
159	static void Phy::regWriteDefault(PPHY pPhy, uint32_t index, uint16_t u16Value, PPDMDEVINS pDevIns)
160	{
161	RT_NOREF(pDevIns);
162	AssertReturnVoid(index < NUM_OF_PHY_REGS);
163	pPhy->au16Regs[index] = u16Value;
164	}
165
166	/**
167	* Read handler for write-only registers.
168	*
169	* Merely reports reads from write-only registers.
170	*
171	* @returns Register value (always 0)
172	*
173	* @param index Register index in register array.
174	*/
175	static uint16_t Phy::regReadForbidden(PPHY pPhy, uint32_t index, PPDMDEVINS pDevIns)
176	{
177	RT_NOREF(pPhy, index, pDevIns);
178	PhyLog(("PHY#%d At %02d read attempted from write-only '%s'\n",
179	pPhy->iInstance, s_regMap[index].u32Address, s_regMap[index].pszName));
180	return 0;
181	}
182
183	/**
184	* Write handler for read-only registers.
185	*
186	* Merely reports writes to read-only registers.
187	*
188	* @param index Register index in register array.
189	* @param value The value to store (ignored).
190	*/
191	static void Phy::regWriteForbidden(PPHY pPhy, uint32_t index, uint16_t u16Value, PPDMDEVINS pDevIns)
192	{
193	RT_NOREF(pPhy, index, u16Value, pDevIns);
194	PhyLog(("PHY#%d At %02d write attempted to read-only '%s'\n",
195	pPhy->iInstance, s_regMap[index].u32Address, s_regMap[index].pszName));
196	}
197
198	/**
199	* Read handler for unimplemented registers.
200	*
201	* Merely reports reads from unimplemented registers.
202	*
203	* @returns Register value (always 0)
204	*
205	* @param index Register index in register array.
206	*/
207	static uint16_t Phy::regReadUnimplemented(PPHY pPhy, uint32_t index, PPDMDEVINS pDevIns)
208	{
209	RT_NOREF(pPhy, index, pDevIns);
210	PhyLog(("PHY#%d At %02d read attempted from unimplemented '%s'\n",
211	pPhy->iInstance, s_regMap[index].u32Address, s_regMap[index].pszName));
212	return 0;
213	}
214
215	/**
216	* Write handler for unimplemented registers.
217	*
218	* Merely reports writes to unimplemented registers.
219	*
220	* @param index Register index in register array.
221	* @param value The value to store (ignored).
222	*/
223	static void Phy::regWriteUnimplemented(PPHY pPhy, uint32_t index, uint16_t u16Value, PPDMDEVINS pDevIns)
224	{
225	RT_NOREF(pPhy, index, u16Value, pDevIns);
226	PhyLog(("PHY#%d At %02d write attempted to unimplemented '%s'\n",
227	pPhy->iInstance, s_regMap[index].u32Address, s_regMap[index].pszName));
228	}
229
230
231	/**
232	* Search PHY register table for register with matching address.
233	*
234	* @returns Index in the register table or -1 if not found.
235	*
236	* @param u32Address Register address.
237	*/
238	static int Phy::lookupRegister(uint32_t u32Address)
239	{
240	unsigned int index;
241
242	for (index = 0; index < RT_ELEMENTS(s_regMap); index++)
243	{
244	if (s_regMap[index].u32Address == u32Address)
245	{
246	return index;
247	}
248	}
249
250	return -1;
251	}
252
253	/**
254	* Read PHY register.
255	*
256	* @returns Value of specified PHY register.
257	*
258	* @param u32Address Register address.
259	*/
260	uint16_t Phy::readRegister(PPHY pPhy, uint32_t u32Address, PPDMDEVINS pDevIns)
261	{
262	int index = Phy::lookupRegister(u32Address);
263	uint16_t u16 = 0;
264
265	if (index != -1)
266	{
267	u16 = s_regMap[index].pfnRead(pPhy, index, pDevIns);
268	PhyLog(("PHY#%d At %02d read %04X from %s (%s)\n",
269	pPhy->iInstance, s_regMap[index].u32Address, u16,
270	s_regMap[index].pszAbbrev, s_regMap[index].pszName));
271	}
272	else
273	{
274	PhyLog(("PHY#%d read attempted from non-existing register %08x\n",
275	pPhy->iInstance, u32Address));
276	}
277	return u16;
278	}
279
280	/**
281	* Write to PHY register.
282	*
283	* @param u32Address Register address.
284	* @param u16Value Value to store.
285	*/
286	void Phy::writeRegister(PPHY pPhy, uint32_t u32Address, uint16_t u16Value, PPDMDEVINS pDevIns)
287	{
288	int index = Phy::lookupRegister(u32Address);
289
290	if (index != -1)
291	{
292	PhyLog(("PHY#%d At %02d write %04X to %s (%s)\n",
293	pPhy->iInstance, s_regMap[index].u32Address, u16Value,
294	s_regMap[index].pszAbbrev, s_regMap[index].pszName));
295	s_regMap[index].pfnWrite(pPhy, index, u16Value, pDevIns);
296	}
297	else
298	{
299	PhyLog(("PHY#%d write attempted to non-existing register %08x\n",
300	pPhy->iInstance, u32Address));
301	}
302	}
303
304	/**
305	* PHY constructor.
306	*
307	* Stores E1000 instance internally. Triggers PHY hard reset.
308	*
309	* @param iNICInstance Number of network controller instance this PHY is
310	* attached to.
311	* @param u16EPid Extended PHY Id.
312	*/
313	void Phy::init(PPHY pPhy, int iNICInstance, uint16_t u16EPid)
314	{
315	pPhy->iInstance = iNICInstance;
316	/* The PHY identifier composed of bits 3 through 18 of the OUI */
317	/* (Organizationally Unique Identifier). OUI is 0x05043. */
318	REG(PID) = 0x0141;
319	/* Extended PHY identifier */
320	REG(EPID) = u16EPid;
321	hardReset(pPhy);
322	}
323
324	/**
325	* Hardware PHY reset.
326	*
327	* Sets all PHY registers to their initial values.
328	*/
329	void Phy::hardReset(PPHY pPhy)
330	{
331	PhyLog(("PHY#%d Hard reset\n", pPhy->iInstance));
332	REG(PCTRL) = PCTRL_SPDSELM \| PCTRL_DUPMOD \| PCTRL_ANEG;
333	/*
334	* 100 and 10 FD/HD, Extended Status, MF Preamble Suppression,
335	* AUTO NEG AB, EXT CAP
336	*/
337	REG(PSTATUS) = 0x7949;
338	REG(ANA) = 0x01E1;
339	/* No flow control by our link partner, all speeds */
340	REG(LPA) = 0x01E0;
341	REG(ANE) = 0x0000;
342	REG(NPT) = 0x2001;
343	REG(LPN) = 0x0000;
344	REG(GCON) = 0x1E00;
345	REG(GSTATUS) = 0x0000;
346	REG(EPSTATUS) = 0x3000;
347	REG(PSCON) = 0x0068;
348	REG(PSSTAT) = 0x0000;
349	REG(PINTE) = 0x0000;
350	REG(PINTS) = 0x0000;
351	REG(EPSCON1) = 0x0D60;
352	REG(PREC) = 0x0000;
353	REG(EPSCON2) = 0x000C;
354	REG(R30PS) = 0x0000;
355	REG(R30AW) = 0x0000;
356
357	pPhy->u16State = MDIO_IDLE;
358	}
359
360	/**
361	* Software PHY reset.
362	*/
363	static void Phy::softReset(PPHY pPhy, PPDMDEVINS pDevIns)
364	{
365	PhyLog(("PHY#%d Soft reset\n", pPhy->iInstance));
366
367	REG(PCTRL) = REG(PCTRL) & (PCTRL_SPDSELM \| PCTRL_DUPMOD \| PCTRL_ANEG \| PCTRL_SPDSELL);
368	/*
369	* 100 and 10 FD/HD, Extended Status, MF Preamble Suppression,
370	* AUTO NEG AB, EXT CAP
371	*/
372	REG(PSTATUS) = 0x7949;
373	REG(PSSTAT) &= 0xe001;
374	PhyLog(("PHY#%d PSTATUS=%04x PSSTAT=%04x\n", pPhy->iInstance, REG(PSTATUS), REG(PSSTAT)));
375
376	e1kPhyLinkResetCallback(pDevIns);
377	}
378
379	/**
380	* Get the current state of the link.
381	*
382	* @returns true if link is up.
383	*/
384	bool Phy::isLinkUp(PPHY pPhy)
385	{
386	return (REG(PSSTAT) & PSSTAT_LINK) != 0;
387	}
388
389	/**
390	* Set the current state of the link.
391	*
392	* @remarks Link Status bit in PHY Status register is latched-low and does
393	* not change the state when the link goes up.
394	*
395	* @param fLinkIsUp New state of the link.
396	*/
397	void Phy::setLinkStatus(PPHY pPhy, bool fLinkIsUp)
398	{
399	if (fLinkIsUp)
400	{
401	REG(PSSTAT) \|= PSSTAT_LINK_ALL;
402	REG(PSTATUS) \|= PSTATUS_NEGCOMP; /* PSTATUS_LNKSTAT is latched low */
403	}
404	else
405	{
406	REG(PSSTAT) &= ~PSSTAT_LINK_ALL;
407	REG(PSTATUS) &= ~(PSTATUS_LNKSTAT \| PSTATUS_NEGCOMP);
408	}
409	PhyLog(("PHY#%d setLinkStatus: PSTATUS=%04x PSSTAT=%04x\n", pPhy->iInstance, REG(PSTATUS), REG(PSSTAT)));
410	}
411
412	#ifdef IN_RING3
413
414	/**
415	* Save PHY state.
416	*
417	* @remarks Since PHY is aggregated into E1K it does not currently supports
418	* versioning of its own.
419	*
420	* @returns VBox status code.
421	* @param pHlp Device helper table.
422	* @param pSSM The handle to save the state to.
423	* @param pPhy The pointer to this instance.
424	*/
425	int Phy::saveState(PCPDMDEVHLPR3 pHlp, PSSMHANDLE pSSM, PPHY pPhy)
426	{
427	pHlp->pfnSSMPutMem(pSSM, pPhy->au16Regs, sizeof(pPhy->au16Regs));
428	return VINF_SUCCESS;
429	}
430
431	/**
432	* Restore previously saved PHY state.
433	*
434	* @remarks Since PHY is aggregated into E1K it does not currently supports
435	* versioning of its own.
436	*
437	* @returns VBox status code.
438	* @param pHlp Device helper table.
439	* @param pSSM The handle to save the state to.
440	* @param pPhy The pointer to this instance.
441	*/
442	int Phy::loadState(PCPDMDEVHLPR3 pHlp, PSSMHANDLE pSSM, PPHY pPhy)
443	{
444	return pHlp->pfnSSMGetMem(pSSM, pPhy->au16Regs, sizeof(pPhy->au16Regs));
445	}
446
447	#endif /* IN_RING3 */
448
449	/* Register-specific handlers ************************************************/
450
451	/**
452	* Write handler for PHY Control register.
453	*
454	* Handles reset.
455	*
456	* @param index Register index in register array.
457	* @param value The value to store (ignored).
458	*/
459	static void Phy::regWritePCTRL(PPHY pPhy, uint32_t index, uint16_t u16Value, PPDMDEVINS pDevIns)
460	{
461	if (u16Value & PCTRL_RESET)
462	softReset(pPhy, pDevIns);
463	else
464	regWriteDefault(pPhy, index, u16Value, pDevIns);
465	}
466
467	/**
468	* Read handler for PHY Status register.
469	*
470	* Handles Latched-Low Link Status bit.
471	*
472	* @returns Register value
473	*
474	* @param index Register index in register array.
475	*/
476	static uint16_t Phy::regReadPSTATUS(PPHY pPhy, uint32_t index, PPDMDEVINS pDevIns)
477	{
478	RT_NOREF(pPhy, index, pDevIns);
479
480	/* Read latched value */
481	uint16_t u16 = REG(PSTATUS);
482	if (REG(PSSTAT) & PSSTAT_LINK)
483	REG(PSTATUS) \|= PSTATUS_LNKSTAT;
484	else
485	REG(PSTATUS) &= ~PSTATUS_LNKSTAT;
486	return u16;
487	}
488
489	/**
490	* Read handler for 1000BASE-T Status register.
491	*
492	* @returns Register value
493	*
494	* @param index Register index in register array.
495	*/
496	static uint16_t Phy::regReadGSTATUS(PPHY pPhy, uint32_t index, PPDMDEVINS pDevIns)
497	{
498	RT_NOREF(pPhy, index, pDevIns);
499
500	/*
501	* - Link partner is capable of 1000BASE-T half duplex
502	* - Link partner is capable of 1000BASE-T full duplex
503	* - Remote receiver OK
504	* - Local receiver OK
505	* - Local PHY config resolved to SLAVE
506	*/
507	return 0x3C00;
508	}
509
510	#if defined(LOG_ENABLED) && !defined(PHY_UNIT_TEST)
511	static const char * Phy::getStateName(uint16_t u16State)
512	{
513	static const char *pcszState[] =
514	{
515	"MDIO_IDLE",
516	"MDIO_ST",
517	"MDIO_OP_ADR",
518	"MDIO_TA_RD",
519	"MDIO_TA_WR",
520	"MDIO_READ",
521	"MDIO_WRITE"
522	};
523
524	return (u16State < RT_ELEMENTS(pcszState)) ? pcszState[u16State] : "<invalid>";
525	}
526	#endif
527
528	bool Phy::readMDIO(PPHY pPhy)
529	{
530	bool fPin = false;
531
532	switch (pPhy->u16State)
533	{
534	case MDIO_TA_RD:
535	Assert(pPhy->u16Cnt == 1);
536	fPin = false;
537	pPhy->u16State = MDIO_READ;
538	pPhy->u16Cnt = 16;
539	break;
540	case MDIO_READ:
541	/* Bits are shifted out in MSB to LSB order */
542	fPin = (pPhy->u16Acc & 0x8000) != 0;
543	pPhy->u16Acc <<= 1;
544	if (--pPhy->u16Cnt == 0)
545	pPhy->u16State = MDIO_IDLE;
546	break;
547	default:
548	PhyLog(("PHY#%d WARNING! MDIO pin read in %s state\n", pPhy->iInstance, Phy::getStateName(pPhy->u16State)));
549	pPhy->u16State = MDIO_IDLE;
550	}
551	return fPin;
552	}
553
554	/** Set the value of MDIO pin. */
555	void Phy::writeMDIO(PPHY pPhy, bool fPin, PPDMDEVINS pDevIns)
556	{
557	switch (pPhy->u16State)
558	{
559	case MDIO_IDLE:
560	if (!fPin)
561	pPhy->u16State = MDIO_ST;
562	break;
563	case MDIO_ST:
564	if (fPin)
565	{
566	pPhy->u16State = MDIO_OP_ADR;
567	pPhy->u16Cnt = 12; /* OP + PHYADR + REGADR */
568	pPhy->u16Acc = 0;
569	}
570	break;
571	case MDIO_OP_ADR:
572	Assert(pPhy->u16Cnt);
573	/* Shift in 'u16Cnt' bits into accumulator */
574	pPhy->u16Acc <<= 1;
575	if (fPin)
576	pPhy->u16Acc \|= 1;
577	if (--pPhy->u16Cnt == 0)
578	{
579	/* Got OP(2) + PHYADR(5) + REGADR(5) */
580	/* Note: A single PHY is supported, ignore PHYADR */
581	switch (pPhy->u16Acc >> 10)
582	{
583	case MDIO_READ_OP:
584	pPhy->u16Acc = readRegister(pPhy, pPhy->u16Acc & 0x1F, pDevIns);
585	pPhy->u16State = MDIO_TA_RD;
586	pPhy->u16Cnt = 1;
587	break;
588	case MDIO_WRITE_OP:
589	pPhy->u16RegAdr = pPhy->u16Acc & 0x1F;
590	pPhy->u16State = MDIO_TA_WR;
591	pPhy->u16Cnt = 2;
592	break;
593	default:
594	PhyLog(("PHY#%d ERROR! Invalid MDIO op: %d\n", pPhy->iInstance, pPhy->u16Acc >> 10));
595	pPhy->u16State = MDIO_IDLE;
596	break;
597	}
598	}
599	break;
600	case MDIO_TA_WR:
601	Assert(pPhy->u16Cnt <= 2);
602	Assert(pPhy->u16Cnt > 0);
603	if (--pPhy->u16Cnt == 0)
604	{
605	pPhy->u16State = MDIO_WRITE;
606	pPhy->u16Cnt = 16;
607	}
608	break;
609	case MDIO_WRITE:
610	Assert(pPhy->u16Cnt);
611	pPhy->u16Acc <<= 1;
612	if (fPin)
613	pPhy->u16Acc \|= 1;
614	if (--pPhy->u16Cnt == 0)
615	{
616	writeRegister(pPhy, pPhy->u16RegAdr, pPhy->u16Acc, pDevIns);
617	pPhy->u16State = MDIO_IDLE;
618	}
619	break;
620	default:
621	PhyLog(("PHY#%d ERROR! MDIO pin write in %s state\n", pPhy->iInstance, Phy::getStateName(pPhy->u16State)));
622	pPhy->u16State = MDIO_IDLE;
623	break;
624	}
625	}
626

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source: vbox/trunk/src/VBox/Devices/Network/DevE1000Phy.cpp@ 82331

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