DevE1000Phy.cpp@ 102827

Last change on this file since 102827 was 98172, checked in by vboxsync, 22 months ago
Devices/Network: Wrapped the cppunit tests tstDevEEPROM and tstDevPhy to IPRT testing.
Property svn:eol-style set to `native` Property svn:keywords set to `Author Date Id Revision`
File size: 19.6 KB

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1	/** $Id: DevE1000Phy.cpp 98172 2023-01-21 13:01:48Z vboxsync $ */
2	/** @file
3	* DevE1000Phy - Intel 82540EM Ethernet Controller Internal PHY Emulation.
4	*
5	* Implemented in accordance with the specification:
6	* PCI/PCI-X Family of Gigabit Ethernet Controllers Software Developer's
7	* Manual 82540EP/EM, 82541xx, 82544GC/EI, 82545GM/EM, 82546GB/EB, and
8	* 82547xx
9	*
10	* 317453-002 Revision 3.5
11	*/
12
13	/*
14	* Copyright (C) 2007-2023 Oracle and/or its affiliates.
15	*
16	* This file is part of VirtualBox base platform packages, as
17	* available from https://www.virtualbox.org.
18	*
19	* This program is free software; you can redistribute it and/or
20	* modify it under the terms of the GNU General Public License
21	* as published by the Free Software Foundation, in version 3 of the
22	* License.
23	*
24	* This program is distributed in the hope that it will be useful, but
25	* WITHOUT ANY WARRANTY; without even the implied warranty of
26	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
27	* General Public License for more details.
28	*
29	* You should have received a copy of the GNU General Public License
30	* along with this program; if not, see <https://www.gnu.org/licenses>.
31	*
32	* SPDX-License-Identifier: GPL-3.0-only
33	*/
34
35	#define LOG_GROUP LOG_GROUP_DEV_E1000
36
37	/** @todo Remove me! For now I want asserts to work in release code. */
38	// #ifndef RT_STRICT
39	// #define RT_STRICT
40	#include <iprt/assert.h>
41	// #undef RT_STRICT
42	// #endif
43
44	#include <iprt/errcore.h>
45	#include <VBox/log.h>
46	#ifdef IN_RING3
47	# include <VBox/vmm/pdmdev.h>
48	#endif
49	#include "DevE1000Phy.h"
50
51	/* Little helpers ************************************************************/
52	#ifdef PHY_UNIT_TEST
53	# ifdef CPP_UNIT
54	# include <stdio.h>
55	# define PhyLog(a) printf a
56	# else
57	# include <iprt/test.h>
58	# define PhyLogC99(...) RTTestIPrintf(RTTESTLVL_ALWAYS, __VA_ARGS__)
59	# define PhyLog(a) PhyLogC99 a
60	# endif
61	#else /* !PHY_UNIT_TEST */
62	# define PhyLog(a) Log(a)
63	#endif /* !PHY_UNIT_TEST */
64
65	#define REG(x) pPhy->au16Regs[x##_IDX]
66
67
68	/* Internals */
69	namespace Phy {
70	#if defined(LOG_ENABLED) \|\| defined(PHY_UNIT_TEST)
71	/** Retrieves state name by id */
72	static const char * getStateName(uint16_t u16State);
73	#endif
74	/** Look up register index by address. */
75	static int lookupRegister(uint32_t u32Address);
76	/** Software-triggered reset. */
77	static void softReset(PPHY pPhy, PPDMDEVINS pDevIns);
78
79	/** Read callback. */
80	typedef uint16_t FNREAD(PPHY pPhy, uint32_t index, PPDMDEVINS pDevIns);
81	/** Write callback. */
82	typedef void FNWRITE(PPHY pPhy, uint32_t index, uint16_t u16Value, PPDMDEVINS pDevIns);
83
84	/** @name Generic handlers
85	* @{ */
86	static FNREAD regReadDefault;
87	static FNWRITE regWriteDefault;
88	static FNREAD regReadForbidden;
89	static FNWRITE regWriteForbidden;
90	static FNREAD regReadUnimplemented;
91	static FNWRITE regWriteUnimplemented;
92	/** @} */
93	/** @name Register-specific handlers
94	* @{ */
95	static FNWRITE regWritePCTRL;
96	static FNREAD regReadPSTATUS;
97	static FNREAD regReadGSTATUS;
98	/** @} */
99
100	/**
101	* PHY register map table.
102	*
103	* Override pfnRead and pfnWrite to implement register-specific behavior.
104	*/
105	static struct RegMap_st
106	{
107	/** PHY register address. */
108	uint32_t u32Address;
109	/** Read callback. */
110	FNREAD *pfnRead;
111	/** Write callback. */
112	FNWRITE *pfnWrite;
113	/** Abbreviated name. */
114	const char *pszAbbrev;
115	/** Full name. */
116	const char *pszName;
117	} s_regMap[NUM_OF_PHY_REGS] =
118	{
119	/ra read callback write callback abbrev full name /
120	/-- ------------------------- -------------------------- ---------- ------------------------------/
121	{ 0, Phy::regReadDefault , Phy::regWritePCTRL , "PCTRL" , "PHY Control" },
122	{ 1, Phy::regReadPSTATUS , Phy::regWriteForbidden , "PSTATUS" , "PHY Status" },
123	{ 2, Phy::regReadDefault , Phy::regWriteForbidden , "PID" , "PHY Identifier" },
124	{ 3, Phy::regReadDefault , Phy::regWriteForbidden , "EPID" , "Extended PHY Identifier" },
125	{ 4, Phy::regReadDefault , Phy::regWriteDefault , "ANA" , "Auto-Negotiation Advertisement" },
126	{ 5, Phy::regReadDefault , Phy::regWriteForbidden , "LPA" , "Link Partner Ability" },
127	{ 6, Phy::regReadUnimplemented, Phy::regWriteForbidden , "ANE" , "Auto-Negotiation Expansion" },
128	{ 7, Phy::regReadUnimplemented, Phy::regWriteUnimplemented, "NPT" , "Next Page Transmit" },
129	{ 8, Phy::regReadUnimplemented, Phy::regWriteForbidden , "LPN" , "Link Partner Next Page" },
130	{ 9, Phy::regReadDefault , Phy::regWriteUnimplemented, "GCON" , "1000BASE-T Control" },
131	{ 10, Phy::regReadGSTATUS , Phy::regWriteForbidden , "GSTATUS" , "1000BASE-T Status" },
132	{ 15, Phy::regReadUnimplemented, Phy::regWriteForbidden , "EPSTATUS" , "Extended PHY Status" },
133	{ 16, Phy::regReadDefault , Phy::regWriteDefault , "PSCON" , "PHY Specific Control" },
134	{ 17, Phy::regReadDefault , Phy::regWriteForbidden , "PSSTAT" , "PHY Specific Status" },
135	{ 18, Phy::regReadUnimplemented, Phy::regWriteUnimplemented, "PINTE" , "PHY Interrupt Enable" },
136	{ 19, Phy::regReadUnimplemented, Phy::regWriteForbidden , "PINTS" , "PHY Interrupt Status" },
137	{ 20, Phy::regReadUnimplemented, Phy::regWriteUnimplemented, "EPSCON1" , "Extended PHY Specific Control 1" },
138	{ 21, Phy::regReadUnimplemented, Phy::regWriteForbidden , "PREC" , "PHY Receive Error Counter" },
139	{ 26, Phy::regReadUnimplemented, Phy::regWriteUnimplemented, "EPSCON2" , "Extended PHY Specific Control 2" },
140	{ 29, Phy::regReadForbidden , Phy::regWriteUnimplemented, "R30PS" , "MDI Register 30 Page Select" },
141	{ 30, Phy::regReadUnimplemented, Phy::regWriteUnimplemented, "R30AW" , "MDI Register 30 Access Window" }
142	};
143	}
144
145	/**
146	* Default read handler.
147	*
148	* Fetches register value from the state structure.
149	*
150	* @returns Register value
151	*
152	* @param index Register index in register array.
153	*/
154	static uint16_t Phy::regReadDefault(PPHY pPhy, uint32_t index, PPDMDEVINS pDevIns)
155	{
156	RT_NOREF(pDevIns);
157	AssertReturn(index<Phy::NUM_OF_PHY_REGS, 0);
158	return pPhy->au16Regs[index];
159	}
160
161	/**
162	* Default write handler.
163	*
164	* Writes the specified register value to the state structure.
165	*
166	* @param index Register index in register array.
167	* @param value The value to store (ignored).
168	*/
169	static void Phy::regWriteDefault(PPHY pPhy, uint32_t index, uint16_t u16Value, PPDMDEVINS pDevIns)
170	{
171	RT_NOREF(pDevIns);
172	AssertReturnVoid(index < NUM_OF_PHY_REGS);
173	pPhy->au16Regs[index] = u16Value;
174	}
175
176	/**
177	* Read handler for write-only registers.
178	*
179	* Merely reports reads from write-only registers.
180	*
181	* @returns Register value (always 0)
182	*
183	* @param index Register index in register array.
184	*/
185	static uint16_t Phy::regReadForbidden(PPHY pPhy, uint32_t index, PPDMDEVINS pDevIns)
186	{
187	RT_NOREF(pPhy, index, pDevIns);
188	PhyLog(("PHY#%d At %02d read attempted from write-only '%s'\n",
189	pPhy->iInstance, s_regMap[index].u32Address, s_regMap[index].pszName));
190	return 0;
191	}
192
193	/**
194	* Write handler for read-only registers.
195	*
196	* Merely reports writes to read-only registers.
197	*
198	* @param index Register index in register array.
199	* @param value The value to store (ignored).
200	*/
201	static void Phy::regWriteForbidden(PPHY pPhy, uint32_t index, uint16_t u16Value, PPDMDEVINS pDevIns)
202	{
203	RT_NOREF(pPhy, index, u16Value, pDevIns);
204	PhyLog(("PHY#%d At %02d write attempted to read-only '%s'\n",
205	pPhy->iInstance, s_regMap[index].u32Address, s_regMap[index].pszName));
206	}
207
208	/**
209	* Read handler for unimplemented registers.
210	*
211	* Merely reports reads from unimplemented registers.
212	*
213	* @returns Register value (always 0)
214	*
215	* @param index Register index in register array.
216	*/
217	static uint16_t Phy::regReadUnimplemented(PPHY pPhy, uint32_t index, PPDMDEVINS pDevIns)
218	{
219	RT_NOREF(pPhy, index, pDevIns);
220	PhyLog(("PHY#%d At %02d read attempted from unimplemented '%s'\n",
221	pPhy->iInstance, s_regMap[index].u32Address, s_regMap[index].pszName));
222	return 0;
223	}
224
225	/**
226	* Write handler for unimplemented registers.
227	*
228	* Merely reports writes to unimplemented registers.
229	*
230	* @param index Register index in register array.
231	* @param value The value to store (ignored).
232	*/
233	static void Phy::regWriteUnimplemented(PPHY pPhy, uint32_t index, uint16_t u16Value, PPDMDEVINS pDevIns)
234	{
235	RT_NOREF(pPhy, index, u16Value, pDevIns);
236	PhyLog(("PHY#%d At %02d write attempted to unimplemented '%s'\n",
237	pPhy->iInstance, s_regMap[index].u32Address, s_regMap[index].pszName));
238	}
239
240
241	/**
242	* Search PHY register table for register with matching address.
243	*
244	* @returns Index in the register table or -1 if not found.
245	*
246	* @param u32Address Register address.
247	*/
248	static int Phy::lookupRegister(uint32_t u32Address)
249	{
250	unsigned int index;
251
252	for (index = 0; index < RT_ELEMENTS(s_regMap); index++)
253	{
254	if (s_regMap[index].u32Address == u32Address)
255	{
256	return (int)index;
257	}
258	}
259
260	return -1;
261	}
262
263	/**
264	* Read PHY register.
265	*
266	* @returns Value of specified PHY register.
267	*
268	* @param u32Address Register address.
269	*/
270	uint16_t Phy::readRegister(PPHY pPhy, uint32_t u32Address, PPDMDEVINS pDevIns)
271	{
272	int index = Phy::lookupRegister(u32Address);
273	uint16_t u16 = 0;
274
275	if (index >= 0)
276	{
277	u16 = s_regMap[index].pfnRead(pPhy, (uint32_t)index, pDevIns);
278	PhyLog(("PHY#%d At %02d read %04X from %s (%s)\n",
279	pPhy->iInstance, s_regMap[index].u32Address, u16,
280	s_regMap[index].pszAbbrev, s_regMap[index].pszName));
281	}
282	else
283	{
284	PhyLog(("PHY#%d read attempted from non-existing register %08x\n",
285	pPhy->iInstance, u32Address));
286	}
287	return u16;
288	}
289
290	/**
291	* Write to PHY register.
292	*
293	* @param u32Address Register address.
294	* @param u16Value Value to store.
295	*/
296	void Phy::writeRegister(PPHY pPhy, uint32_t u32Address, uint16_t u16Value, PPDMDEVINS pDevIns)
297	{
298	int index = Phy::lookupRegister(u32Address);
299
300	if (index >= 0)
301	{
302	PhyLog(("PHY#%d At %02d write %04X to %s (%s)\n",
303	pPhy->iInstance, s_regMap[index].u32Address, u16Value,
304	s_regMap[index].pszAbbrev, s_regMap[index].pszName));
305	s_regMap[index].pfnWrite(pPhy, (uint32_t)index, u16Value, pDevIns);
306	}
307	else
308	{
309	PhyLog(("PHY#%d write attempted to non-existing register %08x\n",
310	pPhy->iInstance, u32Address));
311	}
312	}
313
314	/**
315	* PHY constructor.
316	*
317	* Stores E1000 instance internally. Triggers PHY hard reset.
318	*
319	* @param iNICInstance Number of network controller instance this PHY is
320	* attached to.
321	* @param u16EPid Extended PHY Id.
322	*/
323	void Phy::init(PPHY pPhy, int iNICInstance, uint16_t u16EPid)
324	{
325	pPhy->iInstance = iNICInstance;
326	/* The PHY identifier composed of bits 3 through 18 of the OUI */
327	/* (Organizationally Unique Identifier). OUI is 0x05043. */
328	REG(PID) = 0x0141;
329	/* Extended PHY identifier */
330	REG(EPID) = u16EPid;
331	hardReset(pPhy);
332	}
333
334	/**
335	* Hardware PHY reset.
336	*
337	* Sets all PHY registers to their initial values.
338	*/
339	void Phy::hardReset(PPHY pPhy)
340	{
341	PhyLog(("PHY#%d Hard reset\n", pPhy->iInstance));
342	REG(PCTRL) = PCTRL_SPDSELM \| PCTRL_DUPMOD \| PCTRL_ANEG;
343	/*
344	* 100 and 10 FD/HD, Extended Status, MF Preamble Suppression,
345	* AUTO NEG AB, EXT CAP
346	*/
347	REG(PSTATUS) = 0x7949;
348	REG(ANA) = 0x01E1;
349	/* No flow control by our link partner, all speeds */
350	REG(LPA) = 0x01E0;
351	REG(ANE) = 0x0000;
352	REG(NPT) = 0x2001;
353	REG(LPN) = 0x0000;
354	REG(GCON) = 0x1E00;
355	REG(GSTATUS) = 0x0000;
356	REG(EPSTATUS) = 0x3000;
357	REG(PSCON) = 0x0068;
358	REG(PSSTAT) = 0x0000;
359	REG(PINTE) = 0x0000;
360	REG(PINTS) = 0x0000;
361	REG(EPSCON1) = 0x0D60;
362	REG(PREC) = 0x0000;
363	REG(EPSCON2) = 0x000C;
364	REG(R30PS) = 0x0000;
365	REG(R30AW) = 0x0000;
366
367	pPhy->u16State = MDIO_IDLE;
368	}
369
370	/**
371	* Software PHY reset.
372	*/
373	static void Phy::softReset(PPHY pPhy, PPDMDEVINS pDevIns)
374	{
375	PhyLog(("PHY#%d Soft reset\n", pPhy->iInstance));
376
377	REG(PCTRL) = REG(PCTRL) & (PCTRL_SPDSELM \| PCTRL_DUPMOD \| PCTRL_ANEG \| PCTRL_SPDSELL);
378	/*
379	* 100 and 10 FD/HD, Extended Status, MF Preamble Suppression,
380	* AUTO NEG AB, EXT CAP
381	*/
382	REG(PSTATUS) = 0x7949;
383	REG(PSSTAT) &= 0xe001;
384	PhyLog(("PHY#%d PSTATUS=%04x PSSTAT=%04x\n", pPhy->iInstance, REG(PSTATUS), REG(PSSTAT)));
385
386	#ifndef PHY_UNIT_TEST
387	e1kPhyLinkResetCallback(pDevIns);
388	#else
389	RT_NOREF(pDevIns);
390	#endif
391	}
392
393	/**
394	* Get the current state of the link.
395	*
396	* @returns true if link is up.
397	*/
398	bool Phy::isLinkUp(PPHY pPhy)
399	{
400	return (REG(PSSTAT) & PSSTAT_LINK) != 0;
401	}
402
403	/**
404	* Set the current state of the link.
405	*
406	* @remarks Link Status bit in PHY Status register is latched-low and does
407	* not change the state when the link goes up.
408	*
409	* @param fLinkIsUp New state of the link.
410	*/
411	void Phy::setLinkStatus(PPHY pPhy, bool fLinkIsUp)
412	{
413	if (fLinkIsUp)
414	{
415	REG(PSSTAT) \|= PSSTAT_LINK_ALL;
416	REG(PSTATUS) \|= PSTATUS_NEGCOMP; /* PSTATUS_LNKSTAT is latched low */
417	}
418	else
419	{
420	REG(PSSTAT) &= ~PSSTAT_LINK_ALL;
421	REG(PSTATUS) &= ~(PSTATUS_LNKSTAT \| PSTATUS_NEGCOMP);
422	}
423	PhyLog(("PHY#%d setLinkStatus: PSTATUS=%04x PSSTAT=%04x\n", pPhy->iInstance, REG(PSTATUS), REG(PSSTAT)));
424	}
425
426	#ifdef IN_RING3
427
428	/**
429	* Save PHY state.
430	*
431	* @remarks Since PHY is aggregated into E1K it does not currently supports
432	* versioning of its own.
433	*
434	* @returns VBox status code.
435	* @param pHlp Device helper table.
436	* @param pSSM The handle to save the state to.
437	* @param pPhy The pointer to this instance.
438	*/
439	int Phy::saveState(PCPDMDEVHLPR3 pHlp, PSSMHANDLE pSSM, PPHY pPhy)
440	{
441	pHlp->pfnSSMPutMem(pSSM, pPhy->au16Regs, sizeof(pPhy->au16Regs));
442	return VINF_SUCCESS;
443	}
444
445	/**
446	* Restore previously saved PHY state.
447	*
448	* @remarks Since PHY is aggregated into E1K it does not currently supports
449	* versioning of its own.
450	*
451	* @returns VBox status code.
452	* @param pHlp Device helper table.
453	* @param pSSM The handle to save the state to.
454	* @param pPhy The pointer to this instance.
455	*/
456	int Phy::loadState(PCPDMDEVHLPR3 pHlp, PSSMHANDLE pSSM, PPHY pPhy)
457	{
458	return pHlp->pfnSSMGetMem(pSSM, pPhy->au16Regs, sizeof(pPhy->au16Regs));
459	}
460
461	#endif /* IN_RING3 */
462
463	/* Register-specific handlers ************************************************/
464
465	/**
466	* Write handler for PHY Control register.
467	*
468	* Handles reset.
469	*
470	* @param index Register index in register array.
471	* @param value The value to store (ignored).
472	*/
473	static void Phy::regWritePCTRL(PPHY pPhy, uint32_t index, uint16_t u16Value, PPDMDEVINS pDevIns)
474	{
475	if (u16Value & PCTRL_RESET)
476	softReset(pPhy, pDevIns);
477	else
478	regWriteDefault(pPhy, index, u16Value, pDevIns);
479	}
480
481	/**
482	* Read handler for PHY Status register.
483	*
484	* Handles Latched-Low Link Status bit.
485	*
486	* @returns Register value
487	*
488	* @param index Register index in register array.
489	*/
490	static uint16_t Phy::regReadPSTATUS(PPHY pPhy, uint32_t index, PPDMDEVINS pDevIns)
491	{
492	RT_NOREF(pPhy, index, pDevIns);
493
494	/* Read latched value */
495	uint16_t u16 = REG(PSTATUS);
496	if (REG(PSSTAT) & PSSTAT_LINK)
497	REG(PSTATUS) \|= PSTATUS_LNKSTAT;
498	else
499	REG(PSTATUS) &= ~PSTATUS_LNKSTAT;
500	return u16;
501	}
502
503	/**
504	* Read handler for 1000BASE-T Status register.
505	*
506	* @returns Register value
507	*
508	* @param index Register index in register array.
509	*/
510	static uint16_t Phy::regReadGSTATUS(PPHY pPhy, uint32_t index, PPDMDEVINS pDevIns)
511	{
512	RT_NOREF(pPhy, index, pDevIns);
513
514	/*
515	* - Link partner is capable of 1000BASE-T half duplex
516	* - Link partner is capable of 1000BASE-T full duplex
517	* - Remote receiver OK
518	* - Local receiver OK
519	* - Local PHY config resolved to SLAVE
520	*/
521	return 0x3C00;
522	}
523
524	#if defined(LOG_ENABLED) \|\| defined(PHY_UNIT_TEST)
525	static const char * Phy::getStateName(uint16_t u16State)
526	{
527	static const char *pcszState[] =
528	{
529	"MDIO_IDLE",
530	"MDIO_ST",
531	"MDIO_OP_ADR",
532	"MDIO_TA_RD",
533	"MDIO_TA_WR",
534	"MDIO_READ",
535	"MDIO_WRITE"
536	};
537
538	return (u16State < RT_ELEMENTS(pcszState)) ? pcszState[u16State] : "<invalid>";
539	}
540	#endif
541
542	bool Phy::readMDIO(PPHY pPhy)
543	{
544	bool fPin = false;
545
546	switch (pPhy->u16State)
547	{
548	case MDIO_TA_RD:
549	Assert(pPhy->u16Cnt == 1);
550	fPin = false;
551	pPhy->u16State = MDIO_READ;
552	pPhy->u16Cnt = 16;
553	break;
554	case MDIO_READ:
555	/* Bits are shifted out in MSB to LSB order */
556	fPin = (pPhy->u16Acc & 0x8000) != 0;
557	pPhy->u16Acc <<= 1;
558	if (--pPhy->u16Cnt == 0)
559	pPhy->u16State = MDIO_IDLE;
560	break;
561	default:
562	PhyLog(("PHY#%d WARNING! MDIO pin read in %s state\n", pPhy->iInstance, Phy::getStateName(pPhy->u16State)));
563	pPhy->u16State = MDIO_IDLE;
564	}
565	return fPin;
566	}
567
568	/** Set the value of MDIO pin. */
569	void Phy::writeMDIO(PPHY pPhy, bool fPin, PPDMDEVINS pDevIns)
570	{
571	switch (pPhy->u16State)
572	{
573	case MDIO_IDLE:
574	if (!fPin)
575	pPhy->u16State = MDIO_ST;
576	break;
577	case MDIO_ST:
578	if (fPin)
579	{
580	pPhy->u16State = MDIO_OP_ADR;
581	pPhy->u16Cnt = 12; /* OP + PHYADR + REGADR */
582	pPhy->u16Acc = 0;
583	}
584	break;
585	case MDIO_OP_ADR:
586	Assert(pPhy->u16Cnt);
587	/* Shift in 'u16Cnt' bits into accumulator */
588	pPhy->u16Acc <<= 1;
589	if (fPin)
590	pPhy->u16Acc \|= 1;
591	if (--pPhy->u16Cnt == 0)
592	{
593	/* Got OP(2) + PHYADR(5) + REGADR(5) */
594	/* Note: A single PHY is supported, ignore PHYADR */
595	switch (pPhy->u16Acc >> 10)
596	{
597	case MDIO_READ_OP:
598	pPhy->u16Acc = readRegister(pPhy, pPhy->u16Acc & 0x1F, pDevIns);
599	pPhy->u16State = MDIO_TA_RD;
600	pPhy->u16Cnt = 1;
601	break;
602	case MDIO_WRITE_OP:
603	pPhy->u16RegAdr = pPhy->u16Acc & 0x1F;
604	pPhy->u16State = MDIO_TA_WR;
605	pPhy->u16Cnt = 2;
606	break;
607	default:
608	PhyLog(("PHY#%d ERROR! Invalid MDIO op: %d\n", pPhy->iInstance, pPhy->u16Acc >> 10));
609	pPhy->u16State = MDIO_IDLE;
610	break;
611	}
612	}
613	break;
614	case MDIO_TA_WR:
615	Assert(pPhy->u16Cnt <= 2);
616	Assert(pPhy->u16Cnt > 0);
617	if (--pPhy->u16Cnt == 0)
618	{
619	pPhy->u16State = MDIO_WRITE;
620	pPhy->u16Cnt = 16;
621	}
622	break;
623	case MDIO_WRITE:
624	Assert(pPhy->u16Cnt);
625	pPhy->u16Acc <<= 1;
626	if (fPin)
627	pPhy->u16Acc \|= 1;
628	if (--pPhy->u16Cnt == 0)
629	{
630	writeRegister(pPhy, pPhy->u16RegAdr, pPhy->u16Acc, pDevIns);
631	pPhy->u16State = MDIO_IDLE;
632	}
633	break;
634	default:
635	PhyLog(("PHY#%d ERROR! MDIO pin write in %s state\n", pPhy->iInstance, Phy::getStateName(pPhy->u16State)));
636	pPhy->u16State = MDIO_IDLE;
637	break;
638	}
639	}
640

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source: vbox/trunk/src/VBox/Devices/Network/DevE1000Phy.cpp@ 102827

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