VirtualBox

source: vbox/trunk/src/VBox/Devices/Network/DevE1000.cpp@ 86405

Last change on this file since 86405 was 85146, checked in by vboxsync, 4 years ago

Dev/E1000,PDM: (bugref:9764) disable UFO, UDP header checks, zero MSS handling.
  • Property svn:eol-style set to native
  • Property svn:keywords set to Author Date Id Revision
File size: 326.0 KB
Line 
1/* $Id: DevE1000.cpp 85146 2020-07-09 10:20:38Z vboxsync $ */
2/** @file
3 * DevE1000 - Intel 82540EM Ethernet Controller Emulation.
4 *
5 * Implemented in accordance with the specification:
6 *
7 * PCI/PCI-X Family of Gigabit Ethernet Controllers Software Developer's Manual
8 * 82540EP/EM, 82541xx, 82544GC/EI, 82545GM/EM, 82546GB/EB, and 82547xx
9 *
10 * 317453-002 Revision 3.5
11 *
12 * @todo IPv6 checksum offloading support
13 * @todo Flexible Filter / Wakeup (optional?)
14 */
15
16/*
17 * Copyright (C) 2007-2020 Oracle Corporation
18 *
19 * This file is part of VirtualBox Open Source Edition (OSE), as
20 * available from http://www.virtualbox.org. This file is free software;
21 * you can redistribute it and/or modify it under the terms of the GNU
22 * General Public License (GPL) as published by the Free Software
23 * Foundation, in version 2 as it comes in the "COPYING" file of the
24 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
25 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
26 */
27
28
29/*********************************************************************************************************************************
30* Header Files *
31*********************************************************************************************************************************/
32#define LOG_GROUP LOG_GROUP_DEV_E1000
33#include <iprt/crc.h>
34#include <iprt/ctype.h>
35#include <iprt/net.h>
36#include <iprt/semaphore.h>
37#include <iprt/string.h>
38#include <iprt/time.h>
39#include <iprt/uuid.h>
40#include <VBox/vmm/pdmdev.h>
41#include <VBox/vmm/pdmnetifs.h>
42#include <VBox/vmm/pdmnetinline.h>
43#include <VBox/param.h>
44#include "VBoxDD.h"
45
46#include "DevEEPROM.h"
47#include "DevE1000Phy.h"
48
49
50/*********************************************************************************************************************************
51* Defined Constants And Macros *
52*********************************************************************************************************************************/
53/** @name E1000 Build Options
54 * @{ */
55/** @def E1K_INIT_RA0
56 * E1K_INIT_RA0 forces E1000 to set the first entry in Receive Address filter
57 * table to MAC address obtained from CFGM. Most guests read MAC address from
58 * EEPROM and write it to RA[0] explicitly, but Mac OS X seems to depend on it
59 * being already set (see @bugref{4657}).
60 */
61#define E1K_INIT_RA0
62/** @def E1K_LSC_ON_RESET
63 * E1K_LSC_ON_RESET causes e1000 to generate Link Status Change
64 * interrupt after hard reset. This makes the E1K_LSC_ON_SLU option unnecessary.
65 * With unplugged cable, LSC is triggerred for 82543GC only.
66 */
67#define E1K_LSC_ON_RESET
68/** @def E1K_LSC_ON_SLU
69 * E1K_LSC_ON_SLU causes E1000 to generate Link Status Change interrupt when
70 * the guest driver brings up the link via STATUS.LU bit. Again the only guest
71 * that requires it is Mac OS X (see @bugref{4657}).
72 */
73//#define E1K_LSC_ON_SLU
74/** @def E1K_INIT_LINKUP_DELAY
75 * E1K_INIT_LINKUP_DELAY prevents the link going up while the driver is still
76 * in init (see @bugref{8624}).
77 */
78#define E1K_INIT_LINKUP_DELAY_US (2000 * 1000)
79/** @def E1K_IMS_INT_DELAY_NS
80 * E1K_IMS_INT_DELAY_NS prevents interrupt storms in Windows guests on enabling
81 * interrupts (see @bugref{8624}).
82 */
83#define E1K_IMS_INT_DELAY_NS 100
84/** @def E1K_TX_DELAY
85 * E1K_TX_DELAY aims to improve guest-host transfer rate for TCP streams by
86 * preventing packets to be sent immediately. It allows to send several
87 * packets in a batch reducing the number of acknowledgments. Note that it
88 * effectively disables R0 TX path, forcing sending in R3.
89 */
90//#define E1K_TX_DELAY 150
91/** @def E1K_USE_TX_TIMERS
92 * E1K_USE_TX_TIMERS aims to reduce the number of generated TX interrupts if a
93 * guest driver set the delays via the Transmit Interrupt Delay Value (TIDV)
94 * register. Enabling it showed no positive effects on existing guests so it
95 * stays disabled. See sections 3.2.7.1 and 3.4.3.1 in "8254x Family of Gigabit
96 * Ethernet Controllers Software Developer’s Manual" for more detailed
97 * explanation.
98 */
99//#define E1K_USE_TX_TIMERS
100/** @def E1K_NO_TAD
101 * E1K_NO_TAD disables one of two timers enabled by E1K_USE_TX_TIMERS, the
102 * Transmit Absolute Delay time. This timer sets the maximum time interval
103 * during which TX interrupts can be postponed (delayed). It has no effect
104 * if E1K_USE_TX_TIMERS is not defined.
105 */
106//#define E1K_NO_TAD
107/** @def E1K_REL_DEBUG
108 * E1K_REL_DEBUG enables debug logging of l1, l2, l3 in release build.
109 */
110//#define E1K_REL_DEBUG
111/** @def E1K_INT_STATS
112 * E1K_INT_STATS enables collection of internal statistics used for
113 * debugging of delayed interrupts, etc.
114 */
115#define E1K_INT_STATS
116/** @def E1K_WITH_MSI
117 * E1K_WITH_MSI enables rudimentary MSI support. Not implemented.
118 */
119//#define E1K_WITH_MSI
120/** @def E1K_WITH_TX_CS
121 * E1K_WITH_TX_CS protects e1kXmitPending with a critical section.
122 */
123#define E1K_WITH_TX_CS
124/** @def E1K_WITH_TXD_CACHE
125 * E1K_WITH_TXD_CACHE causes E1000 to fetch multiple TX descriptors in a
126 * single physical memory read (or two if it wraps around the end of TX
127 * descriptor ring). It is required for proper functioning of bandwidth
128 * resource control as it allows to compute exact sizes of packets prior
129 * to allocating their buffers (see @bugref{5582}).
130 */
131#define E1K_WITH_TXD_CACHE
132/** @def E1K_WITH_RXD_CACHE
133 * E1K_WITH_RXD_CACHE causes E1000 to fetch multiple RX descriptors in a
134 * single physical memory read (or two if it wraps around the end of RX
135 * descriptor ring). Intel's packet driver for DOS needs this option in
136 * order to work properly (see @bugref{6217}).
137 */
138#define E1K_WITH_RXD_CACHE
139/** @def E1K_WITH_PREREG_MMIO
140 * E1K_WITH_PREREG_MMIO enables a new style MMIO registration and is
141 * currently only done for testing the relateted PDM, IOM and PGM code. */
142//#define E1K_WITH_PREREG_MMIO
143/* @} */
144/* End of Options ************************************************************/
145
146#ifdef E1K_WITH_TXD_CACHE
147/**
148 * E1K_TXD_CACHE_SIZE specifies the maximum number of TX descriptors stored
149 * in the state structure. It limits the amount of descriptors loaded in one
150 * batch read. For example, Linux guest may use up to 20 descriptors per
151 * TSE packet. The largest TSE packet seen (Windows guest) was 45 descriptors.
152 */
153# define E1K_TXD_CACHE_SIZE 64u
154#endif /* E1K_WITH_TXD_CACHE */
155
156#ifdef E1K_WITH_RXD_CACHE
157/**
158 * E1K_RXD_CACHE_SIZE specifies the maximum number of RX descriptors stored
159 * in the state structure. It limits the amount of descriptors loaded in one
160 * batch read. For example, XP guest adds 15 RX descriptors at a time.
161 */
162# define E1K_RXD_CACHE_SIZE 16u
163#endif /* E1K_WITH_RXD_CACHE */
164
165
166/* Little helpers ************************************************************/
167#undef htons
168#undef ntohs
169#undef htonl
170#undef ntohl
171#define htons(x) ((((x) & 0xff00) >> 8) | (((x) & 0x00ff) << 8))
172#define ntohs(x) htons(x)
173#define htonl(x) ASMByteSwapU32(x)
174#define ntohl(x) htonl(x)
175
176#ifndef DEBUG
177# ifdef E1K_REL_DEBUG
178# define DEBUG
179# define E1kLog(a) LogRel(a)
180# define E1kLog2(a) LogRel(a)
181# define E1kLog3(a) LogRel(a)
182# define E1kLogX(x, a) LogRel(a)
183//# define E1kLog3(a) do {} while (0)
184# else
185# define E1kLog(a) do {} while (0)
186# define E1kLog2(a) do {} while (0)
187# define E1kLog3(a) do {} while (0)
188# define E1kLogX(x, a) do {} while (0)
189# endif
190#else
191# define E1kLog(a) Log(a)
192# define E1kLog2(a) Log2(a)
193# define E1kLog3(a) Log3(a)
194# define E1kLogX(x, a) LogIt(x, LOG_GROUP, a)
195//# define E1kLog(a) do {} while (0)
196//# define E1kLog2(a) do {} while (0)
197//# define E1kLog3(a) do {} while (0)
198#endif
199
200#if 0
201# define LOG_ENABLED
202# define E1kLogRel(a) LogRel(a)
203# undef Log6
204# define Log6(a) LogRel(a)
205#else
206# define E1kLogRel(a) do { } while (0)
207#endif
208
209//#undef DEBUG
210
211#define E1K_RELOCATE(p, o) *(RTHCUINTPTR *)&p += o
212
213#define E1K_INC_CNT32(cnt) \
214do { \
215 if (cnt < UINT32_MAX) \
216 cnt++; \
217} while (0)
218
219#define E1K_ADD_CNT64(cntLo, cntHi, val) \
220do { \
221 uint64_t u64Cnt = RT_MAKE_U64(cntLo, cntHi); \
222 uint64_t tmp = u64Cnt; \
223 u64Cnt += val; \
224 if (tmp > u64Cnt ) \
225 u64Cnt = UINT64_MAX; \
226 cntLo = (uint32_t)u64Cnt; \
227 cntHi = (uint32_t)(u64Cnt >> 32); \
228} while (0)
229
230#ifdef E1K_INT_STATS
231# define E1K_INC_ISTAT_CNT(cnt) do { ++cnt; } while (0)
232#else /* E1K_INT_STATS */
233# define E1K_INC_ISTAT_CNT(cnt) do { } while (0)
234#endif /* E1K_INT_STATS */
235
236
237/*****************************************************************************/
238
239typedef uint32_t E1KCHIP;
240#define E1K_CHIP_82540EM 0
241#define E1K_CHIP_82543GC 1
242#define E1K_CHIP_82545EM 2
243
244#ifdef IN_RING3
245/** Different E1000 chips. */
246static const struct E1kChips
247{
248 uint16_t uPCIVendorId;
249 uint16_t uPCIDeviceId;
250 uint16_t uPCISubsystemVendorId;
251 uint16_t uPCISubsystemId;
252 const char *pcszName;
253} g_aChips[] =
254{
255 /* Vendor Device SSVendor SubSys Name */
256 { 0x8086,
257 /* Temporary code, as MSI-aware driver dislike 0x100E. How to do that right? */
258# ifdef E1K_WITH_MSI
259 0x105E,
260# else
261 0x100E,
262# endif
263 0x8086, 0x001E, "82540EM" }, /* Intel 82540EM-A in Intel PRO/1000 MT Desktop */
264 { 0x8086, 0x1004, 0x8086, 0x1004, "82543GC" }, /* Intel 82543GC in Intel PRO/1000 T Server */
265 { 0x8086, 0x100F, 0x15AD, 0x0750, "82545EM" } /* Intel 82545EM-A in VMWare Network Adapter */
266};
267#endif /* IN_RING3 */
268
269
270/* The size of register area mapped to I/O space */
271#define E1K_IOPORT_SIZE 0x8
272/* The size of memory-mapped register area */
273#define E1K_MM_SIZE 0x20000
274
275#define E1K_MAX_TX_PKT_SIZE 16288
276#define E1K_MAX_RX_PKT_SIZE 16384
277
278/*****************************************************************************/
279
280/** Gets the specfieid bits from the register. */
281#define GET_BITS(reg, bits) ((reg & reg##_##bits##_MASK) >> reg##_##bits##_SHIFT)
282#define GET_BITS_V(val, reg, bits) ((val & reg##_##bits##_MASK) >> reg##_##bits##_SHIFT)
283#define BITS(reg, bits, bitval) (bitval << reg##_##bits##_SHIFT)
284#define SET_BITS(reg, bits, bitval) do { reg = (reg & ~reg##_##bits##_MASK) | (bitval << reg##_##bits##_SHIFT); } while (0)
285#define SET_BITS_V(val, reg, bits, bitval) do { val = (val & ~reg##_##bits##_MASK) | (bitval << reg##_##bits##_SHIFT); } while (0)
286
287#define CTRL_SLU UINT32_C(0x00000040)
288#define CTRL_MDIO UINT32_C(0x00100000)
289#define CTRL_MDC UINT32_C(0x00200000)
290#define CTRL_MDIO_DIR UINT32_C(0x01000000)
291#define CTRL_MDC_DIR UINT32_C(0x02000000)
292#define CTRL_RESET UINT32_C(0x04000000)
293#define CTRL_VME UINT32_C(0x40000000)
294
295#define STATUS_LU UINT32_C(0x00000002)
296#define STATUS_TXOFF UINT32_C(0x00000010)
297
298#define EECD_EE_WIRES UINT32_C(0x0F)
299#define EECD_EE_REQ UINT32_C(0x40)
300#define EECD_EE_GNT UINT32_C(0x80)
301
302#define EERD_START UINT32_C(0x00000001)
303#define EERD_DONE UINT32_C(0x00000010)
304#define EERD_DATA_MASK UINT32_C(0xFFFF0000)
305#define EERD_DATA_SHIFT 16
306#define EERD_ADDR_MASK UINT32_C(0x0000FF00)
307#define EERD_ADDR_SHIFT 8
308
309#define MDIC_DATA_MASK UINT32_C(0x0000FFFF)
310#define MDIC_DATA_SHIFT 0
311#define MDIC_REG_MASK UINT32_C(0x001F0000)
312#define MDIC_REG_SHIFT 16
313#define MDIC_PHY_MASK UINT32_C(0x03E00000)
314#define MDIC_PHY_SHIFT 21
315#define MDIC_OP_WRITE UINT32_C(0x04000000)
316#define MDIC_OP_READ UINT32_C(0x08000000)
317#define MDIC_READY UINT32_C(0x10000000)
318#define MDIC_INT_EN UINT32_C(0x20000000)
319#define MDIC_ERROR UINT32_C(0x40000000)
320
321#define TCTL_EN UINT32_C(0x00000002)
322#define TCTL_PSP UINT32_C(0x00000008)
323
324#define RCTL_EN UINT32_C(0x00000002)
325#define RCTL_UPE UINT32_C(0x00000008)
326#define RCTL_MPE UINT32_C(0x00000010)
327#define RCTL_LPE UINT32_C(0x00000020)
328#define RCTL_LBM_MASK UINT32_C(0x000000C0)
329#define RCTL_LBM_SHIFT 6
330#define RCTL_RDMTS_MASK UINT32_C(0x00000300)
331#define RCTL_RDMTS_SHIFT 8
332#define RCTL_LBM_TCVR UINT32_C(3) /**< PHY or external SerDes loopback. */
333#define RCTL_MO_MASK UINT32_C(0x00003000)
334#define RCTL_MO_SHIFT 12
335#define RCTL_BAM UINT32_C(0x00008000)
336#define RCTL_BSIZE_MASK UINT32_C(0x00030000)
337#define RCTL_BSIZE_SHIFT 16
338#define RCTL_VFE UINT32_C(0x00040000)
339#define RCTL_CFIEN UINT32_C(0x00080000)
340#define RCTL_CFI UINT32_C(0x00100000)
341#define RCTL_BSEX UINT32_C(0x02000000)
342#define RCTL_SECRC UINT32_C(0x04000000)
343
344#define ICR_TXDW UINT32_C(0x00000001)
345#define ICR_TXQE UINT32_C(0x00000002)
346#define ICR_LSC UINT32_C(0x00000004)
347#define ICR_RXDMT0 UINT32_C(0x00000010)
348#define ICR_RXT0 UINT32_C(0x00000080)
349#define ICR_TXD_LOW UINT32_C(0x00008000)
350#define RDTR_FPD UINT32_C(0x80000000)
351
352#define PBA_st ((PBAST*)(pThis->auRegs + PBA_IDX))
353typedef struct
354{
355 unsigned rxa : 7;
356 unsigned rxa_r : 9;
357 unsigned txa : 16;
358} PBAST;
359AssertCompileSize(PBAST, 4);
360
361#define TXDCTL_WTHRESH_MASK 0x003F0000
362#define TXDCTL_WTHRESH_SHIFT 16
363#define TXDCTL_LWTHRESH_MASK 0xFE000000
364#define TXDCTL_LWTHRESH_SHIFT 25
365
366#define RXCSUM_PCSS_MASK UINT32_C(0x000000FF)
367#define RXCSUM_PCSS_SHIFT 0
368
369/** @name Register access macros
370 * @remarks These ASSUME alocal variable @a pThis of type PE1KSTATE.
371 * @{ */
372#define CTRL pThis->auRegs[CTRL_IDX]
373#define STATUS pThis->auRegs[STATUS_IDX]
374#define EECD pThis->auRegs[EECD_IDX]
375#define EERD pThis->auRegs[EERD_IDX]
376#define CTRL_EXT pThis->auRegs[CTRL_EXT_IDX]
377#define FLA pThis->auRegs[FLA_IDX]
378#define MDIC pThis->auRegs[MDIC_IDX]
379#define FCAL pThis->auRegs[FCAL_IDX]
380#define FCAH pThis->auRegs[FCAH_IDX]
381#define FCT pThis->auRegs[FCT_IDX]
382#define VET pThis->auRegs[VET_IDX]
383#define ICR pThis->auRegs[ICR_IDX]
384#define ITR pThis->auRegs[ITR_IDX]
385#define ICS pThis->auRegs[ICS_IDX]
386#define IMS pThis->auRegs[IMS_IDX]
387#define IMC pThis->auRegs[IMC_IDX]
388#define RCTL pThis->auRegs[RCTL_IDX]
389#define FCTTV pThis->auRegs[FCTTV_IDX]
390#define TXCW pThis->auRegs[TXCW_IDX]
391#define RXCW pThis->auRegs[RXCW_IDX]
392#define TCTL pThis->auRegs[TCTL_IDX]
393#define TIPG pThis->auRegs[TIPG_IDX]
394#define AIFS pThis->auRegs[AIFS_IDX]
395#define LEDCTL pThis->auRegs[LEDCTL_IDX]
396#define PBA pThis->auRegs[PBA_IDX]
397#define FCRTL pThis->auRegs[FCRTL_IDX]
398#define FCRTH pThis->auRegs[FCRTH_IDX]
399#define RDFH pThis->auRegs[RDFH_IDX]
400#define RDFT pThis->auRegs[RDFT_IDX]
401#define RDFHS pThis->auRegs[RDFHS_IDX]
402#define RDFTS pThis->auRegs[RDFTS_IDX]
403#define RDFPC pThis->auRegs[RDFPC_IDX]
404#define RDBAL pThis->auRegs[RDBAL_IDX]
405#define RDBAH pThis->auRegs[RDBAH_IDX]
406#define RDLEN pThis->auRegs[RDLEN_IDX]
407#define RDH pThis->auRegs[RDH_IDX]
408#define RDT pThis->auRegs[RDT_IDX]
409#define RDTR pThis->auRegs[RDTR_IDX]
410#define RXDCTL pThis->auRegs[RXDCTL_IDX]
411#define RADV pThis->auRegs[RADV_IDX]
412#define RSRPD pThis->auRegs[RSRPD_IDX]
413#define TXDMAC pThis->auRegs[TXDMAC_IDX]
414#define TDFH pThis->auRegs[TDFH_IDX]
415#define TDFT pThis->auRegs[TDFT_IDX]
416#define TDFHS pThis->auRegs[TDFHS_IDX]
417#define TDFTS pThis->auRegs[TDFTS_IDX]
418#define TDFPC pThis->auRegs[TDFPC_IDX]
419#define TDBAL pThis->auRegs[TDBAL_IDX]
420#define TDBAH pThis->auRegs[TDBAH_IDX]
421#define TDLEN pThis->auRegs[TDLEN_IDX]
422#define TDH pThis->auRegs[TDH_IDX]
423#define TDT pThis->auRegs[TDT_IDX]
424#define TIDV pThis->auRegs[TIDV_IDX]
425#define TXDCTL pThis->auRegs[TXDCTL_IDX]
426#define TADV pThis->auRegs[TADV_IDX]
427#define TSPMT pThis->auRegs[TSPMT_IDX]
428#define CRCERRS pThis->auRegs[CRCERRS_IDX]
429#define ALGNERRC pThis->auRegs[ALGNERRC_IDX]
430#define SYMERRS pThis->auRegs[SYMERRS_IDX]
431#define RXERRC pThis->auRegs[RXERRC_IDX]
432#define MPC pThis->auRegs[MPC_IDX]
433#define SCC pThis->auRegs[SCC_IDX]
434#define ECOL pThis->auRegs[ECOL_IDX]
435#define MCC pThis->auRegs[MCC_IDX]
436#define LATECOL pThis->auRegs[LATECOL_IDX]
437#define COLC pThis->auRegs[COLC_IDX]
438#define DC pThis->auRegs[DC_IDX]
439#define TNCRS pThis->auRegs[TNCRS_IDX]
440/* #define SEC pThis->auRegs[SEC_IDX] Conflict with sys/time.h */
441#define CEXTERR pThis->auRegs[CEXTERR_IDX]
442#define RLEC pThis->auRegs[RLEC_IDX]
443#define XONRXC pThis->auRegs[XONRXC_IDX]
444#define XONTXC pThis->auRegs[XONTXC_IDX]
445#define XOFFRXC pThis->auRegs[XOFFRXC_IDX]
446#define XOFFTXC pThis->auRegs[XOFFTXC_IDX]
447#define FCRUC pThis->auRegs[FCRUC_IDX]
448#define PRC64 pThis->auRegs[PRC64_IDX]
449#define PRC127 pThis->auRegs[PRC127_IDX]
450#define PRC255 pThis->auRegs[PRC255_IDX]
451#define PRC511 pThis->auRegs[PRC511_IDX]
452#define PRC1023 pThis->auRegs[PRC1023_IDX]
453#define PRC1522 pThis->auRegs[PRC1522_IDX]
454#define GPRC pThis->auRegs[GPRC_IDX]
455#define BPRC pThis->auRegs[BPRC_IDX]
456#define MPRC pThis->auRegs[MPRC_IDX]
457#define GPTC pThis->auRegs[GPTC_IDX]
458#define GORCL pThis->auRegs[GORCL_IDX]
459#define GORCH pThis->auRegs[GORCH_IDX]
460#define GOTCL pThis->auRegs[GOTCL_IDX]
461#define GOTCH pThis->auRegs[GOTCH_IDX]
462#define RNBC pThis->auRegs[RNBC_IDX]
463#define RUC pThis->auRegs[RUC_IDX]
464#define RFC pThis->auRegs[RFC_IDX]
465#define ROC pThis->auRegs[ROC_IDX]
466#define RJC pThis->auRegs[RJC_IDX]
467#define MGTPRC pThis->auRegs[MGTPRC_IDX]
468#define MGTPDC pThis->auRegs[MGTPDC_IDX]
469#define MGTPTC pThis->auRegs[MGTPTC_IDX]
470#define TORL pThis->auRegs[TORL_IDX]
471#define TORH pThis->auRegs[TORH_IDX]
472#define TOTL pThis->auRegs[TOTL_IDX]
473#define TOTH pThis->auRegs[TOTH_IDX]
474#define TPR pThis->auRegs[TPR_IDX]
475#define TPT pThis->auRegs[TPT_IDX]
476#define PTC64 pThis->auRegs[PTC64_IDX]
477#define PTC127 pThis->auRegs[PTC127_IDX]
478#define PTC255 pThis->auRegs[PTC255_IDX]
479#define PTC511 pThis->auRegs[PTC511_IDX]
480#define PTC1023 pThis->auRegs[PTC1023_IDX]
481#define PTC1522 pThis->auRegs[PTC1522_IDX]
482#define MPTC pThis->auRegs[MPTC_IDX]
483#define BPTC pThis->auRegs[BPTC_IDX]
484#define TSCTC pThis->auRegs[TSCTC_IDX]
485#define TSCTFC pThis->auRegs[TSCTFC_IDX]
486#define RXCSUM pThis->auRegs[RXCSUM_IDX]
487#define WUC pThis->auRegs[WUC_IDX]
488#define WUFC pThis->auRegs[WUFC_IDX]
489#define WUS pThis->auRegs[WUS_IDX]
490#define MANC pThis->auRegs[MANC_IDX]
491#define IPAV pThis->auRegs[IPAV_IDX]
492#define WUPL pThis->auRegs[WUPL_IDX]
493/** @} */
494
495/**
496 * Indices of memory-mapped registers in register table.
497 */
498typedef enum
499{
500 CTRL_IDX,
501 STATUS_IDX,
502 EECD_IDX,
503 EERD_IDX,
504 CTRL_EXT_IDX,
505 FLA_IDX,
506 MDIC_IDX,
507 FCAL_IDX,
508 FCAH_IDX,
509 FCT_IDX,
510 VET_IDX,
511 ICR_IDX,
512 ITR_IDX,
513 ICS_IDX,
514 IMS_IDX,
515 IMC_IDX,
516 RCTL_IDX,
517 FCTTV_IDX,
518 TXCW_IDX,
519 RXCW_IDX,
520 TCTL_IDX,
521 TIPG_IDX,
522 AIFS_IDX,
523 LEDCTL_IDX,
524 PBA_IDX,
525 FCRTL_IDX,
526 FCRTH_IDX,
527 RDFH_IDX,
528 RDFT_IDX,
529 RDFHS_IDX,
530 RDFTS_IDX,
531 RDFPC_IDX,
532 RDBAL_IDX,
533 RDBAH_IDX,
534 RDLEN_IDX,
535 RDH_IDX,
536 RDT_IDX,
537 RDTR_IDX,
538 RXDCTL_IDX,
539 RADV_IDX,
540 RSRPD_IDX,
541 TXDMAC_IDX,
542 TDFH_IDX,
543 TDFT_IDX,
544 TDFHS_IDX,
545 TDFTS_IDX,
546 TDFPC_IDX,
547 TDBAL_IDX,
548 TDBAH_IDX,
549 TDLEN_IDX,
550 TDH_IDX,
551 TDT_IDX,
552 TIDV_IDX,
553 TXDCTL_IDX,
554 TADV_IDX,
555 TSPMT_IDX,
556 CRCERRS_IDX,
557 ALGNERRC_IDX,
558 SYMERRS_IDX,
559 RXERRC_IDX,
560 MPC_IDX,
561 SCC_IDX,
562 ECOL_IDX,
563 MCC_IDX,
564 LATECOL_IDX,
565 COLC_IDX,
566 DC_IDX,
567 TNCRS_IDX,
568 SEC_IDX,
569 CEXTERR_IDX,
570 RLEC_IDX,
571 XONRXC_IDX,
572 XONTXC_IDX,
573 XOFFRXC_IDX,
574 XOFFTXC_IDX,
575 FCRUC_IDX,
576 PRC64_IDX,
577 PRC127_IDX,
578 PRC255_IDX,
579 PRC511_IDX,
580 PRC1023_IDX,
581 PRC1522_IDX,
582 GPRC_IDX,
583 BPRC_IDX,
584 MPRC_IDX,
585 GPTC_IDX,
586 GORCL_IDX,
587 GORCH_IDX,
588 GOTCL_IDX,
589 GOTCH_IDX,
590 RNBC_IDX,
591 RUC_IDX,
592 RFC_IDX,
593 ROC_IDX,
594 RJC_IDX,
595 MGTPRC_IDX,
596 MGTPDC_IDX,
597 MGTPTC_IDX,
598 TORL_IDX,
599 TORH_IDX,
600 TOTL_IDX,
601 TOTH_IDX,
602 TPR_IDX,
603 TPT_IDX,
604 PTC64_IDX,
605 PTC127_IDX,
606 PTC255_IDX,
607 PTC511_IDX,
608 PTC1023_IDX,
609 PTC1522_IDX,
610 MPTC_IDX,
611 BPTC_IDX,
612 TSCTC_IDX,
613 TSCTFC_IDX,
614 RXCSUM_IDX,
615 WUC_IDX,
616 WUFC_IDX,
617 WUS_IDX,
618 MANC_IDX,
619 IPAV_IDX,
620 WUPL_IDX,
621 MTA_IDX,
622 RA_IDX,
623 VFTA_IDX,
624 IP4AT_IDX,
625 IP6AT_IDX,
626 WUPM_IDX,
627 FFLT_IDX,
628 FFMT_IDX,
629 FFVT_IDX,
630 PBM_IDX,
631 RA_82542_IDX,
632 MTA_82542_IDX,
633 VFTA_82542_IDX,
634 E1K_NUM_OF_REGS
635} E1kRegIndex;
636
637#define E1K_NUM_OF_32BIT_REGS MTA_IDX
638/** The number of registers with strictly increasing offset. */
639#define E1K_NUM_OF_BINARY_SEARCHABLE (WUPL_IDX + 1)
640
641
642/**
643 * Define E1000-specific EEPROM layout.
644 */
645struct E1kEEPROM
646{
647 public:
648 EEPROM93C46 eeprom;
649
650#ifdef IN_RING3
651 /**
652 * Initialize EEPROM content.
653 *
654 * @param macAddr MAC address of E1000.
655 */
656 void init(RTMAC &macAddr)
657 {
658 eeprom.init();
659 memcpy(eeprom.m_au16Data, macAddr.au16, sizeof(macAddr.au16));
660 eeprom.m_au16Data[0x04] = 0xFFFF;
661 /*
662 * bit 3 - full support for power management
663 * bit 10 - full duplex
664 */
665 eeprom.m_au16Data[0x0A] = 0x4408;
666 eeprom.m_au16Data[0x0B] = 0x001E;
667 eeprom.m_au16Data[0x0C] = 0x8086;
668 eeprom.m_au16Data[0x0D] = 0x100E;
669 eeprom.m_au16Data[0x0E] = 0x8086;
670 eeprom.m_au16Data[0x0F] = 0x3040;
671 eeprom.m_au16Data[0x21] = 0x7061;
672 eeprom.m_au16Data[0x22] = 0x280C;
673 eeprom.m_au16Data[0x23] = 0x00C8;
674 eeprom.m_au16Data[0x24] = 0x00C8;
675 eeprom.m_au16Data[0x2F] = 0x0602;
676 updateChecksum();
677 };
678
679 /**
680 * Compute the checksum as required by E1000 and store it
681 * in the last word.
682 */
683 void updateChecksum()
684 {
685 uint16_t u16Checksum = 0;
686
687 for (int i = 0; i < eeprom.SIZE-1; i++)
688 u16Checksum += eeprom.m_au16Data[i];
689 eeprom.m_au16Data[eeprom.SIZE-1] = 0xBABA - u16Checksum;
690 };
691
692 /**
693 * First 6 bytes of EEPROM contain MAC address.
694 *
695 * @returns MAC address of E1000.
696 */
697 void getMac(PRTMAC pMac)
698 {
699 memcpy(pMac->au16, eeprom.m_au16Data, sizeof(pMac->au16));
700 };
701
702 uint32_t read()
703 {
704 return eeprom.read();
705 }
706
707 void write(uint32_t u32Wires)
708 {
709 eeprom.write(u32Wires);
710 }
711
712 bool readWord(uint32_t u32Addr, uint16_t *pu16Value)
713 {
714 return eeprom.readWord(u32Addr, pu16Value);
715 }
716
717 int load(PCPDMDEVHLPR3 pHlp, PSSMHANDLE pSSM)
718 {
719 return eeprom.load(pHlp, pSSM);
720 }
721
722 void save(PCPDMDEVHLPR3 pHlp, PSSMHANDLE pSSM)
723 {
724 eeprom.save(pHlp, pSSM);
725 }
726#endif /* IN_RING3 */
727};
728
729
730#define E1K_SPEC_VLAN(s) (s & 0xFFF)
731#define E1K_SPEC_CFI(s) (!!((s>>12) & 0x1))
732#define E1K_SPEC_PRI(s) ((s>>13) & 0x7)
733
734struct E1kRxDStatus
735{
736 /** @name Descriptor Status field (3.2.3.1)
737 * @{ */
738 unsigned fDD : 1; /**< Descriptor Done. */
739 unsigned fEOP : 1; /**< End of packet. */
740 unsigned fIXSM : 1; /**< Ignore checksum indication. */
741 unsigned fVP : 1; /**< VLAN, matches VET. */
742 unsigned : 1;
743 unsigned fTCPCS : 1; /**< RCP Checksum calculated on the packet. */
744 unsigned fIPCS : 1; /**< IP Checksum calculated on the packet. */
745 unsigned fPIF : 1; /**< Passed in-exact filter */
746 /** @} */
747 /** @name Descriptor Errors field (3.2.3.2)
748 * (Only valid when fEOP and fDD are set.)
749 * @{ */
750 unsigned fCE : 1; /**< CRC or alignment error. */
751 unsigned : 4; /**< Reserved, varies with different models... */
752 unsigned fTCPE : 1; /**< TCP/UDP checksum error. */
753 unsigned fIPE : 1; /**< IP Checksum error. */
754 unsigned fRXE : 1; /**< RX Data error. */
755 /** @} */
756 /** @name Descriptor Special field (3.2.3.3)
757 * @{ */
758 unsigned u16Special : 16; /**< VLAN: Id, Canonical form, Priority. */
759 /** @} */
760};
761typedef struct E1kRxDStatus E1KRXDST;
762
763struct E1kRxDesc_st
764{
765 uint64_t u64BufAddr; /**< Address of data buffer */
766 uint16_t u16Length; /**< Length of data in buffer */
767 uint16_t u16Checksum; /**< Packet checksum */
768 E1KRXDST status;
769};
770typedef struct E1kRxDesc_st E1KRXDESC;
771AssertCompileSize(E1KRXDESC, 16);
772
773#define E1K_DTYP_LEGACY -1
774#define E1K_DTYP_CONTEXT 0
775#define E1K_DTYP_DATA 1
776
777struct E1kTDLegacy
778{
779 uint64_t u64BufAddr; /**< Address of data buffer */
780 struct TDLCmd_st
781 {
782 unsigned u16Length : 16;
783 unsigned u8CSO : 8;
784 /* CMD field : 8 */
785 unsigned fEOP : 1;
786 unsigned fIFCS : 1;
787 unsigned fIC : 1;
788 unsigned fRS : 1;
789 unsigned fRPS : 1;
790 unsigned fDEXT : 1;
791 unsigned fVLE : 1;
792 unsigned fIDE : 1;
793 } cmd;
794 struct TDLDw3_st
795 {
796 /* STA field */
797 unsigned fDD : 1;
798 unsigned fEC : 1;
799 unsigned fLC : 1;
800 unsigned fTURSV : 1;
801 /* RSV field */
802 unsigned u4RSV : 4;
803 /* CSS field */
804 unsigned u8CSS : 8;
805 /* Special field*/
806 unsigned u16Special: 16;
807 } dw3;
808};
809
810/**
811 * TCP/IP Context Transmit Descriptor, section 3.3.6.
812 */
813struct E1kTDContext
814{
815 struct CheckSum_st
816 {
817 /** TSE: Header start. !TSE: Checksum start. */
818 unsigned u8CSS : 8;
819 /** Checksum offset - where to store it. */
820 unsigned u8CSO : 8;
821 /** Checksum ending (inclusive) offset, 0 = end of packet. */
822 unsigned u16CSE : 16;
823 } ip;
824 struct CheckSum_st tu;
825 struct TDCDw2_st
826 {
827 /** TSE: The total number of payload bytes for this context. Sans header. */
828 unsigned u20PAYLEN : 20;
829 /** The descriptor type - E1K_DTYP_CONTEXT (0). */
830 unsigned u4DTYP : 4;
831 /** TUCMD field, 8 bits
832 * @{ */
833 /** TSE: TCP (set) or UDP (clear). */
834 unsigned fTCP : 1;
835 /** TSE: IPv4 (set) or IPv6 (clear) - for finding the payload length field in
836 * the IP header. Does not affect the checksumming.
837 * @remarks 82544GC/EI interprets a cleared field differently. */
838 unsigned fIP : 1;
839 /** TSE: TCP segmentation enable. When clear the context describes */
840 unsigned fTSE : 1;
841 /** Report status (only applies to dw3.fDD for here). */
842 unsigned fRS : 1;
843 /** Reserved, MBZ. */
844 unsigned fRSV1 : 1;
845 /** Descriptor extension, must be set for this descriptor type. */
846 unsigned fDEXT : 1;
847 /** Reserved, MBZ. */
848 unsigned fRSV2 : 1;
849 /** Interrupt delay enable. */
850 unsigned fIDE : 1;
851 /** @} */
852 } dw2;
853 struct TDCDw3_st
854 {
855 /** Descriptor Done. */
856 unsigned fDD : 1;
857 /** Reserved, MBZ. */
858 unsigned u7RSV : 7;
859 /** TSO: The header (prototype) length (Ethernet[, VLAN tag], IP, TCP/UDP. */
860 unsigned u8HDRLEN : 8;
861 /** TSO: Maximum segment size. */
862 unsigned u16MSS : 16;
863 } dw3;
864};
865typedef struct E1kTDContext E1KTXCTX;
866
867/**
868 * TCP/IP Data Transmit Descriptor, section 3.3.7.
869 */
870struct E1kTDData
871{
872 uint64_t u64BufAddr; /**< Address of data buffer */
873 struct TDDCmd_st
874 {
875 /** The total length of data pointed to by this descriptor. */
876 unsigned u20DTALEN : 20;
877 /** The descriptor type - E1K_DTYP_DATA (1). */
878 unsigned u4DTYP : 4;
879 /** @name DCMD field, 8 bits (3.3.7.1).
880 * @{ */
881 /** End of packet. Note TSCTFC update. */
882 unsigned fEOP : 1;
883 /** Insert Ethernet FCS/CRC (requires fEOP to be set). */
884 unsigned fIFCS : 1;
885 /** Use the TSE context when set and the normal when clear. */
886 unsigned fTSE : 1;
887 /** Report status (dw3.STA). */
888 unsigned fRS : 1;
889 /** Reserved. 82544GC/EI defines this report packet set (RPS). */
890 unsigned fRPS : 1;
891 /** Descriptor extension, must be set for this descriptor type. */
892 unsigned fDEXT : 1;
893 /** VLAN enable, requires CTRL.VME, auto enables FCS/CRC.
894 * Insert dw3.SPECIAL after ethernet header. */
895 unsigned fVLE : 1;
896 /** Interrupt delay enable. */
897 unsigned fIDE : 1;
898 /** @} */
899 } cmd;
900 struct TDDDw3_st
901 {
902 /** @name STA field (3.3.7.2)
903 * @{ */
904 unsigned fDD : 1; /**< Descriptor done. */
905 unsigned fEC : 1; /**< Excess collision. */
906 unsigned fLC : 1; /**< Late collision. */
907 /** Reserved, except for the usual oddball (82544GC/EI) where it's called TU. */
908 unsigned fTURSV : 1;
909 /** @} */
910 unsigned u4RSV : 4; /**< Reserved field, MBZ. */
911 /** @name POPTS (Packet Option) field (3.3.7.3)
912 * @{ */
913 unsigned fIXSM : 1; /**< Insert IP checksum. */
914 unsigned fTXSM : 1; /**< Insert TCP/UDP checksum. */
915 unsigned u6RSV : 6; /**< Reserved, MBZ. */
916 /** @} */
917 /** @name SPECIAL field - VLAN tag to be inserted after ethernet header.
918 * Requires fEOP, fVLE and CTRL.VME to be set.
919 * @{ */
920 unsigned u16Special: 16; /**< VLAN: Id, Canonical form, Priority. */
921 /** @} */
922 } dw3;
923};
924typedef struct E1kTDData E1KTXDAT;
925
926union E1kTxDesc
927{
928 struct E1kTDLegacy legacy;
929 struct E1kTDContext context;
930 struct E1kTDData data;
931};
932typedef union E1kTxDesc E1KTXDESC;
933AssertCompileSize(E1KTXDESC, 16);
934
935#define RA_CTL_AS 0x0003
936#define RA_CTL_AV 0x8000
937
938union E1kRecAddr
939{
940 uint32_t au32[32];
941 struct RAArray
942 {
943 uint8_t addr[6];
944 uint16_t ctl;
945 } array[16];
946};
947typedef struct E1kRecAddr::RAArray E1KRAELEM;
948typedef union E1kRecAddr E1KRA;
949AssertCompileSize(E1KRA, 8*16);
950
951#define E1K_IP_RF UINT16_C(0x8000) /**< reserved fragment flag */
952#define E1K_IP_DF UINT16_C(0x4000) /**< dont fragment flag */
953#define E1K_IP_MF UINT16_C(0x2000) /**< more fragments flag */
954#define E1K_IP_OFFMASK UINT16_C(0x1fff) /**< mask for fragmenting bits */
955
956/** @todo use+extend RTNETIPV4 */
957struct E1kIpHeader
958{
959 /* type of service / version / header length */
960 uint16_t tos_ver_hl;
961 /* total length */
962 uint16_t total_len;
963 /* identification */
964 uint16_t ident;
965 /* fragment offset field */
966 uint16_t offset;
967 /* time to live / protocol*/
968 uint16_t ttl_proto;
969 /* checksum */
970 uint16_t chksum;
971 /* source IP address */
972 uint32_t src;
973 /* destination IP address */
974 uint32_t dest;
975};
976AssertCompileSize(struct E1kIpHeader, 20);
977
978#define E1K_TCP_FIN UINT16_C(0x01)
979#define E1K_TCP_SYN UINT16_C(0x02)
980#define E1K_TCP_RST UINT16_C(0x04)
981#define E1K_TCP_PSH UINT16_C(0x08)
982#define E1K_TCP_ACK UINT16_C(0x10)
983#define E1K_TCP_URG UINT16_C(0x20)
984#define E1K_TCP_ECE UINT16_C(0x40)
985#define E1K_TCP_CWR UINT16_C(0x80)
986#define E1K_TCP_FLAGS UINT16_C(0x3f)
987
988/** @todo use+extend RTNETTCP */
989struct E1kTcpHeader
990{
991 uint16_t src;
992 uint16_t dest;
993 uint32_t seqno;
994 uint32_t ackno;
995 uint16_t hdrlen_flags;
996 uint16_t wnd;
997 uint16_t chksum;
998 uint16_t urgp;
999};
1000AssertCompileSize(struct E1kTcpHeader, 20);
1001
1002
1003#ifdef E1K_WITH_TXD_CACHE
1004/** The current Saved state version. */
1005# define E1K_SAVEDSTATE_VERSION 4
1006/** Saved state version for VirtualBox 4.2 with VLAN tag fields. */
1007# define E1K_SAVEDSTATE_VERSION_VBOX_42_VTAG 3
1008#else /* !E1K_WITH_TXD_CACHE */
1009/** The current Saved state version. */
1010# define E1K_SAVEDSTATE_VERSION 3
1011#endif /* !E1K_WITH_TXD_CACHE */
1012/** Saved state version for VirtualBox 4.1 and earlier.
1013 * These did not include VLAN tag fields. */
1014#define E1K_SAVEDSTATE_VERSION_VBOX_41 2
1015/** Saved state version for VirtualBox 3.0 and earlier.
1016 * This did not include the configuration part nor the E1kEEPROM. */
1017#define E1K_SAVEDSTATE_VERSION_VBOX_30 1
1018
1019/**
1020 * E1000 shared device state.
1021 *
1022 * This is shared between ring-0 and ring-3.
1023 */
1024typedef struct E1KSTATE
1025{
1026 char szPrf[8]; /**< Log prefix, e.g. E1000#1. */
1027
1028 /** Handle to PCI region \#0, the MMIO region. */
1029 IOMIOPORTHANDLE hMmioRegion;
1030 /** Handle to PCI region \#2, the I/O ports. */
1031 IOMIOPORTHANDLE hIoPorts;
1032
1033 /** Receive Interrupt Delay Timer. */
1034 TMTIMERHANDLE hRIDTimer;
1035 /** Receive Absolute Delay Timer. */
1036 TMTIMERHANDLE hRADTimer;
1037 /** Transmit Interrupt Delay Timer. */
1038 TMTIMERHANDLE hTIDTimer;
1039 /** Transmit Absolute Delay Timer. */
1040 TMTIMERHANDLE hTADTimer;
1041 /** Transmit Delay Timer. */
1042 TMTIMERHANDLE hTXDTimer;
1043 /** Late Interrupt Timer. */
1044 TMTIMERHANDLE hIntTimer;
1045 /** Link Up(/Restore) Timer. */
1046 TMTIMERHANDLE hLUTimer;
1047
1048 /** Transmit task. */
1049 PDMTASKHANDLE hTxTask;
1050
1051 /** Critical section - what is it protecting? */
1052 PDMCRITSECT cs;
1053 /** RX Critical section. */
1054 PDMCRITSECT csRx;
1055#ifdef E1K_WITH_TX_CS
1056 /** TX Critical section. */
1057 PDMCRITSECT csTx;
1058#endif /* E1K_WITH_TX_CS */
1059 /** MAC address obtained from the configuration. */
1060 RTMAC macConfigured;
1061 uint16_t u16Padding0;
1062 /** EMT: Last time the interrupt was acknowledged. */
1063 uint64_t u64AckedAt;
1064 /** All: Used for eliminating spurious interrupts. */
1065 bool fIntRaised;
1066 /** EMT: false if the cable is disconnected by the GUI. */
1067 bool fCableConnected;
1068 /** EMT: Compute Ethernet CRC for RX packets. */
1069 bool fEthernetCRC;
1070 /** All: throttle interrupts. */
1071 bool fItrEnabled;
1072 /** All: throttle RX interrupts. */
1073 bool fItrRxEnabled;
1074 /** All: Delay TX interrupts using TIDV/TADV. */
1075 bool fTidEnabled;
1076 bool afPadding[2];
1077 /** Link up delay (in milliseconds). */
1078 uint32_t cMsLinkUpDelay;
1079
1080 /** All: Device register storage. */
1081 uint32_t auRegs[E1K_NUM_OF_32BIT_REGS];
1082 /** TX/RX: Status LED. */
1083 PDMLED led;
1084 /** TX/RX: Number of packet being sent/received to show in debug log. */
1085 uint32_t u32PktNo;
1086
1087 /** EMT: Offset of the register to be read via IO. */
1088 uint32_t uSelectedReg;
1089 /** EMT: Multicast Table Array. */
1090 uint32_t auMTA[128];
1091 /** EMT: Receive Address registers. */
1092 E1KRA aRecAddr;
1093 /** EMT: VLAN filter table array. */
1094 uint32_t auVFTA[128];
1095 /** EMT: Receive buffer size. */
1096 uint16_t u16RxBSize;
1097 /** EMT: Locked state -- no state alteration possible. */
1098 bool fLocked;
1099 /** EMT: */
1100 bool fDelayInts;
1101 /** All: */
1102 bool fIntMaskUsed;
1103
1104 /** N/A: */
1105 bool volatile fMaybeOutOfSpace;
1106 /** EMT: Gets signalled when more RX descriptors become available. */
1107 SUPSEMEVENT hEventMoreRxDescAvail;
1108#ifdef E1K_WITH_RXD_CACHE
1109 /** RX: Fetched RX descriptors. */
1110 E1KRXDESC aRxDescriptors[E1K_RXD_CACHE_SIZE];
1111 //uint64_t aRxDescAddr[E1K_RXD_CACHE_SIZE];
1112 /** RX: Actual number of fetched RX descriptors. */
1113 uint32_t nRxDFetched;
1114 /** RX: Index in cache of RX descriptor being processed. */
1115 uint32_t iRxDCurrent;
1116#endif /* E1K_WITH_RXD_CACHE */
1117
1118 /** TX: Context used for TCP segmentation packets. */
1119 E1KTXCTX contextTSE;
1120 /** TX: Context used for ordinary packets. */
1121 E1KTXCTX contextNormal;
1122#ifdef E1K_WITH_TXD_CACHE
1123 /** TX: Fetched TX descriptors. */
1124 E1KTXDESC aTxDescriptors[E1K_TXD_CACHE_SIZE];
1125 /** TX: Actual number of fetched TX descriptors. */
1126 uint8_t nTxDFetched;
1127 /** TX: Index in cache of TX descriptor being processed. */
1128 uint8_t iTxDCurrent;
1129 /** TX: Will this frame be sent as GSO. */
1130 bool fGSO;
1131 /** Alignment padding. */
1132 bool fReserved;
1133 /** TX: Number of bytes in next packet. */
1134 uint32_t cbTxAlloc;
1135
1136#endif /* E1K_WITH_TXD_CACHE */
1137 /** GSO context. u8Type is set to PDMNETWORKGSOTYPE_INVALID when not
1138 * applicable to the current TSE mode. */
1139 PDMNETWORKGSO GsoCtx;
1140 /** Scratch space for holding the loopback / fallback scatter / gather
1141 * descriptor. */
1142 union
1143 {
1144 PDMSCATTERGATHER Sg;
1145 uint8_t padding[8 * sizeof(RTUINTPTR)];
1146 } uTxFallback;
1147 /** TX: Transmit packet buffer use for TSE fallback and loopback. */
1148 uint8_t aTxPacketFallback[E1K_MAX_TX_PKT_SIZE];
1149 /** TX: Number of bytes assembled in TX packet buffer. */
1150 uint16_t u16TxPktLen;
1151 /** TX: False will force segmentation in e1000 instead of sending frames as GSO. */
1152 bool fGSOEnabled;
1153 /** TX: IP checksum has to be inserted if true. */
1154 bool fIPcsum;
1155 /** TX: TCP/UDP checksum has to be inserted if true. */
1156 bool fTCPcsum;
1157 /** TX: VLAN tag has to be inserted if true. */
1158 bool fVTag;
1159 /** TX: TCI part of VLAN tag to be inserted. */
1160 uint16_t u16VTagTCI;
1161 /** TX TSE fallback: Number of payload bytes remaining in TSE context. */
1162 uint32_t u32PayRemain;
1163 /** TX TSE fallback: Number of header bytes remaining in TSE context. */
1164 uint16_t u16HdrRemain;
1165 /** TX TSE fallback: Flags from template header. */
1166 uint16_t u16SavedFlags;
1167 /** TX TSE fallback: Partial checksum from template header. */
1168 uint32_t u32SavedCsum;
1169 /** ?: Emulated controller type. */
1170 E1KCHIP eChip;
1171
1172 /** EMT: Physical interface emulation. */
1173 PHY phy;
1174
1175#if 0
1176 /** Alignment padding. */
1177 uint8_t Alignment[HC_ARCH_BITS == 64 ? 8 : 4];
1178#endif
1179
1180 STAMCOUNTER StatReceiveBytes;
1181 STAMCOUNTER StatTransmitBytes;
1182#if defined(VBOX_WITH_STATISTICS)
1183 STAMPROFILEADV StatMMIOReadRZ;
1184 STAMPROFILEADV StatMMIOReadR3;
1185 STAMPROFILEADV StatMMIOWriteRZ;
1186 STAMPROFILEADV StatMMIOWriteR3;
1187 STAMPROFILEADV StatEEPROMRead;
1188 STAMPROFILEADV StatEEPROMWrite;
1189 STAMPROFILEADV StatIOReadRZ;
1190 STAMPROFILEADV StatIOReadR3;
1191 STAMPROFILEADV StatIOWriteRZ;
1192 STAMPROFILEADV StatIOWriteR3;
1193 STAMPROFILEADV StatLateIntTimer;
1194 STAMCOUNTER StatLateInts;
1195 STAMCOUNTER StatIntsRaised;
1196 STAMCOUNTER StatIntsPrevented;
1197 STAMPROFILEADV StatReceive;
1198 STAMPROFILEADV StatReceiveCRC;
1199 STAMPROFILEADV StatReceiveFilter;
1200 STAMPROFILEADV StatReceiveStore;
1201 STAMPROFILEADV StatTransmitRZ;
1202 STAMPROFILEADV StatTransmitR3;
1203 STAMPROFILE StatTransmitSendRZ;
1204 STAMPROFILE StatTransmitSendR3;
1205 STAMPROFILE StatRxOverflow;
1206 STAMCOUNTER StatRxOverflowWakeupRZ;
1207 STAMCOUNTER StatRxOverflowWakeupR3;
1208 STAMCOUNTER StatTxDescCtxNormal;
1209 STAMCOUNTER StatTxDescCtxTSE;
1210 STAMCOUNTER StatTxDescLegacy;
1211 STAMCOUNTER StatTxDescData;
1212 STAMCOUNTER StatTxDescTSEData;
1213 STAMCOUNTER StatTxPathFallback;
1214 STAMCOUNTER StatTxPathGSO;
1215 STAMCOUNTER StatTxPathRegular;
1216 STAMCOUNTER StatPHYAccesses;
1217 STAMCOUNTER aStatRegWrites[E1K_NUM_OF_REGS];
1218 STAMCOUNTER aStatRegReads[E1K_NUM_OF_REGS];
1219#endif /* VBOX_WITH_STATISTICS */
1220
1221#ifdef E1K_INT_STATS
1222 /* Internal stats */
1223 uint64_t u64ArmedAt;
1224 uint64_t uStatMaxTxDelay;
1225 uint32_t uStatInt;
1226 uint32_t uStatIntTry;
1227 uint32_t uStatIntLower;
1228 uint32_t uStatNoIntICR;
1229 int32_t iStatIntLost;
1230 int32_t iStatIntLostOne;
1231 uint32_t uStatIntIMS;
1232 uint32_t uStatIntSkip;
1233 uint32_t uStatIntLate;
1234 uint32_t uStatIntMasked;
1235 uint32_t uStatIntEarly;
1236 uint32_t uStatIntRx;
1237 uint32_t uStatIntTx;
1238 uint32_t uStatIntICS;
1239 uint32_t uStatIntRDTR;
1240 uint32_t uStatIntRXDMT0;
1241 uint32_t uStatIntTXQE;
1242 uint32_t uStatTxNoRS;
1243 uint32_t uStatTxIDE;
1244 uint32_t uStatTxDelayed;
1245 uint32_t uStatTxDelayExp;
1246 uint32_t uStatTAD;
1247 uint32_t uStatTID;
1248 uint32_t uStatRAD;
1249 uint32_t uStatRID;
1250 uint32_t uStatRxFrm;
1251 uint32_t uStatTxFrm;
1252 uint32_t uStatDescCtx;
1253 uint32_t uStatDescDat;
1254 uint32_t uStatDescLeg;
1255 uint32_t uStatTx1514;
1256 uint32_t uStatTx2962;
1257 uint32_t uStatTx4410;
1258 uint32_t uStatTx5858;
1259 uint32_t uStatTx7306;
1260 uint32_t uStatTx8754;
1261 uint32_t uStatTx16384;
1262 uint32_t uStatTx32768;
1263 uint32_t uStatTxLarge;
1264 uint32_t uStatAlign;
1265#endif /* E1K_INT_STATS */
1266} E1KSTATE;
1267/** Pointer to the E1000 device state. */
1268typedef E1KSTATE *PE1KSTATE;
1269
1270/**
1271 * E1000 ring-3 device state
1272 *
1273 * @implements PDMINETWORKDOWN
1274 * @implements PDMINETWORKCONFIG
1275 * @implements PDMILEDPORTS
1276 */
1277typedef struct E1KSTATER3
1278{
1279 PDMIBASE IBase;
1280 PDMINETWORKDOWN INetworkDown;
1281 PDMINETWORKCONFIG INetworkConfig;
1282 /** LED interface */
1283 PDMILEDPORTS ILeds;
1284 /** Attached network driver. */
1285 R3PTRTYPE(PPDMIBASE) pDrvBase;
1286 R3PTRTYPE(PPDMILEDCONNECTORS) pLedsConnector;
1287
1288 /** Pointer to the shared state. */
1289 R3PTRTYPE(PE1KSTATE) pShared;
1290
1291 /** Device instance. */
1292 PPDMDEVINSR3 pDevInsR3;
1293 /** Attached network driver. */
1294 PPDMINETWORKUPR3 pDrvR3;
1295 /** The scatter / gather buffer used for the current outgoing packet. */
1296 R3PTRTYPE(PPDMSCATTERGATHER) pTxSgR3;
1297
1298 /** EMT: EEPROM emulation */
1299 E1kEEPROM eeprom;
1300} E1KSTATER3;
1301/** Pointer to the E1000 ring-3 device state. */
1302typedef E1KSTATER3 *PE1KSTATER3;
1303
1304
1305/**
1306 * E1000 ring-0 device state
1307 */
1308typedef struct E1KSTATER0
1309{
1310 /** Device instance. */
1311 PPDMDEVINSR0 pDevInsR0;
1312 /** Attached network driver. */
1313 PPDMINETWORKUPR0 pDrvR0;
1314 /** The scatter / gather buffer used for the current outgoing packet - R0. */
1315 R0PTRTYPE(PPDMSCATTERGATHER) pTxSgR0;
1316} E1KSTATER0;
1317/** Pointer to the E1000 ring-0 device state. */
1318typedef E1KSTATER0 *PE1KSTATER0;
1319
1320
1321/**
1322 * E1000 raw-mode device state
1323 */
1324typedef struct E1KSTATERC
1325{
1326 /** Device instance. */
1327 PPDMDEVINSRC pDevInsRC;
1328 /** Attached network driver. */
1329 PPDMINETWORKUPRC pDrvRC;
1330 /** The scatter / gather buffer used for the current outgoing packet. */
1331 RCPTRTYPE(PPDMSCATTERGATHER) pTxSgRC;
1332} E1KSTATERC;
1333/** Pointer to the E1000 raw-mode device state. */
1334typedef E1KSTATERC *PE1KSTATERC;
1335
1336
1337/** @def PE1KSTATECC
1338 * Pointer to the instance data for the current context. */
1339#ifdef IN_RING3
1340typedef E1KSTATER3 E1KSTATECC;
1341typedef PE1KSTATER3 PE1KSTATECC;
1342#elif defined(IN_RING0)
1343typedef E1KSTATER0 E1KSTATECC;
1344typedef PE1KSTATER0 PE1KSTATECC;
1345#elif defined(IN_RC)
1346typedef E1KSTATERC E1KSTATECC;
1347typedef PE1KSTATERC PE1KSTATECC;
1348#else
1349# error "Not IN_RING3, IN_RING0 or IN_RC"
1350#endif
1351
1352
1353#ifndef VBOX_DEVICE_STRUCT_TESTCASE
1354
1355/* Forward declarations ******************************************************/
1356static int e1kXmitPending(PPDMDEVINS pDevIns, PE1KSTATE pThis, bool fOnWorkerThread);
1357
1358/**
1359 * E1000 register read handler.
1360 */
1361typedef int (FNE1KREGREAD)(PPDMDEVINS pDevIns, PE1KSTATE pThis, uint32_t offset, uint32_t index, uint32_t *pu32Value);
1362/**
1363 * E1000 register write handler.
1364 */
1365typedef int (FNE1KREGWRITE)(PPDMDEVINS pDevIns, PE1KSTATE pThis, uint32_t offset, uint32_t index, uint32_t u32Value);
1366
1367static FNE1KREGREAD e1kRegReadUnimplemented;
1368static FNE1KREGWRITE e1kRegWriteUnimplemented;
1369static FNE1KREGREAD e1kRegReadAutoClear;
1370static FNE1KREGREAD e1kRegReadDefault;
1371static FNE1KREGWRITE e1kRegWriteDefault;
1372#if 0 /* unused */
1373static FNE1KREGREAD e1kRegReadCTRL;
1374#endif
1375static FNE1KREGWRITE e1kRegWriteCTRL;
1376static FNE1KREGREAD e1kRegReadEECD;
1377static FNE1KREGWRITE e1kRegWriteEECD;
1378static FNE1KREGWRITE e1kRegWriteEERD;
1379static FNE1KREGWRITE e1kRegWriteMDIC;
1380static FNE1KREGREAD e1kRegReadICR;
1381static FNE1KREGWRITE e1kRegWriteICR;
1382static FNE1KREGWRITE e1kRegWriteICS;
1383static FNE1KREGWRITE e1kRegWriteIMS;
1384static FNE1KREGWRITE e1kRegWriteIMC;
1385static FNE1KREGWRITE e1kRegWriteRCTL;
1386static FNE1KREGWRITE e1kRegWritePBA;
1387static FNE1KREGWRITE e1kRegWriteRDT;
1388static FNE1KREGWRITE e1kRegWriteRDTR;
1389static FNE1KREGWRITE e1kRegWriteTDT;
1390static FNE1KREGREAD e1kRegReadMTA;
1391static FNE1KREGWRITE e1kRegWriteMTA;
1392static FNE1KREGREAD e1kRegReadRA;
1393static FNE1KREGWRITE e1kRegWriteRA;
1394static FNE1KREGREAD e1kRegReadVFTA;
1395static FNE1KREGWRITE e1kRegWriteVFTA;
1396
1397/**
1398 * Register map table.
1399 *
1400 * Override pfnRead and pfnWrite to get register-specific behavior.
1401 */
1402static const struct E1kRegMap_st
1403{
1404 /** Register offset in the register space. */
1405 uint32_t offset;
1406 /** Size in bytes. Registers of size > 4 are in fact tables. */
1407 uint32_t size;
1408 /** Readable bits. */
1409 uint32_t readable;
1410 /** Writable bits. */
1411 uint32_t writable;
1412 /** Read callback. */
1413 FNE1KREGREAD *pfnRead;
1414 /** Write callback. */
1415 FNE1KREGWRITE *pfnWrite;
1416 /** Abbreviated name. */
1417 const char *abbrev;
1418 /** Full name. */
1419 const char *name;
1420} g_aE1kRegMap[E1K_NUM_OF_REGS] =
1421{
1422 /* offset size read mask write mask read callback write callback abbrev full name */
1423 /*------- ------- ---------- ---------- ----------------------- ------------------------ ---------- ------------------------------*/
1424 { 0x00000, 0x00004, 0xDBF31BE9, 0xDBF31BE9, e1kRegReadDefault , e1kRegWriteCTRL , "CTRL" , "Device Control" },
1425 { 0x00008, 0x00004, 0x0000FDFF, 0x00000000, e1kRegReadDefault , e1kRegWriteUnimplemented, "STATUS" , "Device Status" },
1426 { 0x00010, 0x00004, 0x000027F0, 0x00000070, e1kRegReadEECD , e1kRegWriteEECD , "EECD" , "EEPROM/Flash Control/Data" },
1427 { 0x00014, 0x00004, 0xFFFFFF10, 0xFFFFFF00, e1kRegReadDefault , e1kRegWriteEERD , "EERD" , "EEPROM Read" },
1428 { 0x00018, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "CTRL_EXT", "Extended Device Control" },
1429 { 0x0001c, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "FLA" , "Flash Access (N/A)" },
1430 { 0x00020, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadDefault , e1kRegWriteMDIC , "MDIC" , "MDI Control" },
1431 { 0x00028, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "FCAL" , "Flow Control Address Low" },
1432 { 0x0002c, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "FCAH" , "Flow Control Address High" },
1433 { 0x00030, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "FCT" , "Flow Control Type" },
1434 { 0x00038, 0x00004, 0x0000FFFF, 0x0000FFFF, e1kRegReadDefault , e1kRegWriteDefault , "VET" , "VLAN EtherType" },
1435 { 0x000c0, 0x00004, 0x0001F6DF, 0x0001F6DF, e1kRegReadICR , e1kRegWriteICR , "ICR" , "Interrupt Cause Read" },
1436 { 0x000c4, 0x00004, 0x0000FFFF, 0x0000FFFF, e1kRegReadDefault , e1kRegWriteDefault , "ITR" , "Interrupt Throttling" },
1437 { 0x000c8, 0x00004, 0x00000000, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteICS , "ICS" , "Interrupt Cause Set" },
1438 { 0x000d0, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadDefault , e1kRegWriteIMS , "IMS" , "Interrupt Mask Set/Read" },
1439 { 0x000d8, 0x00004, 0x00000000, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteIMC , "IMC" , "Interrupt Mask Clear" },
1440 { 0x00100, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadDefault , e1kRegWriteRCTL , "RCTL" , "Receive Control" },
1441 { 0x00170, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "FCTTV" , "Flow Control Transmit Timer Value" },
1442 { 0x00178, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "TXCW" , "Transmit Configuration Word (N/A)" },
1443 { 0x00180, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "RXCW" , "Receive Configuration Word (N/A)" },
1444 { 0x00400, 0x00004, 0x017FFFFA, 0x017FFFFA, e1kRegReadDefault , e1kRegWriteDefault , "TCTL" , "Transmit Control" },
1445 { 0x00410, 0x00004, 0x3FFFFFFF, 0x3FFFFFFF, e1kRegReadDefault , e1kRegWriteDefault , "TIPG" , "Transmit IPG" },
1446 { 0x00458, 0x00004, 0x0000FFFF, 0x0000FFFF, e1kRegReadDefault , e1kRegWriteDefault , "AIFS" , "Adaptive IFS Throttle - AIT" },
1447 { 0x00e00, 0x00004, 0xCFCFCFCF, 0xCFCFCFCF, e1kRegReadDefault , e1kRegWriteDefault , "LEDCTL" , "LED Control" },
1448 { 0x01000, 0x00004, 0xFFFF007F, 0x0000007F, e1kRegReadDefault , e1kRegWritePBA , "PBA" , "Packet Buffer Allocation" },
1449 { 0x02160, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "FCRTL" , "Flow Control Receive Threshold Low" },
1450 { 0x02168, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "FCRTH" , "Flow Control Receive Threshold High" },
1451 { 0x02410, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "RDFH" , "Receive Data FIFO Head" },
1452 { 0x02418, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "RDFT" , "Receive Data FIFO Tail" },
1453 { 0x02420, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "RDFHS" , "Receive Data FIFO Head Saved Register" },
1454 { 0x02428, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "RDFTS" , "Receive Data FIFO Tail Saved Register" },
1455 { 0x02430, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "RDFPC" , "Receive Data FIFO Packet Count" },
1456 { 0x02800, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadDefault , e1kRegWriteDefault , "RDBAL" , "Receive Descriptor Base Low" },
1457 { 0x02804, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadDefault , e1kRegWriteDefault , "RDBAH" , "Receive Descriptor Base High" },
1458 { 0x02808, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadDefault , e1kRegWriteDefault , "RDLEN" , "Receive Descriptor Length" },
1459 { 0x02810, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadDefault , e1kRegWriteDefault , "RDH" , "Receive Descriptor Head" },
1460 { 0x02818, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadDefault , e1kRegWriteRDT , "RDT" , "Receive Descriptor Tail" },
1461 { 0x02820, 0x00004, 0x0000FFFF, 0x0000FFFF, e1kRegReadDefault , e1kRegWriteRDTR , "RDTR" , "Receive Delay Timer" },
1462 { 0x02828, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "RXDCTL" , "Receive Descriptor Control" },
1463 { 0x0282c, 0x00004, 0x0000FFFF, 0x0000FFFF, e1kRegReadDefault , e1kRegWriteDefault , "RADV" , "Receive Interrupt Absolute Delay Timer" },
1464 { 0x02c00, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "RSRPD" , "Receive Small Packet Detect Interrupt" },
1465 { 0x03000, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "TXDMAC" , "TX DMA Control (N/A)" },
1466 { 0x03410, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "TDFH" , "Transmit Data FIFO Head" },
1467 { 0x03418, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "TDFT" , "Transmit Data FIFO Tail" },
1468 { 0x03420, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "TDFHS" , "Transmit Data FIFO Head Saved Register" },
1469 { 0x03428, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "TDFTS" , "Transmit Data FIFO Tail Saved Register" },
1470 { 0x03430, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "TDFPC" , "Transmit Data FIFO Packet Count" },
1471 { 0x03800, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadDefault , e1kRegWriteDefault , "TDBAL" , "Transmit Descriptor Base Low" },
1472 { 0x03804, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadDefault , e1kRegWriteDefault , "TDBAH" , "Transmit Descriptor Base High" },
1473 { 0x03808, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadDefault , e1kRegWriteDefault , "TDLEN" , "Transmit Descriptor Length" },
1474 { 0x03810, 0x00004, 0x0000FFFF, 0x0000FFFF, e1kRegReadDefault , e1kRegWriteDefault , "TDH" , "Transmit Descriptor Head" },
1475 { 0x03818, 0x00004, 0x0000FFFF, 0x0000FFFF, e1kRegReadDefault , e1kRegWriteTDT , "TDT" , "Transmit Descriptor Tail" },
1476 { 0x03820, 0x00004, 0x0000FFFF, 0x0000FFFF, e1kRegReadDefault , e1kRegWriteDefault , "TIDV" , "Transmit Interrupt Delay Value" },
1477 { 0x03828, 0x00004, 0xFF3F3F3F, 0xFF3F3F3F, e1kRegReadDefault , e1kRegWriteDefault , "TXDCTL" , "Transmit Descriptor Control" },
1478 { 0x0382c, 0x00004, 0x0000FFFF, 0x0000FFFF, e1kRegReadDefault , e1kRegWriteDefault , "TADV" , "Transmit Absolute Interrupt Delay Timer" },
1479 { 0x03830, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadDefault , e1kRegWriteDefault , "TSPMT" , "TCP Segmentation Pad and Threshold" },
1480 { 0x04000, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "CRCERRS" , "CRC Error Count" },
1481 { 0x04004, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "ALGNERRC", "Alignment Error Count" },
1482 { 0x04008, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "SYMERRS" , "Symbol Error Count" },
1483 { 0x0400c, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "RXERRC" , "RX Error Count" },
1484 { 0x04010, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "MPC" , "Missed Packets Count" },
1485 { 0x04014, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "SCC" , "Single Collision Count" },
1486 { 0x04018, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "ECOL" , "Excessive Collisions Count" },
1487 { 0x0401c, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "MCC" , "Multiple Collision Count" },
1488 { 0x04020, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "LATECOL" , "Late Collisions Count" },
1489 { 0x04028, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "COLC" , "Collision Count" },
1490 { 0x04030, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "DC" , "Defer Count" },
1491 { 0x04034, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "TNCRS" , "Transmit - No CRS" },
1492 { 0x04038, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "SEC" , "Sequence Error Count" },
1493 { 0x0403c, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "CEXTERR" , "Carrier Extension Error Count" },
1494 { 0x04040, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "RLEC" , "Receive Length Error Count" },
1495 { 0x04048, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "XONRXC" , "XON Received Count" },
1496 { 0x0404c, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "XONTXC" , "XON Transmitted Count" },
1497 { 0x04050, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "XOFFRXC" , "XOFF Received Count" },
1498 { 0x04054, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "XOFFTXC" , "XOFF Transmitted Count" },
1499 { 0x04058, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "FCRUC" , "FC Received Unsupported Count" },
1500 { 0x0405c, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "PRC64" , "Packets Received (64 Bytes) Count" },
1501 { 0x04060, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "PRC127" , "Packets Received (65-127 Bytes) Count" },
1502 { 0x04064, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "PRC255" , "Packets Received (128-255 Bytes) Count" },
1503 { 0x04068, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "PRC511" , "Packets Received (256-511 Bytes) Count" },
1504 { 0x0406c, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "PRC1023" , "Packets Received (512-1023 Bytes) Count" },
1505 { 0x04070, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "PRC1522" , "Packets Received (1024-Max Bytes)" },
1506 { 0x04074, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "GPRC" , "Good Packets Received Count" },
1507 { 0x04078, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "BPRC" , "Broadcast Packets Received Count" },
1508 { 0x0407c, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "MPRC" , "Multicast Packets Received Count" },
1509 { 0x04080, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "GPTC" , "Good Packets Transmitted Count" },
1510 { 0x04088, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "GORCL" , "Good Octets Received Count (Low)" },
1511 { 0x0408c, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "GORCH" , "Good Octets Received Count (Hi)" },
1512 { 0x04090, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "GOTCL" , "Good Octets Transmitted Count (Low)" },
1513 { 0x04094, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "GOTCH" , "Good Octets Transmitted Count (Hi)" },
1514 { 0x040a0, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "RNBC" , "Receive No Buffers Count" },
1515 { 0x040a4, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "RUC" , "Receive Undersize Count" },
1516 { 0x040a8, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "RFC" , "Receive Fragment Count" },
1517 { 0x040ac, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "ROC" , "Receive Oversize Count" },
1518 { 0x040b0, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "RJC" , "Receive Jabber Count" },
1519 { 0x040b4, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "MGTPRC" , "Management Packets Received Count" },
1520 { 0x040b8, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "MGTPDC" , "Management Packets Dropped Count" },
1521 { 0x040bc, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "MGTPTC" , "Management Pkts Transmitted Count" },
1522 { 0x040c0, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "TORL" , "Total Octets Received (Lo)" },
1523 { 0x040c4, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "TORH" , "Total Octets Received (Hi)" },
1524 { 0x040c8, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "TOTL" , "Total Octets Transmitted (Lo)" },
1525 { 0x040cc, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "TOTH" , "Total Octets Transmitted (Hi)" },
1526 { 0x040d0, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "TPR" , "Total Packets Received" },
1527 { 0x040d4, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "TPT" , "Total Packets Transmitted" },
1528 { 0x040d8, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "PTC64" , "Packets Transmitted (64 Bytes) Count" },
1529 { 0x040dc, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "PTC127" , "Packets Transmitted (65-127 Bytes) Count" },
1530 { 0x040e0, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "PTC255" , "Packets Transmitted (128-255 Bytes) Count" },
1531 { 0x040e4, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "PTC511" , "Packets Transmitted (256-511 Bytes) Count" },
1532 { 0x040e8, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "PTC1023" , "Packets Transmitted (512-1023 Bytes) Count" },
1533 { 0x040ec, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "PTC1522" , "Packets Transmitted (1024 Bytes or Greater) Count" },
1534 { 0x040f0, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "MPTC" , "Multicast Packets Transmitted Count" },
1535 { 0x040f4, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "BPTC" , "Broadcast Packets Transmitted Count" },
1536 { 0x040f8, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "TSCTC" , "TCP Segmentation Context Transmitted Count" },
1537 { 0x040fc, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "TSCTFC" , "TCP Segmentation Context Tx Fail Count" },
1538 { 0x05000, 0x00004, 0x000007FF, 0x000007FF, e1kRegReadDefault , e1kRegWriteDefault , "RXCSUM" , "Receive Checksum Control" },
1539 { 0x05800, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "WUC" , "Wakeup Control" },
1540 { 0x05808, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "WUFC" , "Wakeup Filter Control" },
1541 { 0x05810, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "WUS" , "Wakeup Status" },
1542 { 0x05820, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadDefault , e1kRegWriteDefault , "MANC" , "Management Control" },
1543 { 0x05838, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "IPAV" , "IP Address Valid" },
1544 { 0x05900, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "WUPL" , "Wakeup Packet Length" },
1545 { 0x05200, 0x00200, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadMTA , e1kRegWriteMTA , "MTA" , "Multicast Table Array (n)" },
1546 { 0x05400, 0x00080, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadRA , e1kRegWriteRA , "RA" , "Receive Address (64-bit) (n)" },
1547 { 0x05600, 0x00200, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadVFTA , e1kRegWriteVFTA , "VFTA" , "VLAN Filter Table Array (n)" },
1548 { 0x05840, 0x0001c, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "IP4AT" , "IPv4 Address Table" },
1549 { 0x05880, 0x00010, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "IP6AT" , "IPv6 Address Table" },
1550 { 0x05a00, 0x00080, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "WUPM" , "Wakeup Packet Memory" },
1551 { 0x05f00, 0x0001c, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "FFLT" , "Flexible Filter Length Table" },
1552 { 0x09000, 0x003fc, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "FFMT" , "Flexible Filter Mask Table" },
1553 { 0x09800, 0x003fc, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "FFVT" , "Flexible Filter Value Table" },
1554 { 0x10000, 0x10000, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "PBM" , "Packet Buffer Memory (n)" },
1555 { 0x00040, 0x00080, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadRA , e1kRegWriteRA , "RA82542" , "Receive Address (64-bit) (n) (82542)" },
1556 { 0x00200, 0x00200, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadMTA , e1kRegWriteMTA , "MTA82542", "Multicast Table Array (n) (82542)" },
1557 { 0x00600, 0x00200, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadVFTA , e1kRegWriteVFTA , "VFTA82542", "VLAN Filter Table Array (n) (82542)" }
1558};
1559
1560#ifdef LOG_ENABLED
1561
1562/**
1563 * Convert U32 value to hex string. Masked bytes are replaced with dots.
1564 *
1565 * @remarks The mask has half-byte byte (not bit) granularity (e.g. 0000000F).
1566 *
1567 * @returns The buffer.
1568 *
1569 * @param u32 The word to convert into string.
1570 * @param mask Selects which bytes to convert.
1571 * @param buf Where to put the result.
1572 */
1573static char *e1kU32toHex(uint32_t u32, uint32_t mask, char *buf)
1574{
1575 for (char *ptr = buf + 7; ptr >= buf; --ptr, u32 >>=4, mask >>=4)
1576 {
1577 if (mask & 0xF)
1578 *ptr = (u32 & 0xF) + ((u32 & 0xF) > 9 ? '7' : '0');
1579 else
1580 *ptr = '.';
1581 }
1582 buf[8] = 0;
1583 return buf;
1584}
1585
1586/**
1587 * Returns timer name for debug purposes.
1588 *
1589 * @returns The timer name.
1590 *
1591 * @param pThis The device state structure.
1592 * @param hTimer The timer to name.
1593 */
1594DECLINLINE(const char *) e1kGetTimerName(PE1KSTATE pThis, TMTIMERHANDLE hTimer)
1595{
1596 if (hTimer == pThis->hTIDTimer)
1597 return "TID";
1598 if (hTimer == pThis->hTADTimer)
1599 return "TAD";
1600 if (hTimer == pThis->hRIDTimer)
1601 return "RID";
1602 if (hTimer == pThis->hRADTimer)
1603 return "RAD";
1604 if (hTimer == pThis->hIntTimer)
1605 return "Int";
1606 if (hTimer == pThis->hTXDTimer)
1607 return "TXD";
1608 if (hTimer == pThis->hLUTimer)
1609 return "LinkUp";
1610 return "unknown";
1611}
1612
1613#endif /* LOG_ENABLED */
1614
1615/**
1616 * Arm a timer.
1617 *
1618 * @param pDevIns The device instance.
1619 * @param pThis Pointer to the device state structure.
1620 * @param hTimer The timer to arm.
1621 * @param uExpireIn Expiration interval in microseconds.
1622 */
1623DECLINLINE(void) e1kArmTimer(PPDMDEVINS pDevIns, PE1KSTATE pThis, TMTIMERHANDLE hTimer, uint32_t uExpireIn)
1624{
1625 if (pThis->fLocked)
1626 return;
1627
1628 E1kLog2(("%s Arming %s timer to fire in %d usec...\n",
1629 pThis->szPrf, e1kGetTimerName(pThis, hTimer), uExpireIn));
1630 int rc = PDMDevHlpTimerSetMicro(pDevIns, hTimer, uExpireIn);
1631 AssertRC(rc);
1632}
1633
1634#ifdef IN_RING3
1635/**
1636 * Cancel a timer.
1637 *
1638 * @param pDevIns The device instance.
1639 * @param pThis Pointer to the device state structure.
1640 * @param pTimer Pointer to the timer.
1641 */
1642DECLINLINE(void) e1kCancelTimer(PPDMDEVINS pDevIns, PE1KSTATE pThis, TMTIMERHANDLE hTimer)
1643{
1644 E1kLog2(("%s Stopping %s timer...\n",
1645 pThis->szPrf, e1kGetTimerName(pThis, hTimer)));
1646 int rc = PDMDevHlpTimerStop(pDevIns, hTimer);
1647 if (RT_FAILURE(rc))
1648 E1kLog2(("%s e1kCancelTimer: TMTimerStop(%s) failed with %Rrc\n",
1649 pThis->szPrf, e1kGetTimerName(pThis, hTimer), rc));
1650 RT_NOREF_PV(pThis);
1651}
1652#endif /* IN_RING3 */
1653
1654#define e1kCsEnter(ps, rc) PDMDevHlpCritSectEnter(pDevIns, &ps->cs, rc)
1655#define e1kCsLeave(ps) PDMDevHlpCritSectLeave(pDevIns, &ps->cs)
1656
1657#define e1kCsRxEnter(ps, rc) PDMDevHlpCritSectEnter(pDevIns, &ps->csRx, rc)
1658#define e1kCsRxLeave(ps) PDMDevHlpCritSectLeave(pDevIns, &ps->csRx)
1659#define e1kCsRxIsOwner(ps) PDMDevHlpCritSectIsOwner(pDevIns, &ps->csRx)
1660
1661#ifndef E1K_WITH_TX_CS
1662# define e1kCsTxEnter(ps, rc) VINF_SUCCESS
1663# define e1kCsTxLeave(ps) do { } while (0)
1664#else /* E1K_WITH_TX_CS */
1665# define e1kCsTxEnter(ps, rc) PDMDevHlpCritSectEnter(pDevIns, &ps->csTx, rc)
1666# define e1kCsTxLeave(ps) PDMDevHlpCritSectLeave(pDevIns, &ps->csTx)
1667#endif /* E1K_WITH_TX_CS */
1668
1669
1670/**
1671 * Wakeup the RX thread.
1672 */
1673static void e1kWakeupReceive(PPDMDEVINS pDevIns, PE1KSTATE pThis)
1674{
1675 if ( pThis->fMaybeOutOfSpace
1676 && pThis->hEventMoreRxDescAvail != NIL_SUPSEMEVENT)
1677 {
1678 STAM_COUNTER_INC(&pThis->CTX_SUFF_Z(StatRxOverflowWakeup));
1679 E1kLog(("%s Waking up Out-of-RX-space semaphore\n", pThis->szPrf));
1680 int rc = PDMDevHlpSUPSemEventSignal(pDevIns, pThis->hEventMoreRxDescAvail);
1681 AssertRC(rc);
1682 }
1683}
1684
1685#ifdef IN_RING3
1686
1687/**
1688 * Hardware reset. Revert all registers to initial values.
1689 *
1690 * @param pDevIns The device instance.
1691 * @param pThis The device state structure.
1692 * @param pThisCC The current context instance data.
1693 */
1694static void e1kR3HardReset(PPDMDEVINS pDevIns, PE1KSTATE pThis, PE1KSTATECC pThisCC)
1695{
1696 E1kLog(("%s Hard reset triggered\n", pThis->szPrf));
1697 /* No interrupts should survive device reset, see @bugref(9556). */
1698 if (pThis->fIntRaised)
1699 {
1700 /* Lower(0) INTA(0) */
1701 PDMDevHlpPCISetIrq(pDevIns, 0, 0);
1702 pThis->fIntRaised = false;
1703 E1kLog(("%s e1kR3HardReset: Lowered IRQ: ICR=%08x\n", pThis->szPrf, ICR));
1704 }
1705 memset(pThis->auRegs, 0, sizeof(pThis->auRegs));
1706 memset(pThis->aRecAddr.au32, 0, sizeof(pThis->aRecAddr.au32));
1707#ifdef E1K_INIT_RA0
1708 memcpy(pThis->aRecAddr.au32, pThis->macConfigured.au8,
1709 sizeof(pThis->macConfigured.au8));
1710 pThis->aRecAddr.array[0].ctl |= RA_CTL_AV;
1711#endif /* E1K_INIT_RA0 */
1712 STATUS = 0x0081; /* SPEED=10b (1000 Mb/s), FD=1b (Full Duplex) */
1713 EECD = 0x0100; /* EE_PRES=1b (EEPROM present) */
1714 CTRL = 0x0a09; /* FRCSPD=1b SPEED=10b LRST=1b FD=1b */
1715 TSPMT = 0x01000400;/* TSMT=0400h TSPBP=0100h */
1716 Assert(GET_BITS(RCTL, BSIZE) == 0);
1717 pThis->u16RxBSize = 2048;
1718
1719 uint16_t u16LedCtl = 0x0602; /* LED0/LINK_UP#, LED2/LINK100# */
1720 pThisCC->eeprom.readWord(0x2F, &u16LedCtl); /* Read LEDCTL defaults from EEPROM */
1721 LEDCTL = 0x07008300 | (((uint32_t)u16LedCtl & 0xCF00) << 8) | (u16LedCtl & 0xCF); /* Only LED0 and LED2 defaults come from EEPROM */
1722
1723 /* Reset promiscuous mode */
1724 if (pThisCC->pDrvR3)
1725 pThisCC->pDrvR3->pfnSetPromiscuousMode(pThisCC->pDrvR3, false);
1726
1727#ifdef E1K_WITH_TXD_CACHE
1728 int rc = e1kCsTxEnter(pThis, VERR_SEM_BUSY);
1729 if (RT_LIKELY(rc == VINF_SUCCESS))
1730 {
1731 pThis->nTxDFetched = 0;
1732 pThis->iTxDCurrent = 0;
1733 pThis->fGSO = false;
1734 pThis->cbTxAlloc = 0;
1735 e1kCsTxLeave(pThis);
1736 }
1737#endif /* E1K_WITH_TXD_CACHE */
1738#ifdef E1K_WITH_RXD_CACHE
1739 if (RT_LIKELY(e1kCsRxEnter(pThis, VERR_SEM_BUSY) == VINF_SUCCESS))
1740 {
1741 pThis->iRxDCurrent = pThis->nRxDFetched = 0;
1742 e1kCsRxLeave(pThis);
1743 }
1744#endif /* E1K_WITH_RXD_CACHE */
1745#ifdef E1K_LSC_ON_RESET
1746 E1kLog(("%s Will trigger LSC in %d seconds...\n",
1747 pThis->szPrf, pThis->cMsLinkUpDelay / 1000));
1748 e1kArmTimer(pDevIns, pThis, pThis->hLUTimer, pThis->cMsLinkUpDelay * 1000);
1749#endif /* E1K_LSC_ON_RESET */
1750}
1751
1752#endif /* IN_RING3 */
1753
1754/**
1755 * Compute Internet checksum.
1756 *
1757 * @remarks Refer to http://www.netfor2.com/checksum.html for short intro.
1758 *
1759 * @param pThis The device state structure.
1760 * @param cpPacket The packet.
1761 * @param cb The size of the packet.
1762 * @param pszText A string denoting direction of packet transfer.
1763 *
1764 * @return The 1's complement of the 1's complement sum.
1765 *
1766 * @thread E1000_TX
1767 */
1768static uint16_t e1kCSum16(const void *pvBuf, size_t cb)
1769{
1770 uint32_t csum = 0;
1771 uint16_t *pu16 = (uint16_t *)pvBuf;
1772
1773 while (cb > 1)
1774 {
1775 csum += *pu16++;
1776 cb -= 2;
1777 }
1778 if (cb)
1779 csum += *(uint8_t*)pu16;
1780 while (csum >> 16)
1781 csum = (csum >> 16) + (csum & 0xFFFF);
1782 Assert(csum < 65536);
1783 return (uint16_t)~csum;
1784}
1785
1786/**
1787 * Dump a packet to debug log.
1788 *
1789 * @param pDevIns The device instance.
1790 * @param pThis The device state structure.
1791 * @param cpPacket The packet.
1792 * @param cb The size of the packet.
1793 * @param pszText A string denoting direction of packet transfer.
1794 * @thread E1000_TX
1795 */
1796DECLINLINE(void) e1kPacketDump(PPDMDEVINS pDevIns, PE1KSTATE pThis, const uint8_t *cpPacket, size_t cb, const char *pszText)
1797{
1798#ifdef DEBUG
1799 if (RT_LIKELY(e1kCsEnter(pThis, VERR_SEM_BUSY) == VINF_SUCCESS))
1800 {
1801 Log4(("%s --- %s packet #%d: %RTmac => %RTmac (%d bytes) ---\n",
1802 pThis->szPrf, pszText, ++pThis->u32PktNo, cpPacket+6, cpPacket, cb));
1803 if (ntohs(*(uint16_t*)(cpPacket+12)) == 0x86DD)
1804 {
1805 Log4(("%s --- IPv6: %RTnaipv6 => %RTnaipv6\n",
1806 pThis->szPrf, cpPacket+14+8, cpPacket+14+24));
1807 if (*(cpPacket+14+6) == 0x6)
1808 Log4(("%s --- TCP: seq=%x ack=%x\n", pThis->szPrf,
1809 ntohl(*(uint32_t*)(cpPacket+14+40+4)), ntohl(*(uint32_t*)(cpPacket+14+40+8))));
1810 }
1811 else if (ntohs(*(uint16_t*)(cpPacket+12)) == 0x800)
1812 {
1813 Log4(("%s --- IPv4: %RTnaipv4 => %RTnaipv4\n",
1814 pThis->szPrf, *(uint32_t*)(cpPacket+14+12), *(uint32_t*)(cpPacket+14+16)));
1815 if (*(cpPacket+14+6) == 0x6)
1816 Log4(("%s --- TCP: seq=%x ack=%x\n", pThis->szPrf,
1817 ntohl(*(uint32_t*)(cpPacket+14+20+4)), ntohl(*(uint32_t*)(cpPacket+14+20+8))));
1818 }
1819 E1kLog3(("%.*Rhxd\n", cb, cpPacket));
1820 e1kCsLeave(pThis);
1821 }
1822#else
1823 if (RT_LIKELY(e1kCsEnter(pThis, VERR_SEM_BUSY) == VINF_SUCCESS))
1824 {
1825 if (ntohs(*(uint16_t*)(cpPacket+12)) == 0x86DD)
1826 E1kLogRel(("E1000: %s packet #%d, %RTmac => %RTmac, %RTnaipv6 => %RTnaipv6, seq=%x ack=%x\n",
1827 pszText, ++pThis->u32PktNo, cpPacket+6, cpPacket, cpPacket+14+8, cpPacket+14+24,
1828 ntohl(*(uint32_t*)(cpPacket+14+40+4)), ntohl(*(uint32_t*)(cpPacket+14+40+8))));
1829 else
1830 E1kLogRel(("E1000: %s packet #%d, %RTmac => %RTmac, %RTnaipv4 => %RTnaipv4, seq=%x ack=%x\n",
1831 pszText, ++pThis->u32PktNo, cpPacket+6, cpPacket,
1832 *(uint32_t*)(cpPacket+14+12), *(uint32_t*)(cpPacket+14+16),
1833 ntohl(*(uint32_t*)(cpPacket+14+20+4)), ntohl(*(uint32_t*)(cpPacket+14+20+8))));
1834 e1kCsLeave(pThis);
1835 }
1836 RT_NOREF2(cb, pszText);
1837#endif
1838}
1839
1840/**
1841 * Determine the type of transmit descriptor.
1842 *
1843 * @returns Descriptor type. See E1K_DTYP_XXX defines.
1844 *
1845 * @param pDesc Pointer to descriptor union.
1846 * @thread E1000_TX
1847 */
1848DECLINLINE(int) e1kGetDescType(E1KTXDESC *pDesc)
1849{
1850 if (pDesc->legacy.cmd.fDEXT)
1851 return pDesc->context.dw2.u4DTYP;
1852 return E1K_DTYP_LEGACY;
1853}
1854
1855
1856#ifdef E1K_WITH_RXD_CACHE
1857/**
1858 * Return the number of RX descriptor that belong to the hardware.
1859 *
1860 * @returns the number of available descriptors in RX ring.
1861 * @param pThis The device state structure.
1862 * @thread ???
1863 */
1864DECLINLINE(uint32_t) e1kGetRxLen(PE1KSTATE pThis)
1865{
1866 /**
1867 * Make sure RDT won't change during computation. EMT may modify RDT at
1868 * any moment.
1869 */
1870 uint32_t rdt = RDT;
1871 return (RDH > rdt ? RDLEN/sizeof(E1KRXDESC) : 0) + rdt - RDH;
1872}
1873
1874DECLINLINE(unsigned) e1kRxDInCache(PE1KSTATE pThis)
1875{
1876 return pThis->nRxDFetched > pThis->iRxDCurrent ?
1877 pThis->nRxDFetched - pThis->iRxDCurrent : 0;
1878}
1879
1880DECLINLINE(unsigned) e1kRxDIsCacheEmpty(PE1KSTATE pThis)
1881{
1882 return pThis->iRxDCurrent >= pThis->nRxDFetched;
1883}
1884
1885/**
1886 * Load receive descriptors from guest memory. The caller needs to be in Rx
1887 * critical section.
1888 *
1889 * We need two physical reads in case the tail wrapped around the end of RX
1890 * descriptor ring.
1891 *
1892 * @returns the actual number of descriptors fetched.
1893 * @param pDevIns The device instance.
1894 * @param pThis The device state structure.
1895 * @thread EMT, RX
1896 */
1897DECLINLINE(unsigned) e1kRxDPrefetch(PPDMDEVINS pDevIns, PE1KSTATE pThis)
1898{
1899 /* We've already loaded pThis->nRxDFetched descriptors past RDH. */
1900 unsigned nDescsAvailable = e1kGetRxLen(pThis) - e1kRxDInCache(pThis);
1901 unsigned nDescsToFetch = RT_MIN(nDescsAvailable, E1K_RXD_CACHE_SIZE - pThis->nRxDFetched);
1902 unsigned nDescsTotal = RDLEN / sizeof(E1KRXDESC);
1903 Assert(nDescsTotal != 0);
1904 if (nDescsTotal == 0)
1905 return 0;
1906 unsigned nFirstNotLoaded = (RDH + e1kRxDInCache(pThis)) % nDescsTotal;
1907 unsigned nDescsInSingleRead = RT_MIN(nDescsToFetch, nDescsTotal - nFirstNotLoaded);
1908 E1kLog3(("%s e1kRxDPrefetch: nDescsAvailable=%u nDescsToFetch=%u "
1909 "nDescsTotal=%u nFirstNotLoaded=0x%x nDescsInSingleRead=%u\n",
1910 pThis->szPrf, nDescsAvailable, nDescsToFetch, nDescsTotal,
1911 nFirstNotLoaded, nDescsInSingleRead));
1912 if (nDescsToFetch == 0)
1913 return 0;
1914 E1KRXDESC* pFirstEmptyDesc = &pThis->aRxDescriptors[pThis->nRxDFetched];
1915 PDMDevHlpPhysRead(pDevIns,
1916 ((uint64_t)RDBAH << 32) + RDBAL + nFirstNotLoaded * sizeof(E1KRXDESC),
1917 pFirstEmptyDesc, nDescsInSingleRead * sizeof(E1KRXDESC));
1918 // uint64_t addrBase = ((uint64_t)RDBAH << 32) + RDBAL;
1919 // unsigned i, j;
1920 // for (i = pThis->nRxDFetched; i < pThis->nRxDFetched + nDescsInSingleRead; ++i)
1921 // {
1922 // pThis->aRxDescAddr[i] = addrBase + (nFirstNotLoaded + i - pThis->nRxDFetched) * sizeof(E1KRXDESC);
1923 // E1kLog3(("%s aRxDescAddr[%d] = %p\n", pThis->szPrf, i, pThis->aRxDescAddr[i]));
1924 // }
1925 E1kLog3(("%s Fetched %u RX descriptors at %08x%08x(0x%x), RDLEN=%08x, RDH=%08x, RDT=%08x\n",
1926 pThis->szPrf, nDescsInSingleRead,
1927 RDBAH, RDBAL + RDH * sizeof(E1KRXDESC),
1928 nFirstNotLoaded, RDLEN, RDH, RDT));
1929 if (nDescsToFetch > nDescsInSingleRead)
1930 {
1931 PDMDevHlpPhysRead(pDevIns,
1932 ((uint64_t)RDBAH << 32) + RDBAL,
1933 pFirstEmptyDesc + nDescsInSingleRead,
1934 (nDescsToFetch - nDescsInSingleRead) * sizeof(E1KRXDESC));
1935 // Assert(i == pThis->nRxDFetched + nDescsInSingleRead);
1936 // for (j = 0; i < pThis->nRxDFetched + nDescsToFetch; ++i, ++j)
1937 // {
1938 // pThis->aRxDescAddr[i] = addrBase + j * sizeof(E1KRXDESC);
1939 // E1kLog3(("%s aRxDescAddr[%d] = %p\n", pThis->szPrf, i, pThis->aRxDescAddr[i]));
1940 // }
1941 E1kLog3(("%s Fetched %u RX descriptors at %08x%08x\n",
1942 pThis->szPrf, nDescsToFetch - nDescsInSingleRead,
1943 RDBAH, RDBAL));
1944 }
1945 pThis->nRxDFetched += nDescsToFetch;
1946 return nDescsToFetch;
1947}
1948
1949# ifdef IN_RING3 /* currently only used in ring-3 due to stack space requirements of the caller */
1950/**
1951 * Dump receive descriptor to debug log.
1952 *
1953 * @param pThis The device state structure.
1954 * @param pDesc Pointer to the descriptor.
1955 * @thread E1000_RX
1956 */
1957static void e1kPrintRDesc(PE1KSTATE pThis, E1KRXDESC *pDesc)
1958{
1959 RT_NOREF2(pThis, pDesc);
1960 E1kLog2(("%s <-- Receive Descriptor (%d bytes):\n", pThis->szPrf, pDesc->u16Length));
1961 E1kLog2((" Address=%16LX Length=%04X Csum=%04X\n",
1962 pDesc->u64BufAddr, pDesc->u16Length, pDesc->u16Checksum));
1963 E1kLog2((" STA: %s %s %s %s %s %s %s ERR: %s %s %s %s SPECIAL: %s VLAN=%03x PRI=%x\n",
1964 pDesc->status.fPIF ? "PIF" : "pif",
1965 pDesc->status.fIPCS ? "IPCS" : "ipcs",
1966 pDesc->status.fTCPCS ? "TCPCS" : "tcpcs",
1967 pDesc->status.fVP ? "VP" : "vp",
1968 pDesc->status.fIXSM ? "IXSM" : "ixsm",
1969 pDesc->status.fEOP ? "EOP" : "eop",
1970 pDesc->status.fDD ? "DD" : "dd",
1971 pDesc->status.fRXE ? "RXE" : "rxe",
1972 pDesc->status.fIPE ? "IPE" : "ipe",
1973 pDesc->status.fTCPE ? "TCPE" : "tcpe",
1974 pDesc->status.fCE ? "CE" : "ce",
1975 E1K_SPEC_CFI(pDesc->status.u16Special) ? "CFI" :"cfi",
1976 E1K_SPEC_VLAN(pDesc->status.u16Special),
1977 E1K_SPEC_PRI(pDesc->status.u16Special)));
1978}
1979# endif /* IN_RING3 */
1980#endif /* E1K_WITH_RXD_CACHE */
1981
1982/**
1983 * Dump transmit descriptor to debug log.
1984 *
1985 * @param pThis The device state structure.
1986 * @param pDesc Pointer to descriptor union.
1987 * @param pszDir A string denoting direction of descriptor transfer
1988 * @thread E1000_TX
1989 */
1990static void e1kPrintTDesc(PE1KSTATE pThis, E1KTXDESC *pDesc, const char *pszDir,
1991 unsigned uLevel = RTLOGGRPFLAGS_LEVEL_2)
1992{
1993 RT_NOREF4(pThis, pDesc, pszDir, uLevel);
1994
1995 /*
1996 * Unfortunately we cannot use our format handler here, we want R0 logging
1997 * as well.
1998 */
1999 switch (e1kGetDescType(pDesc))
2000 {
2001 case E1K_DTYP_CONTEXT:
2002 E1kLogX(uLevel, ("%s %s Context Transmit Descriptor %s\n",
2003 pThis->szPrf, pszDir, pszDir));
2004 E1kLogX(uLevel, (" IPCSS=%02X IPCSO=%02X IPCSE=%04X TUCSS=%02X TUCSO=%02X TUCSE=%04X\n",
2005 pDesc->context.ip.u8CSS, pDesc->context.ip.u8CSO, pDesc->context.ip.u16CSE,
2006 pDesc->context.tu.u8CSS, pDesc->context.tu.u8CSO, pDesc->context.tu.u16CSE));
2007 E1kLogX(uLevel, (" TUCMD:%s%s%s %s %s PAYLEN=%04x HDRLEN=%04x MSS=%04x STA: %s\n",
2008 pDesc->context.dw2.fIDE ? " IDE":"",
2009 pDesc->context.dw2.fRS ? " RS" :"",
2010 pDesc->context.dw2.fTSE ? " TSE":"",
2011 pDesc->context.dw2.fIP ? "IPv4":"IPv6",
2012 pDesc->context.dw2.fTCP ? "TCP":"UDP",
2013 pDesc->context.dw2.u20PAYLEN,
2014 pDesc->context.dw3.u8HDRLEN,
2015 pDesc->context.dw3.u16MSS,
2016 pDesc->context.dw3.fDD?"DD":""));
2017 break;
2018 case E1K_DTYP_DATA:
2019 E1kLogX(uLevel, ("%s %s Data Transmit Descriptor (%d bytes) %s\n",
2020 pThis->szPrf, pszDir, pDesc->data.cmd.u20DTALEN, pszDir));
2021 E1kLogX(uLevel, (" Address=%16LX DTALEN=%05X\n",
2022 pDesc->data.u64BufAddr,
2023 pDesc->data.cmd.u20DTALEN));
2024 E1kLogX(uLevel, (" DCMD:%s%s%s%s%s%s%s STA:%s%s%s POPTS:%s%s SPECIAL:%s VLAN=%03x PRI=%x\n",
2025 pDesc->data.cmd.fIDE ? " IDE" :"",
2026 pDesc->data.cmd.fVLE ? " VLE" :"",
2027 pDesc->data.cmd.fRPS ? " RPS" :"",
2028 pDesc->data.cmd.fRS ? " RS" :"",
2029 pDesc->data.cmd.fTSE ? " TSE" :"",
2030 pDesc->data.cmd.fIFCS? " IFCS":"",
2031 pDesc->data.cmd.fEOP ? " EOP" :"",
2032 pDesc->data.dw3.fDD ? " DD" :"",
2033 pDesc->data.dw3.fEC ? " EC" :"",
2034 pDesc->data.dw3.fLC ? " LC" :"",
2035 pDesc->data.dw3.fTXSM? " TXSM":"",
2036 pDesc->data.dw3.fIXSM? " IXSM":"",
2037 E1K_SPEC_CFI(pDesc->data.dw3.u16Special) ? "CFI" :"cfi",
2038 E1K_SPEC_VLAN(pDesc->data.dw3.u16Special),
2039 E1K_SPEC_PRI(pDesc->data.dw3.u16Special)));
2040 break;
2041 case E1K_DTYP_LEGACY:
2042 E1kLogX(uLevel, ("%s %s Legacy Transmit Descriptor (%d bytes) %s\n",
2043 pThis->szPrf, pszDir, pDesc->legacy.cmd.u16Length, pszDir));
2044 E1kLogX(uLevel, (" Address=%16LX DTALEN=%05X\n",
2045 pDesc->data.u64BufAddr,
2046 pDesc->legacy.cmd.u16Length));
2047 E1kLogX(uLevel, (" CMD:%s%s%s%s%s%s%s STA:%s%s%s CSO=%02x CSS=%02x SPECIAL:%s VLAN=%03x PRI=%x\n",
2048 pDesc->legacy.cmd.fIDE ? " IDE" :"",
2049 pDesc->legacy.cmd.fVLE ? " VLE" :"",
2050 pDesc->legacy.cmd.fRPS ? " RPS" :"",
2051 pDesc->legacy.cmd.fRS ? " RS" :"",
2052 pDesc->legacy.cmd.fIC ? " IC" :"",
2053 pDesc->legacy.cmd.fIFCS? " IFCS":"",
2054 pDesc->legacy.cmd.fEOP ? " EOP" :"",
2055 pDesc->legacy.dw3.fDD ? " DD" :"",
2056 pDesc->legacy.dw3.fEC ? " EC" :"",
2057 pDesc->legacy.dw3.fLC ? " LC" :"",
2058 pDesc->legacy.cmd.u8CSO,
2059 pDesc->legacy.dw3.u8CSS,
2060 E1K_SPEC_CFI(pDesc->legacy.dw3.u16Special) ? "CFI" :"cfi",
2061 E1K_SPEC_VLAN(pDesc->legacy.dw3.u16Special),
2062 E1K_SPEC_PRI(pDesc->legacy.dw3.u16Special)));
2063 break;
2064 default:
2065 E1kLog(("%s %s Invalid Transmit Descriptor %s\n",
2066 pThis->szPrf, pszDir, pszDir));
2067 break;
2068 }
2069}
2070
2071/**
2072 * Raise an interrupt later.
2073 *
2074 * @param pThis The device state structure.
2075 */
2076DECLINLINE(void) e1kPostponeInterrupt(PPDMDEVINS pDevIns, PE1KSTATE pThis, uint64_t nsDeadline)
2077{
2078 if (!PDMDevHlpTimerIsActive(pDevIns, pThis->hIntTimer))
2079 PDMDevHlpTimerSetNano(pDevIns, pThis->hIntTimer, nsDeadline);
2080}
2081
2082/**
2083 * Raise interrupt if not masked.
2084 *
2085 * @param pThis The device state structure.
2086 */
2087static int e1kRaiseInterrupt(PPDMDEVINS pDevIns, PE1KSTATE pThis, int rcBusy, uint32_t u32IntCause = 0)
2088{
2089 int rc = e1kCsEnter(pThis, rcBusy);
2090 if (RT_UNLIKELY(rc != VINF_SUCCESS))
2091 return rc;
2092
2093 E1K_INC_ISTAT_CNT(pThis->uStatIntTry);
2094 ICR |= u32IntCause;
2095 if (ICR & IMS)
2096 {
2097 if (pThis->fIntRaised)
2098 {
2099 E1K_INC_ISTAT_CNT(pThis->uStatIntSkip);
2100 E1kLog2(("%s e1kRaiseInterrupt: Already raised, skipped. ICR&IMS=%08x\n",
2101 pThis->szPrf, ICR & IMS));
2102 }
2103 else
2104 {
2105 uint64_t tsNow = PDMDevHlpTimerGet(pDevIns, pThis->hIntTimer);
2106 if (!!ITR && tsNow - pThis->u64AckedAt < ITR * 256
2107 && pThis->fItrEnabled && (pThis->fItrRxEnabled || !(ICR & ICR_RXT0)))
2108 {
2109 E1K_INC_ISTAT_CNT(pThis->uStatIntEarly);
2110 E1kLog2(("%s e1kRaiseInterrupt: Too early to raise again: %d ns < %d ns.\n",
2111 pThis->szPrf, (uint32_t)(tsNow - pThis->u64AckedAt), ITR * 256));
2112 e1kPostponeInterrupt(pDevIns, pThis, ITR * 256);
2113 }
2114 else
2115 {
2116
2117 /* Since we are delivering the interrupt now
2118 * there is no need to do it later -- stop the timer.
2119 */
2120 PDMDevHlpTimerStop(pDevIns, pThis->hIntTimer);
2121 E1K_INC_ISTAT_CNT(pThis->uStatInt);
2122 STAM_COUNTER_INC(&pThis->StatIntsRaised);
2123 /* Got at least one unmasked interrupt cause */
2124 pThis->fIntRaised = true;
2125 /* Raise(1) INTA(0) */
2126 E1kLogRel(("E1000: irq RAISED icr&mask=0x%x, icr=0x%x\n", ICR & IMS, ICR));
2127 PDMDevHlpPCISetIrq(pDevIns, 0, 1);
2128 E1kLog(("%s e1kRaiseInterrupt: Raised. ICR&IMS=%08x\n",
2129 pThis->szPrf, ICR & IMS));
2130 }
2131 }
2132 }
2133 else
2134 {
2135 E1K_INC_ISTAT_CNT(pThis->uStatIntMasked);
2136 E1kLog2(("%s e1kRaiseInterrupt: Not raising, ICR=%08x, IMS=%08x\n",
2137 pThis->szPrf, ICR, IMS));
2138 }
2139 e1kCsLeave(pThis);
2140 return VINF_SUCCESS;
2141}
2142
2143/**
2144 * Compute the physical address of the descriptor.
2145 *
2146 * @returns the physical address of the descriptor.
2147 *
2148 * @param baseHigh High-order 32 bits of descriptor table address.
2149 * @param baseLow Low-order 32 bits of descriptor table address.
2150 * @param idxDesc The descriptor index in the table.
2151 */
2152DECLINLINE(RTGCPHYS) e1kDescAddr(uint32_t baseHigh, uint32_t baseLow, uint32_t idxDesc)
2153{
2154 AssertCompile(sizeof(E1KRXDESC) == sizeof(E1KTXDESC));
2155 return ((uint64_t)baseHigh << 32) + baseLow + idxDesc * sizeof(E1KRXDESC);
2156}
2157
2158#ifdef IN_RING3 /* currently only used in ring-3 due to stack space requirements of the caller */
2159/**
2160 * Advance the head pointer of the receive descriptor queue.
2161 *
2162 * @remarks RDH always points to the next available RX descriptor.
2163 *
2164 * @param pDevIns The device instance.
2165 * @param pThis The device state structure.
2166 */
2167DECLINLINE(void) e1kAdvanceRDH(PPDMDEVINS pDevIns, PE1KSTATE pThis)
2168{
2169 Assert(e1kCsRxIsOwner(pThis));
2170 //e1kCsEnter(pThis, RT_SRC_POS);
2171 if (++RDH * sizeof(E1KRXDESC) >= RDLEN)
2172 RDH = 0;
2173#ifdef E1K_WITH_RXD_CACHE
2174 /*
2175 * We need to fetch descriptors now as the guest may advance RDT all the way
2176 * to RDH as soon as we generate RXDMT0 interrupt. This is mostly to provide
2177 * compatibility with Phar Lap ETS, see @bugref(7346). Note that we do not
2178 * check if the receiver is enabled. It must be, otherwise we won't get here
2179 * in the first place.
2180 *
2181 * Note that we should have moved both RDH and iRxDCurrent by now.
2182 */
2183 if (e1kRxDIsCacheEmpty(pThis))
2184 {
2185 /* Cache is empty, reset it and check if we can fetch more. */
2186 pThis->iRxDCurrent = pThis->nRxDFetched = 0;
2187 E1kLog3(("%s e1kAdvanceRDH: Rx cache is empty, RDH=%x RDT=%x "
2188 "iRxDCurrent=%x nRxDFetched=%x\n",
2189 pThis->szPrf, RDH, RDT, pThis->iRxDCurrent, pThis->nRxDFetched));
2190 e1kRxDPrefetch(pDevIns, pThis);
2191 }
2192#endif /* E1K_WITH_RXD_CACHE */
2193 /*
2194 * Compute current receive queue length and fire RXDMT0 interrupt
2195 * if we are low on receive buffers
2196 */
2197 uint32_t uRQueueLen = RDH>RDT ? RDLEN/sizeof(E1KRXDESC)-RDH+RDT : RDT-RDH;
2198 /*
2199 * The minimum threshold is controlled by RDMTS bits of RCTL:
2200 * 00 = 1/2 of RDLEN
2201 * 01 = 1/4 of RDLEN
2202 * 10 = 1/8 of RDLEN
2203 * 11 = reserved
2204 */
2205 uint32_t uMinRQThreshold = RDLEN / sizeof(E1KRXDESC) / (2 << GET_BITS(RCTL, RDMTS));
2206 if (uRQueueLen <= uMinRQThreshold)
2207 {
2208 E1kLogRel(("E1000: low on RX descriptors, RDH=%x RDT=%x len=%x threshold=%x\n", RDH, RDT, uRQueueLen, uMinRQThreshold));
2209 E1kLog2(("%s Low on RX descriptors, RDH=%x RDT=%x len=%x threshold=%x, raise an interrupt\n",
2210 pThis->szPrf, RDH, RDT, uRQueueLen, uMinRQThreshold));
2211 E1K_INC_ISTAT_CNT(pThis->uStatIntRXDMT0);
2212 e1kRaiseInterrupt(pDevIns, pThis, VERR_SEM_BUSY, ICR_RXDMT0);
2213 }
2214 E1kLog2(("%s e1kAdvanceRDH: at exit RDH=%x RDT=%x len=%x\n",
2215 pThis->szPrf, RDH, RDT, uRQueueLen));
2216 //e1kCsLeave(pThis);
2217}
2218#endif /* IN_RING3 */
2219
2220#ifdef E1K_WITH_RXD_CACHE
2221
2222# ifdef IN_RING3 /* currently only used in ring-3 due to stack space requirements of the caller */
2223
2224/**
2225 * Obtain the next RX descriptor from RXD cache, fetching descriptors from the
2226 * RX ring if the cache is empty.
2227 *
2228 * Note that we cannot advance the cache pointer (iRxDCurrent) yet as it will
2229 * go out of sync with RDH which will cause trouble when EMT checks if the
2230 * cache is empty to do pre-fetch @bugref(6217).
2231 *
2232 * @param pDevIns The device instance.
2233 * @param pThis The device state structure.
2234 * @thread RX
2235 */
2236DECLINLINE(E1KRXDESC *) e1kRxDGet(PPDMDEVINS pDevIns, PE1KSTATE pThis)
2237{
2238 Assert(e1kCsRxIsOwner(pThis));
2239 /* Check the cache first. */
2240 if (pThis->iRxDCurrent < pThis->nRxDFetched)
2241 return &pThis->aRxDescriptors[pThis->iRxDCurrent];
2242 /* Cache is empty, reset it and check if we can fetch more. */
2243 pThis->iRxDCurrent = pThis->nRxDFetched = 0;
2244 if (e1kRxDPrefetch(pDevIns, pThis))
2245 return &pThis->aRxDescriptors[pThis->iRxDCurrent];
2246 /* Out of Rx descriptors. */
2247 return NULL;
2248}
2249
2250
2251/**
2252 * Return the RX descriptor obtained with e1kRxDGet() and advance the cache
2253 * pointer. The descriptor gets written back to the RXD ring.
2254 *
2255 * @param pDevIns The device instance.
2256 * @param pThis The device state structure.
2257 * @param pDesc The descriptor being "returned" to the RX ring.
2258 * @thread RX
2259 */
2260DECLINLINE(void) e1kRxDPut(PPDMDEVINS pDevIns, PE1KSTATE pThis, E1KRXDESC* pDesc)
2261{
2262 Assert(e1kCsRxIsOwner(pThis));
2263 pThis->iRxDCurrent++;
2264 // Assert(pDesc >= pThis->aRxDescriptors);
2265 // Assert(pDesc < pThis->aRxDescriptors + E1K_RXD_CACHE_SIZE);
2266 // uint64_t addr = e1kDescAddr(RDBAH, RDBAL, RDH);
2267 // uint32_t rdh = RDH;
2268 // Assert(pThis->aRxDescAddr[pDesc - pThis->aRxDescriptors] == addr);
2269 PDMDevHlpPCIPhysWrite(pDevIns, e1kDescAddr(RDBAH, RDBAL, RDH), pDesc, sizeof(E1KRXDESC));
2270 /*
2271 * We need to print the descriptor before advancing RDH as it may fetch new
2272 * descriptors into the cache.
2273 */
2274 e1kPrintRDesc(pThis, pDesc);
2275 e1kAdvanceRDH(pDevIns, pThis);
2276}
2277
2278/**
2279 * Store a fragment of received packet at the specifed address.
2280 *
2281 * @param pDevIns The device instance.
2282 * @param pThis The device state structure.
2283 * @param pDesc The next available RX descriptor.
2284 * @param pvBuf The fragment.
2285 * @param cb The size of the fragment.
2286 */
2287static void e1kStoreRxFragment(PPDMDEVINS pDevIns, PE1KSTATE pThis, E1KRXDESC *pDesc, const void *pvBuf, size_t cb)
2288{
2289 STAM_PROFILE_ADV_START(&pThis->StatReceiveStore, a);
2290 E1kLog2(("%s e1kStoreRxFragment: store fragment of %04X at %016LX, EOP=%d\n",
2291 pThis->szPrf, cb, pDesc->u64BufAddr, pDesc->status.fEOP));
2292 PDMDevHlpPCIPhysWrite(pDevIns, pDesc->u64BufAddr, pvBuf, cb);
2293 pDesc->u16Length = (uint16_t)cb;
2294 Assert(pDesc->u16Length == cb);
2295 STAM_PROFILE_ADV_STOP(&pThis->StatReceiveStore, a);
2296 RT_NOREF(pThis);
2297}
2298
2299# endif /* IN_RING3 */
2300
2301#else /* !E1K_WITH_RXD_CACHE */
2302
2303/**
2304 * Store a fragment of received packet that fits into the next available RX
2305 * buffer.
2306 *
2307 * @remarks Trigger the RXT0 interrupt if it is the last fragment of the packet.
2308 *
2309 * @param pDevIns The device instance.
2310 * @param pThis The device state structure.
2311 * @param pDesc The next available RX descriptor.
2312 * @param pvBuf The fragment.
2313 * @param cb The size of the fragment.
2314 */
2315static void e1kStoreRxFragment(PPDMDEVINS pDevIns, PE1KSTATE pThis, E1KRXDESC *pDesc, const void *pvBuf, size_t cb)
2316{
2317 STAM_PROFILE_ADV_START(&pThis->StatReceiveStore, a);
2318 E1kLog2(("%s e1kStoreRxFragment: store fragment of %04X at %016LX, EOP=%d\n", pThis->szPrf, cb, pDesc->u64BufAddr, pDesc->status.fEOP));
2319 PDMDevHlpPCIPhysWrite(pDevIns, pDesc->u64BufAddr, pvBuf, cb);
2320 pDesc->u16Length = (uint16_t)cb; Assert(pDesc->u16Length == cb);
2321 /* Write back the descriptor */
2322 PDMDevHlpPCIPhysWrite(pDevIns, e1kDescAddr(RDBAH, RDBAL, RDH), pDesc, sizeof(E1KRXDESC));
2323 e1kPrintRDesc(pThis, pDesc);
2324 E1kLogRel(("E1000: Wrote back RX desc, RDH=%x\n", RDH));
2325 /* Advance head */
2326 e1kAdvanceRDH(pDevIns, pThis);
2327 //E1kLog2(("%s e1kStoreRxFragment: EOP=%d RDTR=%08X RADV=%08X\n", pThis->szPrf, pDesc->fEOP, RDTR, RADV));
2328 if (pDesc->status.fEOP)
2329 {
2330 /* Complete packet has been stored -- it is time to let the guest know. */
2331#ifdef E1K_USE_RX_TIMERS
2332 if (RDTR)
2333 {
2334 /* Arm the timer to fire in RDTR usec (discard .024) */
2335 e1kArmTimer(pDevIns, pThis, pThis->hRIDTimer, RDTR);
2336 /* If absolute timer delay is enabled and the timer is not running yet, arm it. */
2337 if (RADV != 0 && !PDMDevHlpTimerIsActive(pDevIns, pThis->CTX_SUFF(pRADTimer)))
2338 e1kArmTimer(pThis, pThis->hRADTimer, RADV);
2339 }
2340 else
2341 {
2342#endif
2343 /* 0 delay means immediate interrupt */
2344 E1K_INC_ISTAT_CNT(pThis->uStatIntRx);
2345 e1kRaiseInterrupt(pDevIns, pThis, VERR_SEM_BUSY, ICR_RXT0);
2346#ifdef E1K_USE_RX_TIMERS
2347 }
2348#endif
2349 }
2350 STAM_PROFILE_ADV_STOP(&pThis->StatReceiveStore, a);
2351}
2352
2353#endif /* !E1K_WITH_RXD_CACHE */
2354
2355/**
2356 * Returns true if it is a broadcast packet.
2357 *
2358 * @returns true if destination address indicates broadcast.
2359 * @param pvBuf The ethernet packet.
2360 */
2361DECLINLINE(bool) e1kIsBroadcast(const void *pvBuf)
2362{
2363 static const uint8_t s_abBcastAddr[] = { 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF };
2364 return memcmp(pvBuf, s_abBcastAddr, sizeof(s_abBcastAddr)) == 0;
2365}
2366
2367/**
2368 * Returns true if it is a multicast packet.
2369 *
2370 * @remarks returns true for broadcast packets as well.
2371 * @returns true if destination address indicates multicast.
2372 * @param pvBuf The ethernet packet.
2373 */
2374DECLINLINE(bool) e1kIsMulticast(const void *pvBuf)
2375{
2376 return (*(char*)pvBuf) & 1;
2377}
2378
2379#ifdef IN_RING3 /* currently only used in ring-3 due to stack space requirements of the caller */
2380/**
2381 * Set IXSM, IPCS and TCPCS flags according to the packet type.
2382 *
2383 * @remarks We emulate checksum offloading for major packets types only.
2384 *
2385 * @returns VBox status code.
2386 * @param pThis The device state structure.
2387 * @param pFrame The available data.
2388 * @param cb Number of bytes available in the buffer.
2389 * @param status Bit fields containing status info.
2390 */
2391static int e1kRxChecksumOffload(PE1KSTATE pThis, const uint8_t *pFrame, size_t cb, E1KRXDST *pStatus)
2392{
2393 /** @todo
2394 * It is not safe to bypass checksum verification for packets coming
2395 * from real wire. We currently unable to tell where packets are
2396 * coming from so we tell the driver to ignore our checksum flags
2397 * and do verification in software.
2398 */
2399# if 0
2400 uint16_t uEtherType = ntohs(*(uint16_t*)(pFrame + 12));
2401
2402 E1kLog2(("%s e1kRxChecksumOffload: EtherType=%x\n", pThis->szPrf, uEtherType));
2403
2404 switch (uEtherType)
2405 {
2406 case 0x800: /* IPv4 */
2407 {
2408 pStatus->fIXSM = false;
2409 pStatus->fIPCS = true;
2410 PRTNETIPV4 pIpHdr4 = (PRTNETIPV4)(pFrame + 14);
2411 /* TCP/UDP checksum offloading works with TCP and UDP only */
2412 pStatus->fTCPCS = pIpHdr4->ip_p == 6 || pIpHdr4->ip_p == 17;
2413 break;
2414 }
2415 case 0x86DD: /* IPv6 */
2416 pStatus->fIXSM = false;
2417 pStatus->fIPCS = false;
2418 pStatus->fTCPCS = true;
2419 break;
2420 default: /* ARP, VLAN, etc. */
2421 pStatus->fIXSM = true;
2422 break;
2423 }
2424# else
2425 pStatus->fIXSM = true;
2426 RT_NOREF_PV(pThis); RT_NOREF_PV(pFrame); RT_NOREF_PV(cb);
2427# endif
2428 return VINF_SUCCESS;
2429}
2430#endif /* IN_RING3 */
2431
2432/**
2433 * Pad and store received packet.
2434 *
2435 * @remarks Make sure that the packet appears to upper layer as one coming
2436 * from real Ethernet: pad it and insert FCS.
2437 *
2438 * @returns VBox status code.
2439 * @param pDevIns The device instance.
2440 * @param pThis The device state structure.
2441 * @param pvBuf The available data.
2442 * @param cb Number of bytes available in the buffer.
2443 * @param status Bit fields containing status info.
2444 */
2445static int e1kHandleRxPacket(PPDMDEVINS pDevIns, PE1KSTATE pThis, const void *pvBuf, size_t cb, E1KRXDST status)
2446{
2447#if defined(IN_RING3) /** @todo Remove this extra copying, it's gonna make us run out of kernel / hypervisor stack! */
2448 uint8_t rxPacket[E1K_MAX_RX_PKT_SIZE];
2449 uint8_t *ptr = rxPacket;
2450
2451 int rc = e1kCsRxEnter(pThis, VERR_SEM_BUSY);
2452 if (RT_UNLIKELY(rc != VINF_SUCCESS))
2453 return rc;
2454
2455 if (cb > 70) /* unqualified guess */
2456 pThis->led.Asserted.s.fReading = pThis->led.Actual.s.fReading = 1;
2457
2458 Assert(cb <= E1K_MAX_RX_PKT_SIZE);
2459 Assert(cb > 16);
2460 size_t cbMax = ((RCTL & RCTL_LPE) ? E1K_MAX_RX_PKT_SIZE - 4 : 1518) - (status.fVP ? 0 : 4);
2461 E1kLog3(("%s Max RX packet size is %u\n", pThis->szPrf, cbMax));
2462 if (status.fVP)
2463 {
2464 /* VLAN packet -- strip VLAN tag in VLAN mode */
2465 if ((CTRL & CTRL_VME) && cb > 16)
2466 {
2467 uint16_t *u16Ptr = (uint16_t*)pvBuf;
2468 memcpy(rxPacket, pvBuf, 12); /* Copy src and dst addresses */
2469 status.u16Special = RT_BE2H_U16(u16Ptr[7]); /* Extract VLAN tag */
2470 memcpy(rxPacket + 12, (uint8_t*)pvBuf + 16, cb - 16); /* Copy the rest of the packet */
2471 cb -= 4;
2472 E1kLog3(("%s Stripped tag for VLAN %u (cb=%u)\n",
2473 pThis->szPrf, status.u16Special, cb));
2474 }
2475 else
2476 {
2477 status.fVP = false; /* Set VP only if we stripped the tag */
2478 memcpy(rxPacket, pvBuf, cb);
2479 }
2480 }
2481 else
2482 memcpy(rxPacket, pvBuf, cb);
2483 /* Pad short packets */
2484 if (cb < 60)
2485 {
2486 memset(rxPacket + cb, 0, 60 - cb);
2487 cb = 60;
2488 }
2489 if (!(RCTL & RCTL_SECRC) && cb <= cbMax)
2490 {
2491 STAM_PROFILE_ADV_START(&pThis->StatReceiveCRC, a);
2492 /*
2493 * Add FCS if CRC stripping is not enabled. Since the value of CRC
2494 * is ignored by most of drivers we may as well save us the trouble
2495 * of calculating it (see EthernetCRC CFGM parameter).
2496 */
2497 if (pThis->fEthernetCRC)
2498 *(uint32_t*)(rxPacket + cb) = RTCrc32(rxPacket, cb);
2499 cb += sizeof(uint32_t);
2500 STAM_PROFILE_ADV_STOP(&pThis->StatReceiveCRC, a);
2501 E1kLog3(("%s Added FCS (cb=%u)\n", pThis->szPrf, cb));
2502 }
2503 /* Compute checksum of complete packet */
2504 size_t cbCSumStart = RT_MIN(GET_BITS(RXCSUM, PCSS), cb);
2505 uint16_t checksum = e1kCSum16(rxPacket + cbCSumStart, cb - cbCSumStart);
2506 e1kRxChecksumOffload(pThis, rxPacket, cb, &status);
2507
2508 /* Update stats */
2509 E1K_INC_CNT32(GPRC);
2510 if (e1kIsBroadcast(pvBuf))
2511 E1K_INC_CNT32(BPRC);
2512 else if (e1kIsMulticast(pvBuf))
2513 E1K_INC_CNT32(MPRC);
2514 /* Update octet receive counter */
2515 E1K_ADD_CNT64(GORCL, GORCH, cb);
2516 STAM_REL_COUNTER_ADD(&pThis->StatReceiveBytes, cb);
2517 if (cb == 64)
2518 E1K_INC_CNT32(PRC64);
2519 else if (cb < 128)
2520 E1K_INC_CNT32(PRC127);
2521 else if (cb < 256)
2522 E1K_INC_CNT32(PRC255);
2523 else if (cb < 512)
2524 E1K_INC_CNT32(PRC511);
2525 else if (cb < 1024)
2526 E1K_INC_CNT32(PRC1023);
2527 else
2528 E1K_INC_CNT32(PRC1522);
2529
2530 E1K_INC_ISTAT_CNT(pThis->uStatRxFrm);
2531
2532# ifdef E1K_WITH_RXD_CACHE
2533 while (cb > 0)
2534 {
2535 E1KRXDESC *pDesc = e1kRxDGet(pDevIns, pThis);
2536
2537 if (pDesc == NULL)
2538 {
2539 E1kLog(("%s Out of receive buffers, dropping the packet "
2540 "(cb=%u, in_cache=%u, RDH=%x RDT=%x)\n",
2541 pThis->szPrf, cb, e1kRxDInCache(pThis), RDH, RDT));
2542 break;
2543 }
2544# else /* !E1K_WITH_RXD_CACHE */
2545 if (RDH == RDT)
2546 {
2547 E1kLog(("%s Out of receive buffers, dropping the packet\n",
2548 pThis->szPrf));
2549 }
2550 /* Store the packet to receive buffers */
2551 while (RDH != RDT)
2552 {
2553 /* Load the descriptor pointed by head */
2554 E1KRXDESC desc, *pDesc = &desc;
2555 PDMDevHlpPhysRead(pDevIns, e1kDescAddr(RDBAH, RDBAL, RDH), &desc, sizeof(desc));
2556# endif /* !E1K_WITH_RXD_CACHE */
2557 if (pDesc->u64BufAddr)
2558 {
2559 uint16_t u16RxBufferSize = pThis->u16RxBSize; /* see @bugref{9427} */
2560
2561 /* Update descriptor */
2562 pDesc->status = status;
2563 pDesc->u16Checksum = checksum;
2564 pDesc->status.fDD = true;
2565
2566 /*
2567 * We need to leave Rx critical section here or we risk deadlocking
2568 * with EMT in e1kRegWriteRDT when the write is to an unallocated
2569 * page or has an access handler associated with it.
2570 * Note that it is safe to leave the critical section here since
2571 * e1kRegWriteRDT() never modifies RDH. It never touches already
2572 * fetched RxD cache entries either.
2573 */
2574 if (cb > u16RxBufferSize)
2575 {
2576 pDesc->status.fEOP = false;
2577 e1kCsRxLeave(pThis);
2578 e1kStoreRxFragment(pDevIns, pThis, pDesc, ptr, u16RxBufferSize);
2579 rc = e1kCsRxEnter(pThis, VERR_SEM_BUSY);
2580 if (RT_UNLIKELY(rc != VINF_SUCCESS))
2581 return rc;
2582 ptr += u16RxBufferSize;
2583 cb -= u16RxBufferSize;
2584 }
2585 else
2586 {
2587 pDesc->status.fEOP = true;
2588 e1kCsRxLeave(pThis);
2589 e1kStoreRxFragment(pDevIns, pThis, pDesc, ptr, cb);
2590# ifdef E1K_WITH_RXD_CACHE
2591 rc = e1kCsRxEnter(pThis, VERR_SEM_BUSY);
2592 if (RT_UNLIKELY(rc != VINF_SUCCESS))
2593 return rc;
2594 cb = 0;
2595# else /* !E1K_WITH_RXD_CACHE */
2596 pThis->led.Actual.s.fReading = 0;
2597 return VINF_SUCCESS;
2598# endif /* !E1K_WITH_RXD_CACHE */
2599 }
2600 /*
2601 * Note: RDH is advanced by e1kStoreRxFragment if E1K_WITH_RXD_CACHE
2602 * is not defined.
2603 */
2604 }
2605# ifdef E1K_WITH_RXD_CACHE
2606 /* Write back the descriptor. */
2607 pDesc->status.fDD = true;
2608 e1kRxDPut(pDevIns, pThis, pDesc);
2609# else /* !E1K_WITH_RXD_CACHE */
2610 else
2611 {
2612 /* Write back the descriptor. */
2613 pDesc->status.fDD = true;
2614 PDMDevHlpPCIPhysWrite(pDevIns, e1kDescAddr(RDBAH, RDBAL, RDH), pDesc, sizeof(E1KRXDESC));
2615 e1kAdvanceRDH(pDevIns, pThis);
2616 }
2617# endif /* !E1K_WITH_RXD_CACHE */
2618 }
2619
2620 if (cb > 0)
2621 E1kLog(("%s Out of receive buffers, dropping %u bytes", pThis->szPrf, cb));
2622
2623 pThis->led.Actual.s.fReading = 0;
2624
2625 e1kCsRxLeave(pThis);
2626# ifdef E1K_WITH_RXD_CACHE
2627 /* Complete packet has been stored -- it is time to let the guest know. */
2628# ifdef E1K_USE_RX_TIMERS
2629 if (RDTR)
2630 {
2631 /* Arm the timer to fire in RDTR usec (discard .024) */
2632 e1kArmTimer(pThis, pThis->hRIDTimer, RDTR);
2633 /* If absolute timer delay is enabled and the timer is not running yet, arm it. */
2634 if (RADV != 0 && !PDMDevHlpTimerIsActive(pDevIns, pThis->hRADTimer))
2635 e1kArmTimer(pThis, pThis->hRADTimer, RADV);
2636 }
2637 else
2638 {
2639# endif /* E1K_USE_RX_TIMERS */
2640 /* 0 delay means immediate interrupt */
2641 E1K_INC_ISTAT_CNT(pThis->uStatIntRx);
2642 e1kRaiseInterrupt(pDevIns, pThis, VERR_SEM_BUSY, ICR_RXT0);
2643# ifdef E1K_USE_RX_TIMERS
2644 }
2645# endif /* E1K_USE_RX_TIMERS */
2646# endif /* E1K_WITH_RXD_CACHE */
2647
2648 return VINF_SUCCESS;
2649#else /* !IN_RING3 */
2650 RT_NOREF(pDevIns, pThis, pvBuf, cb, status);
2651 return VERR_INTERNAL_ERROR_2;
2652#endif /* !IN_RING3 */
2653}
2654
2655
2656#ifdef IN_RING3
2657/**
2658 * Bring the link up after the configured delay, 5 seconds by default.
2659 *
2660 * @param pDevIns The device instance.
2661 * @param pThis The device state structure.
2662 * @thread any
2663 */
2664DECLINLINE(void) e1kBringLinkUpDelayed(PPDMDEVINS pDevIns, PE1KSTATE pThis)
2665{
2666 E1kLog(("%s Will bring up the link in %d seconds...\n",
2667 pThis->szPrf, pThis->cMsLinkUpDelay / 1000));
2668 e1kArmTimer(pDevIns, pThis, pThis->hLUTimer, pThis->cMsLinkUpDelay * 1000);
2669}
2670
2671/**
2672 * Bring up the link immediately.
2673 *
2674 * @param pDevIns The device instance.
2675 * @param pThis The device state structure.
2676 * @param pThisCC The current context instance data.
2677 */
2678DECLINLINE(void) e1kR3LinkUp(PPDMDEVINS pDevIns, PE1KSTATE pThis, PE1KSTATECC pThisCC)
2679{
2680 E1kLog(("%s Link is up\n", pThis->szPrf));
2681 STATUS |= STATUS_LU;
2682 Phy::setLinkStatus(&pThis->phy, true);
2683 e1kRaiseInterrupt(pDevIns, pThis, VERR_SEM_BUSY, ICR_LSC);
2684 if (pThisCC->pDrvR3)
2685 pThisCC->pDrvR3->pfnNotifyLinkChanged(pThisCC->pDrvR3, PDMNETWORKLINKSTATE_UP);
2686 /* Trigger processing of pending TX descriptors (see @bugref{8942}). */
2687 PDMDevHlpTaskTrigger(pDevIns, pThis->hTxTask);
2688}
2689
2690/**
2691 * Bring down the link immediately.
2692 *
2693 * @param pDevIns The device instance.
2694 * @param pThis The device state structure.
2695 * @param pThisCC The current context instance data.
2696 */
2697DECLINLINE(void) e1kR3LinkDown(PPDMDEVINS pDevIns, PE1KSTATE pThis, PE1KSTATECC pThisCC)
2698{
2699 E1kLog(("%s Link is down\n", pThis->szPrf));
2700 STATUS &= ~STATUS_LU;
2701#ifdef E1K_LSC_ON_RESET
2702 Phy::setLinkStatus(&pThis->phy, false);
2703#endif /* E1K_LSC_ON_RESET */
2704 e1kRaiseInterrupt(pDevIns, pThis, VERR_SEM_BUSY, ICR_LSC);
2705 if (pThisCC->pDrvR3)
2706 pThisCC->pDrvR3->pfnNotifyLinkChanged(pThisCC->pDrvR3, PDMNETWORKLINKSTATE_DOWN);
2707}
2708
2709/**
2710 * Bring down the link temporarily.
2711 *
2712 * @param pDevIns The device instance.
2713 * @param pThis The device state structure.
2714 * @param pThisCC The current context instance data.
2715 */
2716DECLINLINE(void) e1kR3LinkDownTemp(PPDMDEVINS pDevIns, PE1KSTATE pThis, PE1KSTATECC pThisCC)
2717{
2718 E1kLog(("%s Link is down temporarily\n", pThis->szPrf));
2719 STATUS &= ~STATUS_LU;
2720 Phy::setLinkStatus(&pThis->phy, false);
2721 e1kRaiseInterrupt(pDevIns, pThis, VERR_SEM_BUSY, ICR_LSC);
2722 /*
2723 * Notifying the associated driver that the link went down (even temporarily)
2724 * seems to be the right thing, but it was not done before. This may cause
2725 * a regression if the driver does not expect the link to go down as a result
2726 * of sending PDMNETWORKLINKSTATE_DOWN_RESUME to this device. Earlier versions
2727 * of code notified the driver that the link was up! See @bugref{7057}.
2728 */
2729 if (pThisCC->pDrvR3)
2730 pThisCC->pDrvR3->pfnNotifyLinkChanged(pThisCC->pDrvR3, PDMNETWORKLINKSTATE_DOWN);
2731 e1kBringLinkUpDelayed(pDevIns, pThis);
2732}
2733#endif /* IN_RING3 */
2734
2735#if 0 /* unused */
2736/**
2737 * Read handler for Device Status register.
2738 *
2739 * Get the link status from PHY.
2740 *
2741 * @returns VBox status code.
2742 *
2743 * @param pThis The device state structure.
2744 * @param offset Register offset in memory-mapped frame.
2745 * @param index Register index in register array.
2746 * @param mask Used to implement partial reads (8 and 16-bit).
2747 */
2748static int e1kRegReadCTRL(PE1KSTATE pThis, uint32_t offset, uint32_t index, uint32_t *pu32Value)
2749{
2750 E1kLog(("%s e1kRegReadCTRL: mdio dir=%s mdc dir=%s mdc=%d\n",
2751 pThis->szPrf, (CTRL & CTRL_MDIO_DIR)?"OUT":"IN ",
2752 (CTRL & CTRL_MDC_DIR)?"OUT":"IN ", !!(CTRL & CTRL_MDC)));
2753 if ((CTRL & CTRL_MDIO_DIR) == 0 && (CTRL & CTRL_MDC))
2754 {
2755 /* MDC is high and MDIO pin is used for input, read MDIO pin from PHY */
2756 if (Phy::readMDIO(&pThis->phy))
2757 *pu32Value = CTRL | CTRL_MDIO;
2758 else
2759 *pu32Value = CTRL & ~CTRL_MDIO;
2760 E1kLog(("%s e1kRegReadCTRL: Phy::readMDIO(%d)\n",
2761 pThis->szPrf, !!(*pu32Value & CTRL_MDIO)));
2762 }
2763 else
2764 {
2765 /* MDIO pin is used for output, ignore it */
2766 *pu32Value = CTRL;
2767 }
2768 return VINF_SUCCESS;
2769}
2770#endif /* unused */
2771
2772/**
2773 * A callback used by PHY to indicate that the link needs to be updated due to
2774 * reset of PHY.
2775 *
2776 * @param pDevIns The device instance.
2777 * @thread any
2778 */
2779void e1kPhyLinkResetCallback(PPDMDEVINS pDevIns)
2780{
2781 PE1KSTATE pThis = PDMDEVINS_2_DATA(pDevIns, PE1KSTATE);
2782
2783 /* Make sure we have cable connected and MAC can talk to PHY */
2784 if (pThis->fCableConnected && (CTRL & CTRL_SLU))
2785 e1kArmTimer(pDevIns, pThis, pThis->hLUTimer, E1K_INIT_LINKUP_DELAY_US);
2786}
2787
2788/**
2789 * Write handler for Device Control register.
2790 *
2791 * Handles reset.
2792 *
2793 * @param pThis The device state structure.
2794 * @param offset Register offset in memory-mapped frame.
2795 * @param index Register index in register array.
2796 * @param value The value to store.
2797 * @param mask Used to implement partial writes (8 and 16-bit).
2798 * @thread EMT
2799 */
2800static int e1kRegWriteCTRL(PPDMDEVINS pDevIns, PE1KSTATE pThis, uint32_t offset, uint32_t index, uint32_t value)
2801{
2802 int rc = VINF_SUCCESS;
2803
2804 if (value & CTRL_RESET)
2805 { /* RST */
2806#ifndef IN_RING3
2807 return VINF_IOM_R3_MMIO_WRITE;
2808#else
2809 e1kR3HardReset(pDevIns, pThis, PDMDEVINS_2_DATA_CC(pDevIns, PE1KSTATECC));
2810#endif
2811 }
2812 else
2813 {
2814#ifdef E1K_LSC_ON_SLU
2815 /*
2816 * When the guest changes 'Set Link Up' bit from 0 to 1 we check if
2817 * the link is down and the cable is connected, and if they are we
2818 * bring the link up, see @bugref{8624}.
2819 */
2820 if ( (value & CTRL_SLU)
2821 && !(CTRL & CTRL_SLU)
2822 && pThis->fCableConnected
2823 && !(STATUS & STATUS_LU))
2824 {
2825 /* It should take about 2 seconds for the link to come up */
2826 e1kArmTimer(pDevIns, pThis, pThis->hLUTimer, E1K_INIT_LINKUP_DELAY_US);
2827 }
2828#else /* !E1K_LSC_ON_SLU */
2829 if ( (value & CTRL_SLU)
2830 && !(CTRL & CTRL_SLU)
2831 && pThis->fCableConnected
2832 && !PDMDevHlpTimerIsActive(pDevIns, pThis->hLUTimer))
2833 {
2834 /* PXE does not use LSC interrupts, see @bugref{9113}. */
2835 STATUS |= STATUS_LU;
2836 }
2837#endif /* !E1K_LSC_ON_SLU */
2838 if ((value & CTRL_VME) != (CTRL & CTRL_VME))
2839 {
2840 E1kLog(("%s VLAN Mode %s\n", pThis->szPrf, (value & CTRL_VME) ? "Enabled" : "Disabled"));
2841 }
2842 Log7(("%s e1kRegWriteCTRL: mdio dir=%s mdc dir=%s mdc=%s mdio=%d\n",
2843 pThis->szPrf, (value & CTRL_MDIO_DIR)?"OUT":"IN ",
2844 (value & CTRL_MDC_DIR)?"OUT":"IN ", (value & CTRL_MDC)?"HIGH":"LOW ", !!(value & CTRL_MDIO)));
2845 if (value & CTRL_MDC)
2846 {
2847 if (value & CTRL_MDIO_DIR)
2848 {
2849 Log7(("%s e1kRegWriteCTRL: Phy::writeMDIO(%d)\n", pThis->szPrf, !!(value & CTRL_MDIO)));
2850 /* MDIO direction pin is set to output and MDC is high, write MDIO pin value to PHY */
2851 Phy::writeMDIO(&pThis->phy, !!(value & CTRL_MDIO), pDevIns);
2852 }
2853 else
2854 {
2855 if (Phy::readMDIO(&pThis->phy))
2856 value |= CTRL_MDIO;
2857 else
2858 value &= ~CTRL_MDIO;
2859 Log7(("%s e1kRegWriteCTRL: Phy::readMDIO(%d)\n", pThis->szPrf, !!(value & CTRL_MDIO)));
2860 }
2861 }
2862 rc = e1kRegWriteDefault(pDevIns, pThis, offset, index, value);
2863 }
2864
2865 return rc;
2866}
2867
2868/**
2869 * Write handler for EEPROM/Flash Control/Data register.
2870 *
2871 * Handles EEPROM access requests; forwards writes to EEPROM device if access has been granted.
2872 *
2873 * @param pThis The device state structure.
2874 * @param offset Register offset in memory-mapped frame.
2875 * @param index Register index in register array.
2876 * @param value The value to store.
2877 * @param mask Used to implement partial writes (8 and 16-bit).
2878 * @thread EMT
2879 */
2880static int e1kRegWriteEECD(PPDMDEVINS pDevIns, PE1KSTATE pThis, uint32_t offset, uint32_t index, uint32_t value)
2881{
2882 RT_NOREF(pDevIns, offset, index);
2883#ifdef IN_RING3
2884 /* So far we are concerned with lower byte only */
2885 if ((EECD & EECD_EE_GNT) || pThis->eChip == E1K_CHIP_82543GC)
2886 {
2887 /* Access to EEPROM granted -- forward 4-wire bits to EEPROM device */
2888 /* Note: 82543GC does not need to request EEPROM access */
2889 STAM_PROFILE_ADV_START(&pThis->StatEEPROMWrite, a);
2890 PE1KSTATECC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PE1KSTATECC);
2891 pThisCC->eeprom.write(value & EECD_EE_WIRES);
2892 STAM_PROFILE_ADV_STOP(&pThis->StatEEPROMWrite, a);
2893 }
2894 if (value & EECD_EE_REQ)
2895 EECD |= EECD_EE_REQ|EECD_EE_GNT;
2896 else
2897 EECD &= ~EECD_EE_GNT;
2898 //e1kRegWriteDefault(pThis, offset, index, value );
2899
2900 return VINF_SUCCESS;
2901#else /* !IN_RING3 */
2902 RT_NOREF(pThis, value);
2903 return VINF_IOM_R3_MMIO_WRITE;
2904#endif /* !IN_RING3 */
2905}
2906
2907/**
2908 * Read handler for EEPROM/Flash Control/Data register.
2909 *
2910 * Lower 4 bits come from EEPROM device if EEPROM access has been granted.
2911 *
2912 * @returns VBox status code.
2913 *
2914 * @param pThis The device state structure.
2915 * @param offset Register offset in memory-mapped frame.
2916 * @param index Register index in register array.
2917 * @param mask Used to implement partial reads (8 and 16-bit).
2918 * @thread EMT
2919 */
2920static int e1kRegReadEECD(PPDMDEVINS pDevIns, PE1KSTATE pThis, uint32_t offset, uint32_t index, uint32_t *pu32Value)
2921{
2922#ifdef IN_RING3
2923 uint32_t value = 0; /* Get rid of false positive in parfait. */
2924 int rc = e1kRegReadDefault(pDevIns, pThis, offset, index, &value);
2925 if (RT_SUCCESS(rc))
2926 {
2927 if ((value & EECD_EE_GNT) || pThis->eChip == E1K_CHIP_82543GC)
2928 {
2929 /* Note: 82543GC does not need to request EEPROM access */
2930 /* Access to EEPROM granted -- get 4-wire bits to EEPROM device */
2931 STAM_PROFILE_ADV_START(&pThis->StatEEPROMRead, a);
2932 PE1KSTATECC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PE1KSTATECC);
2933 value |= pThisCC->eeprom.read();
2934 STAM_PROFILE_ADV_STOP(&pThis->StatEEPROMRead, a);
2935 }
2936 *pu32Value = value;
2937 }
2938
2939 return rc;
2940#else /* !IN_RING3 */
2941 RT_NOREF_PV(pDevIns); RT_NOREF_PV(pThis); RT_NOREF_PV(offset); RT_NOREF_PV(index); RT_NOREF_PV(pu32Value);
2942 return VINF_IOM_R3_MMIO_READ;
2943#endif /* !IN_RING3 */
2944}
2945
2946/**
2947 * Write handler for EEPROM Read register.
2948 *
2949 * Handles EEPROM word access requests, reads EEPROM and stores the result
2950 * into DATA field.
2951 *
2952 * @param pThis The device state structure.
2953 * @param offset Register offset in memory-mapped frame.
2954 * @param index Register index in register array.
2955 * @param value The value to store.
2956 * @param mask Used to implement partial writes (8 and 16-bit).
2957 * @thread EMT
2958 */
2959static int e1kRegWriteEERD(PPDMDEVINS pDevIns, PE1KSTATE pThis, uint32_t offset, uint32_t index, uint32_t value)
2960{
2961#ifdef IN_RING3
2962 /* Make use of 'writable' and 'readable' masks. */
2963 e1kRegWriteDefault(pDevIns, pThis, offset, index, value);
2964 /* DONE and DATA are set only if read was triggered by START. */
2965 if (value & EERD_START)
2966 {
2967 STAM_PROFILE_ADV_START(&pThis->StatEEPROMRead, a);
2968 uint16_t tmp;
2969 PE1KSTATECC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PE1KSTATECC);
2970 if (pThisCC->eeprom.readWord(GET_BITS_V(value, EERD, ADDR), &tmp))
2971 SET_BITS(EERD, DATA, tmp);
2972 EERD |= EERD_DONE;
2973 STAM_PROFILE_ADV_STOP(&pThis->StatEEPROMRead, a);
2974 }
2975
2976 return VINF_SUCCESS;
2977#else /* !IN_RING3 */
2978 RT_NOREF_PV(pDevIns); RT_NOREF_PV(pThis); RT_NOREF_PV(offset); RT_NOREF_PV(index); RT_NOREF_PV(value);
2979 return VINF_IOM_R3_MMIO_WRITE;
2980#endif /* !IN_RING3 */
2981}
2982
2983
2984/**
2985 * Write handler for MDI Control register.
2986 *
2987 * Handles PHY read/write requests; forwards requests to internal PHY device.
2988 *
2989 * @param pThis The device state structure.
2990 * @param offset Register offset in memory-mapped frame.
2991 * @param index Register index in register array.
2992 * @param value The value to store.
2993 * @param mask Used to implement partial writes (8 and 16-bit).
2994 * @thread EMT
2995 */
2996static int e1kRegWriteMDIC(PPDMDEVINS pDevIns, PE1KSTATE pThis, uint32_t offset, uint32_t index, uint32_t value)
2997{
2998 if (value & MDIC_INT_EN)
2999 {
3000 E1kLog(("%s ERROR! Interrupt at the end of an MDI cycle is not supported yet.\n",
3001 pThis->szPrf));
3002 }
3003 else if (value & MDIC_READY)
3004 {
3005 E1kLog(("%s ERROR! Ready bit is not reset by software during write operation.\n",
3006 pThis->szPrf));
3007 }
3008 else if (GET_BITS_V(value, MDIC, PHY) != 1)
3009 {
3010 E1kLog(("%s WARNING! Access to invalid PHY detected, phy=%d.\n",
3011 pThis->szPrf, GET_BITS_V(value, MDIC, PHY)));
3012 /*
3013 * Some drivers scan the MDIO bus for a PHY. We can work with these
3014 * drivers if we set MDIC_READY and MDIC_ERROR when there isn't a PHY
3015 * at the requested address, see @bugref{7346}.
3016 */
3017 MDIC = MDIC_READY | MDIC_ERROR;
3018 }
3019 else
3020 {
3021 /* Store the value */
3022 e1kRegWriteDefault(pDevIns, pThis, offset, index, value);
3023 STAM_COUNTER_INC(&pThis->StatPHYAccesses);
3024 /* Forward op to PHY */
3025 if (value & MDIC_OP_READ)
3026 SET_BITS(MDIC, DATA, Phy::readRegister(&pThis->phy, GET_BITS_V(value, MDIC, REG), pDevIns));
3027 else
3028 Phy::writeRegister(&pThis->phy, GET_BITS_V(value, MDIC, REG), value & MDIC_DATA_MASK, pDevIns);
3029 /* Let software know that we are done */
3030 MDIC |= MDIC_READY;
3031 }
3032
3033 return VINF_SUCCESS;
3034}
3035
3036/**
3037 * Write handler for Interrupt Cause Read register.
3038 *
3039 * Bits corresponding to 1s in 'value' will be cleared in ICR register.
3040 *
3041 * @param pThis The device state structure.
3042 * @param offset Register offset in memory-mapped frame.
3043 * @param index Register index in register array.
3044 * @param value The value to store.
3045 * @param mask Used to implement partial writes (8 and 16-bit).
3046 * @thread EMT
3047 */
3048static int e1kRegWriteICR(PPDMDEVINS pDevIns, PE1KSTATE pThis, uint32_t offset, uint32_t index, uint32_t value)
3049{
3050 ICR &= ~value;
3051
3052 RT_NOREF_PV(pDevIns); RT_NOREF_PV(pThis); RT_NOREF_PV(offset); RT_NOREF_PV(index);
3053 return VINF_SUCCESS;
3054}
3055
3056/**
3057 * Read handler for Interrupt Cause Read register.
3058 *
3059 * Reading this register acknowledges all interrupts.
3060 *
3061 * @returns VBox status code.
3062 *
3063 * @param pThis The device state structure.
3064 * @param offset Register offset in memory-mapped frame.
3065 * @param index Register index in register array.
3066 * @param mask Not used.
3067 * @thread EMT
3068 */
3069static int e1kRegReadICR(PPDMDEVINS pDevIns, PE1KSTATE pThis, uint32_t offset, uint32_t index, uint32_t *pu32Value)
3070{
3071 int rc = e1kCsEnter(pThis, VINF_IOM_R3_MMIO_READ);
3072 if (RT_UNLIKELY(rc != VINF_SUCCESS))
3073 return rc;
3074
3075 uint32_t value = 0;
3076 rc = e1kRegReadDefault(pDevIns, pThis, offset, index, &value);
3077 if (RT_SUCCESS(rc))
3078 {
3079 if (value)
3080 {
3081 if (!pThis->fIntRaised)
3082 E1K_INC_ISTAT_CNT(pThis->uStatNoIntICR);
3083 /*
3084 * Not clearing ICR causes QNX to hang as it reads ICR in a loop
3085 * with disabled interrupts.
3086 */
3087 //if (IMS)
3088 if (1)
3089 {
3090 /*
3091 * Interrupts were enabled -- we are supposedly at the very
3092 * beginning of interrupt handler
3093 */
3094 E1kLogRel(("E1000: irq lowered, icr=0x%x\n", ICR));
3095 E1kLog(("%s e1kRegReadICR: Lowered IRQ (%08x)\n", pThis->szPrf, ICR));
3096 /* Clear all pending interrupts */
3097 ICR = 0;
3098 pThis->fIntRaised = false;
3099 /* Lower(0) INTA(0) */
3100 PDMDevHlpPCISetIrq(pDevIns, 0, 0);
3101
3102 pThis->u64AckedAt = PDMDevHlpTimerGet(pDevIns, pThis->hIntTimer);
3103 if (pThis->fIntMaskUsed)
3104 pThis->fDelayInts = true;
3105 }
3106 else
3107 {
3108 /*
3109 * Interrupts are disabled -- in windows guests ICR read is done
3110 * just before re-enabling interrupts
3111 */
3112 E1kLog(("%s e1kRegReadICR: Suppressing auto-clear due to disabled interrupts (%08x)\n", pThis->szPrf, ICR));
3113 }
3114 }
3115 *pu32Value = value;
3116 }
3117 e1kCsLeave(pThis);
3118
3119 return rc;
3120}
3121
3122/**
3123 * Write handler for Interrupt Cause Set register.
3124 *
3125 * Bits corresponding to 1s in 'value' will be set in ICR register.
3126 *
3127 * @param pThis The device state structure.
3128 * @param offset Register offset in memory-mapped frame.
3129 * @param index Register index in register array.
3130 * @param value The value to store.
3131 * @param mask Used to implement partial writes (8 and 16-bit).
3132 * @thread EMT
3133 */
3134static int e1kRegWriteICS(PPDMDEVINS pDevIns, PE1KSTATE pThis, uint32_t offset, uint32_t index, uint32_t value)
3135{
3136 RT_NOREF_PV(offset); RT_NOREF_PV(index);
3137 E1K_INC_ISTAT_CNT(pThis->uStatIntICS);
3138 return e1kRaiseInterrupt(pDevIns, pThis, VINF_IOM_R3_MMIO_WRITE, value & g_aE1kRegMap[ICS_IDX].writable);
3139}
3140
3141/**
3142 * Write handler for Interrupt Mask Set register.
3143 *
3144 * Will trigger pending interrupts.
3145 *
3146 * @param pThis The device state structure.
3147 * @param offset Register offset in memory-mapped frame.
3148 * @param index Register index in register array.
3149 * @param value The value to store.
3150 * @param mask Used to implement partial writes (8 and 16-bit).
3151 * @thread EMT
3152 */
3153static int e1kRegWriteIMS(PPDMDEVINS pDevIns, PE1KSTATE pThis, uint32_t offset, uint32_t index, uint32_t value)
3154{
3155 RT_NOREF_PV(offset); RT_NOREF_PV(index);
3156
3157 IMS |= value;
3158 E1kLogRel(("E1000: irq enabled, RDH=%x RDT=%x TDH=%x TDT=%x\n", RDH, RDT, TDH, TDT));
3159 E1kLog(("%s e1kRegWriteIMS: IRQ enabled\n", pThis->szPrf));
3160 /*
3161 * We cannot raise an interrupt here as it will occasionally cause an interrupt storm
3162 * in Windows guests (see @bugref{8624}, @bugref{5023}).
3163 */
3164 if ((ICR & IMS) && !pThis->fLocked)
3165 {
3166 E1K_INC_ISTAT_CNT(pThis->uStatIntIMS);
3167 e1kPostponeInterrupt(pDevIns, pThis, E1K_IMS_INT_DELAY_NS);
3168 }
3169
3170 return VINF_SUCCESS;
3171}
3172
3173/**
3174 * Write handler for Interrupt Mask Clear register.
3175 *
3176 * Bits corresponding to 1s in 'value' will be cleared in IMS register.
3177 *
3178 * @param pThis The device state structure.
3179 * @param offset Register offset in memory-mapped frame.
3180 * @param index Register index in register array.
3181 * @param value The value to store.
3182 * @param mask Used to implement partial writes (8 and 16-bit).
3183 * @thread EMT
3184 */
3185static int e1kRegWriteIMC(PPDMDEVINS pDevIns, PE1KSTATE pThis, uint32_t offset, uint32_t index, uint32_t value)
3186{
3187 RT_NOREF_PV(offset); RT_NOREF_PV(index);
3188
3189 int rc = e1kCsEnter(pThis, VINF_IOM_R3_MMIO_WRITE);
3190 if (RT_UNLIKELY(rc != VINF_SUCCESS))
3191 return rc;
3192 if (pThis->fIntRaised)
3193 {
3194 /*
3195 * Technically we should reset fIntRaised in ICR read handler, but it will cause
3196 * Windows to freeze since it may receive an interrupt while still in the very beginning
3197 * of interrupt handler.
3198 */
3199 E1K_INC_ISTAT_CNT(pThis->uStatIntLower);
3200 STAM_COUNTER_INC(&pThis->StatIntsPrevented);
3201 E1kLogRel(("E1000: irq lowered (IMC), icr=0x%x\n", ICR));
3202 /* Lower(0) INTA(0) */
3203 PDMDevHlpPCISetIrq(pDevIns, 0, 0);
3204 pThis->fIntRaised = false;
3205 E1kLog(("%s e1kRegWriteIMC: Lowered IRQ: ICR=%08x\n", pThis->szPrf, ICR));
3206 }
3207 IMS &= ~value;
3208 E1kLog(("%s e1kRegWriteIMC: IRQ disabled\n", pThis->szPrf));
3209 e1kCsLeave(pThis);
3210
3211 return VINF_SUCCESS;
3212}
3213
3214/**
3215 * Write handler for Receive Control register.
3216 *
3217 * @param pThis The device state structure.
3218 * @param offset Register offset in memory-mapped frame.
3219 * @param index Register index in register array.
3220 * @param value The value to store.
3221 * @param mask Used to implement partial writes (8 and 16-bit).
3222 * @thread EMT
3223 */
3224static int e1kRegWriteRCTL(PPDMDEVINS pDevIns, PE1KSTATE pThis, uint32_t offset, uint32_t index, uint32_t value)
3225{
3226 /* Update promiscuous mode */
3227 bool fBecomePromiscous = !!(value & (RCTL_UPE | RCTL_MPE));
3228 if (fBecomePromiscous != !!( RCTL & (RCTL_UPE | RCTL_MPE)))
3229 {
3230 /* Promiscuity has changed, pass the knowledge on. */
3231#ifndef IN_RING3
3232 return VINF_IOM_R3_MMIO_WRITE;
3233#else
3234 PE1KSTATECC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PE1KSTATECC);
3235 if (pThisCC->pDrvR3)
3236 pThisCC->pDrvR3->pfnSetPromiscuousMode(pThisCC->pDrvR3, fBecomePromiscous);
3237#endif
3238 }
3239
3240 /* Adjust receive buffer size */
3241 unsigned cbRxBuf = 2048 >> GET_BITS_V(value, RCTL, BSIZE);
3242 if (value & RCTL_BSEX)
3243 cbRxBuf *= 16;
3244 if (cbRxBuf > E1K_MAX_RX_PKT_SIZE)
3245 cbRxBuf = E1K_MAX_RX_PKT_SIZE;
3246 if (cbRxBuf != pThis->u16RxBSize)
3247 E1kLog2(("%s e1kRegWriteRCTL: Setting receive buffer size to %d (old %d)\n",
3248 pThis->szPrf, cbRxBuf, pThis->u16RxBSize));
3249 Assert(cbRxBuf < 65536);
3250 pThis->u16RxBSize = (uint16_t)cbRxBuf;
3251
3252 /* Update the register */
3253 return e1kRegWriteDefault(pDevIns, pThis, offset, index, value);
3254}
3255
3256/**
3257 * Write handler for Packet Buffer Allocation register.
3258 *
3259 * TXA = 64 - RXA.
3260 *
3261 * @param pThis The device state structure.
3262 * @param offset Register offset in memory-mapped frame.
3263 * @param index Register index in register array.
3264 * @param value The value to store.
3265 * @param mask Used to implement partial writes (8 and 16-bit).
3266 * @thread EMT
3267 */
3268static int e1kRegWritePBA(PPDMDEVINS pDevIns, PE1KSTATE pThis, uint32_t offset, uint32_t index, uint32_t value)
3269{
3270 e1kRegWriteDefault(pDevIns, pThis, offset, index, value);
3271 PBA_st->txa = 64 - PBA_st->rxa;
3272
3273 return VINF_SUCCESS;
3274}
3275
3276/**
3277 * Write handler for Receive Descriptor Tail register.
3278 *
3279 * @remarks Write into RDT forces switch to HC and signal to
3280 * e1kR3NetworkDown_WaitReceiveAvail().
3281 *
3282 * @returns VBox status code.
3283 *
3284 * @param pThis The device state structure.
3285 * @param offset Register offset in memory-mapped frame.
3286 * @param index Register index in register array.
3287 * @param value The value to store.
3288 * @param mask Used to implement partial writes (8 and 16-bit).
3289 * @thread EMT
3290 */
3291static int e1kRegWriteRDT(PPDMDEVINS pDevIns, PE1KSTATE pThis, uint32_t offset, uint32_t index, uint32_t value)
3292{
3293#ifndef IN_RING3
3294 /* XXX */
3295// return VINF_IOM_R3_MMIO_WRITE;
3296#endif
3297 int rc = e1kCsRxEnter(pThis, VINF_IOM_R3_MMIO_WRITE);
3298 if (RT_LIKELY(rc == VINF_SUCCESS))
3299 {
3300 E1kLog(("%s e1kRegWriteRDT\n", pThis->szPrf));
3301#ifndef E1K_WITH_RXD_CACHE
3302 /*
3303 * Some drivers advance RDT too far, so that it equals RDH. This
3304 * somehow manages to work with real hardware but not with this
3305 * emulated device. We can work with these drivers if we just
3306 * write 1 less when we see a driver writing RDT equal to RDH,
3307 * see @bugref{7346}.
3308 */
3309 if (value == RDH)
3310 {
3311 if (RDH == 0)
3312 value = (RDLEN / sizeof(E1KRXDESC)) - 1;
3313 else
3314 value = RDH - 1;
3315 }
3316#endif /* !E1K_WITH_RXD_CACHE */
3317 rc = e1kRegWriteDefault(pDevIns, pThis, offset, index, value);
3318#ifdef E1K_WITH_RXD_CACHE
3319 /*
3320 * We need to fetch descriptors now as RDT may go whole circle
3321 * before we attempt to store a received packet. For example,
3322 * Intel's DOS drivers use 2 (!) RX descriptors with the total ring
3323 * size being only 8 descriptors! Note that we fetch descriptors
3324 * only when the cache is empty to reduce the number of memory reads
3325 * in case of frequent RDT writes. Don't fetch anything when the
3326 * receiver is disabled either as RDH, RDT, RDLEN can be in some
3327 * messed up state.
3328 * Note that despite the cache may seem empty, meaning that there are
3329 * no more available descriptors in it, it may still be used by RX
3330 * thread which has not yet written the last descriptor back but has
3331 * temporarily released the RX lock in order to write the packet body
3332 * to descriptor's buffer. At this point we still going to do prefetch
3333 * but it won't actually fetch anything if there are no unused slots in
3334 * our "empty" cache (nRxDFetched==E1K_RXD_CACHE_SIZE). We must not
3335 * reset the cache here even if it appears empty. It will be reset at
3336 * a later point in e1kRxDGet().
3337 */
3338 if (e1kRxDIsCacheEmpty(pThis) && (RCTL & RCTL_EN))
3339 e1kRxDPrefetch(pDevIns, pThis);
3340#endif /* E1K_WITH_RXD_CACHE */
3341 e1kCsRxLeave(pThis);
3342 if (RT_SUCCESS(rc))
3343 {
3344 /* Signal that we have more receive descriptors available. */
3345 e1kWakeupReceive(pDevIns, pThis);
3346 }
3347 }
3348 return rc;
3349}
3350
3351/**
3352 * Write handler for Receive Delay Timer register.
3353 *
3354 * @param pThis The device state structure.
3355 * @param offset Register offset in memory-mapped frame.
3356 * @param index Register index in register array.
3357 * @param value The value to store.
3358 * @param mask Used to implement partial writes (8 and 16-bit).
3359 * @thread EMT
3360 */
3361static int e1kRegWriteRDTR(PPDMDEVINS pDevIns, PE1KSTATE pThis, uint32_t offset, uint32_t index, uint32_t value)
3362{
3363 e1kRegWriteDefault(pDevIns, pThis, offset, index, value);
3364 if (value & RDTR_FPD)
3365 {
3366 /* Flush requested, cancel both timers and raise interrupt */
3367#ifdef E1K_USE_RX_TIMERS
3368 e1kCancelTimer(pDevIns, pThis, pThis->hRIDTimer);
3369 e1kCancelTimer(pDevIns, pThis, pThis->hRADTimer);
3370#endif
3371 E1K_INC_ISTAT_CNT(pThis->uStatIntRDTR);
3372 return e1kRaiseInterrupt(pDevIns, pThis, VINF_IOM_R3_MMIO_WRITE, ICR_RXT0);
3373 }
3374
3375 return VINF_SUCCESS;
3376}
3377
3378DECLINLINE(uint32_t) e1kGetTxLen(PE1KSTATE pThis)
3379{
3380 /**
3381 * Make sure TDT won't change during computation. EMT may modify TDT at
3382 * any moment.
3383 */
3384 uint32_t tdt = TDT;
3385 return (TDH>tdt ? TDLEN/sizeof(E1KTXDESC) : 0) + tdt - TDH;
3386}
3387
3388#ifdef IN_RING3
3389
3390# ifdef E1K_TX_DELAY
3391/**
3392 * Transmit Delay Timer handler.
3393 *
3394 * @remarks We only get here when the timer expires.
3395 *
3396 * @param pDevIns Pointer to device instance structure.
3397 * @param pTimer Pointer to the timer.
3398 * @param pvUser NULL.
3399 * @thread EMT
3400 */
3401static DECLCALLBACK(void) e1kR3TxDelayTimer(PPDMDEVINS pDevIns, PTMTIMER pTimer, void *pvUser)
3402{
3403 PE1KSTATE pThis = (PE1KSTATE)pvUser;
3404 Assert(PDMCritSectIsOwner(&pThis->csTx));
3405
3406 E1K_INC_ISTAT_CNT(pThis->uStatTxDelayExp);
3407# ifdef E1K_INT_STATS
3408 uint64_t u64Elapsed = RTTimeNanoTS() - pThis->u64ArmedAt;
3409 if (u64Elapsed > pThis->uStatMaxTxDelay)
3410 pThis->uStatMaxTxDelay = u64Elapsed;
3411# endif
3412 int rc = e1kXmitPending(pDevIns, pThis, false /*fOnWorkerThread*/);
3413 AssertMsg(RT_SUCCESS(rc) || rc == VERR_TRY_AGAIN, ("%Rrc\n", rc));
3414}
3415# endif /* E1K_TX_DELAY */
3416
3417//# ifdef E1K_USE_TX_TIMERS
3418
3419/**
3420 * Transmit Interrupt Delay Timer handler.
3421 *
3422 * @remarks We only get here when the timer expires.
3423 *
3424 * @param pDevIns Pointer to device instance structure.
3425 * @param pTimer Pointer to the timer.
3426 * @param pvUser NULL.
3427 * @thread EMT
3428 */
3429static DECLCALLBACK(void) e1kR3TxIntDelayTimer(PPDMDEVINS pDevIns, PTMTIMER pTimer, void *pvUser)
3430{
3431 RT_NOREF(pDevIns);
3432 RT_NOREF(pTimer);
3433 PE1KSTATE pThis = (PE1KSTATE)pvUser;
3434
3435 E1K_INC_ISTAT_CNT(pThis->uStatTID);
3436 /* Cancel absolute delay timer as we have already got attention */
3437# ifndef E1K_NO_TAD
3438 e1kCancelTimer(pDevIns, pThis, pThis->hTADTimer);
3439# endif
3440 e1kRaiseInterrupt(pDevIns, pThis, ICR_TXDW);
3441}
3442
3443/**
3444 * Transmit Absolute Delay Timer handler.
3445 *
3446 * @remarks We only get here when the timer expires.
3447 *
3448 * @param pDevIns Pointer to device instance structure.
3449 * @param pTimer Pointer to the timer.
3450 * @param pvUser NULL.
3451 * @thread EMT
3452 */
3453static DECLCALLBACK(void) e1kR3TxAbsDelayTimer(PPDMDEVINS pDevIns, PTMTIMER pTimer, void *pvUser)
3454{
3455 RT_NOREF(pDevIns);
3456 RT_NOREF(pTimer);
3457 PE1KSTATE pThis = (PE1KSTATE)pvUser;
3458
3459 E1K_INC_ISTAT_CNT(pThis->uStatTAD);
3460 /* Cancel interrupt delay timer as we have already got attention */
3461 e1kCancelTimer(pDevIns, pThis, pThis->hTIDTimer);
3462 e1kRaiseInterrupt(pDevIns, pThis, ICR_TXDW);
3463}
3464
3465//# endif /* E1K_USE_TX_TIMERS */
3466# ifdef E1K_USE_RX_TIMERS
3467
3468/**
3469 * Receive Interrupt Delay Timer handler.
3470 *
3471 * @remarks We only get here when the timer expires.
3472 *
3473 * @param pDevIns Pointer to device instance structure.
3474 * @param pTimer Pointer to the timer.
3475 * @param pvUser NULL.
3476 * @thread EMT
3477 */
3478static DECLCALLBACK(void) e1kR3RxIntDelayTimer(PPDMDEVINS pDevIns, PTMTIMER pTimer, void *pvUser)
3479{
3480 PE1KSTATE pThis = (PE1KSTATE)pvUser;
3481
3482 E1K_INC_ISTAT_CNT(pThis->uStatRID);
3483 /* Cancel absolute delay timer as we have already got attention */
3484 e1kCancelTimer(pDevIns, pThis, pThis->hRADTimer);
3485 e1kRaiseInterrupt(pDevIns, pThis, ICR_RXT0);
3486}
3487
3488/**
3489 * Receive Absolute Delay Timer handler.
3490 *
3491 * @remarks We only get here when the timer expires.
3492 *
3493 * @param pDevIns Pointer to device instance structure.
3494 * @param pTimer Pointer to the timer.
3495 * @param pvUser NULL.
3496 * @thread EMT
3497 */
3498static DECLCALLBACK(void) e1kR3RxAbsDelayTimer(PPDMDEVINS pDevIns, PTMTIMER pTimer, void *pvUser)
3499{
3500 PE1KSTATE pThis = (PE1KSTATE)pvUser;
3501
3502 E1K_INC_ISTAT_CNT(pThis->uStatRAD);
3503 /* Cancel interrupt delay timer as we have already got attention */
3504 e1kCancelTimer(pDevIns, pThis, pThis->hRIDTimer);
3505 e1kRaiseInterrupt(pDevIns, pThis, ICR_RXT0);
3506}
3507
3508# endif /* E1K_USE_RX_TIMERS */
3509
3510/**
3511 * Late Interrupt Timer handler.
3512 *
3513 * @param pDevIns Pointer to device instance structure.
3514 * @param pTimer Pointer to the timer.
3515 * @param pvUser NULL.
3516 * @thread EMT
3517 */
3518static DECLCALLBACK(void) e1kR3LateIntTimer(PPDMDEVINS pDevIns, PTMTIMER pTimer, void *pvUser)
3519{
3520 RT_NOREF(pDevIns, pTimer);
3521 PE1KSTATE pThis = (PE1KSTATE)pvUser;
3522
3523 STAM_PROFILE_ADV_START(&pThis->StatLateIntTimer, a);
3524 STAM_COUNTER_INC(&pThis->StatLateInts);
3525 E1K_INC_ISTAT_CNT(pThis->uStatIntLate);
3526# if 0
3527 if (pThis->iStatIntLost > -100)
3528 pThis->iStatIntLost--;
3529# endif
3530 e1kRaiseInterrupt(pDevIns, pThis, VERR_SEM_BUSY, 0);
3531 STAM_PROFILE_ADV_STOP(&pThis->StatLateIntTimer, a);
3532}
3533
3534/**
3535 * Link Up Timer handler.
3536 *
3537 * @param pDevIns Pointer to device instance structure.
3538 * @param pTimer Pointer to the timer.
3539 * @param pvUser NULL.
3540 * @thread EMT
3541 */
3542static DECLCALLBACK(void) e1kR3LinkUpTimer(PPDMDEVINS pDevIns, PTMTIMER pTimer, void *pvUser)
3543{
3544 RT_NOREF(pTimer);
3545 PE1KSTATE pThis = (PE1KSTATE)pvUser;
3546 PE1KSTATECC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PE1KSTATECC);
3547
3548 /*
3549 * This can happen if we set the link status to down when the Link up timer was
3550 * already armed (shortly after e1kLoadDone() or when the cable was disconnected
3551 * and connect+disconnect the cable very quick. Moreover, 82543GC triggers LSC
3552 * on reset even if the cable is unplugged (see @bugref{8942}).
3553 */
3554 if (pThis->fCableConnected)
3555 {
3556 /* 82543GC does not have an internal PHY */
3557 if (pThis->eChip == E1K_CHIP_82543GC || (CTRL & CTRL_SLU))
3558 e1kR3LinkUp(pDevIns, pThis, pThisCC);
3559 }
3560# ifdef E1K_LSC_ON_RESET
3561 else if (pThis->eChip == E1K_CHIP_82543GC)
3562 e1kR3LinkDown(pDevIns, pThis, pThisCC);
3563# endif /* E1K_LSC_ON_RESET */
3564}
3565
3566#endif /* IN_RING3 */
3567
3568/**
3569 * Sets up the GSO context according to the TSE new context descriptor.
3570 *
3571 * @param pGso The GSO context to setup.
3572 * @param pCtx The context descriptor.
3573 */
3574DECLINLINE(void) e1kSetupGsoCtx(PPDMNETWORKGSO pGso, E1KTXCTX const *pCtx)
3575{
3576 pGso->u8Type = PDMNETWORKGSOTYPE_INVALID;
3577
3578 /*
3579 * See if the context descriptor describes something that could be TCP or
3580 * UDP over IPv[46].
3581 */
3582 /* Check the header ordering and spacing: 1. Ethernet, 2. IP, 3. TCP/UDP. */
3583 if (RT_UNLIKELY( pCtx->ip.u8CSS < sizeof(RTNETETHERHDR) ))
3584 {
3585 E1kLog(("e1kSetupGsoCtx: IPCSS=%#x\n", pCtx->ip.u8CSS));
3586 return;
3587 }
3588 if (RT_UNLIKELY( pCtx->tu.u8CSS < (size_t)pCtx->ip.u8CSS + (pCtx->dw2.fIP ? RTNETIPV4_MIN_LEN : RTNETIPV6_MIN_LEN) ))
3589 {
3590 E1kLog(("e1kSetupGsoCtx: TUCSS=%#x\n", pCtx->tu.u8CSS));
3591 return;
3592 }
3593 if (RT_UNLIKELY( pCtx->dw2.fTCP
3594 ? pCtx->dw3.u8HDRLEN < (size_t)pCtx->tu.u8CSS + RTNETTCP_MIN_LEN
3595 : pCtx->dw3.u8HDRLEN != (size_t)pCtx->tu.u8CSS + RTNETUDP_MIN_LEN ))
3596 {
3597 E1kLog(("e1kSetupGsoCtx: HDRLEN=%#x TCP=%d\n", pCtx->dw3.u8HDRLEN, pCtx->dw2.fTCP));
3598 return;
3599 }
3600
3601 /* The end of the TCP/UDP checksum should stop at the end of the packet or at least after the headers. */
3602 if (RT_UNLIKELY( pCtx->tu.u16CSE > 0 && pCtx->tu.u16CSE <= pCtx->dw3.u8HDRLEN ))
3603 {
3604 E1kLog(("e1kSetupGsoCtx: TUCSE=%#x HDRLEN=%#x\n", pCtx->tu.u16CSE, pCtx->dw3.u8HDRLEN));
3605 return;
3606 }
3607
3608 /* IPv4 checksum offset. */
3609 if (RT_UNLIKELY( pCtx->dw2.fIP && (size_t)pCtx->ip.u8CSO - pCtx->ip.u8CSS != RT_UOFFSETOF(RTNETIPV4, ip_sum) ))
3610 {
3611 E1kLog(("e1kSetupGsoCtx: IPCSO=%#x IPCSS=%#x\n", pCtx->ip.u8CSO, pCtx->ip.u8CSS));
3612 return;
3613 }
3614
3615 /* TCP/UDP checksum offsets. */
3616 if (RT_UNLIKELY( (size_t)pCtx->tu.u8CSO - pCtx->tu.u8CSS
3617 != ( pCtx->dw2.fTCP
3618 ? RT_UOFFSETOF(RTNETTCP, th_sum)
3619 : RT_UOFFSETOF(RTNETUDP, uh_sum) ) ))
3620 {
3621 E1kLog(("e1kSetupGsoCtx: TUCSO=%#x TUCSS=%#x TCP=%d\n", pCtx->ip.u8CSO, pCtx->ip.u8CSS, pCtx->dw2.fTCP));
3622 return;
3623 }
3624
3625 /*
3626 * Because of internal networking using a 16-bit size field for GSO context
3627 * plus frame, we have to make sure we don't exceed this.
3628 */
3629 if (RT_UNLIKELY( pCtx->dw3.u8HDRLEN + pCtx->dw2.u20PAYLEN > VBOX_MAX_GSO_SIZE ))
3630 {
3631 E1kLog(("e1kSetupGsoCtx: HDRLEN(=%#x) + PAYLEN(=%#x) = %#x, max is %#x\n",
3632 pCtx->dw3.u8HDRLEN, pCtx->dw2.u20PAYLEN, pCtx->dw3.u8HDRLEN + pCtx->dw2.u20PAYLEN, VBOX_MAX_GSO_SIZE));
3633 return;
3634 }
3635
3636 /*
3637 * We're good for now - we'll do more checks when seeing the data.
3638 * So, figure the type of offloading and setup the context.
3639 */
3640 if (pCtx->dw2.fIP)
3641 {
3642 if (pCtx->dw2.fTCP)
3643 {
3644 pGso->u8Type = PDMNETWORKGSOTYPE_IPV4_TCP;
3645 pGso->cbHdrsSeg = pCtx->dw3.u8HDRLEN;
3646 }
3647 else
3648 {
3649 pGso->u8Type = PDMNETWORKGSOTYPE_IPV4_UDP;
3650 pGso->cbHdrsSeg = pCtx->tu.u8CSS; /* IP header only */
3651 }
3652 /** @todo Detect IPv4-IPv6 tunneling (need test setup since linux doesn't do
3653 * this yet it seems)... */
3654 }
3655 else
3656 {
3657 pGso->cbHdrsSeg = pCtx->dw3.u8HDRLEN; /** @todo IPv6 UFO */
3658 if (pCtx->dw2.fTCP)
3659 pGso->u8Type = PDMNETWORKGSOTYPE_IPV6_TCP;
3660 else
3661 pGso->u8Type = PDMNETWORKGSOTYPE_IPV6_UDP;
3662 }
3663 pGso->offHdr1 = pCtx->ip.u8CSS;
3664 pGso->offHdr2 = pCtx->tu.u8CSS;
3665 pGso->cbHdrsTotal = pCtx->dw3.u8HDRLEN;
3666 pGso->cbMaxSeg = pCtx->dw3.u16MSS + (pGso->u8Type == PDMNETWORKGSOTYPE_IPV4_UDP ? pGso->offHdr2 : 0);
3667 Assert(PDMNetGsoIsValid(pGso, sizeof(*pGso), pGso->cbMaxSeg * 5));
3668 E1kLog2(("e1kSetupGsoCtx: mss=%#x hdr=%#x hdrseg=%#x hdr1=%#x hdr2=%#x %s\n",
3669 pGso->cbMaxSeg, pGso->cbHdrsTotal, pGso->cbHdrsSeg, pGso->offHdr1, pGso->offHdr2, PDMNetGsoTypeName((PDMNETWORKGSOTYPE)pGso->u8Type) ));
3670}
3671
3672/**
3673 * Checks if we can use GSO processing for the current TSE frame.
3674 *
3675 * @param pThis The device state structure.
3676 * @param pGso The GSO context.
3677 * @param pData The first data descriptor of the frame.
3678 * @param pCtx The TSO context descriptor.
3679 */
3680DECLINLINE(bool) e1kCanDoGso(PE1KSTATE pThis, PCPDMNETWORKGSO pGso, E1KTXDAT const *pData, E1KTXCTX const *pCtx)
3681{
3682 if (!pData->cmd.fTSE)
3683 {
3684 E1kLog2(("e1kCanDoGso: !TSE\n"));
3685 return false;
3686 }
3687 if (pData->cmd.fVLE) /** @todo VLAN tagging. */
3688 {
3689 E1kLog(("e1kCanDoGso: VLE\n"));
3690 return false;
3691 }
3692 if (RT_UNLIKELY(!pThis->fGSOEnabled))
3693 {
3694 E1kLog3(("e1kCanDoGso: GSO disabled via CFGM\n"));
3695 return false;
3696 }
3697
3698 switch ((PDMNETWORKGSOTYPE)pGso->u8Type)
3699 {
3700 case PDMNETWORKGSOTYPE_IPV4_TCP:
3701 case PDMNETWORKGSOTYPE_IPV4_UDP:
3702 if (!pData->dw3.fIXSM)
3703 {
3704 E1kLog(("e1kCanDoGso: !IXSM (IPv4)\n"));
3705 return false;
3706 }
3707 if (!pData->dw3.fTXSM)
3708 {
3709 E1kLog(("e1kCanDoGso: !TXSM (IPv4)\n"));
3710 return false;
3711 }
3712 /** @todo what more check should we perform here? Ethernet frame type? */
3713 E1kLog2(("e1kCanDoGso: OK, IPv4\n"));
3714 return true;
3715
3716 case PDMNETWORKGSOTYPE_IPV6_TCP:
3717 case PDMNETWORKGSOTYPE_IPV6_UDP:
3718 if (pData->dw3.fIXSM && pCtx->ip.u8CSO)
3719 {
3720 E1kLog(("e1kCanDoGso: IXSM (IPv6)\n"));
3721 return false;
3722 }
3723 if (!pData->dw3.fTXSM)
3724 {
3725 E1kLog(("e1kCanDoGso: TXSM (IPv6)\n"));
3726 return false;
3727 }
3728 /** @todo what more check should we perform here? Ethernet frame type? */
3729 E1kLog2(("e1kCanDoGso: OK, IPv4\n"));
3730 return true;
3731
3732 default:
3733 Assert(pGso->u8Type == PDMNETWORKGSOTYPE_INVALID);
3734 E1kLog2(("e1kCanDoGso: e1kSetupGsoCtx failed\n"));
3735 return false;
3736 }
3737}
3738
3739/**
3740 * Frees the current xmit buffer.
3741 *
3742 * @param pThis The device state structure.
3743 */
3744static void e1kXmitFreeBuf(PE1KSTATE pThis, PE1KSTATECC pThisCC)
3745{
3746 PPDMSCATTERGATHER pSg = pThisCC->CTX_SUFF(pTxSg);
3747 if (pSg)
3748 {
3749 pThisCC->CTX_SUFF(pTxSg) = NULL;
3750
3751 if (pSg->pvAllocator != pThis)
3752 {
3753 PPDMINETWORKUP pDrv = pThisCC->CTX_SUFF(pDrv);
3754 if (pDrv)
3755 pDrv->pfnFreeBuf(pDrv, pSg);
3756 }
3757 else
3758 {
3759 /* loopback */
3760 AssertCompileMemberSize(E1KSTATE, uTxFallback.Sg, 8 * sizeof(size_t));
3761 Assert(pSg->fFlags == (PDMSCATTERGATHER_FLAGS_MAGIC | PDMSCATTERGATHER_FLAGS_OWNER_3));
3762 pSg->fFlags = 0;
3763 pSg->pvAllocator = NULL;
3764 }
3765 }
3766}
3767
3768#ifndef E1K_WITH_TXD_CACHE
3769/**
3770 * Allocates an xmit buffer.
3771 *
3772 * @returns See PDMINETWORKUP::pfnAllocBuf.
3773 * @param pThis The device state structure.
3774 * @param cbMin The minimum frame size.
3775 * @param fExactSize Whether cbMin is exact or if we have to max it
3776 * out to the max MTU size.
3777 * @param fGso Whether this is a GSO frame or not.
3778 */
3779DECLINLINE(int) e1kXmitAllocBuf(PE1KSTATE pThis, PE1KSTATECC pThisCC, size_t cbMin, bool fExactSize, bool fGso)
3780{
3781 /* Adjust cbMin if necessary. */
3782 if (!fExactSize)
3783 cbMin = RT_MAX(cbMin, E1K_MAX_TX_PKT_SIZE);
3784
3785 /* Deal with existing buffer (descriptor screw up, reset, etc). */
3786 if (RT_UNLIKELY(pThisCC->CTX_SUFF(pTxSg)))
3787 e1kXmitFreeBuf(pThis, pThisCC);
3788 Assert(pThisCC->CTX_SUFF(pTxSg) == NULL);
3789
3790 /*
3791 * Allocate the buffer.
3792 */
3793 PPDMSCATTERGATHER pSg;
3794 if (RT_LIKELY(GET_BITS(RCTL, LBM) != RCTL_LBM_TCVR))
3795 {
3796 PPDMINETWORKUP pDrv = pThisCC->CTX_SUFF(pDrv);
3797 if (RT_UNLIKELY(!pDrv))
3798 return VERR_NET_DOWN;
3799 int rc = pDrv->pfnAllocBuf(pDrv, cbMin, fGso ? &pThis->GsoCtx : NULL, &pSg);
3800 if (RT_FAILURE(rc))
3801 {
3802 /* Suspend TX as we are out of buffers atm */
3803 STATUS |= STATUS_TXOFF;
3804 return rc;
3805 }
3806 }
3807 else
3808 {
3809 /* Create a loopback using the fallback buffer and preallocated SG. */
3810 AssertCompileMemberSize(E1KSTATE, uTxFallback.Sg, 8 * sizeof(size_t));
3811 pSg = &pThis->uTxFallback.Sg;
3812 pSg->fFlags = PDMSCATTERGATHER_FLAGS_MAGIC | PDMSCATTERGATHER_FLAGS_OWNER_3;
3813 pSg->cbUsed = 0;
3814 pSg->cbAvailable = 0;
3815 pSg->pvAllocator = pThis;
3816 pSg->pvUser = NULL; /* No GSO here. */
3817 pSg->cSegs = 1;
3818 pSg->aSegs[0].pvSeg = pThis->aTxPacketFallback;
3819 pSg->aSegs[0].cbSeg = sizeof(pThis->aTxPacketFallback);
3820 }
3821
3822 pThisCC->CTX_SUFF(pTxSg) = pSg;
3823 return VINF_SUCCESS;
3824}
3825#else /* E1K_WITH_TXD_CACHE */
3826/**
3827 * Allocates an xmit buffer.
3828 *
3829 * @returns See PDMINETWORKUP::pfnAllocBuf.
3830 * @param pThis The device state structure.
3831 * @param cbMin The minimum frame size.
3832 * @param fExactSize Whether cbMin is exact or if we have to max it
3833 * out to the max MTU size.
3834 * @param fGso Whether this is a GSO frame or not.
3835 */
3836DECLINLINE(int) e1kXmitAllocBuf(PE1KSTATE pThis, PE1KSTATECC pThisCC, bool fGso)
3837{
3838 /* Deal with existing buffer (descriptor screw up, reset, etc). */
3839 if (RT_UNLIKELY(pThisCC->CTX_SUFF(pTxSg)))
3840 e1kXmitFreeBuf(pThis, pThisCC);
3841 Assert(pThisCC->CTX_SUFF(pTxSg) == NULL);
3842
3843 /*
3844 * Allocate the buffer.
3845 */
3846 PPDMSCATTERGATHER pSg;
3847 if (RT_LIKELY(GET_BITS(RCTL, LBM) != RCTL_LBM_TCVR))
3848 {
3849 if (pThis->cbTxAlloc == 0)
3850 {
3851 /* Zero packet, no need for the buffer */
3852 return VINF_SUCCESS;
3853 }
3854 if (fGso && pThis->GsoCtx.u8Type == PDMNETWORKGSOTYPE_INVALID)
3855 {
3856 E1kLog3(("Invalid GSO context, won't allocate this packet, cb=%u %s%s\n",
3857 pThis->cbTxAlloc, pThis->fVTag ? "VLAN " : "", pThis->fGSO ? "GSO " : ""));
3858 /* No valid GSO context is available, ignore this packet. */
3859 pThis->cbTxAlloc = 0;
3860 return VINF_SUCCESS;
3861 }
3862
3863 PPDMINETWORKUP pDrv = pThisCC->CTX_SUFF(pDrv);
3864 if (RT_UNLIKELY(!pDrv))
3865 return VERR_NET_DOWN;
3866 int rc = pDrv->pfnAllocBuf(pDrv, pThis->cbTxAlloc, fGso ? &pThis->GsoCtx : NULL, &pSg);
3867 if (RT_FAILURE(rc))
3868 {
3869 /* Suspend TX as we are out of buffers atm */
3870 STATUS |= STATUS_TXOFF;
3871 return rc;
3872 }
3873 E1kLog3(("%s Allocated buffer for TX packet: cb=%u %s%s\n",
3874 pThis->szPrf, pThis->cbTxAlloc,
3875 pThis->fVTag ? "VLAN " : "",
3876 pThis->fGSO ? "GSO " : ""));
3877 }
3878 else
3879 {
3880 /* Create a loopback using the fallback buffer and preallocated SG. */
3881 AssertCompileMemberSize(E1KSTATE, uTxFallback.Sg, 8 * sizeof(size_t));
3882 pSg = &pThis->uTxFallback.Sg;
3883 pSg->fFlags = PDMSCATTERGATHER_FLAGS_MAGIC | PDMSCATTERGATHER_FLAGS_OWNER_3;
3884 pSg->cbUsed = 0;
3885 pSg->cbAvailable = sizeof(pThis->aTxPacketFallback);
3886 pSg->pvAllocator = pThis;
3887 pSg->pvUser = NULL; /* No GSO here. */
3888 pSg->cSegs = 1;
3889 pSg->aSegs[0].pvSeg = pThis->aTxPacketFallback;
3890 pSg->aSegs[0].cbSeg = sizeof(pThis->aTxPacketFallback);
3891 }
3892 pThis->cbTxAlloc = 0;
3893
3894 pThisCC->CTX_SUFF(pTxSg) = pSg;
3895 return VINF_SUCCESS;
3896}
3897#endif /* E1K_WITH_TXD_CACHE */
3898
3899/**
3900 * Checks if it's a GSO buffer or not.
3901 *
3902 * @returns true / false.
3903 * @param pTxSg The scatter / gather buffer.
3904 */
3905DECLINLINE(bool) e1kXmitIsGsoBuf(PDMSCATTERGATHER const *pTxSg)
3906{
3907#if 0
3908 if (!pTxSg)
3909 E1kLog(("e1kXmitIsGsoBuf: pTxSG is NULL\n"));
3910 if (pTxSg && pTxSg->pvUser)
3911 E1kLog(("e1kXmitIsGsoBuf: pvUser is NULL\n"));
3912#endif
3913 return pTxSg && pTxSg->pvUser /* GSO indicator */;
3914}
3915
3916#ifndef E1K_WITH_TXD_CACHE
3917/**
3918 * Load transmit descriptor from guest memory.
3919 *
3920 * @param pDevIns The device instance.
3921 * @param pDesc Pointer to descriptor union.
3922 * @param addr Physical address in guest context.
3923 * @thread E1000_TX
3924 */
3925DECLINLINE(void) e1kLoadDesc(PPDMDEVINS pDevIns, E1KTXDESC *pDesc, RTGCPHYS addr)
3926{
3927 PDMDevHlpPhysRead(pDevIns, addr, pDesc, sizeof(E1KTXDESC));
3928}
3929#else /* E1K_WITH_TXD_CACHE */
3930/**
3931 * Load transmit descriptors from guest memory.
3932 *
3933 * We need two physical reads in case the tail wrapped around the end of TX
3934 * descriptor ring.
3935 *
3936 * @returns the actual number of descriptors fetched.
3937 * @param pDevIns The device instance.
3938 * @param pThis The device state structure.
3939 * @thread E1000_TX
3940 */
3941DECLINLINE(unsigned) e1kTxDLoadMore(PPDMDEVINS pDevIns, PE1KSTATE pThis)
3942{
3943 Assert(pThis->iTxDCurrent == 0);
3944 /* We've already loaded pThis->nTxDFetched descriptors past TDH. */
3945 unsigned nDescsAvailable = e1kGetTxLen(pThis) - pThis->nTxDFetched;
3946 /* The following two lines ensure that pThis->nTxDFetched never overflows. */
3947 AssertCompile(E1K_TXD_CACHE_SIZE < (256 * sizeof(pThis->nTxDFetched)));
3948 unsigned nDescsToFetch = RT_MIN(nDescsAvailable, E1K_TXD_CACHE_SIZE - pThis->nTxDFetched);
3949 unsigned nDescsTotal = TDLEN / sizeof(E1KTXDESC);
3950 unsigned nFirstNotLoaded = (TDH + pThis->nTxDFetched) % nDescsTotal;
3951 unsigned nDescsInSingleRead = RT_MIN(nDescsToFetch, nDescsTotal - nFirstNotLoaded);
3952 E1kLog3(("%s e1kTxDLoadMore: nDescsAvailable=%u nDescsToFetch=%u nDescsTotal=%u nFirstNotLoaded=0x%x nDescsInSingleRead=%u\n",
3953 pThis->szPrf, nDescsAvailable, nDescsToFetch, nDescsTotal,
3954 nFirstNotLoaded, nDescsInSingleRead));
3955 if (nDescsToFetch == 0)
3956 return 0;
3957 E1KTXDESC* pFirstEmptyDesc = &pThis->aTxDescriptors[pThis->nTxDFetched];
3958 PDMDevHlpPhysRead(pDevIns,
3959 ((uint64_t)TDBAH << 32) + TDBAL + nFirstNotLoaded * sizeof(E1KTXDESC),
3960 pFirstEmptyDesc, nDescsInSingleRead * sizeof(E1KTXDESC));
3961 E1kLog3(("%s Fetched %u TX descriptors at %08x%08x(0x%x), TDLEN=%08x, TDH=%08x, TDT=%08x\n",
3962 pThis->szPrf, nDescsInSingleRead,
3963 TDBAH, TDBAL + TDH * sizeof(E1KTXDESC),
3964 nFirstNotLoaded, TDLEN, TDH, TDT));
3965 if (nDescsToFetch > nDescsInSingleRead)
3966 {
3967 PDMDevHlpPhysRead(pDevIns,
3968 ((uint64_t)TDBAH << 32) + TDBAL,
3969 pFirstEmptyDesc + nDescsInSingleRead,
3970 (nDescsToFetch - nDescsInSingleRead) * sizeof(E1KTXDESC));
3971 E1kLog3(("%s Fetched %u TX descriptors at %08x%08x\n",
3972 pThis->szPrf, nDescsToFetch - nDescsInSingleRead,
3973 TDBAH, TDBAL));
3974 }
3975 pThis->nTxDFetched += (uint8_t)nDescsToFetch;
3976 return nDescsToFetch;
3977}
3978
3979/**
3980 * Load transmit descriptors from guest memory only if there are no loaded
3981 * descriptors.
3982 *
3983 * @returns true if there are descriptors in cache.
3984 * @param pDevIns The device instance.
3985 * @param pThis The device state structure.
3986 * @thread E1000_TX
3987 */
3988DECLINLINE(bool) e1kTxDLazyLoad(PPDMDEVINS pDevIns, PE1KSTATE pThis)
3989{
3990 if (pThis->nTxDFetched == 0)
3991 return e1kTxDLoadMore(pDevIns, pThis) != 0;
3992 return true;
3993}
3994#endif /* E1K_WITH_TXD_CACHE */
3995
3996/**
3997 * Write back transmit descriptor to guest memory.
3998 *
3999 * @param pDevIns The device instance.
4000 * @param pThis The device state structure.
4001 * @param pDesc Pointer to descriptor union.
4002 * @param addr Physical address in guest context.
4003 * @thread E1000_TX
4004 */
4005DECLINLINE(void) e1kWriteBackDesc(PPDMDEVINS pDevIns, PE1KSTATE pThis, E1KTXDESC *pDesc, RTGCPHYS addr)
4006{
4007 /* Only the last half of the descriptor has to be written back. */
4008 e1kPrintTDesc(pThis, pDesc, "^^^");
4009 PDMDevHlpPCIPhysWrite(pDevIns, addr, pDesc, sizeof(E1KTXDESC));
4010}
4011
4012/**
4013 * Transmit complete frame.
4014 *
4015 * @remarks We skip the FCS since we're not responsible for sending anything to
4016 * a real ethernet wire.
4017 *
4018 * @param pDevIns The device instance.
4019 * @param pThis The device state structure.
4020 * @param pThisCC The current context instance data.
4021 * @param fOnWorkerThread Whether we're on a worker thread or an EMT.
4022 * @thread E1000_TX
4023 */
4024static void e1kTransmitFrame(PPDMDEVINS pDevIns, PE1KSTATE pThis, PE1KSTATECC pThisCC, bool fOnWorkerThread)
4025{
4026 PPDMSCATTERGATHER pSg = pThisCC->CTX_SUFF(pTxSg);
4027 uint32_t cbFrame = pSg ? (uint32_t)pSg->cbUsed : 0;
4028 Assert(!pSg || pSg->cSegs == 1);
4029
4030 if (cbFrame > 70) /* unqualified guess */
4031 pThis->led.Asserted.s.fWriting = pThis->led.Actual.s.fWriting = 1;
4032
4033#ifdef E1K_INT_STATS
4034 if (cbFrame <= 1514)
4035 E1K_INC_ISTAT_CNT(pThis->uStatTx1514);
4036 else if (cbFrame <= 2962)
4037 E1K_INC_ISTAT_CNT(pThis->uStatTx2962);
4038 else if (cbFrame <= 4410)
4039 E1K_INC_ISTAT_CNT(pThis->uStatTx4410);
4040 else if (cbFrame <= 5858)
4041 E1K_INC_ISTAT_CNT(pThis->uStatTx5858);
4042 else if (cbFrame <= 7306)
4043 E1K_INC_ISTAT_CNT(pThis->uStatTx7306);
4044 else if (cbFrame <= 8754)
4045 E1K_INC_ISTAT_CNT(pThis->uStatTx8754);
4046 else if (cbFrame <= 16384)
4047 E1K_INC_ISTAT_CNT(pThis->uStatTx16384);
4048 else if (cbFrame <= 32768)
4049 E1K_INC_ISTAT_CNT(pThis->uStatTx32768);
4050 else
4051 E1K_INC_ISTAT_CNT(pThis->uStatTxLarge);
4052#endif /* E1K_INT_STATS */
4053
4054 /* Add VLAN tag */
4055 if (cbFrame > 12 && pThis->fVTag)
4056 {
4057 E1kLog3(("%s Inserting VLAN tag %08x\n",
4058 pThis->szPrf, RT_BE2H_U16((uint16_t)VET) | (RT_BE2H_U16(pThis->u16VTagTCI) << 16)));
4059 memmove((uint8_t*)pSg->aSegs[0].pvSeg + 16, (uint8_t*)pSg->aSegs[0].pvSeg + 12, cbFrame - 12);
4060 *((uint32_t*)pSg->aSegs[0].pvSeg + 3) = RT_BE2H_U16((uint16_t)VET) | (RT_BE2H_U16(pThis->u16VTagTCI) << 16);
4061 pSg->cbUsed += 4;
4062 cbFrame += 4;
4063 Assert(pSg->cbUsed == cbFrame);
4064 Assert(pSg->cbUsed <= pSg->cbAvailable);
4065 }
4066/* E1kLog2(("%s < < < Outgoing packet. Dump follows: > > >\n"
4067 "%.*Rhxd\n"
4068 "%s < < < < < < < < < < < < < End of dump > > > > > > > > > > > >\n",
4069 pThis->szPrf, cbFrame, pSg->aSegs[0].pvSeg, pThis->szPrf));*/
4070
4071 /* Update the stats */
4072 E1K_INC_CNT32(TPT);
4073 E1K_ADD_CNT64(TOTL, TOTH, cbFrame);
4074 E1K_INC_CNT32(GPTC);
4075 if (pSg && e1kIsBroadcast(pSg->aSegs[0].pvSeg))
4076 E1K_INC_CNT32(BPTC);
4077 else if (pSg && e1kIsMulticast(pSg->aSegs[0].pvSeg))
4078 E1K_INC_CNT32(MPTC);
4079 /* Update octet transmit counter */
4080 E1K_ADD_CNT64(GOTCL, GOTCH, cbFrame);
4081 if (pThisCC->CTX_SUFF(pDrv))
4082 STAM_REL_COUNTER_ADD(&pThis->StatTransmitBytes, cbFrame);
4083 if (cbFrame == 64)
4084 E1K_INC_CNT32(PTC64);
4085 else if (cbFrame < 128)
4086 E1K_INC_CNT32(PTC127);
4087 else if (cbFrame < 256)
4088 E1K_INC_CNT32(PTC255);
4089 else if (cbFrame < 512)
4090 E1K_INC_CNT32(PTC511);
4091 else if (cbFrame < 1024)
4092 E1K_INC_CNT32(PTC1023);
4093 else
4094 E1K_INC_CNT32(PTC1522);
4095
4096 E1K_INC_ISTAT_CNT(pThis->uStatTxFrm);
4097
4098 /*
4099 * Dump and send the packet.
4100 */
4101 int rc = VERR_NET_DOWN;
4102 if (pSg && pSg->pvAllocator != pThis)
4103 {
4104 e1kPacketDump(pDevIns, pThis, (uint8_t const *)pSg->aSegs[0].pvSeg, cbFrame, "--> Outgoing");
4105
4106 pThisCC->CTX_SUFF(pTxSg) = NULL;
4107 PPDMINETWORKUP pDrv = pThisCC->CTX_SUFF(pDrv);
4108 if (pDrv)
4109 {
4110 /* Release critical section to avoid deadlock in CanReceive */
4111 //e1kCsLeave(pThis);
4112 STAM_PROFILE_START(&pThis->CTX_SUFF_Z(StatTransmitSend), a);
4113 rc = pDrv->pfnSendBuf(pDrv, pSg, fOnWorkerThread);
4114 STAM_PROFILE_STOP(&pThis->CTX_SUFF_Z(StatTransmitSend), a);
4115 //e1kCsEnter(pThis, RT_SRC_POS);
4116 }
4117 }
4118 else if (pSg)
4119 {
4120 Assert(pSg->aSegs[0].pvSeg == pThis->aTxPacketFallback);
4121 e1kPacketDump(pDevIns, pThis, (uint8_t const *)pSg->aSegs[0].pvSeg, cbFrame, "--> Loopback");
4122
4123 /** @todo do we actually need to check that we're in loopback mode here? */
4124 if (GET_BITS(RCTL, LBM) == RCTL_LBM_TCVR)
4125 {
4126 E1KRXDST status;
4127 RT_ZERO(status);
4128 status.fPIF = true;
4129 e1kHandleRxPacket(pDevIns, pThis, pSg->aSegs[0].pvSeg, cbFrame, status);
4130 rc = VINF_SUCCESS;
4131 }
4132 e1kXmitFreeBuf(pThis, pThisCC);
4133 }
4134 else
4135 rc = VERR_NET_DOWN;
4136 if (RT_FAILURE(rc))
4137 {
4138 E1kLogRel(("E1000: ERROR! pfnSend returned %Rrc\n", rc));
4139 /** @todo handle VERR_NET_DOWN and VERR_NET_NO_BUFFER_SPACE. Signal error ? */
4140 }
4141
4142 pThis->led.Actual.s.fWriting = 0;
4143}
4144
4145/**
4146 * Compute and write internet checksum (e1kCSum16) at the specified offset.
4147 *
4148 * @param pThis The device state structure.
4149 * @param pPkt Pointer to the packet.
4150 * @param u16PktLen Total length of the packet.
4151 * @param cso Offset in packet to write checksum at.
4152 * @param css Offset in packet to start computing
4153 * checksum from.
4154 * @param cse Offset in packet to stop computing
4155 * checksum at.
4156 * @thread E1000_TX
4157 */
4158static void e1kInsertChecksum(PE1KSTATE pThis, uint8_t *pPkt, uint16_t u16PktLen, uint8_t cso, uint8_t css, uint16_t cse)
4159{
4160 RT_NOREF1(pThis);
4161
4162 if (css >= u16PktLen)
4163 {
4164 E1kLog2(("%s css(%X) is greater than packet length-1(%X), checksum is not inserted\n",
4165 pThis->szPrf, cso, u16PktLen));
4166 return;
4167 }
4168
4169 if (cso >= u16PktLen - 1)
4170 {
4171 E1kLog2(("%s cso(%X) is greater than packet length-2(%X), checksum is not inserted\n",
4172 pThis->szPrf, cso, u16PktLen));
4173 return;
4174 }
4175
4176 if (cse == 0 || cse >= u16PktLen)
4177 cse = u16PktLen - 1;
4178 else if (cse < css)
4179 {
4180 E1kLog2(("%s css(%X) is greater than cse(%X), checksum is not inserted\n",
4181 pThis->szPrf, css, cse));
4182 return;
4183 }
4184
4185 uint16_t u16ChkSum = e1kCSum16(pPkt + css, cse - css + 1);
4186 E1kLog2(("%s Inserting csum: %04X at %02X, old value: %04X\n", pThis->szPrf,
4187 u16ChkSum, cso, *(uint16_t*)(pPkt + cso)));
4188 *(uint16_t*)(pPkt + cso) = u16ChkSum;
4189}
4190
4191/**
4192 * Add a part of descriptor's buffer to transmit frame.
4193 *
4194 * @remarks data.u64BufAddr is used unconditionally for both data
4195 * and legacy descriptors since it is identical to
4196 * legacy.u64BufAddr.
4197 *
4198 * @param pDevIns The device instance.
4199 * @param pThis The device state structure.
4200 * @param pDesc Pointer to the descriptor to transmit.
4201 * @param u16Len Length of buffer to the end of segment.
4202 * @param fSend Force packet sending.
4203 * @param fOnWorkerThread Whether we're on a worker thread or an EMT.
4204 * @thread E1000_TX
4205 */
4206#ifndef E1K_WITH_TXD_CACHE
4207static void e1kFallbackAddSegment(PPDMDEVINS pDevIns, PE1KSTATE pThis, RTGCPHYS PhysAddr, uint16_t u16Len, bool fSend, bool fOnWorkerThread)
4208{
4209 PE1KSTATECC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PE1KSTATECC);
4210 /* TCP header being transmitted */
4211 struct E1kTcpHeader *pTcpHdr = (struct E1kTcpHeader *)(pThis->aTxPacketFallback + pThis->contextTSE.tu.u8CSS);
4212 /* IP header being transmitted */
4213 struct E1kIpHeader *pIpHdr = (struct E1kIpHeader *)(pThis->aTxPacketFallback + pThis->contextTSE.ip.u8CSS);
4214
4215 E1kLog3(("%s e1kFallbackAddSegment: Length=%x, remaining payload=%x, header=%x, send=%RTbool\n",
4216 pThis->szPrf, u16Len, pThis->u32PayRemain, pThis->u16HdrRemain, fSend));
4217 Assert(pThis->u32PayRemain + pThis->u16HdrRemain > 0);
4218
4219 PDMDevHlpPhysRead(pDevIns, PhysAddr, pThis->aTxPacketFallback + pThis->u16TxPktLen, u16Len);
4220 E1kLog3(("%s Dump of the segment:\n"
4221 "%.*Rhxd\n"
4222 "%s --- End of dump ---\n",
4223 pThis->szPrf, u16Len, pThis->aTxPacketFallback + pThis->u16TxPktLen, pThis->szPrf));
4224 pThis->u16TxPktLen += u16Len;
4225 E1kLog3(("%s e1kFallbackAddSegment: pThis->u16TxPktLen=%x\n",
4226 pThis->szPrf, pThis->u16TxPktLen));
4227 if (pThis->u16HdrRemain > 0)
4228 {
4229 /* The header was not complete, check if it is now */
4230 if (u16Len >= pThis->u16HdrRemain)
4231 {
4232 /* The rest is payload */
4233 u16Len -= pThis->u16HdrRemain;
4234 pThis->u16HdrRemain = 0;
4235 /* Save partial checksum and flags */
4236 pThis->u32SavedCsum = pTcpHdr->chksum;
4237 pThis->u16SavedFlags = pTcpHdr->hdrlen_flags;
4238 /* Clear FIN and PSH flags now and set them only in the last segment */
4239 pTcpHdr->hdrlen_flags &= ~htons(E1K_TCP_FIN | E1K_TCP_PSH);
4240 }
4241 else
4242 {
4243 /* Still not */
4244 pThis->u16HdrRemain -= u16Len;
4245 E1kLog3(("%s e1kFallbackAddSegment: Header is still incomplete, 0x%x bytes remain.\n",
4246 pThis->szPrf, pThis->u16HdrRemain));
4247 return;
4248 }
4249 }
4250
4251 pThis->u32PayRemain -= u16Len;
4252
4253 if (fSend)
4254 {
4255 /* Leave ethernet header intact */
4256 /* IP Total Length = payload + headers - ethernet header */
4257 pIpHdr->total_len = htons(pThis->u16TxPktLen - pThis->contextTSE.ip.u8CSS);
4258 E1kLog3(("%s e1kFallbackAddSegment: End of packet, pIpHdr->total_len=%x\n",
4259 pThis->szPrf, ntohs(pIpHdr->total_len)));
4260 /* Update IP Checksum */
4261 pIpHdr->chksum = 0;
4262 e1kInsertChecksum(pThis, pThis->aTxPacketFallback, pThis->u16TxPktLen,
4263 pThis->contextTSE.ip.u8CSO,
4264 pThis->contextTSE.ip.u8CSS,
4265 pThis->contextTSE.ip.u16CSE);
4266
4267 /* Update TCP flags */
4268 /* Restore original FIN and PSH flags for the last segment */
4269 if (pThis->u32PayRemain == 0)
4270 {
4271 pTcpHdr->hdrlen_flags = pThis->u16SavedFlags;
4272 E1K_INC_CNT32(TSCTC);
4273 }
4274 /* Add TCP length to partial pseudo header sum */
4275 uint32_t csum = pThis->u32SavedCsum
4276 + htons(pThis->u16TxPktLen - pThis->contextTSE.tu.u8CSS);
4277 while (csum >> 16)
4278 csum = (csum >> 16) + (csum & 0xFFFF);
4279 pTcpHdr->chksum = csum;
4280 /* Compute final checksum */
4281 e1kInsertChecksum(pThis, pThis->aTxPacketFallback, pThis->u16TxPktLen,
4282 pThis->contextTSE.tu.u8CSO,
4283 pThis->contextTSE.tu.u8CSS,
4284 pThis->contextTSE.tu.u16CSE);
4285
4286 /*
4287 * Transmit it. If we've use the SG already, allocate a new one before
4288 * we copy of the data.
4289 */
4290 PPDMSCATTERGATHER pTxSg = pThisCC->CTX_SUFF(pTxSg);
4291 if (!pTxSg)
4292 {
4293 e1kXmitAllocBuf(pThis, pThisCC, pThis->u16TxPktLen + (pThis->fVTag ? 4 : 0), true /*fExactSize*/, false /*fGso*/);
4294 pTxSg = pThisCC->CTX_SUFF(pTxSg);
4295 }
4296 if (pTxSg)
4297 {
4298 Assert(pThis->u16TxPktLen <= pThisCC->CTX_SUFF(pTxSg)->cbAvailable);
4299 Assert(pTxSg->cSegs == 1);
4300 if (pThis->CCCTX_SUFF(pTxSg)->aSegs[0].pvSeg != pThis->aTxPacketFallback)
4301 memcpy(pTxSg->aSegs[0].pvSeg, pThis->aTxPacketFallback, pThis->u16TxPktLen);
4302 pTxSg->cbUsed = pThis->u16TxPktLen;
4303 pTxSg->aSegs[0].cbSeg = pThis->u16TxPktLen;
4304 }
4305 e1kTransmitFrame(pDevIns, pThis, pThisCC, fOnWorkerThread);
4306
4307 /* Update Sequence Number */
4308 pTcpHdr->seqno = htonl(ntohl(pTcpHdr->seqno) + pThis->u16TxPktLen
4309 - pThis->contextTSE.dw3.u8HDRLEN);
4310 /* Increment IP identification */
4311 pIpHdr->ident = htons(ntohs(pIpHdr->ident) + 1);
4312 }
4313}
4314#else /* E1K_WITH_TXD_CACHE */
4315static int e1kFallbackAddSegment(PPDMDEVINS pDevIns, PE1KSTATE pThis, RTGCPHYS PhysAddr, uint16_t u16Len, bool fSend, bool fOnWorkerThread)
4316{
4317 int rc = VINF_SUCCESS;
4318 PE1KSTATECC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PE1KSTATECC);
4319 /* TCP header being transmitted */
4320 struct E1kTcpHeader *pTcpHdr = (struct E1kTcpHeader *)(pThis->aTxPacketFallback + pThis->contextTSE.tu.u8CSS);
4321 /* IP header being transmitted */
4322 struct E1kIpHeader *pIpHdr = (struct E1kIpHeader *)(pThis->aTxPacketFallback + pThis->contextTSE.ip.u8CSS);
4323
4324 E1kLog3(("%s e1kFallbackAddSegment: Length=%x, remaining payload=%x, header=%x, send=%RTbool\n",
4325 pThis->szPrf, u16Len, pThis->u32PayRemain, pThis->u16HdrRemain, fSend));
4326 AssertReturn(pThis->u32PayRemain + pThis->u16HdrRemain > 0, VINF_SUCCESS);
4327
4328 if (pThis->u16TxPktLen + u16Len <= sizeof(pThis->aTxPacketFallback))
4329 PDMDevHlpPhysRead(pDevIns, PhysAddr, pThis->aTxPacketFallback + pThis->u16TxPktLen, u16Len);
4330 else
4331 E1kLog(("%s e1kFallbackAddSegment: writing beyond aTxPacketFallback, u16TxPktLen=%d(0x%x) + u16Len=%d(0x%x) > %d\n",
4332 pThis->szPrf, pThis->u16TxPktLen, pThis->u16TxPktLen, u16Len, u16Len, sizeof(pThis->aTxPacketFallback)));
4333 E1kLog3(("%s Dump of the segment:\n"
4334 "%.*Rhxd\n"
4335 "%s --- End of dump ---\n",
4336 pThis->szPrf, u16Len, pThis->aTxPacketFallback + pThis->u16TxPktLen, pThis->szPrf));
4337 pThis->u16TxPktLen += u16Len;
4338 E1kLog3(("%s e1kFallbackAddSegment: pThis->u16TxPktLen=%x\n",
4339 pThis->szPrf, pThis->u16TxPktLen));
4340 if (pThis->u16HdrRemain > 0)
4341 {
4342 /* The header was not complete, check if it is now */
4343 if (u16Len >= pThis->u16HdrRemain)
4344 {
4345 /* The rest is payload */
4346 u16Len -= pThis->u16HdrRemain;
4347 pThis->u16HdrRemain = 0;
4348 /* Save partial checksum and flags */
4349 pThis->u32SavedCsum = pTcpHdr->chksum;
4350 pThis->u16SavedFlags = pTcpHdr->hdrlen_flags;
4351 /* Clear FIN and PSH flags now and set them only in the last segment */
4352 pTcpHdr->hdrlen_flags &= ~htons(E1K_TCP_FIN | E1K_TCP_PSH);
4353 }
4354 else
4355 {
4356 /* Still not */
4357 pThis->u16HdrRemain -= u16Len;
4358 E1kLog3(("%s e1kFallbackAddSegment: Header is still incomplete, 0x%x bytes remain.\n",
4359 pThis->szPrf, pThis->u16HdrRemain));
4360 return rc;
4361 }
4362 }
4363
4364 if (u16Len > pThis->u32PayRemain)
4365 pThis->u32PayRemain = 0;
4366 else
4367 pThis->u32PayRemain -= u16Len;
4368
4369 if (fSend)
4370 {
4371 /* Leave ethernet header intact */
4372 /* IP Total Length = payload + headers - ethernet header */
4373 pIpHdr->total_len = htons(pThis->u16TxPktLen - pThis->contextTSE.ip.u8CSS);
4374 E1kLog3(("%s e1kFallbackAddSegment: End of packet, pIpHdr->total_len=%x\n",
4375 pThis->szPrf, ntohs(pIpHdr->total_len)));
4376 /* Update IP Checksum */
4377 pIpHdr->chksum = 0;
4378 e1kInsertChecksum(pThis, pThis->aTxPacketFallback, pThis->u16TxPktLen,
4379 pThis->contextTSE.ip.u8CSO,
4380 pThis->contextTSE.ip.u8CSS,
4381 pThis->contextTSE.ip.u16CSE);
4382
4383 /* Update TCP flags */
4384 /* Restore original FIN and PSH flags for the last segment */
4385 if (pThis->u32PayRemain == 0)
4386 {
4387 pTcpHdr->hdrlen_flags = pThis->u16SavedFlags;
4388 E1K_INC_CNT32(TSCTC);
4389 }
4390 /* Add TCP length to partial pseudo header sum */
4391 uint32_t csum = pThis->u32SavedCsum
4392 + htons(pThis->u16TxPktLen - pThis->contextTSE.tu.u8CSS);
4393 while (csum >> 16)
4394 csum = (csum >> 16) + (csum & 0xFFFF);
4395 Assert(csum < 65536);
4396 pTcpHdr->chksum = (uint16_t)csum;
4397 /* Compute final checksum */
4398 e1kInsertChecksum(pThis, pThis->aTxPacketFallback, pThis->u16TxPktLen,
4399 pThis->contextTSE.tu.u8CSO,
4400 pThis->contextTSE.tu.u8CSS,
4401 pThis->contextTSE.tu.u16CSE);
4402
4403 /*
4404 * Transmit it.
4405 */
4406 PPDMSCATTERGATHER pTxSg = pThisCC->CTX_SUFF(pTxSg);
4407 if (pTxSg)
4408 {
4409 /* Make sure the packet fits into the allocated buffer */
4410 size_t cbCopy = RT_MIN(pThis->u16TxPktLen, pThisCC->CTX_SUFF(pTxSg)->cbAvailable);
4411#ifdef DEBUG
4412 if (pThis->u16TxPktLen > pTxSg->cbAvailable)
4413 E1kLog(("%s e1kFallbackAddSegment: truncating packet, u16TxPktLen=%d(0x%x) > cbAvailable=%d(0x%x)\n",
4414 pThis->szPrf, pThis->u16TxPktLen, pThis->u16TxPktLen, pTxSg->cbAvailable, pTxSg->cbAvailable));
4415#endif /* DEBUG */
4416 Assert(pTxSg->cSegs == 1);
4417 if (pTxSg->aSegs[0].pvSeg != pThis->aTxPacketFallback)
4418 memcpy(pTxSg->aSegs[0].pvSeg, pThis->aTxPacketFallback, cbCopy);
4419 pTxSg->cbUsed = cbCopy;
4420 pTxSg->aSegs[0].cbSeg = cbCopy;
4421 }
4422 e1kTransmitFrame(pDevIns, pThis, pThisCC, fOnWorkerThread);
4423
4424 /* Update Sequence Number */
4425 pTcpHdr->seqno = htonl(ntohl(pTcpHdr->seqno) + pThis->u16TxPktLen
4426 - pThis->contextTSE.dw3.u8HDRLEN);
4427 /* Increment IP identification */
4428 pIpHdr->ident = htons(ntohs(pIpHdr->ident) + 1);
4429
4430 /* Allocate new buffer for the next segment. */
4431 if (pThis->u32PayRemain)
4432 {
4433 pThis->cbTxAlloc = RT_MIN(pThis->u32PayRemain,
4434 pThis->contextTSE.dw3.u16MSS)
4435 + pThis->contextTSE.dw3.u8HDRLEN;
4436 /* Do not add VLAN tags to empty packets. */
4437 if (pThis->fVTag && pThis->cbTxAlloc > 0)
4438 pThis->cbTxAlloc += 4;
4439 rc = e1kXmitAllocBuf(pThis, pThisCC, false /* fGSO */);
4440 }
4441 }
4442
4443 return rc;
4444}
4445#endif /* E1K_WITH_TXD_CACHE */
4446
4447#ifndef E1K_WITH_TXD_CACHE
4448/**
4449 * TCP segmentation offloading fallback: Add descriptor's buffer to transmit
4450 * frame.
4451 *
4452 * We construct the frame in the fallback buffer first and the copy it to the SG
4453 * buffer before passing it down to the network driver code.
4454 *
4455 * @returns true if the frame should be transmitted, false if not.
4456 *
4457 * @param pThis The device state structure.
4458 * @param pDesc Pointer to the descriptor to transmit.
4459 * @param cbFragment Length of descriptor's buffer.
4460 * @param fOnWorkerThread Whether we're on a worker thread or an EMT.
4461 * @thread E1000_TX
4462 */
4463static bool e1kFallbackAddToFrame(PE1KSTATE pThis, E1KTXDESC *pDesc, uint32_t cbFragment, bool fOnWorkerThread)
4464{
4465 PPDMSCATTERGATHER pTxSg = pThisCC->CTX_SUFF(pTxSg);
4466 Assert(e1kGetDescType(pDesc) == E1K_DTYP_DATA);
4467 Assert(pDesc->data.cmd.fTSE);
4468 Assert(!e1kXmitIsGsoBuf(pTxSg));
4469
4470 uint16_t u16MaxPktLen = pThis->contextTSE.dw3.u8HDRLEN + pThis->contextTSE.dw3.u16MSS;
4471 Assert(u16MaxPktLen != 0);
4472 Assert(u16MaxPktLen < E1K_MAX_TX_PKT_SIZE);
4473
4474 /*
4475 * Carve out segments.
4476 */
4477 do
4478 {
4479 /* Calculate how many bytes we have left in this TCP segment */
4480 uint32_t cb = u16MaxPktLen - pThis->u16TxPktLen;
4481 if (cb > cbFragment)
4482 {
4483 /* This descriptor fits completely into current segment */
4484 cb = cbFragment;
4485 e1kFallbackAddSegment(pDevIns, pThis, pDesc->data.u64BufAddr, cb, pDesc->data.cmd.fEOP /*fSend*/, fOnWorkerThread);
4486 }
4487 else
4488 {
4489 e1kFallbackAddSegment(pDevIns, pThis, pDesc->data.u64BufAddr, cb, true /*fSend*/, fOnWorkerThread);
4490 /*
4491 * Rewind the packet tail pointer to the beginning of payload,
4492 * so we continue writing right beyond the header.
4493 */
4494 pThis->u16TxPktLen = pThis->contextTSE.dw3.u8HDRLEN;
4495 }
4496
4497 pDesc->data.u64BufAddr += cb;
4498 cbFragment -= cb;
4499 } while (cbFragment > 0);
4500
4501 if (pDesc->data.cmd.fEOP)
4502 {
4503 /* End of packet, next segment will contain header. */
4504 if (pThis->u32PayRemain != 0)
4505 E1K_INC_CNT32(TSCTFC);
4506 pThis->u16TxPktLen = 0;
4507 e1kXmitFreeBuf(pThis, PDMDEVINS_2_DATA_CC(pDevIns, PE1KSTATECC));
4508 }
4509
4510 return false;
4511}
4512#else /* E1K_WITH_TXD_CACHE */
4513/**
4514 * TCP segmentation offloading fallback: Add descriptor's buffer to transmit
4515 * frame.
4516 *
4517 * We construct the frame in the fallback buffer first and the copy it to the SG
4518 * buffer before passing it down to the network driver code.
4519 *
4520 * @returns error code
4521 *
4522 * @param pDevIns The device instance.
4523 * @param pThis The device state structure.
4524 * @param pDesc Pointer to the descriptor to transmit.
4525 * @param cbFragment Length of descriptor's buffer.
4526 * @param fOnWorkerThread Whether we're on a worker thread or an EMT.
4527 * @thread E1000_TX
4528 */
4529static int e1kFallbackAddToFrame(PPDMDEVINS pDevIns, PE1KSTATE pThis, E1KTXDESC *pDesc, bool fOnWorkerThread)
4530{
4531#ifdef VBOX_STRICT
4532 PPDMSCATTERGATHER pTxSg = PDMDEVINS_2_DATA_CC(pDevIns, PE1KSTATECC)->CTX_SUFF(pTxSg);
4533 Assert(e1kGetDescType(pDesc) == E1K_DTYP_DATA);
4534 Assert(pDesc->data.cmd.fTSE);
4535 Assert(!e1kXmitIsGsoBuf(pTxSg));
4536#endif
4537
4538 uint16_t u16MaxPktLen = pThis->contextTSE.dw3.u8HDRLEN + pThis->contextTSE.dw3.u16MSS;
4539 /* We cannot produce empty packets, ignore all TX descriptors (see @bugref{9571}) */
4540 if (u16MaxPktLen == 0)
4541 return VINF_SUCCESS;
4542
4543 /*
4544 * Carve out segments.
4545 */
4546 int rc = VINF_SUCCESS;
4547 do
4548 {
4549 /* Calculate how many bytes we have left in this TCP segment */
4550 uint16_t cb = u16MaxPktLen - pThis->u16TxPktLen;
4551 if (cb > pDesc->data.cmd.u20DTALEN)
4552 {
4553 /* This descriptor fits completely into current segment */
4554 cb = (uint16_t)pDesc->data.cmd.u20DTALEN; /* u20DTALEN at this point is guarantied to fit into 16 bits. */
4555 rc = e1kFallbackAddSegment(pDevIns, pThis, pDesc->data.u64BufAddr, cb, pDesc->data.cmd.fEOP /*fSend*/, fOnWorkerThread);
4556 }
4557 else
4558 {
4559 rc = e1kFallbackAddSegment(pDevIns, pThis, pDesc->data.u64BufAddr, cb, true /*fSend*/, fOnWorkerThread);
4560 /*
4561 * Rewind the packet tail pointer to the beginning of payload,
4562 * so we continue writing right beyond the header.
4563 */
4564 pThis->u16TxPktLen = pThis->contextTSE.dw3.u8HDRLEN;
4565 }
4566
4567 pDesc->data.u64BufAddr += cb;
4568 pDesc->data.cmd.u20DTALEN -= cb;
4569 } while (pDesc->data.cmd.u20DTALEN > 0 && RT_SUCCESS(rc));
4570
4571 if (pDesc->data.cmd.fEOP)
4572 {
4573 /* End of packet, next segment will contain header. */
4574 if (pThis->u32PayRemain != 0)
4575 E1K_INC_CNT32(TSCTFC);
4576 pThis->u16TxPktLen = 0;
4577 e1kXmitFreeBuf(pThis, PDMDEVINS_2_DATA_CC(pDevIns, PE1KSTATECC));
4578 }
4579
4580 return VINF_SUCCESS; /// @todo consider rc;
4581}
4582#endif /* E1K_WITH_TXD_CACHE */
4583
4584
4585/**
4586 * Add descriptor's buffer to transmit frame.
4587 *
4588 * This deals with GSO and normal frames, e1kFallbackAddToFrame deals with the
4589 * TSE frames we cannot handle as GSO.
4590 *
4591 * @returns true on success, false on failure.
4592 *
4593 * @param pDevIns The device instance.
4594 * @param pThisCC The current context instance data.
4595 * @param pThis The device state structure.
4596 * @param PhysAddr The physical address of the descriptor buffer.
4597 * @param cbFragment Length of descriptor's buffer.
4598 * @thread E1000_TX
4599 */
4600static bool e1kAddToFrame(PPDMDEVINS pDevIns, PE1KSTATE pThis, PE1KSTATECC pThisCC, RTGCPHYS PhysAddr, uint32_t cbFragment)
4601{
4602 PPDMSCATTERGATHER pTxSg = pThisCC->CTX_SUFF(pTxSg);
4603 bool const fGso = e1kXmitIsGsoBuf(pTxSg);
4604 uint32_t const cbNewPkt = cbFragment + pThis->u16TxPktLen;
4605
4606 LogFlow(("%s e1kAddToFrame: ENTER cbFragment=%d u16TxPktLen=%d cbUsed=%d cbAvailable=%d fGSO=%s\n",
4607 pThis->szPrf, cbFragment, pThis->u16TxPktLen, pTxSg->cbUsed, pTxSg->cbAvailable,
4608 fGso ? "true" : "false"));
4609 PCPDMNETWORKGSO pGso = (PCPDMNETWORKGSO)pTxSg->pvUser;
4610 if (pGso)
4611 {
4612 if (RT_UNLIKELY(pGso->cbMaxSeg == 0))
4613 {
4614 E1kLog(("%s zero-sized fragments are not allowed\n", pThis->szPrf));
4615 return false;
4616 }
4617 if (RT_UNLIKELY(pGso->u8Type == PDMNETWORKGSOTYPE_IPV4_UDP))
4618 {
4619 E1kLog(("%s UDP fragmentation is no longer supported\n", pThis->szPrf));
4620 return false;
4621 }
4622 }
4623 if (RT_UNLIKELY( !fGso && cbNewPkt > E1K_MAX_TX_PKT_SIZE ))
4624 {
4625 E1kLog(("%s Transmit packet is too large: %u > %u(max)\n", pThis->szPrf, cbNewPkt, E1K_MAX_TX_PKT_SIZE));
4626 return false;
4627 }
4628 if (RT_UNLIKELY( cbNewPkt > pTxSg->cbAvailable ))
4629 {
4630 E1kLog(("%s Transmit packet is too large: %u > %u(max)\n", pThis->szPrf, cbNewPkt, pTxSg->cbAvailable));
4631 return false;
4632 }
4633
4634 if (RT_LIKELY(pTxSg))
4635 {
4636 Assert(pTxSg->cSegs == 1);
4637 if (pTxSg->cbUsed != pThis->u16TxPktLen)
4638 E1kLog(("%s e1kAddToFrame: pTxSg->cbUsed=%d(0x%x) != u16TxPktLen=%d(0x%x)\n",
4639 pThis->szPrf, pTxSg->cbUsed, pTxSg->cbUsed, pThis->u16TxPktLen, pThis->u16TxPktLen));
4640
4641 PDMDevHlpPhysRead(pDevIns, PhysAddr, (uint8_t *)pTxSg->aSegs[0].pvSeg + pThis->u16TxPktLen, cbFragment);
4642
4643 pTxSg->cbUsed = cbNewPkt;
4644 }
4645 pThis->u16TxPktLen = cbNewPkt;
4646
4647 return true;
4648}
4649
4650
4651/**
4652 * Write the descriptor back to guest memory and notify the guest.
4653 *
4654 * @param pThis The device state structure.
4655 * @param pDesc Pointer to the descriptor have been transmitted.
4656 * @param addr Physical address of the descriptor in guest memory.
4657 * @thread E1000_TX
4658 */
4659static void e1kDescReport(PPDMDEVINS pDevIns, PE1KSTATE pThis, E1KTXDESC *pDesc, RTGCPHYS addr)
4660{
4661 /*
4662 * We fake descriptor write-back bursting. Descriptors are written back as they are
4663 * processed.
4664 */
4665 /* Let's pretend we process descriptors. Write back with DD set. */
4666 /*
4667 * Prior to r71586 we tried to accomodate the case when write-back bursts
4668 * are enabled without actually implementing bursting by writing back all
4669 * descriptors, even the ones that do not have RS set. This caused kernel
4670 * panics with Linux SMP kernels, as the e1000 driver tried to free up skb
4671 * associated with written back descriptor if it happened to be a context
4672 * descriptor since context descriptors do not have skb associated to them.
4673 * Starting from r71586 we write back only the descriptors with RS set,
4674 * which is a little bit different from what the real hardware does in
4675 * case there is a chain of data descritors where some of them have RS set
4676 * and others do not. It is very uncommon scenario imho.
4677 * We need to check RPS as well since some legacy drivers use it instead of
4678 * RS even with newer cards.
4679 */
4680 if (pDesc->legacy.cmd.fRS || pDesc->legacy.cmd.fRPS)
4681 {
4682 pDesc->legacy.dw3.fDD = 1; /* Descriptor Done */
4683 e1kWriteBackDesc(pDevIns, pThis, pDesc, addr);
4684 if (pDesc->legacy.cmd.fEOP)
4685 {
4686//#ifdef E1K_USE_TX_TIMERS
4687 if (pThis->fTidEnabled && pDesc->legacy.cmd.fIDE)
4688 {
4689 E1K_INC_ISTAT_CNT(pThis->uStatTxIDE);
4690 //if (pThis->fIntRaised)
4691 //{
4692 // /* Interrupt is already pending, no need for timers */
4693 // ICR |= ICR_TXDW;
4694 //}
4695 //else {
4696 /* Arm the timer to fire in TIVD usec (discard .024) */
4697 e1kArmTimer(pDevIns, pThis, pThis->hTIDTimer, TIDV);
4698# ifndef E1K_NO_TAD
4699 /* If absolute timer delay is enabled and the timer is not running yet, arm it. */
4700 E1kLog2(("%s Checking if TAD timer is running\n",
4701 pThis->szPrf));
4702 if (TADV != 0 && !PDMDevHlpTimerIsActive(pDevIns, pThis->hTADTimer))
4703 e1kArmTimer(pDevIns, pThis, pThis->hTADTimer, TADV);
4704# endif /* E1K_NO_TAD */
4705 }
4706 else
4707 {
4708 if (pThis->fTidEnabled)
4709 {
4710 E1kLog2(("%s No IDE set, cancel TAD timer and raise interrupt\n",
4711 pThis->szPrf));
4712 /* Cancel both timers if armed and fire immediately. */
4713# ifndef E1K_NO_TAD
4714 PDMDevHlpTimerStop(pDevIns, pThis->hTADTimer);
4715# endif
4716 PDMDevHlpTimerStop(pDevIns, pThis->hTIDTimer);
4717 }
4718//#endif /* E1K_USE_TX_TIMERS */
4719 E1K_INC_ISTAT_CNT(pThis->uStatIntTx);
4720 e1kRaiseInterrupt(pDevIns, pThis, VERR_SEM_BUSY, ICR_TXDW);
4721//#ifdef E1K_USE_TX_TIMERS
4722 }
4723//#endif /* E1K_USE_TX_TIMERS */
4724 }
4725 }
4726 else
4727 {
4728 E1K_INC_ISTAT_CNT(pThis->uStatTxNoRS);
4729 }
4730}
4731
4732#ifndef E1K_WITH_TXD_CACHE
4733
4734/**
4735 * Process Transmit Descriptor.
4736 *
4737 * E1000 supports three types of transmit descriptors:
4738 * - legacy data descriptors of older format (context-less).
4739 * - data the same as legacy but providing new offloading capabilities.
4740 * - context sets up the context for following data descriptors.
4741 *
4742 * @param pDevIns The device instance.
4743 * @param pThis The device state structure.
4744 * @param pThisCC The current context instance data.
4745 * @param pDesc Pointer to descriptor union.
4746 * @param addr Physical address of descriptor in guest memory.
4747 * @param fOnWorkerThread Whether we're on a worker thread or an EMT.
4748 * @thread E1000_TX
4749 */
4750static int e1kXmitDesc(PPDMDEVINS pDevIns, PE1KSTATE pThis, PE1KSTATECC pThisCC, E1KTXDESC *pDesc,
4751 RTGCPHYS addr, bool fOnWorkerThread)
4752{
4753 int rc = VINF_SUCCESS;
4754 uint32_t cbVTag = 0;
4755
4756 e1kPrintTDesc(pThis, pDesc, "vvv");
4757
4758//#ifdef E1K_USE_TX_TIMERS
4759 if (pThis->fTidEnabled)
4760 e1kCancelTimer(pDevIns, pThis, pThis->hTIDTimer);
4761//#endif /* E1K_USE_TX_TIMERS */
4762
4763 switch (e1kGetDescType(pDesc))
4764 {
4765 case E1K_DTYP_CONTEXT:
4766 if (pDesc->context.dw2.fTSE)
4767 {
4768 pThis->contextTSE = pDesc->context;
4769 pThis->u32PayRemain = pDesc->context.dw2.u20PAYLEN;
4770 pThis->u16HdrRemain = pDesc->context.dw3.u8HDRLEN;
4771 e1kSetupGsoCtx(&pThis->GsoCtx, &pDesc->context);
4772 STAM_COUNTER_INC(&pThis->StatTxDescCtxTSE);
4773 }
4774 else
4775 {
4776 pThis->contextNormal = pDesc->context;
4777 STAM_COUNTER_INC(&pThis->StatTxDescCtxNormal);
4778 }
4779 E1kLog2(("%s %s context updated: IP CSS=%02X, IP CSO=%02X, IP CSE=%04X"
4780 ", TU CSS=%02X, TU CSO=%02X, TU CSE=%04X\n", pThis->szPrf,
4781 pDesc->context.dw2.fTSE ? "TSE" : "Normal",
4782 pDesc->context.ip.u8CSS,
4783 pDesc->context.ip.u8CSO,
4784 pDesc->context.ip.u16CSE,
4785 pDesc->context.tu.u8CSS,
4786 pDesc->context.tu.u8CSO,
4787 pDesc->context.tu.u16CSE));
4788 E1K_INC_ISTAT_CNT(pThis->uStatDescCtx);
4789 e1kDescReport(pThis, pDesc, addr);
4790 break;
4791
4792 case E1K_DTYP_DATA:
4793 {
4794 if (pDesc->data.cmd.u20DTALEN == 0 || pDesc->data.u64BufAddr == 0)
4795 {
4796 E1kLog2(("% Empty data descriptor, skipped.\n", pThis->szPrf));
4797 /** @todo Same as legacy when !TSE. See below. */
4798 break;
4799 }
4800 STAM_COUNTER_INC(pDesc->data.cmd.fTSE?
4801 &pThis->StatTxDescTSEData:
4802 &pThis->StatTxDescData);
4803 STAM_PROFILE_ADV_START(&pThis->CTX_SUFF_Z(StatTransmit), a);
4804 E1K_INC_ISTAT_CNT(pThis->uStatDescDat);
4805
4806 /*
4807 * The last descriptor of non-TSE packet must contain VLE flag.
4808 * TSE packets have VLE flag in the first descriptor. The later
4809 * case is taken care of a bit later when cbVTag gets assigned.
4810 *
4811 * 1) pDesc->data.cmd.fEOP && !pDesc->data.cmd.fTSE
4812 */
4813 if (pDesc->data.cmd.fEOP && !pDesc->data.cmd.fTSE)
4814 {
4815 pThis->fVTag = pDesc->data.cmd.fVLE;
4816 pThis->u16VTagTCI = pDesc->data.dw3.u16Special;
4817 }
4818 /*
4819 * First fragment: Allocate new buffer and save the IXSM and TXSM
4820 * packet options as these are only valid in the first fragment.
4821 */
4822 if (pThis->u16TxPktLen == 0)
4823 {
4824 pThis->fIPcsum = pDesc->data.dw3.fIXSM;
4825 pThis->fTCPcsum = pDesc->data.dw3.fTXSM;
4826 E1kLog2(("%s Saving checksum flags:%s%s; \n", pThis->szPrf,
4827 pThis->fIPcsum ? " IP" : "",
4828 pThis->fTCPcsum ? " TCP/UDP" : ""));
4829 if (pDesc->data.cmd.fTSE)
4830 {
4831 /* 2) pDesc->data.cmd.fTSE && pThis->u16TxPktLen == 0 */
4832 pThis->fVTag = pDesc->data.cmd.fVLE;
4833 pThis->u16VTagTCI = pDesc->data.dw3.u16Special;
4834 cbVTag = pThis->fVTag ? 4 : 0;
4835 }
4836 else if (pDesc->data.cmd.fEOP)
4837 cbVTag = pDesc->data.cmd.fVLE ? 4 : 0;
4838 else
4839 cbVTag = 4;
4840 E1kLog3(("%s About to allocate TX buffer: cbVTag=%u\n", pThis->szPrf, cbVTag));
4841 if (e1kCanDoGso(pThis, &pThis->GsoCtx, &pDesc->data, &pThis->contextTSE))
4842 rc = e1kXmitAllocBuf(pThis, pThisCC, pThis->contextTSE.dw2.u20PAYLEN + pThis->contextTSE.dw3.u8HDRLEN + cbVTag,
4843 true /*fExactSize*/, true /*fGso*/);
4844 else if (pDesc->data.cmd.fTSE)
4845 rc = e1kXmitAllocBuf(pThis, pThisCC, , pThis->contextTSE.dw3.u16MSS + pThis->contextTSE.dw3.u8HDRLEN + cbVTag,
4846 pDesc->data.cmd.fTSE /*fExactSize*/, false /*fGso*/);
4847 else
4848 rc = e1kXmitAllocBuf(pThis, pThisCC, pDesc->data.cmd.u20DTALEN + cbVTag,
4849 pDesc->data.cmd.fEOP /*fExactSize*/, false /*fGso*/);
4850
4851 /**
4852 * @todo: Perhaps it is not that simple for GSO packets! We may
4853 * need to unwind some changes.
4854 */
4855 if (RT_FAILURE(rc))
4856 {
4857 STAM_PROFILE_ADV_STOP(&pThis->CTX_SUFF_Z(StatTransmit), a);
4858 break;
4859 }
4860 /** @todo Is there any way to indicating errors other than collisions? Like
4861 * VERR_NET_DOWN. */
4862 }
4863
4864 /*
4865 * Add the descriptor data to the frame. If the frame is complete,
4866 * transmit it and reset the u16TxPktLen field.
4867 */
4868 if (e1kXmitIsGsoBuf(pThisCC->CTX_SUFF(pTxSg)))
4869 {
4870 STAM_COUNTER_INC(&pThis->StatTxPathGSO);
4871 bool fRc = e1kAddToFrame(pDevIns, pThis, pThisCC, pDesc->data.u64BufAddr, pDesc->data.cmd.u20DTALEN);
4872 if (pDesc->data.cmd.fEOP)
4873 {
4874 if ( fRc
4875 && pThisCC->CTX_SUFF(pTxSg)
4876 && pThisCC->CTX_SUFF(pTxSg)->cbUsed == (size_t)pThis->contextTSE.dw3.u8HDRLEN + pThis->contextTSE.dw2.u20PAYLEN)
4877 {
4878 e1kTransmitFrame(pDevIns, pThis, pThisCC, fOnWorkerThread);
4879 E1K_INC_CNT32(TSCTC);
4880 }
4881 else
4882 {
4883 if (fRc)
4884 E1kLog(("%s bad GSO/TSE %p or %u < %u\n" , pThis->szPrf,
4885 pThisCC->CTX_SUFF(pTxSg), pThisCC->CTX_SUFF(pTxSg) ? pThisCC->CTX_SUFF(pTxSg)->cbUsed : 0,
4886 pThis->contextTSE.dw3.u8HDRLEN + pThis->contextTSE.dw2.u20PAYLEN));
4887 e1kXmitFreeBuf(pThis);
4888 E1K_INC_CNT32(TSCTFC);
4889 }
4890 pThis->u16TxPktLen = 0;
4891 }
4892 }
4893 else if (!pDesc->data.cmd.fTSE)
4894 {
4895 STAM_COUNTER_INC(&pThis->StatTxPathRegular);
4896 bool fRc = e1kAddToFrame(pDevIns, pThis, pThisCC, pDesc->data.u64BufAddr, pDesc->data.cmd.u20DTALEN);
4897 if (pDesc->data.cmd.fEOP)
4898 {
4899 if (fRc && pThisCC->CTX_SUFF(pTxSg))
4900 {
4901 Assert(pThisCC->CTX_SUFF(pTxSg)->cSegs == 1);
4902 if (pThis->fIPcsum)
4903 e1kInsertChecksum(pThis, (uint8_t *)pThisCC->CTX_SUFF(pTxSg)->aSegs[0].pvSeg, pThis->u16TxPktLen,
4904 pThis->contextNormal.ip.u8CSO,
4905 pThis->contextNormal.ip.u8CSS,
4906 pThis->contextNormal.ip.u16CSE);
4907 if (pThis->fTCPcsum)
4908 e1kInsertChecksum(pThis, (uint8_t *)pThisCC->CTX_SUFF(pTxSg)->aSegs[0].pvSeg, pThis->u16TxPktLen,
4909 pThis->contextNormal.tu.u8CSO,
4910 pThis->contextNormal.tu.u8CSS,
4911 pThis->contextNormal.tu.u16CSE);
4912 e1kTransmitFrame(pDevIns, pThis, pThisCC, fOnWorkerThread);
4913 }
4914 else
4915 e1kXmitFreeBuf(pThis);
4916 pThis->u16TxPktLen = 0;
4917 }
4918 }
4919 else
4920 {
4921 STAM_COUNTER_INC(&pThis->StatTxPathFallback);
4922 e1kFallbackAddToFrame(pDevIns, pThis, pDesc, pDesc->data.cmd.u20DTALEN, fOnWorkerThread);
4923 }
4924
4925 e1kDescReport(pThis, pDesc, addr);
4926 STAM_PROFILE_ADV_STOP(&pThis->CTX_SUFF_Z(StatTransmit), a);
4927 break;
4928 }
4929
4930 case E1K_DTYP_LEGACY:
4931 if (pDesc->legacy.cmd.u16Length == 0 || pDesc->legacy.u64BufAddr == 0)
4932 {
4933 E1kLog(("%s Empty legacy descriptor, skipped.\n", pThis->szPrf));
4934 /** @todo 3.3.3, Length/Buffer Address: RS set -> write DD when processing. */
4935 break;
4936 }
4937 STAM_COUNTER_INC(&pThis->StatTxDescLegacy);
4938 STAM_PROFILE_ADV_START(&pThis->CTX_SUFF_Z(StatTransmit), a);
4939
4940 /* First fragment: allocate new buffer. */
4941 if (pThis->u16TxPktLen == 0)
4942 {
4943 if (pDesc->legacy.cmd.fEOP)
4944 cbVTag = pDesc->legacy.cmd.fVLE ? 4 : 0;
4945 else
4946 cbVTag = 4;
4947 E1kLog3(("%s About to allocate TX buffer: cbVTag=%u\n", pThis->szPrf, cbVTag));
4948 /** @todo reset status bits? */
4949 rc = e1kXmitAllocBuf(pThis, pThisCC, pDesc->legacy.cmd.u16Length + cbVTag, pDesc->legacy.cmd.fEOP, false /*fGso*/);
4950 if (RT_FAILURE(rc))
4951 {
4952 STAM_PROFILE_ADV_STOP(&pThis->CTX_SUFF_Z(StatTransmit), a);
4953 break;
4954 }
4955
4956 /** @todo Is there any way to indicating errors other than collisions? Like
4957 * VERR_NET_DOWN. */
4958 }
4959
4960 /* Add fragment to frame. */
4961 if (e1kAddToFrame(pDevIns, pThis, pThisCC, pDesc->data.u64BufAddr, pDesc->legacy.cmd.u16Length))
4962 {
4963 E1K_INC_ISTAT_CNT(pThis->uStatDescLeg);
4964
4965 /* Last fragment: Transmit and reset the packet storage counter. */
4966 if (pDesc->legacy.cmd.fEOP)
4967 {
4968 pThis->fVTag = pDesc->legacy.cmd.fVLE;
4969 pThis->u16VTagTCI = pDesc->legacy.dw3.u16Special;
4970 /** @todo Offload processing goes here. */
4971 e1kTransmitFrame(pDevIns, pThis, pThisCC, fOnWorkerThread);
4972 pThis->u16TxPktLen = 0;
4973 }
4974 }
4975 /* Last fragment + failure: free the buffer and reset the storage counter. */
4976 else if (pDesc->legacy.cmd.fEOP)
4977 {
4978 e1kXmitFreeBuf(pThis);
4979 pThis->u16TxPktLen = 0;
4980 }
4981
4982 e1kDescReport(pThis, pDesc, addr);
4983 STAM_PROFILE_ADV_STOP(&pThis->CTX_SUFF_Z(StatTransmit), a);
4984 break;
4985
4986 default:
4987 E1kLog(("%s ERROR Unsupported transmit descriptor type: 0x%04x\n",
4988 pThis->szPrf, e1kGetDescType(pDesc)));
4989 break;
4990 }
4991
4992 return rc;
4993}
4994
4995#else /* E1K_WITH_TXD_CACHE */
4996
4997/**
4998 * Process Transmit Descriptor.
4999 *
5000 * E1000 supports three types of transmit descriptors:
5001 * - legacy data descriptors of older format (context-less).
5002 * - data the same as legacy but providing new offloading capabilities.
5003 * - context sets up the context for following data descriptors.
5004 *
5005 * @param pDevIns The device instance.
5006 * @param pThis The device state structure.
5007 * @param pThisCC The current context instance data.
5008 * @param pDesc Pointer to descriptor union.
5009 * @param addr Physical address of descriptor in guest memory.
5010 * @param fOnWorkerThread Whether we're on a worker thread or an EMT.
5011 * @param cbPacketSize Size of the packet as previously computed.
5012 * @thread E1000_TX
5013 */
5014static int e1kXmitDesc(PPDMDEVINS pDevIns, PE1KSTATE pThis, PE1KSTATECC pThisCC, E1KTXDESC *pDesc,
5015 RTGCPHYS addr, bool fOnWorkerThread)
5016{
5017 int rc = VINF_SUCCESS;
5018
5019 e1kPrintTDesc(pThis, pDesc, "vvv");
5020
5021 if (pDesc->legacy.dw3.fDD)
5022 {
5023 E1kLog(("%s e1kXmitDesc: skipping bad descriptor ^^^\n", pThis->szPrf));
5024 e1kDescReport(pDevIns, pThis, pDesc, addr);
5025 return VINF_SUCCESS;
5026 }
5027
5028//#ifdef E1K_USE_TX_TIMERS
5029 if (pThis->fTidEnabled)
5030 PDMDevHlpTimerStop(pDevIns, pThis->hTIDTimer);
5031//#endif /* E1K_USE_TX_TIMERS */
5032
5033 switch (e1kGetDescType(pDesc))
5034 {
5035 case E1K_DTYP_CONTEXT:
5036 /* The caller have already updated the context */
5037 E1K_INC_ISTAT_CNT(pThis->uStatDescCtx);
5038 e1kDescReport(pDevIns, pThis, pDesc, addr);
5039 break;
5040
5041 case E1K_DTYP_DATA:
5042 {
5043 STAM_COUNTER_INC(pDesc->data.cmd.fTSE?
5044 &pThis->StatTxDescTSEData:
5045 &pThis->StatTxDescData);
5046 E1K_INC_ISTAT_CNT(pThis->uStatDescDat);
5047 STAM_PROFILE_ADV_START(&pThis->CTX_SUFF_Z(StatTransmit), a);
5048 if (pDesc->data.cmd.u20DTALEN == 0 || pDesc->data.u64BufAddr == 0)
5049 {
5050 E1kLog2(("% Empty data descriptor, skipped.\n", pThis->szPrf));
5051 if (pDesc->data.cmd.fEOP)
5052 {
5053 e1kTransmitFrame(pDevIns, pThis, pThisCC, fOnWorkerThread);
5054 pThis->u16TxPktLen = 0;
5055 }
5056 }
5057 else
5058 {
5059 /*
5060 * Add the descriptor data to the frame. If the frame is complete,
5061 * transmit it and reset the u16TxPktLen field.
5062 */
5063 if (e1kXmitIsGsoBuf(pThisCC->CTX_SUFF(pTxSg)))
5064 {
5065 STAM_COUNTER_INC(&pThis->StatTxPathGSO);
5066 bool fRc = e1kAddToFrame(pDevIns, pThis, pThisCC, pDesc->data.u64BufAddr, pDesc->data.cmd.u20DTALEN);
5067 if (pDesc->data.cmd.fEOP)
5068 {
5069 if ( fRc
5070 && pThisCC->CTX_SUFF(pTxSg)
5071 && pThisCC->CTX_SUFF(pTxSg)->cbUsed == (size_t)pThis->contextTSE.dw3.u8HDRLEN + pThis->contextTSE.dw2.u20PAYLEN)
5072 {
5073 e1kTransmitFrame(pDevIns, pThis, pThisCC, fOnWorkerThread);
5074 E1K_INC_CNT32(TSCTC);
5075 }
5076 else
5077 {
5078 if (fRc)
5079 E1kLog(("%s bad GSO/TSE %p or %u < %u\n" , pThis->szPrf,
5080 pThisCC->CTX_SUFF(pTxSg), pThisCC->CTX_SUFF(pTxSg) ? pThisCC->CTX_SUFF(pTxSg)->cbUsed : 0,
5081 pThis->contextTSE.dw3.u8HDRLEN + pThis->contextTSE.dw2.u20PAYLEN));
5082 e1kXmitFreeBuf(pThis, pThisCC);
5083 E1K_INC_CNT32(TSCTFC);
5084 }
5085 pThis->u16TxPktLen = 0;
5086 }
5087 }
5088 else if (!pDesc->data.cmd.fTSE)
5089 {
5090 STAM_COUNTER_INC(&pThis->StatTxPathRegular);
5091 bool fRc = e1kAddToFrame(pDevIns, pThis, pThisCC, pDesc->data.u64BufAddr, pDesc->data.cmd.u20DTALEN);
5092 if (pDesc->data.cmd.fEOP)
5093 {
5094 if (fRc && pThisCC->CTX_SUFF(pTxSg))
5095 {
5096 Assert(pThisCC->CTX_SUFF(pTxSg)->cSegs == 1);
5097 if (pThis->fIPcsum)
5098 e1kInsertChecksum(pThis, (uint8_t *)pThisCC->CTX_SUFF(pTxSg)->aSegs[0].pvSeg, pThis->u16TxPktLen,
5099 pThis->contextNormal.ip.u8CSO,
5100 pThis->contextNormal.ip.u8CSS,
5101 pThis->contextNormal.ip.u16CSE);
5102 if (pThis->fTCPcsum)
5103 e1kInsertChecksum(pThis, (uint8_t *)pThisCC->CTX_SUFF(pTxSg)->aSegs[0].pvSeg, pThis->u16TxPktLen,
5104 pThis->contextNormal.tu.u8CSO,
5105 pThis->contextNormal.tu.u8CSS,
5106 pThis->contextNormal.tu.u16CSE);
5107 e1kTransmitFrame(pDevIns, pThis, pThisCC, fOnWorkerThread);
5108 }
5109 else
5110 e1kXmitFreeBuf(pThis, pThisCC);
5111 pThis->u16TxPktLen = 0;
5112 }
5113 }
5114 else
5115 {
5116 STAM_COUNTER_INC(&pThis->StatTxPathFallback);
5117 rc = e1kFallbackAddToFrame(pDevIns, pThis, pDesc, fOnWorkerThread);
5118 }
5119 }
5120 e1kDescReport(pDevIns, pThis, pDesc, addr);
5121 STAM_PROFILE_ADV_STOP(&pThis->CTX_SUFF_Z(StatTransmit), a);
5122 break;
5123 }
5124
5125 case E1K_DTYP_LEGACY:
5126 STAM_COUNTER_INC(&pThis->StatTxDescLegacy);
5127 STAM_PROFILE_ADV_START(&pThis->CTX_SUFF_Z(StatTransmit), a);
5128 if (pDesc->legacy.cmd.u16Length == 0 || pDesc->legacy.u64BufAddr == 0)
5129 {
5130 E1kLog(("%s Empty legacy descriptor, skipped.\n", pThis->szPrf));
5131 }
5132 else
5133 {
5134 /* Add fragment to frame. */
5135 if (e1kAddToFrame(pDevIns, pThis, pThisCC, pDesc->data.u64BufAddr, pDesc->legacy.cmd.u16Length))
5136 {
5137 E1K_INC_ISTAT_CNT(pThis->uStatDescLeg);
5138
5139 /* Last fragment: Transmit and reset the packet storage counter. */
5140 if (pDesc->legacy.cmd.fEOP)
5141 {
5142 if (pDesc->legacy.cmd.fIC)
5143 {
5144 e1kInsertChecksum(pThis,
5145 (uint8_t *)pThisCC->CTX_SUFF(pTxSg)->aSegs[0].pvSeg,
5146 pThis->u16TxPktLen,
5147 pDesc->legacy.cmd.u8CSO,
5148 pDesc->legacy.dw3.u8CSS,
5149 0);
5150 }
5151 e1kTransmitFrame(pDevIns, pThis, pThisCC, fOnWorkerThread);
5152 pThis->u16TxPktLen = 0;
5153 }
5154 }
5155 /* Last fragment + failure: free the buffer and reset the storage counter. */
5156 else if (pDesc->legacy.cmd.fEOP)
5157 {
5158 e1kXmitFreeBuf(pThis, pThisCC);
5159 pThis->u16TxPktLen = 0;
5160 }
5161 }
5162 e1kDescReport(pDevIns, pThis, pDesc, addr);
5163 STAM_PROFILE_ADV_STOP(&pThis->CTX_SUFF_Z(StatTransmit), a);
5164 break;
5165
5166 default:
5167 E1kLog(("%s ERROR Unsupported transmit descriptor type: 0x%04x\n",
5168 pThis->szPrf, e1kGetDescType(pDesc)));
5169 break;
5170 }
5171
5172 return rc;
5173}
5174
5175DECLINLINE(void) e1kUpdateTxContext(PE1KSTATE pThis, E1KTXDESC *pDesc)
5176{
5177 if (pDesc->context.dw2.fTSE)
5178 {
5179 pThis->contextTSE = pDesc->context;
5180 uint32_t cbMaxSegmentSize = pThis->contextTSE.dw3.u16MSS + pThis->contextTSE.dw3.u8HDRLEN + 4; /*VTAG*/
5181 if (RT_UNLIKELY(cbMaxSegmentSize > E1K_MAX_TX_PKT_SIZE))
5182 {
5183 pThis->contextTSE.dw3.u16MSS = E1K_MAX_TX_PKT_SIZE - pThis->contextTSE.dw3.u8HDRLEN - 4; /*VTAG*/
5184 LogRelMax(10, ("%s: Transmit packet is too large: %u > %u(max). Adjusted MSS to %u.\n",
5185 pThis->szPrf, cbMaxSegmentSize, E1K_MAX_TX_PKT_SIZE, pThis->contextTSE.dw3.u16MSS));
5186 }
5187 pThis->u32PayRemain = pThis->contextTSE.dw2.u20PAYLEN;
5188 pThis->u16HdrRemain = pThis->contextTSE.dw3.u8HDRLEN;
5189 e1kSetupGsoCtx(&pThis->GsoCtx, &pThis->contextTSE);
5190 STAM_COUNTER_INC(&pThis->StatTxDescCtxTSE);
5191 }
5192 else
5193 {
5194 pThis->contextNormal = pDesc->context;
5195 STAM_COUNTER_INC(&pThis->StatTxDescCtxNormal);
5196 }
5197 E1kLog2(("%s %s context updated: IP CSS=%02X, IP CSO=%02X, IP CSE=%04X"
5198 ", TU CSS=%02X, TU CSO=%02X, TU CSE=%04X\n", pThis->szPrf,
5199 pDesc->context.dw2.fTSE ? "TSE" : "Normal",
5200 pDesc->context.ip.u8CSS,
5201 pDesc->context.ip.u8CSO,
5202 pDesc->context.ip.u16CSE,
5203 pDesc->context.tu.u8CSS,
5204 pDesc->context.tu.u8CSO,
5205 pDesc->context.tu.u16CSE));
5206}
5207
5208static bool e1kLocateTxPacket(PE1KSTATE pThis)
5209{
5210 LogFlow(("%s e1kLocateTxPacket: ENTER cbTxAlloc=%d\n",
5211 pThis->szPrf, pThis->cbTxAlloc));
5212 /* Check if we have located the packet already. */
5213 if (pThis->cbTxAlloc)
5214 {
5215 LogFlow(("%s e1kLocateTxPacket: RET true cbTxAlloc=%d\n",
5216 pThis->szPrf, pThis->cbTxAlloc));
5217 return true;
5218 }
5219
5220 bool fTSE = false;
5221 uint32_t cbPacket = 0;
5222
5223 for (int i = pThis->iTxDCurrent; i < pThis->nTxDFetched; ++i)
5224 {
5225 E1KTXDESC *pDesc = &pThis->aTxDescriptors[i];
5226 switch (e1kGetDescType(pDesc))
5227 {
5228 case E1K_DTYP_CONTEXT:
5229 if (cbPacket == 0)
5230 e1kUpdateTxContext(pThis, pDesc);
5231 else
5232 E1kLog(("%s e1kLocateTxPacket: ignoring a context descriptor in the middle of a packet, cbPacket=%d\n",
5233 pThis->szPrf, cbPacket));
5234 continue;
5235 case E1K_DTYP_LEGACY:
5236 /* Skip invalid descriptors. */
5237 if (cbPacket > 0 && (pThis->fGSO || fTSE))
5238 {
5239 E1kLog(("%s e1kLocateTxPacket: ignoring a legacy descriptor in the segmentation context, cbPacket=%d\n",
5240 pThis->szPrf, cbPacket));
5241 pDesc->legacy.dw3.fDD = true; /* Make sure it is skipped by processing */
5242 continue;
5243 }
5244 /* Skip empty descriptors. */
5245 if (!pDesc->legacy.u64BufAddr || !pDesc->legacy.cmd.u16Length)
5246 break;
5247 cbPacket += pDesc->legacy.cmd.u16Length;
5248 pThis->fGSO = false;
5249 break;
5250 case E1K_DTYP_DATA:
5251 /* Skip invalid descriptors. */
5252 if (cbPacket > 0 && (bool)pDesc->data.cmd.fTSE != fTSE)
5253 {
5254 E1kLog(("%s e1kLocateTxPacket: ignoring %sTSE descriptor in the %ssegmentation context, cbPacket=%d\n",
5255 pThis->szPrf, pDesc->data.cmd.fTSE ? "" : "non-", fTSE ? "" : "non-", cbPacket));
5256 pDesc->data.dw3.fDD = true; /* Make sure it is skipped by processing */
5257 continue;
5258 }
5259 /* Skip empty descriptors. */
5260 if (!pDesc->data.u64BufAddr || !pDesc->data.cmd.u20DTALEN)
5261 break;
5262 if (cbPacket == 0)
5263 {
5264 /*
5265 * The first fragment: save IXSM and TXSM options
5266 * as these are only valid in the first fragment.
5267 */
5268 pThis->fIPcsum = pDesc->data.dw3.fIXSM;
5269 pThis->fTCPcsum = pDesc->data.dw3.fTXSM;
5270 fTSE = pDesc->data.cmd.fTSE;
5271 /*
5272 * TSE descriptors have VLE bit properly set in
5273 * the first fragment.
5274 */
5275 if (fTSE)
5276 {
5277 pThis->fVTag = pDesc->data.cmd.fVLE;
5278 pThis->u16VTagTCI = pDesc->data.dw3.u16Special;
5279 }
5280 pThis->fGSO = e1kCanDoGso(pThis, &pThis->GsoCtx, &pDesc->data, &pThis->contextTSE);
5281 }
5282 cbPacket += pDesc->data.cmd.u20DTALEN;
5283 break;
5284 default:
5285 AssertMsgFailed(("Impossible descriptor type!"));
5286 continue;
5287 }
5288 if (pDesc->legacy.cmd.fEOP)
5289 {
5290 /*
5291 * Non-TSE descriptors have VLE bit properly set in
5292 * the last fragment.
5293 */
5294 if (!fTSE)
5295 {
5296 pThis->fVTag = pDesc->data.cmd.fVLE;
5297 pThis->u16VTagTCI = pDesc->data.dw3.u16Special;
5298 }
5299 /*
5300 * Compute the required buffer size. If we cannot do GSO but still
5301 * have to do segmentation we allocate the first segment only.
5302 */
5303 pThis->cbTxAlloc = (!fTSE || pThis->fGSO) ?
5304 cbPacket :
5305 RT_MIN(cbPacket, pThis->contextTSE.dw3.u16MSS + pThis->contextTSE.dw3.u8HDRLEN);
5306 /* Do not add VLAN tags to empty packets. */
5307 if (pThis->fVTag && pThis->cbTxAlloc > 0)
5308 pThis->cbTxAlloc += 4;
5309 LogFlow(("%s e1kLocateTxPacket: RET true cbTxAlloc=%d cbPacket=%d%s%s\n",
5310 pThis->szPrf, pThis->cbTxAlloc, cbPacket,
5311 pThis->fGSO ? " GSO" : "", fTSE ? " TSE" : ""));
5312 return true;
5313 }
5314 }
5315
5316 if (cbPacket == 0 && pThis->nTxDFetched - pThis->iTxDCurrent > 0)
5317 {
5318 /* All descriptors were empty, we need to process them as a dummy packet */
5319 LogFlow(("%s e1kLocateTxPacket: RET true cbTxAlloc=%d, zero packet!\n",
5320 pThis->szPrf, pThis->cbTxAlloc));
5321 return true;
5322 }
5323 LogFlow(("%s e1kLocateTxPacket: RET false cbTxAlloc=%d cbPacket=%d\n",
5324 pThis->szPrf, pThis->cbTxAlloc, cbPacket));
5325 return false;
5326}
5327
5328static int e1kXmitPacket(PPDMDEVINS pDevIns, PE1KSTATE pThis, bool fOnWorkerThread)
5329{
5330 PE1KSTATECC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PE1KSTATECC);
5331 int rc = VINF_SUCCESS;
5332
5333 LogFlow(("%s e1kXmitPacket: ENTER current=%d fetched=%d\n",
5334 pThis->szPrf, pThis->iTxDCurrent, pThis->nTxDFetched));
5335
5336 while (pThis->iTxDCurrent < pThis->nTxDFetched)
5337 {
5338 E1KTXDESC *pDesc = &pThis->aTxDescriptors[pThis->iTxDCurrent];
5339 E1kLog3(("%s About to process new TX descriptor at %08x%08x, TDLEN=%08x, TDH=%08x, TDT=%08x\n",
5340 pThis->szPrf, TDBAH, TDBAL + TDH * sizeof(E1KTXDESC), TDLEN, TDH, TDT));
5341 rc = e1kXmitDesc(pDevIns, pThis, pThisCC, pDesc, e1kDescAddr(TDBAH, TDBAL, TDH), fOnWorkerThread);
5342 if (RT_FAILURE(rc))
5343 break;
5344 if (++TDH * sizeof(E1KTXDESC) >= TDLEN)
5345 TDH = 0;
5346 uint32_t uLowThreshold = GET_BITS(TXDCTL, LWTHRESH)*8;
5347 if (uLowThreshold != 0 && e1kGetTxLen(pThis) <= uLowThreshold)
5348 {
5349 E1kLog2(("%s Low on transmit descriptors, raise ICR.TXD_LOW, len=%x thresh=%x\n",
5350 pThis->szPrf, e1kGetTxLen(pThis), GET_BITS(TXDCTL, LWTHRESH)*8));
5351 e1kRaiseInterrupt(pDevIns, pThis, VERR_SEM_BUSY, ICR_TXD_LOW);
5352 }
5353 ++pThis->iTxDCurrent;
5354 if (e1kGetDescType(pDesc) != E1K_DTYP_CONTEXT && pDesc->legacy.cmd.fEOP)
5355 break;
5356 }
5357
5358 LogFlow(("%s e1kXmitPacket: RET %Rrc current=%d fetched=%d\n",
5359 pThis->szPrf, rc, pThis->iTxDCurrent, pThis->nTxDFetched));
5360 return rc;
5361}
5362
5363#endif /* E1K_WITH_TXD_CACHE */
5364#ifndef E1K_WITH_TXD_CACHE
5365
5366/**
5367 * Transmit pending descriptors.
5368 *
5369 * @returns VBox status code. VERR_TRY_AGAIN is returned if we're busy.
5370 *
5371 * @param pDevIns The device instance.
5372 * @param pThis The E1000 state.
5373 * @param fOnWorkerThread Whether we're on a worker thread or on an EMT.
5374 */
5375static int e1kXmitPending(PPDMDEVINS pDevIns, PE1KSTATE pThis, bool fOnWorkerThread)
5376{
5377 int rc = VINF_SUCCESS;
5378 PE1KSTATECC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PE1KSTATECC);
5379
5380 /* Check if transmitter is enabled. */
5381 if (!(TCTL & TCTL_EN))
5382 return VINF_SUCCESS;
5383 /*
5384 * Grab the xmit lock of the driver as well as the E1K device state.
5385 */
5386 rc = e1kCsTxEnter(pThis, VERR_SEM_BUSY);
5387 if (RT_LIKELY(rc == VINF_SUCCESS))
5388 {
5389 PPDMINETWORKUP pDrv = pThis->CTX_SUFF(pDrv);
5390 if (pDrv)
5391 {
5392 rc = pDrv->pfnBeginXmit(pDrv, fOnWorkerThread);
5393 if (RT_FAILURE(rc))
5394 {
5395 e1kCsTxLeave(pThis);
5396 return rc;
5397 }
5398 }
5399 /*
5400 * Process all pending descriptors.
5401 * Note! Do not process descriptors in locked state
5402 */
5403 while (TDH != TDT && !pThis->fLocked)
5404 {
5405 E1KTXDESC desc;
5406 E1kLog3(("%s About to process new TX descriptor at %08x%08x, TDLEN=%08x, TDH=%08x, TDT=%08x\n",
5407 pThis->szPrf, TDBAH, TDBAL + TDH * sizeof(desc), TDLEN, TDH, TDT));
5408
5409 e1kLoadDesc(pDevIns, &desc, ((uint64_t)TDBAH << 32) + TDBAL + TDH * sizeof(desc));
5410 rc = e1kXmitDesc(pDevIns, pThis, pThisCC, &desc, e1kDescAddr(TDBAH, TDBAL, TDH), fOnWorkerThread);
5411 /* If we failed to transmit descriptor we will try it again later */
5412 if (RT_FAILURE(rc))
5413 break;
5414 if (++TDH * sizeof(desc) >= TDLEN)
5415 TDH = 0;
5416
5417 if (e1kGetTxLen(pThis) <= GET_BITS(TXDCTL, LWTHRESH)*8)
5418 {
5419 E1kLog2(("%s Low on transmit descriptors, raise ICR.TXD_LOW, len=%x thresh=%x\n",
5420 pThis->szPrf, e1kGetTxLen(pThis), GET_BITS(TXDCTL, LWTHRESH)*8));
5421 e1kRaiseInterrupt(pDevIns, pThis, VERR_SEM_BUSY, ICR_TXD_LOW);
5422 }
5423
5424 STAM_PROFILE_ADV_STOP(&pThis->CTX_SUFF_Z(StatTransmit), a);
5425 }
5426
5427 /// @todo uncomment: pThis->uStatIntTXQE++;
5428 /// @todo uncomment: e1kRaiseInterrupt(pDevIns, pThis, ICR_TXQE);
5429 /*
5430 * Release the lock.
5431 */
5432 if (pDrv)
5433 pDrv->pfnEndXmit(pDrv);
5434 e1kCsTxLeave(pThis);
5435 }
5436
5437 return rc;
5438}
5439
5440#else /* E1K_WITH_TXD_CACHE */
5441
5442static void e1kDumpTxDCache(PPDMDEVINS pDevIns, PE1KSTATE pThis)
5443{
5444 unsigned i, cDescs = TDLEN / sizeof(E1KTXDESC);
5445 uint32_t tdh = TDH;
5446 LogRel(("E1000: -- Transmit Descriptors (%d total) --\n", cDescs));
5447 for (i = 0; i < cDescs; ++i)
5448 {
5449 E1KTXDESC desc;
5450 PDMDevHlpPhysRead(pDevIns , e1kDescAddr(TDBAH, TDBAL, i), &desc, sizeof(desc));
5451 if (i == tdh)
5452 LogRel(("E1000: >>> "));
5453 LogRel(("E1000: %RGp: %R[e1ktxd]\n", e1kDescAddr(TDBAH, TDBAL, i), &desc));
5454 }
5455 LogRel(("E1000: -- Transmit Descriptors in Cache (at %d (TDH %d)/ fetched %d / max %d) --\n",
5456 pThis->iTxDCurrent, TDH, pThis->nTxDFetched, E1K_TXD_CACHE_SIZE));
5457 if (tdh > pThis->iTxDCurrent)
5458 tdh -= pThis->iTxDCurrent;
5459 else
5460 tdh = cDescs + tdh - pThis->iTxDCurrent;
5461 for (i = 0; i < pThis->nTxDFetched; ++i)
5462 {
5463 if (i == pThis->iTxDCurrent)
5464 LogRel(("E1000: >>> "));
5465 LogRel(("E1000: %RGp: %R[e1ktxd]\n", e1kDescAddr(TDBAH, TDBAL, tdh++ % cDescs), &pThis->aTxDescriptors[i]));
5466 }
5467}
5468
5469/**
5470 * Transmit pending descriptors.
5471 *
5472 * @returns VBox status code. VERR_TRY_AGAIN is returned if we're busy.
5473 *
5474 * @param pDevIns The device instance.
5475 * @param pThis The E1000 state.
5476 * @param fOnWorkerThread Whether we're on a worker thread or on an EMT.
5477 */
5478static int e1kXmitPending(PPDMDEVINS pDevIns, PE1KSTATE pThis, bool fOnWorkerThread)
5479{
5480 PE1KSTATECC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PE1KSTATECC);
5481 int rc = VINF_SUCCESS;
5482
5483 /* Check if transmitter is enabled. */
5484 if (!(TCTL & TCTL_EN))
5485 return VINF_SUCCESS;
5486 /*
5487 * Grab the xmit lock of the driver as well as the E1K device state.
5488 */
5489 PPDMINETWORKUP pDrv = pThisCC->CTX_SUFF(pDrv);
5490 if (pDrv)
5491 {
5492 rc = pDrv->pfnBeginXmit(pDrv, fOnWorkerThread);
5493 if (RT_FAILURE(rc))
5494 return rc;
5495 }
5496
5497 /*
5498 * Process all pending descriptors.
5499 * Note! Do not process descriptors in locked state
5500 */
5501 rc = e1kCsTxEnter(pThis, VERR_SEM_BUSY);
5502 if (RT_LIKELY(rc == VINF_SUCCESS))
5503 {
5504 STAM_PROFILE_ADV_START(&pThis->CTX_SUFF_Z(StatTransmit), a);
5505 /*
5506 * fIncomplete is set whenever we try to fetch additional descriptors
5507 * for an incomplete packet. If fail to locate a complete packet on
5508 * the next iteration we need to reset the cache or we risk to get
5509 * stuck in this loop forever.
5510 */
5511 bool fIncomplete = false;
5512 while (!pThis->fLocked && e1kTxDLazyLoad(pDevIns, pThis))
5513 {
5514 while (e1kLocateTxPacket(pThis))
5515 {
5516 fIncomplete = false;
5517 /* Found a complete packet, allocate it. */
5518 rc = e1kXmitAllocBuf(pThis, pThisCC, pThis->fGSO);
5519 /* If we're out of bandwidth we'll come back later. */
5520 if (RT_FAILURE(rc))
5521 goto out;
5522 /* Copy the packet to allocated buffer and send it. */
5523 rc = e1kXmitPacket(pDevIns, pThis, fOnWorkerThread);
5524 /* If we're out of bandwidth we'll come back later. */
5525 if (RT_FAILURE(rc))
5526 goto out;
5527 }
5528 uint8_t u8Remain = pThis->nTxDFetched - pThis->iTxDCurrent;
5529 if (RT_UNLIKELY(fIncomplete))
5530 {
5531 static bool fTxDCacheDumped = false;
5532 /*
5533 * The descriptor cache is full, but we were unable to find
5534 * a complete packet in it. Drop the cache and hope that
5535 * the guest driver can recover from network card error.
5536 */
5537 LogRel(("%s: No complete packets in%s TxD cache! "
5538 "Fetched=%d, current=%d, TX len=%d.\n",
5539 pThis->szPrf,
5540 u8Remain == E1K_TXD_CACHE_SIZE ? " full" : "",
5541 pThis->nTxDFetched, pThis->iTxDCurrent,
5542 e1kGetTxLen(pThis)));
5543 if (!fTxDCacheDumped)
5544 {
5545 fTxDCacheDumped = true;
5546 e1kDumpTxDCache(pDevIns, pThis);
5547 }
5548 pThis->iTxDCurrent = pThis->nTxDFetched = 0;
5549 /*
5550 * Returning an error at this point means Guru in R0
5551 * (see @bugref{6428}).
5552 */
5553# ifdef IN_RING3
5554 rc = VERR_NET_INCOMPLETE_TX_PACKET;
5555# else /* !IN_RING3 */
5556 rc = VINF_IOM_R3_MMIO_WRITE;
5557# endif /* !IN_RING3 */
5558 goto out;
5559 }
5560 if (u8Remain > 0)
5561 {
5562 Log4(("%s Incomplete packet at %d. Already fetched %d, "
5563 "%d more are available\n",
5564 pThis->szPrf, pThis->iTxDCurrent, u8Remain,
5565 e1kGetTxLen(pThis) - u8Remain));
5566
5567 /*
5568 * A packet was partially fetched. Move incomplete packet to
5569 * the beginning of cache buffer, then load more descriptors.
5570 */
5571 memmove(pThis->aTxDescriptors,
5572 &pThis->aTxDescriptors[pThis->iTxDCurrent],
5573 u8Remain * sizeof(E1KTXDESC));
5574 pThis->iTxDCurrent = 0;
5575 pThis->nTxDFetched = u8Remain;
5576 e1kTxDLoadMore(pDevIns, pThis);
5577 fIncomplete = true;
5578 }
5579 else
5580 pThis->nTxDFetched = 0;
5581 pThis->iTxDCurrent = 0;
5582 }
5583 if (!pThis->fLocked && GET_BITS(TXDCTL, LWTHRESH) == 0)
5584 {
5585 E1kLog2(("%s Out of transmit descriptors, raise ICR.TXD_LOW\n",
5586 pThis->szPrf));
5587 e1kRaiseInterrupt(pDevIns, pThis, VERR_SEM_BUSY, ICR_TXD_LOW);
5588 }
5589out:
5590 STAM_PROFILE_ADV_STOP(&pThis->CTX_SUFF_Z(StatTransmit), a);
5591
5592 /// @todo uncomment: pThis->uStatIntTXQE++;
5593 /// @todo uncomment: e1kRaiseInterrupt(pDevIns, pThis, ICR_TXQE);
5594
5595 e1kCsTxLeave(pThis);
5596 }
5597
5598
5599 /*
5600 * Release the lock.
5601 */
5602 if (pDrv)
5603 pDrv->pfnEndXmit(pDrv);
5604 return rc;
5605}
5606
5607#endif /* E1K_WITH_TXD_CACHE */
5608#ifdef IN_RING3
5609
5610/**
5611 * @interface_method_impl{PDMINETWORKDOWN,pfnXmitPending}
5612 */
5613static DECLCALLBACK(void) e1kR3NetworkDown_XmitPending(PPDMINETWORKDOWN pInterface)
5614{
5615 PE1KSTATECC pThisCC = RT_FROM_MEMBER(pInterface, E1KSTATECC, INetworkDown);
5616 PE1KSTATE pThis = pThisCC->pShared;
5617 /* Resume suspended transmission */
5618 STATUS &= ~STATUS_TXOFF;
5619 e1kXmitPending(pThisCC->pDevInsR3, pThis, true /*fOnWorkerThread*/);
5620}
5621
5622/**
5623 * @callback_method_impl{FNPDMTASKDEV,
5624 * Executes e1kXmitPending at the behest of ring-0/raw-mode.}
5625 * @note Not executed on EMT.
5626 */
5627static DECLCALLBACK(void) e1kR3TxTaskCallback(PPDMDEVINS pDevIns, void *pvUser)
5628{
5629 PE1KSTATE pThis = PDMDEVINS_2_DATA(pDevIns, PE1KSTATE);
5630 E1kLog2(("%s e1kR3TxTaskCallback:\n", pThis->szPrf));
5631
5632 int rc = e1kXmitPending(pDevIns, pThis, false /*fOnWorkerThread*/);
5633 AssertMsg(RT_SUCCESS(rc) || rc == VERR_TRY_AGAIN || rc == VERR_NET_DOWN, ("%Rrc\n", rc));
5634
5635 RT_NOREF(rc, pvUser);
5636}
5637
5638#endif /* IN_RING3 */
5639
5640/**
5641 * Write handler for Transmit Descriptor Tail register.
5642 *
5643 * @param pThis The device state structure.
5644 * @param offset Register offset in memory-mapped frame.
5645 * @param index Register index in register array.
5646 * @param value The value to store.
5647 * @param mask Used to implement partial writes (8 and 16-bit).
5648 * @thread EMT
5649 */
5650static int e1kRegWriteTDT(PPDMDEVINS pDevIns, PE1KSTATE pThis, uint32_t offset, uint32_t index, uint32_t value)
5651{
5652 int rc = e1kRegWriteDefault(pDevIns, pThis, offset, index, value);
5653
5654 /* All descriptors starting with head and not including tail belong to us. */
5655 /* Process them. */
5656 E1kLog2(("%s e1kRegWriteTDT: TDBAL=%08x, TDBAH=%08x, TDLEN=%08x, TDH=%08x, TDT=%08x\n",
5657 pThis->szPrf, TDBAL, TDBAH, TDLEN, TDH, TDT));
5658
5659 /* Ignore TDT writes when the link is down. */
5660 if (TDH != TDT && (STATUS & STATUS_LU))
5661 {
5662 Log5(("E1000: TDT write: TDH=%08x, TDT=%08x, %d descriptors to process\n", TDH, TDT, e1kGetTxLen(pThis)));
5663 E1kLog(("%s e1kRegWriteTDT: %d descriptors to process\n",
5664 pThis->szPrf, e1kGetTxLen(pThis)));
5665
5666 /* Transmit pending packets if possible, defer it if we cannot do it
5667 in the current context. */
5668#ifdef E1K_TX_DELAY
5669 rc = e1kCsTxEnter(pThis, VERR_SEM_BUSY);
5670 if (RT_LIKELY(rc == VINF_SUCCESS))
5671 {
5672 if (!PDMDevInsTimerIsActive(pDevIns, pThis->hTXDTimer))
5673 {
5674# ifdef E1K_INT_STATS
5675 pThis->u64ArmedAt = RTTimeNanoTS();
5676# endif
5677 e1kArmTimer(pDevIns, pThis, pThis->hTXDTimer, E1K_TX_DELAY);
5678 }
5679 E1K_INC_ISTAT_CNT(pThis->uStatTxDelayed);
5680 e1kCsTxLeave(pThis);
5681 return rc;
5682 }
5683 /* We failed to enter the TX critical section -- transmit as usual. */
5684#endif /* E1K_TX_DELAY */
5685#ifndef IN_RING3
5686 PE1KSTATECC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PE1KSTATECC);
5687 if (!pThisCC->CTX_SUFF(pDrv))
5688 {
5689 PDMDevHlpTaskTrigger(pDevIns, pThis->hTxTask);
5690 rc = VINF_SUCCESS;
5691 }
5692 else
5693#endif
5694 {
5695 rc = e1kXmitPending(pDevIns, pThis, false /*fOnWorkerThread*/);
5696 if (rc == VERR_TRY_AGAIN)
5697 rc = VINF_SUCCESS;
5698#ifndef IN_RING3
5699 else if (rc == VERR_SEM_BUSY)
5700 rc = VINF_IOM_R3_MMIO_WRITE;
5701#endif
5702 AssertRC(rc);
5703 }
5704 }
5705
5706 return rc;
5707}
5708
5709/**
5710 * Write handler for Multicast Table Array registers.
5711 *
5712 * @param pThis The device state structure.
5713 * @param offset Register offset in memory-mapped frame.
5714 * @param index Register index in register array.
5715 * @param value The value to store.
5716 * @thread EMT
5717 */
5718static int e1kRegWriteMTA(PPDMDEVINS pDevIns, PE1KSTATE pThis, uint32_t offset, uint32_t index, uint32_t value)
5719{
5720 RT_NOREF_PV(pDevIns);
5721 AssertReturn(offset - g_aE1kRegMap[index].offset < sizeof(pThis->auMTA), VERR_DEV_IO_ERROR);
5722 pThis->auMTA[(offset - g_aE1kRegMap[index].offset) / sizeof(pThis->auMTA[0])] = value;
5723
5724 return VINF_SUCCESS;
5725}
5726
5727/**
5728 * Read handler for Multicast Table Array registers.
5729 *
5730 * @returns VBox status code.
5731 *
5732 * @param pThis The device state structure.
5733 * @param offset Register offset in memory-mapped frame.
5734 * @param index Register index in register array.
5735 * @thread EMT
5736 */
5737static int e1kRegReadMTA(PPDMDEVINS pDevIns, PE1KSTATE pThis, uint32_t offset, uint32_t index, uint32_t *pu32Value)
5738{
5739 RT_NOREF_PV(pDevIns);
5740 AssertReturn(offset - g_aE1kRegMap[index].offset < sizeof(pThis->auMTA), VERR_DEV_IO_ERROR);
5741 *pu32Value = pThis->auMTA[(offset - g_aE1kRegMap[index].offset)/sizeof(pThis->auMTA[0])];
5742
5743 return VINF_SUCCESS;
5744}
5745
5746/**
5747 * Write handler for Receive Address registers.
5748 *
5749 * @param pThis The device state structure.
5750 * @param offset Register offset in memory-mapped frame.
5751 * @param index Register index in register array.
5752 * @param value The value to store.
5753 * @thread EMT
5754 */
5755static int e1kRegWriteRA(PPDMDEVINS pDevIns, PE1KSTATE pThis, uint32_t offset, uint32_t index, uint32_t value)
5756{
5757 RT_NOREF_PV(pDevIns);
5758 AssertReturn(offset - g_aE1kRegMap[index].offset < sizeof(pThis->aRecAddr.au32), VERR_DEV_IO_ERROR);
5759 pThis->aRecAddr.au32[(offset - g_aE1kRegMap[index].offset)/sizeof(pThis->aRecAddr.au32[0])] = value;
5760
5761 return VINF_SUCCESS;
5762}
5763
5764/**
5765 * Read handler for Receive Address registers.
5766 *
5767 * @returns VBox status code.
5768 *
5769 * @param pThis The device state structure.
5770 * @param offset Register offset in memory-mapped frame.
5771 * @param index Register index in register array.
5772 * @thread EMT
5773 */
5774static int e1kRegReadRA(PPDMDEVINS pDevIns, PE1KSTATE pThis, uint32_t offset, uint32_t index, uint32_t *pu32Value)
5775{
5776 RT_NOREF_PV(pDevIns);
5777 AssertReturn(offset - g_aE1kRegMap[index].offset< sizeof(pThis->aRecAddr.au32), VERR_DEV_IO_ERROR);
5778 *pu32Value = pThis->aRecAddr.au32[(offset - g_aE1kRegMap[index].offset)/sizeof(pThis->aRecAddr.au32[0])];
5779
5780 return VINF_SUCCESS;
5781}
5782
5783/**
5784 * Write handler for VLAN Filter Table Array registers.
5785 *
5786 * @param pThis The device state structure.
5787 * @param offset Register offset in memory-mapped frame.
5788 * @param index Register index in register array.
5789 * @param value The value to store.
5790 * @thread EMT
5791 */
5792static int e1kRegWriteVFTA(PPDMDEVINS pDevIns, PE1KSTATE pThis, uint32_t offset, uint32_t index, uint32_t value)
5793{
5794 RT_NOREF_PV(pDevIns);
5795 AssertReturn(offset - g_aE1kRegMap[index].offset < sizeof(pThis->auVFTA), VINF_SUCCESS);
5796 pThis->auVFTA[(offset - g_aE1kRegMap[index].offset)/sizeof(pThis->auVFTA[0])] = value;
5797
5798 return VINF_SUCCESS;
5799}
5800
5801/**
5802 * Read handler for VLAN Filter Table Array registers.
5803 *
5804 * @returns VBox status code.
5805 *
5806 * @param pThis The device state structure.
5807 * @param offset Register offset in memory-mapped frame.
5808 * @param index Register index in register array.
5809 * @thread EMT
5810 */
5811static int e1kRegReadVFTA(PPDMDEVINS pDevIns, PE1KSTATE pThis, uint32_t offset, uint32_t index, uint32_t *pu32Value)
5812{
5813 RT_NOREF_PV(pDevIns);
5814 AssertReturn(offset - g_aE1kRegMap[index].offset< sizeof(pThis->auVFTA), VERR_DEV_IO_ERROR);
5815 *pu32Value = pThis->auVFTA[(offset - g_aE1kRegMap[index].offset)/sizeof(pThis->auVFTA[0])];
5816
5817 return VINF_SUCCESS;
5818}
5819
5820/**
5821 * Read handler for unimplemented registers.
5822 *
5823 * Merely reports reads from unimplemented registers.
5824 *
5825 * @returns VBox status code.
5826 *
5827 * @param pThis The device state structure.
5828 * @param offset Register offset in memory-mapped frame.
5829 * @param index Register index in register array.
5830 * @thread EMT
5831 */
5832static int e1kRegReadUnimplemented(PPDMDEVINS pDevIns, PE1KSTATE pThis, uint32_t offset, uint32_t index, uint32_t *pu32Value)
5833{
5834 RT_NOREF(pDevIns, pThis, offset, index);
5835 E1kLog(("%s At %08X read (00000000) attempt from unimplemented register %s (%s)\n",
5836 pThis->szPrf, offset, g_aE1kRegMap[index].abbrev, g_aE1kRegMap[index].name));
5837 *pu32Value = 0;
5838
5839 return VINF_SUCCESS;
5840}
5841
5842/**
5843 * Default register read handler with automatic clear operation.
5844 *
5845 * Retrieves the value of register from register array in device state structure.
5846 * Then resets all bits.
5847 *
5848 * @remarks The 'mask' parameter is simply ignored as masking and shifting is
5849 * done in the caller.
5850 *
5851 * @returns VBox status code.
5852 *
5853 * @param pThis The device state structure.
5854 * @param offset Register offset in memory-mapped frame.
5855 * @param index Register index in register array.
5856 * @thread EMT
5857 */
5858static int e1kRegReadAutoClear(PPDMDEVINS pDevIns, PE1KSTATE pThis, uint32_t offset, uint32_t index, uint32_t *pu32Value)
5859{
5860 AssertReturn(index < E1K_NUM_OF_32BIT_REGS, VERR_DEV_IO_ERROR);
5861 int rc = e1kRegReadDefault(pDevIns, pThis, offset, index, pu32Value);
5862 pThis->auRegs[index] = 0;
5863
5864 return rc;
5865}
5866
5867/**
5868 * Default register read handler.
5869 *
5870 * Retrieves the value of register from register array in device state structure.
5871 * Bits corresponding to 0s in 'readable' mask will always read as 0s.
5872 *
5873 * @remarks The 'mask' parameter is simply ignored as masking and shifting is
5874 * done in the caller.
5875 *
5876 * @returns VBox status code.
5877 *
5878 * @param pThis The device state structure.
5879 * @param offset Register offset in memory-mapped frame.
5880 * @param index Register index in register array.
5881 * @thread EMT
5882 */
5883static int e1kRegReadDefault(PPDMDEVINS pDevIns, PE1KSTATE pThis, uint32_t offset, uint32_t index, uint32_t *pu32Value)
5884{
5885 RT_NOREF_PV(pDevIns); RT_NOREF_PV(offset);
5886
5887 AssertReturn(index < E1K_NUM_OF_32BIT_REGS, VERR_DEV_IO_ERROR);
5888 *pu32Value = pThis->auRegs[index] & g_aE1kRegMap[index].readable;
5889
5890 return VINF_SUCCESS;
5891}
5892
5893/**
5894 * Write handler for unimplemented registers.
5895 *
5896 * Merely reports writes to unimplemented registers.
5897 *
5898 * @param pThis The device state structure.
5899 * @param offset Register offset in memory-mapped frame.
5900 * @param index Register index in register array.
5901 * @param value The value to store.
5902 * @thread EMT
5903 */
5904
5905 static int e1kRegWriteUnimplemented(PPDMDEVINS pDevIns, PE1KSTATE pThis, uint32_t offset, uint32_t index, uint32_t value)
5906{
5907 RT_NOREF_PV(pDevIns); RT_NOREF_PV(pThis); RT_NOREF_PV(offset); RT_NOREF_PV(index); RT_NOREF_PV(value);
5908
5909 E1kLog(("%s At %08X write attempt (%08X) to unimplemented register %s (%s)\n",
5910 pThis->szPrf, offset, value, g_aE1kRegMap[index].abbrev, g_aE1kRegMap[index].name));
5911
5912 return VINF_SUCCESS;
5913}
5914
5915/**
5916 * Default register write handler.
5917 *
5918 * Stores the value to the register array in device state structure. Only bits
5919 * corresponding to 1s both in 'writable' and 'mask' will be stored.
5920 *
5921 * @returns VBox status code.
5922 *
5923 * @param pThis The device state structure.
5924 * @param offset Register offset in memory-mapped frame.
5925 * @param index Register index in register array.
5926 * @param value The value to store.
5927 * @param mask Used to implement partial writes (8 and 16-bit).
5928 * @thread EMT
5929 */
5930
5931static int e1kRegWriteDefault(PPDMDEVINS pDevIns, PE1KSTATE pThis, uint32_t offset, uint32_t index, uint32_t value)
5932{
5933 RT_NOREF(pDevIns, offset);
5934
5935 AssertReturn(index < E1K_NUM_OF_32BIT_REGS, VERR_DEV_IO_ERROR);
5936 pThis->auRegs[index] = (value & g_aE1kRegMap[index].writable)
5937 | (pThis->auRegs[index] & ~g_aE1kRegMap[index].writable);
5938
5939 return VINF_SUCCESS;
5940}
5941
5942/**
5943 * Search register table for matching register.
5944 *
5945 * @returns Index in the register table or -1 if not found.
5946 *
5947 * @param offReg Register offset in memory-mapped region.
5948 * @thread EMT
5949 */
5950static int e1kRegLookup(uint32_t offReg)
5951{
5952
5953#if 0
5954 int index;
5955
5956 for (index = 0; index < E1K_NUM_OF_REGS; index++)
5957 {
5958 if (g_aE1kRegMap[index].offset <= offReg && offReg < g_aE1kRegMap[index].offset + g_aE1kRegMap[index].size)
5959 {
5960 return index;
5961 }
5962 }
5963#else
5964 int iStart = 0;
5965 int iEnd = E1K_NUM_OF_BINARY_SEARCHABLE;
5966 for (;;)
5967 {
5968 int i = (iEnd - iStart) / 2 + iStart;
5969 uint32_t offCur = g_aE1kRegMap[i].offset;
5970 if (offReg < offCur)
5971 {
5972 if (i == iStart)
5973 break;
5974 iEnd = i;
5975 }
5976 else if (offReg >= offCur + g_aE1kRegMap[i].size)
5977 {
5978 i++;
5979 if (i == iEnd)
5980 break;
5981 iStart = i;
5982 }
5983 else
5984 return i;
5985 Assert(iEnd > iStart);
5986 }
5987
5988 for (unsigned i = E1K_NUM_OF_BINARY_SEARCHABLE; i < RT_ELEMENTS(g_aE1kRegMap); i++)
5989 if (offReg - g_aE1kRegMap[i].offset < g_aE1kRegMap[i].size)
5990 return (int)i;
5991
5992# ifdef VBOX_STRICT
5993 for (unsigned i = 0; i < RT_ELEMENTS(g_aE1kRegMap); i++)
5994 Assert(offReg - g_aE1kRegMap[i].offset >= g_aE1kRegMap[i].size);
5995# endif
5996
5997#endif
5998
5999 return -1;
6000}
6001
6002/**
6003 * Handle unaligned register read operation.
6004 *
6005 * Looks up and calls appropriate handler.
6006 *
6007 * @returns VBox status code.
6008 *
6009 * @param pDevIns The device instance.
6010 * @param pThis The device state structure.
6011 * @param offReg Register offset in memory-mapped frame.
6012 * @param pv Where to store the result.
6013 * @param cb Number of bytes to read.
6014 * @thread EMT
6015 * @remarks IOM takes care of unaligned and small reads via MMIO. For I/O port
6016 * accesses we have to take care of that ourselves.
6017 */
6018static int e1kRegReadUnaligned(PPDMDEVINS pDevIns, PE1KSTATE pThis, uint32_t offReg, void *pv, uint32_t cb)
6019{
6020 uint32_t u32 = 0;
6021 uint32_t shift;
6022 int rc = VINF_SUCCESS;
6023 int index = e1kRegLookup(offReg);
6024#ifdef LOG_ENABLED
6025 char buf[9];
6026#endif
6027
6028 /*
6029 * From the spec:
6030 * For registers that should be accessed as 32-bit double words, partial writes (less than a 32-bit
6031 * double word) is ignored. Partial reads return all 32 bits of data regardless of the byte enables.
6032 */
6033
6034 /*
6035 * To be able to read bytes and short word we convert them to properly
6036 * shifted 32-bit words and masks. The idea is to keep register-specific
6037 * handlers simple. Most accesses will be 32-bit anyway.
6038 */
6039 uint32_t mask;
6040 switch (cb)
6041 {
6042 case 4: mask = 0xFFFFFFFF; break;
6043 case 2: mask = 0x0000FFFF; break;
6044 case 1: mask = 0x000000FF; break;
6045 default:
6046 return PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "unsupported op size: offset=%#10x cb=%#10x\n", offReg, cb);
6047 }
6048 if (index >= 0)
6049 {
6050 RT_UNTRUSTED_VALIDATED_FENCE(); /* paranoia because of port I/O. */
6051 if (g_aE1kRegMap[index].readable)
6052 {
6053 /* Make the mask correspond to the bits we are about to read. */
6054 shift = (offReg - g_aE1kRegMap[index].offset) % sizeof(uint32_t) * 8;
6055 mask <<= shift;
6056 if (!mask)
6057 return PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "Zero mask: offset=%#10x cb=%#10x\n", offReg, cb);
6058 /*
6059 * Read it. Pass the mask so the handler knows what has to be read.
6060 * Mask out irrelevant bits.
6061 */
6062 //rc = e1kCsEnter(pThis, VERR_SEM_BUSY, RT_SRC_POS);
6063 if (RT_UNLIKELY(rc != VINF_SUCCESS))
6064 return rc;
6065 //pThis->fDelayInts = false;
6066 //pThis->iStatIntLost += pThis->iStatIntLostOne;
6067 //pThis->iStatIntLostOne = 0;
6068 rc = g_aE1kRegMap[index].pfnRead(pDevIns, pThis, offReg & 0xFFFFFFFC, (uint32_t)index, &u32);
6069 u32 &= mask;
6070 //e1kCsLeave(pThis);
6071 E1kLog2(("%s At %08X read %s from %s (%s)\n",
6072 pThis->szPrf, offReg, e1kU32toHex(u32, mask, buf), g_aE1kRegMap[index].abbrev, g_aE1kRegMap[index].name));
6073 Log6(("%s At %08X read %s from %s (%s) [UNALIGNED]\n",
6074 pThis->szPrf, offReg, e1kU32toHex(u32, mask, buf), g_aE1kRegMap[index].abbrev, g_aE1kRegMap[index].name));
6075 /* Shift back the result. */
6076 u32 >>= shift;
6077 }
6078 else
6079 E1kLog(("%s At %08X read (%s) attempt from write-only register %s (%s)\n",
6080 pThis->szPrf, offReg, e1kU32toHex(u32, mask, buf), g_aE1kRegMap[index].abbrev, g_aE1kRegMap[index].name));
6081 if (IOM_SUCCESS(rc))
6082 STAM_COUNTER_INC(&pThis->aStatRegReads[index]);
6083 }
6084 else
6085 E1kLog(("%s At %08X read (%s) attempt from non-existing register\n",
6086 pThis->szPrf, offReg, e1kU32toHex(u32, mask, buf)));
6087
6088 memcpy(pv, &u32, cb);
6089 return rc;
6090}
6091
6092/**
6093 * Handle 4 byte aligned and sized read operation.
6094 *
6095 * Looks up and calls appropriate handler.
6096 *
6097 * @returns VBox status code.
6098 *
6099 * @param pDevIns The device instance.
6100 * @param pThis The device state structure.
6101 * @param offReg Register offset in memory-mapped frame.
6102 * @param pu32 Where to store the result.
6103 * @thread EMT
6104 */
6105static VBOXSTRICTRC e1kRegReadAlignedU32(PPDMDEVINS pDevIns, PE1KSTATE pThis, uint32_t offReg, uint32_t *pu32)
6106{
6107 Assert(!(offReg & 3));
6108
6109 /*
6110 * Lookup the register and check that it's readable.
6111 */
6112 VBOXSTRICTRC rc = VINF_SUCCESS;
6113 int idxReg = e1kRegLookup(offReg);
6114 if (RT_LIKELY(idxReg >= 0))
6115 {
6116 RT_UNTRUSTED_VALIDATED_FENCE(); /* paranoia because of port I/O. */
6117 if (RT_UNLIKELY(g_aE1kRegMap[idxReg].readable))
6118 {
6119 /*
6120 * Read it. Pass the mask so the handler knows what has to be read.
6121 * Mask out irrelevant bits.
6122 */
6123 //rc = e1kCsEnter(pThis, VERR_SEM_BUSY, RT_SRC_POS);
6124 //if (RT_UNLIKELY(rc != VINF_SUCCESS))
6125 // return rc;
6126 //pThis->fDelayInts = false;
6127 //pThis->iStatIntLost += pThis->iStatIntLostOne;
6128 //pThis->iStatIntLostOne = 0;
6129 rc = g_aE1kRegMap[idxReg].pfnRead(pDevIns, pThis, offReg & 0xFFFFFFFC, (uint32_t)idxReg, pu32);
6130 //e1kCsLeave(pThis);
6131 Log6(("%s At %08X read %08X from %s (%s)\n",
6132 pThis->szPrf, offReg, *pu32, g_aE1kRegMap[idxReg].abbrev, g_aE1kRegMap[idxReg].name));
6133 if (IOM_SUCCESS(rc))
6134 STAM_COUNTER_INC(&pThis->aStatRegReads[idxReg]);
6135 }
6136 else
6137 E1kLog(("%s At %08X read attempt from non-readable register %s (%s)\n",
6138 pThis->szPrf, offReg, g_aE1kRegMap[idxReg].abbrev, g_aE1kRegMap[idxReg].name));
6139 }
6140 else
6141 E1kLog(("%s At %08X read attempt from non-existing register\n", pThis->szPrf, offReg));
6142 return rc;
6143}
6144
6145/**
6146 * Handle 4 byte sized and aligned register write operation.
6147 *
6148 * Looks up and calls appropriate handler.
6149 *
6150 * @returns VBox status code.
6151 *
6152 * @param pDevIns The device instance.
6153 * @param pThis The device state structure.
6154 * @param offReg Register offset in memory-mapped frame.
6155 * @param u32Value The value to write.
6156 * @thread EMT
6157 */
6158static VBOXSTRICTRC e1kRegWriteAlignedU32(PPDMDEVINS pDevIns, PE1KSTATE pThis, uint32_t offReg, uint32_t u32Value)
6159{
6160 VBOXSTRICTRC rc = VINF_SUCCESS;
6161 int index = e1kRegLookup(offReg);
6162 if (RT_LIKELY(index >= 0))
6163 {
6164 RT_UNTRUSTED_VALIDATED_FENCE(); /* paranoia because of port I/O. */
6165 if (RT_LIKELY(g_aE1kRegMap[index].writable))
6166 {
6167 /*
6168 * Write it. Pass the mask so the handler knows what has to be written.
6169 * Mask out irrelevant bits.
6170 */
6171 Log6(("%s At %08X write %08X to %s (%s)\n",
6172 pThis->szPrf, offReg, u32Value, g_aE1kRegMap[index].abbrev, g_aE1kRegMap[index].name));
6173 //rc = e1kCsEnter(pThis, VERR_SEM_BUSY, RT_SRC_POS);
6174 //if (RT_UNLIKELY(rc != VINF_SUCCESS))
6175 // return rc;
6176 //pThis->fDelayInts = false;
6177 //pThis->iStatIntLost += pThis->iStatIntLostOne;
6178 //pThis->iStatIntLostOne = 0;
6179 rc = g_aE1kRegMap[index].pfnWrite(pDevIns, pThis, offReg, (uint32_t)index, u32Value);
6180 //e1kCsLeave(pThis);
6181 }
6182 else
6183 E1kLog(("%s At %08X write attempt (%08X) to read-only register %s (%s)\n",
6184 pThis->szPrf, offReg, u32Value, g_aE1kRegMap[index].abbrev, g_aE1kRegMap[index].name));
6185 if (IOM_SUCCESS(rc))
6186 STAM_COUNTER_INC(&pThis->aStatRegWrites[index]);
6187 }
6188 else
6189 E1kLog(("%s At %08X write attempt (%08X) to non-existing register\n",
6190 pThis->szPrf, offReg, u32Value));
6191 return rc;
6192}
6193
6194
6195/* -=-=-=-=- MMIO and I/O Port Callbacks -=-=-=-=- */
6196
6197/**
6198 * @callback_method_impl{FNIOMMMIONEWREAD}
6199 */
6200static DECLCALLBACK(VBOXSTRICTRC) e1kMMIORead(PPDMDEVINS pDevIns, void *pvUser, RTGCPHYS off, void *pv, uint32_t cb)
6201{
6202 RT_NOREF2(pvUser, cb);
6203 PE1KSTATE pThis = PDMDEVINS_2_DATA(pDevIns, PE1KSTATE);
6204 STAM_PROFILE_ADV_START(&pThis->CTX_SUFF_Z(StatMMIORead), a);
6205
6206 Assert(off < E1K_MM_SIZE);
6207 Assert(cb == 4);
6208 Assert(!(off & 3));
6209
6210 VBOXSTRICTRC rcStrict = e1kRegReadAlignedU32(pDevIns, pThis, (uint32_t)off, (uint32_t *)pv);
6211
6212 STAM_PROFILE_ADV_STOP(&pThis->CTX_SUFF_Z(StatMMIORead), a);
6213 return rcStrict;
6214}
6215
6216/**
6217 * @callback_method_impl{FNIOMMMIONEWWRITE}
6218 */
6219static DECLCALLBACK(VBOXSTRICTRC) e1kMMIOWrite(PPDMDEVINS pDevIns, void *pvUser, RTGCPHYS off, void const *pv, uint32_t cb)
6220{
6221 RT_NOREF2(pvUser, cb);
6222 PE1KSTATE pThis = PDMDEVINS_2_DATA(pDevIns, PE1KSTATE);
6223 STAM_PROFILE_ADV_START(&pThis->CTX_SUFF_Z(StatMMIOWrite), a);
6224
6225 Assert(off < E1K_MM_SIZE);
6226 Assert(cb == 4);
6227 Assert(!(off & 3));
6228
6229 VBOXSTRICTRC rcStrict = e1kRegWriteAlignedU32(pDevIns, pThis, (uint32_t)off, *(uint32_t const *)pv);
6230
6231 STAM_PROFILE_ADV_STOP(&pThis->CTX_SUFF_Z(StatMMIOWrite), a);
6232 return rcStrict;
6233}
6234
6235/**
6236 * @callback_method_impl{FNIOMIOPORTNEWIN}
6237 */
6238static DECLCALLBACK(VBOXSTRICTRC) e1kIOPortIn(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT offPort, uint32_t *pu32, unsigned cb)
6239{
6240 PE1KSTATE pThis = PDMDEVINS_2_DATA(pDevIns, PE1KSTATE);
6241 VBOXSTRICTRC rc;
6242 STAM_PROFILE_ADV_START(&pThis->CTX_SUFF_Z(StatIORead), a);
6243 RT_NOREF_PV(pvUser);
6244
6245 if (RT_LIKELY(cb == 4))
6246 switch (offPort)
6247 {
6248 case 0x00: /* IOADDR */
6249 *pu32 = pThis->uSelectedReg;
6250 E1kLog2(("%s e1kIOPortIn: IOADDR(0), selecting register %#010x, val=%#010x\n", pThis->szPrf, pThis->uSelectedReg, *pu32));
6251 rc = VINF_SUCCESS;
6252 break;
6253
6254 case 0x04: /* IODATA */
6255 if (!(pThis->uSelectedReg & 3))
6256 rc = e1kRegReadAlignedU32(pDevIns, pThis, pThis->uSelectedReg, pu32);
6257 else /** @todo r=bird: I wouldn't be surprised if this unaligned branch wasn't necessary. */
6258 rc = e1kRegReadUnaligned(pDevIns, pThis, pThis->uSelectedReg, pu32, cb);
6259 if (rc == VINF_IOM_R3_MMIO_READ)
6260 rc = VINF_IOM_R3_IOPORT_READ;
6261 E1kLog2(("%s e1kIOPortIn: IODATA(4), reading from selected register %#010x, val=%#010x\n", pThis->szPrf, pThis->uSelectedReg, *pu32));
6262 break;
6263
6264 default:
6265 E1kLog(("%s e1kIOPortIn: invalid port %#010x\n", pThis->szPrf, offPort));
6266 /** @todo r=bird: Check what real hardware returns here. */
6267 //rc = VERR_IOM_IOPORT_UNUSED; /* Why not? */
6268 rc = VINF_IOM_MMIO_UNUSED_00; /* used to return VINF_SUCCESS and not touch *pu32, which amounted to this. */
6269 break;
6270 }
6271 else
6272 {
6273 E1kLog(("%s e1kIOPortIn: invalid op size: offPort=%RTiop cb=%08x", pThis->szPrf, offPort, cb));
6274 rc = PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "%s e1kIOPortIn: invalid op size: offPort=%RTiop cb=%08x\n", pThis->szPrf, offPort, cb);
6275 *pu32 = 0; /** @todo r=bird: Check what real hardware returns here. (Didn't used to set a value here, picked zero as that's what we'd end up in most cases.) */
6276 }
6277 STAM_PROFILE_ADV_STOP(&pThis->CTX_SUFF_Z(StatIORead), a);
6278 return rc;
6279}
6280
6281
6282/**
6283 * @callback_method_impl{FNIOMIOPORTNEWOUT}
6284 */
6285static DECLCALLBACK(VBOXSTRICTRC) e1kIOPortOut(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT offPort, uint32_t u32, unsigned cb)
6286{
6287 PE1KSTATE pThis = PDMDEVINS_2_DATA(pDevIns, PE1KSTATE);
6288 VBOXSTRICTRC rc;
6289 STAM_PROFILE_ADV_START(&pThis->CTX_SUFF_Z(StatIOWrite), a);
6290 RT_NOREF_PV(pvUser);
6291
6292 E1kLog2(("%s e1kIOPortOut: offPort=%RTiop value=%08x\n", pThis->szPrf, offPort, u32));
6293 if (RT_LIKELY(cb == 4))
6294 {
6295 switch (offPort)
6296 {
6297 case 0x00: /* IOADDR */
6298 pThis->uSelectedReg = u32;
6299 E1kLog2(("%s e1kIOPortOut: IOADDR(0), selected register %08x\n", pThis->szPrf, pThis->uSelectedReg));
6300 rc = VINF_SUCCESS;
6301 break;
6302
6303 case 0x04: /* IODATA */
6304 E1kLog2(("%s e1kIOPortOut: IODATA(4), writing to selected register %#010x, value=%#010x\n", pThis->szPrf, pThis->uSelectedReg, u32));
6305 if (RT_LIKELY(!(pThis->uSelectedReg & 3)))
6306 {
6307 rc = e1kRegWriteAlignedU32(pDevIns, pThis, pThis->uSelectedReg, u32);
6308 if (rc == VINF_IOM_R3_MMIO_WRITE)
6309 rc = VINF_IOM_R3_IOPORT_WRITE;
6310 }
6311 else
6312 rc = PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS,
6313 "Spec violation: misaligned offset: %#10x, ignored.\n", pThis->uSelectedReg);
6314 break;
6315
6316 default:
6317 E1kLog(("%s e1kIOPortOut: invalid port %#010x\n", pThis->szPrf, offPort));
6318 rc = PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "invalid port %#010x\n", offPort);
6319 }
6320 }
6321 else
6322 {
6323 E1kLog(("%s e1kIOPortOut: invalid op size: offPort=%RTiop cb=%08x\n", pThis->szPrf, offPort, cb));
6324 rc = PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "%s: invalid op size: offPort=%RTiop cb=%#x\n", pThis->szPrf, offPort, cb);
6325 }
6326
6327 STAM_PROFILE_ADV_STOP(&pThis->CTX_SUFF_Z(StatIOWrite), a);
6328 return rc;
6329}
6330
6331#ifdef IN_RING3
6332
6333/**
6334 * Dump complete device state to log.
6335 *
6336 * @param pThis Pointer to device state.
6337 */
6338static void e1kDumpState(PE1KSTATE pThis)
6339{
6340 RT_NOREF(pThis);
6341 for (int i = 0; i < E1K_NUM_OF_32BIT_REGS; ++i)
6342 E1kLog2(("%s: %8.8s = %08x\n", pThis->szPrf, g_aE1kRegMap[i].abbrev, pThis->auRegs[i]));
6343# ifdef E1K_INT_STATS
6344 LogRel(("%s: Interrupt attempts: %d\n", pThis->szPrf, pThis->uStatIntTry));
6345 LogRel(("%s: Interrupts raised : %d\n", pThis->szPrf, pThis->uStatInt));
6346 LogRel(("%s: Interrupts lowered: %d\n", pThis->szPrf, pThis->uStatIntLower));
6347 LogRel(("%s: ICR outside ISR : %d\n", pThis->szPrf, pThis->uStatNoIntICR));
6348 LogRel(("%s: IMS raised ints : %d\n", pThis->szPrf, pThis->uStatIntIMS));
6349 LogRel(("%s: Interrupts skipped: %d\n", pThis->szPrf, pThis->uStatIntSkip));
6350 LogRel(("%s: Masked interrupts : %d\n", pThis->szPrf, pThis->uStatIntMasked));
6351 LogRel(("%s: Early interrupts : %d\n", pThis->szPrf, pThis->uStatIntEarly));
6352 LogRel(("%s: Late interrupts : %d\n", pThis->szPrf, pThis->uStatIntLate));
6353 LogRel(("%s: Lost interrupts : %d\n", pThis->szPrf, pThis->iStatIntLost));
6354 LogRel(("%s: Interrupts by RX : %d\n", pThis->szPrf, pThis->uStatIntRx));
6355 LogRel(("%s: Interrupts by TX : %d\n", pThis->szPrf, pThis->uStatIntTx));
6356 LogRel(("%s: Interrupts by ICS : %d\n", pThis->szPrf, pThis->uStatIntICS));
6357 LogRel(("%s: Interrupts by RDTR: %d\n", pThis->szPrf, pThis->uStatIntRDTR));
6358 LogRel(("%s: Interrupts by RDMT: %d\n", pThis->szPrf, pThis->uStatIntRXDMT0));
6359 LogRel(("%s: Interrupts by TXQE: %d\n", pThis->szPrf, pThis->uStatIntTXQE));
6360 LogRel(("%s: TX int delay asked: %d\n", pThis->szPrf, pThis->uStatTxIDE));
6361 LogRel(("%s: TX delayed: %d\n", pThis->szPrf, pThis->uStatTxDelayed));
6362 LogRel(("%s: TX delay expired: %d\n", pThis->szPrf, pThis->uStatTxDelayExp));
6363 LogRel(("%s: TX no report asked: %d\n", pThis->szPrf, pThis->uStatTxNoRS));
6364 LogRel(("%s: TX abs timer expd : %d\n", pThis->szPrf, pThis->uStatTAD));
6365 LogRel(("%s: TX int timer expd : %d\n", pThis->szPrf, pThis->uStatTID));
6366 LogRel(("%s: RX abs timer expd : %d\n", pThis->szPrf, pThis->uStatRAD));
6367 LogRel(("%s: RX int timer expd : %d\n", pThis->szPrf, pThis->uStatRID));
6368 LogRel(("%s: TX CTX descriptors: %d\n", pThis->szPrf, pThis->uStatDescCtx));
6369 LogRel(("%s: TX DAT descriptors: %d\n", pThis->szPrf, pThis->uStatDescDat));
6370 LogRel(("%s: TX LEG descriptors: %d\n", pThis->szPrf, pThis->uStatDescLeg));
6371 LogRel(("%s: Received frames : %d\n", pThis->szPrf, pThis->uStatRxFrm));
6372 LogRel(("%s: Transmitted frames: %d\n", pThis->szPrf, pThis->uStatTxFrm));
6373 LogRel(("%s: TX frames up to 1514: %d\n", pThis->szPrf, pThis->uStatTx1514));
6374 LogRel(("%s: TX frames up to 2962: %d\n", pThis->szPrf, pThis->uStatTx2962));
6375 LogRel(("%s: TX frames up to 4410: %d\n", pThis->szPrf, pThis->uStatTx4410));
6376 LogRel(("%s: TX frames up to 5858: %d\n", pThis->szPrf, pThis->uStatTx5858));
6377 LogRel(("%s: TX frames up to 7306: %d\n", pThis->szPrf, pThis->uStatTx7306));
6378 LogRel(("%s: TX frames up to 8754: %d\n", pThis->szPrf, pThis->uStatTx8754));
6379 LogRel(("%s: TX frames up to 16384: %d\n", pThis->szPrf, pThis->uStatTx16384));
6380 LogRel(("%s: TX frames up to 32768: %d\n", pThis->szPrf, pThis->uStatTx32768));
6381 LogRel(("%s: Larger TX frames : %d\n", pThis->szPrf, pThis->uStatTxLarge));
6382 LogRel(("%s: Max TX Delay : %lld\n", pThis->szPrf, pThis->uStatMaxTxDelay));
6383# endif /* E1K_INT_STATS */
6384}
6385
6386
6387/* -=-=-=-=- PDMINETWORKDOWN -=-=-=-=- */
6388
6389/**
6390 * Check if the device can receive data now.
6391 * This must be called before the pfnRecieve() method is called.
6392 *
6393 * @returns Number of bytes the device can receive.
6394 * @param pDevIns The device instance.
6395 * @param pThis The instance data.
6396 * @thread EMT
6397 */
6398static int e1kCanReceive(PPDMDEVINS pDevIns, PE1KSTATE pThis)
6399{
6400#ifndef E1K_WITH_RXD_CACHE
6401 size_t cb;
6402
6403 if (RT_UNLIKELY(e1kCsRxEnter(pThis, VERR_SEM_BUSY) != VINF_SUCCESS))
6404 return VERR_NET_NO_BUFFER_SPACE;
6405
6406 if (RT_UNLIKELY(RDLEN == sizeof(E1KRXDESC)))
6407 {
6408 E1KRXDESC desc;
6409 PDMDevHlpPhysRead(pDevIns, e1kDescAddr(RDBAH, RDBAL, RDH), &desc, sizeof(desc));
6410 if (desc.status.fDD)
6411 cb = 0;
6412 else
6413 cb = pThis->u16RxBSize;
6414 }
6415 else if (RDH < RDT)
6416 cb = (RDT - RDH) * pThis->u16RxBSize;
6417 else if (RDH > RDT)
6418 cb = (RDLEN/sizeof(E1KRXDESC) - RDH + RDT) * pThis->u16RxBSize;
6419 else
6420 {
6421 cb = 0;
6422 E1kLogRel(("E1000: OUT of RX descriptors!\n"));
6423 }
6424 E1kLog2(("%s e1kCanReceive: at exit RDH=%d RDT=%d RDLEN=%d u16RxBSize=%d cb=%lu\n",
6425 pThis->szPrf, RDH, RDT, RDLEN, pThis->u16RxBSize, cb));
6426
6427 e1kCsRxLeave(pThis);
6428 return cb > 0 ? VINF_SUCCESS : VERR_NET_NO_BUFFER_SPACE;
6429#else /* E1K_WITH_RXD_CACHE */
6430 int rc = VINF_SUCCESS;
6431
6432 if (RT_UNLIKELY(e1kCsRxEnter(pThis, VERR_SEM_BUSY) != VINF_SUCCESS))
6433 return VERR_NET_NO_BUFFER_SPACE;
6434
6435 if (RT_UNLIKELY(RDLEN == sizeof(E1KRXDESC)))
6436 {
6437 E1KRXDESC desc;
6438 PDMDevHlpPhysRead(pDevIns, e1kDescAddr(RDBAH, RDBAL, RDH), &desc, sizeof(desc));
6439 if (desc.status.fDD)
6440 rc = VERR_NET_NO_BUFFER_SPACE;
6441 }
6442 else if (e1kRxDIsCacheEmpty(pThis) && RDH == RDT)
6443 {
6444 /* Cache is empty, so is the RX ring. */
6445 rc = VERR_NET_NO_BUFFER_SPACE;
6446 }
6447 E1kLog2(("%s e1kCanReceive: at exit in_cache=%d RDH=%d RDT=%d RDLEN=%d"
6448 " u16RxBSize=%d rc=%Rrc\n", pThis->szPrf,
6449 e1kRxDInCache(pThis), RDH, RDT, RDLEN, pThis->u16RxBSize, rc));
6450
6451 e1kCsRxLeave(pThis);
6452 return rc;
6453#endif /* E1K_WITH_RXD_CACHE */
6454}
6455
6456/**
6457 * @interface_method_impl{PDMINETWORKDOWN,pfnWaitReceiveAvail}
6458 */
6459static DECLCALLBACK(int) e1kR3NetworkDown_WaitReceiveAvail(PPDMINETWORKDOWN pInterface, RTMSINTERVAL cMillies)
6460{
6461 PE1KSTATECC pThisCC = RT_FROM_MEMBER(pInterface, E1KSTATECC, INetworkDown);
6462 PE1KSTATE pThis = pThisCC->pShared;
6463 PPDMDEVINS pDevIns = pThisCC->pDevInsR3;
6464
6465 int rc = e1kCanReceive(pDevIns, pThis);
6466
6467 if (RT_SUCCESS(rc))
6468 return VINF_SUCCESS;
6469 if (RT_UNLIKELY(cMillies == 0))
6470 return VERR_NET_NO_BUFFER_SPACE;
6471
6472 rc = VERR_INTERRUPTED;
6473 ASMAtomicXchgBool(&pThis->fMaybeOutOfSpace, true);
6474 STAM_PROFILE_START(&pThis->StatRxOverflow, a);
6475 VMSTATE enmVMState;
6476 while (RT_LIKELY( (enmVMState = PDMDevHlpVMState(pDevIns)) == VMSTATE_RUNNING
6477 || enmVMState == VMSTATE_RUNNING_LS))
6478 {
6479 int rc2 = e1kCanReceive(pDevIns, pThis);
6480 if (RT_SUCCESS(rc2))
6481 {
6482 rc = VINF_SUCCESS;
6483 break;
6484 }
6485 E1kLogRel(("E1000: e1kR3NetworkDown_WaitReceiveAvail: waiting cMillies=%u...\n", cMillies));
6486 E1kLog(("%s: e1kR3NetworkDown_WaitReceiveAvail: waiting cMillies=%u...\n", pThis->szPrf, cMillies));
6487 PDMDevHlpSUPSemEventWaitNoResume(pDevIns, pThis->hEventMoreRxDescAvail, cMillies);
6488 }
6489 STAM_PROFILE_STOP(&pThis->StatRxOverflow, a);
6490 ASMAtomicXchgBool(&pThis->fMaybeOutOfSpace, false);
6491
6492 return rc;
6493}
6494
6495
6496/**
6497 * Matches the packet addresses against Receive Address table. Looks for
6498 * exact matches only.
6499 *
6500 * @returns true if address matches.
6501 * @param pThis Pointer to the state structure.
6502 * @param pvBuf The ethernet packet.
6503 * @param cb Number of bytes available in the packet.
6504 * @thread EMT
6505 */
6506static bool e1kPerfectMatch(PE1KSTATE pThis, const void *pvBuf)
6507{
6508 for (unsigned i = 0; i < RT_ELEMENTS(pThis->aRecAddr.array); i++)
6509 {
6510 E1KRAELEM* ra = pThis->aRecAddr.array + i;
6511
6512 /* Valid address? */
6513 if (ra->ctl & RA_CTL_AV)
6514 {
6515 Assert((ra->ctl & RA_CTL_AS) < 2);
6516 //unsigned char *pAddr = (unsigned char*)pvBuf + sizeof(ra->addr)*(ra->ctl & RA_CTL_AS);
6517 //E1kLog3(("%s Matching %02x:%02x:%02x:%02x:%02x:%02x against %02x:%02x:%02x:%02x:%02x:%02x...\n",
6518 // pThis->szPrf, pAddr[0], pAddr[1], pAddr[2], pAddr[3], pAddr[4], pAddr[5],
6519 // ra->addr[0], ra->addr[1], ra->addr[2], ra->addr[3], ra->addr[4], ra->addr[5]));
6520 /*
6521 * Address Select:
6522 * 00b = Destination address
6523 * 01b = Source address
6524 * 10b = Reserved
6525 * 11b = Reserved
6526 * Since ethernet header is (DA, SA, len) we can use address
6527 * select as index.
6528 */
6529 if (memcmp((char*)pvBuf + sizeof(ra->addr)*(ra->ctl & RA_CTL_AS),
6530 ra->addr, sizeof(ra->addr)) == 0)
6531 return true;
6532 }
6533 }
6534
6535 return false;
6536}
6537
6538/**
6539 * Matches the packet addresses against Multicast Table Array.
6540 *
6541 * @remarks This is imperfect match since it matches not exact address but
6542 * a subset of addresses.
6543 *
6544 * @returns true if address matches.
6545 * @param pThis Pointer to the state structure.
6546 * @param pvBuf The ethernet packet.
6547 * @param cb Number of bytes available in the packet.
6548 * @thread EMT
6549 */
6550static bool e1kImperfectMatch(PE1KSTATE pThis, const void *pvBuf)
6551{
6552 /* Get bits 32..47 of destination address */
6553 uint16_t u16Bit = ((uint16_t*)pvBuf)[2];
6554
6555 unsigned offset = GET_BITS(RCTL, MO);
6556 /*
6557 * offset means:
6558 * 00b = bits 36..47
6559 * 01b = bits 35..46
6560 * 10b = bits 34..45
6561 * 11b = bits 32..43
6562 */
6563 if (offset < 3)
6564 u16Bit = u16Bit >> (4 - offset);
6565 return ASMBitTest(pThis->auMTA, u16Bit & 0xFFF);
6566}
6567
6568/**
6569 * Determines if the packet is to be delivered to upper layer.
6570 *
6571 * The following filters supported:
6572 * - Exact Unicast/Multicast
6573 * - Promiscuous Unicast/Multicast
6574 * - Multicast
6575 * - VLAN
6576 *
6577 * @returns true if packet is intended for this node.
6578 * @param pThis Pointer to the state structure.
6579 * @param pvBuf The ethernet packet.
6580 * @param cb Number of bytes available in the packet.
6581 * @param pStatus Bit field to store status bits.
6582 * @thread EMT
6583 */
6584static bool e1kAddressFilter(PE1KSTATE pThis, const void *pvBuf, size_t cb, E1KRXDST *pStatus)
6585{
6586 Assert(cb > 14);
6587 /* Assume that we fail to pass exact filter. */
6588 pStatus->fPIF = false;
6589 pStatus->fVP = false;
6590 /* Discard oversized packets */
6591 if (cb > E1K_MAX_RX_PKT_SIZE)
6592 {
6593 E1kLog(("%s ERROR: Incoming packet is too big, cb=%d > max=%d\n",
6594 pThis->szPrf, cb, E1K_MAX_RX_PKT_SIZE));
6595 E1K_INC_CNT32(ROC);
6596 return false;
6597 }
6598 else if (!(RCTL & RCTL_LPE) && cb > 1522)
6599 {
6600 /* When long packet reception is disabled packets over 1522 are discarded */
6601 E1kLog(("%s Discarding incoming packet (LPE=0), cb=%d\n",
6602 pThis->szPrf, cb));
6603 E1K_INC_CNT32(ROC);
6604 return false;
6605 }
6606
6607 uint16_t *u16Ptr = (uint16_t*)pvBuf;
6608 /* Compare TPID with VLAN Ether Type */
6609 if (RT_BE2H_U16(u16Ptr[6]) == VET)
6610 {
6611 pStatus->fVP = true;
6612 /* Is VLAN filtering enabled? */
6613 if (RCTL & RCTL_VFE)
6614 {
6615 /* It is 802.1q packet indeed, let's filter by VID */
6616 if (RCTL & RCTL_CFIEN)
6617 {
6618 E1kLog3(("%s VLAN filter: VLAN=%d CFI=%d RCTL_CFI=%d\n", pThis->szPrf,
6619 E1K_SPEC_VLAN(RT_BE2H_U16(u16Ptr[7])),
6620 E1K_SPEC_CFI(RT_BE2H_U16(u16Ptr[7])),
6621 !!(RCTL & RCTL_CFI)));
6622 if (E1K_SPEC_CFI(RT_BE2H_U16(u16Ptr[7])) != !!(RCTL & RCTL_CFI))
6623 {
6624 E1kLog2(("%s Packet filter: CFIs do not match in packet and RCTL (%d!=%d)\n",
6625 pThis->szPrf, E1K_SPEC_CFI(RT_BE2H_U16(u16Ptr[7])), !!(RCTL & RCTL_CFI)));
6626 return false;
6627 }
6628 }
6629 else
6630 E1kLog3(("%s VLAN filter: VLAN=%d\n", pThis->szPrf,
6631 E1K_SPEC_VLAN(RT_BE2H_U16(u16Ptr[7]))));
6632 if (!ASMBitTest(pThis->auVFTA, E1K_SPEC_VLAN(RT_BE2H_U16(u16Ptr[7]))))
6633 {
6634 E1kLog2(("%s Packet filter: no VLAN match (id=%d)\n",
6635 pThis->szPrf, E1K_SPEC_VLAN(RT_BE2H_U16(u16Ptr[7]))));
6636 return false;
6637 }
6638 }
6639 }
6640 /* Broadcast filtering */
6641 if (e1kIsBroadcast(pvBuf) && (RCTL & RCTL_BAM))
6642 return true;
6643 E1kLog2(("%s Packet filter: not a broadcast\n", pThis->szPrf));
6644 if (e1kIsMulticast(pvBuf))
6645 {
6646 /* Is multicast promiscuous enabled? */
6647 if (RCTL & RCTL_MPE)
6648 return true;
6649 E1kLog2(("%s Packet filter: no promiscuous multicast\n", pThis->szPrf));
6650 /* Try perfect matches first */
6651 if (e1kPerfectMatch(pThis, pvBuf))
6652 {
6653 pStatus->fPIF = true;
6654 return true;
6655 }
6656 E1kLog2(("%s Packet filter: no perfect match\n", pThis->szPrf));
6657 if (e1kImperfectMatch(pThis, pvBuf))
6658 return true;
6659 E1kLog2(("%s Packet filter: no imperfect match\n", pThis->szPrf));
6660 }
6661 else {
6662 /* Is unicast promiscuous enabled? */
6663 if (RCTL & RCTL_UPE)
6664 return true;
6665 E1kLog2(("%s Packet filter: no promiscuous unicast\n", pThis->szPrf));
6666 if (e1kPerfectMatch(pThis, pvBuf))
6667 {
6668 pStatus->fPIF = true;
6669 return true;
6670 }
6671 E1kLog2(("%s Packet filter: no perfect match\n", pThis->szPrf));
6672 }
6673 E1kLog2(("%s Packet filter: packet discarded\n", pThis->szPrf));
6674 return false;
6675}
6676
6677/**
6678 * @interface_method_impl{PDMINETWORKDOWN,pfnReceive}
6679 */
6680static DECLCALLBACK(int) e1kR3NetworkDown_Receive(PPDMINETWORKDOWN pInterface, const void *pvBuf, size_t cb)
6681{
6682 PE1KSTATECC pThisCC = RT_FROM_MEMBER(pInterface, E1KSTATECC, INetworkDown);
6683 PE1KSTATE pThis = pThisCC->pShared;
6684 PPDMDEVINS pDevIns = pThisCC->pDevInsR3;
6685 int rc = VINF_SUCCESS;
6686
6687 /*
6688 * Drop packets if the VM is not running yet/anymore.
6689 */
6690 VMSTATE enmVMState = PDMDevHlpVMState(pDevIns);
6691 if ( enmVMState != VMSTATE_RUNNING
6692 && enmVMState != VMSTATE_RUNNING_LS)
6693 {
6694 E1kLog(("%s Dropping incoming packet as VM is not running.\n", pThis->szPrf));
6695 return VINF_SUCCESS;
6696 }
6697
6698 /* Discard incoming packets in locked state */
6699 if (!(RCTL & RCTL_EN) || pThis->fLocked || !(STATUS & STATUS_LU))
6700 {
6701 E1kLog(("%s Dropping incoming packet as receive operation is disabled.\n", pThis->szPrf));
6702 return VINF_SUCCESS;
6703 }
6704
6705 STAM_PROFILE_ADV_START(&pThis->StatReceive, a);
6706
6707 //if (!e1kCsEnter(pThis, RT_SRC_POS))
6708 // return VERR_PERMISSION_DENIED;
6709
6710 e1kPacketDump(pDevIns, pThis, (const uint8_t*)pvBuf, cb, "<-- Incoming");
6711
6712 /* Update stats */
6713 if (RT_LIKELY(e1kCsEnter(pThis, VERR_SEM_BUSY) == VINF_SUCCESS))
6714 {
6715 E1K_INC_CNT32(TPR);
6716 E1K_ADD_CNT64(TORL, TORH, cb < 64? 64 : cb);
6717 e1kCsLeave(pThis);
6718 }
6719 STAM_PROFILE_ADV_START(&pThis->StatReceiveFilter, a);
6720 E1KRXDST status;
6721 RT_ZERO(status);
6722 bool fPassed = e1kAddressFilter(pThis, pvBuf, cb, &status);
6723 STAM_PROFILE_ADV_STOP(&pThis->StatReceiveFilter, a);
6724 if (fPassed)
6725 {
6726 rc = e1kHandleRxPacket(pDevIns, pThis, pvBuf, cb, status);
6727 }
6728 //e1kCsLeave(pThis);
6729 STAM_PROFILE_ADV_STOP(&pThis->StatReceive, a);
6730
6731 return rc;
6732}
6733
6734
6735/* -=-=-=-=- PDMILEDPORTS -=-=-=-=- */
6736
6737/**
6738 * @interface_method_impl{PDMILEDPORTS,pfnQueryStatusLed}
6739 */
6740static DECLCALLBACK(int) e1kR3QueryStatusLed(PPDMILEDPORTS pInterface, unsigned iLUN, PPDMLED *ppLed)
6741{
6742 if (iLUN == 0)
6743 {
6744 PE1KSTATECC pThisCC = RT_FROM_MEMBER(pInterface, E1KSTATECC, ILeds);
6745 *ppLed = &pThisCC->pShared->led;
6746 return VINF_SUCCESS;
6747 }
6748 return VERR_PDM_LUN_NOT_FOUND;
6749}
6750
6751
6752/* -=-=-=-=- PDMINETWORKCONFIG -=-=-=-=- */
6753
6754/**
6755 * @interface_method_impl{PDMINETWORKCONFIG,pfnGetMac}
6756 */
6757static DECLCALLBACK(int) e1kR3GetMac(PPDMINETWORKCONFIG pInterface, PRTMAC pMac)
6758{
6759 PE1KSTATECC pThisCC = RT_FROM_MEMBER(pInterface, E1KSTATECC, INetworkConfig);
6760 pThisCC->eeprom.getMac(pMac);
6761 return VINF_SUCCESS;
6762}
6763
6764/**
6765 * @interface_method_impl{PDMINETWORKCONFIG,pfnGetLinkState}
6766 */
6767static DECLCALLBACK(PDMNETWORKLINKSTATE) e1kR3GetLinkState(PPDMINETWORKCONFIG pInterface)
6768{
6769 PE1KSTATECC pThisCC = RT_FROM_MEMBER(pInterface, E1KSTATECC, INetworkConfig);
6770 PE1KSTATE pThis = pThisCC->pShared;
6771 if (STATUS & STATUS_LU)
6772 return PDMNETWORKLINKSTATE_UP;
6773 return PDMNETWORKLINKSTATE_DOWN;
6774}
6775
6776/**
6777 * @interface_method_impl{PDMINETWORKCONFIG,pfnSetLinkState}
6778 */
6779static DECLCALLBACK(int) e1kR3SetLinkState(PPDMINETWORKCONFIG pInterface, PDMNETWORKLINKSTATE enmState)
6780{
6781 PE1KSTATECC pThisCC = RT_FROM_MEMBER(pInterface, E1KSTATECC, INetworkConfig);
6782 PE1KSTATE pThis = pThisCC->pShared;
6783 PPDMDEVINS pDevIns = pThisCC->pDevInsR3;
6784
6785 E1kLog(("%s e1kR3SetLinkState: enmState=%d\n", pThis->szPrf, enmState));
6786 switch (enmState)
6787 {
6788 case PDMNETWORKLINKSTATE_UP:
6789 pThis->fCableConnected = true;
6790 /* If link was down, bring it up after a while. */
6791 if (!(STATUS & STATUS_LU))
6792 e1kBringLinkUpDelayed(pDevIns, pThis);
6793 break;
6794 case PDMNETWORKLINKSTATE_DOWN:
6795 pThis->fCableConnected = false;
6796 /* Always set the phy link state to down, regardless of the STATUS_LU bit.
6797 * We might have to set the link state before the driver initializes us. */
6798 Phy::setLinkStatus(&pThis->phy, false);
6799 /* If link was up, bring it down. */
6800 if (STATUS & STATUS_LU)
6801 e1kR3LinkDown(pDevIns, pThis, pThisCC);
6802 break;
6803 case PDMNETWORKLINKSTATE_DOWN_RESUME:
6804 /*
6805 * There is not much sense in bringing down the link if it has not come up yet.
6806 * If it is up though, we bring it down temporarely, then bring it up again.
6807 */
6808 if (STATUS & STATUS_LU)
6809 e1kR3LinkDownTemp(pDevIns, pThis, pThisCC);
6810 break;
6811 default:
6812 ;
6813 }
6814 return VINF_SUCCESS;
6815}
6816
6817
6818/* -=-=-=-=- PDMIBASE -=-=-=-=- */
6819
6820/**
6821 * @interface_method_impl{PDMIBASE,pfnQueryInterface}
6822 */
6823static DECLCALLBACK(void *) e1kR3QueryInterface(struct PDMIBASE *pInterface, const char *pszIID)
6824{
6825 PE1KSTATECC pThisCC = RT_FROM_MEMBER(pInterface, E1KSTATECC, IBase);
6826 Assert(&pThisCC->IBase == pInterface);
6827
6828 PDMIBASE_RETURN_INTERFACE(pszIID, PDMIBASE, &pThisCC->IBase);
6829 PDMIBASE_RETURN_INTERFACE(pszIID, PDMINETWORKDOWN, &pThisCC->INetworkDown);
6830 PDMIBASE_RETURN_INTERFACE(pszIID, PDMINETWORKCONFIG, &pThisCC->INetworkConfig);
6831 PDMIBASE_RETURN_INTERFACE(pszIID, PDMILEDPORTS, &pThisCC->ILeds);
6832 return NULL;
6833}
6834
6835
6836/* -=-=-=-=- Saved State -=-=-=-=- */
6837
6838/**
6839 * Saves the configuration.
6840 *
6841 * @param pThis The E1K state.
6842 * @param pSSM The handle to the saved state.
6843 */
6844static void e1kSaveConfig(PCPDMDEVHLPR3 pHlp, PE1KSTATE pThis, PSSMHANDLE pSSM)
6845{
6846 pHlp->pfnSSMPutMem(pSSM, &pThis->macConfigured, sizeof(pThis->macConfigured));
6847 pHlp->pfnSSMPutU32(pSSM, pThis->eChip);
6848}
6849
6850/**
6851 * @callback_method_impl{FNSSMDEVLIVEEXEC,Save basic configuration.}
6852 */
6853static DECLCALLBACK(int) e1kLiveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t uPass)
6854{
6855 RT_NOREF(uPass);
6856 e1kSaveConfig(pDevIns->pHlpR3, PDMDEVINS_2_DATA(pDevIns, PE1KSTATE), pSSM);
6857 return VINF_SSM_DONT_CALL_AGAIN;
6858}
6859
6860/**
6861 * @callback_method_impl{FNSSMDEVSAVEPREP,Synchronize.}
6862 */
6863static DECLCALLBACK(int) e1kSavePrep(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
6864{
6865 RT_NOREF(pSSM);
6866 PE1KSTATE pThis = PDMDEVINS_2_DATA(pDevIns, PE1KSTATE);
6867
6868 int rc = e1kCsEnter(pThis, VERR_SEM_BUSY);
6869 if (RT_UNLIKELY(rc != VINF_SUCCESS))
6870 return rc;
6871 e1kCsLeave(pThis);
6872 return VINF_SUCCESS;
6873#if 0
6874 /* 1) Prevent all threads from modifying the state and memory */
6875 //pThis->fLocked = true;
6876 /* 2) Cancel all timers */
6877#ifdef E1K_TX_DELAY
6878 e1kCancelTimer(pThis, pThis->CTX_SUFF(pTXDTimer));
6879#endif /* E1K_TX_DELAY */
6880//#ifdef E1K_USE_TX_TIMERS
6881 if (pThis->fTidEnabled)
6882 {
6883 e1kCancelTimer(pThis, pThis->CTX_SUFF(pTIDTimer));
6884#ifndef E1K_NO_TAD
6885 e1kCancelTimer(pThis, pThis->CTX_SUFF(pTADTimer));
6886#endif /* E1K_NO_TAD */
6887 }
6888//#endif /* E1K_USE_TX_TIMERS */
6889#ifdef E1K_USE_RX_TIMERS
6890 e1kCancelTimer(pThis, pThis->CTX_SUFF(pRIDTimer));
6891 e1kCancelTimer(pThis, pThis->CTX_SUFF(pRADTimer));
6892#endif /* E1K_USE_RX_TIMERS */
6893 e1kCancelTimer(pThis, pThis->CTX_SUFF(pIntTimer));
6894 /* 3) Did I forget anything? */
6895 E1kLog(("%s Locked\n", pThis->szPrf));
6896 return VINF_SUCCESS;
6897#endif
6898}
6899
6900/**
6901 * @callback_method_impl{FNSSMDEVSAVEEXEC}
6902 */
6903static DECLCALLBACK(int) e1kSaveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
6904{
6905 PE1KSTATE pThis = PDMDEVINS_2_DATA(pDevIns, PE1KSTATE);
6906 PE1KSTATECC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PE1KSTATECC);
6907 PCPDMDEVHLPR3 pHlp = pDevIns->pHlpR3;
6908
6909 e1kSaveConfig(pHlp, pThis, pSSM);
6910 pThisCC->eeprom.save(pHlp, pSSM);
6911 e1kDumpState(pThis);
6912 pHlp->pfnSSMPutMem(pSSM, pThis->auRegs, sizeof(pThis->auRegs));
6913 pHlp->pfnSSMPutBool(pSSM, pThis->fIntRaised);
6914 Phy::saveState(pHlp, pSSM, &pThis->phy);
6915 pHlp->pfnSSMPutU32(pSSM, pThis->uSelectedReg);
6916 pHlp->pfnSSMPutMem(pSSM, pThis->auMTA, sizeof(pThis->auMTA));
6917 pHlp->pfnSSMPutMem(pSSM, &pThis->aRecAddr, sizeof(pThis->aRecAddr));
6918 pHlp->pfnSSMPutMem(pSSM, pThis->auVFTA, sizeof(pThis->auVFTA));
6919 pHlp->pfnSSMPutU64(pSSM, pThis->u64AckedAt);
6920 pHlp->pfnSSMPutU16(pSSM, pThis->u16RxBSize);
6921 //pHlp->pfnSSMPutBool(pSSM, pThis->fDelayInts);
6922 //pHlp->pfnSSMPutBool(pSSM, pThis->fIntMaskUsed);
6923 pHlp->pfnSSMPutU16(pSSM, pThis->u16TxPktLen);
6924/** @todo State wrt to the TSE buffer is incomplete, so little point in
6925 * saving this actually. */
6926 pHlp->pfnSSMPutMem(pSSM, pThis->aTxPacketFallback, pThis->u16TxPktLen);
6927 pHlp->pfnSSMPutBool(pSSM, pThis->fIPcsum);
6928 pHlp->pfnSSMPutBool(pSSM, pThis->fTCPcsum);
6929 pHlp->pfnSSMPutMem(pSSM, &pThis->contextTSE, sizeof(pThis->contextTSE));
6930 pHlp->pfnSSMPutMem(pSSM, &pThis->contextNormal, sizeof(pThis->contextNormal));
6931 pHlp->pfnSSMPutBool(pSSM, pThis->fVTag);
6932 pHlp->pfnSSMPutU16(pSSM, pThis->u16VTagTCI);
6933#ifdef E1K_WITH_TXD_CACHE
6934# if 0
6935 pHlp->pfnSSMPutU8(pSSM, pThis->nTxDFetched);
6936 pHlp->pfnSSMPutMem(pSSM, pThis->aTxDescriptors,
6937 pThis->nTxDFetched * sizeof(pThis->aTxDescriptors[0]));
6938# else
6939 /*
6940 * There is no point in storing TX descriptor cache entries as we can simply
6941 * fetch them again. Moreover, normally the cache is always empty when we
6942 * save the state. Store zero entries for compatibility.
6943 */
6944 pHlp->pfnSSMPutU8(pSSM, 0);
6945# endif
6946#endif /* E1K_WITH_TXD_CACHE */
6947/** @todo GSO requires some more state here. */
6948 E1kLog(("%s State has been saved\n", pThis->szPrf));
6949 return VINF_SUCCESS;
6950}
6951
6952#if 0
6953/**
6954 * @callback_method_impl{FNSSMDEVSAVEDONE}
6955 */
6956static DECLCALLBACK(int) e1kSaveDone(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
6957{
6958 PE1KSTATE pThis = PDMDEVINS_2_DATA(pDevIns, PE1KSTATE);
6959
6960 /* If VM is being powered off unlocking will result in assertions in PGM */
6961 if (PDMDevHlpGetVM(pDevIns)->enmVMState == VMSTATE_RUNNING)
6962 pThis->fLocked = false;
6963 else
6964 E1kLog(("%s VM is not running -- remain locked\n", pThis->szPrf));
6965 E1kLog(("%s Unlocked\n", pThis->szPrf));
6966 return VINF_SUCCESS;
6967}
6968#endif
6969
6970/**
6971 * @callback_method_impl{FNSSMDEVLOADPREP,Synchronize.}
6972 */
6973static DECLCALLBACK(int) e1kLoadPrep(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
6974{
6975 RT_NOREF(pSSM);
6976 PE1KSTATE pThis = PDMDEVINS_2_DATA(pDevIns, PE1KSTATE);
6977
6978 int rc = e1kCsEnter(pThis, VERR_SEM_BUSY);
6979 if (RT_UNLIKELY(rc != VINF_SUCCESS))
6980 return rc;
6981 e1kCsLeave(pThis);
6982 return VINF_SUCCESS;
6983}
6984
6985/**
6986 * @callback_method_impl{FNSSMDEVLOADEXEC}
6987 */
6988static DECLCALLBACK(int) e1kLoadExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
6989{
6990 PE1KSTATE pThis = PDMDEVINS_2_DATA(pDevIns, PE1KSTATE);
6991 PE1KSTATECC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PE1KSTATECC);
6992 PCPDMDEVHLPR3 pHlp = pDevIns->pHlpR3;
6993 int rc;
6994
6995 if ( uVersion != E1K_SAVEDSTATE_VERSION
6996#ifdef E1K_WITH_TXD_CACHE
6997 && uVersion != E1K_SAVEDSTATE_VERSION_VBOX_42_VTAG
6998#endif /* E1K_WITH_TXD_CACHE */
6999 && uVersion != E1K_SAVEDSTATE_VERSION_VBOX_41
7000 && uVersion != E1K_SAVEDSTATE_VERSION_VBOX_30)
7001 return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
7002
7003 if ( uVersion > E1K_SAVEDSTATE_VERSION_VBOX_30
7004 || uPass != SSM_PASS_FINAL)
7005 {
7006 /* config checks */
7007 RTMAC macConfigured;
7008 rc = pHlp->pfnSSMGetMem(pSSM, &macConfigured, sizeof(macConfigured));
7009 AssertRCReturn(rc, rc);
7010 if ( memcmp(&macConfigured, &pThis->macConfigured, sizeof(macConfigured))
7011 && (uPass == 0 || !PDMDevHlpVMTeleportedAndNotFullyResumedYet(pDevIns)) )
7012 LogRel(("%s: The mac address differs: config=%RTmac saved=%RTmac\n", pThis->szPrf, &pThis->macConfigured, &macConfigured));
7013
7014 E1KCHIP eChip;
7015 rc = pHlp->pfnSSMGetU32(pSSM, &eChip);
7016 AssertRCReturn(rc, rc);
7017 if (eChip != pThis->eChip)
7018 return pHlp->pfnSSMSetCfgError(pSSM, RT_SRC_POS, N_("The chip type differs: config=%u saved=%u"), pThis->eChip, eChip);
7019 }
7020
7021 if (uPass == SSM_PASS_FINAL)
7022 {
7023 if (uVersion > E1K_SAVEDSTATE_VERSION_VBOX_30)
7024 {
7025 rc = pThisCC->eeprom.load(pHlp, pSSM);
7026 AssertRCReturn(rc, rc);
7027 }
7028 /* the state */
7029 pHlp->pfnSSMGetMem(pSSM, &pThis->auRegs, sizeof(pThis->auRegs));
7030 pHlp->pfnSSMGetBool(pSSM, &pThis->fIntRaised);
7031 /** @todo PHY could be made a separate device with its own versioning */
7032 Phy::loadState(pHlp, pSSM, &pThis->phy);
7033 pHlp->pfnSSMGetU32(pSSM, &pThis->uSelectedReg);
7034 pHlp->pfnSSMGetMem(pSSM, &pThis->auMTA, sizeof(pThis->auMTA));
7035 pHlp->pfnSSMGetMem(pSSM, &pThis->aRecAddr, sizeof(pThis->aRecAddr));
7036 pHlp->pfnSSMGetMem(pSSM, &pThis->auVFTA, sizeof(pThis->auVFTA));
7037 pHlp->pfnSSMGetU64(pSSM, &pThis->u64AckedAt);
7038 pHlp->pfnSSMGetU16(pSSM, &pThis->u16RxBSize);
7039 //pHlp->pfnSSMGetBool(pSSM, pThis->fDelayInts);
7040 //pHlp->pfnSSMGetBool(pSSM, pThis->fIntMaskUsed);
7041 rc = pHlp->pfnSSMGetU16(pSSM, &pThis->u16TxPktLen);
7042 AssertRCReturn(rc, rc);
7043 if (pThis->u16TxPktLen > sizeof(pThis->aTxPacketFallback))
7044 pThis->u16TxPktLen = sizeof(pThis->aTxPacketFallback);
7045 pHlp->pfnSSMGetMem(pSSM, &pThis->aTxPacketFallback[0], pThis->u16TxPktLen);
7046 pHlp->pfnSSMGetBool(pSSM, &pThis->fIPcsum);
7047 pHlp->pfnSSMGetBool(pSSM, &pThis->fTCPcsum);
7048 pHlp->pfnSSMGetMem(pSSM, &pThis->contextTSE, sizeof(pThis->contextTSE));
7049 rc = pHlp->pfnSSMGetMem(pSSM, &pThis->contextNormal, sizeof(pThis->contextNormal));
7050 AssertRCReturn(rc, rc);
7051 if (uVersion > E1K_SAVEDSTATE_VERSION_VBOX_41)
7052 {
7053 pHlp->pfnSSMGetBool(pSSM, &pThis->fVTag);
7054 rc = pHlp->pfnSSMGetU16(pSSM, &pThis->u16VTagTCI);
7055 AssertRCReturn(rc, rc);
7056 }
7057 else
7058 {
7059 pThis->fVTag = false;
7060 pThis->u16VTagTCI = 0;
7061 }
7062#ifdef E1K_WITH_TXD_CACHE
7063 if (uVersion > E1K_SAVEDSTATE_VERSION_VBOX_42_VTAG)
7064 {
7065 rc = pHlp->pfnSSMGetU8(pSSM, &pThis->nTxDFetched);
7066 AssertRCReturn(rc, rc);
7067 if (pThis->nTxDFetched)
7068 pHlp->pfnSSMGetMem(pSSM, pThis->aTxDescriptors,
7069 pThis->nTxDFetched * sizeof(pThis->aTxDescriptors[0]));
7070 }
7071 else
7072 pThis->nTxDFetched = 0;
7073 /**
7074 * @todo Perhaps we should not store TXD cache as the entries can be
7075 * simply fetched again from guest's memory. Or can't they?
7076 */
7077#endif /* E1K_WITH_TXD_CACHE */
7078#ifdef E1K_WITH_RXD_CACHE
7079 /*
7080 * There is no point in storing the RX descriptor cache in the saved
7081 * state, we just need to make sure it is empty.
7082 */
7083 pThis->iRxDCurrent = pThis->nRxDFetched = 0;
7084#endif /* E1K_WITH_RXD_CACHE */
7085 rc = pHlp->pfnSSMHandleGetStatus(pSSM);
7086 AssertRCReturn(rc, rc);
7087
7088 /* derived state */
7089 e1kSetupGsoCtx(&pThis->GsoCtx, &pThis->contextTSE);
7090
7091 E1kLog(("%s State has been restored\n", pThis->szPrf));
7092 e1kDumpState(pThis);
7093 }
7094 return VINF_SUCCESS;
7095}
7096
7097/**
7098 * @callback_method_impl{FNSSMDEVLOADDONE, Link status adjustments after loading.}
7099 */
7100static DECLCALLBACK(int) e1kLoadDone(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
7101{
7102 PE1KSTATE pThis = PDMDEVINS_2_DATA(pDevIns, PE1KSTATE);
7103 PE1KSTATECC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PE1KSTATECC);
7104 RT_NOREF(pSSM);
7105
7106 /* Update promiscuous mode */
7107 if (pThisCC->pDrvR3)
7108 pThisCC->pDrvR3->pfnSetPromiscuousMode(pThisCC->pDrvR3, !!(RCTL & (RCTL_UPE | RCTL_MPE)));
7109
7110 /*
7111 * Force the link down here, since PDMNETWORKLINKSTATE_DOWN_RESUME is never
7112 * passed to us. We go through all this stuff if the link was up and we
7113 * wasn't teleported.
7114 */
7115 if ( (STATUS & STATUS_LU)
7116 && !PDMDevHlpVMTeleportedAndNotFullyResumedYet(pDevIns)
7117 && pThis->cMsLinkUpDelay)
7118 {
7119 e1kR3LinkDownTemp(pDevIns, pThis, pThisCC);
7120 }
7121 return VINF_SUCCESS;
7122}
7123
7124
7125
7126/* -=-=-=-=- Debug Info + Log Types -=-=-=-=- */
7127
7128/**
7129 * @callback_method_impl{FNRTSTRFORMATTYPE}
7130 */
7131static DECLCALLBACK(size_t) e1kFmtRxDesc(PFNRTSTROUTPUT pfnOutput,
7132 void *pvArgOutput,
7133 const char *pszType,
7134 void const *pvValue,
7135 int cchWidth,
7136 int cchPrecision,
7137 unsigned fFlags,
7138 void *pvUser)
7139{
7140 RT_NOREF(cchWidth, cchPrecision, fFlags, pvUser);
7141 AssertReturn(strcmp(pszType, "e1krxd") == 0, 0);
7142 E1KRXDESC* pDesc = (E1KRXDESC*)pvValue;
7143 if (!pDesc)
7144 return RTStrFormat(pfnOutput, pvArgOutput, NULL, 0, "NULL_RXD");
7145
7146 size_t cbPrintf = 0;
7147 cbPrintf += RTStrFormat(pfnOutput, pvArgOutput, NULL, 0, "Address=%16LX Length=%04X Csum=%04X\n",
7148 pDesc->u64BufAddr, pDesc->u16Length, pDesc->u16Checksum);
7149 cbPrintf += RTStrFormat(pfnOutput, pvArgOutput, NULL, 0, " STA: %s %s %s %s %s %s %s ERR: %s %s %s %s SPECIAL: %s VLAN=%03x PRI=%x",
7150 pDesc->status.fPIF ? "PIF" : "pif",
7151 pDesc->status.fIPCS ? "IPCS" : "ipcs",
7152 pDesc->status.fTCPCS ? "TCPCS" : "tcpcs",
7153 pDesc->status.fVP ? "VP" : "vp",
7154 pDesc->status.fIXSM ? "IXSM" : "ixsm",
7155 pDesc->status.fEOP ? "EOP" : "eop",
7156 pDesc->status.fDD ? "DD" : "dd",
7157 pDesc->status.fRXE ? "RXE" : "rxe",
7158 pDesc->status.fIPE ? "IPE" : "ipe",
7159 pDesc->status.fTCPE ? "TCPE" : "tcpe",
7160 pDesc->status.fCE ? "CE" : "ce",
7161 E1K_SPEC_CFI(pDesc->status.u16Special) ? "CFI" :"cfi",
7162 E1K_SPEC_VLAN(pDesc->status.u16Special),
7163 E1K_SPEC_PRI(pDesc->status.u16Special));
7164 return cbPrintf;
7165}
7166
7167/**
7168 * @callback_method_impl{FNRTSTRFORMATTYPE}
7169 */
7170static DECLCALLBACK(size_t) e1kFmtTxDesc(PFNRTSTROUTPUT pfnOutput,
7171 void *pvArgOutput,
7172 const char *pszType,
7173 void const *pvValue,
7174 int cchWidth,
7175 int cchPrecision,
7176 unsigned fFlags,
7177 void *pvUser)
7178{
7179 RT_NOREF(cchWidth, cchPrecision, fFlags, pvUser);
7180 AssertReturn(strcmp(pszType, "e1ktxd") == 0, 0);
7181 E1KTXDESC *pDesc = (E1KTXDESC*)pvValue;
7182 if (!pDesc)
7183 return RTStrFormat(pfnOutput, pvArgOutput, NULL, 0, "NULL_TXD");
7184
7185 size_t cbPrintf = 0;
7186 switch (e1kGetDescType(pDesc))
7187 {
7188 case E1K_DTYP_CONTEXT:
7189 cbPrintf += RTStrFormat(pfnOutput, pvArgOutput, NULL, 0, "Type=Context\n"
7190 " IPCSS=%02X IPCSO=%02X IPCSE=%04X TUCSS=%02X TUCSO=%02X TUCSE=%04X\n"
7191 " TUCMD:%s%s%s %s %s PAYLEN=%04x HDRLEN=%04x MSS=%04x STA: %s",
7192 pDesc->context.ip.u8CSS, pDesc->context.ip.u8CSO, pDesc->context.ip.u16CSE,
7193 pDesc->context.tu.u8CSS, pDesc->context.tu.u8CSO, pDesc->context.tu.u16CSE,
7194 pDesc->context.dw2.fIDE ? " IDE":"",
7195 pDesc->context.dw2.fRS ? " RS" :"",
7196 pDesc->context.dw2.fTSE ? " TSE":"",
7197 pDesc->context.dw2.fIP ? "IPv4":"IPv6",
7198 pDesc->context.dw2.fTCP ? "TCP":"UDP",
7199 pDesc->context.dw2.u20PAYLEN,
7200 pDesc->context.dw3.u8HDRLEN,
7201 pDesc->context.dw3.u16MSS,
7202 pDesc->context.dw3.fDD?"DD":"");
7203 break;
7204 case E1K_DTYP_DATA:
7205 cbPrintf += RTStrFormat(pfnOutput, pvArgOutput, NULL, 0, "Type=Data Address=%16LX DTALEN=%05X\n"
7206 " DCMD:%s%s%s%s%s%s%s STA:%s%s%s POPTS:%s%s SPECIAL:%s VLAN=%03x PRI=%x",
7207 pDesc->data.u64BufAddr,
7208 pDesc->data.cmd.u20DTALEN,
7209 pDesc->data.cmd.fIDE ? " IDE" :"",
7210 pDesc->data.cmd.fVLE ? " VLE" :"",
7211 pDesc->data.cmd.fRPS ? " RPS" :"",
7212 pDesc->data.cmd.fRS ? " RS" :"",
7213 pDesc->data.cmd.fTSE ? " TSE" :"",
7214 pDesc->data.cmd.fIFCS? " IFCS":"",
7215 pDesc->data.cmd.fEOP ? " EOP" :"",
7216 pDesc->data.dw3.fDD ? " DD" :"",
7217 pDesc->data.dw3.fEC ? " EC" :"",
7218 pDesc->data.dw3.fLC ? " LC" :"",
7219 pDesc->data.dw3.fTXSM? " TXSM":"",
7220 pDesc->data.dw3.fIXSM? " IXSM":"",
7221 E1K_SPEC_CFI(pDesc->data.dw3.u16Special) ? "CFI" :"cfi",
7222 E1K_SPEC_VLAN(pDesc->data.dw3.u16Special),
7223 E1K_SPEC_PRI(pDesc->data.dw3.u16Special));
7224 break;
7225 case E1K_DTYP_LEGACY:
7226 cbPrintf += RTStrFormat(pfnOutput, pvArgOutput, NULL, 0, "Type=Legacy Address=%16LX DTALEN=%05X\n"
7227 " CMD:%s%s%s%s%s%s%s STA:%s%s%s CSO=%02x CSS=%02x SPECIAL:%s VLAN=%03x PRI=%x",
7228 pDesc->data.u64BufAddr,
7229 pDesc->legacy.cmd.u16Length,
7230 pDesc->legacy.cmd.fIDE ? " IDE" :"",
7231 pDesc->legacy.cmd.fVLE ? " VLE" :"",
7232 pDesc->legacy.cmd.fRPS ? " RPS" :"",
7233 pDesc->legacy.cmd.fRS ? " RS" :"",
7234 pDesc->legacy.cmd.fIC ? " IC" :"",
7235 pDesc->legacy.cmd.fIFCS? " IFCS":"",
7236 pDesc->legacy.cmd.fEOP ? " EOP" :"",
7237 pDesc->legacy.dw3.fDD ? " DD" :"",
7238 pDesc->legacy.dw3.fEC ? " EC" :"",
7239 pDesc->legacy.dw3.fLC ? " LC" :"",
7240 pDesc->legacy.cmd.u8CSO,
7241 pDesc->legacy.dw3.u8CSS,
7242 E1K_SPEC_CFI(pDesc->legacy.dw3.u16Special) ? "CFI" :"cfi",
7243 E1K_SPEC_VLAN(pDesc->legacy.dw3.u16Special),
7244 E1K_SPEC_PRI(pDesc->legacy.dw3.u16Special));
7245 break;
7246 default:
7247 cbPrintf += RTStrFormat(pfnOutput, pvArgOutput, NULL, 0, "Invalid Transmit Descriptor");
7248 break;
7249 }
7250
7251 return cbPrintf;
7252}
7253
7254/** Initializes debug helpers (logging format types). */
7255static int e1kInitDebugHelpers(void)
7256{
7257 int rc = VINF_SUCCESS;
7258 static bool s_fHelpersRegistered = false;
7259 if (!s_fHelpersRegistered)
7260 {
7261 s_fHelpersRegistered = true;
7262 rc = RTStrFormatTypeRegister("e1krxd", e1kFmtRxDesc, NULL);
7263 AssertRCReturn(rc, rc);
7264 rc = RTStrFormatTypeRegister("e1ktxd", e1kFmtTxDesc, NULL);
7265 AssertRCReturn(rc, rc);
7266 }
7267 return rc;
7268}
7269
7270/**
7271 * Status info callback.
7272 *
7273 * @param pDevIns The device instance.
7274 * @param pHlp The output helpers.
7275 * @param pszArgs The arguments.
7276 */
7277static DECLCALLBACK(void) e1kInfo(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
7278{
7279 RT_NOREF(pszArgs);
7280 PE1KSTATE pThis = PDMDEVINS_2_DATA(pDevIns, PE1KSTATE);
7281 unsigned i;
7282 // bool fRcvRing = false;
7283 // bool fXmtRing = false;
7284
7285 /*
7286 * Parse args.
7287 if (pszArgs)
7288 {
7289 fRcvRing = strstr(pszArgs, "verbose") || strstr(pszArgs, "rcv");
7290 fXmtRing = strstr(pszArgs, "verbose") || strstr(pszArgs, "xmt");
7291 }
7292 */
7293
7294 /*
7295 * Show info.
7296 */
7297 pHlp->pfnPrintf(pHlp, "E1000 #%d: port=%04x mmio=%RGp mac-cfg=%RTmac %s%s%s\n",
7298 pDevIns->iInstance,
7299 PDMDevHlpIoPortGetMappingAddress(pDevIns, pThis->hIoPorts),
7300 PDMDevHlpMmioGetMappingAddress(pDevIns, pThis->hMmioRegion),
7301 &pThis->macConfigured, g_aChips[pThis->eChip].pcszName,
7302 pDevIns->fRCEnabled ? " RC" : "", pDevIns->fR0Enabled ? " R0" : "");
7303
7304 e1kCsEnter(pThis, VERR_INTERNAL_ERROR); /* Not sure why but PCNet does it */
7305
7306 for (i = 0; i < E1K_NUM_OF_32BIT_REGS; ++i)
7307 pHlp->pfnPrintf(pHlp, "%8.8s = %08x\n", g_aE1kRegMap[i].abbrev, pThis->auRegs[i]);
7308
7309 for (i = 0; i < RT_ELEMENTS(pThis->aRecAddr.array); i++)
7310 {
7311 E1KRAELEM* ra = pThis->aRecAddr.array + i;
7312 if (ra->ctl & RA_CTL_AV)
7313 {
7314 const char *pcszTmp;
7315 switch (ra->ctl & RA_CTL_AS)
7316 {
7317 case 0: pcszTmp = "DST"; break;
7318 case 1: pcszTmp = "SRC"; break;
7319 default: pcszTmp = "reserved";
7320 }
7321 pHlp->pfnPrintf(pHlp, "RA%02d: %s %RTmac\n", i, pcszTmp, ra->addr);
7322 }
7323 }
7324 unsigned cDescs = RDLEN / sizeof(E1KRXDESC);
7325 uint32_t rdh = RDH;
7326 pHlp->pfnPrintf(pHlp, "\n-- Receive Descriptors (%d total) --\n", cDescs);
7327 for (i = 0; i < cDescs; ++i)
7328 {
7329 E1KRXDESC desc;
7330 PDMDevHlpPhysRead(pDevIns, e1kDescAddr(RDBAH, RDBAL, i),
7331 &desc, sizeof(desc));
7332 if (i == rdh)
7333 pHlp->pfnPrintf(pHlp, ">>> ");
7334 pHlp->pfnPrintf(pHlp, "%RGp: %R[e1krxd]\n", e1kDescAddr(RDBAH, RDBAL, i), &desc);
7335 }
7336#ifdef E1K_WITH_RXD_CACHE
7337 pHlp->pfnPrintf(pHlp, "\n-- Receive Descriptors in Cache (at %d (RDH %d)/ fetched %d / max %d) --\n",
7338 pThis->iRxDCurrent, RDH, pThis->nRxDFetched, E1K_RXD_CACHE_SIZE);
7339 if (rdh > pThis->iRxDCurrent)
7340 rdh -= pThis->iRxDCurrent;
7341 else
7342 rdh = cDescs + rdh - pThis->iRxDCurrent;
7343 for (i = 0; i < pThis->nRxDFetched; ++i)
7344 {
7345 if (i == pThis->iRxDCurrent)
7346 pHlp->pfnPrintf(pHlp, ">>> ");
7347 pHlp->pfnPrintf(pHlp, "%RGp: %R[e1krxd]\n",
7348 e1kDescAddr(RDBAH, RDBAL, rdh++ % cDescs),
7349 &pThis->aRxDescriptors[i]);
7350 }
7351#endif /* E1K_WITH_RXD_CACHE */
7352
7353 cDescs = TDLEN / sizeof(E1KTXDESC);
7354 uint32_t tdh = TDH;
7355 pHlp->pfnPrintf(pHlp, "\n-- Transmit Descriptors (%d total) --\n", cDescs);
7356 for (i = 0; i < cDescs; ++i)
7357 {
7358 E1KTXDESC desc;
7359 PDMDevHlpPhysRead(pDevIns, e1kDescAddr(TDBAH, TDBAL, i),
7360 &desc, sizeof(desc));
7361 if (i == tdh)
7362 pHlp->pfnPrintf(pHlp, ">>> ");
7363 pHlp->pfnPrintf(pHlp, "%RGp: %R[e1ktxd]\n", e1kDescAddr(TDBAH, TDBAL, i), &desc);
7364 }
7365#ifdef E1K_WITH_TXD_CACHE
7366 pHlp->pfnPrintf(pHlp, "\n-- Transmit Descriptors in Cache (at %d (TDH %d)/ fetched %d / max %d) --\n",
7367 pThis->iTxDCurrent, TDH, pThis->nTxDFetched, E1K_TXD_CACHE_SIZE);
7368 if (tdh > pThis->iTxDCurrent)
7369 tdh -= pThis->iTxDCurrent;
7370 else
7371 tdh = cDescs + tdh - pThis->iTxDCurrent;
7372 for (i = 0; i < pThis->nTxDFetched; ++i)
7373 {
7374 if (i == pThis->iTxDCurrent)
7375 pHlp->pfnPrintf(pHlp, ">>> ");
7376 pHlp->pfnPrintf(pHlp, "%RGp: %R[e1ktxd]\n",
7377 e1kDescAddr(TDBAH, TDBAL, tdh++ % cDescs),
7378 &pThis->aTxDescriptors[i]);
7379 }
7380#endif /* E1K_WITH_TXD_CACHE */
7381
7382
7383#ifdef E1K_INT_STATS
7384 pHlp->pfnPrintf(pHlp, "Interrupt attempts: %d\n", pThis->uStatIntTry);
7385 pHlp->pfnPrintf(pHlp, "Interrupts raised : %d\n", pThis->uStatInt);
7386 pHlp->pfnPrintf(pHlp, "Interrupts lowered: %d\n", pThis->uStatIntLower);
7387 pHlp->pfnPrintf(pHlp, "ICR outside ISR : %d\n", pThis->uStatNoIntICR);
7388 pHlp->pfnPrintf(pHlp, "IMS raised ints : %d\n", pThis->uStatIntIMS);
7389 pHlp->pfnPrintf(pHlp, "Interrupts skipped: %d\n", pThis->uStatIntSkip);
7390 pHlp->pfnPrintf(pHlp, "Masked interrupts : %d\n", pThis->uStatIntMasked);
7391 pHlp->pfnPrintf(pHlp, "Early interrupts : %d\n", pThis->uStatIntEarly);
7392 pHlp->pfnPrintf(pHlp, "Late interrupts : %d\n", pThis->uStatIntLate);
7393 pHlp->pfnPrintf(pHlp, "Lost interrupts : %d\n", pThis->iStatIntLost);
7394 pHlp->pfnPrintf(pHlp, "Interrupts by RX : %d\n", pThis->uStatIntRx);
7395 pHlp->pfnPrintf(pHlp, "Interrupts by TX : %d\n", pThis->uStatIntTx);
7396 pHlp->pfnPrintf(pHlp, "Interrupts by ICS : %d\n", pThis->uStatIntICS);
7397 pHlp->pfnPrintf(pHlp, "Interrupts by RDTR: %d\n", pThis->uStatIntRDTR);
7398 pHlp->pfnPrintf(pHlp, "Interrupts by RDMT: %d\n", pThis->uStatIntRXDMT0);
7399 pHlp->pfnPrintf(pHlp, "Interrupts by TXQE: %d\n", pThis->uStatIntTXQE);
7400 pHlp->pfnPrintf(pHlp, "TX int delay asked: %d\n", pThis->uStatTxIDE);
7401 pHlp->pfnPrintf(pHlp, "TX delayed: %d\n", pThis->uStatTxDelayed);
7402 pHlp->pfnPrintf(pHlp, "TX delayed expired: %d\n", pThis->uStatTxDelayExp);
7403 pHlp->pfnPrintf(pHlp, "TX no report asked: %d\n", pThis->uStatTxNoRS);
7404 pHlp->pfnPrintf(pHlp, "TX abs timer expd : %d\n", pThis->uStatTAD);
7405 pHlp->pfnPrintf(pHlp, "TX int timer expd : %d\n", pThis->uStatTID);
7406 pHlp->pfnPrintf(pHlp, "RX abs timer expd : %d\n", pThis->uStatRAD);
7407 pHlp->pfnPrintf(pHlp, "RX int timer expd : %d\n", pThis->uStatRID);
7408 pHlp->pfnPrintf(pHlp, "TX CTX descriptors: %d\n", pThis->uStatDescCtx);
7409 pHlp->pfnPrintf(pHlp, "TX DAT descriptors: %d\n", pThis->uStatDescDat);
7410 pHlp->pfnPrintf(pHlp, "TX LEG descriptors: %d\n", pThis->uStatDescLeg);
7411 pHlp->pfnPrintf(pHlp, "Received frames : %d\n", pThis->uStatRxFrm);
7412 pHlp->pfnPrintf(pHlp, "Transmitted frames: %d\n", pThis->uStatTxFrm);
7413 pHlp->pfnPrintf(pHlp, "TX frames up to 1514: %d\n", pThis->uStatTx1514);
7414 pHlp->pfnPrintf(pHlp, "TX frames up to 2962: %d\n", pThis->uStatTx2962);
7415 pHlp->pfnPrintf(pHlp, "TX frames up to 4410: %d\n", pThis->uStatTx4410);
7416 pHlp->pfnPrintf(pHlp, "TX frames up to 5858: %d\n", pThis->uStatTx5858);
7417 pHlp->pfnPrintf(pHlp, "TX frames up to 7306: %d\n", pThis->uStatTx7306);
7418 pHlp->pfnPrintf(pHlp, "TX frames up to 8754: %d\n", pThis->uStatTx8754);
7419 pHlp->pfnPrintf(pHlp, "TX frames up to 16384: %d\n", pThis->uStatTx16384);
7420 pHlp->pfnPrintf(pHlp, "TX frames up to 32768: %d\n", pThis->uStatTx32768);
7421 pHlp->pfnPrintf(pHlp, "Larger TX frames : %d\n", pThis->uStatTxLarge);
7422#endif /* E1K_INT_STATS */
7423
7424 e1kCsLeave(pThis);
7425}
7426
7427
7428
7429/* -=-=-=-=- PDMDEVREG -=-=-=-=- */
7430
7431/**
7432 * Detach notification.
7433 *
7434 * One port on the network card has been disconnected from the network.
7435 *
7436 * @param pDevIns The device instance.
7437 * @param iLUN The logical unit which is being detached.
7438 * @param fFlags Flags, combination of the PDMDEVATT_FLAGS_* \#defines.
7439 */
7440static DECLCALLBACK(void) e1kR3Detach(PPDMDEVINS pDevIns, unsigned iLUN, uint32_t fFlags)
7441{
7442 PE1KSTATE pThis = PDMDEVINS_2_DATA(pDevIns, PE1KSTATE);
7443 PE1KSTATECC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PE1KSTATECC);
7444 Log(("%s e1kR3Detach:\n", pThis->szPrf));
7445 RT_NOREF(fFlags);
7446
7447 AssertLogRelReturnVoid(iLUN == 0);
7448
7449 PDMDevHlpCritSectEnter(pDevIns, &pThis->cs, VERR_SEM_BUSY);
7450
7451 /** @todo r=pritesh still need to check if i missed
7452 * to clean something in this function
7453 */
7454
7455 /*
7456 * Zero some important members.
7457 */
7458 pThisCC->pDrvBase = NULL;
7459 pThisCC->pDrvR3 = NULL;
7460#if 0 /** @todo @bugref{9218} ring-0 driver stuff */
7461 pThisR0->pDrvR0 = NIL_RTR0PTR;
7462 pThisRC->pDrvRC = NIL_RTRCPTR;
7463#endif
7464
7465 PDMDevHlpCritSectLeave(pDevIns, &pThis->cs);
7466}
7467
7468/**
7469 * Attach the Network attachment.
7470 *
7471 * One port on the network card has been connected to a network.
7472 *
7473 * @returns VBox status code.
7474 * @param pDevIns The device instance.
7475 * @param iLUN The logical unit which is being attached.
7476 * @param fFlags Flags, combination of the PDMDEVATT_FLAGS_* \#defines.
7477 *
7478 * @remarks This code path is not used during construction.
7479 */
7480static DECLCALLBACK(int) e1kR3Attach(PPDMDEVINS pDevIns, unsigned iLUN, uint32_t fFlags)
7481{
7482 PE1KSTATE pThis = PDMDEVINS_2_DATA(pDevIns, PE1KSTATE);
7483 PE1KSTATECC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PE1KSTATECC);
7484 LogFlow(("%s e1kR3Attach:\n", pThis->szPrf));
7485 RT_NOREF(fFlags);
7486
7487 AssertLogRelReturn(iLUN == 0, VERR_PDM_NO_SUCH_LUN);
7488
7489 PDMDevHlpCritSectEnter(pDevIns, &pThis->cs, VERR_SEM_BUSY);
7490
7491 /*
7492 * Attach the driver.
7493 */
7494 int rc = PDMDevHlpDriverAttach(pDevIns, 0, &pThisCC->IBase, &pThisCC->pDrvBase, "Network Port");
7495 if (RT_SUCCESS(rc))
7496 {
7497 pThisCC->pDrvR3 = PDMIBASE_QUERY_INTERFACE(pThisCC->pDrvBase, PDMINETWORKUP);
7498 AssertMsgStmt(pThisCC->pDrvR3, ("Failed to obtain the PDMINETWORKUP interface!\n"),
7499 rc = VERR_PDM_MISSING_INTERFACE_BELOW);
7500 if (RT_SUCCESS(rc))
7501 {
7502#if 0 /** @todo @bugref{9218} ring-0 driver stuff */
7503 pThisR0->pDrvR0 = PDMIBASER0_QUERY_INTERFACE(PDMIBASE_QUERY_INTERFACE(pThisCC->pDrvBase, PDMIBASER0), PDMINETWORKUP);
7504 pThisRC->pDrvRC = PDMIBASERC_QUERY_INTERFACE(PDMIBASE_QUERY_INTERFACE(pThisCC->pDrvBase, PDMIBASERC), PDMINETWORKUP);
7505#endif
7506 }
7507 }
7508 else if ( rc == VERR_PDM_NO_ATTACHED_DRIVER
7509 || rc == VERR_PDM_CFG_MISSING_DRIVER_NAME)
7510 {
7511 /* This should never happen because this function is not called
7512 * if there is no driver to attach! */
7513 Log(("%s No attached driver!\n", pThis->szPrf));
7514 }
7515
7516 /*
7517 * Temporary set the link down if it was up so that the guest will know
7518 * that we have change the configuration of the network card
7519 */
7520 if ((STATUS & STATUS_LU) && RT_SUCCESS(rc))
7521 e1kR3LinkDownTemp(pDevIns, pThis, pThisCC);
7522
7523 PDMDevHlpCritSectLeave(pDevIns, &pThis->cs);
7524 return rc;
7525}
7526
7527/**
7528 * @copydoc FNPDMDEVPOWEROFF
7529 */
7530static DECLCALLBACK(void) e1kR3PowerOff(PPDMDEVINS pDevIns)
7531{
7532 /* Poke thread waiting for buffer space. */
7533 e1kWakeupReceive(pDevIns, PDMDEVINS_2_DATA(pDevIns, PE1KSTATE));
7534}
7535
7536/**
7537 * @copydoc FNPDMDEVRESET
7538 */
7539static DECLCALLBACK(void) e1kR3Reset(PPDMDEVINS pDevIns)
7540{
7541 PE1KSTATE pThis = PDMDEVINS_2_DATA(pDevIns, PE1KSTATE);
7542 PE1KSTATECC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PE1KSTATECC);
7543#ifdef E1K_TX_DELAY
7544 e1kCancelTimer(pDevIns, pThis, pThis->hTXDTimer);
7545#endif /* E1K_TX_DELAY */
7546 e1kCancelTimer(pDevIns, pThis, pThis->hIntTimer);
7547 e1kCancelTimer(pDevIns, pThis, pThis->hLUTimer);
7548 e1kXmitFreeBuf(pThis, pThisCC);
7549 pThis->u16TxPktLen = 0;
7550 pThis->fIPcsum = false;
7551 pThis->fTCPcsum = false;
7552 pThis->fIntMaskUsed = false;
7553 pThis->fDelayInts = false;
7554 pThis->fLocked = false;
7555 pThis->u64AckedAt = 0;
7556 e1kR3HardReset(pDevIns, pThis, pThisCC);
7557}
7558
7559/**
7560 * @copydoc FNPDMDEVSUSPEND
7561 */
7562static DECLCALLBACK(void) e1kR3Suspend(PPDMDEVINS pDevIns)
7563{
7564 /* Poke thread waiting for buffer space. */
7565 e1kWakeupReceive(pDevIns, PDMDEVINS_2_DATA(pDevIns, PE1KSTATE));
7566}
7567
7568/**
7569 * Device relocation callback.
7570 *
7571 * When this callback is called the device instance data, and if the
7572 * device have a GC component, is being relocated, or/and the selectors
7573 * have been changed. The device must use the chance to perform the
7574 * necessary pointer relocations and data updates.
7575 *
7576 * Before the GC code is executed the first time, this function will be
7577 * called with a 0 delta so GC pointer calculations can be one in one place.
7578 *
7579 * @param pDevIns Pointer to the device instance.
7580 * @param offDelta The relocation delta relative to the old location.
7581 *
7582 * @remark A relocation CANNOT fail.
7583 */
7584static DECLCALLBACK(void) e1kR3Relocate(PPDMDEVINS pDevIns, RTGCINTPTR offDelta)
7585{
7586 PE1KSTATERC pThisRC = PDMINS_2_DATA_RC(pDevIns, PE1KSTATERC);
7587 if (pThisRC)
7588 pThisRC->pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
7589 RT_NOREF(offDelta);
7590}
7591
7592/**
7593 * Destruct a device instance.
7594 *
7595 * We need to free non-VM resources only.
7596 *
7597 * @returns VBox status code.
7598 * @param pDevIns The device instance data.
7599 * @thread EMT
7600 */
7601static DECLCALLBACK(int) e1kR3Destruct(PPDMDEVINS pDevIns)
7602{
7603 PDMDEV_CHECK_VERSIONS_RETURN_QUIET(pDevIns);
7604 PE1KSTATE pThis = PDMDEVINS_2_DATA(pDevIns, PE1KSTATE);
7605
7606 e1kDumpState(pThis);
7607 E1kLog(("%s Destroying instance\n", pThis->szPrf));
7608 if (PDMDevHlpCritSectIsInitialized(pDevIns, &pThis->cs))
7609 {
7610 if (pThis->hEventMoreRxDescAvail != NIL_SUPSEMEVENT)
7611 {
7612 PDMDevHlpSUPSemEventSignal(pDevIns, pThis->hEventMoreRxDescAvail);
7613 RTThreadYield();
7614 PDMDevHlpSUPSemEventClose(pDevIns, pThis->hEventMoreRxDescAvail);
7615 pThis->hEventMoreRxDescAvail = NIL_SUPSEMEVENT;
7616 }
7617#ifdef E1K_WITH_TX_CS
7618 PDMDevHlpCritSectDelete(pDevIns, &pThis->csTx);
7619#endif /* E1K_WITH_TX_CS */
7620 PDMDevHlpCritSectDelete(pDevIns, &pThis->csRx);
7621 PDMDevHlpCritSectDelete(pDevIns, &pThis->cs);
7622 }
7623 return VINF_SUCCESS;
7624}
7625
7626
7627/**
7628 * Set PCI configuration space registers.
7629 *
7630 * @param pci Reference to PCI device structure.
7631 * @thread EMT
7632 */
7633static void e1kR3ConfigurePciDev(PPDMPCIDEV pPciDev, E1KCHIP eChip)
7634{
7635 Assert(eChip < RT_ELEMENTS(g_aChips));
7636 /* Configure PCI Device, assume 32-bit mode ******************************/
7637 PDMPciDevSetVendorId(pPciDev, g_aChips[eChip].uPCIVendorId);
7638 PDMPciDevSetDeviceId(pPciDev, g_aChips[eChip].uPCIDeviceId);
7639 PDMPciDevSetWord( pPciDev, VBOX_PCI_SUBSYSTEM_VENDOR_ID, g_aChips[eChip].uPCISubsystemVendorId);
7640 PDMPciDevSetWord( pPciDev, VBOX_PCI_SUBSYSTEM_ID, g_aChips[eChip].uPCISubsystemId);
7641
7642 PDMPciDevSetWord( pPciDev, VBOX_PCI_COMMAND, 0x0000);
7643 /* DEVSEL Timing (medium device), 66 MHz Capable, New capabilities */
7644 PDMPciDevSetWord( pPciDev, VBOX_PCI_STATUS,
7645 VBOX_PCI_STATUS_DEVSEL_MEDIUM | VBOX_PCI_STATUS_CAP_LIST | VBOX_PCI_STATUS_66MHZ);
7646 /* Stepping A2 */
7647 PDMPciDevSetByte( pPciDev, VBOX_PCI_REVISION_ID, 0x02);
7648 /* Ethernet adapter */
7649 PDMPciDevSetByte( pPciDev, VBOX_PCI_CLASS_PROG, 0x00);
7650 PDMPciDevSetWord( pPciDev, VBOX_PCI_CLASS_DEVICE, 0x0200);
7651 /* normal single function Ethernet controller */
7652 PDMPciDevSetByte( pPciDev, VBOX_PCI_HEADER_TYPE, 0x00);
7653 /* Memory Register Base Address */
7654 PDMPciDevSetDWord(pPciDev, VBOX_PCI_BASE_ADDRESS_0, 0x00000000);
7655 /* Memory Flash Base Address */
7656 PDMPciDevSetDWord(pPciDev, VBOX_PCI_BASE_ADDRESS_1, 0x00000000);
7657 /* IO Register Base Address */
7658 PDMPciDevSetDWord(pPciDev, VBOX_PCI_BASE_ADDRESS_2, 0x00000001);
7659 /* Expansion ROM Base Address */
7660 PDMPciDevSetDWord(pPciDev, VBOX_PCI_ROM_ADDRESS, 0x00000000);
7661 /* Capabilities Pointer */
7662 PDMPciDevSetByte( pPciDev, VBOX_PCI_CAPABILITY_LIST, 0xDC);
7663 /* Interrupt Pin: INTA# */
7664 PDMPciDevSetByte( pPciDev, VBOX_PCI_INTERRUPT_PIN, 0x01);
7665 /* Max_Lat/Min_Gnt: very high priority and time slice */
7666 PDMPciDevSetByte( pPciDev, VBOX_PCI_MIN_GNT, 0xFF);
7667 PDMPciDevSetByte( pPciDev, VBOX_PCI_MAX_LAT, 0x00);
7668
7669 /* PCI Power Management Registers ****************************************/
7670 /* Capability ID: PCI Power Management Registers */
7671 PDMPciDevSetByte( pPciDev, 0xDC, VBOX_PCI_CAP_ID_PM);
7672 /* Next Item Pointer: PCI-X */
7673 PDMPciDevSetByte( pPciDev, 0xDC + 1, 0xE4);
7674 /* Power Management Capabilities: PM disabled, DSI */
7675 PDMPciDevSetWord( pPciDev, 0xDC + 2,
7676 0x0002 | VBOX_PCI_PM_CAP_DSI);
7677 /* Power Management Control / Status Register: PM disabled */
7678 PDMPciDevSetWord( pPciDev, 0xDC + 4, 0x0000);
7679 /* PMCSR_BSE Bridge Support Extensions: Not supported */
7680 PDMPciDevSetByte( pPciDev, 0xDC + 6, 0x00);
7681 /* Data Register: PM disabled, always 0 */
7682 PDMPciDevSetByte( pPciDev, 0xDC + 7, 0x00);
7683
7684 /* PCI-X Configuration Registers *****************************************/
7685 /* Capability ID: PCI-X Configuration Registers */
7686 PDMPciDevSetByte( pPciDev, 0xE4, VBOX_PCI_CAP_ID_PCIX);
7687#ifdef E1K_WITH_MSI
7688 PDMPciDevSetByte( pPciDev, 0xE4 + 1, 0x80);
7689#else
7690 /* Next Item Pointer: None (Message Signalled Interrupts are disabled) */
7691 PDMPciDevSetByte( pPciDev, 0xE4 + 1, 0x00);
7692#endif
7693 /* PCI-X Command: Enable Relaxed Ordering */
7694 PDMPciDevSetWord( pPciDev, 0xE4 + 2, VBOX_PCI_X_CMD_ERO);
7695 /* PCI-X Status: 32-bit, 66MHz*/
7696 /** @todo is this value really correct? fff8 doesn't look like actual PCI address */
7697 PDMPciDevSetDWord(pPciDev, 0xE4 + 4, 0x0040FFF8);
7698}
7699
7700/**
7701 * @interface_method_impl{PDMDEVREG,pfnConstruct}
7702 */
7703static DECLCALLBACK(int) e1kR3Construct(PPDMDEVINS pDevIns, int iInstance, PCFGMNODE pCfg)
7704{
7705 PDMDEV_CHECK_VERSIONS_RETURN(pDevIns);
7706 PE1KSTATE pThis = PDMDEVINS_2_DATA(pDevIns, PE1KSTATE);
7707 PE1KSTATECC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PE1KSTATECC);
7708 int rc;
7709
7710 /*
7711 * Initialize the instance data (state).
7712 * Note! Caller has initialized it to ZERO already.
7713 */
7714 RTStrPrintf(pThis->szPrf, sizeof(pThis->szPrf), "E1000#%d", iInstance);
7715 E1kLog(("%s Constructing new instance sizeof(E1KRXDESC)=%d\n", pThis->szPrf, sizeof(E1KRXDESC)));
7716 pThis->hEventMoreRxDescAvail = NIL_SUPSEMEVENT;
7717 pThis->u16TxPktLen = 0;
7718 pThis->fIPcsum = false;
7719 pThis->fTCPcsum = false;
7720 pThis->fIntMaskUsed = false;
7721 pThis->fDelayInts = false;
7722 pThis->fLocked = false;
7723 pThis->u64AckedAt = 0;
7724 pThis->led.u32Magic = PDMLED_MAGIC;
7725 pThis->u32PktNo = 1;
7726
7727 pThisCC->pDevInsR3 = pDevIns;
7728 pThisCC->pShared = pThis;
7729
7730 /* Interfaces */
7731 pThisCC->IBase.pfnQueryInterface = e1kR3QueryInterface;
7732
7733 pThisCC->INetworkDown.pfnWaitReceiveAvail = e1kR3NetworkDown_WaitReceiveAvail;
7734 pThisCC->INetworkDown.pfnReceive = e1kR3NetworkDown_Receive;
7735 pThisCC->INetworkDown.pfnXmitPending = e1kR3NetworkDown_XmitPending;
7736
7737 pThisCC->ILeds.pfnQueryStatusLed = e1kR3QueryStatusLed;
7738
7739 pThisCC->INetworkConfig.pfnGetMac = e1kR3GetMac;
7740 pThisCC->INetworkConfig.pfnGetLinkState = e1kR3GetLinkState;
7741 pThisCC->INetworkConfig.pfnSetLinkState = e1kR3SetLinkState;
7742
7743 /*
7744 * Internal validations.
7745 */
7746 for (uint32_t iReg = 1; iReg < E1K_NUM_OF_BINARY_SEARCHABLE; iReg++)
7747 AssertLogRelMsgReturn( g_aE1kRegMap[iReg].offset > g_aE1kRegMap[iReg - 1].offset
7748 && g_aE1kRegMap[iReg].offset + g_aE1kRegMap[iReg].size
7749 >= g_aE1kRegMap[iReg - 1].offset + g_aE1kRegMap[iReg - 1].size,
7750 ("%s@%#xLB%#x vs %s@%#xLB%#x\n",
7751 g_aE1kRegMap[iReg].abbrev, g_aE1kRegMap[iReg].offset, g_aE1kRegMap[iReg].size,
7752 g_aE1kRegMap[iReg - 1].abbrev, g_aE1kRegMap[iReg - 1].offset, g_aE1kRegMap[iReg - 1].size),
7753 VERR_INTERNAL_ERROR_4);
7754
7755 /*
7756 * Validate configuration.
7757 */
7758 PDMDEV_VALIDATE_CONFIG_RETURN(pDevIns,
7759 "MAC|"
7760 "CableConnected|"
7761 "AdapterType|"
7762 "LineSpeed|"
7763 "ItrEnabled|"
7764 "ItrRxEnabled|"
7765 "EthernetCRC|"
7766 "GSOEnabled|"
7767 "LinkUpDelay|"
7768 "StatNo",
7769 "");
7770
7771 /** @todo LineSpeed unused! */
7772
7773 /*
7774 * Get config params
7775 */
7776 PCPDMDEVHLPR3 pHlp = pDevIns->pHlpR3;
7777 rc = pHlp->pfnCFGMQueryBytes(pCfg, "MAC", pThis->macConfigured.au8, sizeof(pThis->macConfigured.au8));
7778 if (RT_FAILURE(rc))
7779 return PDMDEV_SET_ERROR(pDevIns, rc,
7780 N_("Configuration error: Failed to get MAC address"));
7781 rc = pHlp->pfnCFGMQueryBool(pCfg, "CableConnected", &pThis->fCableConnected);
7782 if (RT_FAILURE(rc))
7783 return PDMDEV_SET_ERROR(pDevIns, rc,
7784 N_("Configuration error: Failed to get the value of 'CableConnected'"));
7785 rc = pHlp->pfnCFGMQueryU32(pCfg, "AdapterType", (uint32_t*)&pThis->eChip);
7786 if (RT_FAILURE(rc))
7787 return PDMDEV_SET_ERROR(pDevIns, rc,
7788 N_("Configuration error: Failed to get the value of 'AdapterType'"));
7789 Assert(pThis->eChip <= E1K_CHIP_82545EM);
7790
7791 rc = pHlp->pfnCFGMQueryBoolDef(pCfg, "EthernetCRC", &pThis->fEthernetCRC, true);
7792 if (RT_FAILURE(rc))
7793 return PDMDEV_SET_ERROR(pDevIns, rc,
7794 N_("Configuration error: Failed to get the value of 'EthernetCRC'"));
7795
7796 rc = pHlp->pfnCFGMQueryBoolDef(pCfg, "GSOEnabled", &pThis->fGSOEnabled, true);
7797 if (RT_FAILURE(rc))
7798 return PDMDEV_SET_ERROR(pDevIns, rc,
7799 N_("Configuration error: Failed to get the value of 'GSOEnabled'"));
7800
7801 rc = pHlp->pfnCFGMQueryBoolDef(pCfg, "ItrEnabled", &pThis->fItrEnabled, false);
7802 if (RT_FAILURE(rc))
7803 return PDMDEV_SET_ERROR(pDevIns, rc,
7804 N_("Configuration error: Failed to get the value of 'ItrEnabled'"));
7805
7806 rc = pHlp->pfnCFGMQueryBoolDef(pCfg, "ItrRxEnabled", &pThis->fItrRxEnabled, true);
7807 if (RT_FAILURE(rc))
7808 return PDMDEV_SET_ERROR(pDevIns, rc,
7809 N_("Configuration error: Failed to get the value of 'ItrRxEnabled'"));
7810
7811 rc = pHlp->pfnCFGMQueryBoolDef(pCfg, "TidEnabled", &pThis->fTidEnabled, false);
7812 if (RT_FAILURE(rc))
7813 return PDMDEV_SET_ERROR(pDevIns, rc,
7814 N_("Configuration error: Failed to get the value of 'TidEnabled'"));
7815
7816 rc = pHlp->pfnCFGMQueryU32Def(pCfg, "LinkUpDelay", (uint32_t*)&pThis->cMsLinkUpDelay, 3000); /* ms */
7817 if (RT_FAILURE(rc))
7818 return PDMDEV_SET_ERROR(pDevIns, rc,
7819 N_("Configuration error: Failed to get the value of 'LinkUpDelay'"));
7820 Assert(pThis->cMsLinkUpDelay <= 300000); /* less than 5 minutes */
7821 if (pThis->cMsLinkUpDelay > 5000)
7822 LogRel(("%s: WARNING! Link up delay is set to %u seconds!\n", pThis->szPrf, pThis->cMsLinkUpDelay / 1000));
7823 else if (pThis->cMsLinkUpDelay == 0)
7824 LogRel(("%s: WARNING! Link up delay is disabled!\n", pThis->szPrf));
7825
7826 uint32_t uStatNo = (uint32_t)iInstance;
7827 rc = pHlp->pfnCFGMQueryU32Def(pCfg, "StatNo", &uStatNo, (uint32_t)iInstance);
7828 if (RT_FAILURE(rc))
7829 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to get the \"StatNo\" value"));
7830
7831 LogRel(("%s: Chip=%s LinkUpDelay=%ums EthernetCRC=%s GSO=%s Itr=%s ItrRx=%s TID=%s R0=%s RC=%s\n", pThis->szPrf,
7832 g_aChips[pThis->eChip].pcszName, pThis->cMsLinkUpDelay,
7833 pThis->fEthernetCRC ? "on" : "off",
7834 pThis->fGSOEnabled ? "enabled" : "disabled",
7835 pThis->fItrEnabled ? "enabled" : "disabled",
7836 pThis->fItrRxEnabled ? "enabled" : "disabled",
7837 pThis->fTidEnabled ? "enabled" : "disabled",
7838 pDevIns->fR0Enabled ? "enabled" : "disabled",
7839 pDevIns->fRCEnabled ? "enabled" : "disabled"));
7840
7841 /*
7842 * Initialize sub-components and register everything with the VMM.
7843 */
7844
7845 /* Initialize the EEPROM. */
7846 pThisCC->eeprom.init(pThis->macConfigured);
7847
7848 /* Initialize internal PHY. */
7849 Phy::init(&pThis->phy, iInstance, pThis->eChip == E1K_CHIP_82543GC ? PHY_EPID_M881000 : PHY_EPID_M881011);
7850
7851 /* Initialize critical sections. We do our own locking. */
7852 rc = PDMDevHlpSetDeviceCritSect(pDevIns, PDMDevHlpCritSectGetNop(pDevIns));
7853 AssertRCReturn(rc, rc);
7854
7855 rc = PDMDevHlpCritSectInit(pDevIns, &pThis->cs, RT_SRC_POS, "E1000#%d", iInstance);
7856 AssertRCReturn(rc, rc);
7857 rc = PDMDevHlpCritSectInit(pDevIns, &pThis->csRx, RT_SRC_POS, "E1000#%dRX", iInstance);
7858 AssertRCReturn(rc, rc);
7859#ifdef E1K_WITH_TX_CS
7860 rc = PDMDevHlpCritSectInit(pDevIns, &pThis->csTx, RT_SRC_POS, "E1000#%dTX", iInstance);
7861 AssertRCReturn(rc, rc);
7862#endif
7863
7864 /* Saved state registration. */
7865 rc = PDMDevHlpSSMRegisterEx(pDevIns, E1K_SAVEDSTATE_VERSION, sizeof(E1KSTATE), NULL,
7866 NULL, e1kLiveExec, NULL,
7867 e1kSavePrep, e1kSaveExec, NULL,
7868 e1kLoadPrep, e1kLoadExec, e1kLoadDone);
7869 AssertRCReturn(rc, rc);
7870
7871 /* Set PCI config registers and register ourselves with the PCI bus. */
7872 PDMPCIDEV_ASSERT_VALID(pDevIns, pDevIns->apPciDevs[0]);
7873 e1kR3ConfigurePciDev(pDevIns->apPciDevs[0], pThis->eChip);
7874 rc = PDMDevHlpPCIRegister(pDevIns, pDevIns->apPciDevs[0]);
7875 AssertRCReturn(rc, rc);
7876
7877#ifdef E1K_WITH_MSI
7878 PDMMSIREG MsiReg;
7879 RT_ZERO(MsiReg);
7880 MsiReg.cMsiVectors = 1;
7881 MsiReg.iMsiCapOffset = 0x80;
7882 MsiReg.iMsiNextOffset = 0x0;
7883 MsiReg.fMsi64bit = false;
7884 rc = PDMDevHlpPCIRegisterMsi(pDevIns, &MsiReg);
7885 AssertRCReturn(rc, rc);
7886#endif
7887
7888 /*
7889 * Map our registers to memory space (region 0, see e1kR3ConfigurePciDev)
7890 * From the spec (regarding flags):
7891 * For registers that should be accessed as 32-bit double words,
7892 * partial writes (less than a 32-bit double word) is ignored.
7893 * Partial reads return all 32 bits of data regardless of the
7894 * byte enables.
7895 */
7896 rc = PDMDevHlpMmioCreateEx(pDevIns, E1K_MM_SIZE, IOMMMIO_FLAGS_READ_DWORD | IOMMMIO_FLAGS_WRITE_ONLY_DWORD,
7897 pDevIns->apPciDevs[0], 0 /*iPciRegion*/,
7898 e1kMMIOWrite, e1kMMIORead, NULL /*pfnFill*/, NULL /*pvUser*/, "E1000", &pThis->hMmioRegion);
7899 AssertRCReturn(rc, rc);
7900 rc = PDMDevHlpPCIIORegionRegisterMmio(pDevIns, 0, E1K_MM_SIZE, PCI_ADDRESS_SPACE_MEM, pThis->hMmioRegion, NULL);
7901 AssertRCReturn(rc, rc);
7902
7903 /* Map our registers to IO space (region 2, see e1kR3ConfigurePciDev) */
7904 static IOMIOPORTDESC const s_aExtDescs[] =
7905 {
7906 { "IOADDR", "IOADDR", NULL, NULL }, { "unused", "unused", NULL, NULL }, { "unused", "unused", NULL, NULL }, { "unused", "unused", NULL, NULL },
7907 { "IODATA", "IODATA", NULL, NULL }, { "unused", "unused", NULL, NULL }, { "unused", "unused", NULL, NULL }, { "unused", "unused", NULL, NULL },
7908 { NULL, NULL, NULL, NULL }
7909 };
7910 rc = PDMDevHlpIoPortCreate(pDevIns, E1K_IOPORT_SIZE, pDevIns->apPciDevs[0], 2 /*iPciRegion*/,
7911 e1kIOPortOut, e1kIOPortIn, NULL /*pvUser*/, "E1000", s_aExtDescs, &pThis->hIoPorts);
7912 AssertRCReturn(rc, rc);
7913 rc = PDMDevHlpPCIIORegionRegisterIo(pDevIns, 2, E1K_IOPORT_SIZE, pThis->hIoPorts);
7914 AssertRCReturn(rc, rc);
7915
7916 /* Create transmit queue */
7917 rc = PDMDevHlpTaskCreate(pDevIns, PDMTASK_F_RZ, "E1000-Xmit", e1kR3TxTaskCallback, NULL, &pThis->hTxTask);
7918 AssertRCReturn(rc, rc);
7919
7920#ifdef E1K_TX_DELAY
7921 /* Create Transmit Delay Timer */
7922 rc = PDMDevHlpTimerCreate(pDevIns, TMCLOCK_VIRTUAL, e1kR3TxDelayTimer, pThis, TMTIMER_FLAGS_NO_CRIT_SECT,
7923 "E1000 Transmit Delay Timer", &pThis->hTXDTimer);
7924 AssertRCReturn(rc, rc);
7925 rc = PDMDevHlpTimerSetCritSect(pDevIns, pThis->hTXDTimer, &pThis->csTx);
7926 AssertRCReturn(rc, rc);
7927#endif /* E1K_TX_DELAY */
7928
7929//#ifdef E1K_USE_TX_TIMERS
7930 if (pThis->fTidEnabled)
7931 {
7932 /* Create Transmit Interrupt Delay Timer */
7933 rc = PDMDevHlpTimerCreate(pDevIns, TMCLOCK_VIRTUAL, e1kR3TxIntDelayTimer, pThis, TMTIMER_FLAGS_NO_CRIT_SECT,
7934 "E1000 Transmit Interrupt Delay Timer", &pThis->hTIDTimer);
7935 AssertRCReturn(rc, rc);
7936
7937# ifndef E1K_NO_TAD
7938 /* Create Transmit Absolute Delay Timer */
7939 rc = PDMDevHlpTimerCreate(pDevIns, TMCLOCK_VIRTUAL, e1kR3TxAbsDelayTimer, pThis, TMTIMER_FLAGS_NO_CRIT_SECT,
7940 "E1000 Transmit Absolute Delay Timer", &pThis->hTADTimer);
7941 AssertRCReturn(rc, rc);
7942# endif /* E1K_NO_TAD */
7943 }
7944//#endif /* E1K_USE_TX_TIMERS */
7945
7946#ifdef E1K_USE_RX_TIMERS
7947 /* Create Receive Interrupt Delay Timer */
7948 rc = PDMDevHlpTimerCreate(pDevIns, TMCLOCK_VIRTUAL, e1kR3RxIntDelayTimer, pThis, TMTIMER_FLAGS_NO_CRIT_SECT,
7949 "E1000 Receive Interrupt Delay Timer", &pThis->hRIDTimer);
7950 AssertRCReturn(rc, rc);
7951
7952 /* Create Receive Absolute Delay Timer */
7953 rc = PDMDevHlpTimerCreate(pDevIns, TMCLOCK_VIRTUAL, e1kR3RxAbsDelayTimer, pThis, TMTIMER_FLAGS_NO_CRIT_SECT,
7954 "E1000 Receive Absolute Delay Timer", &pThis->hRADTimer);
7955 AssertRCReturn(rc, rc);
7956#endif /* E1K_USE_RX_TIMERS */
7957
7958 /* Create Late Interrupt Timer */
7959 rc = PDMDevHlpTimerCreate(pDevIns, TMCLOCK_VIRTUAL, e1kR3LateIntTimer, pThis, TMTIMER_FLAGS_NO_CRIT_SECT,
7960 "E1000 Late Interrupt Timer", &pThis->hIntTimer);
7961 AssertRCReturn(rc, rc);
7962
7963 /* Create Link Up Timer */
7964 rc = PDMDevHlpTimerCreate(pDevIns, TMCLOCK_VIRTUAL, e1kR3LinkUpTimer, pThis, TMTIMER_FLAGS_NO_CRIT_SECT,
7965 "E1000 Link Up Timer", &pThis->hLUTimer);
7966 AssertRCReturn(rc, rc);
7967
7968 /* Register the info item */
7969 char szTmp[20];
7970 RTStrPrintf(szTmp, sizeof(szTmp), "e1k%d", iInstance);
7971 PDMDevHlpDBGFInfoRegister(pDevIns, szTmp, "E1000 info.", e1kInfo);
7972
7973 /* Status driver */
7974 PPDMIBASE pBase;
7975 rc = PDMDevHlpDriverAttach(pDevIns, PDM_STATUS_LUN, &pThisCC->IBase, &pBase, "Status Port");
7976 if (RT_FAILURE(rc))
7977 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Failed to attach the status LUN"));
7978 pThisCC->pLedsConnector = PDMIBASE_QUERY_INTERFACE(pBase, PDMILEDCONNECTORS);
7979
7980 /* Network driver */
7981 rc = PDMDevHlpDriverAttach(pDevIns, 0, &pThisCC->IBase, &pThisCC->pDrvBase, "Network Port");
7982 if (RT_SUCCESS(rc))
7983 {
7984 pThisCC->pDrvR3 = PDMIBASE_QUERY_INTERFACE(pThisCC->pDrvBase, PDMINETWORKUP);
7985 AssertMsgReturn(pThisCC->pDrvR3, ("Failed to obtain the PDMINETWORKUP interface!\n"), VERR_PDM_MISSING_INTERFACE_BELOW);
7986
7987#if 0 /** @todo @bugref{9218} ring-0 driver stuff */
7988 pThisR0->pDrvR0 = PDMIBASER0_QUERY_INTERFACE(PDMIBASE_QUERY_INTERFACE(pThisCC->pDrvBase, PDMIBASER0), PDMINETWORKUP);
7989 pThisRC->pDrvRC = PDMIBASERC_QUERY_INTERFACE(PDMIBASE_QUERY_INTERFACE(pThisCC->pDrvBase, PDMIBASERC), PDMINETWORKUP);
7990#endif
7991 }
7992 else if ( rc == VERR_PDM_NO_ATTACHED_DRIVER
7993 || rc == VERR_PDM_CFG_MISSING_DRIVER_NAME)
7994 {
7995 /* No error! */
7996 E1kLog(("%s This adapter is not attached to any network!\n", pThis->szPrf));
7997 }
7998 else
7999 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Failed to attach the network LUN"));
8000
8001 rc = PDMDevHlpSUPSemEventCreate(pDevIns, &pThis->hEventMoreRxDescAvail);
8002 AssertRCReturn(rc, rc);
8003
8004 rc = e1kInitDebugHelpers();
8005 AssertRCReturn(rc, rc);
8006
8007 e1kR3HardReset(pDevIns, pThis, pThisCC);
8008
8009 /*
8010 * Register statistics.
8011 * The /Public/ bits are official and used by session info in the GUI.
8012 */
8013 PDMDevHlpSTAMRegisterF(pDevIns, &pThis->StatReceiveBytes, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_BYTES,
8014 "Amount of data received", "/Public/NetAdapter/%u/BytesReceived", uStatNo);
8015 PDMDevHlpSTAMRegisterF(pDevIns, &pThis->StatTransmitBytes, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_BYTES,
8016 "Amount of data transmitted", "/Public/NetAdapter/%u/BytesTransmitted", uStatNo);
8017 PDMDevHlpSTAMRegisterF(pDevIns, &pDevIns->iInstance, STAMTYPE_U32, STAMVISIBILITY_ALWAYS, STAMUNIT_NONE,
8018 "Device instance number", "/Public/NetAdapter/%u/%s", uStatNo, pDevIns->pReg->szName);
8019
8020 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatReceiveBytes, STAMTYPE_COUNTER, "ReceiveBytes", STAMUNIT_BYTES, "Amount of data received");
8021 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatTransmitBytes, STAMTYPE_COUNTER, "TransmitBytes", STAMUNIT_BYTES, "Amount of data transmitted");
8022
8023#if defined(VBOX_WITH_STATISTICS)
8024 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMMIOReadRZ, STAMTYPE_PROFILE, "MMIO/ReadRZ", STAMUNIT_TICKS_PER_CALL, "Profiling MMIO reads in RZ");
8025 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMMIOReadR3, STAMTYPE_PROFILE, "MMIO/ReadR3", STAMUNIT_TICKS_PER_CALL, "Profiling MMIO reads in R3");
8026 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMMIOWriteRZ, STAMTYPE_PROFILE, "MMIO/WriteRZ", STAMUNIT_TICKS_PER_CALL, "Profiling MMIO writes in RZ");
8027 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMMIOWriteR3, STAMTYPE_PROFILE, "MMIO/WriteR3", STAMUNIT_TICKS_PER_CALL, "Profiling MMIO writes in R3");
8028 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatEEPROMRead, STAMTYPE_PROFILE, "EEPROM/Read", STAMUNIT_TICKS_PER_CALL, "Profiling EEPROM reads");
8029 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatEEPROMWrite, STAMTYPE_PROFILE, "EEPROM/Write", STAMUNIT_TICKS_PER_CALL, "Profiling EEPROM writes");
8030 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatIOReadRZ, STAMTYPE_PROFILE, "IO/ReadRZ", STAMUNIT_TICKS_PER_CALL, "Profiling IO reads in RZ");
8031 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatIOReadR3, STAMTYPE_PROFILE, "IO/ReadR3", STAMUNIT_TICKS_PER_CALL, "Profiling IO reads in R3");
8032 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatIOWriteRZ, STAMTYPE_PROFILE, "IO/WriteRZ", STAMUNIT_TICKS_PER_CALL, "Profiling IO writes in RZ");
8033 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatIOWriteR3, STAMTYPE_PROFILE, "IO/WriteR3", STAMUNIT_TICKS_PER_CALL, "Profiling IO writes in R3");
8034 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatLateIntTimer, STAMTYPE_PROFILE, "LateInt/Timer", STAMUNIT_TICKS_PER_CALL, "Profiling late int timer");
8035 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatLateInts, STAMTYPE_COUNTER, "LateInt/Occured", STAMUNIT_OCCURENCES, "Number of late interrupts");
8036 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatIntsRaised, STAMTYPE_COUNTER, "Interrupts/Raised", STAMUNIT_OCCURENCES, "Number of raised interrupts");
8037 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatIntsPrevented, STAMTYPE_COUNTER, "Interrupts/Prevented", STAMUNIT_OCCURENCES, "Number of prevented interrupts");
8038 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatReceive, STAMTYPE_PROFILE, "Receive/Total", STAMUNIT_TICKS_PER_CALL, "Profiling receive");
8039 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatReceiveCRC, STAMTYPE_PROFILE, "Receive/CRC", STAMUNIT_TICKS_PER_CALL, "Profiling receive checksumming");
8040 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatReceiveFilter, STAMTYPE_PROFILE, "Receive/Filter", STAMUNIT_TICKS_PER_CALL, "Profiling receive filtering");
8041 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatReceiveStore, STAMTYPE_PROFILE, "Receive/Store", STAMUNIT_TICKS_PER_CALL, "Profiling receive storing");
8042 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatRxOverflow, STAMTYPE_PROFILE, "RxOverflow", STAMUNIT_TICKS_PER_OCCURENCE, "Profiling RX overflows");
8043 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatRxOverflowWakeupRZ, STAMTYPE_COUNTER, "RxOverflowWakeupRZ", STAMUNIT_OCCURENCES, "Nr of RX overflow wakeups in RZ");
8044 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatRxOverflowWakeupR3, STAMTYPE_COUNTER, "RxOverflowWakeupR3", STAMUNIT_OCCURENCES, "Nr of RX overflow wakeups in R3");
8045 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatTransmitRZ, STAMTYPE_PROFILE, "Transmit/TotalRZ", STAMUNIT_TICKS_PER_CALL, "Profiling transmits in RZ");
8046 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatTransmitR3, STAMTYPE_PROFILE, "Transmit/TotalR3", STAMUNIT_TICKS_PER_CALL, "Profiling transmits in R3");
8047 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatTransmitSendRZ, STAMTYPE_PROFILE, "Transmit/SendRZ", STAMUNIT_TICKS_PER_CALL, "Profiling send transmit in RZ");
8048 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatTransmitSendR3, STAMTYPE_PROFILE, "Transmit/SendR3", STAMUNIT_TICKS_PER_CALL, "Profiling send transmit in R3");
8049
8050 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatTxDescCtxNormal, STAMTYPE_COUNTER, "TxDesc/ContexNormal", STAMUNIT_OCCURENCES, "Number of normal context descriptors");
8051 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatTxDescCtxTSE, STAMTYPE_COUNTER, "TxDesc/ContextTSE", STAMUNIT_OCCURENCES, "Number of TSE context descriptors");
8052 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatTxDescData, STAMTYPE_COUNTER, "TxDesc/Data", STAMUNIT_OCCURENCES, "Number of TX data descriptors");
8053 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatTxDescLegacy, STAMTYPE_COUNTER, "TxDesc/Legacy", STAMUNIT_OCCURENCES, "Number of TX legacy descriptors");
8054 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatTxDescTSEData, STAMTYPE_COUNTER, "TxDesc/TSEData", STAMUNIT_OCCURENCES, "Number of TX TSE data descriptors");
8055 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatTxPathFallback, STAMTYPE_COUNTER, "TxPath/Fallback", STAMUNIT_OCCURENCES, "Fallback TSE descriptor path");
8056 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatTxPathGSO, STAMTYPE_COUNTER, "TxPath/GSO", STAMUNIT_OCCURENCES, "GSO TSE descriptor path");
8057 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatTxPathRegular, STAMTYPE_COUNTER, "TxPath/Normal", STAMUNIT_OCCURENCES, "Regular descriptor path");
8058 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatPHYAccesses, STAMTYPE_COUNTER, "PHYAccesses", STAMUNIT_OCCURENCES, "Number of PHY accesses");
8059 for (unsigned iReg = 0; iReg < E1K_NUM_OF_REGS; iReg++)
8060 {
8061 PDMDevHlpSTAMRegisterF(pDevIns, &pThis->aStatRegReads[iReg], STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES,
8062 g_aE1kRegMap[iReg].name, "Regs/%s-Reads", g_aE1kRegMap[iReg].abbrev);
8063 PDMDevHlpSTAMRegisterF(pDevIns, &pThis->aStatRegWrites[iReg], STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES,
8064 g_aE1kRegMap[iReg].name, "Regs/%s-Writes", g_aE1kRegMap[iReg].abbrev);
8065 }
8066#endif /* VBOX_WITH_STATISTICS */
8067
8068#ifdef E1K_INT_STATS
8069 PDMDevHlpSTAMRegister(pDevIns, &pThis->u64ArmedAt, STAMTYPE_U64, "u64ArmedAt", STAMUNIT_NS, NULL);
8070 PDMDevHlpSTAMRegister(pDevIns, &pThis->uStatMaxTxDelay, STAMTYPE_U64, "uStatMaxTxDelay", STAMUNIT_NS, NULL);
8071 PDMDevHlpSTAMRegister(pDevIns, &pThis->uStatInt, STAMTYPE_U32, "uStatInt", STAMUNIT_NS, NULL);
8072 PDMDevHlpSTAMRegister(pDevIns, &pThis->uStatIntTry, STAMTYPE_U32, "uStatIntTry", STAMUNIT_NS, NULL);
8073 PDMDevHlpSTAMRegister(pDevIns, &pThis->uStatIntLower, STAMTYPE_U32, "uStatIntLower", STAMUNIT_NS, NULL);
8074 PDMDevHlpSTAMRegister(pDevIns, &pThis->uStatNoIntICR, STAMTYPE_U32, "uStatNoIntICR", STAMUNIT_NS, NULL);
8075 PDMDevHlpSTAMRegister(pDevIns, &pThis->iStatIntLost, STAMTYPE_U32, "iStatIntLost", STAMUNIT_NS, NULL);
8076 PDMDevHlpSTAMRegister(pDevIns, &pThis->iStatIntLostOne, STAMTYPE_U32, "iStatIntLostOne", STAMUNIT_NS, NULL);
8077 PDMDevHlpSTAMRegister(pDevIns, &pThis->uStatIntIMS, STAMTYPE_U32, "uStatIntIMS", STAMUNIT_NS, NULL);
8078 PDMDevHlpSTAMRegister(pDevIns, &pThis->uStatIntSkip, STAMTYPE_U32, "uStatIntSkip", STAMUNIT_NS, NULL);
8079 PDMDevHlpSTAMRegister(pDevIns, &pThis->uStatIntLate, STAMTYPE_U32, "uStatIntLate", STAMUNIT_NS, NULL);
8080 PDMDevHlpSTAMRegister(pDevIns, &pThis->uStatIntMasked, STAMTYPE_U32, "uStatIntMasked", STAMUNIT_NS, NULL);
8081 PDMDevHlpSTAMRegister(pDevIns, &pThis->uStatIntEarly, STAMTYPE_U32, "uStatIntEarly", STAMUNIT_NS, NULL);
8082 PDMDevHlpSTAMRegister(pDevIns, &pThis->uStatIntRx, STAMTYPE_U32, "uStatIntRx", STAMUNIT_NS, NULL);
8083 PDMDevHlpSTAMRegister(pDevIns, &pThis->uStatIntTx, STAMTYPE_U32, "uStatIntTx", STAMUNIT_NS, NULL);
8084 PDMDevHlpSTAMRegister(pDevIns, &pThis->uStatIntICS, STAMTYPE_U32, "uStatIntICS", STAMUNIT_NS, NULL);
8085 PDMDevHlpSTAMRegister(pDevIns, &pThis->uStatIntRDTR, STAMTYPE_U32, "uStatIntRDTR", STAMUNIT_NS, NULL);
8086 PDMDevHlpSTAMRegister(pDevIns, &pThis->uStatIntRXDMT0, STAMTYPE_U32, "uStatIntRXDMT0", STAMUNIT_NS, NULL);
8087 PDMDevHlpSTAMRegister(pDevIns, &pThis->uStatIntTXQE, STAMTYPE_U32, "uStatIntTXQE", STAMUNIT_NS, NULL);
8088 PDMDevHlpSTAMRegister(pDevIns, &pThis->uStatTxNoRS, STAMTYPE_U32, "uStatTxNoRS", STAMUNIT_NS, NULL);
8089 PDMDevHlpSTAMRegister(pDevIns, &pThis->uStatTxIDE, STAMTYPE_U32, "uStatTxIDE", STAMUNIT_NS, NULL);
8090 PDMDevHlpSTAMRegister(pDevIns, &pThis->uStatTxDelayed, STAMTYPE_U32, "uStatTxDelayed", STAMUNIT_NS, NULL);
8091 PDMDevHlpSTAMRegister(pDevIns, &pThis->uStatTxDelayExp, STAMTYPE_U32, "uStatTxDelayExp", STAMUNIT_NS, NULL);
8092 PDMDevHlpSTAMRegister(pDevIns, &pThis->uStatTAD, STAMTYPE_U32, "uStatTAD", STAMUNIT_NS, NULL);
8093 PDMDevHlpSTAMRegister(pDevIns, &pThis->uStatTID, STAMTYPE_U32, "uStatTID", STAMUNIT_NS, NULL);
8094 PDMDevHlpSTAMRegister(pDevIns, &pThis->uStatRAD, STAMTYPE_U32, "uStatRAD", STAMUNIT_NS, NULL);
8095 PDMDevHlpSTAMRegister(pDevIns, &pThis->uStatRID, STAMTYPE_U32, "uStatRID", STAMUNIT_NS, NULL);
8096 PDMDevHlpSTAMRegister(pDevIns, &pThis->uStatRxFrm, STAMTYPE_U32, "uStatRxFrm", STAMUNIT_NS, NULL);
8097 PDMDevHlpSTAMRegister(pDevIns, &pThis->uStatTxFrm, STAMTYPE_U32, "uStatTxFrm", STAMUNIT_NS, NULL);
8098 PDMDevHlpSTAMRegister(pDevIns, &pThis->uStatDescCtx, STAMTYPE_U32, "uStatDescCtx", STAMUNIT_NS, NULL);
8099 PDMDevHlpSTAMRegister(pDevIns, &pThis->uStatDescDat, STAMTYPE_U32, "uStatDescDat", STAMUNIT_NS, NULL);
8100 PDMDevHlpSTAMRegister(pDevIns, &pThis->uStatDescLeg, STAMTYPE_U32, "uStatDescLeg", STAMUNIT_NS, NULL);
8101 PDMDevHlpSTAMRegister(pDevIns, &pThis->uStatTx1514, STAMTYPE_U32, "uStatTx1514", STAMUNIT_NS, NULL);
8102 PDMDevHlpSTAMRegister(pDevIns, &pThis->uStatTx2962, STAMTYPE_U32, "uStatTx2962", STAMUNIT_NS, NULL);
8103 PDMDevHlpSTAMRegister(pDevIns, &pThis->uStatTx4410, STAMTYPE_U32, "uStatTx4410", STAMUNIT_NS, NULL);
8104 PDMDevHlpSTAMRegister(pDevIns, &pThis->uStatTx5858, STAMTYPE_U32, "uStatTx5858", STAMUNIT_NS, NULL);
8105 PDMDevHlpSTAMRegister(pDevIns, &pThis->uStatTx7306, STAMTYPE_U32, "uStatTx7306", STAMUNIT_NS, NULL);
8106 PDMDevHlpSTAMRegister(pDevIns, &pThis->uStatTx8754, STAMTYPE_U32, "uStatTx8754", STAMUNIT_NS, NULL);
8107 PDMDevHlpSTAMRegister(pDevIns, &pThis->uStatTx16384, STAMTYPE_U32, "uStatTx16384", STAMUNIT_NS, NULL);
8108 PDMDevHlpSTAMRegister(pDevIns, &pThis->uStatTx32768, STAMTYPE_U32, "uStatTx32768", STAMUNIT_NS, NULL);
8109 PDMDevHlpSTAMRegister(pDevIns, &pThis->uStatTxLarge, STAMTYPE_U32, "uStatTxLarge", STAMUNIT_NS, NULL);
8110#endif /* E1K_INT_STATS */
8111
8112 return VINF_SUCCESS;
8113}
8114
8115#else /* !IN_RING3 */
8116
8117/**
8118 * @callback_method_impl{PDMDEVREGR0,pfnConstruct}
8119 */
8120static DECLCALLBACK(int) e1kRZConstruct(PPDMDEVINS pDevIns)
8121{
8122 PDMDEV_CHECK_VERSIONS_RETURN(pDevIns);
8123 PE1KSTATE pThis = PDMDEVINS_2_DATA(pDevIns, PE1KSTATE);
8124 PE1KSTATECC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PE1KSTATECC);
8125
8126 /* Initialize context specific state data: */
8127 pThisCC->CTX_SUFF(pDevIns) = pDevIns;
8128 /** @todo @bugref{9218} ring-0 driver stuff */
8129 pThisCC->CTX_SUFF(pDrv) = NULL;
8130 pThisCC->CTX_SUFF(pTxSg) = NULL;
8131
8132 /* Configure critical sections the same way: */
8133 int rc = PDMDevHlpSetDeviceCritSect(pDevIns, PDMDevHlpCritSectGetNop(pDevIns));
8134 AssertRCReturn(rc, rc);
8135
8136 /* Set up MMIO and I/O port callbacks for this context: */
8137 rc = PDMDevHlpMmioSetUpContext(pDevIns, pThis->hMmioRegion, e1kMMIOWrite, e1kMMIORead, NULL /*pvUser*/);
8138 AssertRCReturn(rc, rc);
8139
8140 rc = PDMDevHlpIoPortSetUpContext(pDevIns, pThis->hIoPorts, e1kIOPortOut, e1kIOPortIn, NULL /*pvUser*/);
8141 AssertRCReturn(rc, rc);
8142
8143 return VINF_SUCCESS;
8144}
8145
8146#endif /* !IN_RING3 */
8147
8148/**
8149 * The device registration structure.
8150 */
8151const PDMDEVREG g_DeviceE1000 =
8152{
8153 /* .u32version = */ PDM_DEVREG_VERSION,
8154 /* .uReserved0 = */ 0,
8155 /* .szName = */ "e1000",
8156 /* .fFlags = */ PDM_DEVREG_FLAGS_DEFAULT_BITS | PDM_DEVREG_FLAGS_RZ | PDM_DEVREG_FLAGS_NEW_STYLE,
8157 /* .fClass = */ PDM_DEVREG_CLASS_NETWORK,
8158 /* .cMaxInstances = */ ~0U,
8159 /* .uSharedVersion = */ 42,
8160 /* .cbInstanceShared = */ sizeof(E1KSTATE),
8161 /* .cbInstanceCC = */ sizeof(E1KSTATECC),
8162 /* .cbInstanceRC = */ sizeof(E1KSTATERC),
8163 /* .cMaxPciDevices = */ 1,
8164 /* .cMaxMsixVectors = */ 0,
8165 /* .pszDescription = */ "Intel PRO/1000 MT Desktop Ethernet.",
8166#if defined(IN_RING3)
8167 /* .pszRCMod = */ "VBoxDDRC.rc",
8168 /* .pszR0Mod = */ "VBoxDDR0.r0",
8169 /* .pfnConstruct = */ e1kR3Construct,
8170 /* .pfnDestruct = */ e1kR3Destruct,
8171 /* .pfnRelocate = */ e1kR3Relocate,
8172 /* .pfnMemSetup = */ NULL,
8173 /* .pfnPowerOn = */ NULL,
8174 /* .pfnReset = */ e1kR3Reset,
8175 /* .pfnSuspend = */ e1kR3Suspend,
8176 /* .pfnResume = */ NULL,
8177 /* .pfnAttach = */ e1kR3Attach,
8178 /* .pfnDeatch = */ e1kR3Detach,
8179 /* .pfnQueryInterface = */ NULL,
8180 /* .pfnInitComplete = */ NULL,
8181 /* .pfnPowerOff = */ e1kR3PowerOff,
8182 /* .pfnSoftReset = */ NULL,
8183 /* .pfnReserved0 = */ NULL,
8184 /* .pfnReserved1 = */ NULL,
8185 /* .pfnReserved2 = */ NULL,
8186 /* .pfnReserved3 = */ NULL,
8187 /* .pfnReserved4 = */ NULL,
8188 /* .pfnReserved5 = */ NULL,
8189 /* .pfnReserved6 = */ NULL,
8190 /* .pfnReserved7 = */ NULL,
8191#elif defined(IN_RING0)
8192 /* .pfnEarlyConstruct = */ NULL,
8193 /* .pfnConstruct = */ e1kRZConstruct,
8194 /* .pfnDestruct = */ NULL,
8195 /* .pfnFinalDestruct = */ NULL,
8196 /* .pfnRequest = */ NULL,
8197 /* .pfnReserved0 = */ NULL,
8198 /* .pfnReserved1 = */ NULL,
8199 /* .pfnReserved2 = */ NULL,
8200 /* .pfnReserved3 = */ NULL,
8201 /* .pfnReserved4 = */ NULL,
8202 /* .pfnReserved5 = */ NULL,
8203 /* .pfnReserved6 = */ NULL,
8204 /* .pfnReserved7 = */ NULL,
8205#elif defined(IN_RC)
8206 /* .pfnConstruct = */ e1kRZConstruct,
8207 /* .pfnReserved0 = */ NULL,
8208 /* .pfnReserved1 = */ NULL,
8209 /* .pfnReserved2 = */ NULL,
8210 /* .pfnReserved3 = */ NULL,
8211 /* .pfnReserved4 = */ NULL,
8212 /* .pfnReserved5 = */ NULL,
8213 /* .pfnReserved6 = */ NULL,
8214 /* .pfnReserved7 = */ NULL,
8215#else
8216# error "Not in IN_RING3, IN_RING0 or IN_RC!"
8217#endif
8218 /* .u32VersionEnd = */ PDM_DEVREG_VERSION
8219};
8220
8221#endif /* !VBOX_DEVICE_STRUCT_TESTCASE */
Note: See TracBrowser for help on using the repository browser.

© 2024 Oracle Support Privacy / Do Not Sell My Info Terms of Use Trademark Policy Automated Access Etiquette