VirtualBox

source: vbox/trunk/src/VBox/Devices/Network/DevE1000.cpp@ 33540

Last change on this file since 33540 was 33540, checked in by vboxsync, 14 years ago

*: spelling fixes, thanks Timeless!
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1/* $Id: DevE1000.cpp 33540 2010-10-28 09:27:05Z vboxsync $ */
2/** @file
3 * DevE1000 - Intel 82540EM Ethernet Controller Emulation.
4 *
5 * Implemented in accordance with the specification:
6 *
7 * PCI/PCI-X Family of Gigabit Ethernet Controllers Software Developer's Manual
8 * 82540EP/EM, 82541xx, 82544GC/EI, 82545GM/EM, 82546GB/EB, and 82547xx
9 *
10 * 317453-002 Revision 3.5
11 *
12 * @todo IPv6 checksum offloading support
13 * @todo VLAN checksum offloading support
14 * @todo Flexible Filter / Wakeup (optional?)
15 */
16
17/*
18 * Copyright (C) 2007-2010 Oracle Corporation
19 *
20 * This file is part of VirtualBox Open Source Edition (OSE), as
21 * available from http://www.virtualbox.org. This file is free software;
22 * you can redistribute it and/or modify it under the terms of the GNU
23 * General Public License (GPL) as published by the Free Software
24 * Foundation, in version 2 as it comes in the "COPYING" file of the
25 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
26 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
27 */
28
29#define LOG_GROUP LOG_GROUP_DEV_E1000
30
31//#define E1kLogRel(a) LogRel(a)
32#define E1kLogRel(a)
33
34/* Options */
35#define E1K_INIT_RA0
36#define E1K_LSC_ON_SLU
37#define E1K_ITR_ENABLED
38//#define E1K_GLOBAL_MUTEX
39//#define E1K_USE_TX_TIMERS
40//#define E1K_NO_TAD
41//#define E1K_REL_DEBUG
42//#define E1K_INT_STATS
43//#define E1K_REL_STATS
44//#define E1K_USE_SUPLIB_SEMEVENT
45//#define E1K_WITH_MSI
46
47#include <iprt/crc.h>
48#include <iprt/ctype.h>
49#include <iprt/net.h>
50#include <iprt/semaphore.h>
51#include <iprt/string.h>
52#include <iprt/uuid.h>
53#include <VBox/pdmdev.h>
54#include <VBox/pdmnetifs.h>
55#include <VBox/pdmnetinline.h>
56#include <VBox/param.h>
57#include "../Builtins.h"
58
59#include "DevEEPROM.h"
60#include "DevE1000Phy.h"
61
62/* Little helpers ************************************************************/
63#undef htons
64#undef ntohs
65#undef htonl
66#undef ntohl
67#define htons(x) ((((x) & 0xff00) >> 8) | (((x) & 0x00ff) << 8))
68#define ntohs(x) htons(x)
69#define htonl(x) ASMByteSwapU32(x)
70#define ntohl(x) htonl(x)
71
72#ifndef DEBUG
73# ifdef E1K_REL_STATS
74# undef STAM_COUNTER_INC
75# undef STAM_PROFILE_ADV_START
76# undef STAM_PROFILE_ADV_STOP
77# define STAM_COUNTER_INC STAM_REL_COUNTER_INC
78# define STAM_PROFILE_ADV_START STAM_REL_PROFILE_ADV_START
79# define STAM_PROFILE_ADV_STOP STAM_REL_PROFILE_ADV_STOP
80# endif
81# ifdef E1K_REL_DEBUG
82# define DEBUG
83# define E1kLog(a) LogRel(a)
84# define E1kLog2(a) LogRel(a)
85# define E1kLog3(a) LogRel(a)
86//# define E1kLog3(a) do {} while (0)
87# else
88# define E1kLog(a) do {} while (0)
89# define E1kLog2(a) do {} while (0)
90# define E1kLog3(a) do {} while (0)
91# endif
92#else
93# define E1kLog(a) Log(a)
94# define E1kLog2(a) Log2(a)
95# define E1kLog3(a) Log3(a)
96//# define E1kLog(a) do {} while (0)
97//# define E1kLog2(a) do {} while (0)
98//# define E1kLog3(a) do {} while (0)
99#endif
100
101//#undef DEBUG
102
103#define INSTANCE(pState) pState->szInstance
104#define STATE_TO_DEVINS(pState) (((E1KSTATE *)pState)->CTX_SUFF(pDevIns))
105#define E1K_RELOCATE(p, o) *(RTHCUINTPTR *)&p += o
106
107#define E1K_INC_CNT32(cnt) \
108do { \
109 if (cnt < UINT32_MAX) \
110 cnt++; \
111} while (0)
112
113#define E1K_ADD_CNT64(cntLo, cntHi, val) \
114do { \
115 uint64_t u64Cnt = RT_MAKE_U64(cntLo, cntHi); \
116 uint64_t tmp = u64Cnt; \
117 u64Cnt += val; \
118 if (tmp > u64Cnt ) \
119 u64Cnt = UINT64_MAX; \
120 cntLo = (uint32_t)u64Cnt; \
121 cntHi = (uint32_t)(u64Cnt >> 32); \
122} while (0)
123
124#ifdef E1K_INT_STATS
125# define E1K_INC_ISTAT_CNT(cnt) ++cnt
126#else /* E1K_INT_STATS */
127# define E1K_INC_ISTAT_CNT(cnt)
128#endif /* E1K_INT_STATS */
129
130
131/*****************************************************************************/
132
133typedef uint32_t E1KCHIP;
134#define E1K_CHIP_82540EM 0
135#define E1K_CHIP_82543GC 1
136#define E1K_CHIP_82545EM 2
137
138struct E1kChips
139{
140 uint16_t uPCIVendorId;
141 uint16_t uPCIDeviceId;
142 uint16_t uPCISubsystemVendorId;
143 uint16_t uPCISubsystemId;
144 const char *pcszName;
145} g_Chips[] =
146{
147 /* Vendor Device SSVendor SubSys Name */
148 { 0x8086,
149 /* Temporary code, as MSI-aware driver dislike 0x100E. How to do that right? */
150#ifdef E1K_WITH_MSI
151 0x105E,
152#else
153 0x100E,
154#endif
155 0x8086, 0x001E, "82540EM" }, /* Intel 82540EM-A in Intel PRO/1000 MT Desktop */
156 { 0x8086, 0x1004, 0x8086, 0x1004, "82543GC" }, /* Intel 82543GC in Intel PRO/1000 T Server */
157 { 0x8086, 0x100F, 0x15AD, 0x0750, "82545EM" } /* Intel 82545EM-A in VMWare Network Adapter */
158};
159
160
161/* The size of register area mapped to I/O space */
162#define E1K_IOPORT_SIZE 0x8
163/* The size of memory-mapped register area */
164#define E1K_MM_SIZE 0x20000
165
166#define E1K_MAX_TX_PKT_SIZE 16288
167#define E1K_MAX_RX_PKT_SIZE 16384
168
169/*****************************************************************************/
170
171/** Gets the specfieid bits from the register. */
172#define GET_BITS(reg, bits) ((reg & reg##_##bits##_MASK) >> reg##_##bits##_SHIFT)
173#define GET_BITS_V(val, reg, bits) ((val & reg##_##bits##_MASK) >> reg##_##bits##_SHIFT)
174#define BITS(reg, bits, bitval) (bitval << reg##_##bits##_SHIFT)
175#define SET_BITS(reg, bits, bitval) do { reg = (reg & ~reg##_##bits##_MASK) | (bitval << reg##_##bits##_SHIFT); } while (0)
176#define SET_BITS_V(val, reg, bits, bitval) do { val = (val & ~reg##_##bits##_MASK) | (bitval << reg##_##bits##_SHIFT); } while (0)
177
178#define CTRL_SLU 0x00000040
179#define CTRL_MDIO 0x00100000
180#define CTRL_MDC 0x00200000
181#define CTRL_MDIO_DIR 0x01000000
182#define CTRL_MDC_DIR 0x02000000
183#define CTRL_RESET 0x04000000
184#define CTRL_VME 0x40000000
185
186#define STATUS_LU 0x00000002
187
188#define EECD_EE_WIRES 0x0F
189#define EECD_EE_REQ 0x40
190#define EECD_EE_GNT 0x80
191
192#define EERD_START 0x00000001
193#define EERD_DONE 0x00000010
194#define EERD_DATA_MASK 0xFFFF0000
195#define EERD_DATA_SHIFT 16
196#define EERD_ADDR_MASK 0x0000FF00
197#define EERD_ADDR_SHIFT 8
198
199#define MDIC_DATA_MASK 0x0000FFFF
200#define MDIC_DATA_SHIFT 0
201#define MDIC_REG_MASK 0x001F0000
202#define MDIC_REG_SHIFT 16
203#define MDIC_PHY_MASK 0x03E00000
204#define MDIC_PHY_SHIFT 21
205#define MDIC_OP_WRITE 0x04000000
206#define MDIC_OP_READ 0x08000000
207#define MDIC_READY 0x10000000
208#define MDIC_INT_EN 0x20000000
209#define MDIC_ERROR 0x40000000
210
211#define TCTL_EN 0x00000002
212#define TCTL_PSP 0x00000008
213
214#define RCTL_EN 0x00000002
215#define RCTL_UPE 0x00000008
216#define RCTL_MPE 0x00000010
217#define RCTL_LPE 0x00000020
218#define RCTL_LBM_MASK 0x000000C0
219#define RCTL_LBM_SHIFT 6
220#define RCTL_RDMTS_MASK 0x00000300
221#define RCTL_RDMTS_SHIFT 8
222#define RCTL_LBM_TCVR 3 /**< PHY or external SerDes loopback. */
223#define RCTL_MO_MASK 0x00003000
224#define RCTL_MO_SHIFT 12
225#define RCTL_BAM 0x00008000
226#define RCTL_BSIZE_MASK 0x00030000
227#define RCTL_BSIZE_SHIFT 16
228#define RCTL_VFE 0x00040000
229#define RCTL_BSEX 0x02000000
230#define RCTL_SECRC 0x04000000
231
232#define ICR_TXDW 0x00000001
233#define ICR_TXQE 0x00000002
234#define ICR_LSC 0x00000004
235#define ICR_RXDMT0 0x00000010
236#define ICR_RXT0 0x00000080
237#define ICR_TXD_LOW 0x00008000
238#define RDTR_FPD 0x80000000
239
240#define PBA_st ((PBAST*)(pState->auRegs + PBA_IDX))
241typedef struct
242{
243 unsigned rxa : 7;
244 unsigned rxa_r : 9;
245 unsigned txa : 16;
246} PBAST;
247AssertCompileSize(PBAST, 4);
248
249#define TXDCTL_WTHRESH_MASK 0x003F0000
250#define TXDCTL_WTHRESH_SHIFT 16
251#define TXDCTL_LWTHRESH_MASK 0xFE000000
252#define TXDCTL_LWTHRESH_SHIFT 25
253
254#define RXCSUM_PCSS_MASK 0x000000FF
255#define RXCSUM_PCSS_SHIFT 0
256
257/* Register access macros ****************************************************/
258#define CTRL pState->auRegs[CTRL_IDX]
259#define STATUS pState->auRegs[STATUS_IDX]
260#define EECD pState->auRegs[EECD_IDX]
261#define EERD pState->auRegs[EERD_IDX]
262#define CTRL_EXT pState->auRegs[CTRL_EXT_IDX]
263#define FLA pState->auRegs[FLA_IDX]
264#define MDIC pState->auRegs[MDIC_IDX]
265#define FCAL pState->auRegs[FCAL_IDX]
266#define FCAH pState->auRegs[FCAH_IDX]
267#define FCT pState->auRegs[FCT_IDX]
268#define VET pState->auRegs[VET_IDX]
269#define ICR pState->auRegs[ICR_IDX]
270#define ITR pState->auRegs[ITR_IDX]
271#define ICS pState->auRegs[ICS_IDX]
272#define IMS pState->auRegs[IMS_IDX]
273#define IMC pState->auRegs[IMC_IDX]
274#define RCTL pState->auRegs[RCTL_IDX]
275#define FCTTV pState->auRegs[FCTTV_IDX]
276#define TXCW pState->auRegs[TXCW_IDX]
277#define RXCW pState->auRegs[RXCW_IDX]
278#define TCTL pState->auRegs[TCTL_IDX]
279#define TIPG pState->auRegs[TIPG_IDX]
280#define AIFS pState->auRegs[AIFS_IDX]
281#define LEDCTL pState->auRegs[LEDCTL_IDX]
282#define PBA pState->auRegs[PBA_IDX]
283#define FCRTL pState->auRegs[FCRTL_IDX]
284#define FCRTH pState->auRegs[FCRTH_IDX]
285#define RDFH pState->auRegs[RDFH_IDX]
286#define RDFT pState->auRegs[RDFT_IDX]
287#define RDFHS pState->auRegs[RDFHS_IDX]
288#define RDFTS pState->auRegs[RDFTS_IDX]
289#define RDFPC pState->auRegs[RDFPC_IDX]
290#define RDBAL pState->auRegs[RDBAL_IDX]
291#define RDBAH pState->auRegs[RDBAH_IDX]
292#define RDLEN pState->auRegs[RDLEN_IDX]
293#define RDH pState->auRegs[RDH_IDX]
294#define RDT pState->auRegs[RDT_IDX]
295#define RDTR pState->auRegs[RDTR_IDX]
296#define RXDCTL pState->auRegs[RXDCTL_IDX]
297#define RADV pState->auRegs[RADV_IDX]
298#define RSRPD pState->auRegs[RSRPD_IDX]
299#define TXDMAC pState->auRegs[TXDMAC_IDX]
300#define TDFH pState->auRegs[TDFH_IDX]
301#define TDFT pState->auRegs[TDFT_IDX]
302#define TDFHS pState->auRegs[TDFHS_IDX]
303#define TDFTS pState->auRegs[TDFTS_IDX]
304#define TDFPC pState->auRegs[TDFPC_IDX]
305#define TDBAL pState->auRegs[TDBAL_IDX]
306#define TDBAH pState->auRegs[TDBAH_IDX]
307#define TDLEN pState->auRegs[TDLEN_IDX]
308#define TDH pState->auRegs[TDH_IDX]
309#define TDT pState->auRegs[TDT_IDX]
310#define TIDV pState->auRegs[TIDV_IDX]
311#define TXDCTL pState->auRegs[TXDCTL_IDX]
312#define TADV pState->auRegs[TADV_IDX]
313#define TSPMT pState->auRegs[TSPMT_IDX]
314#define CRCERRS pState->auRegs[CRCERRS_IDX]
315#define ALGNERRC pState->auRegs[ALGNERRC_IDX]
316#define SYMERRS pState->auRegs[SYMERRS_IDX]
317#define RXERRC pState->auRegs[RXERRC_IDX]
318#define MPC pState->auRegs[MPC_IDX]
319#define SCC pState->auRegs[SCC_IDX]
320#define ECOL pState->auRegs[ECOL_IDX]
321#define MCC pState->auRegs[MCC_IDX]
322#define LATECOL pState->auRegs[LATECOL_IDX]
323#define COLC pState->auRegs[COLC_IDX]
324#define DC pState->auRegs[DC_IDX]
325#define TNCRS pState->auRegs[TNCRS_IDX]
326#define SEC pState->auRegs[SEC_IDX]
327#define CEXTERR pState->auRegs[CEXTERR_IDX]
328#define RLEC pState->auRegs[RLEC_IDX]
329#define XONRXC pState->auRegs[XONRXC_IDX]
330#define XONTXC pState->auRegs[XONTXC_IDX]
331#define XOFFRXC pState->auRegs[XOFFRXC_IDX]
332#define XOFFTXC pState->auRegs[XOFFTXC_IDX]
333#define FCRUC pState->auRegs[FCRUC_IDX]
334#define PRC64 pState->auRegs[PRC64_IDX]
335#define PRC127 pState->auRegs[PRC127_IDX]
336#define PRC255 pState->auRegs[PRC255_IDX]
337#define PRC511 pState->auRegs[PRC511_IDX]
338#define PRC1023 pState->auRegs[PRC1023_IDX]
339#define PRC1522 pState->auRegs[PRC1522_IDX]
340#define GPRC pState->auRegs[GPRC_IDX]
341#define BPRC pState->auRegs[BPRC_IDX]
342#define MPRC pState->auRegs[MPRC_IDX]
343#define GPTC pState->auRegs[GPTC_IDX]
344#define GORCL pState->auRegs[GORCL_IDX]
345#define GORCH pState->auRegs[GORCH_IDX]
346#define GOTCL pState->auRegs[GOTCL_IDX]
347#define GOTCH pState->auRegs[GOTCH_IDX]
348#define RNBC pState->auRegs[RNBC_IDX]
349#define RUC pState->auRegs[RUC_IDX]
350#define RFC pState->auRegs[RFC_IDX]
351#define ROC pState->auRegs[ROC_IDX]
352#define RJC pState->auRegs[RJC_IDX]
353#define MGTPRC pState->auRegs[MGTPRC_IDX]
354#define MGTPDC pState->auRegs[MGTPDC_IDX]
355#define MGTPTC pState->auRegs[MGTPTC_IDX]
356#define TORL pState->auRegs[TORL_IDX]
357#define TORH pState->auRegs[TORH_IDX]
358#define TOTL pState->auRegs[TOTL_IDX]
359#define TOTH pState->auRegs[TOTH_IDX]
360#define TPR pState->auRegs[TPR_IDX]
361#define TPT pState->auRegs[TPT_IDX]
362#define PTC64 pState->auRegs[PTC64_IDX]
363#define PTC127 pState->auRegs[PTC127_IDX]
364#define PTC255 pState->auRegs[PTC255_IDX]
365#define PTC511 pState->auRegs[PTC511_IDX]
366#define PTC1023 pState->auRegs[PTC1023_IDX]
367#define PTC1522 pState->auRegs[PTC1522_IDX]
368#define MPTC pState->auRegs[MPTC_IDX]
369#define BPTC pState->auRegs[BPTC_IDX]
370#define TSCTC pState->auRegs[TSCTC_IDX]
371#define TSCTFC pState->auRegs[TSCTFC_IDX]
372#define RXCSUM pState->auRegs[RXCSUM_IDX]
373#define WUC pState->auRegs[WUC_IDX]
374#define WUFC pState->auRegs[WUFC_IDX]
375#define WUS pState->auRegs[WUS_IDX]
376#define MANC pState->auRegs[MANC_IDX]
377#define IPAV pState->auRegs[IPAV_IDX]
378#define WUPL pState->auRegs[WUPL_IDX]
379
380/**
381 * Indices of memory-mapped registers in register table
382 */
383typedef enum
384{
385 CTRL_IDX,
386 STATUS_IDX,
387 EECD_IDX,
388 EERD_IDX,
389 CTRL_EXT_IDX,
390 FLA_IDX,
391 MDIC_IDX,
392 FCAL_IDX,
393 FCAH_IDX,
394 FCT_IDX,
395 VET_IDX,
396 ICR_IDX,
397 ITR_IDX,
398 ICS_IDX,
399 IMS_IDX,
400 IMC_IDX,
401 RCTL_IDX,
402 FCTTV_IDX,
403 TXCW_IDX,
404 RXCW_IDX,
405 TCTL_IDX,
406 TIPG_IDX,
407 AIFS_IDX,
408 LEDCTL_IDX,
409 PBA_IDX,
410 FCRTL_IDX,
411 FCRTH_IDX,
412 RDFH_IDX,
413 RDFT_IDX,
414 RDFHS_IDX,
415 RDFTS_IDX,
416 RDFPC_IDX,
417 RDBAL_IDX,
418 RDBAH_IDX,
419 RDLEN_IDX,
420 RDH_IDX,
421 RDT_IDX,
422 RDTR_IDX,
423 RXDCTL_IDX,
424 RADV_IDX,
425 RSRPD_IDX,
426 TXDMAC_IDX,
427 TDFH_IDX,
428 TDFT_IDX,
429 TDFHS_IDX,
430 TDFTS_IDX,
431 TDFPC_IDX,
432 TDBAL_IDX,
433 TDBAH_IDX,
434 TDLEN_IDX,
435 TDH_IDX,
436 TDT_IDX,
437 TIDV_IDX,
438 TXDCTL_IDX,
439 TADV_IDX,
440 TSPMT_IDX,
441 CRCERRS_IDX,
442 ALGNERRC_IDX,
443 SYMERRS_IDX,
444 RXERRC_IDX,
445 MPC_IDX,
446 SCC_IDX,
447 ECOL_IDX,
448 MCC_IDX,
449 LATECOL_IDX,
450 COLC_IDX,
451 DC_IDX,
452 TNCRS_IDX,
453 SEC_IDX,
454 CEXTERR_IDX,
455 RLEC_IDX,
456 XONRXC_IDX,
457 XONTXC_IDX,
458 XOFFRXC_IDX,
459 XOFFTXC_IDX,
460 FCRUC_IDX,
461 PRC64_IDX,
462 PRC127_IDX,
463 PRC255_IDX,
464 PRC511_IDX,
465 PRC1023_IDX,
466 PRC1522_IDX,
467 GPRC_IDX,
468 BPRC_IDX,
469 MPRC_IDX,
470 GPTC_IDX,
471 GORCL_IDX,
472 GORCH_IDX,
473 GOTCL_IDX,
474 GOTCH_IDX,
475 RNBC_IDX,
476 RUC_IDX,
477 RFC_IDX,
478 ROC_IDX,
479 RJC_IDX,
480 MGTPRC_IDX,
481 MGTPDC_IDX,
482 MGTPTC_IDX,
483 TORL_IDX,
484 TORH_IDX,
485 TOTL_IDX,
486 TOTH_IDX,
487 TPR_IDX,
488 TPT_IDX,
489 PTC64_IDX,
490 PTC127_IDX,
491 PTC255_IDX,
492 PTC511_IDX,
493 PTC1023_IDX,
494 PTC1522_IDX,
495 MPTC_IDX,
496 BPTC_IDX,
497 TSCTC_IDX,
498 TSCTFC_IDX,
499 RXCSUM_IDX,
500 WUC_IDX,
501 WUFC_IDX,
502 WUS_IDX,
503 MANC_IDX,
504 IPAV_IDX,
505 WUPL_IDX,
506 MTA_IDX,
507 RA_IDX,
508 VFTA_IDX,
509 IP4AT_IDX,
510 IP6AT_IDX,
511 WUPM_IDX,
512 FFLT_IDX,
513 FFMT_IDX,
514 FFVT_IDX,
515 PBM_IDX,
516 RA_82542_IDX,
517 MTA_82542_IDX,
518 VFTA_82542_IDX,
519 E1K_NUM_OF_REGS
520} E1kRegIndex;
521
522#define E1K_NUM_OF_32BIT_REGS MTA_IDX
523
524
525/**
526 * Define E1000-specific EEPROM layout.
527 */
528class E1kEEPROM
529{
530 public:
531 EEPROM93C46 eeprom;
532
533#ifdef IN_RING3
534 /**
535 * Initialize EEPROM content.
536 *
537 * @param macAddr MAC address of E1000.
538 */
539 void init(RTMAC &macAddr)
540 {
541 eeprom.init();
542 memcpy(eeprom.m_au16Data, macAddr.au16, sizeof(macAddr.au16));
543 eeprom.m_au16Data[0x04] = 0xFFFF;
544 /*
545 * bit 3 - full support for power management
546 * bit 10 - full duplex
547 */
548 eeprom.m_au16Data[0x0A] = 0x4408;
549 eeprom.m_au16Data[0x0B] = 0x001E;
550 eeprom.m_au16Data[0x0C] = 0x8086;
551 eeprom.m_au16Data[0x0D] = 0x100E;
552 eeprom.m_au16Data[0x0E] = 0x8086;
553 eeprom.m_au16Data[0x0F] = 0x3040;
554 eeprom.m_au16Data[0x21] = 0x7061;
555 eeprom.m_au16Data[0x22] = 0x280C;
556 eeprom.m_au16Data[0x23] = 0x00C8;
557 eeprom.m_au16Data[0x24] = 0x00C8;
558 eeprom.m_au16Data[0x2F] = 0x0602;
559 updateChecksum();
560 };
561
562 /**
563 * Compute the checksum as required by E1000 and store it
564 * in the last word.
565 */
566 void updateChecksum()
567 {
568 uint16_t u16Checksum = 0;
569
570 for (int i = 0; i < eeprom.SIZE-1; i++)
571 u16Checksum += eeprom.m_au16Data[i];
572 eeprom.m_au16Data[eeprom.SIZE-1] = 0xBABA - u16Checksum;
573 };
574
575 /**
576 * First 6 bytes of EEPROM contain MAC address.
577 *
578 * @returns MAC address of E1000.
579 */
580 void getMac(PRTMAC pMac)
581 {
582 memcpy(pMac->au16, eeprom.m_au16Data, sizeof(pMac->au16));
583 };
584
585 uint32_t read()
586 {
587 return eeprom.read();
588 }
589
590 void write(uint32_t u32Wires)
591 {
592 eeprom.write(u32Wires);
593 }
594
595 bool readWord(uint32_t u32Addr, uint16_t *pu16Value)
596 {
597 return eeprom.readWord(u32Addr, pu16Value);
598 }
599
600 int load(PSSMHANDLE pSSM)
601 {
602 return eeprom.load(pSSM);
603 }
604
605 void save(PSSMHANDLE pSSM)
606 {
607 eeprom.save(pSSM);
608 }
609#endif /* IN_RING3 */
610};
611
612
613struct E1kRxDStatus
614{
615 /** @name Descriptor Status field (3.2.3.1)
616 * @{ */
617 unsigned fDD : 1; /**< Descriptor Done. */
618 unsigned fEOP : 1; /**< End of packet. */
619 unsigned fIXSM : 1; /**< Ignore checksum indication. */
620 unsigned fVP : 1; /**< VLAN, matches VET. */
621 unsigned : 1;
622 unsigned fTCPCS : 1; /**< RCP Checksum calculated on the packet. */
623 unsigned fIPCS : 1; /**< IP Checksum calculated on the packet. */
624 unsigned fPIF : 1; /**< Passed in-exact filter */
625 /** @} */
626 /** @name Descriptor Errors field (3.2.3.2)
627 * (Only valid when fEOP and fDD are set.)
628 * @{ */
629 unsigned fCE : 1; /**< CRC or alignment error. */
630 unsigned : 4; /**< Reserved, varies with different models... */
631 unsigned fTCPE : 1; /**< TCP/UDP checksum error. */
632 unsigned fIPE : 1; /**< IP Checksum error. */
633 unsigned fRXE : 1; /**< RX Data error. */
634 /** @} */
635 /** @name Descriptor Special field (3.2.3.3)
636 * @{ */
637 unsigned u12VLAN : 12; /**< VLAN identifier. */
638 unsigned fCFI : 1; /**< Canonical form indicator (VLAN). */
639 unsigned u3PRI : 3; /**< User priority (VLAN). */
640 /** @} */
641};
642typedef struct E1kRxDStatus E1KRXDST;
643
644struct E1kRxDesc_st
645{
646 uint64_t u64BufAddr; /**< Address of data buffer */
647 uint16_t u16Length; /**< Length of data in buffer */
648 uint16_t u16Checksum; /**< Packet checksum */
649 E1KRXDST status;
650};
651typedef struct E1kRxDesc_st E1KRXDESC;
652AssertCompileSize(E1KRXDESC, 16);
653
654#define E1K_DTYP_LEGACY -1
655#define E1K_DTYP_CONTEXT 0
656#define E1K_DTYP_DATA 1
657
658struct E1kTDLegacy
659{
660 uint64_t u64BufAddr; /**< Address of data buffer */
661 struct TDLCmd_st
662 {
663 unsigned u16Length : 16;
664 unsigned u8CSO : 8;
665 /* CMD field : 8 */
666 unsigned fEOP : 1;
667 unsigned fIFCS : 1;
668 unsigned fIC : 1;
669 unsigned fRS : 1;
670 unsigned fRSV : 1;
671 unsigned fDEXT : 1;
672 unsigned fVLE : 1;
673 unsigned fIDE : 1;
674 } cmd;
675 struct TDLDw3_st
676 {
677 /* STA field */
678 unsigned fDD : 1;
679 unsigned fEC : 1;
680 unsigned fLC : 1;
681 unsigned fTURSV : 1;
682 /* RSV field */
683 unsigned u4RSV : 4;
684 /* CSS field */
685 unsigned u8CSS : 8;
686 /* Special field*/
687 unsigned u12VLAN : 12;
688 unsigned fCFI : 1;
689 unsigned u3PRI : 3;
690 } dw3;
691};
692
693/**
694 * TCP/IP Context Transmit Descriptor, section 3.3.6.
695 */
696struct E1kTDContext
697{
698 struct CheckSum_st
699 {
700 /** TSE: Header start. !TSE: Checksum start. */
701 unsigned u8CSS : 8;
702 /** Checksum offset - where to store it. */
703 unsigned u8CSO : 8;
704 /** Checksum ending (inclusive) offset, 0 = end of packet. */
705 unsigned u16CSE : 16;
706 } ip;
707 struct CheckSum_st tu;
708 struct TDCDw2_st
709 {
710 /** TSE: The total number of payload bytes for this context. Sans header. */
711 unsigned u20PAYLEN : 20;
712 /** The descriptor type - E1K_DTYP_CONTEXT (0). */
713 unsigned u4DTYP : 4;
714 /** TUCMD field, 8 bits
715 * @{ */
716 /** TSE: TCP (set) or UDP (clear). */
717 unsigned fTCP : 1;
718 /** TSE: IPv4 (set) or IPv6 (clear) - for finding the payload length field in
719 * the IP header. Does not affect the checksumming.
720 * @remarks 82544GC/EI interprets a cleared field differently. */
721 unsigned fIP : 1;
722 /** TSE: TCP segmentation enable. When clear the context describes */
723 unsigned fTSE : 1;
724 /** Report status (only applies to dw3.fDD for here). */
725 unsigned fRS : 1;
726 /** Reserved, MBZ. */
727 unsigned fRSV1 : 1;
728 /** Descriptor extension, must be set for this descriptor type. */
729 unsigned fDEXT : 1;
730 /** Reserved, MBZ. */
731 unsigned fRSV2 : 1;
732 /** Interrupt delay enable. */
733 unsigned fIDE : 1;
734 /** @} */
735 } dw2;
736 struct TDCDw3_st
737 {
738 /** Descriptor Done. */
739 unsigned fDD : 1;
740 /** Reserved, MBZ. */
741 unsigned u7RSV : 7;
742 /** TSO: The header (prototype) length (Ethernet[, VLAN tag], IP, TCP/UDP. */
743 unsigned u8HDRLEN : 8;
744 /** TSO: Maximum segment size. */
745 unsigned u16MSS : 16;
746 } dw3;
747};
748typedef struct E1kTDContext E1KTXCTX;
749
750/**
751 * TCP/IP Data Transmit Descriptor, section 3.3.7.
752 */
753struct E1kTDData
754{
755 uint64_t u64BufAddr; /**< Address of data buffer */
756 struct TDDCmd_st
757 {
758 /** The total length of data pointed to by this descriptor. */
759 unsigned u20DTALEN : 20;
760 /** The descriptor type - E1K_DTYP_DATA (1). */
761 unsigned u4DTYP : 4;
762 /** @name DCMD field, 8 bits (3.3.7.1).
763 * @{ */
764 /** End of packet. Note TSCTFC update. */
765 unsigned fEOP : 1;
766 /** Insert Ethernet FCS/CRC (requires fEOP to be set). */
767 unsigned fIFCS : 1;
768 /** Use the TSE context when set and the normal when clear. */
769 unsigned fTSE : 1;
770 /** Report status (dw3.STA). */
771 unsigned fRS : 1;
772 /** Reserved. 82544GC/EI defines this report packet set (RPS). */
773 unsigned fRSV : 1;
774 /** Descriptor extension, must be set for this descriptor type. */
775 unsigned fDEXT : 1;
776 /** VLAN enable, requires CTRL.VME, auto enables FCS/CRC.
777 * Insert dw3.SPECIAL after ethernet header. */
778 unsigned fVLE : 1;
779 /** Interrupt delay enable. */
780 unsigned fIDE : 1;
781 /** @} */
782 } cmd;
783 struct TDDDw3_st
784 {
785 /** @name STA field (3.3.7.2)
786 * @{ */
787 unsigned fDD : 1; /**< Descriptor done. */
788 unsigned fEC : 1; /**< Excess collision. */
789 unsigned fLC : 1; /**< Late collision. */
790 /** Reserved, except for the usual oddball (82544GC/EI) where it's called TU. */
791 unsigned fTURSV : 1;
792 /** @} */
793 unsigned u4RSV : 4; /**< Reserved field, MBZ. */
794 /** @name POPTS (Packet Option) field (3.3.7.3)
795 * @{ */
796 unsigned fIXSM : 1; /**< Insert IP checksum. */
797 unsigned fTXSM : 1; /**< Insert TCP/UDP checksum. */
798 unsigned u6RSV : 6; /**< Reserved, MBZ. */
799 /** @} */
800 /** @name SPECIAL field - VLAN tag to be inserted after ethernet header.
801 * Requires fEOP, fVLE and CTRL.VME to be set.
802 * @{ */
803 unsigned u12VLAN : 12; /**< VLAN identifier. */
804 unsigned fCFI : 1; /**< Canonical form indicator (VLAN). */
805 unsigned u3PRI : 3; /**< User priority (VLAN). */
806 /** @} */
807 } dw3;
808};
809typedef struct E1kTDData E1KTXDAT;
810
811union E1kTxDesc
812{
813 struct E1kTDLegacy legacy;
814 struct E1kTDContext context;
815 struct E1kTDData data;
816};
817typedef union E1kTxDesc E1KTXDESC;
818AssertCompileSize(E1KTXDESC, 16);
819
820#define RA_CTL_AS 0x0003
821#define RA_CTL_AV 0x8000
822
823union E1kRecAddr
824{
825 uint32_t au32[32];
826 struct RAArray
827 {
828 uint8_t addr[6];
829 uint16_t ctl;
830 } array[16];
831};
832typedef struct E1kRecAddr::RAArray E1KRAELEM;
833typedef union E1kRecAddr E1KRA;
834AssertCompileSize(E1KRA, 8*16);
835
836#define E1K_IP_RF 0x8000 /* reserved fragment flag */
837#define E1K_IP_DF 0x4000 /* dont fragment flag */
838#define E1K_IP_MF 0x2000 /* more fragments flag */
839#define E1K_IP_OFFMASK 0x1fff /* mask for fragmenting bits */
840
841/** @todo use+extend RTNETIPV4 */
842struct E1kIpHeader
843{
844 /* type of service / version / header length */
845 uint16_t tos_ver_hl;
846 /* total length */
847 uint16_t total_len;
848 /* identification */
849 uint16_t ident;
850 /* fragment offset field */
851 uint16_t offset;
852 /* time to live / protocol*/
853 uint16_t ttl_proto;
854 /* checksum */
855 uint16_t chksum;
856 /* source IP address */
857 uint32_t src;
858 /* destination IP address */
859 uint32_t dest;
860};
861AssertCompileSize(struct E1kIpHeader, 20);
862
863#define E1K_TCP_FIN 0x01U
864#define E1K_TCP_SYN 0x02U
865#define E1K_TCP_RST 0x04U
866#define E1K_TCP_PSH 0x08U
867#define E1K_TCP_ACK 0x10U
868#define E1K_TCP_URG 0x20U
869#define E1K_TCP_ECE 0x40U
870#define E1K_TCP_CWR 0x80U
871
872#define E1K_TCP_FLAGS 0x3fU
873
874/** @todo use+extend RTNETTCP */
875struct E1kTcpHeader
876{
877 uint16_t src;
878 uint16_t dest;
879 uint32_t seqno;
880 uint32_t ackno;
881 uint16_t hdrlen_flags;
882 uint16_t wnd;
883 uint16_t chksum;
884 uint16_t urgp;
885};
886AssertCompileSize(struct E1kTcpHeader, 20);
887
888
889/** The current Saved state version. */
890#define E1K_SAVEDSTATE_VERSION 2
891/** Saved state version for VirtualBox 3.0 and earlier.
892 * This did not include the configuration part nor the E1kEEPROM. */
893#define E1K_SAVEDSTATE_VERSION_VBOX_30 1
894
895/**
896 * Device state structure. Holds the current state of device.
897 *
898 * @implements PDMINETWORKDOWN
899 * @implements PDMINETWORKCONFIG
900 * @implements PDMILEDPORTS
901 */
902struct E1kState_st
903{
904 char szInstance[8]; /**< Instance name, e.g. E1000#1. */
905 PDMIBASE IBase;
906 PDMINETWORKDOWN INetworkDown;
907 PDMINETWORKCONFIG INetworkConfig;
908 PDMILEDPORTS ILeds; /**< LED interface */
909 R3PTRTYPE(PPDMIBASE) pDrvBase; /**< Attached network driver. */
910 R3PTRTYPE(PPDMILEDCONNECTORS) pLedsConnector;
911
912 PPDMDEVINSR3 pDevInsR3; /**< Device instance - R3. */
913 R3PTRTYPE(PPDMQUEUE) pTxQueueR3; /**< Transmit queue - R3. */
914 R3PTRTYPE(PPDMQUEUE) pCanRxQueueR3; /**< Rx wakeup signaller - R3. */
915 PPDMINETWORKUPR3 pDrvR3; /**< Attached network driver - R3. */
916 PTMTIMERR3 pRIDTimerR3; /**< Receive Interrupt Delay Timer - R3. */
917 PTMTIMERR3 pRADTimerR3; /**< Receive Absolute Delay Timer - R3. */
918 PTMTIMERR3 pTIDTimerR3; /**< Transmit Interrupt Delay Timer - R3. */
919 PTMTIMERR3 pTADTimerR3; /**< Transmit Absolute Delay Timer - R3. */
920 PTMTIMERR3 pIntTimerR3; /**< Late Interrupt Timer - R3. */
921 PTMTIMERR3 pLUTimerR3; /**< Link Up(/Restore) Timer. */
922 /** The scatter / gather buffer used for the current outgoing packet - R3. */
923 R3PTRTYPE(PPDMSCATTERGATHER) pTxSgR3;
924
925 PPDMDEVINSR0 pDevInsR0; /**< Device instance - R0. */
926 R0PTRTYPE(PPDMQUEUE) pTxQueueR0; /**< Transmit queue - R0. */
927 R0PTRTYPE(PPDMQUEUE) pCanRxQueueR0; /**< Rx wakeup signaller - R0. */
928 PPDMINETWORKUPR0 pDrvR0; /**< Attached network driver - R0. */
929 PTMTIMERR0 pRIDTimerR0; /**< Receive Interrupt Delay Timer - R0. */
930 PTMTIMERR0 pRADTimerR0; /**< Receive Absolute Delay Timer - R0. */
931 PTMTIMERR0 pTIDTimerR0; /**< Transmit Interrupt Delay Timer - R0. */
932 PTMTIMERR0 pTADTimerR0; /**< Transmit Absolute Delay Timer - R0. */
933 PTMTIMERR0 pIntTimerR0; /**< Late Interrupt Timer - R0. */
934 PTMTIMERR0 pLUTimerR0; /**< Link Up(/Restore) Timer - R0. */
935 /** The scatter / gather buffer used for the current outgoing packet - R0. */
936 R0PTRTYPE(PPDMSCATTERGATHER) pTxSgR0;
937
938 PPDMDEVINSRC pDevInsRC; /**< Device instance - RC. */
939 RCPTRTYPE(PPDMQUEUE) pTxQueueRC; /**< Transmit queue - RC. */
940 RCPTRTYPE(PPDMQUEUE) pCanRxQueueRC; /**< Rx wakeup signaller - RC. */
941 PPDMINETWORKUPRC pDrvRC; /**< Attached network driver - RC. */
942 PTMTIMERRC pRIDTimerRC; /**< Receive Interrupt Delay Timer - RC. */
943 PTMTIMERRC pRADTimerRC; /**< Receive Absolute Delay Timer - RC. */
944 PTMTIMERRC pTIDTimerRC; /**< Transmit Interrupt Delay Timer - RC. */
945 PTMTIMERRC pTADTimerRC; /**< Transmit Absolute Delay Timer - RC. */
946 PTMTIMERRC pIntTimerRC; /**< Late Interrupt Timer - RC. */
947 PTMTIMERRC pLUTimerRC; /**< Link Up(/Restore) Timer - RC. */
948 /** The scatter / gather buffer used for the current outgoing packet - RC. */
949 RCPTRTYPE(PPDMSCATTERGATHER) pTxSgRC;
950 RTRCPTR RCPtrAlignment;
951
952#if HC_ARCH_BITS == 32
953 uint32_t Alignment1;
954#endif
955 PDMCRITSECT cs; /**< Critical section - what is it protecting? */
956#ifndef E1K_GLOBAL_MUTEX
957 PDMCRITSECT csRx; /**< RX Critical section. */
958// PDMCRITSECT csTx; /**< TX Critical section. */
959#endif
960 /** Base address of memory-mapped registers. */
961 RTGCPHYS addrMMReg;
962 /** MAC address obtained from the configuration. */
963 RTMAC macConfigured;
964 /** Base port of I/O space region. */
965 RTIOPORT addrIOPort;
966 /** EMT: */
967 PCIDEVICE pciDevice;
968 /** EMT: Last time the interrupt was acknowledged. */
969 uint64_t u64AckedAt;
970 /** All: Used for eliminating spurious interrupts. */
971 bool fIntRaised;
972 /** EMT: false if the cable is disconnected by the GUI. */
973 bool fCableConnected;
974 /** EMT: */
975 bool fR0Enabled;
976 /** EMT: */
977 bool fGCEnabled;
978
979 /** All: Device register storage. */
980 uint32_t auRegs[E1K_NUM_OF_32BIT_REGS];
981 /** TX/RX: Status LED. */
982 PDMLED led;
983 /** TX/RX: Number of packet being sent/received to show in debug log. */
984 uint32_t u32PktNo;
985
986 /** EMT: Offset of the register to be read via IO. */
987 uint32_t uSelectedReg;
988 /** EMT: Multicast Table Array. */
989 uint32_t auMTA[128];
990 /** EMT: Receive Address registers. */
991 E1KRA aRecAddr;
992 /** EMT: VLAN filter table array. */
993 uint32_t auVFTA[128];
994 /** EMT: Receive buffer size. */
995 uint16_t u16RxBSize;
996 /** EMT: Locked state -- no state alteration possible. */
997 bool fLocked;
998 /** EMT: */
999 bool fDelayInts;
1000 /** All: */
1001 bool fIntMaskUsed;
1002
1003 /** N/A: */
1004 bool volatile fMaybeOutOfSpace;
1005 /** EMT: Gets signalled when more RX descriptors become available. */
1006 RTSEMEVENT hEventMoreRxDescAvail;
1007
1008 /** TX: Context used for TCP segmentation packets. */
1009 E1KTXCTX contextTSE;
1010 /** TX: Context used for ordinary packets. */
1011 E1KTXCTX contextNormal;
1012 /** GSO context. u8Type is set to PDMNETWORKGSOTYPE_INVALID when not
1013 * applicable to the current TSE mode. */
1014 PDMNETWORKGSO GsoCtx;
1015 /** Scratch space for holding the loopback / fallback scatter / gather
1016 * descriptor. */
1017 union
1018 {
1019 PDMSCATTERGATHER Sg;
1020 uint8_t padding[8 * sizeof(RTUINTPTR)];
1021 } uTxFallback;
1022 /** TX: Transmit packet buffer use for TSE fallback and loopback. */
1023 uint8_t aTxPacketFallback[E1K_MAX_TX_PKT_SIZE];
1024 /** TX: Number of bytes assembled in TX packet buffer. */
1025 uint16_t u16TxPktLen;
1026 /** TX: IP checksum has to be inserted if true. */
1027 bool fIPcsum;
1028 /** TX: TCP/UDP checksum has to be inserted if true. */
1029 bool fTCPcsum;
1030 /** TX TSE fallback: Number of payload bytes remaining in TSE context. */
1031 uint32_t u32PayRemain;
1032 /** TX TSE fallback: Number of header bytes remaining in TSE context. */
1033 uint16_t u16HdrRemain;
1034 /** TX TSE fallback: Flags from template header. */
1035 uint16_t u16SavedFlags;
1036 /** TX TSE fallback: Partial checksum from template header. */
1037 uint32_t u32SavedCsum;
1038 /** ?: Emulated controller type. */
1039 E1KCHIP eChip;
1040 uint32_t alignmentFix;
1041
1042 /** EMT: EEPROM emulation */
1043 E1kEEPROM eeprom;
1044 /** EMT: Physical interface emulation. */
1045 PHY phy;
1046
1047#if 0
1048 /** Alignment padding. */
1049 uint8_t Alignment[HC_ARCH_BITS == 64 ? 8 : 4];
1050#endif
1051
1052 STAMCOUNTER StatReceiveBytes;
1053 STAMCOUNTER StatTransmitBytes;
1054#if defined(VBOX_WITH_STATISTICS) || defined(E1K_REL_STATS)
1055 STAMPROFILEADV StatMMIOReadRZ;
1056 STAMPROFILEADV StatMMIOReadR3;
1057 STAMPROFILEADV StatMMIOWriteRZ;
1058 STAMPROFILEADV StatMMIOWriteR3;
1059 STAMPROFILEADV StatEEPROMRead;
1060 STAMPROFILEADV StatEEPROMWrite;
1061 STAMPROFILEADV StatIOReadRZ;
1062 STAMPROFILEADV StatIOReadR3;
1063 STAMPROFILEADV StatIOWriteRZ;
1064 STAMPROFILEADV StatIOWriteR3;
1065 STAMPROFILEADV StatLateIntTimer;
1066 STAMCOUNTER StatLateInts;
1067 STAMCOUNTER StatIntsRaised;
1068 STAMCOUNTER StatIntsPrevented;
1069 STAMPROFILEADV StatReceive;
1070 STAMPROFILEADV StatReceiveFilter;
1071 STAMPROFILEADV StatReceiveStore;
1072 STAMPROFILEADV StatTransmitRZ;
1073 STAMPROFILEADV StatTransmitR3;
1074 STAMPROFILE StatTransmitSendRZ;
1075 STAMPROFILE StatTransmitSendR3;
1076 STAMPROFILE StatRxOverflow;
1077 STAMCOUNTER StatRxOverflowWakeup;
1078 STAMCOUNTER StatTxDescCtxNormal;
1079 STAMCOUNTER StatTxDescCtxTSE;
1080 STAMCOUNTER StatTxDescLegacy;
1081 STAMCOUNTER StatTxDescData;
1082 STAMCOUNTER StatTxDescTSEData;
1083 STAMCOUNTER StatTxPathFallback;
1084 STAMCOUNTER StatTxPathGSO;
1085 STAMCOUNTER StatTxPathRegular;
1086 STAMCOUNTER StatPHYAccesses;
1087
1088#endif /* VBOX_WITH_STATISTICS || E1K_REL_STATS */
1089
1090#ifdef E1K_INT_STATS
1091 /* Internal stats */
1092 uint32_t uStatInt;
1093 uint32_t uStatIntTry;
1094 int32_t uStatIntLower;
1095 uint32_t uStatIntDly;
1096 int32_t iStatIntLost;
1097 int32_t iStatIntLostOne;
1098 uint32_t uStatDisDly;
1099 uint32_t uStatIntSkip;
1100 uint32_t uStatIntLate;
1101 uint32_t uStatIntMasked;
1102 uint32_t uStatIntEarly;
1103 uint32_t uStatIntRx;
1104 uint32_t uStatIntTx;
1105 uint32_t uStatIntICS;
1106 uint32_t uStatIntRDTR;
1107 uint32_t uStatIntRXDMT0;
1108 uint32_t uStatIntTXQE;
1109 uint32_t uStatTxNoRS;
1110 uint32_t uStatTxIDE;
1111 uint32_t uStatTAD;
1112 uint32_t uStatTID;
1113 uint32_t uStatRAD;
1114 uint32_t uStatRID;
1115 uint32_t uStatRxFrm;
1116 uint32_t uStatTxFrm;
1117 uint32_t uStatDescCtx;
1118 uint32_t uStatDescDat;
1119 uint32_t uStatDescLeg;
1120#endif /* E1K_INT_STATS */
1121};
1122typedef struct E1kState_st E1KSTATE;
1123
1124#ifndef VBOX_DEVICE_STRUCT_TESTCASE
1125
1126/* Forward declarations ******************************************************/
1127RT_C_DECLS_BEGIN
1128PDMBOTHCBDECL(int) e1kMMIORead (PPDMDEVINS pDevIns, void *pvUser, RTGCPHYS GCPhysAddr, void *pv, unsigned cb);
1129PDMBOTHCBDECL(int) e1kMMIOWrite(PPDMDEVINS pDevIns, void *pvUser, RTGCPHYS GCPhysAddr, void *pv, unsigned cb);
1130PDMBOTHCBDECL(int) e1kIOPortIn (PPDMDEVINS pDevIns, void *pvUser, RTIOPORT port, uint32_t *pu32, unsigned cb);
1131PDMBOTHCBDECL(int) e1kIOPortOut(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT port, uint32_t u32, unsigned cb);
1132RT_C_DECLS_END
1133
1134static int e1kXmitPending(E1KSTATE *pState, bool fOnWorkerThread);
1135
1136static int e1kRegReadUnimplemented (E1KSTATE* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value);
1137static int e1kRegWriteUnimplemented(E1KSTATE* pState, uint32_t offset, uint32_t index, uint32_t u32Value);
1138static int e1kRegReadAutoClear (E1KSTATE* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value);
1139static int e1kRegReadDefault (E1KSTATE* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value);
1140static int e1kRegWriteDefault (E1KSTATE* pState, uint32_t offset, uint32_t index, uint32_t u32Value);
1141#if 0 /* unused */
1142static int e1kRegReadCTRL (E1KSTATE* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value);
1143#endif
1144static int e1kRegWriteCTRL (E1KSTATE* pState, uint32_t offset, uint32_t index, uint32_t u32Value);
1145static int e1kRegReadEECD (E1KSTATE* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value);
1146static int e1kRegWriteEECD (E1KSTATE* pState, uint32_t offset, uint32_t index, uint32_t u32Value);
1147static int e1kRegWriteEERD (E1KSTATE* pState, uint32_t offset, uint32_t index, uint32_t u32Value);
1148static int e1kRegWriteMDIC (E1KSTATE* pState, uint32_t offset, uint32_t index, uint32_t u32Value);
1149static int e1kRegReadICR (E1KSTATE* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value);
1150static int e1kRegWriteICR (E1KSTATE* pState, uint32_t offset, uint32_t index, uint32_t u32Value);
1151static int e1kRegWriteICS (E1KSTATE* pState, uint32_t offset, uint32_t index, uint32_t u32Value);
1152static int e1kRegWriteIMS (E1KSTATE* pState, uint32_t offset, uint32_t index, uint32_t u32Value);
1153static int e1kRegWriteIMC (E1KSTATE* pState, uint32_t offset, uint32_t index, uint32_t u32Value);
1154static int e1kRegWriteRCTL (E1KSTATE* pState, uint32_t offset, uint32_t index, uint32_t u32Value);
1155static int e1kRegWritePBA (E1KSTATE* pState, uint32_t offset, uint32_t index, uint32_t u32Value);
1156static int e1kRegWriteRDT (E1KSTATE* pState, uint32_t offset, uint32_t index, uint32_t u32Value);
1157static int e1kRegWriteRDTR (E1KSTATE* pState, uint32_t offset, uint32_t index, uint32_t u32Value);
1158static int e1kRegWriteTDT (E1KSTATE* pState, uint32_t offset, uint32_t index, uint32_t u32Value);
1159static int e1kRegReadMTA (E1KSTATE* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value);
1160static int e1kRegWriteMTA (E1KSTATE* pState, uint32_t offset, uint32_t index, uint32_t u32Value);
1161static int e1kRegReadRA (E1KSTATE* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value);
1162static int e1kRegWriteRA (E1KSTATE* pState, uint32_t offset, uint32_t index, uint32_t u32Value);
1163static int e1kRegReadVFTA (E1KSTATE* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value);
1164static int e1kRegWriteVFTA (E1KSTATE* pState, uint32_t offset, uint32_t index, uint32_t u32Value);
1165
1166/**
1167 * Register map table.
1168 *
1169 * Override fn_read and fn_write to get register-specific behavior.
1170 */
1171const static struct E1kRegMap_st
1172{
1173 /** Register offset in the register space. */
1174 uint32_t offset;
1175 /** Size in bytes. Registers of size > 4 are in fact tables. */
1176 uint32_t size;
1177 /** Readable bits. */
1178 uint32_t readable;
1179 /** Writable bits. */
1180 uint32_t writable;
1181 /** Read callback. */
1182 int (*pfnRead)(E1KSTATE* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value);
1183 /** Write callback. */
1184 int (*pfnWrite)(E1KSTATE* pState, uint32_t offset, uint32_t index, uint32_t u32Value);
1185 /** Abbreviated name. */
1186 const char *abbrev;
1187 /** Full name. */
1188 const char *name;
1189} s_e1kRegMap[E1K_NUM_OF_REGS] =
1190{
1191 /* offset size read mask write mask read callback write callback abbrev full name */
1192 /*------- ------- ---------- ---------- ----------------------- ------------------------ ---------- ------------------------------*/
1193 { 0x00000, 0x00004, 0xDBF31BE9, 0xDBF31BE9, e1kRegReadDefault , e1kRegWriteCTRL , "CTRL" , "Device Control" },
1194 { 0x00008, 0x00004, 0x0000FDFF, 0x00000000, e1kRegReadDefault , e1kRegWriteUnimplemented, "STATUS" , "Device Status" },
1195 { 0x00010, 0x00004, 0x000027F0, 0x00000070, e1kRegReadEECD , e1kRegWriteEECD , "EECD" , "EEPROM/Flash Control/Data" },
1196 { 0x00014, 0x00004, 0xFFFFFF10, 0xFFFFFF00, e1kRegReadDefault , e1kRegWriteEERD , "EERD" , "EEPROM Read" },
1197 { 0x00018, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "CTRL_EXT", "Extended Device Control" },
1198 { 0x0001c, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "FLA" , "Flash Access (N/A)" },
1199 { 0x00020, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadDefault , e1kRegWriteMDIC , "MDIC" , "MDI Control" },
1200 { 0x00028, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "FCAL" , "Flow Control Address Low" },
1201 { 0x0002c, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "FCAH" , "Flow Control Address High" },
1202 { 0x00030, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "FCT" , "Flow Control Type" },
1203 { 0x00038, 0x00004, 0x0000FFFF, 0x0000FFFF, e1kRegReadDefault , e1kRegWriteDefault , "VET" , "VLAN EtherType" },
1204 { 0x000c0, 0x00004, 0x0001F6DF, 0x0001F6DF, e1kRegReadICR , e1kRegWriteICR , "ICR" , "Interrupt Cause Read" },
1205 { 0x000c4, 0x00004, 0x0000FFFF, 0x0000FFFF, e1kRegReadDefault , e1kRegWriteDefault , "ITR" , "Interrupt Throttling" },
1206 { 0x000c8, 0x00004, 0x00000000, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteICS , "ICS" , "Interrupt Cause Set" },
1207 { 0x000d0, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadDefault , e1kRegWriteIMS , "IMS" , "Interrupt Mask Set/Read" },
1208 { 0x000d8, 0x00004, 0x00000000, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteIMC , "IMC" , "Interrupt Mask Clear" },
1209 { 0x00100, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadDefault , e1kRegWriteRCTL , "RCTL" , "Receive Control" },
1210 { 0x00170, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "FCTTV" , "Flow Control Transmit Timer Value" },
1211 { 0x00178, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "TXCW" , "Transmit Configuration Word (N/A)" },
1212 { 0x00180, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "RXCW" , "Receive Configuration Word (N/A)" },
1213 { 0x00400, 0x00004, 0x017FFFFA, 0x017FFFFA, e1kRegReadDefault , e1kRegWriteDefault , "TCTL" , "Transmit Control" },
1214 { 0x00410, 0x00004, 0x3FFFFFFF, 0x3FFFFFFF, e1kRegReadDefault , e1kRegWriteDefault , "TIPG" , "Transmit IPG" },
1215 { 0x00458, 0x00004, 0x0000FFFF, 0x0000FFFF, e1kRegReadDefault , e1kRegWriteDefault , "AIFS" , "Adaptive IFS Throttle - AIT" },
1216 { 0x00e00, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "LEDCTL" , "LED Control" },
1217 { 0x01000, 0x00004, 0xFFFF007F, 0x0000007F, e1kRegReadDefault , e1kRegWritePBA , "PBA" , "Packet Buffer Allocation" },
1218 { 0x02160, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "FCRTL" , "Flow Control Receive Threshold Low" },
1219 { 0x02168, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "FCRTH" , "Flow Control Receive Threshold High" },
1220 { 0x02410, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "RDFH" , "Receive Data FIFO Head" },
1221 { 0x02418, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "RDFT" , "Receive Data FIFO Tail" },
1222 { 0x02420, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "RDFHS" , "Receive Data FIFO Head Saved Register" },
1223 { 0x02428, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "RDFTS" , "Receive Data FIFO Tail Saved Register" },
1224 { 0x02430, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "RDFPC" , "Receive Data FIFO Packet Count" },
1225 { 0x02800, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadDefault , e1kRegWriteDefault , "RDBAL" , "Receive Descriptor Base Low" },
1226 { 0x02804, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadDefault , e1kRegWriteDefault , "RDBAH" , "Receive Descriptor Base High" },
1227 { 0x02808, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadDefault , e1kRegWriteDefault , "RDLEN" , "Receive Descriptor Length" },
1228 { 0x02810, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadDefault , e1kRegWriteDefault , "RDH" , "Receive Descriptor Head" },
1229 { 0x02818, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadDefault , e1kRegWriteRDT , "RDT" , "Receive Descriptor Tail" },
1230 { 0x02820, 0x00004, 0x0000FFFF, 0x0000FFFF, e1kRegReadDefault , e1kRegWriteRDTR , "RDTR" , "Receive Delay Timer" },
1231 { 0x02828, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "RXDCTL" , "Receive Descriptor Control" },
1232 { 0x0282c, 0x00004, 0x0000FFFF, 0x0000FFFF, e1kRegReadDefault , e1kRegWriteDefault , "RADV" , "Receive Interrupt Absolute Delay Timer" },
1233 { 0x02c00, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "RSRPD" , "Receive Small Packet Detect Interrupt" },
1234 { 0x03000, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "TXDMAC" , "TX DMA Control (N/A)" },
1235 { 0x03410, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "TDFH" , "Transmit Data FIFO Head" },
1236 { 0x03418, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "TDFT" , "Transmit Data FIFO Tail" },
1237 { 0x03420, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "TDFHS" , "Transmit Data FIFO Head Saved Register" },
1238 { 0x03428, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "TDFTS" , "Transmit Data FIFO Tail Saved Register" },
1239 { 0x03430, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "TDFPC" , "Transmit Data FIFO Packet Count" },
1240 { 0x03800, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadDefault , e1kRegWriteDefault , "TDBAL" , "Transmit Descriptor Base Low" },
1241 { 0x03804, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadDefault , e1kRegWriteDefault , "TDBAH" , "Transmit Descriptor Base High" },
1242 { 0x03808, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadDefault , e1kRegWriteDefault , "TDLEN" , "Transmit Descriptor Length" },
1243 { 0x03810, 0x00004, 0x0000FFFF, 0x0000FFFF, e1kRegReadDefault , e1kRegWriteDefault , "TDH" , "Transmit Descriptor Head" },
1244 { 0x03818, 0x00004, 0x0000FFFF, 0x0000FFFF, e1kRegReadDefault , e1kRegWriteTDT , "TDT" , "Transmit Descriptor Tail" },
1245 { 0x03820, 0x00004, 0x0000FFFF, 0x0000FFFF, e1kRegReadDefault , e1kRegWriteDefault , "TIDV" , "Transmit Interrupt Delay Value" },
1246 { 0x03828, 0x00004, 0xFF3F3F3F, 0xFF3F3F3F, e1kRegReadDefault , e1kRegWriteDefault , "TXDCTL" , "Transmit Descriptor Control" },
1247 { 0x0382c, 0x00004, 0x0000FFFF, 0x0000FFFF, e1kRegReadDefault , e1kRegWriteDefault , "TADV" , "Transmit Absolute Interrupt Delay Timer" },
1248 { 0x03830, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadDefault , e1kRegWriteDefault , "TSPMT" , "TCP Segmentation Pad and Threshold" },
1249 { 0x04000, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "CRCERRS" , "CRC Error Count" },
1250 { 0x04004, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "ALGNERRC", "Alignment Error Count" },
1251 { 0x04008, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "SYMERRS" , "Symbol Error Count" },
1252 { 0x0400c, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "RXERRC" , "RX Error Count" },
1253 { 0x04010, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "MPC" , "Missed Packets Count" },
1254 { 0x04014, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "SCC" , "Single Collision Count" },
1255 { 0x04018, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "ECOL" , "Excessive Collisions Count" },
1256 { 0x0401c, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "MCC" , "Multiple Collision Count" },
1257 { 0x04020, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "LATECOL" , "Late Collisions Count" },
1258 { 0x04028, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "COLC" , "Collision Count" },
1259 { 0x04030, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "DC" , "Defer Count" },
1260 { 0x04034, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "TNCRS" , "Transmit - No CRS" },
1261 { 0x04038, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "SEC" , "Sequence Error Count" },
1262 { 0x0403c, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "CEXTERR" , "Carrier Extension Error Count" },
1263 { 0x04040, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "RLEC" , "Receive Length Error Count" },
1264 { 0x04048, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "XONRXC" , "XON Received Count" },
1265 { 0x0404c, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "XONTXC" , "XON Transmitted Count" },
1266 { 0x04050, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "XOFFRXC" , "XOFF Received Count" },
1267 { 0x04054, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "XOFFTXC" , "XOFF Transmitted Count" },
1268 { 0x04058, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "FCRUC" , "FC Received Unsupported Count" },
1269 { 0x0405c, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "PRC64" , "Packets Received (64 Bytes) Count" },
1270 { 0x04060, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "PRC127" , "Packets Received (65-127 Bytes) Count" },
1271 { 0x04064, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "PRC255" , "Packets Received (128-255 Bytes) Count" },
1272 { 0x04068, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "PRC511" , "Packets Received (256-511 Bytes) Count" },
1273 { 0x0406c, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "PRC1023" , "Packets Received (512-1023 Bytes) Count" },
1274 { 0x04070, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "PRC1522" , "Packets Received (1024-Max Bytes)" },
1275 { 0x04074, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "GPRC" , "Good Packets Received Count" },
1276 { 0x04078, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "BPRC" , "Broadcast Packets Received Count" },
1277 { 0x0407c, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "MPRC" , "Multicast Packets Received Count" },
1278 { 0x04080, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "GPTC" , "Good Packets Transmitted Count" },
1279 { 0x04088, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "GORCL" , "Good Octets Received Count (Low)" },
1280 { 0x0408c, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "GORCH" , "Good Octets Received Count (Hi)" },
1281 { 0x04090, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "GOTCL" , "Good Octets Transmitted Count (Low)" },
1282 { 0x04094, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "GOTCH" , "Good Octets Transmitted Count (Hi)" },
1283 { 0x040a0, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "RNBC" , "Receive No Buffers Count" },
1284 { 0x040a4, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "RUC" , "Receive Undersize Count" },
1285 { 0x040a8, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "RFC" , "Receive Fragment Count" },
1286 { 0x040ac, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "ROC" , "Receive Oversize Count" },
1287 { 0x040b0, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "RJC" , "Receive Jabber Count" },
1288 { 0x040b4, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "MGTPRC" , "Management Packets Received Count" },
1289 { 0x040b8, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "MGTPDC" , "Management Packets Dropped Count" },
1290 { 0x040bc, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "MGTPTC" , "Management Pkts Transmitted Count" },
1291 { 0x040c0, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "TORL" , "Total Octets Received (Lo)" },
1292 { 0x040c4, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "TORH" , "Total Octets Received (Hi)" },
1293 { 0x040c8, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "TOTL" , "Total Octets Transmitted (Lo)" },
1294 { 0x040cc, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "TOTH" , "Total Octets Transmitted (Hi)" },
1295 { 0x040d0, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "TPR" , "Total Packets Received" },
1296 { 0x040d4, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "TPT" , "Total Packets Transmitted" },
1297 { 0x040d8, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "PTC64" , "Packets Transmitted (64 Bytes) Count" },
1298 { 0x040dc, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "PTC127" , "Packets Transmitted (65-127 Bytes) Count" },
1299 { 0x040e0, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "PTC255" , "Packets Transmitted (128-255 Bytes) Count" },
1300 { 0x040e4, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "PTC511" , "Packets Transmitted (256-511 Bytes) Count" },
1301 { 0x040e8, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "PTC1023" , "Packets Transmitted (512-1023 Bytes) Count" },
1302 { 0x040ec, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "PTC1522" , "Packets Transmitted (1024 Bytes or Greater) Count" },
1303 { 0x040f0, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "MPTC" , "Multicast Packets Transmitted Count" },
1304 { 0x040f4, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "BPTC" , "Broadcast Packets Transmitted Count" },
1305 { 0x040f8, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "TSCTC" , "TCP Segmentation Context Transmitted Count" },
1306 { 0x040fc, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "TSCTFC" , "TCP Segmentation Context Tx Fail Count" },
1307 { 0x05000, 0x00004, 0x000007FF, 0x000007FF, e1kRegReadDefault , e1kRegWriteDefault , "RXCSUM" , "Receive Checksum Control" },
1308 { 0x05800, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "WUC" , "Wakeup Control" },
1309 { 0x05808, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "WUFC" , "Wakeup Filter Control" },
1310 { 0x05810, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "WUS" , "Wakeup Status" },
1311 { 0x05820, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadDefault , e1kRegWriteDefault , "MANC" , "Management Control" },
1312 { 0x05838, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "IPAV" , "IP Address Valid" },
1313 { 0x05900, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "WUPL" , "Wakeup Packet Length" },
1314 { 0x05200, 0x00200, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadMTA , e1kRegWriteMTA , "MTA" , "Multicast Table Array (n)" },
1315 { 0x05400, 0x00080, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadRA , e1kRegWriteRA , "RA" , "Receive Address (64-bit) (n)" },
1316 { 0x05600, 0x00200, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadVFTA , e1kRegWriteVFTA , "VFTA" , "VLAN Filter Table Array (n)" },
1317 { 0x05840, 0x0001c, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "IP4AT" , "IPv4 Address Table" },
1318 { 0x05880, 0x00010, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "IP6AT" , "IPv6 Address Table" },
1319 { 0x05a00, 0x00080, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "WUPM" , "Wakeup Packet Memory" },
1320 { 0x05f00, 0x0001c, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "FFLT" , "Flexible Filter Length Table" },
1321 { 0x09000, 0x003fc, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "FFMT" , "Flexible Filter Mask Table" },
1322 { 0x09800, 0x003fc, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "FFVT" , "Flexible Filter Value Table" },
1323 { 0x10000, 0x10000, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "PBM" , "Packet Buffer Memory (n)" },
1324 { 0x00040, 0x00080, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadRA , e1kRegWriteRA , "RA" , "Receive Address (64-bit) (n) (82542)" },
1325 { 0x00200, 0x00200, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadMTA , e1kRegWriteMTA , "MTA" , "Multicast Table Array (n) (82542)" },
1326 { 0x00600, 0x00200, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadVFTA , e1kRegWriteVFTA , "VFTA" , "VLAN Filter Table Array (n) (82542)" }
1327};
1328
1329#ifdef DEBUG
1330
1331/**
1332 * Convert U32 value to hex string. Masked bytes are replaced with dots.
1333 *
1334 * @remarks The mask has byte (not bit) granularity (e.g. 000000FF).
1335 *
1336 * @returns The buffer.
1337 *
1338 * @param u32 The word to convert into string.
1339 * @param mask Selects which bytes to convert.
1340 * @param buf Where to put the result.
1341 */
1342static char *e1kU32toHex(uint32_t u32, uint32_t mask, char *buf)
1343{
1344 for (char *ptr = buf + 7; ptr >= buf; --ptr, u32 >>=4, mask >>=4)
1345 {
1346 if (mask & 0xF)
1347 *ptr = (u32 & 0xF) + ((u32 & 0xF) > 9 ? '7' : '0');
1348 else
1349 *ptr = '.';
1350 }
1351 buf[8] = 0;
1352 return buf;
1353}
1354
1355/**
1356 * Returns timer name for debug purposes.
1357 *
1358 * @returns The timer name.
1359 *
1360 * @param pState The device state structure.
1361 * @param pTimer The timer to get the name for.
1362 */
1363DECLINLINE(const char *) e1kGetTimerName(E1KSTATE *pState, PTMTIMER pTimer)
1364{
1365 if (pTimer == pState->CTX_SUFF(pTIDTimer))
1366 return "TID";
1367 if (pTimer == pState->CTX_SUFF(pTADTimer))
1368 return "TAD";
1369 if (pTimer == pState->CTX_SUFF(pRIDTimer))
1370 return "RID";
1371 if (pTimer == pState->CTX_SUFF(pRADTimer))
1372 return "RAD";
1373 if (pTimer == pState->CTX_SUFF(pIntTimer))
1374 return "Int";
1375 return "unknown";
1376}
1377
1378#endif /* DEBUG */
1379
1380/**
1381 * Arm a timer.
1382 *
1383 * @param pState Pointer to the device state structure.
1384 * @param pTimer Pointer to the timer.
1385 * @param uExpireIn Expiration interval in microseconds.
1386 */
1387DECLINLINE(void) e1kArmTimer(E1KSTATE *pState, PTMTIMER pTimer, uint32_t uExpireIn)
1388{
1389 if (pState->fLocked)
1390 return;
1391
1392 E1kLog2(("%s Arming %s timer to fire in %d usec...\n",
1393 INSTANCE(pState), e1kGetTimerName(pState, pTimer), uExpireIn));
1394 TMTimerSet(pTimer, TMTimerFromMicro(pTimer, uExpireIn) +
1395 TMTimerGet(pTimer));
1396}
1397
1398/**
1399 * Cancel a timer.
1400 *
1401 * @param pState Pointer to the device state structure.
1402 * @param pTimer Pointer to the timer.
1403 */
1404DECLINLINE(void) e1kCancelTimer(E1KSTATE *pState, PTMTIMER pTimer)
1405{
1406 E1kLog2(("%s Stopping %s timer...\n",
1407 INSTANCE(pState), e1kGetTimerName(pState, pTimer)));
1408 int rc = TMTimerStop(pTimer);
1409 if (RT_FAILURE(rc))
1410 {
1411 E1kLog2(("%s e1kCancelTimer: TMTimerStop() failed with %Rrc\n",
1412 INSTANCE(pState), rc));
1413 }
1414}
1415
1416#ifdef E1K_GLOBAL_MUTEX
1417DECLINLINE(int) e1kCsEnter(E1KSTATE *pState, int iBusyRc)
1418{
1419 return VINF_SUCCESS;
1420}
1421
1422DECLINLINE(void) e1kCsLeave(E1KSTATE *pState)
1423{
1424}
1425
1426#define e1kCsRxEnter(ps, rc) VINF_SUCCESS
1427#define e1kCsRxLeave(ps) do { } while (0)
1428
1429#define e1kCsTxEnter(ps, rc) VINF_SUCCESS
1430#define e1kCsTxLeave(ps) do { } while (0)
1431
1432
1433DECLINLINE(int) e1kMutexAcquire(E1KSTATE *pState, int iBusyRc, RT_SRC_POS_DECL)
1434{
1435 int rc = PDMCritSectEnter(&pState->cs, iBusyRc);
1436 if (RT_UNLIKELY(rc != VINF_SUCCESS))
1437 {
1438 E1kLog2(("%s ==> FAILED to enter critical section at %s:%d:%s with rc=\n",
1439 INSTANCE(pState), RT_SRC_POS_ARGS, rc));
1440 PDMDevHlpDBGFStop(pState->CTX_SUFF(pDevIns), RT_SRC_POS_ARGS,
1441 "%s Failed to enter critical section, rc=%Rrc\n",
1442 INSTANCE(pState), rc);
1443 }
1444 else
1445 {
1446 //E1kLog2(("%s ==> Mutex acquired at %s:%d:%s\n", INSTANCE(pState), RT_SRC_POS_ARGS));
1447 }
1448 return rc;
1449}
1450
1451DECLINLINE(void) e1kMutexRelease(E1KSTATE *pState)
1452{
1453 //E1kLog2(("%s <== Releasing mutex...\n", INSTANCE(pState)));
1454 PDMCritSectLeave(&pState->cs);
1455}
1456
1457#else /* !E1K_GLOBAL_MUTEX */
1458#define e1kCsEnter(ps, rc) PDMCritSectEnter(&ps->cs, rc)
1459#define e1kCsLeave(ps) PDMCritSectLeave(&ps->cs)
1460
1461#define e1kCsRxEnter(ps, rc) PDMCritSectEnter(&ps->csRx, rc)
1462#define e1kCsRxLeave(ps) PDMCritSectLeave(&ps->csRx)
1463
1464#define e1kCsTxEnter(ps, rc) VINF_SUCCESS
1465#define e1kCsTxLeave(ps) do { } while (0)
1466//#define e1kCsTxEnter(ps, rc) PDMCritSectEnter(&ps->csTx, rc)
1467//#define e1kCsTxLeave(ps) PDMCritSectLeave(&ps->csTx)
1468
1469#if 0
1470DECLINLINE(int) e1kCsEnter(E1KSTATE *pState, PPDMCRITSECT pCs, int iBusyRc, RT_SRC_POS_DECL)
1471{
1472 int rc = PDMCritSectEnter(pCs, iBusyRc);
1473 if (RT_FAILURE(rc))
1474 {
1475 E1kLog2(("%s ==> FAILED to enter critical section at %s:%d:%s with rc=%Rrc\n",
1476 INSTANCE(pState), RT_SRC_POS_ARGS, rc));
1477 PDMDeviceDBGFStop(pState->CTX_SUFF(pDevIns), RT_SRC_POS_ARGS,
1478 "%s Failed to enter critical section, rc=%Rrc\n",
1479 INSTANCE(pState), rc);
1480 }
1481 else
1482 {
1483 //E1kLog2(("%s ==> Entered critical section at %s:%d:%s\n", INSTANCE(pState), RT_SRC_POS_ARGS));
1484 }
1485 return RT_SUCCESS(rc);
1486}
1487
1488DECLINLINE(void) e1kCsLeave(E1KSTATE *pState, PPDMCRITSECT pCs)
1489{
1490 //E1kLog2(("%s <== Leaving critical section\n", INSTANCE(pState)));
1491 PDMCritSectLeave(&pState->cs);
1492}
1493#endif
1494DECLINLINE(int) e1kMutexAcquire(E1KSTATE *pState, int iBusyRc, RT_SRC_POS_DECL)
1495{
1496 return VINF_SUCCESS;
1497}
1498
1499DECLINLINE(void) e1kMutexRelease(E1KSTATE *pState)
1500{
1501}
1502#endif /* !E1K_GLOBAL_MUTEX */
1503
1504#ifdef IN_RING3
1505/**
1506 * Wakeup the RX thread.
1507 */
1508static void e1kWakeupReceive(PPDMDEVINS pDevIns)
1509{
1510 E1KSTATE *pState = PDMINS_2_DATA(pDevIns, E1KSTATE *);
1511 if ( pState->fMaybeOutOfSpace
1512 && pState->hEventMoreRxDescAvail != NIL_RTSEMEVENT)
1513 {
1514 STAM_COUNTER_INC(&pState->StatRxOverflowWakeup);
1515 E1kLog(("%s Waking up Out-of-RX-space semaphore\n", INSTANCE(pState)));
1516 RTSemEventSignal(pState->hEventMoreRxDescAvail);
1517 }
1518}
1519
1520/**
1521 * Hardware reset. Revert all registers to initial values.
1522 *
1523 * @param pState The device state structure.
1524 */
1525PDMBOTHCBDECL(void) e1kHardReset(E1KSTATE *pState)
1526{
1527 E1kLog(("%s Hard reset triggered\n", INSTANCE(pState)));
1528 memset(pState->auRegs, 0, sizeof(pState->auRegs));
1529 memset(pState->aRecAddr.au32, 0, sizeof(pState->aRecAddr.au32));
1530#ifdef E1K_INIT_RA0
1531 memcpy(pState->aRecAddr.au32, pState->macConfigured.au8,
1532 sizeof(pState->macConfigured.au8));
1533 pState->aRecAddr.array[0].ctl |= RA_CTL_AV;
1534#endif /* E1K_INIT_RA0 */
1535 STATUS = 0x0081; /* SPEED=10b (1000 Mb/s), FD=1b (Full Duplex) */
1536 EECD = 0x0100; /* EE_PRES=1b (EEPROM present) */
1537 CTRL = 0x0a09; /* FRCSPD=1b SPEED=10b LRST=1b FD=1b */
1538 TSPMT = 0x01000400;/* TSMT=0400h TSPBP=0100h */
1539 Assert(GET_BITS(RCTL, BSIZE) == 0);
1540 pState->u16RxBSize = 2048;
1541
1542 /* Reset promiscuous mode */
1543 if (pState->pDrvR3)
1544 pState->pDrvR3->pfnSetPromiscuousMode(pState->pDrvR3, false);
1545}
1546#endif
1547
1548/**
1549 * Compute Internet checksum.
1550 *
1551 * @remarks Refer to http://www.netfor2.com/checksum.html for short intro.
1552 *
1553 * @param pState The device state structure.
1554 * @param cpPacket The packet.
1555 * @param cb The size of the packet.
1556 * @param cszText A string denoting direction of packet transfer.
1557 *
1558 * @return The 1's complement of the 1's complement sum.
1559 *
1560 * @thread E1000_TX
1561 */
1562static uint16_t e1kCSum16(const void *pvBuf, size_t cb)
1563{
1564 uint32_t csum = 0;
1565 uint16_t *pu16 = (uint16_t *)pvBuf;
1566
1567 while (cb > 1)
1568 {
1569 csum += *pu16++;
1570 cb -= 2;
1571 }
1572 if (cb)
1573 csum += *(uint8_t*)pu16;
1574 while (csum >> 16)
1575 csum = (csum >> 16) + (csum & 0xFFFF);
1576 return ~csum;
1577}
1578
1579/**
1580 * Dump a packet to debug log.
1581 *
1582 * @param pState The device state structure.
1583 * @param cpPacket The packet.
1584 * @param cb The size of the packet.
1585 * @param cszText A string denoting direction of packet transfer.
1586 * @thread E1000_TX
1587 */
1588DECLINLINE(void) e1kPacketDump(E1KSTATE* pState, const uint8_t *cpPacket, size_t cb, const char *cszText)
1589{
1590#ifdef DEBUG
1591 if (RT_LIKELY(e1kCsEnter(pState, VERR_SEM_BUSY) == VINF_SUCCESS))
1592 {
1593 E1kLog(("%s --- %s packet #%d: ---\n",
1594 INSTANCE(pState), cszText, ++pState->u32PktNo));
1595 E1kLog3(("%.*Rhxd\n", cb, cpPacket));
1596 e1kCsLeave(pState);
1597 }
1598#else
1599 if (RT_LIKELY(e1kCsEnter(pState, VERR_SEM_BUSY) == VINF_SUCCESS))
1600 {
1601 E1kLogRel(("E1000: %s packet #%d, seq=%x ack=%x\n", cszText, pState->u32PktNo++, ntohl(*(uint32_t*)(cpPacket+0x26)), ntohl(*(uint32_t*)(cpPacket+0x2A))));
1602 e1kCsLeave(pState);
1603 }
1604#endif
1605}
1606
1607/**
1608 * Determine the type of transmit descriptor.
1609 *
1610 * @returns Descriptor type. See E1K_DTYP_XXX defines.
1611 *
1612 * @param pDesc Pointer to descriptor union.
1613 * @thread E1000_TX
1614 */
1615DECLINLINE(int) e1kGetDescType(E1KTXDESC* pDesc)
1616{
1617 if (pDesc->legacy.cmd.fDEXT)
1618 return pDesc->context.dw2.u4DTYP;
1619 return E1K_DTYP_LEGACY;
1620}
1621
1622/**
1623 * Dump receive descriptor to debug log.
1624 *
1625 * @param pState The device state structure.
1626 * @param pDesc Pointer to the descriptor.
1627 * @thread E1000_RX
1628 */
1629static void e1kPrintRDesc(E1KSTATE* pState, E1KRXDESC* pDesc)
1630{
1631 E1kLog2(("%s <-- Receive Descriptor (%d bytes):\n", INSTANCE(pState), pDesc->u16Length));
1632 E1kLog2((" Address=%16LX Length=%04X Csum=%04X\n",
1633 pDesc->u64BufAddr, pDesc->u16Length, pDesc->u16Checksum));
1634 E1kLog2((" STA: %s %s %s %s %s %s %s ERR: %s %s %s %s SPECIAL: %s VLAN=%03x PRI=%x\n",
1635 pDesc->status.fPIF ? "PIF" : "pif",
1636 pDesc->status.fIPCS ? "IPCS" : "ipcs",
1637 pDesc->status.fTCPCS ? "TCPCS" : "tcpcs",
1638 pDesc->status.fVP ? "VP" : "vp",
1639 pDesc->status.fIXSM ? "IXSM" : "ixsm",
1640 pDesc->status.fEOP ? "EOP" : "eop",
1641 pDesc->status.fDD ? "DD" : "dd",
1642 pDesc->status.fRXE ? "RXE" : "rxe",
1643 pDesc->status.fIPE ? "IPE" : "ipe",
1644 pDesc->status.fTCPE ? "TCPE" : "tcpe",
1645 pDesc->status.fCE ? "CE" : "ce",
1646 pDesc->status.fCFI ? "CFI" :"cfi",
1647 pDesc->status.u12VLAN,
1648 pDesc->status.u3PRI));
1649}
1650
1651/**
1652 * Dump transmit descriptor to debug log.
1653 *
1654 * @param pState The device state structure.
1655 * @param pDesc Pointer to descriptor union.
1656 * @param cszDir A string denoting direction of descriptor transfer
1657 * @thread E1000_TX
1658 */
1659static void e1kPrintTDesc(E1KSTATE* pState, E1KTXDESC* pDesc, const char* cszDir)
1660{
1661 switch (e1kGetDescType(pDesc))
1662 {
1663 case E1K_DTYP_CONTEXT:
1664 E1kLog2(("%s %s Context Transmit Descriptor %s\n",
1665 INSTANCE(pState), cszDir, cszDir));
1666 E1kLog2((" IPCSS=%02X IPCSO=%02X IPCSE=%04X TUCSS=%02X TUCSO=%02X TUCSE=%04X\n",
1667 pDesc->context.ip.u8CSS, pDesc->context.ip.u8CSO, pDesc->context.ip.u16CSE,
1668 pDesc->context.tu.u8CSS, pDesc->context.tu.u8CSO, pDesc->context.tu.u16CSE));
1669 E1kLog2((" TUCMD:%s%s%s %s %s PAYLEN=%04x HDRLEN=%04x MSS=%04x STA: %s\n",
1670 pDesc->context.dw2.fIDE ? " IDE":"",
1671 pDesc->context.dw2.fRS ? " RS" :"",
1672 pDesc->context.dw2.fTSE ? " TSE":"",
1673 pDesc->context.dw2.fIP ? "IPv4":"IPv6",
1674 pDesc->context.dw2.fTCP ? "TCP":"UDP",
1675 pDesc->context.dw2.u20PAYLEN,
1676 pDesc->context.dw3.u8HDRLEN,
1677 pDesc->context.dw3.u16MSS,
1678 pDesc->context.dw3.fDD?"DD":""));
1679 break;
1680 case E1K_DTYP_DATA:
1681 E1kLog2(("%s %s Data Transmit Descriptor (%d bytes) %s\n",
1682 INSTANCE(pState), cszDir, pDesc->data.cmd.u20DTALEN, cszDir));
1683 E1kLog2((" Address=%16LX DTALEN=%05X\n",
1684 pDesc->data.u64BufAddr,
1685 pDesc->data.cmd.u20DTALEN));
1686 E1kLog2((" DCMD:%s%s%s%s%s%s STA:%s%s%s POPTS:%s%s SPECIAL:%s VLAN=%03x PRI=%x\n",
1687 pDesc->data.cmd.fIDE ? " IDE" :"",
1688 pDesc->data.cmd.fVLE ? " VLE" :"",
1689 pDesc->data.cmd.fRS ? " RS" :"",
1690 pDesc->data.cmd.fTSE ? " TSE" :"",
1691 pDesc->data.cmd.fIFCS? " IFCS":"",
1692 pDesc->data.cmd.fEOP ? " EOP" :"",
1693 pDesc->data.dw3.fDD ? " DD" :"",
1694 pDesc->data.dw3.fEC ? " EC" :"",
1695 pDesc->data.dw3.fLC ? " LC" :"",
1696 pDesc->data.dw3.fTXSM? " TXSM":"",
1697 pDesc->data.dw3.fIXSM? " IXSM":"",
1698 pDesc->data.dw3.fCFI ? " CFI" :"",
1699 pDesc->data.dw3.u12VLAN,
1700 pDesc->data.dw3.u3PRI));
1701 break;
1702 case E1K_DTYP_LEGACY:
1703 E1kLog2(("%s %s Legacy Transmit Descriptor (%d bytes) %s\n",
1704 INSTANCE(pState), cszDir, pDesc->legacy.cmd.u16Length, cszDir));
1705 E1kLog2((" Address=%16LX DTALEN=%05X\n",
1706 pDesc->data.u64BufAddr,
1707 pDesc->legacy.cmd.u16Length));
1708 E1kLog2((" CMD:%s%s%s%s%s%s STA:%s%s%s CSO=%02x CSS=%02x SPECIAL:%s VLAN=%03x PRI=%x\n",
1709 pDesc->legacy.cmd.fIDE ? " IDE" :"",
1710 pDesc->legacy.cmd.fVLE ? " VLE" :"",
1711 pDesc->legacy.cmd.fRS ? " RS" :"",
1712 pDesc->legacy.cmd.fIC ? " IC" :"",
1713 pDesc->legacy.cmd.fIFCS? " IFCS":"",
1714 pDesc->legacy.cmd.fEOP ? " EOP" :"",
1715 pDesc->legacy.dw3.fDD ? " DD" :"",
1716 pDesc->legacy.dw3.fEC ? " EC" :"",
1717 pDesc->legacy.dw3.fLC ? " LC" :"",
1718 pDesc->legacy.cmd.u8CSO,
1719 pDesc->legacy.dw3.u8CSS,
1720 pDesc->legacy.dw3.fCFI ? " CFI" :"",
1721 pDesc->legacy.dw3.u12VLAN,
1722 pDesc->legacy.dw3.u3PRI));
1723 break;
1724 default:
1725 E1kLog(("%s %s Invalid Transmit Descriptor %s\n",
1726 INSTANCE(pState), cszDir, cszDir));
1727 break;
1728 }
1729}
1730
1731/**
1732 * Raise interrupt if not masked.
1733 *
1734 * @param pState The device state structure.
1735 */
1736PDMBOTHCBDECL(int) e1kRaiseInterrupt(E1KSTATE *pState, int rcBusy, uint32_t u32IntCause = 0)
1737{
1738 int rc = e1kCsEnter(pState, rcBusy);
1739 if (RT_UNLIKELY(rc != VINF_SUCCESS))
1740 return rc;
1741
1742 E1K_INC_ISTAT_CNT(pState->uStatIntTry);
1743 ICR |= u32IntCause;
1744 if (ICR & IMS)
1745 {
1746#if 0
1747 if (pState->fDelayInts)
1748 {
1749 E1K_INC_ISTAT_CNT(pState->uStatIntDly);
1750 pState->iStatIntLostOne = 1;
1751 E1kLog2(("%s e1kRaiseInterrupt: Delayed. ICR=%08x\n",
1752 INSTANCE(pState), ICR));
1753#define E1K_LOST_IRQ_THRSLD 20
1754//#define E1K_LOST_IRQ_THRSLD 200000000
1755 if (pState->iStatIntLost >= E1K_LOST_IRQ_THRSLD)
1756 {
1757 E1kLog2(("%s WARNING! Disabling delayed interrupt logic: delayed=%d, delivered=%d\n",
1758 INSTANCE(pState), pState->uStatIntDly, pState->uStatIntLate));
1759 pState->fIntMaskUsed = false;
1760 pState->uStatDisDly++;
1761 }
1762 }
1763 else
1764#endif
1765 if (pState->fIntRaised)
1766 {
1767 E1K_INC_ISTAT_CNT(pState->uStatIntSkip);
1768 E1kLog2(("%s e1kRaiseInterrupt: Already raised, skipped. ICR&IMS=%08x\n",
1769 INSTANCE(pState), ICR & IMS));
1770 }
1771 else
1772 {
1773#ifdef E1K_ITR_ENABLED
1774 uint64_t tstamp = TMTimerGet(pState->CTX_SUFF(pIntTimer));
1775 /* interrupts/sec = 1 / (256 * 10E-9 * ITR) */
1776 E1kLog2(("%s e1kRaiseInterrupt: tstamp - pState->u64AckedAt = %d, ITR * 256 = %d\n",
1777 INSTANCE(pState), (uint32_t)(tstamp - pState->u64AckedAt), ITR * 256));
1778 if (!!ITR && pState->fIntMaskUsed && tstamp - pState->u64AckedAt < ITR * 256)
1779 {
1780 E1K_INC_ISTAT_CNT(pState->uStatIntEarly);
1781 E1kLog2(("%s e1kRaiseInterrupt: Too early to raise again: %d ns < %d ns.\n",
1782 INSTANCE(pState), (uint32_t)(tstamp - pState->u64AckedAt), ITR * 256));
1783 }
1784 else
1785#endif
1786 {
1787
1788 /* Since we are delivering the interrupt now
1789 * there is no need to do it later -- stop the timer.
1790 */
1791 TMTimerStop(pState->CTX_SUFF(pIntTimer));
1792 E1K_INC_ISTAT_CNT(pState->uStatInt);
1793 STAM_COUNTER_INC(&pState->StatIntsRaised);
1794 /* Got at least one unmasked interrupt cause */
1795 pState->fIntRaised = true;
1796 /* Raise(1) INTA(0) */
1797 //e1kMutexRelease(pState);
1798 E1kLogRel(("E1000: irq RAISED icr&mask=0x%x, icr=0x%x\n", ICR & IMS, ICR));
1799 PDMDevHlpPCISetIrq(pState->CTX_SUFF(pDevIns), 0, 1);
1800 //e1kMutexAcquire(pState, RT_SRC_POS);
1801 E1kLog(("%s e1kRaiseInterrupt: Raised. ICR&IMS=%08x\n",
1802 INSTANCE(pState), ICR & IMS));
1803 }
1804 }
1805 }
1806 else
1807 {
1808 E1K_INC_ISTAT_CNT(pState->uStatIntMasked);
1809 E1kLog2(("%s e1kRaiseInterrupt: Not raising, ICR=%08x, IMS=%08x\n",
1810 INSTANCE(pState), ICR, IMS));
1811 }
1812 e1kCsLeave(pState);
1813 return VINF_SUCCESS;
1814}
1815
1816/**
1817 * Compute the physical address of the descriptor.
1818 *
1819 * @returns the physical address of the descriptor.
1820 *
1821 * @param baseHigh High-order 32 bits of descriptor table address.
1822 * @param baseLow Low-order 32 bits of descriptor table address.
1823 * @param idxDesc The descriptor index in the table.
1824 */
1825DECLINLINE(RTGCPHYS) e1kDescAddr(uint32_t baseHigh, uint32_t baseLow, uint32_t idxDesc)
1826{
1827 AssertCompile(sizeof(E1KRXDESC) == sizeof(E1KTXDESC));
1828 return ((uint64_t)baseHigh << 32) + baseLow + idxDesc * sizeof(E1KRXDESC);
1829}
1830
1831/**
1832 * Advance the head pointer of the receive descriptor queue.
1833 *
1834 * @remarks RDH always points to the next available RX descriptor.
1835 *
1836 * @param pState The device state structure.
1837 */
1838DECLINLINE(void) e1kAdvanceRDH(E1KSTATE *pState)
1839{
1840 //e1kCsEnter(pState, RT_SRC_POS);
1841 if (++RDH * sizeof(E1KRXDESC) >= RDLEN)
1842 RDH = 0;
1843 /*
1844 * Compute current receive queue length and fire RXDMT0 interrupt
1845 * if we are low on receive buffers
1846 */
1847 uint32_t uRQueueLen = RDH>RDT ? RDLEN/sizeof(E1KRXDESC)-RDH+RDT : RDT-RDH;
1848 /*
1849 * The minimum threshold is controlled by RDMTS bits of RCTL:
1850 * 00 = 1/2 of RDLEN
1851 * 01 = 1/4 of RDLEN
1852 * 10 = 1/8 of RDLEN
1853 * 11 = reserved
1854 */
1855 uint32_t uMinRQThreshold = RDLEN / sizeof(E1KRXDESC) / (2 << GET_BITS(RCTL, RDMTS));
1856 if (uRQueueLen <= uMinRQThreshold)
1857 {
1858 E1kLogRel(("E1000: low on RX descriptors, RDH=%x RDT=%x len=%x threshold=%x\n", RDH, RDT, uRQueueLen, uMinRQThreshold));
1859 E1kLog2(("%s Low on RX descriptors, RDH=%x RDT=%x len=%x threshold=%x, raise an interrupt\n",
1860 INSTANCE(pState), RDH, RDT, uRQueueLen, uMinRQThreshold));
1861 E1K_INC_ISTAT_CNT(pState->uStatIntRXDMT0);
1862 e1kRaiseInterrupt(pState, VERR_SEM_BUSY, ICR_RXDMT0);
1863 }
1864 //e1kCsLeave(pState);
1865}
1866
1867/**
1868 * Store a fragment of received packet that fits into the next available RX
1869 * buffer.
1870 *
1871 * @remarks Trigger the RXT0 interrupt if it is the last fragment of the packet.
1872 *
1873 * @param pState The device state structure.
1874 * @param pDesc The next available RX descriptor.
1875 * @param pvBuf The fragment.
1876 * @param cb The size of the fragment.
1877 */
1878static DECLCALLBACK(void) e1kStoreRxFragment(E1KSTATE *pState, E1KRXDESC *pDesc, const void *pvBuf, size_t cb)
1879{
1880 STAM_PROFILE_ADV_START(&pState->StatReceiveStore, a);
1881 E1kLog2(("%s e1kStoreRxFragment: store fragment of %04X at %016LX, EOP=%d\n", pState->szInstance, cb, pDesc->u64BufAddr, pDesc->status.fEOP));
1882 PDMDevHlpPhysWrite(pState->CTX_SUFF(pDevIns), pDesc->u64BufAddr, pvBuf, cb);
1883 pDesc->u16Length = (uint16_t)cb; Assert(pDesc->u16Length == cb);
1884 /* Write back the descriptor */
1885 PDMDevHlpPhysWrite(pState->CTX_SUFF(pDevIns), e1kDescAddr(RDBAH, RDBAL, RDH), pDesc, sizeof(E1KRXDESC));
1886 e1kPrintRDesc(pState, pDesc);
1887 E1kLogRel(("E1000: Wrote back RX desc, RDH=%x\n", RDH));
1888 /* Advance head */
1889 e1kAdvanceRDH(pState);
1890 //E1kLog2(("%s e1kStoreRxFragment: EOP=%d RDTR=%08X RADV=%08X\n", INSTANCE(pState), pDesc->fEOP, RDTR, RADV));
1891 if (pDesc->status.fEOP)
1892 {
1893 /* Complete packet has been stored -- it is time to let the guest know. */
1894#ifdef E1K_USE_RX_TIMERS
1895 if (RDTR)
1896 {
1897 /* Arm the timer to fire in RDTR usec (discard .024) */
1898 e1kArmTimer(pState, pState->CTX_SUFF(pRIDTimer), RDTR);
1899 /* If absolute timer delay is enabled and the timer is not running yet, arm it. */
1900 if (RADV != 0 && !TMTimerIsActive(pState->CTX_SUFF(pRADTimer)))
1901 e1kArmTimer(pState, pState->CTX_SUFF(pRADTimer), RADV);
1902 }
1903 else
1904 {
1905#endif
1906 /* 0 delay means immediate interrupt */
1907 E1K_INC_ISTAT_CNT(pState->uStatIntRx);
1908 e1kRaiseInterrupt(pState, VERR_SEM_BUSY, ICR_RXT0);
1909#ifdef E1K_USE_RX_TIMERS
1910 }
1911#endif
1912 }
1913 STAM_PROFILE_ADV_STOP(&pState->StatReceiveStore, a);
1914}
1915
1916/**
1917 * Returns true if it is a broadcast packet.
1918 *
1919 * @returns true if destination address indicates broadcast.
1920 * @param pvBuf The ethernet packet.
1921 */
1922DECLINLINE(bool) e1kIsBroadcast(const void *pvBuf)
1923{
1924 static const uint8_t s_abBcastAddr[] = { 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF };
1925 return memcmp(pvBuf, s_abBcastAddr, sizeof(s_abBcastAddr)) == 0;
1926}
1927
1928/**
1929 * Returns true if it is a multicast packet.
1930 *
1931 * @remarks returns true for broadcast packets as well.
1932 * @returns true if destination address indicates multicast.
1933 * @param pvBuf The ethernet packet.
1934 */
1935DECLINLINE(bool) e1kIsMulticast(const void *pvBuf)
1936{
1937 return (*(char*)pvBuf) & 1;
1938}
1939
1940/**
1941 * Set IXSM, IPCS and TCPCS flags according to the packet type.
1942 *
1943 * @remarks We emulate checksum offloading for major packets types only.
1944 *
1945 * @returns VBox status code.
1946 * @param pState The device state structure.
1947 * @param pFrame The available data.
1948 * @param cb Number of bytes available in the buffer.
1949 * @param status Bit fields containing status info.
1950 */
1951static int e1kRxChecksumOffload(E1KSTATE* pState, const uint8_t *pFrame, size_t cb, E1KRXDST *pStatus)
1952{
1953 /** @todo
1954 * It is not safe to bypass checksum verification for packets coming
1955 * from real wire. We currently unable to tell where packets are
1956 * coming from so we tell the driver to ignore our checksum flags
1957 * and do verification in software.
1958 */
1959#if 0
1960 uint16_t uEtherType = ntohs(*(uint16_t*)(pFrame + 12));
1961
1962 E1kLog2(("%s e1kRxChecksumOffload: EtherType=%x\n", INSTANCE(pState), uEtherType));
1963
1964 switch (uEtherType)
1965 {
1966 case 0x800: /* IPv4 */
1967 {
1968 pStatus->fIXSM = false;
1969 pStatus->fIPCS = true;
1970 PRTNETIPV4 pIpHdr4 = (PRTNETIPV4)(pFrame + 14);
1971 /* TCP/UDP checksum offloading works with TCP and UDP only */
1972 pStatus->fTCPCS = pIpHdr4->ip_p == 6 || pIpHdr4->ip_p == 17;
1973 break;
1974 }
1975 case 0x86DD: /* IPv6 */
1976 pStatus->fIXSM = false;
1977 pStatus->fIPCS = false;
1978 pStatus->fTCPCS = true;
1979 break;
1980 default: /* ARP, VLAN, etc. */
1981 pStatus->fIXSM = true;
1982 break;
1983 }
1984#else
1985 pStatus->fIXSM = true;
1986#endif
1987 return VINF_SUCCESS;
1988}
1989
1990/**
1991 * Pad and store received packet.
1992 *
1993 * @remarks Make sure that the packet appears to upper layer as one coming
1994 * from real Ethernet: pad it and insert FCS.
1995 *
1996 * @returns VBox status code.
1997 * @param pState The device state structure.
1998 * @param pvBuf The available data.
1999 * @param cb Number of bytes available in the buffer.
2000 * @param status Bit fields containing status info.
2001 */
2002static int e1kHandleRxPacket(E1KSTATE* pState, const void *pvBuf, size_t cb, E1KRXDST status)
2003{
2004#if defined(IN_RING3) /** @todo Remove this extra copying, it's gonna make us run out of kernel / hypervisor stack! */
2005 uint8_t rxPacket[E1K_MAX_RX_PKT_SIZE];
2006 uint8_t *ptr = rxPacket;
2007
2008#ifndef E1K_GLOBAL_MUTEX
2009 int rc = e1kCsRxEnter(pState, VERR_SEM_BUSY);
2010 if (RT_UNLIKELY(rc != VINF_SUCCESS))
2011 return rc;
2012#endif
2013
2014 if (cb > 70) /* unqualified guess */
2015 pState->led.Asserted.s.fReading = pState->led.Actual.s.fReading = 1;
2016
2017 Assert(cb <= E1K_MAX_RX_PKT_SIZE);
2018 memcpy(rxPacket, pvBuf, cb);
2019 /* Pad short packets */
2020 if (cb < 60)
2021 {
2022 memset(rxPacket + cb, 0, 60 - cb);
2023 cb = 60;
2024 }
2025 if (!(RCTL & RCTL_SECRC))
2026 {
2027 /* Add FCS if CRC stripping is not enabled */
2028 *(uint32_t*)(rxPacket + cb) = RTCrc32(rxPacket, cb);
2029 cb += sizeof(uint32_t);
2030 }
2031 /* Compute checksum of complete packet */
2032 uint16_t checksum = e1kCSum16(rxPacket + GET_BITS(RXCSUM, PCSS), cb);
2033 e1kRxChecksumOffload(pState, rxPacket, cb, &status);
2034
2035 /* Update stats */
2036 E1K_INC_CNT32(GPRC);
2037 if (e1kIsBroadcast(pvBuf))
2038 E1K_INC_CNT32(BPRC);
2039 else if (e1kIsMulticast(pvBuf))
2040 E1K_INC_CNT32(MPRC);
2041 /* Update octet receive counter */
2042 E1K_ADD_CNT64(GORCL, GORCH, cb);
2043 STAM_REL_COUNTER_ADD(&pState->StatReceiveBytes, cb);
2044 if (cb == 64)
2045 E1K_INC_CNT32(PRC64);
2046 else if (cb < 128)
2047 E1K_INC_CNT32(PRC127);
2048 else if (cb < 256)
2049 E1K_INC_CNT32(PRC255);
2050 else if (cb < 512)
2051 E1K_INC_CNT32(PRC511);
2052 else if (cb < 1024)
2053 E1K_INC_CNT32(PRC1023);
2054 else
2055 E1K_INC_CNT32(PRC1522);
2056
2057 E1K_INC_ISTAT_CNT(pState->uStatRxFrm);
2058
2059 if (RDH == RDT)
2060 {
2061 E1kLog(("%s Out of recieve buffers, dropping the packet",
2062 INSTANCE(pState)));
2063 }
2064 /* Store the packet to receive buffers */
2065 while (RDH != RDT)
2066 {
2067 /* Load the descriptor pointed by head */
2068 E1KRXDESC desc;
2069 PDMDevHlpPhysRead(pState->CTX_SUFF(pDevIns), e1kDescAddr(RDBAH, RDBAL, RDH),
2070 &desc, sizeof(desc));
2071 if (desc.u64BufAddr)
2072 {
2073 /* Update descriptor */
2074 desc.status = status;
2075 desc.u16Checksum = checksum;
2076 desc.status.fDD = true;
2077
2078 /*
2079 * We need to leave Rx critical section here or we risk deadlocking
2080 * with EMT in e1kRegWriteRDT when the write is to an unallocated
2081 * page or has an access handler associated with it.
2082 * Note that it is safe to leave the critical section here since e1kRegWriteRDT()
2083 * modifies RDT only.
2084 */
2085 if (cb > pState->u16RxBSize)
2086 {
2087 desc.status.fEOP = false;
2088 e1kCsRxLeave(pState);
2089 e1kStoreRxFragment(pState, &desc, ptr, pState->u16RxBSize);
2090 rc = e1kCsRxEnter(pState, VERR_SEM_BUSY);
2091 if (RT_UNLIKELY(rc != VINF_SUCCESS))
2092 return rc;
2093 ptr += pState->u16RxBSize;
2094 cb -= pState->u16RxBSize;
2095 }
2096 else
2097 {
2098 desc.status.fEOP = true;
2099 e1kCsRxLeave(pState);
2100 e1kStoreRxFragment(pState, &desc, ptr, cb);
2101 pState->led.Actual.s.fReading = 0;
2102 return VINF_SUCCESS;
2103 }
2104 /* Note: RDH is advanced by e1kStoreRxFragment! */
2105 }
2106 else
2107 {
2108 desc.status.fDD = true;
2109 PDMDevHlpPhysWrite(pState->CTX_SUFF(pDevIns),
2110 e1kDescAddr(RDBAH, RDBAL, RDH),
2111 &desc, sizeof(desc));
2112 e1kAdvanceRDH(pState);
2113 }
2114 }
2115
2116 if (cb > 0)
2117 E1kLog(("%s Out of recieve buffers, dropping %u bytes", INSTANCE(pState), cb));
2118
2119 pState->led.Actual.s.fReading = 0;
2120
2121 e1kCsRxLeave(pState);
2122
2123 return VINF_SUCCESS;
2124#else
2125 return VERR_INTERNAL_ERROR_2;
2126#endif
2127}
2128
2129
2130#if 0 /* unused */
2131/**
2132 * Read handler for Device Status register.
2133 *
2134 * Get the link status from PHY.
2135 *
2136 * @returns VBox status code.
2137 *
2138 * @param pState The device state structure.
2139 * @param offset Register offset in memory-mapped frame.
2140 * @param index Register index in register array.
2141 * @param mask Used to implement partial reads (8 and 16-bit).
2142 */
2143static int e1kRegReadCTRL(E1KSTATE* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value)
2144{
2145 E1kLog(("%s e1kRegReadCTRL: mdio dir=%s mdc dir=%s mdc=%d\n",
2146 INSTANCE(pState), (CTRL & CTRL_MDIO_DIR)?"OUT":"IN ",
2147 (CTRL & CTRL_MDC_DIR)?"OUT":"IN ", !!(CTRL & CTRL_MDC)));
2148 if ((CTRL & CTRL_MDIO_DIR) == 0 && (CTRL & CTRL_MDC))
2149 {
2150 /* MDC is high and MDIO pin is used for input, read MDIO pin from PHY */
2151 if (Phy::readMDIO(&pState->phy))
2152 *pu32Value = CTRL | CTRL_MDIO;
2153 else
2154 *pu32Value = CTRL & ~CTRL_MDIO;
2155 E1kLog(("%s e1kRegReadCTRL: Phy::readMDIO(%d)\n",
2156 INSTANCE(pState), !!(*pu32Value & CTRL_MDIO)));
2157 }
2158 else
2159 {
2160 /* MDIO pin is used for output, ignore it */
2161 *pu32Value = CTRL;
2162 }
2163 return VINF_SUCCESS;
2164}
2165#endif /* unused */
2166
2167/**
2168 * Write handler for Device Control register.
2169 *
2170 * Handles reset.
2171 *
2172 * @param pState The device state structure.
2173 * @param offset Register offset in memory-mapped frame.
2174 * @param index Register index in register array.
2175 * @param value The value to store.
2176 * @param mask Used to implement partial writes (8 and 16-bit).
2177 * @thread EMT
2178 */
2179static int e1kRegWriteCTRL(E1KSTATE* pState, uint32_t offset, uint32_t index, uint32_t value)
2180{
2181 int rc = VINF_SUCCESS;
2182
2183 if (value & CTRL_RESET)
2184 { /* RST */
2185#ifndef IN_RING3
2186 return VINF_IOM_HC_IOPORT_WRITE;
2187#else
2188 e1kHardReset(pState);
2189#endif
2190 }
2191 else
2192 {
2193 if ( (value & CTRL_SLU)
2194 && pState->fCableConnected
2195 && !(STATUS & STATUS_LU))
2196 {
2197 /* The driver indicates that we should bring up the link */
2198 /* Do so in 5 seconds. */
2199 e1kArmTimer(pState, pState->CTX_SUFF(pLUTimer), 5000000);
2200 /*
2201 * Change the status (but not PHY status) anyway as Windows expects
2202 * it for 82543GC.
2203 */
2204 STATUS |= STATUS_LU;
2205 }
2206 if (value & CTRL_VME)
2207 {
2208 E1kLog(("%s VLAN Mode is not supported yet!\n", INSTANCE(pState)));
2209 }
2210 E1kLog(("%s e1kRegWriteCTRL: mdio dir=%s mdc dir=%s mdc=%s mdio=%d\n",
2211 INSTANCE(pState), (value & CTRL_MDIO_DIR)?"OUT":"IN ",
2212 (value & CTRL_MDC_DIR)?"OUT":"IN ", (value & CTRL_MDC)?"HIGH":"LOW ", !!(value & CTRL_MDIO)));
2213 if (value & CTRL_MDC)
2214 {
2215 if (value & CTRL_MDIO_DIR)
2216 {
2217 E1kLog(("%s e1kRegWriteCTRL: Phy::writeMDIO(%d)\n", INSTANCE(pState), !!(value & CTRL_MDIO)));
2218 /* MDIO direction pin is set to output and MDC is high, write MDIO pin value to PHY */
2219 Phy::writeMDIO(&pState->phy, !!(value & CTRL_MDIO));
2220 }
2221 else
2222 {
2223 if (Phy::readMDIO(&pState->phy))
2224 value |= CTRL_MDIO;
2225 else
2226 value &= ~CTRL_MDIO;
2227 E1kLog(("%s e1kRegWriteCTRL: Phy::readMDIO(%d)\n",
2228 INSTANCE(pState), !!(value & CTRL_MDIO)));
2229 }
2230 }
2231 rc = e1kRegWriteDefault(pState, offset, index, value);
2232 }
2233
2234 return rc;
2235}
2236
2237/**
2238 * Write handler for EEPROM/Flash Control/Data register.
2239 *
2240 * Handles EEPROM access requests; forwards writes to EEPROM device if access has been granted.
2241 *
2242 * @param pState The device state structure.
2243 * @param offset Register offset in memory-mapped frame.
2244 * @param index Register index in register array.
2245 * @param value The value to store.
2246 * @param mask Used to implement partial writes (8 and 16-bit).
2247 * @thread EMT
2248 */
2249static int e1kRegWriteEECD(E1KSTATE* pState, uint32_t offset, uint32_t index, uint32_t value)
2250{
2251#ifdef IN_RING3
2252 /* So far we are concerned with lower byte only */
2253 if ((EECD & EECD_EE_GNT) || pState->eChip == E1K_CHIP_82543GC)
2254 {
2255 /* Access to EEPROM granted -- forward 4-wire bits to EEPROM device */
2256 /* Note: 82543GC does not need to request EEPROM access */
2257 STAM_PROFILE_ADV_START(&pState->StatEEPROMWrite, a);
2258 pState->eeprom.write(value & EECD_EE_WIRES);
2259 STAM_PROFILE_ADV_STOP(&pState->StatEEPROMWrite, a);
2260 }
2261 if (value & EECD_EE_REQ)
2262 EECD |= EECD_EE_REQ|EECD_EE_GNT;
2263 else
2264 EECD &= ~EECD_EE_GNT;
2265 //e1kRegWriteDefault(pState, offset, index, value );
2266
2267 return VINF_SUCCESS;
2268#else /* !IN_RING3 */
2269 return VINF_IOM_HC_MMIO_WRITE;
2270#endif /* !IN_RING3 */
2271}
2272
2273/**
2274 * Read handler for EEPROM/Flash Control/Data register.
2275 *
2276 * Lower 4 bits come from EEPROM device if EEPROM access has been granted.
2277 *
2278 * @returns VBox status code.
2279 *
2280 * @param pState The device state structure.
2281 * @param offset Register offset in memory-mapped frame.
2282 * @param index Register index in register array.
2283 * @param mask Used to implement partial reads (8 and 16-bit).
2284 * @thread EMT
2285 */
2286static int e1kRegReadEECD(E1KSTATE* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value)
2287{
2288#ifdef IN_RING3
2289 uint32_t value;
2290 int rc = e1kRegReadDefault(pState, offset, index, &value);
2291 if (RT_SUCCESS(rc))
2292 {
2293 if ((value & EECD_EE_GNT) || pState->eChip == E1K_CHIP_82543GC)
2294 {
2295 /* Note: 82543GC does not need to request EEPROM access */
2296 /* Access to EEPROM granted -- get 4-wire bits to EEPROM device */
2297 STAM_PROFILE_ADV_START(&pState->StatEEPROMRead, a);
2298 value |= pState->eeprom.read();
2299 STAM_PROFILE_ADV_STOP(&pState->StatEEPROMRead, a);
2300 }
2301 *pu32Value = value;
2302 }
2303
2304 return rc;
2305#else /* !IN_RING3 */
2306 return VINF_IOM_HC_MMIO_READ;
2307#endif /* !IN_RING3 */
2308}
2309
2310/**
2311 * Write handler for EEPROM Read register.
2312 *
2313 * Handles EEPROM word access requests, reads EEPROM and stores the result
2314 * into DATA field.
2315 *
2316 * @param pState The device state structure.
2317 * @param offset Register offset in memory-mapped frame.
2318 * @param index Register index in register array.
2319 * @param value The value to store.
2320 * @param mask Used to implement partial writes (8 and 16-bit).
2321 * @thread EMT
2322 */
2323static int e1kRegWriteEERD(E1KSTATE* pState, uint32_t offset, uint32_t index, uint32_t value)
2324{
2325#ifdef IN_RING3
2326 /* Make use of 'writable' and 'readable' masks. */
2327 e1kRegWriteDefault(pState, offset, index, value);
2328 /* DONE and DATA are set only if read was triggered by START. */
2329 if (value & EERD_START)
2330 {
2331 uint16_t tmp;
2332 STAM_PROFILE_ADV_START(&pState->StatEEPROMRead, a);
2333 if (pState->eeprom.readWord(GET_BITS_V(value, EERD, ADDR), &tmp))
2334 SET_BITS(EERD, DATA, tmp);
2335 EERD |= EERD_DONE;
2336 STAM_PROFILE_ADV_STOP(&pState->StatEEPROMRead, a);
2337 }
2338
2339 return VINF_SUCCESS;
2340#else /* !IN_RING3 */
2341 return VINF_IOM_HC_MMIO_WRITE;
2342#endif /* !IN_RING3 */
2343}
2344
2345
2346/**
2347 * Write handler for MDI Control register.
2348 *
2349 * Handles PHY read/write requests; forwards requests to internal PHY device.
2350 *
2351 * @param pState The device state structure.
2352 * @param offset Register offset in memory-mapped frame.
2353 * @param index Register index in register array.
2354 * @param value The value to store.
2355 * @param mask Used to implement partial writes (8 and 16-bit).
2356 * @thread EMT
2357 */
2358static int e1kRegWriteMDIC(E1KSTATE* pState, uint32_t offset, uint32_t index, uint32_t value)
2359{
2360 if (value & MDIC_INT_EN)
2361 {
2362 E1kLog(("%s ERROR! Interrupt at the end of an MDI cycle is not supported yet.\n",
2363 INSTANCE(pState)));
2364 }
2365 else if (value & MDIC_READY)
2366 {
2367 E1kLog(("%s ERROR! Ready bit is not reset by software during write operation.\n",
2368 INSTANCE(pState)));
2369 }
2370 else if (GET_BITS_V(value, MDIC, PHY) != 1)
2371 {
2372 E1kLog(("%s ERROR! Access to invalid PHY detected, phy=%d.\n",
2373 INSTANCE(pState), GET_BITS_V(value, MDIC, PHY)));
2374 }
2375 else
2376 {
2377 /* Store the value */
2378 e1kRegWriteDefault(pState, offset, index, value);
2379 STAM_COUNTER_INC(&pState->StatPHYAccesses);
2380 /* Forward op to PHY */
2381 if (value & MDIC_OP_READ)
2382 SET_BITS(MDIC, DATA, Phy::readRegister(&pState->phy, GET_BITS_V(value, MDIC, REG)));
2383 else
2384 Phy::writeRegister(&pState->phy, GET_BITS_V(value, MDIC, REG), value & MDIC_DATA_MASK);
2385 /* Let software know that we are done */
2386 MDIC |= MDIC_READY;
2387 }
2388
2389 return VINF_SUCCESS;
2390}
2391
2392/**
2393 * Write handler for Interrupt Cause Read register.
2394 *
2395 * Bits corresponding to 1s in 'value' will be cleared in ICR register.
2396 *
2397 * @param pState The device state structure.
2398 * @param offset Register offset in memory-mapped frame.
2399 * @param index Register index in register array.
2400 * @param value The value to store.
2401 * @param mask Used to implement partial writes (8 and 16-bit).
2402 * @thread EMT
2403 */
2404static int e1kRegWriteICR(E1KSTATE* pState, uint32_t offset, uint32_t index, uint32_t value)
2405{
2406 ICR &= ~value;
2407
2408 return VINF_SUCCESS;
2409}
2410
2411/**
2412 * Read handler for Interrupt Cause Read register.
2413 *
2414 * Reading this register acknowledges all interrupts.
2415 *
2416 * @returns VBox status code.
2417 *
2418 * @param pState The device state structure.
2419 * @param offset Register offset in memory-mapped frame.
2420 * @param index Register index in register array.
2421 * @param mask Not used.
2422 * @thread EMT
2423 */
2424static int e1kRegReadICR(E1KSTATE* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value)
2425{
2426 int rc = e1kCsEnter(pState, VINF_IOM_HC_MMIO_READ);
2427 if (RT_UNLIKELY(rc != VINF_SUCCESS))
2428 return rc;
2429
2430 uint32_t value = 0;
2431 rc = e1kRegReadDefault(pState, offset, index, &value);
2432 if (RT_SUCCESS(rc))
2433 {
2434 if (value)
2435 {
2436 /*
2437 * Not clearing ICR causes QNX to hang as it reads ICR in a loop
2438 * with disabled interrupts.
2439 */
2440 //if (IMS)
2441 if (1)
2442 {
2443 /*
2444 * Interrupts were enabled -- we are supposedly at the very
2445 * beginning of interrupt handler
2446 */
2447 E1kLogRel(("E1000: irq lowered, icr=0x%x\n", ICR));
2448 E1kLog(("%s e1kRegReadICR: Lowered IRQ (%08x)\n", INSTANCE(pState), ICR));
2449 /* Clear all pending interrupts */
2450 ICR = 0;
2451 pState->fIntRaised = false;
2452 /* Lower(0) INTA(0) */
2453 //e1kMutexRelease(pState);
2454 PDMDevHlpPCISetIrq(pState->CTX_SUFF(pDevIns), 0, 0);
2455 //e1kMutexAcquire(pState, RT_SRC_POS);
2456
2457 pState->u64AckedAt = TMTimerGet(pState->CTX_SUFF(pIntTimer));
2458 if (pState->fIntMaskUsed)
2459 pState->fDelayInts = true;
2460 }
2461 else
2462 {
2463 /*
2464 * Interrupts are disabled -- in windows guests ICR read is done
2465 * just before re-enabling interrupts
2466 */
2467 E1kLog(("%s e1kRegReadICR: Suppressing auto-clear due to disabled interrupts (%08x)\n", INSTANCE(pState), ICR));
2468 }
2469 }
2470 *pu32Value = value;
2471 }
2472 e1kCsLeave(pState);
2473
2474 return rc;
2475}
2476
2477/**
2478 * Write handler for Interrupt Cause Set register.
2479 *
2480 * Bits corresponding to 1s in 'value' will be set in ICR register.
2481 *
2482 * @param pState The device state structure.
2483 * @param offset Register offset in memory-mapped frame.
2484 * @param index Register index in register array.
2485 * @param value The value to store.
2486 * @param mask Used to implement partial writes (8 and 16-bit).
2487 * @thread EMT
2488 */
2489static int e1kRegWriteICS(E1KSTATE* pState, uint32_t offset, uint32_t index, uint32_t value)
2490{
2491 E1K_INC_ISTAT_CNT(pState->uStatIntICS);
2492 return e1kRaiseInterrupt(pState, VINF_IOM_HC_MMIO_WRITE, value & s_e1kRegMap[ICS_IDX].writable);
2493}
2494
2495/**
2496 * Write handler for Interrupt Mask Set register.
2497 *
2498 * Will trigger pending interrupts.
2499 *
2500 * @param pState The device state structure.
2501 * @param offset Register offset in memory-mapped frame.
2502 * @param index Register index in register array.
2503 * @param value The value to store.
2504 * @param mask Used to implement partial writes (8 and 16-bit).
2505 * @thread EMT
2506 */
2507static int e1kRegWriteIMS(E1KSTATE* pState, uint32_t offset, uint32_t index, uint32_t value)
2508{
2509 IMS |= value;
2510 E1kLogRel(("E1000: irq enabled, RDH=%x RDT=%x TDH=%x TDT=%x\n", RDH, RDT, TDH, TDT));
2511 E1kLog(("%s e1kRegWriteIMS: IRQ enabled\n", INSTANCE(pState)));
2512 /* Mask changes, we need to raise pending interrupts. */
2513 if ((ICR & IMS) && !pState->fLocked)
2514 {
2515 E1kLog2(("%s e1kRegWriteIMS: IRQ pending (%08x), arming late int timer...\n",
2516 INSTANCE(pState), ICR));
2517 //TMTimerSet(pState->CTX_SUFF(pIntTimer), TMTimerFromNano(pState->CTX_SUFF(pIntTimer), ITR * 256) +
2518 // TMTimerGet(pState->CTX_SUFF(pIntTimer)));
2519 e1kRaiseInterrupt(pState, VERR_SEM_BUSY);
2520 }
2521
2522 return VINF_SUCCESS;
2523}
2524
2525/**
2526 * Write handler for Interrupt Mask Clear register.
2527 *
2528 * Bits corresponding to 1s in 'value' will be cleared in IMS register.
2529 *
2530 * @param pState The device state structure.
2531 * @param offset Register offset in memory-mapped frame.
2532 * @param index Register index in register array.
2533 * @param value The value to store.
2534 * @param mask Used to implement partial writes (8 and 16-bit).
2535 * @thread EMT
2536 */
2537static int e1kRegWriteIMC(E1KSTATE* pState, uint32_t offset, uint32_t index, uint32_t value)
2538{
2539 int rc = e1kCsEnter(pState, VINF_IOM_HC_MMIO_WRITE);
2540 if (RT_UNLIKELY(rc != VINF_SUCCESS))
2541 return rc;
2542 if (pState->fIntRaised)
2543 {
2544 /*
2545 * Technically we should reset fIntRaised in ICR read handler, but it will cause
2546 * Windows to freeze since it may receive an interrupt while still in the very beginning
2547 * of interrupt handler.
2548 */
2549 E1K_INC_ISTAT_CNT(pState->uStatIntLower);
2550 STAM_COUNTER_INC(&pState->StatIntsPrevented);
2551 E1kLogRel(("E1000: irq lowered (IMC), icr=0x%x\n", ICR));
2552 /* Lower(0) INTA(0) */
2553 PDMDevHlpPCISetIrq(pState->CTX_SUFF(pDevIns), 0, 0);
2554 pState->fIntRaised = false;
2555 E1kLog(("%s e1kRegWriteIMC: Lowered IRQ: ICR=%08x\n", INSTANCE(pState), ICR));
2556 }
2557 IMS &= ~value;
2558 E1kLog(("%s e1kRegWriteIMC: IRQ disabled\n", INSTANCE(pState)));
2559 e1kCsLeave(pState);
2560
2561 return VINF_SUCCESS;
2562}
2563
2564/**
2565 * Write handler for Receive Control register.
2566 *
2567 * @param pState The device state structure.
2568 * @param offset Register offset in memory-mapped frame.
2569 * @param index Register index in register array.
2570 * @param value The value to store.
2571 * @param mask Used to implement partial writes (8 and 16-bit).
2572 * @thread EMT
2573 */
2574static int e1kRegWriteRCTL(E1KSTATE* pState, uint32_t offset, uint32_t index, uint32_t value)
2575{
2576 /* Update promiscuous mode */
2577 bool fBecomePromiscous = !!(value & (RCTL_UPE | RCTL_MPE));
2578 if (fBecomePromiscous != !!( RCTL & (RCTL_UPE | RCTL_MPE)))
2579 {
2580 /* Promiscuity has changed, pass the knowledge on. */
2581#ifndef IN_RING3
2582 return VINF_IOM_HC_IOPORT_WRITE;
2583#else
2584 if (pState->pDrvR3)
2585 pState->pDrvR3->pfnSetPromiscuousMode(pState->pDrvR3, fBecomePromiscous);
2586#endif
2587 }
2588
2589 /* Adjust receive buffer size */
2590 unsigned cbRxBuf = 2048 >> GET_BITS_V(value, RCTL, BSIZE);
2591 if (value & RCTL_BSEX)
2592 cbRxBuf *= 16;
2593 if (cbRxBuf != pState->u16RxBSize)
2594 E1kLog2(("%s e1kRegWriteRCTL: Setting receive buffer size to %d (old %d)\n",
2595 INSTANCE(pState), cbRxBuf, pState->u16RxBSize));
2596 pState->u16RxBSize = cbRxBuf;
2597
2598 /* Update the register */
2599 e1kRegWriteDefault(pState, offset, index, value);
2600
2601 return VINF_SUCCESS;
2602}
2603
2604/**
2605 * Write handler for Packet Buffer Allocation register.
2606 *
2607 * TXA = 64 - RXA.
2608 *
2609 * @param pState The device state structure.
2610 * @param offset Register offset in memory-mapped frame.
2611 * @param index Register index in register array.
2612 * @param value The value to store.
2613 * @param mask Used to implement partial writes (8 and 16-bit).
2614 * @thread EMT
2615 */
2616static int e1kRegWritePBA(E1KSTATE* pState, uint32_t offset, uint32_t index, uint32_t value)
2617{
2618 e1kRegWriteDefault(pState, offset, index, value);
2619 PBA_st->txa = 64 - PBA_st->rxa;
2620
2621 return VINF_SUCCESS;
2622}
2623
2624/**
2625 * Write handler for Receive Descriptor Tail register.
2626 *
2627 * @remarks Write into RDT forces switch to HC and signal to
2628 * e1kNetworkDown_WaitReceiveAvail().
2629 *
2630 * @returns VBox status code.
2631 *
2632 * @param pState The device state structure.
2633 * @param offset Register offset in memory-mapped frame.
2634 * @param index Register index in register array.
2635 * @param value The value to store.
2636 * @param mask Used to implement partial writes (8 and 16-bit).
2637 * @thread EMT
2638 */
2639static int e1kRegWriteRDT(E1KSTATE* pState, uint32_t offset, uint32_t index, uint32_t value)
2640{
2641#ifndef IN_RING3
2642 /* XXX */
2643// return VINF_IOM_HC_MMIO_WRITE;
2644#endif
2645 int rc = e1kCsRxEnter(pState, VINF_IOM_HC_MMIO_WRITE);
2646 if (RT_LIKELY(rc == VINF_SUCCESS))
2647 {
2648 E1kLog(("%s e1kRegWriteRDT\n", INSTANCE(pState)));
2649 rc = e1kRegWriteDefault(pState, offset, index, value);
2650 e1kCsRxLeave(pState);
2651 if (RT_SUCCESS(rc))
2652 {
2653/** @todo bird: Use SUPSem* for this so we can signal it in ring-0 as well
2654 * without requiring any context switches. We should also check the
2655 * wait condition before bothering to queue the item as we're currently
2656 * queuing thousands of items per second here in a normal transmit
2657 * scenario. Expect performance changes when fixing this! */
2658#ifdef IN_RING3
2659 /* Signal that we have more receive descriptors available. */
2660 e1kWakeupReceive(pState->CTX_SUFF(pDevIns));
2661#else
2662 PPDMQUEUEITEMCORE pItem = PDMQueueAlloc(pState->CTX_SUFF(pCanRxQueue));
2663 if (pItem)
2664 PDMQueueInsert(pState->CTX_SUFF(pCanRxQueue), pItem);
2665#endif
2666 }
2667 }
2668 return rc;
2669}
2670
2671/**
2672 * Write handler for Receive Delay Timer register.
2673 *
2674 * @param pState The device state structure.
2675 * @param offset Register offset in memory-mapped frame.
2676 * @param index Register index in register array.
2677 * @param value The value to store.
2678 * @param mask Used to implement partial writes (8 and 16-bit).
2679 * @thread EMT
2680 */
2681static int e1kRegWriteRDTR(E1KSTATE* pState, uint32_t offset, uint32_t index, uint32_t value)
2682{
2683 e1kRegWriteDefault(pState, offset, index, value);
2684 if (value & RDTR_FPD)
2685 {
2686 /* Flush requested, cancel both timers and raise interrupt */
2687#ifdef E1K_USE_RX_TIMERS
2688 e1kCancelTimer(pState, pState->CTX_SUFF(pRIDTimer));
2689 e1kCancelTimer(pState, pState->CTX_SUFF(pRADTimer));
2690#endif
2691 E1K_INC_ISTAT_CNT(pState->uStatIntRDTR);
2692 return e1kRaiseInterrupt(pState, VINF_IOM_HC_MMIO_WRITE, ICR_RXT0);
2693 }
2694
2695 return VINF_SUCCESS;
2696}
2697
2698DECLINLINE(uint32_t) e1kGetTxLen(E1KSTATE* pState)
2699{
2700 /**
2701 * Make sure TDT won't change during computation. EMT may modify TDT at
2702 * any moment.
2703 */
2704 uint32_t tdt = TDT;
2705 return (TDH>tdt ? TDLEN/sizeof(E1KTXDESC) : 0) + tdt - TDH;
2706}
2707
2708#ifdef IN_RING3
2709#ifdef E1K_USE_TX_TIMERS
2710
2711/**
2712 * Transmit Interrupt Delay Timer handler.
2713 *
2714 * @remarks We only get here when the timer expires.
2715 *
2716 * @param pDevIns Pointer to device instance structure.
2717 * @param pTimer Pointer to the timer.
2718 * @param pvUser NULL.
2719 * @thread EMT
2720 */
2721static DECLCALLBACK(void) e1kTxIntDelayTimer(PPDMDEVINS pDevIns, PTMTIMER pTimer, void *pvUser)
2722{
2723 E1KSTATE *pState = (E1KSTATE *)pvUser;
2724
2725 if (RT_LIKELY(e1kMutexAcquire(pState, VERR_SEM_BUSY, RT_SRC_POS) == VINF_SUCCESS))
2726 {
2727 E1K_INC_ISTAT_CNT(pState->uStatTID);
2728 /* Cancel absolute delay timer as we have already got attention */
2729#ifndef E1K_NO_TAD
2730 e1kCancelTimer(pState, pState->CTX_SUFF(pTADTimer));
2731#endif /* E1K_NO_TAD */
2732 e1kRaiseInterrupt(pState, ICR_TXDW);
2733 e1kMutexRelease(pState);
2734 }
2735}
2736
2737/**
2738 * Transmit Absolute Delay Timer handler.
2739 *
2740 * @remarks We only get here when the timer expires.
2741 *
2742 * @param pDevIns Pointer to device instance structure.
2743 * @param pTimer Pointer to the timer.
2744 * @param pvUser NULL.
2745 * @thread EMT
2746 */
2747static DECLCALLBACK(void) e1kTxAbsDelayTimer(PPDMDEVINS pDevIns, PTMTIMER pTimer, void *pvUser)
2748{
2749 E1KSTATE *pState = (E1KSTATE *)pvUser;
2750
2751 if (RT_LIKELY(e1kMutexAcquire(pState, VERR_SEM_BUSY, RT_SRC_POS) == VINF_SUCCESS))
2752 {
2753 E1K_INC_ISTAT_CNT(pState->uStatTAD);
2754 /* Cancel interrupt delay timer as we have already got attention */
2755 e1kCancelTimer(pState, pState->CTX_SUFF(pTIDTimer));
2756 e1kRaiseInterrupt(pState, ICR_TXDW);
2757 e1kMutexRelease(pState);
2758 }
2759}
2760
2761#endif /* E1K_USE_TX_TIMERS */
2762#ifdef E1K_USE_RX_TIMERS
2763
2764/**
2765 * Receive Interrupt Delay Timer handler.
2766 *
2767 * @remarks We only get here when the timer expires.
2768 *
2769 * @param pDevIns Pointer to device instance structure.
2770 * @param pTimer Pointer to the timer.
2771 * @param pvUser NULL.
2772 * @thread EMT
2773 */
2774static DECLCALLBACK(void) e1kRxIntDelayTimer(PPDMDEVINS pDevIns, PTMTIMER pTimer, void *pvUser)
2775{
2776 E1KSTATE *pState = (E1KSTATE *)pvUser;
2777
2778 if (RT_LIKELY(e1kMutexAcquire(pState, VERR_SEM_BUSY, RT_SRC_POS) == VINF_SUCCESS))
2779 {
2780 E1K_INC_ISTAT_CNT(pState->uStatRID);
2781 /* Cancel absolute delay timer as we have already got attention */
2782 e1kCancelTimer(pState, pState->CTX_SUFF(pRADTimer));
2783 e1kRaiseInterrupt(pState, ICR_RXT0);
2784 e1kMutexRelease(pState);
2785 }
2786}
2787
2788/**
2789 * Receive Absolute Delay Timer handler.
2790 *
2791 * @remarks We only get here when the timer expires.
2792 *
2793 * @param pDevIns Pointer to device instance structure.
2794 * @param pTimer Pointer to the timer.
2795 * @param pvUser NULL.
2796 * @thread EMT
2797 */
2798static DECLCALLBACK(void) e1kRxAbsDelayTimer(PPDMDEVINS pDevIns, PTMTIMER pTimer, void *pvUser)
2799{
2800 E1KSTATE *pState = (E1KSTATE *)pvUser;
2801
2802 if (RT_LIKELY(e1kMutexAcquire(pState, VERR_SEM_BUSY, RT_SRC_POS) == VINF_SUCCESS))
2803 {
2804 E1K_INC_ISTAT_CNT(pState->uStatRAD);
2805 /* Cancel interrupt delay timer as we have already got attention */
2806 e1kCancelTimer(pState, pState->CTX_SUFF(pRIDTimer));
2807 e1kRaiseInterrupt(pState, ICR_RXT0);
2808 e1kMutexRelease(pState);
2809 }
2810}
2811
2812#endif /* E1K_USE_RX_TIMERS */
2813
2814/**
2815 * Late Interrupt Timer handler.
2816 *
2817 * @param pDevIns Pointer to device instance structure.
2818 * @param pTimer Pointer to the timer.
2819 * @param pvUser NULL.
2820 * @thread EMT
2821 */
2822static DECLCALLBACK(void) e1kLateIntTimer(PPDMDEVINS pDevIns, PTMTIMER pTimer, void *pvUser)
2823{
2824 E1KSTATE *pState = (E1KSTATE *)pvUser;
2825
2826 STAM_PROFILE_ADV_START(&pState->StatLateIntTimer, a);
2827 if (RT_LIKELY(e1kMutexAcquire(pState, VERR_SEM_BUSY, RT_SRC_POS) == VINF_SUCCESS))
2828 {
2829 STAM_COUNTER_INC(&pState->StatLateInts);
2830 E1K_INC_ISTAT_CNT(pState->uStatIntLate);
2831#if 0
2832 if (pState->iStatIntLost > -100)
2833 pState->iStatIntLost--;
2834#endif
2835 e1kRaiseInterrupt(pState, VERR_SEM_BUSY, 0);
2836 e1kMutexRelease(pState);
2837 }
2838 STAM_PROFILE_ADV_STOP(&pState->StatLateIntTimer, a);
2839}
2840
2841/**
2842 * Link Up Timer handler.
2843 *
2844 * @param pDevIns Pointer to device instance structure.
2845 * @param pTimer Pointer to the timer.
2846 * @param pvUser NULL.
2847 * @thread EMT
2848 */
2849static DECLCALLBACK(void) e1kLinkUpTimer(PPDMDEVINS pDevIns, PTMTIMER pTimer, void *pvUser)
2850{
2851 E1KSTATE *pState = (E1KSTATE *)pvUser;
2852
2853 if (RT_LIKELY(e1kMutexAcquire(pState, VERR_SEM_BUSY, RT_SRC_POS) == VINF_SUCCESS))
2854 {
2855 STATUS |= STATUS_LU;
2856 Phy::setLinkStatus(&pState->phy, true);
2857 e1kRaiseInterrupt(pState, VERR_SEM_BUSY, ICR_LSC);
2858 e1kMutexRelease(pState);
2859 }
2860}
2861
2862#endif /* IN_RING3 */
2863
2864/**
2865 * Sets up the GSO context according to the TSE new context descriptor.
2866 *
2867 * @param pGso The GSO context to setup.
2868 * @param pCtx The context descriptor.
2869 */
2870DECLINLINE(void) e1kSetupGsoCtx(PPDMNETWORKGSO pGso, E1KTXCTX const *pCtx)
2871{
2872 pGso->u8Type = PDMNETWORKGSOTYPE_INVALID;
2873
2874 /*
2875 * See if the context descriptor describes something that could be TCP or
2876 * UDP over IPv[46].
2877 */
2878 /* Check the header ordering and spacing: 1. Ethernet, 2. IP, 3. TCP/UDP. */
2879 if (RT_UNLIKELY( pCtx->ip.u8CSS < sizeof(RTNETETHERHDR) ))
2880 {
2881 E1kLog(("e1kSetupGsoCtx: IPCSS=%#x\n", pCtx->ip.u8CSS));
2882 return;
2883 }
2884 if (RT_UNLIKELY( pCtx->tu.u8CSS < (size_t)pCtx->ip.u8CSS + (pCtx->dw2.fIP ? RTNETIPV4_MIN_LEN : RTNETIPV6_MIN_LEN) ))
2885 {
2886 E1kLog(("e1kSetupGsoCtx: TUCSS=%#x\n", pCtx->tu.u8CSS));
2887 return;
2888 }
2889 if (RT_UNLIKELY( pCtx->dw2.fTCP
2890 ? pCtx->dw3.u8HDRLEN < (size_t)pCtx->tu.u8CSS + RTNETTCP_MIN_LEN
2891 : pCtx->dw3.u8HDRLEN != (size_t)pCtx->tu.u8CSS + RTNETUDP_MIN_LEN ))
2892 {
2893 E1kLog(("e1kSetupGsoCtx: HDRLEN=%#x TCP=%d\n", pCtx->dw3.u8HDRLEN, pCtx->dw2.fTCP));
2894 return;
2895 }
2896
2897 /* The end of the TCP/UDP checksum should stop at the end of the packet or at least after the headers. */
2898 if (RT_UNLIKELY( pCtx->tu.u16CSE > 0 && pCtx->tu.u16CSE <= pCtx->dw3.u8HDRLEN ))
2899 {
2900 E1kLog(("e1kSetupGsoCtx: TUCSE=%#x HDRLEN=%#x\n", pCtx->tu.u16CSE, pCtx->dw3.u8HDRLEN));
2901 return;
2902 }
2903
2904 /* IPv4 checksum offset. */
2905 if (RT_UNLIKELY( pCtx->dw2.fIP && (size_t)pCtx->ip.u8CSO - pCtx->ip.u8CSS != RT_UOFFSETOF(RTNETIPV4, ip_sum) ))
2906 {
2907 E1kLog(("e1kSetupGsoCtx: IPCSO=%#x IPCSS=%#x\n", pCtx->ip.u8CSO, pCtx->ip.u8CSS));
2908 return;
2909 }
2910
2911 /* TCP/UDP checksum offsets. */
2912 if (RT_UNLIKELY( (size_t)pCtx->tu.u8CSO - pCtx->tu.u8CSS
2913 != ( pCtx->dw2.fTCP
2914 ? RT_UOFFSETOF(RTNETTCP, th_sum)
2915 : RT_UOFFSETOF(RTNETUDP, uh_sum) ) ))
2916 {
2917 E1kLog(("e1kSetupGsoCtx: TUCSO=%#x TUCSS=%#x TCP=%d\n", pCtx->ip.u8CSO, pCtx->ip.u8CSS, pCtx->dw2.fTCP));
2918 return;
2919 }
2920
2921 /*
2922 * Because of internal networking using a 16-bit size field for GSO context
2923 * plus frame, we have to make sure we don't exceed this.
2924 */
2925 if (RT_UNLIKELY( pCtx->dw3.u8HDRLEN + pCtx->dw2.u20PAYLEN > VBOX_MAX_GSO_SIZE ))
2926 {
2927 E1kLog(("e1kSetupGsoCtx: HDRLEN(=%#x) + PAYLEN(=%#x) = %#x, max is %#x\n",
2928 pCtx->dw3.u8HDRLEN, pCtx->dw2.u20PAYLEN, pCtx->dw3.u8HDRLEN + pCtx->dw2.u20PAYLEN, VBOX_MAX_GSO_SIZE));
2929 return;
2930 }
2931
2932 /*
2933 * We're good for now - we'll do more checks when seeing the data.
2934 * So, figure the type of offloading and setup the context.
2935 */
2936 if (pCtx->dw2.fIP)
2937 {
2938 if (pCtx->dw2.fTCP)
2939 pGso->u8Type = PDMNETWORKGSOTYPE_IPV4_TCP;
2940 else
2941 pGso->u8Type = PDMNETWORKGSOTYPE_IPV4_UDP;
2942 /** @todo Detect IPv4-IPv6 tunneling (need test setup since linux doesn't do
2943 * this yet it seems)... */
2944 }
2945 else
2946 {
2947 if (pCtx->dw2.fTCP)
2948 pGso->u8Type = PDMNETWORKGSOTYPE_IPV6_TCP;
2949 else
2950 pGso->u8Type = PDMNETWORKGSOTYPE_IPV6_UDP;
2951 }
2952 pGso->offHdr1 = pCtx->ip.u8CSS;
2953 pGso->offHdr2 = pCtx->tu.u8CSS;
2954 pGso->cbHdrs = pCtx->dw3.u8HDRLEN;
2955 pGso->cbMaxSeg = pCtx->dw3.u16MSS;
2956 Assert(PDMNetGsoIsValid(pGso, sizeof(*pGso), pGso->cbMaxSeg * 5));
2957 E1kLog2(("e1kSetupGsoCtx: mss=%#x hdr=%#x hdr1=%#x hdr2=%#x %s\n",
2958 pGso->cbMaxSeg, pGso->cbHdrs, pGso->offHdr1, pGso->offHdr2, PDMNetGsoTypeName((PDMNETWORKGSOTYPE)pGso->u8Type) ));
2959}
2960
2961/**
2962 * Checks if we can use GSO processing for the current TSE frame.
2963 *
2964 * @param pGso The GSO context.
2965 * @param pData The first data descriptor of the frame.
2966 * @param pCtx The TSO context descriptor.
2967 */
2968DECLINLINE(bool) e1kCanDoGso(PCPDMNETWORKGSO pGso, E1KTXDAT const *pData, E1KTXCTX const *pCtx)
2969{
2970 if (!pData->cmd.fTSE)
2971 {
2972 E1kLog2(("e1kCanDoGso: !TSE\n"));
2973 return false;
2974 }
2975 if (pData->cmd.fVLE) /** @todo VLAN tagging. */
2976 {
2977 E1kLog(("e1kCanDoGso: VLE\n"));
2978 return false;
2979 }
2980
2981 switch ((PDMNETWORKGSOTYPE)pGso->u8Type)
2982 {
2983 case PDMNETWORKGSOTYPE_IPV4_TCP:
2984 case PDMNETWORKGSOTYPE_IPV4_UDP:
2985 if (!pData->dw3.fIXSM)
2986 {
2987 E1kLog(("e1kCanDoGso: !IXSM (IPv4)\n"));
2988 return false;
2989 }
2990 if (!pData->dw3.fTXSM)
2991 {
2992 E1kLog(("e1kCanDoGso: !TXSM (IPv4)\n"));
2993 return false;
2994 }
2995 /** @todo what more check should we perform here? Ethernet frame type? */
2996 E1kLog2(("e1kCanDoGso: OK, IPv4\n"));
2997 return true;
2998
2999 case PDMNETWORKGSOTYPE_IPV6_TCP:
3000 case PDMNETWORKGSOTYPE_IPV6_UDP:
3001 if (pData->dw3.fIXSM && pCtx->ip.u8CSO)
3002 {
3003 E1kLog(("e1kCanDoGso: IXSM (IPv6)\n"));
3004 return false;
3005 }
3006 if (!pData->dw3.fTXSM)
3007 {
3008 E1kLog(("e1kCanDoGso: TXSM (IPv6)\n"));
3009 return false;
3010 }
3011 /** @todo what more check should we perform here? Ethernet frame type? */
3012 E1kLog2(("e1kCanDoGso: OK, IPv4\n"));
3013 return true;
3014
3015 default:
3016 Assert(pGso->u8Type == PDMNETWORKGSOTYPE_INVALID);
3017 E1kLog2(("e1kCanDoGso: e1kSetupGsoCtx failed\n"));
3018 return false;
3019 }
3020}
3021
3022/**
3023 * Frees the current xmit buffer.
3024 *
3025 * @param pState The device state structure.
3026 */
3027static void e1kXmitFreeBuf(E1KSTATE *pState)
3028{
3029 PPDMSCATTERGATHER pSg = pState->CTX_SUFF(pTxSg);
3030 if (pSg)
3031 {
3032 pState->CTX_SUFF(pTxSg) = NULL;
3033
3034 if (pSg->pvAllocator != pState)
3035 {
3036 PPDMINETWORKUP pDrv = pState->CTX_SUFF(pDrv);
3037 if (pDrv)
3038 pDrv->pfnFreeBuf(pDrv, pSg);
3039 }
3040 else
3041 {
3042 /* loopback */
3043 AssertCompileMemberSize(E1KSTATE, uTxFallback.Sg, 8 * sizeof(size_t));
3044 Assert(pSg->fFlags == (PDMSCATTERGATHER_FLAGS_MAGIC | PDMSCATTERGATHER_FLAGS_OWNER_3));
3045 pSg->fFlags = 0;
3046 pSg->pvAllocator = NULL;
3047 }
3048 }
3049}
3050
3051/**
3052 * Allocates a xmit buffer.
3053 *
3054 * Presently this will always return a buffer. Later on we'll have a
3055 * out-of-buffer mechanism in place where the driver calls us back when buffers
3056 * becomes available.
3057 *
3058 * @returns See PDMINETWORKUP::pfnAllocBuf.
3059 * @param pState The device state structure.
3060 * @param cbMin The minimum frame size.
3061 * @param fExactSize Whether cbMin is exact or if we have to max it
3062 * out to the max MTU size.
3063 * @param fGso Whether this is a GSO frame or not.
3064 */
3065DECLINLINE(int) e1kXmitAllocBuf(E1KSTATE *pState, size_t cbMin, bool fExactSize, bool fGso)
3066{
3067 /* Adjust cbMin if necessary. */
3068 if (!fExactSize)
3069 cbMin = RT_MAX(cbMin, E1K_MAX_TX_PKT_SIZE);
3070
3071 /* Deal with existing buffer (descriptor screw up, reset, etc). */
3072 if (RT_UNLIKELY(pState->CTX_SUFF(pTxSg)))
3073 e1kXmitFreeBuf(pState);
3074 Assert(pState->CTX_SUFF(pTxSg) == NULL);
3075
3076 /*
3077 * Allocate the buffer.
3078 */
3079 PPDMSCATTERGATHER pSg;
3080 if (RT_LIKELY(GET_BITS(RCTL, LBM) != RCTL_LBM_TCVR))
3081 {
3082 PPDMINETWORKUP pDrv = pState->CTX_SUFF(pDrv);
3083 if (RT_UNLIKELY(!pDrv))
3084 return VERR_NET_DOWN;
3085 int rc = pDrv->pfnAllocBuf(pDrv, cbMin, fGso ? &pState->GsoCtx : NULL, &pSg);
3086 if (RT_FAILURE(rc))
3087 return rc;
3088 }
3089 else
3090 {
3091 /* Create a loopback using the fallback buffer and preallocated SG. */
3092 AssertCompileMemberSize(E1KSTATE, uTxFallback.Sg, 8 * sizeof(size_t));
3093 pSg = &pState->uTxFallback.Sg;
3094 pSg->fFlags = PDMSCATTERGATHER_FLAGS_MAGIC | PDMSCATTERGATHER_FLAGS_OWNER_3;
3095 pSg->cbUsed = 0;
3096 pSg->cbAvailable = 0;
3097 pSg->pvAllocator = pState;
3098 pSg->pvUser = NULL; /* No GSO here. */
3099 pSg->cSegs = 1;
3100 pSg->aSegs[0].pvSeg = pState->aTxPacketFallback;
3101 pSg->aSegs[0].cbSeg = sizeof(pState->aTxPacketFallback);
3102 }
3103
3104 pState->CTX_SUFF(pTxSg) = pSg;
3105 return VINF_SUCCESS;
3106}
3107
3108/**
3109 * Checks if it's a GSO buffer or not.
3110 *
3111 * @returns true / false.
3112 * @param pTxSg The scatter / gather buffer.
3113 */
3114DECLINLINE(bool) e1kXmitIsGsoBuf(PDMSCATTERGATHER const *pTxSg)
3115{
3116#if 0
3117 if (!pTxSg)
3118 E1kLog(("e1kXmitIsGsoBuf: pTxSG is NULL\n"));
3119 if (pTxSg && pTxSg->pvUser)
3120 E1kLog(("e1kXmitIsGsoBuf: pvUser is NULL\n"));
3121#endif
3122 return pTxSg && pTxSg->pvUser /* GSO indicator */;
3123}
3124
3125/**
3126 * Load transmit descriptor from guest memory.
3127 *
3128 * @param pState The device state structure.
3129 * @param pDesc Pointer to descriptor union.
3130 * @param addr Physical address in guest context.
3131 * @thread E1000_TX
3132 */
3133DECLINLINE(void) e1kLoadDesc(E1KSTATE* pState, E1KTXDESC* pDesc, RTGCPHYS addr)
3134{
3135 PDMDevHlpPhysRead(pState->CTX_SUFF(pDevIns), addr, pDesc, sizeof(E1KTXDESC));
3136}
3137
3138/**
3139 * Write back transmit descriptor to guest memory.
3140 *
3141 * @param pState The device state structure.
3142 * @param pDesc Pointer to descriptor union.
3143 * @param addr Physical address in guest context.
3144 * @thread E1000_TX
3145 */
3146DECLINLINE(void) e1kWriteBackDesc(E1KSTATE* pState, E1KTXDESC* pDesc, RTGCPHYS addr)
3147{
3148 /* Only the last half of the descriptor has to be written back. */
3149 e1kPrintTDesc(pState, pDesc, "^^^");
3150 PDMDevHlpPhysWrite(pState->CTX_SUFF(pDevIns), addr, pDesc, sizeof(E1KTXDESC));
3151}
3152
3153/**
3154 * Transmit complete frame.
3155 *
3156 * @remarks We skip the FCS since we're not responsible for sending anything to
3157 * a real ethernet wire.
3158 *
3159 * @param pState The device state structure.
3160 * @param fOnWorkerThread Whether we're on a worker thread or an EMT.
3161 * @thread E1000_TX
3162 */
3163static void e1kTransmitFrame(E1KSTATE* pState, bool fOnWorkerThread)
3164{
3165 PPDMSCATTERGATHER pSg = pState->CTX_SUFF(pTxSg);
3166 uint32_t const cbFrame = pSg ? (uint32_t)pSg->cbUsed : 0;
3167 Assert(!pSg || pSg->cSegs == 1);
3168
3169/* E1kLog2(("%s <<< Outgoing packet. Dump follows: >>>\n"
3170 "%.*Rhxd\n"
3171 "%s <<<<<<<<<<<<< End of dump >>>>>>>>>>>>\n",
3172 INSTANCE(pState), cbFrame, pSg->aSegs[0].pvSeg, INSTANCE(pState)));*/
3173
3174 if (cbFrame > 70) /* unqualified guess */
3175 pState->led.Asserted.s.fWriting = pState->led.Actual.s.fWriting = 1;
3176
3177 /* Update the stats */
3178 E1K_INC_CNT32(TPT);
3179 E1K_ADD_CNT64(TOTL, TOTH, cbFrame);
3180 E1K_INC_CNT32(GPTC);
3181 if (pSg && e1kIsBroadcast(pSg->aSegs[0].pvSeg))
3182 E1K_INC_CNT32(BPTC);
3183 else if (pSg && e1kIsMulticast(pSg->aSegs[0].pvSeg))
3184 E1K_INC_CNT32(MPTC);
3185 /* Update octet transmit counter */
3186 E1K_ADD_CNT64(GOTCL, GOTCH, cbFrame);
3187 if (pState->CTX_SUFF(pDrv))
3188 STAM_REL_COUNTER_ADD(&pState->StatTransmitBytes, cbFrame);
3189 if (cbFrame == 64)
3190 E1K_INC_CNT32(PTC64);
3191 else if (cbFrame < 128)
3192 E1K_INC_CNT32(PTC127);
3193 else if (cbFrame < 256)
3194 E1K_INC_CNT32(PTC255);
3195 else if (cbFrame < 512)
3196 E1K_INC_CNT32(PTC511);
3197 else if (cbFrame < 1024)
3198 E1K_INC_CNT32(PTC1023);
3199 else
3200 E1K_INC_CNT32(PTC1522);
3201
3202 E1K_INC_ISTAT_CNT(pState->uStatTxFrm);
3203
3204 /*
3205 * Dump and send the packet.
3206 */
3207 int rc = VERR_NET_DOWN;
3208 if (pSg && pSg->pvAllocator != pState)
3209 {
3210 e1kPacketDump(pState, (uint8_t const *)pSg->aSegs[0].pvSeg, cbFrame, "--> Outgoing");
3211
3212 pState->CTX_SUFF(pTxSg) = NULL;
3213 PPDMINETWORKUP pDrv = pState->CTX_SUFF(pDrv);
3214 if (pDrv)
3215 {
3216 /* Release critical section to avoid deadlock in CanReceive */
3217 //e1kCsLeave(pState);
3218 e1kMutexRelease(pState);
3219 STAM_PROFILE_START(&pState->CTX_SUFF_Z(StatTransmitSend), a);
3220 rc = pDrv->pfnSendBuf(pDrv, pSg, fOnWorkerThread);
3221 STAM_PROFILE_STOP(&pState->CTX_SUFF_Z(StatTransmitSend), a);
3222 e1kMutexAcquire(pState, VERR_SEM_BUSY, RT_SRC_POS);
3223 //e1kCsEnter(pState, RT_SRC_POS);
3224 }
3225 }
3226 else if (pSg)
3227 {
3228 Assert(pSg->aSegs[0].pvSeg == pState->aTxPacketFallback);
3229 e1kPacketDump(pState, (uint8_t const *)pSg->aSegs[0].pvSeg, cbFrame, "--> Loopback");
3230
3231 /** @todo do we actually need to check that we're in loopback mode here? */
3232 if (GET_BITS(RCTL, LBM) == RCTL_LBM_TCVR)
3233 {
3234 E1KRXDST status;
3235 RT_ZERO(status);
3236 status.fPIF = true;
3237 e1kHandleRxPacket(pState, pSg->aSegs[0].pvSeg, cbFrame, status);
3238 rc = VINF_SUCCESS;
3239 }
3240 e1kXmitFreeBuf(pState);
3241 }
3242 else
3243 rc = VERR_NET_DOWN;
3244 if (RT_FAILURE(rc))
3245 {
3246 E1kLogRel(("E1000: ERROR! pfnSend returned %Rrc\n", rc));
3247 /** @todo handle VERR_NET_DOWN and VERR_NET_NO_BUFFER_SPACE. Signal error ? */
3248 }
3249
3250 pState->led.Actual.s.fWriting = 0;
3251}
3252
3253/**
3254 * Compute and write internet checksum (e1kCSum16) at the specified offset.
3255 *
3256 * @param pState The device state structure.
3257 * @param pPkt Pointer to the packet.
3258 * @param u16PktLen Total length of the packet.
3259 * @param cso Offset in packet to write checksum at.
3260 * @param css Offset in packet to start computing
3261 * checksum from.
3262 * @param cse Offset in packet to stop computing
3263 * checksum at.
3264 * @thread E1000_TX
3265 */
3266static void e1kInsertChecksum(E1KSTATE* pState, uint8_t *pPkt, uint16_t u16PktLen, uint8_t cso, uint8_t css, uint16_t cse)
3267{
3268 if (cso > u16PktLen)
3269 {
3270 E1kLog2(("%s cso(%X) is greater than packet length(%X), checksum is not inserted\n",
3271 INSTANCE(pState), cso, u16PktLen));
3272 return;
3273 }
3274
3275 if (cse == 0)
3276 cse = u16PktLen - 1;
3277 uint16_t u16ChkSum = e1kCSum16(pPkt + css, cse - css + 1);
3278 E1kLog2(("%s Inserting csum: %04X at %02X, old value: %04X\n", INSTANCE(pState),
3279 u16ChkSum, cso, *(uint16_t*)(pPkt + cso)));
3280 *(uint16_t*)(pPkt + cso) = u16ChkSum;
3281}
3282
3283/**
3284 * Add a part of descriptor's buffer to transmit frame.
3285 *
3286 * @remarks data.u64BufAddr is used unconditionally for both data
3287 * and legacy descriptors since it is identical to
3288 * legacy.u64BufAddr.
3289 *
3290 * @param pState The device state structure.
3291 * @param pDesc Pointer to the descriptor to transmit.
3292 * @param u16Len Length of buffer to the end of segment.
3293 * @param fSend Force packet sending.
3294 * @param fOnWorkerThread Whether we're on a worker thread or an EMT.
3295 * @thread E1000_TX
3296 */
3297static void e1kFallbackAddSegment(E1KSTATE* pState, RTGCPHYS PhysAddr, uint16_t u16Len, bool fSend, bool fOnWorkerThread)
3298{
3299 /* TCP header being transmitted */
3300 struct E1kTcpHeader *pTcpHdr = (struct E1kTcpHeader *)
3301 (pState->aTxPacketFallback + pState->contextTSE.tu.u8CSS);
3302 /* IP header being transmitted */
3303 struct E1kIpHeader *pIpHdr = (struct E1kIpHeader *)
3304 (pState->aTxPacketFallback + pState->contextTSE.ip.u8CSS);
3305
3306 E1kLog3(("%s e1kFallbackAddSegment: Length=%x, remaining payload=%x, header=%x, send=%RTbool\n",
3307 INSTANCE(pState), u16Len, pState->u32PayRemain, pState->u16HdrRemain, fSend));
3308 Assert(pState->u32PayRemain + pState->u16HdrRemain > 0);
3309
3310 PDMDevHlpPhysRead(pState->CTX_SUFF(pDevIns), PhysAddr,
3311 pState->aTxPacketFallback + pState->u16TxPktLen, u16Len);
3312 E1kLog3(("%s Dump of the segment:\n"
3313 "%.*Rhxd\n"
3314 "%s --- End of dump ---\n",
3315 INSTANCE(pState), u16Len, pState->aTxPacketFallback + pState->u16TxPktLen, INSTANCE(pState)));
3316 pState->u16TxPktLen += u16Len;
3317 E1kLog3(("%s e1kFallbackAddSegment: pState->u16TxPktLen=%x\n",
3318 INSTANCE(pState), pState->u16TxPktLen));
3319 if (pState->u16HdrRemain > 0)
3320 {
3321 /* The header was not complete, check if it is now */
3322 if (u16Len >= pState->u16HdrRemain)
3323 {
3324 /* The rest is payload */
3325 u16Len -= pState->u16HdrRemain;
3326 pState->u16HdrRemain = 0;
3327 /* Save partial checksum and flags */
3328 pState->u32SavedCsum = pTcpHdr->chksum;
3329 pState->u16SavedFlags = pTcpHdr->hdrlen_flags;
3330 /* Clear FIN and PSH flags now and set them only in the last segment */
3331 pTcpHdr->hdrlen_flags &= ~htons(E1K_TCP_FIN | E1K_TCP_PSH);
3332 }
3333 else
3334 {
3335 /* Still not */
3336 pState->u16HdrRemain -= u16Len;
3337 E1kLog3(("%s e1kFallbackAddSegment: Header is still incomplete, 0x%x bytes remain.\n",
3338 INSTANCE(pState), pState->u16HdrRemain));
3339 return;
3340 }
3341 }
3342
3343 pState->u32PayRemain -= u16Len;
3344
3345 if (fSend)
3346 {
3347 /* Leave ethernet header intact */
3348 /* IP Total Length = payload + headers - ethernet header */
3349 pIpHdr->total_len = htons(pState->u16TxPktLen - pState->contextTSE.ip.u8CSS);
3350 E1kLog3(("%s e1kFallbackAddSegment: End of packet, pIpHdr->total_len=%x\n",
3351 INSTANCE(pState), ntohs(pIpHdr->total_len)));
3352 /* Update IP Checksum */
3353 pIpHdr->chksum = 0;
3354 e1kInsertChecksum(pState, pState->aTxPacketFallback, pState->u16TxPktLen,
3355 pState->contextTSE.ip.u8CSO,
3356 pState->contextTSE.ip.u8CSS,
3357 pState->contextTSE.ip.u16CSE);
3358
3359 /* Update TCP flags */
3360 /* Restore original FIN and PSH flags for the last segment */
3361 if (pState->u32PayRemain == 0)
3362 {
3363 pTcpHdr->hdrlen_flags = pState->u16SavedFlags;
3364 E1K_INC_CNT32(TSCTC);
3365 }
3366 /* Add TCP length to partial pseudo header sum */
3367 uint32_t csum = pState->u32SavedCsum
3368 + htons(pState->u16TxPktLen - pState->contextTSE.tu.u8CSS);
3369 while (csum >> 16)
3370 csum = (csum >> 16) + (csum & 0xFFFF);
3371 pTcpHdr->chksum = csum;
3372 /* Compute final checksum */
3373 e1kInsertChecksum(pState, pState->aTxPacketFallback, pState->u16TxPktLen,
3374 pState->contextTSE.tu.u8CSO,
3375 pState->contextTSE.tu.u8CSS,
3376 pState->contextTSE.tu.u16CSE);
3377
3378 /*
3379 * Transmit it. If we've use the SG already, allocate a new one before
3380 * we copy of the data.
3381 */
3382 if (!pState->CTX_SUFF(pTxSg))
3383 e1kXmitAllocBuf(pState, pState->u16TxPktLen, true /*fExactSize*/, false /*fGso*/);
3384 if (pState->CTX_SUFF(pTxSg))
3385 {
3386 Assert(pState->u16TxPktLen <= pState->CTX_SUFF(pTxSg)->cbAvailable);
3387 Assert(pState->CTX_SUFF(pTxSg)->cSegs == 1);
3388 if (pState->CTX_SUFF(pTxSg)->aSegs[0].pvSeg != pState->aTxPacketFallback)
3389 memcpy(pState->CTX_SUFF(pTxSg)->aSegs[0].pvSeg, pState->aTxPacketFallback, pState->u16TxPktLen);
3390 pState->CTX_SUFF(pTxSg)->cbUsed = pState->u16TxPktLen;
3391 pState->CTX_SUFF(pTxSg)->aSegs[0].cbSeg = pState->u16TxPktLen;
3392 }
3393 e1kTransmitFrame(pState, fOnWorkerThread);
3394
3395 /* Update Sequence Number */
3396 pTcpHdr->seqno = htonl(ntohl(pTcpHdr->seqno) + pState->u16TxPktLen
3397 - pState->contextTSE.dw3.u8HDRLEN);
3398 /* Increment IP identification */
3399 pIpHdr->ident = htons(ntohs(pIpHdr->ident) + 1);
3400 }
3401}
3402
3403/**
3404 * TCP segmentation offloading fallback: Add descriptor's buffer to transmit
3405 * frame.
3406 *
3407 * We construct the frame in the fallback buffer first and the copy it to the SG
3408 * buffer before passing it down to the network driver code.
3409 *
3410 * @returns true if the frame should be transmitted, false if not.
3411 *
3412 * @param pState The device state structure.
3413 * @param pDesc Pointer to the descriptor to transmit.
3414 * @param cbFragment Length of descriptor's buffer.
3415 * @param fOnWorkerThread Whether we're on a worker thread or an EMT.
3416 * @thread E1000_TX
3417 */
3418static bool e1kFallbackAddToFrame(E1KSTATE* pState, E1KTXDESC* pDesc, uint32_t cbFragment, bool fOnWorkerThread)
3419{
3420 PPDMSCATTERGATHER pTxSg = pState->CTX_SUFF(pTxSg);
3421 Assert(e1kGetDescType(pDesc) == E1K_DTYP_DATA);
3422 Assert(pDesc->data.cmd.fTSE);
3423 Assert(!e1kXmitIsGsoBuf(pTxSg));
3424
3425 uint16_t u16MaxPktLen = pState->contextTSE.dw3.u8HDRLEN + pState->contextTSE.dw3.u16MSS;
3426 Assert(u16MaxPktLen != 0);
3427 Assert(u16MaxPktLen < E1K_MAX_TX_PKT_SIZE);
3428
3429 /*
3430 * Carve out segments.
3431 */
3432 do
3433 {
3434 /* Calculate how many bytes we have left in this TCP segment */
3435 uint32_t cb = u16MaxPktLen - pState->u16TxPktLen;
3436 if (cb > cbFragment)
3437 {
3438 /* This descriptor fits completely into current segment */
3439 cb = cbFragment;
3440 e1kFallbackAddSegment(pState, pDesc->data.u64BufAddr, cb, pDesc->data.cmd.fEOP /*fSend*/, fOnWorkerThread);
3441 }
3442 else
3443 {
3444 e1kFallbackAddSegment(pState, pDesc->data.u64BufAddr, cb, true /*fSend*/, fOnWorkerThread);
3445 /*
3446 * Rewind the packet tail pointer to the beginning of payload,
3447 * so we continue writing right beyond the header.
3448 */
3449 pState->u16TxPktLen = pState->contextTSE.dw3.u8HDRLEN;
3450 }
3451
3452 pDesc->data.u64BufAddr += cb;
3453 cbFragment -= cb;
3454 } while (cbFragment > 0);
3455
3456 if (pDesc->data.cmd.fEOP)
3457 {
3458 /* End of packet, next segment will contain header. */
3459 if (pState->u32PayRemain != 0)
3460 E1K_INC_CNT32(TSCTFC);
3461 pState->u16TxPktLen = 0;
3462 e1kXmitFreeBuf(pState);
3463 }
3464
3465 return false;
3466}
3467
3468
3469/**
3470 * Add descriptor's buffer to transmit frame.
3471 *
3472 * This deals with GSO and normal frames, e1kFallbackAddToFrame deals with the
3473 * TSE frames we cannot handle as GSO.
3474 *
3475 * @returns true on success, false on failure.
3476 *
3477 * @param pThis The device state structure.
3478 * @param PhysAddr The physical address of the descriptor buffer.
3479 * @param cbFragment Length of descriptor's buffer.
3480 * @thread E1000_TX
3481 */
3482static bool e1kAddToFrame(E1KSTATE *pThis, RTGCPHYS PhysAddr, uint32_t cbFragment)
3483{
3484 PPDMSCATTERGATHER pTxSg = pThis->CTX_SUFF(pTxSg);
3485 bool const fGso = e1kXmitIsGsoBuf(pTxSg);
3486 uint32_t const cbNewPkt = cbFragment + pThis->u16TxPktLen;
3487
3488 if (RT_UNLIKELY( !fGso && cbNewPkt > E1K_MAX_TX_PKT_SIZE ))
3489 {
3490 E1kLog(("%s Transmit packet is too large: %u > %u(max)\n", INSTANCE(pThis), cbNewPkt, E1K_MAX_TX_PKT_SIZE));
3491 return false;
3492 }
3493 if (RT_UNLIKELY( fGso && cbNewPkt > pTxSg->cbAvailable ))
3494 {
3495 E1kLog(("%s Transmit packet is too large: %u > %u(max)/GSO\n", INSTANCE(pThis), cbNewPkt, pTxSg->cbAvailable));
3496 return false;
3497 }
3498
3499 if (RT_LIKELY(pTxSg))
3500 {
3501 Assert(pTxSg->cSegs == 1);
3502 Assert(pTxSg->cbUsed == pThis->u16TxPktLen);
3503
3504 PDMDevHlpPhysRead(pThis->CTX_SUFF(pDevIns), PhysAddr,
3505 (uint8_t *)pTxSg->aSegs[0].pvSeg + pThis->u16TxPktLen, cbFragment);
3506
3507 pTxSg->cbUsed = cbNewPkt;
3508 }
3509 pThis->u16TxPktLen = cbNewPkt;
3510
3511 return true;
3512}
3513
3514
3515/**
3516 * Write the descriptor back to guest memory and notify the guest.
3517 *
3518 * @param pState The device state structure.
3519 * @param pDesc Pointer to the descriptor have been transmitted.
3520 * @param addr Physical address of the descriptor in guest memory.
3521 * @thread E1000_TX
3522 */
3523static void e1kDescReport(E1KSTATE* pState, E1KTXDESC* pDesc, RTGCPHYS addr)
3524{
3525 /*
3526 * We fake descriptor write-back bursting. Descriptors are written back as they are
3527 * processed.
3528 */
3529 /* Let's pretend we process descriptors. Write back with DD set. */
3530 if (pDesc->legacy.cmd.fRS || (GET_BITS(TXDCTL, WTHRESH) > 0))
3531 {
3532 pDesc->legacy.dw3.fDD = 1; /* Descriptor Done */
3533 e1kWriteBackDesc(pState, pDesc, addr);
3534 if (pDesc->legacy.cmd.fEOP)
3535 {
3536#ifdef E1K_USE_TX_TIMERS
3537 if (pDesc->legacy.cmd.fIDE)
3538 {
3539 E1K_INC_ISTAT_CNT(pState->uStatTxIDE);
3540 //if (pState->fIntRaised)
3541 //{
3542 // /* Interrupt is already pending, no need for timers */
3543 // ICR |= ICR_TXDW;
3544 //}
3545 //else {
3546 /* Arm the timer to fire in TIVD usec (discard .024) */
3547 e1kArmTimer(pState, pState->CTX_SUFF(pTIDTimer), TIDV);
3548# ifndef E1K_NO_TAD
3549 /* If absolute timer delay is enabled and the timer is not running yet, arm it. */
3550 E1kLog2(("%s Checking if TAD timer is running\n",
3551 INSTANCE(pState)));
3552 if (TADV != 0 && !TMTimerIsActive(pState->CTX_SUFF(pTADTimer)))
3553 e1kArmTimer(pState, pState->CTX_SUFF(pTADTimer), TADV);
3554# endif /* E1K_NO_TAD */
3555 }
3556 else
3557 {
3558 E1kLog2(("%s No IDE set, cancel TAD timer and raise interrupt\n",
3559 INSTANCE(pState)));
3560# ifndef E1K_NO_TAD
3561 /* Cancel both timers if armed and fire immediately. */
3562 e1kCancelTimer(pState, pState->CTX_SUFF(pTADTimer));
3563# endif /* E1K_NO_TAD */
3564#endif /* E1K_USE_TX_TIMERS */
3565 E1K_INC_ISTAT_CNT(pState->uStatIntTx);
3566 e1kRaiseInterrupt(pState, VERR_SEM_BUSY, ICR_TXDW);
3567#ifdef E1K_USE_TX_TIMERS
3568 }
3569#endif /* E1K_USE_TX_TIMERS */
3570 }
3571 }
3572 else
3573 {
3574 E1K_INC_ISTAT_CNT(pState->uStatTxNoRS);
3575 }
3576}
3577
3578/**
3579 * Process Transmit Descriptor.
3580 *
3581 * E1000 supports three types of transmit descriptors:
3582 * - legacy data descriptors of older format (context-less).
3583 * - data the same as legacy but providing new offloading capabilities.
3584 * - context sets up the context for following data descriptors.
3585 *
3586 * @param pState The device state structure.
3587 * @param pDesc Pointer to descriptor union.
3588 * @param addr Physical address of descriptor in guest memory.
3589 * @param fOnWorkerThread Whether we're on a worker thread or an EMT.
3590 * @thread E1000_TX
3591 */
3592static void e1kXmitDesc(E1KSTATE* pState, E1KTXDESC* pDesc, RTGCPHYS addr, bool fOnWorkerThread)
3593{
3594 e1kPrintTDesc(pState, pDesc, "vvv");
3595
3596#ifdef E1K_USE_TX_TIMERS
3597 e1kCancelTimer(pState, pState->CTX_SUFF(pTIDTimer));
3598#endif /* E1K_USE_TX_TIMERS */
3599
3600 switch (e1kGetDescType(pDesc))
3601 {
3602 case E1K_DTYP_CONTEXT:
3603 if (pDesc->context.dw2.fTSE)
3604 {
3605 pState->contextTSE = pDesc->context;
3606 pState->u32PayRemain = pDesc->context.dw2.u20PAYLEN;
3607 pState->u16HdrRemain = pDesc->context.dw3.u8HDRLEN;
3608 e1kSetupGsoCtx(&pState->GsoCtx, &pDesc->context);
3609 STAM_COUNTER_INC(&pState->StatTxDescCtxTSE);
3610 }
3611 else
3612 {
3613 pState->contextNormal = pDesc->context;
3614 STAM_COUNTER_INC(&pState->StatTxDescCtxNormal);
3615 }
3616 E1kLog2(("%s %s context updated: IP CSS=%02X, IP CSO=%02X, IP CSE=%04X"
3617 ", TU CSS=%02X, TU CSO=%02X, TU CSE=%04X\n", INSTANCE(pState),
3618 pDesc->context.dw2.fTSE ? "TSE" : "Normal",
3619 pDesc->context.ip.u8CSS,
3620 pDesc->context.ip.u8CSO,
3621 pDesc->context.ip.u16CSE,
3622 pDesc->context.tu.u8CSS,
3623 pDesc->context.tu.u8CSO,
3624 pDesc->context.tu.u16CSE));
3625 E1K_INC_ISTAT_CNT(pState->uStatDescCtx);
3626 e1kDescReport(pState, pDesc, addr);
3627 break;
3628
3629 case E1K_DTYP_DATA:
3630 {
3631 if (pDesc->data.cmd.u20DTALEN == 0 || pDesc->data.u64BufAddr == 0)
3632 {
3633 E1kLog2(("% Empty data descriptor, skipped.\n", INSTANCE(pState)));
3634 /** @todo Same as legacy when !TSE. See below. */
3635 break;
3636 }
3637 STAM_COUNTER_INC(pDesc->data.cmd.fTSE?
3638 &pState->StatTxDescTSEData:
3639 &pState->StatTxDescData);
3640 STAM_PROFILE_ADV_START(&pState->CTX_SUFF_Z(StatTransmit), a);
3641 E1K_INC_ISTAT_CNT(pState->uStatDescDat);
3642
3643 /*
3644 * First fragment: Allocate new buffer and save the IXSM and TXSM
3645 * packet options as these are only valid in the first fragment.
3646 */
3647 if (pState->u16TxPktLen == 0)
3648 {
3649 pState->fIPcsum = pDesc->data.dw3.fIXSM;
3650 pState->fTCPcsum = pDesc->data.dw3.fTXSM;
3651 E1kLog2(("%s Saving checksum flags:%s%s; \n", INSTANCE(pState),
3652 pState->fIPcsum ? " IP" : "",
3653 pState->fTCPcsum ? " TCP/UDP" : ""));
3654 if (e1kCanDoGso(&pState->GsoCtx, &pDesc->data, &pState->contextTSE))
3655 e1kXmitAllocBuf(pState, pState->contextTSE.dw2.u20PAYLEN + pState->contextTSE.dw3.u8HDRLEN,
3656 true /*fExactSize*/, true /*fGso*/);
3657 else
3658 e1kXmitAllocBuf(pState, pState->contextTSE.dw3.u16MSS + pState->contextTSE.dw3.u8HDRLEN,
3659 pDesc->data.cmd.fTSE /*fExactSize*/, false /*fGso*/);
3660 /** @todo Is there any way to indicating errors other than collisions? Like
3661 * VERR_NET_DOWN. */
3662 }
3663
3664 /*
3665 * Add the descriptor data to the frame. If the frame is complete,
3666 * transmit it and reset the u16TxPktLen field.
3667 */
3668 if (e1kXmitIsGsoBuf(pState->CTX_SUFF(pTxSg)))
3669 {
3670 STAM_COUNTER_INC(&pState->StatTxPathGSO);
3671 bool fRc = e1kAddToFrame(pState, pDesc->data.u64BufAddr, pDesc->data.cmd.u20DTALEN);
3672 if (pDesc->data.cmd.fEOP)
3673 {
3674 if ( fRc
3675 && pState->CTX_SUFF(pTxSg)
3676 && pState->CTX_SUFF(pTxSg)->cbUsed == (size_t)pState->contextTSE.dw3.u8HDRLEN + pState->contextTSE.dw2.u20PAYLEN)
3677 {
3678 e1kTransmitFrame(pState, fOnWorkerThread);
3679 E1K_INC_CNT32(TSCTC);
3680 }
3681 else
3682 {
3683 if (fRc)
3684 E1kLog(("%s bad GSO/TSE %p or %u < %u\n" , INSTANCE(pState),
3685 pState->CTX_SUFF(pTxSg), pState->CTX_SUFF(pTxSg) ? pState->CTX_SUFF(pTxSg)->cbUsed : 0,
3686 pState->contextTSE.dw3.u8HDRLEN + pState->contextTSE.dw2.u20PAYLEN));
3687 e1kXmitFreeBuf(pState);
3688 E1K_INC_CNT32(TSCTFC);
3689 }
3690 pState->u16TxPktLen = 0;
3691 }
3692 }
3693 else if (!pDesc->data.cmd.fTSE)
3694 {
3695 STAM_COUNTER_INC(&pState->StatTxPathRegular);
3696 bool fRc = e1kAddToFrame(pState, pDesc->data.u64BufAddr, pDesc->data.cmd.u20DTALEN);
3697 if (pDesc->data.cmd.fEOP)
3698 {
3699 if (fRc && pState->CTX_SUFF(pTxSg))
3700 {
3701 Assert(pState->CTX_SUFF(pTxSg)->cSegs == 1);
3702 if (pState->fIPcsum)
3703 e1kInsertChecksum(pState, (uint8_t *)pState->CTX_SUFF(pTxSg)->aSegs[0].pvSeg, pState->u16TxPktLen,
3704 pState->contextNormal.ip.u8CSO,
3705 pState->contextNormal.ip.u8CSS,
3706 pState->contextNormal.ip.u16CSE);
3707 if (pState->fTCPcsum)
3708 e1kInsertChecksum(pState, (uint8_t *)pState->CTX_SUFF(pTxSg)->aSegs[0].pvSeg, pState->u16TxPktLen,
3709 pState->contextNormal.tu.u8CSO,
3710 pState->contextNormal.tu.u8CSS,
3711 pState->contextNormal.tu.u16CSE);
3712 e1kTransmitFrame(pState, fOnWorkerThread);
3713 }
3714 else
3715 e1kXmitFreeBuf(pState);
3716 pState->u16TxPktLen = 0;
3717 }
3718 }
3719 else
3720 {
3721 STAM_COUNTER_INC(&pState->StatTxPathFallback);
3722 e1kFallbackAddToFrame(pState, pDesc, pDesc->data.cmd.u20DTALEN, fOnWorkerThread);
3723 }
3724
3725 e1kDescReport(pState, pDesc, addr);
3726 STAM_PROFILE_ADV_STOP(&pState->CTX_SUFF_Z(StatTransmit), a);
3727 break;
3728 }
3729
3730 case E1K_DTYP_LEGACY:
3731 if (pDesc->legacy.cmd.u16Length == 0 || pDesc->legacy.u64BufAddr == 0)
3732 {
3733 E1kLog(("%s Empty legacy descriptor, skipped.\n", INSTANCE(pState)));
3734 /** @todo 3.3.3, Length/Buffer Address: RS set -> write DD when processing. */
3735 break;
3736 }
3737 STAM_COUNTER_INC(&pState->StatTxDescLegacy);
3738 STAM_PROFILE_ADV_START(&pState->CTX_SUFF_Z(StatTransmit), a);
3739
3740 /* First fragment: allocate new buffer. */
3741 if (pState->u16TxPktLen == 0)
3742 /** @todo reset status bits? */
3743 e1kXmitAllocBuf(pState, pDesc->legacy.cmd.u16Length, pDesc->legacy.cmd.fEOP, false /*fGso*/);
3744 /** @todo Is there any way to indicating errors other than collisions? Like
3745 * VERR_NET_DOWN. */
3746
3747 /* Add fragment to frame. */
3748 if (e1kAddToFrame(pState, pDesc->data.u64BufAddr, pDesc->legacy.cmd.u16Length))
3749 {
3750 E1K_INC_ISTAT_CNT(pState->uStatDescLeg);
3751
3752 /* Last fragment: Transmit and reset the packet storage counter. */
3753 if (pDesc->legacy.cmd.fEOP)
3754 {
3755 /** @todo Offload processing goes here. */
3756 e1kTransmitFrame(pState, fOnWorkerThread);
3757 pState->u16TxPktLen = 0;
3758 }
3759 }
3760 /* Last fragment + failure: free the buffer and reset the storage counter. */
3761 else if (pDesc->legacy.cmd.fEOP)
3762 {
3763 e1kXmitFreeBuf(pState);
3764 pState->u16TxPktLen = 0;
3765 }
3766
3767 e1kDescReport(pState, pDesc, addr);
3768 STAM_PROFILE_ADV_STOP(&pState->CTX_SUFF_Z(StatTransmit), a);
3769 break;
3770
3771 default:
3772 E1kLog(("%s ERROR Unsupported transmit descriptor type: 0x%04x\n",
3773 INSTANCE(pState), e1kGetDescType(pDesc)));
3774 break;
3775 }
3776}
3777
3778
3779/**
3780 * Transmit pending descriptors.
3781 *
3782 * @returns VBox status code. VERR_TRY_AGAIN is returned if we're busy.
3783 *
3784 * @param pState The E1000 state.
3785 * @param fOnWorkerThread Whether we're on a worker thread or on an EMT.
3786 */
3787static int e1kXmitPending(E1KSTATE *pState, bool fOnWorkerThread)
3788{
3789 int rc;
3790
3791 /*
3792 * Grab the xmit lock of the driver as well as the E1K device state.
3793 */
3794 PPDMINETWORKUP pDrv = pState->CTX_SUFF(pDrv);
3795 if (pDrv)
3796 {
3797 rc = pDrv->pfnBeginXmit(pDrv, fOnWorkerThread);
3798 if (RT_FAILURE(rc))
3799 return rc;
3800 }
3801 rc = e1kMutexAcquire(pState, VERR_TRY_AGAIN, RT_SRC_POS);
3802 if (RT_SUCCESS(rc))
3803 {
3804 /*
3805 * Process all pending descriptors.
3806 * Note! Do not process descriptors in locked state
3807 */
3808 while (TDH != TDT && !pState->fLocked)
3809 {
3810 E1KTXDESC desc;
3811 E1kLog3(("%s About to process new TX descriptor at %08x%08x, TDLEN=%08x, TDH=%08x, TDT=%08x\n",
3812 INSTANCE(pState), TDBAH, TDBAL + TDH * sizeof(desc), TDLEN, TDH, TDT));
3813
3814 e1kLoadDesc(pState, &desc, ((uint64_t)TDBAH << 32) + TDBAL + TDH * sizeof(desc));
3815 e1kXmitDesc(pState, &desc, ((uint64_t)TDBAH << 32) + TDBAL + TDH * sizeof(desc), fOnWorkerThread);
3816 if (++TDH * sizeof(desc) >= TDLEN)
3817 TDH = 0;
3818
3819 if (e1kGetTxLen(pState) <= GET_BITS(TXDCTL, LWTHRESH)*8)
3820 {
3821 E1kLog2(("%s Low on transmit descriptors, raise ICR.TXD_LOW, len=%x thresh=%x\n",
3822 INSTANCE(pState), e1kGetTxLen(pState), GET_BITS(TXDCTL, LWTHRESH)*8));
3823 e1kRaiseInterrupt(pState, VERR_SEM_BUSY, ICR_TXD_LOW);
3824 }
3825
3826 STAM_PROFILE_ADV_STOP(&pState->CTX_SUFF_Z(StatTransmit), a);
3827 }
3828
3829 /// @todo: uncomment: pState->uStatIntTXQE++;
3830 /// @todo: uncomment: e1kRaiseInterrupt(pState, ICR_TXQE);
3831
3832 /*
3833 * Release the locks.
3834 */
3835 e1kMutexRelease(pState);
3836 }
3837 if (pDrv)
3838 pDrv->pfnEndXmit(pDrv);
3839 return rc;
3840}
3841
3842#ifdef IN_RING3
3843
3844/**
3845 * @interface_method_impl{PDMINETWORKDOWN,pfnXmitPending}
3846 */
3847static DECLCALLBACK(void) e1kNetworkDown_XmitPending(PPDMINETWORKDOWN pInterface)
3848{
3849 E1KSTATE *pState = RT_FROM_MEMBER(pInterface, E1KSTATE, INetworkDown);
3850 e1kXmitPending(pState, true /*fOnWorkerThread*/);
3851}
3852
3853/**
3854 * Callback for consuming from transmit queue. It gets called in R3 whenever
3855 * we enqueue something in R0/GC.
3856 *
3857 * @returns true
3858 * @param pDevIns Pointer to device instance structure.
3859 * @param pItem Pointer to the element being dequeued (not used).
3860 * @thread ???
3861 */
3862static DECLCALLBACK(bool) e1kTxQueueConsumer(PPDMDEVINS pDevIns, PPDMQUEUEITEMCORE pItem)
3863{
3864 NOREF(pItem);
3865 E1KSTATE *pState = PDMINS_2_DATA(pDevIns, E1KSTATE *);
3866 E1kLog2(("%s e1kTxQueueConsumer:\n", INSTANCE(pState)));
3867
3868 int rc = e1kXmitPending(pState, false /*fOnWorkerThread*/);
3869 AssertMsg(RT_SUCCESS(rc) || rc == VERR_TRY_AGAIN, ("%Rrc\n", rc));
3870
3871 return true;
3872}
3873
3874/**
3875 * Handler for the wakeup signaller queue.
3876 */
3877static DECLCALLBACK(bool) e1kCanRxQueueConsumer(PPDMDEVINS pDevIns, PPDMQUEUEITEMCORE pItem)
3878{
3879 e1kWakeupReceive(pDevIns);
3880 return true;
3881}
3882
3883#endif /* IN_RING3 */
3884
3885/**
3886 * Write handler for Transmit Descriptor Tail register.
3887 *
3888 * @param pState The device state structure.
3889 * @param offset Register offset in memory-mapped frame.
3890 * @param index Register index in register array.
3891 * @param value The value to store.
3892 * @param mask Used to implement partial writes (8 and 16-bit).
3893 * @thread EMT
3894 */
3895static int e1kRegWriteTDT(E1KSTATE* pState, uint32_t offset, uint32_t index, uint32_t value)
3896{
3897 int rc = e1kCsTxEnter(pState, VINF_IOM_HC_MMIO_WRITE);
3898 if (RT_UNLIKELY(rc != VINF_SUCCESS))
3899 return rc;
3900 rc = e1kRegWriteDefault(pState, offset, index, value);
3901
3902 /* All descriptors starting with head and not including tail belong to us. */
3903 /* Process them. */
3904 E1kLog2(("%s e1kRegWriteTDT: TDBAL=%08x, TDBAH=%08x, TDLEN=%08x, TDH=%08x, TDT=%08x\n",
3905 INSTANCE(pState), TDBAL, TDBAH, TDLEN, TDH, TDT));
3906
3907 /* Ignore TDT writes when the link is down. */
3908 if (TDH != TDT && (STATUS & STATUS_LU))
3909 {
3910 E1kLogRel(("E1000: TDT write: %d descriptors to process\n", e1kGetTxLen(pState)));
3911 E1kLog(("%s e1kRegWriteTDT: %d descriptors to process, waking up E1000_TX thread\n",
3912 INSTANCE(pState), e1kGetTxLen(pState)));
3913 e1kCsTxLeave(pState);
3914
3915 /* Transmit pending packets if possible, defer it if we cannot do it
3916 in the current context. */
3917# ifndef IN_RING3
3918 if (!pState->CTX_SUFF(pDrv))
3919 {
3920 PPDMQUEUEITEMCORE pItem = PDMQueueAlloc(pState->CTX_SUFF(pTxQueue));
3921 if (RT_UNLIKELY(pItem))
3922 PDMQueueInsert(pState->CTX_SUFF(pTxQueue), pItem);
3923 }
3924 else
3925# endif
3926 {
3927 rc = e1kXmitPending(pState, false /*fOnWorkerThread*/);
3928 if (rc == VERR_TRY_AGAIN)
3929 rc = VINF_SUCCESS;
3930 AssertRC(rc);
3931 }
3932 }
3933 else
3934 e1kCsTxLeave(pState);
3935
3936 return rc;
3937}
3938
3939/**
3940 * Write handler for Multicast Table Array registers.
3941 *
3942 * @param pState The device state structure.
3943 * @param offset Register offset in memory-mapped frame.
3944 * @param index Register index in register array.
3945 * @param value The value to store.
3946 * @thread EMT
3947 */
3948static int e1kRegWriteMTA(E1KSTATE* pState, uint32_t offset, uint32_t index, uint32_t value)
3949{
3950 AssertReturn(offset - s_e1kRegMap[index].offset < sizeof(pState->auMTA), VERR_DEV_IO_ERROR);
3951 pState->auMTA[(offset - s_e1kRegMap[index].offset)/sizeof(pState->auMTA[0])] = value;
3952
3953 return VINF_SUCCESS;
3954}
3955
3956/**
3957 * Read handler for Multicast Table Array registers.
3958 *
3959 * @returns VBox status code.
3960 *
3961 * @param pState The device state structure.
3962 * @param offset Register offset in memory-mapped frame.
3963 * @param index Register index in register array.
3964 * @thread EMT
3965 */
3966static int e1kRegReadMTA(E1KSTATE* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value)
3967{
3968 AssertReturn(offset - s_e1kRegMap[index].offset< sizeof(pState->auMTA), VERR_DEV_IO_ERROR);
3969 *pu32Value = pState->auMTA[(offset - s_e1kRegMap[index].offset)/sizeof(pState->auMTA[0])];
3970
3971 return VINF_SUCCESS;
3972}
3973
3974/**
3975 * Write handler for Receive Address registers.
3976 *
3977 * @param pState The device state structure.
3978 * @param offset Register offset in memory-mapped frame.
3979 * @param index Register index in register array.
3980 * @param value The value to store.
3981 * @thread EMT
3982 */
3983static int e1kRegWriteRA(E1KSTATE* pState, uint32_t offset, uint32_t index, uint32_t value)
3984{
3985 AssertReturn(offset - s_e1kRegMap[index].offset < sizeof(pState->aRecAddr.au32), VERR_DEV_IO_ERROR);
3986 pState->aRecAddr.au32[(offset - s_e1kRegMap[index].offset)/sizeof(pState->aRecAddr.au32[0])] = value;
3987
3988 return VINF_SUCCESS;
3989}
3990
3991/**
3992 * Read handler for Receive Address registers.
3993 *
3994 * @returns VBox status code.
3995 *
3996 * @param pState The device state structure.
3997 * @param offset Register offset in memory-mapped frame.
3998 * @param index Register index in register array.
3999 * @thread EMT
4000 */
4001static int e1kRegReadRA(E1KSTATE* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value)
4002{
4003 AssertReturn(offset - s_e1kRegMap[index].offset< sizeof(pState->aRecAddr.au32), VERR_DEV_IO_ERROR);
4004 *pu32Value = pState->aRecAddr.au32[(offset - s_e1kRegMap[index].offset)/sizeof(pState->aRecAddr.au32[0])];
4005
4006 return VINF_SUCCESS;
4007}
4008
4009/**
4010 * Write handler for VLAN Filter Table Array registers.
4011 *
4012 * @param pState The device state structure.
4013 * @param offset Register offset in memory-mapped frame.
4014 * @param index Register index in register array.
4015 * @param value The value to store.
4016 * @thread EMT
4017 */
4018static int e1kRegWriteVFTA(E1KSTATE* pState, uint32_t offset, uint32_t index, uint32_t value)
4019{
4020 AssertReturn(offset - s_e1kRegMap[index].offset < sizeof(pState->auVFTA), VINF_SUCCESS);
4021 pState->auVFTA[(offset - s_e1kRegMap[index].offset)/sizeof(pState->auVFTA[0])] = value;
4022
4023 return VINF_SUCCESS;
4024}
4025
4026/**
4027 * Read handler for VLAN Filter Table Array registers.
4028 *
4029 * @returns VBox status code.
4030 *
4031 * @param pState The device state structure.
4032 * @param offset Register offset in memory-mapped frame.
4033 * @param index Register index in register array.
4034 * @thread EMT
4035 */
4036static int e1kRegReadVFTA(E1KSTATE* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value)
4037{
4038 AssertReturn(offset - s_e1kRegMap[index].offset< sizeof(pState->auVFTA), VERR_DEV_IO_ERROR);
4039 *pu32Value = pState->auVFTA[(offset - s_e1kRegMap[index].offset)/sizeof(pState->auVFTA[0])];
4040
4041 return VINF_SUCCESS;
4042}
4043
4044/**
4045 * Read handler for unimplemented registers.
4046 *
4047 * Merely reports reads from unimplemented registers.
4048 *
4049 * @returns VBox status code.
4050 *
4051 * @param pState The device state structure.
4052 * @param offset Register offset in memory-mapped frame.
4053 * @param index Register index in register array.
4054 * @thread EMT
4055 */
4056
4057static int e1kRegReadUnimplemented(E1KSTATE* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value)
4058{
4059 E1kLog(("%s At %08X read (00000000) attempt from unimplemented register %s (%s)\n",
4060 INSTANCE(pState), offset, s_e1kRegMap[index].abbrev, s_e1kRegMap[index].name));
4061 *pu32Value = 0;
4062
4063 return VINF_SUCCESS;
4064}
4065
4066/**
4067 * Default register read handler with automatic clear operation.
4068 *
4069 * Retrieves the value of register from register array in device state structure.
4070 * Then resets all bits.
4071 *
4072 * @remarks The 'mask' parameter is simply ignored as masking and shifting is
4073 * done in the caller.
4074 *
4075 * @returns VBox status code.
4076 *
4077 * @param pState The device state structure.
4078 * @param offset Register offset in memory-mapped frame.
4079 * @param index Register index in register array.
4080 * @thread EMT
4081 */
4082
4083static int e1kRegReadAutoClear(E1KSTATE* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value)
4084{
4085 AssertReturn(index < E1K_NUM_OF_32BIT_REGS, VERR_DEV_IO_ERROR);
4086 int rc = e1kRegReadDefault(pState, offset, index, pu32Value);
4087 pState->auRegs[index] = 0;
4088
4089 return rc;
4090}
4091
4092/**
4093 * Default register read handler.
4094 *
4095 * Retrieves the value of register from register array in device state structure.
4096 * Bits corresponding to 0s in 'readable' mask will always read as 0s.
4097 *
4098 * @remarks The 'mask' parameter is simply ignored as masking and shifting is
4099 * done in the caller.
4100 *
4101 * @returns VBox status code.
4102 *
4103 * @param pState The device state structure.
4104 * @param offset Register offset in memory-mapped frame.
4105 * @param index Register index in register array.
4106 * @thread EMT
4107 */
4108
4109static int e1kRegReadDefault(E1KSTATE* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value)
4110{
4111 AssertReturn(index < E1K_NUM_OF_32BIT_REGS, VERR_DEV_IO_ERROR);
4112 *pu32Value = pState->auRegs[index] & s_e1kRegMap[index].readable;
4113
4114 return VINF_SUCCESS;
4115}
4116
4117/**
4118 * Write handler for unimplemented registers.
4119 *
4120 * Merely reports writes to unimplemented registers.
4121 *
4122 * @param pState The device state structure.
4123 * @param offset Register offset in memory-mapped frame.
4124 * @param index Register index in register array.
4125 * @param value The value to store.
4126 * @thread EMT
4127 */
4128
4129 static int e1kRegWriteUnimplemented(E1KSTATE* pState, uint32_t offset, uint32_t index, uint32_t value)
4130{
4131 E1kLog(("%s At %08X write attempt (%08X) to unimplemented register %s (%s)\n",
4132 INSTANCE(pState), offset, value, s_e1kRegMap[index].abbrev, s_e1kRegMap[index].name));
4133
4134 return VINF_SUCCESS;
4135}
4136
4137/**
4138 * Default register write handler.
4139 *
4140 * Stores the value to the register array in device state structure. Only bits
4141 * corresponding to 1s both in 'writable' and 'mask' will be stored.
4142 *
4143 * @returns VBox status code.
4144 *
4145 * @param pState The device state structure.
4146 * @param offset Register offset in memory-mapped frame.
4147 * @param index Register index in register array.
4148 * @param value The value to store.
4149 * @param mask Used to implement partial writes (8 and 16-bit).
4150 * @thread EMT
4151 */
4152
4153static int e1kRegWriteDefault(E1KSTATE* pState, uint32_t offset, uint32_t index, uint32_t value)
4154{
4155 AssertReturn(index < E1K_NUM_OF_32BIT_REGS, VERR_DEV_IO_ERROR);
4156 pState->auRegs[index] = (value & s_e1kRegMap[index].writable) |
4157 (pState->auRegs[index] & ~s_e1kRegMap[index].writable);
4158
4159 return VINF_SUCCESS;
4160}
4161
4162/**
4163 * Search register table for matching register.
4164 *
4165 * @returns Index in the register table or -1 if not found.
4166 *
4167 * @param pState The device state structure.
4168 * @param uOffset Register offset in memory-mapped region.
4169 * @thread EMT
4170 */
4171static int e1kRegLookup(E1KSTATE *pState, uint32_t uOffset)
4172{
4173 int index;
4174
4175 for (index = 0; index < E1K_NUM_OF_REGS; index++)
4176 {
4177 if (s_e1kRegMap[index].offset <= uOffset && uOffset < s_e1kRegMap[index].offset + s_e1kRegMap[index].size)
4178 {
4179 return index;
4180 }
4181 }
4182
4183 return -1;
4184}
4185
4186/**
4187 * Handle register read operation.
4188 *
4189 * Looks up and calls appropriate handler.
4190 *
4191 * @returns VBox status code.
4192 *
4193 * @param pState The device state structure.
4194 * @param uOffset Register offset in memory-mapped frame.
4195 * @param pv Where to store the result.
4196 * @param cb Number of bytes to read.
4197 * @thread EMT
4198 */
4199static int e1kRegRead(E1KSTATE *pState, uint32_t uOffset, void *pv, uint32_t cb)
4200{
4201 uint32_t u32 = 0;
4202 uint32_t mask = 0;
4203 uint32_t shift;
4204 int rc = VINF_SUCCESS;
4205 int index = e1kRegLookup(pState, uOffset);
4206 const char *szInst = INSTANCE(pState);
4207#ifdef DEBUG
4208 char buf[9];
4209#endif
4210
4211 /*
4212 * From the spec:
4213 * For registers that should be accessed as 32-bit double words, partial writes (less than a 32-bit
4214 * double word) is ignored. Partial reads return all 32 bits of data regardless of the byte enables.
4215 */
4216
4217 /*
4218 * To be able to write bytes and short word we convert them
4219 * to properly shifted 32-bit words and masks. The idea is
4220 * to keep register-specific handlers simple. Most accesses
4221 * will be 32-bit anyway.
4222 */
4223 switch (cb)
4224 {
4225 case 1: mask = 0x000000FF; break;
4226 case 2: mask = 0x0000FFFF; break;
4227 case 4: mask = 0xFFFFFFFF; break;
4228 default:
4229 return PDMDevHlpDBGFStop(pState->CTX_SUFF(pDevIns), RT_SRC_POS,
4230 "%s e1kRegRead: unsupported op size: offset=%#10x cb=%#10x\n",
4231 szInst, uOffset, cb);
4232 }
4233 if (index != -1)
4234 {
4235 if (s_e1kRegMap[index].readable)
4236 {
4237 /* Make the mask correspond to the bits we are about to read. */
4238 shift = (uOffset - s_e1kRegMap[index].offset) % sizeof(uint32_t) * 8;
4239 mask <<= shift;
4240 if (!mask)
4241 return PDMDevHlpDBGFStop(pState->CTX_SUFF(pDevIns), RT_SRC_POS,
4242 "%s e1kRegRead: Zero mask: offset=%#10x cb=%#10x\n",
4243 szInst, uOffset, cb);
4244 /*
4245 * Read it. Pass the mask so the handler knows what has to be read.
4246 * Mask out irrelevant bits.
4247 */
4248#ifdef E1K_GLOBAL_MUTEX
4249 rc = e1kMutexAcquire(pState, VINF_IOM_HC_MMIO_READ, RT_SRC_POS);
4250#else
4251 //rc = e1kCsEnter(pState, VERR_SEM_BUSY, RT_SRC_POS);
4252#endif
4253 if (RT_UNLIKELY(rc != VINF_SUCCESS))
4254 return rc;
4255 //pState->fDelayInts = false;
4256 //pState->iStatIntLost += pState->iStatIntLostOne;
4257 //pState->iStatIntLostOne = 0;
4258 rc = s_e1kRegMap[index].pfnRead(pState, uOffset & 0xFFFFFFFC, index, &u32) & mask;
4259 //e1kCsLeave(pState);
4260 e1kMutexRelease(pState);
4261 E1kLog2(("%s At %08X read %s from %s (%s)\n",
4262 szInst, uOffset, e1kU32toHex(u32, mask, buf), s_e1kRegMap[index].abbrev, s_e1kRegMap[index].name));
4263 /* Shift back the result. */
4264 u32 >>= shift;
4265 }
4266 else
4267 {
4268 E1kLog(("%s At %08X read (%s) attempt from write-only register %s (%s)\n",
4269 szInst, uOffset, e1kU32toHex(u32, mask, buf), s_e1kRegMap[index].abbrev, s_e1kRegMap[index].name));
4270 }
4271 }
4272 else
4273 {
4274 E1kLog(("%s At %08X read (%s) attempt from non-existing register\n",
4275 szInst, uOffset, e1kU32toHex(u32, mask, buf)));
4276 }
4277
4278 memcpy(pv, &u32, cb);
4279 return rc;
4280}
4281
4282/**
4283 * Handle register write operation.
4284 *
4285 * Looks up and calls appropriate handler.
4286 *
4287 * @returns VBox status code.
4288 *
4289 * @param pState The device state structure.
4290 * @param uOffset Register offset in memory-mapped frame.
4291 * @param pv Where to fetch the value.
4292 * @param cb Number of bytes to write.
4293 * @thread EMT
4294 */
4295static int e1kRegWrite(E1KSTATE *pState, uint32_t uOffset, void *pv, unsigned cb)
4296{
4297 int rc = VINF_SUCCESS;
4298 int index = e1kRegLookup(pState, uOffset);
4299 uint32_t u32;
4300
4301 /*
4302 * From the spec:
4303 * For registers that should be accessed as 32-bit double words, partial writes (less than a 32-bit
4304 * double word) is ignored. Partial reads return all 32 bits of data regardless of the byte enables.
4305 */
4306
4307 if (cb != 4)
4308 {
4309 E1kLog(("%s e1kRegWrite: Spec violation: unsupported op size: offset=%#10x cb=%#10x, ignored.\n",
4310 INSTANCE(pState), uOffset, cb));
4311 return VINF_SUCCESS;
4312 }
4313 if (uOffset & 3)
4314 {
4315 E1kLog(("%s e1kRegWrite: Spec violation: misaligned offset: %#10x cb=%#10x, ignored.\n",
4316 INSTANCE(pState), uOffset, cb));
4317 return VINF_SUCCESS;
4318 }
4319 u32 = *(uint32_t*)pv;
4320 if (index != -1)
4321 {
4322 if (s_e1kRegMap[index].writable)
4323 {
4324 /*
4325 * Write it. Pass the mask so the handler knows what has to be written.
4326 * Mask out irrelevant bits.
4327 */
4328 E1kLog2(("%s At %08X write %08X to %s (%s)\n",
4329 INSTANCE(pState), uOffset, u32, s_e1kRegMap[index].abbrev, s_e1kRegMap[index].name));
4330#ifdef E1K_GLOBAL_MUTEX
4331 rc = e1kMutexAcquire(pState, VINF_IOM_HC_MMIO_WRITE, RT_SRC_POS);
4332#else
4333 //rc = e1kCsEnter(pState, VERR_SEM_BUSY, RT_SRC_POS);
4334#endif
4335 if (RT_UNLIKELY(rc != VINF_SUCCESS))
4336 return rc;
4337 //pState->fDelayInts = false;
4338 //pState->iStatIntLost += pState->iStatIntLostOne;
4339 //pState->iStatIntLostOne = 0;
4340 rc = s_e1kRegMap[index].pfnWrite(pState, uOffset, index, u32);
4341 //e1kCsLeave(pState);
4342 e1kMutexRelease(pState);
4343 }
4344 else
4345 {
4346 E1kLog(("%s At %08X write attempt (%08X) to read-only register %s (%s)\n",
4347 INSTANCE(pState), uOffset, u32, s_e1kRegMap[index].abbrev, s_e1kRegMap[index].name));
4348 }
4349 }
4350 else
4351 {
4352 E1kLog(("%s At %08X write attempt (%08X) to non-existing register\n",
4353 INSTANCE(pState), uOffset, u32));
4354 }
4355 return rc;
4356}
4357
4358/**
4359 * I/O handler for memory-mapped read operations.
4360 *
4361 * @returns VBox status code.
4362 *
4363 * @param pDevIns The device instance.
4364 * @param pvUser User argument.
4365 * @param GCPhysAddr Physical address (in GC) where the read starts.
4366 * @param pv Where to store the result.
4367 * @param cb Number of bytes read.
4368 * @thread EMT
4369 */
4370PDMBOTHCBDECL(int) e1kMMIORead(PPDMDEVINS pDevIns, void *pvUser,
4371 RTGCPHYS GCPhysAddr, void *pv, unsigned cb)
4372{
4373 NOREF(pvUser);
4374 E1KSTATE *pState = PDMINS_2_DATA(pDevIns, E1KSTATE *);
4375 uint32_t uOffset = GCPhysAddr - pState->addrMMReg;
4376 STAM_PROFILE_ADV_START(&pState->CTX_SUFF_Z(StatMMIORead), a);
4377
4378 Assert(uOffset < E1K_MM_SIZE);
4379
4380 int rc = e1kRegRead(pState, uOffset, pv, cb);
4381 STAM_PROFILE_ADV_STOP(&pState->CTX_SUFF_Z(StatMMIORead), a);
4382 return rc;
4383}
4384
4385/**
4386 * Memory mapped I/O Handler for write operations.
4387 *
4388 * @returns VBox status code.
4389 *
4390 * @param pDevIns The device instance.
4391 * @param pvUser User argument.
4392 * @param GCPhysAddr Physical address (in GC) where the read starts.
4393 * @param pv Where to fetch the value.
4394 * @param cb Number of bytes to write.
4395 * @thread EMT
4396 */
4397PDMBOTHCBDECL(int) e1kMMIOWrite(PPDMDEVINS pDevIns, void *pvUser,
4398 RTGCPHYS GCPhysAddr, void *pv, unsigned cb)
4399{
4400 NOREF(pvUser);
4401 E1KSTATE *pState = PDMINS_2_DATA(pDevIns, E1KSTATE *);
4402 uint32_t uOffset = GCPhysAddr - pState->addrMMReg;
4403 int rc;
4404 STAM_PROFILE_ADV_START(&pState->CTX_SUFF_Z(StatMMIOWrite), a);
4405
4406 Assert(uOffset < E1K_MM_SIZE);
4407 if (cb != 4)
4408 {
4409 E1kLog(("%s e1kMMIOWrite: invalid op size: offset=%#10x cb=%#10x", pDevIns, uOffset, cb));
4410 rc = PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "e1kMMIOWrite: invalid op size: offset=%#10x cb=%#10x\n", uOffset, cb);
4411 }
4412 else
4413 rc = e1kRegWrite(pState, uOffset, pv, cb);
4414
4415 STAM_PROFILE_ADV_STOP(&pState->CTX_SUFF_Z(StatMMIOWrite), a);
4416 return rc;
4417}
4418
4419/**
4420 * Port I/O Handler for IN operations.
4421 *
4422 * @returns VBox status code.
4423 *
4424 * @param pDevIns The device instance.
4425 * @param pvUser Pointer to the device state structure.
4426 * @param port Port number used for the IN operation.
4427 * @param pu32 Where to store the result.
4428 * @param cb Number of bytes read.
4429 * @thread EMT
4430 */
4431PDMBOTHCBDECL(int) e1kIOPortIn(PPDMDEVINS pDevIns, void *pvUser,
4432 RTIOPORT port, uint32_t *pu32, unsigned cb)
4433{
4434 E1KSTATE *pState = PDMINS_2_DATA(pDevIns, E1KSTATE *);
4435 int rc = VINF_SUCCESS;
4436 const char *szInst = INSTANCE(pState);
4437 STAM_PROFILE_ADV_START(&pState->CTX_SUFF_Z(StatIORead), a);
4438
4439 port -= pState->addrIOPort;
4440 if (cb != 4)
4441 {
4442 E1kLog(("%s e1kIOPortIn: invalid op size: port=%RTiop cb=%08x", szInst, port, cb));
4443 rc = PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "%s e1kIOPortIn: invalid op size: port=%RTiop cb=%08x\n", szInst, port, cb);
4444 }
4445 else
4446 switch (port)
4447 {
4448 case 0x00: /* IOADDR */
4449 *pu32 = pState->uSelectedReg;
4450 E1kLog2(("%s e1kIOPortIn: IOADDR(0), selecting register %#010x, val=%#010x\n", szInst, pState->uSelectedReg, *pu32));
4451 break;
4452 case 0x04: /* IODATA */
4453 rc = e1kRegRead(pState, pState->uSelectedReg, pu32, cb);
4454 /** @todo wrong return code triggers assertions in the debug build; fix please */
4455 if (rc == VINF_IOM_HC_MMIO_READ)
4456 rc = VINF_IOM_HC_IOPORT_READ;
4457
4458 E1kLog2(("%s e1kIOPortIn: IODATA(4), reading from selected register %#010x, val=%#010x\n", szInst, pState->uSelectedReg, *pu32));
4459 break;
4460 default:
4461 E1kLog(("%s e1kIOPortIn: invalid port %#010x\n", szInst, port));
4462 //*pRC = VERR_IOM_IOPORT_UNUSED;
4463 }
4464
4465 STAM_PROFILE_ADV_STOP(&pState->CTX_SUFF_Z(StatIORead), a);
4466 return rc;
4467}
4468
4469
4470/**
4471 * Port I/O Handler for OUT operations.
4472 *
4473 * @returns VBox status code.
4474 *
4475 * @param pDevIns The device instance.
4476 * @param pvUser User argument.
4477 * @param Port Port number used for the IN operation.
4478 * @param u32 The value to output.
4479 * @param cb The value size in bytes.
4480 * @thread EMT
4481 */
4482PDMBOTHCBDECL(int) e1kIOPortOut(PPDMDEVINS pDevIns, void *pvUser,
4483 RTIOPORT port, uint32_t u32, unsigned cb)
4484{
4485 E1KSTATE *pState = PDMINS_2_DATA(pDevIns, E1KSTATE *);
4486 int rc = VINF_SUCCESS;
4487 const char *szInst = INSTANCE(pState);
4488 STAM_PROFILE_ADV_START(&pState->CTX_SUFF_Z(StatIOWrite), a);
4489
4490 E1kLog2(("%s e1kIOPortOut: port=%RTiop value=%08x\n", szInst, port, u32));
4491 if (cb != 4)
4492 {
4493 E1kLog(("%s e1kIOPortOut: invalid op size: port=%RTiop cb=%08x\n", szInst, port, cb));
4494 rc = PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "%s e1kIOPortOut: invalid op size: port=%RTiop cb=%08x\n", szInst, port, cb);
4495 }
4496 else
4497 {
4498 port -= pState->addrIOPort;
4499 switch (port)
4500 {
4501 case 0x00: /* IOADDR */
4502 pState->uSelectedReg = u32;
4503 E1kLog2(("%s e1kIOPortOut: IOADDR(0), selected register %08x\n", szInst, pState->uSelectedReg));
4504 break;
4505 case 0x04: /* IODATA */
4506 E1kLog2(("%s e1kIOPortOut: IODATA(4), writing to selected register %#010x, value=%#010x\n", szInst, pState->uSelectedReg, u32));
4507 rc = e1kRegWrite(pState, pState->uSelectedReg, &u32, cb);
4508 /** @todo wrong return code triggers assertions in the debug build; fix please */
4509 if (rc == VINF_IOM_HC_MMIO_WRITE)
4510 rc = VINF_IOM_HC_IOPORT_WRITE;
4511 break;
4512 default:
4513 E1kLog(("%s e1kIOPortOut: invalid port %#010x\n", szInst, port));
4514 /** @todo Do we need to return an error here?
4515 * bird: VINF_SUCCESS is fine for unhandled cases of an OUT handler. (If you're curious
4516 * about the guest code and a bit adventuresome, try rc = PDMDeviceDBGFStop(...);) */
4517 rc = PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "e1kIOPortOut: invalid port %#010x\n", port);
4518 }
4519 }
4520
4521 STAM_PROFILE_ADV_STOP(&pState->CTX_SUFF_Z(StatIOWrite), a);
4522 return rc;
4523}
4524
4525#ifdef IN_RING3
4526/**
4527 * Dump complete device state to log.
4528 *
4529 * @param pState Pointer to device state.
4530 */
4531static void e1kDumpState(E1KSTATE *pState)
4532{
4533 for (int i = 0; i<E1K_NUM_OF_32BIT_REGS; ++i)
4534 {
4535 E1kLog2(("%s %8.8s = %08x\n", INSTANCE(pState),
4536 s_e1kRegMap[i].abbrev, pState->auRegs[i]));
4537 }
4538#ifdef E1K_INT_STATS
4539 LogRel(("%s Interrupt attempts: %d\n", INSTANCE(pState), pState->uStatIntTry));
4540 LogRel(("%s Interrupts raised : %d\n", INSTANCE(pState), pState->uStatInt));
4541 LogRel(("%s Interrupts lowered: %d\n", INSTANCE(pState), pState->uStatIntLower));
4542 LogRel(("%s Interrupts delayed: %d\n", INSTANCE(pState), pState->uStatIntDly));
4543 LogRel(("%s Disabled delayed: %d\n", INSTANCE(pState), pState->uStatDisDly));
4544 LogRel(("%s Interrupts skipped: %d\n", INSTANCE(pState), pState->uStatIntSkip));
4545 LogRel(("%s Masked interrupts : %d\n", INSTANCE(pState), pState->uStatIntMasked));
4546 LogRel(("%s Early interrupts : %d\n", INSTANCE(pState), pState->uStatIntEarly));
4547 LogRel(("%s Late interrupts : %d\n", INSTANCE(pState), pState->uStatIntLate));
4548 LogRel(("%s Lost interrupts : %d\n", INSTANCE(pState), pState->iStatIntLost));
4549 LogRel(("%s Interrupts by RX : %d\n", INSTANCE(pState), pState->uStatIntRx));
4550 LogRel(("%s Interrupts by TX : %d\n", INSTANCE(pState), pState->uStatIntTx));
4551 LogRel(("%s Interrupts by ICS : %d\n", INSTANCE(pState), pState->uStatIntICS));
4552 LogRel(("%s Interrupts by RDTR: %d\n", INSTANCE(pState), pState->uStatIntRDTR));
4553 LogRel(("%s Interrupts by RDMT: %d\n", INSTANCE(pState), pState->uStatIntRXDMT0));
4554 LogRel(("%s Interrupts by TXQE: %d\n", INSTANCE(pState), pState->uStatIntTXQE));
4555 LogRel(("%s TX int delay asked: %d\n", INSTANCE(pState), pState->uStatTxIDE));
4556 LogRel(("%s TX no report asked: %d\n", INSTANCE(pState), pState->uStatTxNoRS));
4557 LogRel(("%s TX abs timer expd : %d\n", INSTANCE(pState), pState->uStatTAD));
4558 LogRel(("%s TX int timer expd : %d\n", INSTANCE(pState), pState->uStatTID));
4559 LogRel(("%s RX abs timer expd : %d\n", INSTANCE(pState), pState->uStatRAD));
4560 LogRel(("%s RX int timer expd : %d\n", INSTANCE(pState), pState->uStatRID));
4561 LogRel(("%s TX CTX descriptors: %d\n", INSTANCE(pState), pState->uStatDescCtx));
4562 LogRel(("%s TX DAT descriptors: %d\n", INSTANCE(pState), pState->uStatDescDat));
4563 LogRel(("%s TX LEG descriptors: %d\n", INSTANCE(pState), pState->uStatDescLeg));
4564 LogRel(("%s Received frames : %d\n", INSTANCE(pState), pState->uStatRxFrm));
4565 LogRel(("%s Transmitted frames: %d\n", INSTANCE(pState), pState->uStatTxFrm));
4566#endif /* E1K_INT_STATS */
4567}
4568
4569/**
4570 * Map PCI I/O region.
4571 *
4572 * @return VBox status code.
4573 * @param pPciDev Pointer to PCI device. Use pPciDev->pDevIns to get the device instance.
4574 * @param iRegion The region number.
4575 * @param GCPhysAddress Physical address of the region. If iType is PCI_ADDRESS_SPACE_IO, this is an
4576 * I/O port, else it's a physical address.
4577 * This address is *NOT* relative to pci_mem_base like earlier!
4578 * @param cb Region size.
4579 * @param enmType One of the PCI_ADDRESS_SPACE_* values.
4580 * @thread EMT
4581 */
4582static DECLCALLBACK(int) e1kMap(PPCIDEVICE pPciDev, int iRegion,
4583 RTGCPHYS GCPhysAddress, uint32_t cb, PCIADDRESSSPACE enmType)
4584{
4585 int rc;
4586 E1KSTATE *pState = PDMINS_2_DATA(pPciDev->pDevIns, E1KSTATE*);
4587
4588 switch (enmType)
4589 {
4590 case PCI_ADDRESS_SPACE_IO:
4591 pState->addrIOPort = (RTIOPORT)GCPhysAddress;
4592 rc = PDMDevHlpIOPortRegister(pPciDev->pDevIns, pState->addrIOPort, cb, 0,
4593 e1kIOPortOut, e1kIOPortIn, NULL, NULL, "E1000");
4594 if (RT_FAILURE(rc))
4595 break;
4596 if (pState->fR0Enabled)
4597 {
4598 rc = PDMDevHlpIOPortRegisterR0(pPciDev->pDevIns, pState->addrIOPort, cb, 0,
4599 "e1kIOPortOut", "e1kIOPortIn", NULL, NULL, "E1000");
4600 if (RT_FAILURE(rc))
4601 break;
4602 }
4603 if (pState->fGCEnabled)
4604 {
4605 rc = PDMDevHlpIOPortRegisterRC(pPciDev->pDevIns, pState->addrIOPort, cb, 0,
4606 "e1kIOPortOut", "e1kIOPortIn", NULL, NULL, "E1000");
4607 }
4608 break;
4609 case PCI_ADDRESS_SPACE_MEM:
4610 pState->addrMMReg = GCPhysAddress;
4611 rc = PDMDevHlpMMIORegister(pPciDev->pDevIns, GCPhysAddress, cb, 0,
4612 e1kMMIOWrite, e1kMMIORead, NULL, "E1000");
4613 if (pState->fR0Enabled)
4614 {
4615 rc = PDMDevHlpMMIORegisterR0(pPciDev->pDevIns, GCPhysAddress, cb, 0,
4616 "e1kMMIOWrite", "e1kMMIORead", NULL);
4617 if (RT_FAILURE(rc))
4618 break;
4619 }
4620 if (pState->fGCEnabled)
4621 {
4622 rc = PDMDevHlpMMIORegisterRC(pPciDev->pDevIns, GCPhysAddress, cb, 0,
4623 "e1kMMIOWrite", "e1kMMIORead", NULL);
4624 }
4625 break;
4626 default:
4627 /* We should never get here */
4628 AssertMsgFailed(("Invalid PCI address space param in map callback"));
4629 rc = VERR_INTERNAL_ERROR;
4630 break;
4631 }
4632 return rc;
4633}
4634
4635/**
4636 * Check if the device can receive data now.
4637 * This must be called before the pfnRecieve() method is called.
4638 *
4639 * @returns Number of bytes the device can receive.
4640 * @param pInterface Pointer to the interface structure containing the called function pointer.
4641 * @thread EMT
4642 */
4643static int e1kCanReceive(E1KSTATE *pState)
4644{
4645 size_t cb;
4646
4647 if (RT_UNLIKELY(e1kMutexAcquire(pState, VERR_SEM_BUSY, RT_SRC_POS) != VINF_SUCCESS))
4648 return VERR_NET_NO_BUFFER_SPACE;
4649 if (RT_UNLIKELY(e1kCsRxEnter(pState, VERR_SEM_BUSY) != VINF_SUCCESS))
4650 return VERR_NET_NO_BUFFER_SPACE;
4651
4652 if (RDH < RDT)
4653 cb = (RDT - RDH) * pState->u16RxBSize;
4654 else if (RDH > RDT)
4655 cb = (RDLEN/sizeof(E1KRXDESC) - RDH + RDT) * pState->u16RxBSize;
4656 else
4657 {
4658 cb = 0;
4659 E1kLogRel(("E1000: OUT of RX descriptors!\n"));
4660 }
4661
4662 e1kCsRxLeave(pState);
4663 e1kMutexRelease(pState);
4664 return cb > 0 ? VINF_SUCCESS : VERR_NET_NO_BUFFER_SPACE;
4665}
4666
4667/**
4668 * @interface_method_impl{PDMINETWORKDOWN,pfnWaitReceiveAvail}
4669 */
4670static DECLCALLBACK(int) e1kNetworkDown_WaitReceiveAvail(PPDMINETWORKDOWN pInterface, RTMSINTERVAL cMillies)
4671{
4672 E1KSTATE *pState = RT_FROM_MEMBER(pInterface, E1KSTATE, INetworkDown);
4673 int rc = e1kCanReceive(pState);
4674
4675 if (RT_SUCCESS(rc))
4676 return VINF_SUCCESS;
4677 if (RT_UNLIKELY(cMillies == 0))
4678 return VERR_NET_NO_BUFFER_SPACE;
4679
4680 rc = VERR_INTERRUPTED;
4681 ASMAtomicXchgBool(&pState->fMaybeOutOfSpace, true);
4682 STAM_PROFILE_START(&pState->StatRxOverflow, a);
4683 VMSTATE enmVMState;
4684 while (RT_LIKELY( (enmVMState = PDMDevHlpVMState(pState->CTX_SUFF(pDevIns))) == VMSTATE_RUNNING
4685 || enmVMState == VMSTATE_RUNNING_LS))
4686 {
4687 int rc2 = e1kCanReceive(pState);
4688 if (RT_SUCCESS(rc2))
4689 {
4690 rc = VINF_SUCCESS;
4691 break;
4692 }
4693 E1kLogRel(("E1000 e1kNetworkDown_WaitReceiveAvail: waiting cMillies=%u...\n",
4694 cMillies));
4695 E1kLog(("%s e1kNetworkDown_WaitReceiveAvail: waiting cMillies=%u...\n",
4696 INSTANCE(pState), cMillies));
4697 RTSemEventWait(pState->hEventMoreRxDescAvail, cMillies);
4698 }
4699 STAM_PROFILE_STOP(&pState->StatRxOverflow, a);
4700 ASMAtomicXchgBool(&pState->fMaybeOutOfSpace, false);
4701
4702 return rc;
4703}
4704
4705
4706/**
4707 * Matches the packet addresses against Receive Address table. Looks for
4708 * exact matches only.
4709 *
4710 * @returns true if address matches.
4711 * @param pState Pointer to the state structure.
4712 * @param pvBuf The ethernet packet.
4713 * @param cb Number of bytes available in the packet.
4714 * @thread EMT
4715 */
4716static bool e1kPerfectMatch(E1KSTATE *pState, const void *pvBuf)
4717{
4718 for (unsigned i = 0; i < RT_ELEMENTS(pState->aRecAddr.array); i++)
4719 {
4720 E1KRAELEM* ra = pState->aRecAddr.array + i;
4721
4722 /* Valid address? */
4723 if (ra->ctl & RA_CTL_AV)
4724 {
4725 Assert((ra->ctl & RA_CTL_AS) < 2);
4726 //unsigned char *pAddr = (unsigned char*)pvBuf + sizeof(ra->addr)*(ra->ctl & RA_CTL_AS);
4727 //E1kLog3(("%s Matching %02x:%02x:%02x:%02x:%02x:%02x against %02x:%02x:%02x:%02x:%02x:%02x...\n",
4728 // INSTANCE(pState), pAddr[0], pAddr[1], pAddr[2], pAddr[3], pAddr[4], pAddr[5],
4729 // ra->addr[0], ra->addr[1], ra->addr[2], ra->addr[3], ra->addr[4], ra->addr[5]));
4730 /*
4731 * Address Select:
4732 * 00b = Destination address
4733 * 01b = Source address
4734 * 10b = Reserved
4735 * 11b = Reserved
4736 * Since ethernet header is (DA, SA, len) we can use address
4737 * select as index.
4738 */
4739 if (memcmp((char*)pvBuf + sizeof(ra->addr)*(ra->ctl & RA_CTL_AS),
4740 ra->addr, sizeof(ra->addr)) == 0)
4741 return true;
4742 }
4743 }
4744
4745 return false;
4746}
4747
4748/**
4749 * Matches the packet addresses against Multicast Table Array.
4750 *
4751 * @remarks This is imperfect match since it matches not exact address but
4752 * a subset of addresses.
4753 *
4754 * @returns true if address matches.
4755 * @param pState Pointer to the state structure.
4756 * @param pvBuf The ethernet packet.
4757 * @param cb Number of bytes available in the packet.
4758 * @thread EMT
4759 */
4760static bool e1kImperfectMatch(E1KSTATE *pState, const void *pvBuf)
4761{
4762 /* Get bits 32..47 of destination address */
4763 uint16_t u16Bit = ((uint16_t*)pvBuf)[2];
4764
4765 unsigned offset = GET_BITS(RCTL, MO);
4766 /*
4767 * offset means:
4768 * 00b = bits 36..47
4769 * 01b = bits 35..46
4770 * 10b = bits 34..45
4771 * 11b = bits 32..43
4772 */
4773 if (offset < 3)
4774 u16Bit = u16Bit >> (4 - offset);
4775 return ASMBitTest(pState->auMTA, u16Bit & 0xFFF);
4776}
4777
4778/**
4779 * Determines if the packet is to be delivered to upper layer. The following
4780 * filters supported:
4781 * - Exact Unicast/Multicast
4782 * - Promiscuous Unicast/Multicast
4783 * - Multicast
4784 * - VLAN
4785 *
4786 * @returns true if packet is intended for this node.
4787 * @param pState Pointer to the state structure.
4788 * @param pvBuf The ethernet packet.
4789 * @param cb Number of bytes available in the packet.
4790 * @param pStatus Bit field to store status bits.
4791 * @thread EMT
4792 */
4793static bool e1kAddressFilter(E1KSTATE *pState, const void *pvBuf, size_t cb, E1KRXDST *pStatus)
4794{
4795 Assert(cb > 14);
4796 /* Assume that we fail to pass exact filter. */
4797 pStatus->fPIF = false;
4798 pStatus->fVP = false;
4799 /* Discard oversized packets */
4800 if (cb > E1K_MAX_RX_PKT_SIZE)
4801 {
4802 E1kLog(("%s ERROR: Incoming packet is too big, cb=%d > max=%d\n",
4803 INSTANCE(pState), cb, E1K_MAX_RX_PKT_SIZE));
4804 E1K_INC_CNT32(ROC);
4805 return false;
4806 }
4807 else if (!(RCTL & RCTL_LPE) && cb > 1522)
4808 {
4809 /* When long packet reception is disabled packets over 1522 are discarded */
4810 E1kLog(("%s Discarding incoming packet (LPE=0), cb=%d\n",
4811 INSTANCE(pState), cb));
4812 E1K_INC_CNT32(ROC);
4813 return false;
4814 }
4815
4816 /* Broadcast filtering */
4817 if (e1kIsBroadcast(pvBuf) && (RCTL & RCTL_BAM))
4818 return true;
4819 E1kLog2(("%s Packet filter: not a broadcast\n", INSTANCE(pState)));
4820 if (e1kIsMulticast(pvBuf))
4821 {
4822 /* Is multicast promiscuous enabled? */
4823 if (RCTL & RCTL_MPE)
4824 return true;
4825 E1kLog2(("%s Packet filter: no promiscuous multicast\n", INSTANCE(pState)));
4826 /* Try perfect matches first */
4827 if (e1kPerfectMatch(pState, pvBuf))
4828 {
4829 pStatus->fPIF = true;
4830 return true;
4831 }
4832 E1kLog2(("%s Packet filter: no perfect match\n", INSTANCE(pState)));
4833 if (e1kImperfectMatch(pState, pvBuf))
4834 return true;
4835 E1kLog2(("%s Packet filter: no imperfect match\n", INSTANCE(pState)));
4836 }
4837 else {
4838 /* Is unicast promiscuous enabled? */
4839 if (RCTL & RCTL_UPE)
4840 return true;
4841 E1kLog2(("%s Packet filter: no promiscuous unicast\n", INSTANCE(pState)));
4842 if (e1kPerfectMatch(pState, pvBuf))
4843 {
4844 pStatus->fPIF = true;
4845 return true;
4846 }
4847 E1kLog2(("%s Packet filter: no perfect match\n", INSTANCE(pState)));
4848 }
4849 /* Is VLAN filtering enabled? */
4850 if (RCTL & RCTL_VFE)
4851 {
4852 uint16_t *u16Ptr = (uint16_t*)pvBuf;
4853 /* Compare TPID with VLAN Ether Type */
4854 if (u16Ptr[6] == VET)
4855 {
4856 pStatus->fVP = true;
4857 /* It is 802.1q packet indeed, let's filter by VID */
4858 if (ASMBitTest(pState->auVFTA, RT_BE2H_U16(u16Ptr[7]) & 0xFFF))
4859 return true;
4860 E1kLog2(("%s Packet filter: no VLAN match\n", INSTANCE(pState)));
4861 }
4862 }
4863 E1kLog2(("%s Packet filter: packet discarded\n", INSTANCE(pState)));
4864 return false;
4865}
4866
4867/**
4868 * @interface_method_impl{PDMINETWORKDOWN,pfnReceive}
4869 */
4870static DECLCALLBACK(int) e1kNetworkDown_Receive(PPDMINETWORKDOWN pInterface, const void *pvBuf, size_t cb)
4871{
4872 E1KSTATE *pState = RT_FROM_MEMBER(pInterface, E1KSTATE, INetworkDown);
4873 int rc = VINF_SUCCESS;
4874
4875 /*
4876 * Drop packets if the VM is not running yet/anymore.
4877 */
4878 VMSTATE enmVMState = PDMDevHlpVMState(STATE_TO_DEVINS(pState));
4879 if ( enmVMState != VMSTATE_RUNNING
4880 && enmVMState != VMSTATE_RUNNING_LS)
4881 {
4882 E1kLog(("%s Dropping incoming packet as VM is not running.\n", INSTANCE(pState)));
4883 return VINF_SUCCESS;
4884 }
4885
4886 /* Discard incoming packets in locked state */
4887 if (!(RCTL & RCTL_EN) || pState->fLocked || !(STATUS & STATUS_LU))
4888 {
4889 E1kLog(("%s Dropping incoming packet as receive operation is disabled.\n", INSTANCE(pState)));
4890 return VINF_SUCCESS;
4891 }
4892
4893 STAM_PROFILE_ADV_START(&pState->StatReceive, a);
4894 rc = e1kMutexAcquire(pState, VERR_SEM_BUSY, RT_SRC_POS);
4895 if (RT_LIKELY(rc == VINF_SUCCESS))
4896 {
4897 //if (!e1kCsEnter(pState, RT_SRC_POS))
4898 // return VERR_PERMISSION_DENIED;
4899
4900 e1kPacketDump(pState, (const uint8_t*)pvBuf, cb, "<-- Incoming");
4901
4902 /* Update stats */
4903 if (RT_LIKELY(e1kCsEnter(pState, VERR_SEM_BUSY) == VINF_SUCCESS))
4904 {
4905 E1K_INC_CNT32(TPR);
4906 E1K_ADD_CNT64(TORL, TORH, cb < 64? 64 : cb);
4907 e1kCsLeave(pState);
4908 }
4909 STAM_PROFILE_ADV_START(&pState->StatReceiveFilter, a);
4910 E1KRXDST status;
4911 RT_ZERO(status);
4912 bool fPassed = e1kAddressFilter(pState, pvBuf, cb, &status);
4913 STAM_PROFILE_ADV_STOP(&pState->StatReceiveFilter, a);
4914 if (fPassed)
4915 {
4916 rc = e1kHandleRxPacket(pState, pvBuf, cb, status);
4917 }
4918 //e1kCsLeave(pState);
4919 e1kMutexRelease(pState);
4920 }
4921 STAM_PROFILE_ADV_STOP(&pState->StatReceive, a);
4922
4923 return rc;
4924}
4925
4926/**
4927 * Gets the pointer to the status LED of a unit.
4928 *
4929 * @returns VBox status code.
4930 * @param pInterface Pointer to the interface structure.
4931 * @param iLUN The unit which status LED we desire.
4932 * @param ppLed Where to store the LED pointer.
4933 * @thread EMT
4934 */
4935static DECLCALLBACK(int) e1kQueryStatusLed(PPDMILEDPORTS pInterface, unsigned iLUN, PPDMLED *ppLed)
4936{
4937 E1KSTATE *pState = RT_FROM_MEMBER(pInterface, E1KSTATE, ILeds);
4938 int rc = VERR_PDM_LUN_NOT_FOUND;
4939
4940 if (iLUN == 0)
4941 {
4942 *ppLed = &pState->led;
4943 rc = VINF_SUCCESS;
4944 }
4945 return rc;
4946}
4947
4948/**
4949 * Gets the current Media Access Control (MAC) address.
4950 *
4951 * @returns VBox status code.
4952 * @param pInterface Pointer to the interface structure containing the called function pointer.
4953 * @param pMac Where to store the MAC address.
4954 * @thread EMT
4955 */
4956static DECLCALLBACK(int) e1kGetMac(PPDMINETWORKCONFIG pInterface, PRTMAC pMac)
4957{
4958 E1KSTATE *pState = RT_FROM_MEMBER(pInterface, E1KSTATE, INetworkConfig);
4959 pState->eeprom.getMac(pMac);
4960 return VINF_SUCCESS;
4961}
4962
4963
4964/**
4965 * Gets the new link state.
4966 *
4967 * @returns The current link state.
4968 * @param pInterface Pointer to the interface structure containing the called function pointer.
4969 * @thread EMT
4970 */
4971static DECLCALLBACK(PDMNETWORKLINKSTATE) e1kGetLinkState(PPDMINETWORKCONFIG pInterface)
4972{
4973 E1KSTATE *pState = RT_FROM_MEMBER(pInterface, E1KSTATE, INetworkConfig);
4974 if (STATUS & STATUS_LU)
4975 return PDMNETWORKLINKSTATE_UP;
4976 return PDMNETWORKLINKSTATE_DOWN;
4977}
4978
4979
4980/**
4981 * Sets the new link state.
4982 *
4983 * @returns VBox status code.
4984 * @param pInterface Pointer to the interface structure containing the called function pointer.
4985 * @param enmState The new link state
4986 * @thread EMT
4987 */
4988static DECLCALLBACK(int) e1kSetLinkState(PPDMINETWORKCONFIG pInterface, PDMNETWORKLINKSTATE enmState)
4989{
4990 E1KSTATE *pState = RT_FROM_MEMBER(pInterface, E1KSTATE, INetworkConfig);
4991 bool fOldUp = !!(STATUS & STATUS_LU);
4992 bool fNewUp = enmState == PDMNETWORKLINKSTATE_UP;
4993
4994 if ( fNewUp != fOldUp
4995 || (!fNewUp && pState->fCableConnected)) /* old state was connected but STATUS not
4996 * yet written by guest */
4997 {
4998 if (fNewUp)
4999 {
5000 E1kLog(("%s Link will be up in approximately 5 secs\n", INSTANCE(pState)));
5001 pState->fCableConnected = true;
5002 STATUS &= ~STATUS_LU;
5003 Phy::setLinkStatus(&pState->phy, false);
5004 e1kRaiseInterrupt(pState, VERR_SEM_BUSY, ICR_LSC);
5005 /* Restore the link back in 5 second. */
5006 e1kArmTimer(pState, pState->pLUTimerR3, 5000000);
5007 }
5008 else
5009 {
5010 E1kLog(("%s Link is down\n", INSTANCE(pState)));
5011 pState->fCableConnected = false;
5012 STATUS &= ~STATUS_LU;
5013 Phy::setLinkStatus(&pState->phy, false);
5014 e1kRaiseInterrupt(pState, VERR_SEM_BUSY, ICR_LSC);
5015 }
5016 if (pState->pDrvR3)
5017 pState->pDrvR3->pfnNotifyLinkChanged(pState->pDrvR3, enmState);
5018 }
5019 return VINF_SUCCESS;
5020}
5021
5022/**
5023 * @interface_method_impl{PDMIBASE,pfnQueryInterface}
5024 */
5025static DECLCALLBACK(void *) e1kQueryInterface(struct PDMIBASE *pInterface, const char *pszIID)
5026{
5027 E1KSTATE *pThis = RT_FROM_MEMBER(pInterface, E1KSTATE, IBase);
5028 Assert(&pThis->IBase == pInterface);
5029
5030 PDMIBASE_RETURN_INTERFACE(pszIID, PDMIBASE, &pThis->IBase);
5031 PDMIBASE_RETURN_INTERFACE(pszIID, PDMINETWORKDOWN, &pThis->INetworkDown);
5032 PDMIBASE_RETURN_INTERFACE(pszIID, PDMINETWORKCONFIG, &pThis->INetworkConfig);
5033 PDMIBASE_RETURN_INTERFACE(pszIID, PDMILEDPORTS, &pThis->ILeds);
5034 return NULL;
5035}
5036
5037/**
5038 * Saves the configuration.
5039 *
5040 * @param pState The E1K state.
5041 * @param pSSM The handle to the saved state.
5042 */
5043static void e1kSaveConfig(E1KSTATE *pState, PSSMHANDLE pSSM)
5044{
5045 SSMR3PutMem(pSSM, &pState->macConfigured, sizeof(pState->macConfigured));
5046 SSMR3PutU32(pSSM, pState->eChip);
5047}
5048
5049/**
5050 * Live save - save basic configuration.
5051 *
5052 * @returns VBox status code.
5053 * @param pDevIns The device instance.
5054 * @param pSSM The handle to the saved state.
5055 * @param uPass
5056 */
5057static DECLCALLBACK(int) e1kLiveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t uPass)
5058{
5059 E1KSTATE *pState = PDMINS_2_DATA(pDevIns, E1KSTATE*);
5060 e1kSaveConfig(pState, pSSM);
5061 return VINF_SSM_DONT_CALL_AGAIN;
5062}
5063
5064/**
5065 * Prepares for state saving.
5066 *
5067 * @returns VBox status code.
5068 * @param pDevIns The device instance.
5069 * @param pSSM The handle to the saved state.
5070 */
5071static DECLCALLBACK(int) e1kSavePrep(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
5072{
5073 E1KSTATE* pState = PDMINS_2_DATA(pDevIns, E1KSTATE*);
5074
5075 int rc = e1kCsEnter(pState, VERR_SEM_BUSY);
5076 if (RT_UNLIKELY(rc != VINF_SUCCESS))
5077 return rc;
5078 e1kCsLeave(pState);
5079 return VINF_SUCCESS;
5080#if 0
5081 int rc = e1kMutexAcquire(pState, VERR_SEM_BUSY, RT_SRC_POS);
5082 if (RT_UNLIKELY(rc != VINF_SUCCESS))
5083 return rc;
5084 /* 1) Prevent all threads from modifying the state and memory */
5085 //pState->fLocked = true;
5086 /* 2) Cancel all timers */
5087#ifdef E1K_USE_TX_TIMERS
5088 e1kCancelTimer(pState, pState->CTX_SUFF(pTIDTimer));
5089#ifndef E1K_NO_TAD
5090 e1kCancelTimer(pState, pState->CTX_SUFF(pTADTimer));
5091#endif /* E1K_NO_TAD */
5092#endif /* E1K_USE_TX_TIMERS */
5093#ifdef E1K_USE_RX_TIMERS
5094 e1kCancelTimer(pState, pState->CTX_SUFF(pRIDTimer));
5095 e1kCancelTimer(pState, pState->CTX_SUFF(pRADTimer));
5096#endif /* E1K_USE_RX_TIMERS */
5097 e1kCancelTimer(pState, pState->CTX_SUFF(pIntTimer));
5098 /* 3) Did I forget anything? */
5099 E1kLog(("%s Locked\n", INSTANCE(pState)));
5100 e1kMutexRelease(pState);
5101 return VINF_SUCCESS;
5102#endif
5103}
5104
5105
5106/**
5107 * Saves the state of device.
5108 *
5109 * @returns VBox status code.
5110 * @param pDevIns The device instance.
5111 * @param pSSM The handle to the saved state.
5112 */
5113static DECLCALLBACK(int) e1kSaveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
5114{
5115 E1KSTATE* pState = PDMINS_2_DATA(pDevIns, E1KSTATE*);
5116
5117 e1kSaveConfig(pState, pSSM);
5118 pState->eeprom.save(pSSM);
5119 e1kDumpState(pState);
5120 SSMR3PutMem(pSSM, pState->auRegs, sizeof(pState->auRegs));
5121 SSMR3PutBool(pSSM, pState->fIntRaised);
5122 Phy::saveState(pSSM, &pState->phy);
5123 SSMR3PutU32(pSSM, pState->uSelectedReg);
5124 SSMR3PutMem(pSSM, pState->auMTA, sizeof(pState->auMTA));
5125 SSMR3PutMem(pSSM, &pState->aRecAddr, sizeof(pState->aRecAddr));
5126 SSMR3PutMem(pSSM, pState->auVFTA, sizeof(pState->auVFTA));
5127 SSMR3PutU64(pSSM, pState->u64AckedAt);
5128 SSMR3PutU16(pSSM, pState->u16RxBSize);
5129 //SSMR3PutBool(pSSM, pState->fDelayInts);
5130 //SSMR3PutBool(pSSM, pState->fIntMaskUsed);
5131 SSMR3PutU16(pSSM, pState->u16TxPktLen);
5132/** @todo State wrt to the TSE buffer is incomplete, so little point in
5133 * saving this actually. */
5134 SSMR3PutMem(pSSM, pState->aTxPacketFallback, pState->u16TxPktLen);
5135 SSMR3PutBool(pSSM, pState->fIPcsum);
5136 SSMR3PutBool(pSSM, pState->fTCPcsum);
5137 SSMR3PutMem(pSSM, &pState->contextTSE, sizeof(pState->contextTSE));
5138 SSMR3PutMem(pSSM, &pState->contextNormal, sizeof(pState->contextNormal));
5139/**@todo GSO requires some more state here. */
5140 E1kLog(("%s State has been saved\n", INSTANCE(pState)));
5141 return VINF_SUCCESS;
5142}
5143
5144#if 0
5145/**
5146 * Cleanup after saving.
5147 *
5148 * @returns VBox status code.
5149 * @param pDevIns The device instance.
5150 * @param pSSM The handle to the saved state.
5151 */
5152static DECLCALLBACK(int) e1kSaveDone(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
5153{
5154 E1KSTATE* pState = PDMINS_2_DATA(pDevIns, E1KSTATE*);
5155
5156 int rc = e1kMutexAcquire(pState, VERR_SEM_BUSY, RT_SRC_POS);
5157 if (RT_UNLIKELY(rc != VINF_SUCCESS))
5158 return rc;
5159 /* If VM is being powered off unlocking will result in assertions in PGM */
5160 if (PDMDevHlpGetVM(pDevIns)->enmVMState == VMSTATE_RUNNING)
5161 pState->fLocked = false;
5162 else
5163 E1kLog(("%s VM is not running -- remain locked\n", INSTANCE(pState)));
5164 E1kLog(("%s Unlocked\n", INSTANCE(pState)));
5165 e1kMutexRelease(pState);
5166 return VINF_SUCCESS;
5167}
5168#endif
5169
5170/**
5171 * Sync with .
5172 *
5173 * @returns VBox status code.
5174 * @param pDevIns The device instance.
5175 * @param pSSM The handle to the saved state.
5176 */
5177static DECLCALLBACK(int) e1kLoadPrep(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
5178{
5179 E1KSTATE* pState = PDMINS_2_DATA(pDevIns, E1KSTATE*);
5180
5181 int rc = e1kCsEnter(pState, VERR_SEM_BUSY);
5182 if (RT_UNLIKELY(rc != VINF_SUCCESS))
5183 return rc;
5184 e1kCsLeave(pState);
5185 return VINF_SUCCESS;
5186}
5187
5188/**
5189 * Restore previously saved state of device.
5190 *
5191 * @returns VBox status code.
5192 * @param pDevIns The device instance.
5193 * @param pSSM The handle to the saved state.
5194 * @param uVersion The data unit version number.
5195 * @param uPass The data pass.
5196 */
5197static DECLCALLBACK(int) e1kLoadExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
5198{
5199 E1KSTATE *pState = PDMINS_2_DATA(pDevIns, E1KSTATE*);
5200 int rc;
5201
5202 if ( uVersion != E1K_SAVEDSTATE_VERSION
5203 && uVersion != E1K_SAVEDSTATE_VERSION_VBOX_30)
5204 return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
5205
5206 if ( uVersion > E1K_SAVEDSTATE_VERSION_VBOX_30
5207 || uPass != SSM_PASS_FINAL)
5208 {
5209 /* config checks */
5210 RTMAC macConfigured;
5211 rc = SSMR3GetMem(pSSM, &macConfigured, sizeof(macConfigured));
5212 AssertRCReturn(rc, rc);
5213 if ( memcmp(&macConfigured, &pState->macConfigured, sizeof(macConfigured))
5214 && (uPass == 0 || !PDMDevHlpVMTeleportedAndNotFullyResumedYet(pDevIns)) )
5215 LogRel(("%s: The mac address differs: config=%RTmac saved=%RTmac\n", INSTANCE(pState), &pState->macConfigured, &macConfigured));
5216
5217 E1KCHIP eChip;
5218 rc = SSMR3GetU32(pSSM, &eChip);
5219 AssertRCReturn(rc, rc);
5220 if (eChip != pState->eChip)
5221 return SSMR3SetCfgError(pSSM, RT_SRC_POS, N_("The chip type differs: config=%u saved=%u"), pState->eChip, eChip);
5222 }
5223
5224 if (uPass == SSM_PASS_FINAL)
5225 {
5226 if (uVersion > E1K_SAVEDSTATE_VERSION_VBOX_30)
5227 {
5228 rc = pState->eeprom.load(pSSM);
5229 AssertRCReturn(rc, rc);
5230 }
5231 /* the state */
5232 SSMR3GetMem(pSSM, &pState->auRegs, sizeof(pState->auRegs));
5233 SSMR3GetBool(pSSM, &pState->fIntRaised);
5234 /** @todo: PHY could be made a separate device with its own versioning */
5235 Phy::loadState(pSSM, &pState->phy);
5236 SSMR3GetU32(pSSM, &pState->uSelectedReg);
5237 SSMR3GetMem(pSSM, &pState->auMTA, sizeof(pState->auMTA));
5238 SSMR3GetMem(pSSM, &pState->aRecAddr, sizeof(pState->aRecAddr));
5239 SSMR3GetMem(pSSM, &pState->auVFTA, sizeof(pState->auVFTA));
5240 SSMR3GetU64(pSSM, &pState->u64AckedAt);
5241 SSMR3GetU16(pSSM, &pState->u16RxBSize);
5242 //SSMR3GetBool(pSSM, pState->fDelayInts);
5243 //SSMR3GetBool(pSSM, pState->fIntMaskUsed);
5244 SSMR3GetU16(pSSM, &pState->u16TxPktLen);
5245 SSMR3GetMem(pSSM, &pState->aTxPacketFallback[0], pState->u16TxPktLen);
5246 SSMR3GetBool(pSSM, &pState->fIPcsum);
5247 SSMR3GetBool(pSSM, &pState->fTCPcsum);
5248 SSMR3GetMem(pSSM, &pState->contextTSE, sizeof(pState->contextTSE));
5249 rc = SSMR3GetMem(pSSM, &pState->contextNormal, sizeof(pState->contextNormal));
5250 AssertRCReturn(rc, rc);
5251
5252 /* derived state */
5253 e1kSetupGsoCtx(&pState->GsoCtx, &pState->contextTSE);
5254
5255 E1kLog(("%s State has been restored\n", INSTANCE(pState)));
5256 e1kDumpState(pState);
5257 }
5258 return VINF_SUCCESS;
5259}
5260
5261/**
5262 * Link status adjustments after loading.
5263 *
5264 * @returns VBox status code.
5265 * @param pDevIns The device instance.
5266 * @param pSSM The handle to the saved state.
5267 */
5268static DECLCALLBACK(int) e1kLoadDone(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
5269{
5270 E1KSTATE* pState = PDMINS_2_DATA(pDevIns, E1KSTATE*);
5271
5272 int rc = e1kMutexAcquire(pState, VERR_SEM_BUSY, RT_SRC_POS);
5273 if (RT_UNLIKELY(rc != VINF_SUCCESS))
5274 return rc;
5275
5276 /* Update promiscuous mode */
5277 if (pState->pDrvR3)
5278 pState->pDrvR3->pfnSetPromiscuousMode(pState->pDrvR3,
5279 !!(RCTL & (RCTL_UPE | RCTL_MPE)));
5280
5281 /*
5282 * Force the link down here, since PDMNETWORKLINKSTATE_DOWN_RESUME is never
5283 * passed to us. We go through all this stuff if the link was up and we
5284 * wasn't teleported.
5285 */
5286 if ( (STATUS & STATUS_LU)
5287 && !PDMDevHlpVMTeleportedAndNotFullyResumedYet(pDevIns))
5288 {
5289 E1kLog(("%s Link is down temporarily\n", INSTANCE(pState)));
5290 STATUS &= ~STATUS_LU;
5291 Phy::setLinkStatus(&pState->phy, false);
5292 e1kRaiseInterrupt(pState, VERR_SEM_BUSY, ICR_LSC);
5293 /* Restore the link back in five seconds. */
5294 e1kArmTimer(pState, pState->pLUTimerR3, 5000000);
5295 }
5296 e1kMutexRelease(pState);
5297 return VINF_SUCCESS;
5298}
5299
5300
5301/* -=-=-=-=- PDMDEVREG -=-=-=-=- */
5302
5303/**
5304 * Detach notification.
5305 *
5306 * One port on the network card has been disconnected from the network.
5307 *
5308 * @param pDevIns The device instance.
5309 * @param iLUN The logical unit which is being detached.
5310 * @param fFlags Flags, combination of the PDMDEVATT_FLAGS_* \#defines.
5311 */
5312static DECLCALLBACK(void) e1kDetach(PPDMDEVINS pDevIns, unsigned iLUN, uint32_t fFlags)
5313{
5314 E1KSTATE *pState = PDMINS_2_DATA(pDevIns, E1KSTATE*);
5315 Log(("%s e1kDetach:\n", INSTANCE(pState)));
5316
5317 AssertLogRelReturnVoid(iLUN == 0);
5318
5319 PDMCritSectEnter(&pState->cs, VERR_SEM_BUSY);
5320
5321 /** @todo: r=pritesh still need to check if i missed
5322 * to clean something in this function
5323 */
5324
5325 /*
5326 * Zero some important members.
5327 */
5328 pState->pDrvBase = NULL;
5329 pState->pDrvR3 = NULL;
5330 pState->pDrvR0 = NIL_RTR0PTR;
5331 pState->pDrvRC = NIL_RTRCPTR;
5332
5333 PDMCritSectLeave(&pState->cs);
5334}
5335
5336/**
5337 * Attach the Network attachment.
5338 *
5339 * One port on the network card has been connected to a network.
5340 *
5341 * @returns VBox status code.
5342 * @param pDevIns The device instance.
5343 * @param iLUN The logical unit which is being attached.
5344 * @param fFlags Flags, combination of the PDMDEVATT_FLAGS_* \#defines.
5345 *
5346 * @remarks This code path is not used during construction.
5347 */
5348static DECLCALLBACK(int) e1kAttach(PPDMDEVINS pDevIns, unsigned iLUN, uint32_t fFlags)
5349{
5350 E1KSTATE *pState = PDMINS_2_DATA(pDevIns, E1KSTATE*);
5351 LogFlow(("%s e1kAttach:\n", INSTANCE(pState)));
5352
5353 AssertLogRelReturn(iLUN == 0, VERR_PDM_NO_SUCH_LUN);
5354
5355 PDMCritSectEnter(&pState->cs, VERR_SEM_BUSY);
5356
5357 /*
5358 * Attach the driver.
5359 */
5360 int rc = PDMDevHlpDriverAttach(pDevIns, 0, &pState->IBase, &pState->pDrvBase, "Network Port");
5361 if (RT_SUCCESS(rc))
5362 {
5363 if (rc == VINF_NAT_DNS)
5364 {
5365#ifdef RT_OS_LINUX
5366 PDMDevHlpVMSetRuntimeError(pDevIns, 0 /*fFlags*/, "NoDNSforNAT",
5367 N_("A Domain Name Server (DNS) for NAT networking could not be determined. Please check your /etc/resolv.conf for <tt>nameserver</tt> entries. Either add one manually (<i>man resolv.conf</i>) or ensure that your host is correctly connected to an ISP. If you ignore this warning the guest will not be able to perform nameserver lookups and it will probably observe delays if trying so"));
5368#else
5369 PDMDevHlpVMSetRuntimeError(pDevIns, 0 /*fFlags*/, "NoDNSforNAT",
5370 N_("A Domain Name Server (DNS) for NAT networking could not be determined. Ensure that your host is correctly connected to an ISP. If you ignore this warning the guest will not be able to perform nameserver lookups and it will probably observe delays if trying so"));
5371#endif
5372 }
5373 pState->pDrvR3 = PDMIBASE_QUERY_INTERFACE(pState->pDrvBase, PDMINETWORKUP);
5374 AssertMsgStmt(pState->pDrvR3, ("Failed to obtain the PDMINETWORKUP interface!\n"),
5375 rc = VERR_PDM_MISSING_INTERFACE_BELOW);
5376 if (RT_SUCCESS(rc))
5377 {
5378 PPDMIBASER0 pBaseR0 = PDMIBASE_QUERY_INTERFACE(pState->pDrvBase, PDMIBASER0);
5379 pState->pDrvR0 = pBaseR0 ? pBaseR0->pfnQueryInterface(pBaseR0, PDMINETWORKUP_IID) : NIL_RTR0PTR;
5380
5381 PPDMIBASERC pBaseRC = PDMIBASE_QUERY_INTERFACE(pState->pDrvBase, PDMIBASERC);
5382 pState->pDrvRC = pBaseRC ? pBaseRC->pfnQueryInterface(pBaseRC, PDMINETWORKUP_IID) : NIL_RTR0PTR;
5383 }
5384 }
5385 else if ( rc == VERR_PDM_NO_ATTACHED_DRIVER
5386 || rc == VERR_PDM_CFG_MISSING_DRIVER_NAME)
5387 {
5388 /* This should never happen because this function is not called
5389 * if there is no driver to attach! */
5390 Log(("%s No attached driver!\n", INSTANCE(pState)));
5391 }
5392
5393 /*
5394 * Temporary set the link down if it was up so that the guest
5395 * will know that we have change the configuration of the
5396 * network card
5397 */
5398 if ((STATUS & STATUS_LU) && RT_SUCCESS(rc))
5399 {
5400 STATUS &= ~STATUS_LU;
5401 Phy::setLinkStatus(&pState->phy, false);
5402 e1kRaiseInterrupt(pState, VERR_SEM_BUSY, ICR_LSC);
5403 /* Restore the link back in 5 second. */
5404 e1kArmTimer(pState, pState->pLUTimerR3, 5000000);
5405 }
5406
5407 PDMCritSectLeave(&pState->cs);
5408 return rc;
5409
5410}
5411
5412/**
5413 * @copydoc FNPDMDEVPOWEROFF
5414 */
5415static DECLCALLBACK(void) e1kPowerOff(PPDMDEVINS pDevIns)
5416{
5417 /* Poke thread waiting for buffer space. */
5418 e1kWakeupReceive(pDevIns);
5419}
5420
5421/**
5422 * @copydoc FNPDMDEVSUSPEND
5423 */
5424static DECLCALLBACK(void) e1kSuspend(PPDMDEVINS pDevIns)
5425{
5426 /* Poke thread waiting for buffer space. */
5427 e1kWakeupReceive(pDevIns);
5428}
5429
5430/**
5431 * Device relocation callback.
5432 *
5433 * When this callback is called the device instance data, and if the
5434 * device have a GC component, is being relocated, or/and the selectors
5435 * have been changed. The device must use the chance to perform the
5436 * necessary pointer relocations and data updates.
5437 *
5438 * Before the GC code is executed the first time, this function will be
5439 * called with a 0 delta so GC pointer calculations can be one in one place.
5440 *
5441 * @param pDevIns Pointer to the device instance.
5442 * @param offDelta The relocation delta relative to the old location.
5443 *
5444 * @remark A relocation CANNOT fail.
5445 */
5446static DECLCALLBACK(void) e1kRelocate(PPDMDEVINS pDevIns, RTGCINTPTR offDelta)
5447{
5448 E1KSTATE* pState = PDMINS_2_DATA(pDevIns, E1KSTATE*);
5449 pState->pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
5450 pState->pTxQueueRC = PDMQueueRCPtr(pState->pTxQueueR3);
5451 pState->pCanRxQueueRC = PDMQueueRCPtr(pState->pCanRxQueueR3);
5452#ifdef E1K_USE_RX_TIMERS
5453 pState->pRIDTimerRC = TMTimerRCPtr(pState->pRIDTimerR3);
5454 pState->pRADTimerRC = TMTimerRCPtr(pState->pRADTimerR3);
5455#endif /* E1K_USE_RX_TIMERS */
5456#ifdef E1K_USE_TX_TIMERS
5457 pState->pTIDTimerRC = TMTimerRCPtr(pState->pTIDTimerR3);
5458# ifndef E1K_NO_TAD
5459 pState->pTADTimerRC = TMTimerRCPtr(pState->pTADTimerR3);
5460# endif /* E1K_NO_TAD */
5461#endif /* E1K_USE_TX_TIMERS */
5462 pState->pIntTimerRC = TMTimerRCPtr(pState->pIntTimerR3);
5463 pState->pLUTimerRC = TMTimerRCPtr(pState->pLUTimerR3);
5464}
5465
5466/**
5467 * Destruct a device instance.
5468 *
5469 * We need to free non-VM resources only.
5470 *
5471 * @returns VBox status.
5472 * @param pDevIns The device instance data.
5473 * @thread EMT
5474 */
5475static DECLCALLBACK(int) e1kDestruct(PPDMDEVINS pDevIns)
5476{
5477 E1KSTATE* pState = PDMINS_2_DATA(pDevIns, E1KSTATE*);
5478 PDMDEV_CHECK_VERSIONS_RETURN_QUIET(pDevIns);
5479
5480 e1kDumpState(pState);
5481 E1kLog(("%s Destroying instance\n", INSTANCE(pState)));
5482 if (PDMCritSectIsInitialized(&pState->cs))
5483 {
5484 if (pState->hEventMoreRxDescAvail != NIL_RTSEMEVENT)
5485 {
5486 RTSemEventSignal(pState->hEventMoreRxDescAvail);
5487 RTSemEventDestroy(pState->hEventMoreRxDescAvail);
5488 pState->hEventMoreRxDescAvail = NIL_RTSEMEVENT;
5489 }
5490#ifndef E1K_GLOBAL_MUTEX
5491 PDMR3CritSectDelete(&pState->csRx);
5492 //PDMR3CritSectDelete(&pState->csTx);
5493#endif
5494 PDMR3CritSectDelete(&pState->cs);
5495 }
5496 return VINF_SUCCESS;
5497}
5498
5499/**
5500 * Sets 8-bit register in PCI configuration space.
5501 * @param refPciDev The PCI device.
5502 * @param uOffset The register offset.
5503 * @param u16Value The value to store in the register.
5504 * @thread EMT
5505 */
5506DECLINLINE(void) e1kPCICfgSetU8(PCIDEVICE& refPciDev, uint32_t uOffset, uint8_t u8Value)
5507{
5508 Assert(uOffset < sizeof(refPciDev.config));
5509 refPciDev.config[uOffset] = u8Value;
5510}
5511
5512/**
5513 * Sets 16-bit register in PCI configuration space.
5514 * @param refPciDev The PCI device.
5515 * @param uOffset The register offset.
5516 * @param u16Value The value to store in the register.
5517 * @thread EMT
5518 */
5519DECLINLINE(void) e1kPCICfgSetU16(PCIDEVICE& refPciDev, uint32_t uOffset, uint16_t u16Value)
5520{
5521 Assert(uOffset+sizeof(u16Value) <= sizeof(refPciDev.config));
5522 *(uint16_t*)&refPciDev.config[uOffset] = u16Value;
5523}
5524
5525/**
5526 * Sets 32-bit register in PCI configuration space.
5527 * @param refPciDev The PCI device.
5528 * @param uOffset The register offset.
5529 * @param u32Value The value to store in the register.
5530 * @thread EMT
5531 */
5532DECLINLINE(void) e1kPCICfgSetU32(PCIDEVICE& refPciDev, uint32_t uOffset, uint32_t u32Value)
5533{
5534 Assert(uOffset+sizeof(u32Value) <= sizeof(refPciDev.config));
5535 *(uint32_t*)&refPciDev.config[uOffset] = u32Value;
5536}
5537
5538/**
5539 * Set PCI configuration space registers.
5540 *
5541 * @param pci Reference to PCI device structure.
5542 * @thread EMT
5543 */
5544static DECLCALLBACK(void) e1kConfigurePCI(PCIDEVICE& pci, E1KCHIP eChip)
5545{
5546 Assert(eChip < RT_ELEMENTS(g_Chips));
5547 /* Configure PCI Device, assume 32-bit mode ******************************/
5548 PCIDevSetVendorId(&pci, g_Chips[eChip].uPCIVendorId);
5549 PCIDevSetDeviceId(&pci, g_Chips[eChip].uPCIDeviceId);
5550 e1kPCICfgSetU16(pci, VBOX_PCI_SUBSYSTEM_VENDOR_ID, g_Chips[eChip].uPCISubsystemVendorId);
5551 e1kPCICfgSetU16(pci, VBOX_PCI_SUBSYSTEM_ID, g_Chips[eChip].uPCISubsystemId);
5552
5553 e1kPCICfgSetU16(pci, VBOX_PCI_COMMAND, 0x0000);
5554 /* DEVSEL Timing (medium device), 66 MHz Capable, New capabilities */
5555 e1kPCICfgSetU16(pci, VBOX_PCI_STATUS,
5556 VBOX_PCI_STATUS_DEVSEL_MEDIUM | VBOX_PCI_STATUS_CAP_LIST | VBOX_PCI_STATUS_66MHZ);
5557 /* Stepping A2 */
5558 e1kPCICfgSetU8( pci, VBOX_PCI_REVISION_ID, 0x02);
5559 /* Ethernet adapter */
5560 e1kPCICfgSetU8( pci, VBOX_PCI_CLASS_PROG, 0x00);
5561 e1kPCICfgSetU16(pci, VBOX_PCI_CLASS_DEVICE, 0x0200);
5562 /* normal single function Ethernet controller */
5563 e1kPCICfgSetU8( pci, VBOX_PCI_HEADER_TYPE, 0x00);
5564 /* Memory Register Base Address */
5565 e1kPCICfgSetU32(pci, VBOX_PCI_BASE_ADDRESS_0, 0x00000000);
5566 /* Memory Flash Base Address */
5567 e1kPCICfgSetU32(pci, VBOX_PCI_BASE_ADDRESS_1, 0x00000000);
5568 /* IO Register Base Address */
5569 e1kPCICfgSetU32(pci, VBOX_PCI_BASE_ADDRESS_2, 0x00000001);
5570 /* Expansion ROM Base Address */
5571 e1kPCICfgSetU32(pci, VBOX_PCI_ROM_ADDRESS, 0x00000000);
5572 /* Capabilities Pointer */
5573 e1kPCICfgSetU8( pci, VBOX_PCI_CAPABILITY_LIST, 0xDC);
5574 /* Interrupt Pin: INTA# */
5575 e1kPCICfgSetU8( pci, VBOX_PCI_INTERRUPT_PIN, 0x01);
5576 /* Max_Lat/Min_Gnt: very high priority and time slice */
5577 e1kPCICfgSetU8( pci, VBOX_PCI_MIN_GNT, 0xFF);
5578 e1kPCICfgSetU8( pci, VBOX_PCI_MAX_LAT, 0x00);
5579
5580 /* PCI Power Management Registers ****************************************/
5581 /* Capability ID: PCI Power Management Registers */
5582 e1kPCICfgSetU8( pci, 0xDC, VBOX_PCI_CAP_ID_PM);
5583 /* Next Item Pointer: PCI-X */
5584 e1kPCICfgSetU8( pci, 0xDC + 1, 0xE4);
5585 /* Power Management Capabilities: PM disabled, DSI */
5586 e1kPCICfgSetU16(pci, 0xDC + 2,
5587 0x0002 | VBOX_PCI_PM_CAP_DSI);
5588 /* Power Management Control / Status Register: PM disabled */
5589 e1kPCICfgSetU16(pci, 0xDC + 4, 0x0000);
5590 /* PMCSR_BSE Bridge Support Extensions: Not supported */
5591 e1kPCICfgSetU8( pci, 0xDC + 6, 0x00);
5592 /* Data Register: PM disabled, always 0 */
5593 e1kPCICfgSetU8( pci, 0xDC + 7, 0x00);
5594
5595 /* PCI-X Configuration Registers *****************************************/
5596 /* Capability ID: PCI-X Configuration Registers */
5597 e1kPCICfgSetU8( pci, 0xE4, VBOX_PCI_CAP_ID_PCIX);
5598#ifdef E1K_WITH_MSI
5599 e1kPCICfgSetU8( pci, 0xE4 + 1, 0x80);
5600#else
5601 /* Next Item Pointer: None (Message Signalled Interrupts are disabled) */
5602 e1kPCICfgSetU8( pci, 0xE4 + 1, 0x00);
5603#endif
5604 /* PCI-X Command: Enable Relaxed Ordering */
5605 e1kPCICfgSetU16(pci, 0xE4 + 2, VBOX_PCI_X_CMD_ERO);
5606 /* PCI-X Status: 32-bit, 66MHz*/
5607 /// @todo: is this value really correct? fff8 doesn't look like actual PCI address
5608 e1kPCICfgSetU32(pci, 0xE4 + 4, 0x0040FFF8);
5609}
5610
5611/**
5612 * @interface_method_impl{PDMDEVREG,pfnConstruct}
5613 */
5614static DECLCALLBACK(int) e1kConstruct(PPDMDEVINS pDevIns, int iInstance, PCFGMNODE pCfg)
5615{
5616 E1KSTATE* pState = PDMINS_2_DATA(pDevIns, E1KSTATE*);
5617 int rc;
5618 PDMDEV_CHECK_VERSIONS_RETURN(pDevIns);
5619
5620 /* Init handles and log related stuff. */
5621 RTStrPrintf(pState->szInstance, sizeof(pState->szInstance), "E1000#%d", iInstance);
5622 E1kLog(("%s Constructing new instance sizeof(E1KRXDESC)=%d\n", INSTANCE(pState), sizeof(E1KRXDESC)));
5623 pState->hEventMoreRxDescAvail = NIL_RTSEMEVENT;
5624
5625 /*
5626 * Validate configuration.
5627 */
5628 if (!CFGMR3AreValuesValid(pCfg, "MAC\0" "CableConnected\0" "AdapterType\0" "LineSpeed\0"))
5629 return PDMDEV_SET_ERROR(pDevIns, VERR_PDM_DEVINS_UNKNOWN_CFG_VALUES,
5630 N_("Invalid configuration for E1000 device"));
5631
5632 /** @todo: LineSpeed unused! */
5633
5634 /* Get config params */
5635 rc = CFGMR3QueryBytes(pCfg, "MAC", pState->macConfigured.au8,
5636 sizeof(pState->macConfigured.au8));
5637 if (RT_FAILURE(rc))
5638 return PDMDEV_SET_ERROR(pDevIns, rc,
5639 N_("Configuration error: Failed to get MAC address"));
5640 rc = CFGMR3QueryBool(pCfg, "CableConnected", &pState->fCableConnected);
5641 if (RT_FAILURE(rc))
5642 return PDMDEV_SET_ERROR(pDevIns, rc,
5643 N_("Configuration error: Failed to get the value of 'CableConnected'"));
5644 rc = CFGMR3QueryU32(pCfg, "AdapterType", (uint32_t*)&pState->eChip);
5645 if (RT_FAILURE(rc))
5646 return PDMDEV_SET_ERROR(pDevIns, rc,
5647 N_("Configuration error: Failed to get the value of 'AdapterType'"));
5648 Assert(pState->eChip <= E1K_CHIP_82545EM);
5649
5650 E1kLog(("%s Chip=%s\n", INSTANCE(pState), g_Chips[pState->eChip].pcszName));
5651
5652 /* Initialize state structure */
5653 pState->fR0Enabled = true;
5654 pState->fGCEnabled = true;
5655 pState->pDevInsR3 = pDevIns;
5656 pState->pDevInsR0 = PDMDEVINS_2_R0PTR(pDevIns);
5657 pState->pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
5658 pState->u16TxPktLen = 0;
5659 pState->fIPcsum = false;
5660 pState->fTCPcsum = false;
5661 pState->fIntMaskUsed = false;
5662 pState->fDelayInts = false;
5663 pState->fLocked = false;
5664 pState->u64AckedAt = 0;
5665 pState->led.u32Magic = PDMLED_MAGIC;
5666 pState->u32PktNo = 1;
5667
5668#ifdef E1K_INT_STATS
5669 pState->uStatInt = 0;
5670 pState->uStatIntTry = 0;
5671 pState->uStatIntLower = 0;
5672 pState->uStatIntDly = 0;
5673 pState->uStatDisDly = 0;
5674 pState->iStatIntLost = 0;
5675 pState->iStatIntLostOne = 0;
5676 pState->uStatIntLate = 0;
5677 pState->uStatIntMasked = 0;
5678 pState->uStatIntEarly = 0;
5679 pState->uStatIntRx = 0;
5680 pState->uStatIntTx = 0;
5681 pState->uStatIntICS = 0;
5682 pState->uStatIntRDTR = 0;
5683 pState->uStatIntRXDMT0 = 0;
5684 pState->uStatIntTXQE = 0;
5685 pState->uStatTxNoRS = 0;
5686 pState->uStatTxIDE = 0;
5687 pState->uStatTAD = 0;
5688 pState->uStatTID = 0;
5689 pState->uStatRAD = 0;
5690 pState->uStatRID = 0;
5691 pState->uStatRxFrm = 0;
5692 pState->uStatTxFrm = 0;
5693 pState->uStatDescCtx = 0;
5694 pState->uStatDescDat = 0;
5695 pState->uStatDescLeg = 0;
5696#endif /* E1K_INT_STATS */
5697
5698 /* Interfaces */
5699 pState->IBase.pfnQueryInterface = e1kQueryInterface;
5700
5701 pState->INetworkDown.pfnWaitReceiveAvail = e1kNetworkDown_WaitReceiveAvail;
5702 pState->INetworkDown.pfnReceive = e1kNetworkDown_Receive;
5703 pState->INetworkDown.pfnXmitPending = e1kNetworkDown_XmitPending;
5704
5705 pState->ILeds.pfnQueryStatusLed = e1kQueryStatusLed;
5706
5707 pState->INetworkConfig.pfnGetMac = e1kGetMac;
5708 pState->INetworkConfig.pfnGetLinkState = e1kGetLinkState;
5709 pState->INetworkConfig.pfnSetLinkState = e1kSetLinkState;
5710
5711 /* Initialize the EEPROM */
5712 pState->eeprom.init(pState->macConfigured);
5713
5714 /* Initialize internal PHY */
5715 Phy::init(&pState->phy, iInstance,
5716 pState->eChip == E1K_CHIP_82543GC?
5717 PHY_EPID_M881000 : PHY_EPID_M881011);
5718 Phy::setLinkStatus(&pState->phy, pState->fCableConnected);
5719
5720 rc = PDMDevHlpSSMRegisterEx(pDevIns, E1K_SAVEDSTATE_VERSION, sizeof(E1KSTATE), NULL,
5721 NULL, e1kLiveExec, NULL,
5722 e1kSavePrep, e1kSaveExec, NULL,
5723 e1kLoadPrep, e1kLoadExec, e1kLoadDone);
5724 if (RT_FAILURE(rc))
5725 return rc;
5726
5727 /* Initialize critical section */
5728 rc = PDMDevHlpCritSectInit(pDevIns, &pState->cs, RT_SRC_POS, "%s", pState->szInstance);
5729 if (RT_FAILURE(rc))
5730 return rc;
5731#ifndef E1K_GLOBAL_MUTEX
5732 rc = PDMDevHlpCritSectInit(pDevIns, &pState->csRx, RT_SRC_POS, "%sRX", pState->szInstance);
5733 if (RT_FAILURE(rc))
5734 return rc;
5735#endif
5736
5737 /* Set PCI config registers */
5738 e1kConfigurePCI(pState->pciDevice, pState->eChip);
5739 /* Register PCI device */
5740 rc = PDMDevHlpPCIRegister(pDevIns, &pState->pciDevice);
5741 if (RT_FAILURE(rc))
5742 return rc;
5743
5744#ifdef E1K_WITH_MSI
5745 PDMMSIREG aMsiReg;
5746 aMsiReg.cVectors = 1;
5747 aMsiReg.iCapOffset = 0x80;
5748 aMsiReg.iNextOffset = 0x0;
5749 aMsiReg.iMsiFlags = 0;
5750 rc = PDMDevHlpPCIRegisterMsi(pDevIns, &aMsiReg);
5751 AssertRC(rc);
5752 if (RT_FAILURE (rc))
5753 return rc;
5754#endif
5755
5756
5757 /* Map our registers to memory space (region 0, see e1kConfigurePCI)*/
5758 rc = PDMDevHlpPCIIORegionRegister(pDevIns, 0, E1K_MM_SIZE,
5759 PCI_ADDRESS_SPACE_MEM, e1kMap);
5760 if (RT_FAILURE(rc))
5761 return rc;
5762 /* Map our registers to IO space (region 2, see e1kConfigurePCI) */
5763 rc = PDMDevHlpPCIIORegionRegister(pDevIns, 2, E1K_IOPORT_SIZE,
5764 PCI_ADDRESS_SPACE_IO, e1kMap);
5765 if (RT_FAILURE(rc))
5766 return rc;
5767
5768 /* Create transmit queue */
5769 rc = PDMDevHlpQueueCreate(pDevIns, sizeof(PDMQUEUEITEMCORE), 1, 0,
5770 e1kTxQueueConsumer, true, "E1000-Xmit", &pState->pTxQueueR3);
5771 if (RT_FAILURE(rc))
5772 return rc;
5773 pState->pTxQueueR0 = PDMQueueR0Ptr(pState->pTxQueueR3);
5774 pState->pTxQueueRC = PDMQueueRCPtr(pState->pTxQueueR3);
5775
5776 /* Create the RX notifier signaller. */
5777 rc = PDMDevHlpQueueCreate(pDevIns, sizeof(PDMQUEUEITEMCORE), 1, 0,
5778 e1kCanRxQueueConsumer, true, "E1000-Rcv", &pState->pCanRxQueueR3);
5779 if (RT_FAILURE(rc))
5780 return rc;
5781 pState->pCanRxQueueR0 = PDMQueueR0Ptr(pState->pCanRxQueueR3);
5782 pState->pCanRxQueueRC = PDMQueueRCPtr(pState->pCanRxQueueR3);
5783
5784#ifdef E1K_USE_TX_TIMERS
5785 /* Create Transmit Interrupt Delay Timer */
5786 rc = PDMDevHlpTMTimerCreate(pDevIns, TMCLOCK_VIRTUAL, e1kTxIntDelayTimer, pState,
5787 TMTIMER_FLAGS_DEFAULT_CRIT_SECT, /** @todo check locking here. */
5788 "E1000 Transmit Interrupt Delay Timer", &pState->pTIDTimerR3);
5789 if (RT_FAILURE(rc))
5790 return rc;
5791 pState->pTIDTimerR0 = TMTimerR0Ptr(pState->pTIDTimerR3);
5792 pState->pTIDTimerRC = TMTimerRCPtr(pState->pTIDTimerR3);
5793
5794# ifndef E1K_NO_TAD
5795 /* Create Transmit Absolute Delay Timer */
5796 rc = PDMDevHlpTMTimerCreate(pDevIns, TMCLOCK_VIRTUAL, e1kTxAbsDelayTimer, pState,
5797 TMTIMER_FLAGS_DEFAULT_CRIT_SECT, /** @todo check locking here. */
5798 "E1000 Transmit Absolute Delay Timer", &pState->pTADTimerR3);
5799 if (RT_FAILURE(rc))
5800 return rc;
5801 pState->pTADTimerR0 = TMTimerR0Ptr(pState->pTADTimerR3);
5802 pState->pTADTimerRC = TMTimerRCPtr(pState->pTADTimerR3);
5803# endif /* E1K_NO_TAD */
5804#endif /* E1K_USE_TX_TIMERS */
5805
5806#ifdef E1K_USE_RX_TIMERS
5807 /* Create Receive Interrupt Delay Timer */
5808 rc = PDMDevHlpTMTimerCreate(pDevIns, TMCLOCK_VIRTUAL, e1kRxIntDelayTimer, pState,
5809 TMTIMER_FLAGS_DEFAULT_CRIT_SECT, /** @todo check locking here. */
5810 "E1000 Receive Interrupt Delay Timer", &pState->pRIDTimerR3);
5811 if (RT_FAILURE(rc))
5812 return rc;
5813 pState->pRIDTimerR0 = TMTimerR0Ptr(pState->pRIDTimerR3);
5814 pState->pRIDTimerRC = TMTimerRCPtr(pState->pRIDTimerR3);
5815
5816 /* Create Receive Absolute Delay Timer */
5817 rc = PDMDevHlpTMTimerCreate(pDevIns, TMCLOCK_VIRTUAL, e1kRxAbsDelayTimer, pState,
5818 TMTIMER_FLAGS_DEFAULT_CRIT_SECT, /** @todo check locking here. */
5819 "E1000 Receive Absolute Delay Timer", &pState->pRADTimerR3);
5820 if (RT_FAILURE(rc))
5821 return rc;
5822 pState->pRADTimerR0 = TMTimerR0Ptr(pState->pRADTimerR3);
5823 pState->pRADTimerRC = TMTimerRCPtr(pState->pRADTimerR3);
5824#endif /* E1K_USE_RX_TIMERS */
5825
5826 /* Create Late Interrupt Timer */
5827 rc = PDMDevHlpTMTimerCreate(pDevIns, TMCLOCK_VIRTUAL, e1kLateIntTimer, pState,
5828 TMTIMER_FLAGS_DEFAULT_CRIT_SECT, /** @todo check locking here. */
5829 "E1000 Late Interrupt Timer", &pState->pIntTimerR3);
5830 if (RT_FAILURE(rc))
5831 return rc;
5832 pState->pIntTimerR0 = TMTimerR0Ptr(pState->pIntTimerR3);
5833 pState->pIntTimerRC = TMTimerRCPtr(pState->pIntTimerR3);
5834
5835 /* Create Link Up Timer */
5836 rc = PDMDevHlpTMTimerCreate(pDevIns, TMCLOCK_VIRTUAL, e1kLinkUpTimer, pState,
5837 TMTIMER_FLAGS_DEFAULT_CRIT_SECT, /** @todo check locking here. */
5838 "E1000 Link Up Timer", &pState->pLUTimerR3);
5839 if (RT_FAILURE(rc))
5840 return rc;
5841 pState->pLUTimerR0 = TMTimerR0Ptr(pState->pLUTimerR3);
5842 pState->pLUTimerRC = TMTimerRCPtr(pState->pLUTimerR3);
5843
5844 /* Status driver */
5845 PPDMIBASE pBase;
5846 rc = PDMDevHlpDriverAttach(pDevIns, PDM_STATUS_LUN, &pState->IBase, &pBase, "Status Port");
5847 if (RT_FAILURE(rc))
5848 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Failed to attach the status LUN"));
5849 pState->pLedsConnector = PDMIBASE_QUERY_INTERFACE(pBase, PDMILEDCONNECTORS);
5850
5851 rc = PDMDevHlpDriverAttach(pDevIns, 0, &pState->IBase, &pState->pDrvBase, "Network Port");
5852 if (RT_SUCCESS(rc))
5853 {
5854 if (rc == VINF_NAT_DNS)
5855 {
5856 PDMDevHlpVMSetRuntimeError(pDevIns, 0 /*fFlags*/, "NoDNSforNAT",
5857 N_("A Domain Name Server (DNS) for NAT networking could not be determined. Ensure that your host is correctly connected to an ISP. If you ignore this warning the guest will not be able to perform nameserver lookups and it will probably observe delays if trying so"));
5858 }
5859 pState->pDrvR3 = PDMIBASE_QUERY_INTERFACE(pState->pDrvBase, PDMINETWORKUP);
5860 AssertMsgReturn(pState->pDrvR3, ("Failed to obtain the PDMINETWORKUP interface!\n"),
5861 VERR_PDM_MISSING_INTERFACE_BELOW);
5862
5863 pState->pDrvR0 = PDMIBASER0_QUERY_INTERFACE(PDMIBASE_QUERY_INTERFACE(pState->pDrvBase, PDMIBASER0), PDMINETWORKUP);
5864 pState->pDrvRC = PDMIBASERC_QUERY_INTERFACE(PDMIBASE_QUERY_INTERFACE(pState->pDrvBase, PDMIBASERC), PDMINETWORKUP);
5865 }
5866 else if ( rc == VERR_PDM_NO_ATTACHED_DRIVER
5867 || rc == VERR_PDM_CFG_MISSING_DRIVER_NAME)
5868 {
5869 /* No error! */
5870 E1kLog(("%s This adapter is not attached to any network!\n", INSTANCE(pState)));
5871 }
5872 else
5873 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Failed to attach the network LUN"));
5874
5875 rc = RTSemEventCreate(&pState->hEventMoreRxDescAvail);
5876 if (RT_FAILURE(rc))
5877 return rc;
5878
5879 e1kHardReset(pState);
5880
5881#if defined(VBOX_WITH_STATISTICS) || defined(E1K_REL_STATS)
5882 PDMDevHlpSTAMRegisterF(pDevIns, &pState->StatMMIOReadRZ, STAMTYPE_PROFILE, STAMVISIBILITY_ALWAYS, STAMUNIT_TICKS_PER_CALL, "Profiling MMIO reads in RZ", "/Devices/E1k%d/MMIO/ReadRZ", iInstance);
5883 PDMDevHlpSTAMRegisterF(pDevIns, &pState->StatMMIOReadR3, STAMTYPE_PROFILE, STAMVISIBILITY_ALWAYS, STAMUNIT_TICKS_PER_CALL, "Profiling MMIO reads in R3", "/Devices/E1k%d/MMIO/ReadR3", iInstance);
5884 PDMDevHlpSTAMRegisterF(pDevIns, &pState->StatMMIOWriteRZ, STAMTYPE_PROFILE, STAMVISIBILITY_ALWAYS, STAMUNIT_TICKS_PER_CALL, "Profiling MMIO writes in RZ", "/Devices/E1k%d/MMIO/WriteRZ", iInstance);
5885 PDMDevHlpSTAMRegisterF(pDevIns, &pState->StatMMIOWriteR3, STAMTYPE_PROFILE, STAMVISIBILITY_ALWAYS, STAMUNIT_TICKS_PER_CALL, "Profiling MMIO writes in R3", "/Devices/E1k%d/MMIO/WriteR3", iInstance);
5886 PDMDevHlpSTAMRegisterF(pDevIns, &pState->StatEEPROMRead, STAMTYPE_PROFILE, STAMVISIBILITY_ALWAYS, STAMUNIT_TICKS_PER_CALL, "Profiling EEPROM reads", "/Devices/E1k%d/EEPROM/Read", iInstance);
5887 PDMDevHlpSTAMRegisterF(pDevIns, &pState->StatEEPROMWrite, STAMTYPE_PROFILE, STAMVISIBILITY_ALWAYS, STAMUNIT_TICKS_PER_CALL, "Profiling EEPROM writes", "/Devices/E1k%d/EEPROM/Write", iInstance);
5888 PDMDevHlpSTAMRegisterF(pDevIns, &pState->StatIOReadRZ, STAMTYPE_PROFILE, STAMVISIBILITY_ALWAYS, STAMUNIT_TICKS_PER_CALL, "Profiling IO reads in RZ", "/Devices/E1k%d/IO/ReadRZ", iInstance);
5889 PDMDevHlpSTAMRegisterF(pDevIns, &pState->StatIOReadR3, STAMTYPE_PROFILE, STAMVISIBILITY_ALWAYS, STAMUNIT_TICKS_PER_CALL, "Profiling IO reads in R3", "/Devices/E1k%d/IO/ReadR3", iInstance);
5890 PDMDevHlpSTAMRegisterF(pDevIns, &pState->StatIOWriteRZ, STAMTYPE_PROFILE, STAMVISIBILITY_ALWAYS, STAMUNIT_TICKS_PER_CALL, "Profiling IO writes in RZ", "/Devices/E1k%d/IO/WriteRZ", iInstance);
5891 PDMDevHlpSTAMRegisterF(pDevIns, &pState->StatIOWriteR3, STAMTYPE_PROFILE, STAMVISIBILITY_ALWAYS, STAMUNIT_TICKS_PER_CALL, "Profiling IO writes in R3", "/Devices/E1k%d/IO/WriteR3", iInstance);
5892 PDMDevHlpSTAMRegisterF(pDevIns, &pState->StatLateIntTimer, STAMTYPE_PROFILE, STAMVISIBILITY_ALWAYS, STAMUNIT_TICKS_PER_CALL, "Profiling late int timer", "/Devices/E1k%d/LateInt/Timer", iInstance);
5893 PDMDevHlpSTAMRegisterF(pDevIns, &pState->StatLateInts, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, "Number of late interrupts", "/Devices/E1k%d/LateInt/Occured", iInstance);
5894 PDMDevHlpSTAMRegisterF(pDevIns, &pState->StatIntsRaised, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, "Number of raised interrupts", "/Devices/E1k%d/Interrupts/Raised", iInstance);
5895 PDMDevHlpSTAMRegisterF(pDevIns, &pState->StatIntsPrevented, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, "Number of prevented interrupts", "/Devices/E1k%d/Interrupts/Prevented", iInstance);
5896 PDMDevHlpSTAMRegisterF(pDevIns, &pState->StatReceive, STAMTYPE_PROFILE, STAMVISIBILITY_ALWAYS, STAMUNIT_TICKS_PER_CALL, "Profiling receive", "/Devices/E1k%d/Receive/Total", iInstance);
5897 PDMDevHlpSTAMRegisterF(pDevIns, &pState->StatReceiveFilter, STAMTYPE_PROFILE, STAMVISIBILITY_ALWAYS, STAMUNIT_TICKS_PER_CALL, "Profiling receive filtering", "/Devices/E1k%d/Receive/Filter", iInstance);
5898 PDMDevHlpSTAMRegisterF(pDevIns, &pState->StatReceiveStore, STAMTYPE_PROFILE, STAMVISIBILITY_ALWAYS, STAMUNIT_TICKS_PER_CALL, "Profiling receive storing", "/Devices/E1k%d/Receive/Store", iInstance);
5899 PDMDevHlpSTAMRegisterF(pDevIns, &pState->StatRxOverflow, STAMTYPE_PROFILE, STAMVISIBILITY_ALWAYS, STAMUNIT_TICKS_PER_OCCURENCE, "Profiling RX overflows", "/Devices/E1k%d/RxOverflow", iInstance);
5900 PDMDevHlpSTAMRegisterF(pDevIns, &pState->StatRxOverflowWakeup, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, "Nr of RX overflow wakeups", "/Devices/E1k%d/RxOverflowWakeup", iInstance);
5901#endif /* VBOX_WITH_STATISTICS || E1K_REL_STATS */
5902 PDMDevHlpSTAMRegisterF(pDevIns, &pState->StatReceiveBytes, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_BYTES, "Amount of data received", "/Devices/E1k%d/ReceiveBytes", iInstance);
5903#if defined(VBOX_WITH_STATISTICS) || defined(E1K_REL_STATS)
5904 PDMDevHlpSTAMRegisterF(pDevIns, &pState->StatTransmitRZ, STAMTYPE_PROFILE, STAMVISIBILITY_ALWAYS, STAMUNIT_TICKS_PER_CALL, "Profiling transmits in RZ", "/Devices/E1k%d/Transmit/TotalRZ", iInstance);
5905 PDMDevHlpSTAMRegisterF(pDevIns, &pState->StatTransmitR3, STAMTYPE_PROFILE, STAMVISIBILITY_ALWAYS, STAMUNIT_TICKS_PER_CALL, "Profiling transmits in R3", "/Devices/E1k%d/Transmit/TotalR3", iInstance);
5906#endif /* VBOX_WITH_STATISTICS || E1K_REL_STATS */
5907 PDMDevHlpSTAMRegisterF(pDevIns, &pState->StatTransmitBytes, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_BYTES, "Amount of data transmitted", "/Devices/E1k%d/TransmitBytes", iInstance);
5908#if defined(VBOX_WITH_STATISTICS) || defined(E1K_REL_STATS)
5909 PDMDevHlpSTAMRegisterF(pDevIns, &pState->StatTransmitSendRZ, STAMTYPE_PROFILE, STAMVISIBILITY_ALWAYS, STAMUNIT_TICKS_PER_CALL, "Profiling send transmit in RZ", "/Devices/E1k%d/Transmit/SendRZ", iInstance);
5910 PDMDevHlpSTAMRegisterF(pDevIns, &pState->StatTransmitSendR3, STAMTYPE_PROFILE, STAMVISIBILITY_ALWAYS, STAMUNIT_TICKS_PER_CALL, "Profiling send transmit in R3", "/Devices/E1k%d/Transmit/SendR3", iInstance);
5911
5912 PDMDevHlpSTAMRegisterF(pDevIns, &pState->StatTxDescCtxNormal, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, "Number of normal context descriptors","/Devices/E1k%d/TxDesc/ContexNormal", iInstance);
5913 PDMDevHlpSTAMRegisterF(pDevIns, &pState->StatTxDescCtxTSE, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, "Number of TSE context descriptors", "/Devices/E1k%d/TxDesc/ContextTSE", iInstance);
5914 PDMDevHlpSTAMRegisterF(pDevIns, &pState->StatTxDescData, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, "Number of TX data descriptors", "/Devices/E1k%d/TxDesc/Data", iInstance);
5915 PDMDevHlpSTAMRegisterF(pDevIns, &pState->StatTxDescLegacy, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, "Number of TX legacy descriptors", "/Devices/E1k%d/TxDesc/Legacy", iInstance);
5916 PDMDevHlpSTAMRegisterF(pDevIns, &pState->StatTxDescTSEData, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, "Number of TX TSE data descriptors", "/Devices/E1k%d/TxDesc/TSEData", iInstance);
5917 PDMDevHlpSTAMRegisterF(pDevIns, &pState->StatTxPathFallback, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, "Fallback TSE descriptor path", "/Devices/E1k%d/TxPath/Fallback", iInstance);
5918 PDMDevHlpSTAMRegisterF(pDevIns, &pState->StatTxPathGSO, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, "GSO TSE descriptor path", "/Devices/E1k%d/TxPath/GSO", iInstance);
5919 PDMDevHlpSTAMRegisterF(pDevIns, &pState->StatTxPathRegular, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, "Regular descriptor path", "/Devices/E1k%d/TxPath/Normal", iInstance);
5920 PDMDevHlpSTAMRegisterF(pDevIns, &pState->StatPHYAccesses, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, "Number of PHY accesses", "/Devices/E1k%d/PHYAccesses", iInstance);
5921#endif /* VBOX_WITH_STATISTICS || E1K_REL_STATS */
5922
5923 return VINF_SUCCESS;
5924}
5925
5926/**
5927 * The device registration structure.
5928 */
5929const PDMDEVREG g_DeviceE1000 =
5930{
5931 /* Structure version. PDM_DEVREG_VERSION defines the current version. */
5932 PDM_DEVREG_VERSION,
5933 /* Device name. */
5934 "e1000",
5935 /* Name of guest context module (no path).
5936 * Only evalutated if PDM_DEVREG_FLAGS_RC is set. */
5937 "VBoxDDGC.gc",
5938 /* Name of ring-0 module (no path).
5939 * Only evalutated if PDM_DEVREG_FLAGS_RC is set. */
5940 "VBoxDDR0.r0",
5941 /* The description of the device. The UTF-8 string pointed to shall, like this structure,
5942 * remain unchanged from registration till VM destruction. */
5943 "Intel PRO/1000 MT Desktop Ethernet.\n",
5944
5945 /* Flags, combination of the PDM_DEVREG_FLAGS_* \#defines. */
5946 PDM_DEVREG_FLAGS_DEFAULT_BITS | PDM_DEVREG_FLAGS_RC | PDM_DEVREG_FLAGS_R0,
5947 /* Device class(es), combination of the PDM_DEVREG_CLASS_* \#defines. */
5948 PDM_DEVREG_CLASS_NETWORK,
5949 /* Maximum number of instances (per VM). */
5950 8,
5951 /* Size of the instance data. */
5952 sizeof(E1KSTATE),
5953
5954 /* Construct instance - required. */
5955 e1kConstruct,
5956 /* Destruct instance - optional. */
5957 e1kDestruct,
5958 /* Relocation command - optional. */
5959 e1kRelocate,
5960 /* I/O Control interface - optional. */
5961 NULL,
5962 /* Power on notification - optional. */
5963 NULL,
5964 /* Reset notification - optional. */
5965 NULL,
5966 /* Suspend notification - optional. */
5967 e1kSuspend,
5968 /* Resume notification - optional. */
5969 NULL,
5970 /* Attach command - optional. */
5971 e1kAttach,
5972 /* Detach notification - optional. */
5973 e1kDetach,
5974 /* Query a LUN base interface - optional. */
5975 NULL,
5976 /* Init complete notification - optional. */
5977 NULL,
5978 /* Power off notification - optional. */
5979 e1kPowerOff,
5980 /* pfnSoftReset */
5981 NULL,
5982 /* u32VersionEnd */
5983 PDM_DEVREG_VERSION
5984};
5985
5986#endif /* IN_RING3 */
5987#endif /* !VBOX_DEVICE_STRUCT_TESTCASE */
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