VirtualBox

source: vbox/trunk/src/VBox/Devices/Graphics/vmsvga_include/svga3d_shaderdefs.h@ 97441

Last change on this file since 97441 was 96407, checked in by vboxsync, 2 years ago

scm copyright and license note update
  • Property svn:eol-style set to native
File size: 14.6 KB
Line 
1/**********************************************************
2 * Copyright 2007-2014 VMware, Inc. All rights reserved.
3 *
4 * Permission is hereby granted, free of charge, to any person
5 * obtaining a copy of this software and associated documentation
6 * files (the "Software"), to deal in the Software without
7 * restriction, including without limitation the rights to use, copy,
8 * modify, merge, publish, distribute, sublicense, and/or sell copies
9 * of the Software, and to permit persons to whom the Software is
10 * furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice shall be
13 * included in all copies or substantial portions of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
16 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
17 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
18 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
19 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
20 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
21 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
22 * SOFTWARE.
23 *
24 **********************************************************/
25
26/*
27 * svga3d_shaderdefs.h --
28 *
29 * SVGA3D byte code format and limit definitions.
30 *
31 * The format of the byte code directly corresponds to that defined
32 * by Microsoft DirectX SDK 9.0c (file d3d9types.h). The format can
33 * also be extended so that different shader formats can be supported
34 * for example GLSL, ARB vp/fp, NV/ATI shader formats, etc.
35 *
36 */
37
38#ifndef __SVGA3D_SHADER_DEFS__
39#define __SVGA3D_SHADER_DEFS__
40
41/* SVGA3D shader hardware limits. */
42
43#define SVGA3D_INPUTREG_MAX 16
44#define SVGA3D_OUTPUTREG_MAX 12
45#define SVGA3D_VERTEX_SAMPLERREG_MAX 4
46#define SVGA3D_PIXEL_SAMPLERREG_MAX 16
47#define SVGA3D_SAMPLERREG_MAX (SVGA3D_PIXEL_SAMPLERREG_MAX+\
48 SVGA3D_VERTEX_SAMPLERREG_MAX)
49#define SVGA3D_TEMPREG_MAX 32
50#define SVGA3D_CONSTREG_MAX 256
51#define SVGA3D_CONSTINTREG_MAX 16
52#define SVGA3D_CONSTBOOLREG_MAX 16
53#define SVGA3D_ADDRREG_MAX 1
54#define SVGA3D_PREDREG_MAX 1
55
56/* SVGA3D byte code specific limits */
57
58#define SVGA3D_MAX_SRC_REGS 4
59#define SVGA3D_MAX_NESTING_LEVEL 32
60
61/* SVGA3D version information. */
62
63#define SVGA3D_VS_TYPE 0xFFFE
64#define SVGA3D_PS_TYPE 0xFFFF
65
66typedef struct {
67 union {
68 struct {
69 uint32 minor : 8;
70 uint32 major : 8;
71 uint32 type : 16;
72 };
73
74 uint32 value;
75 };
76} SVGA3dShaderVersion;
77
78#define SVGA3D_VS_10 ((SVGA3D_VS_TYPE << 16) | 1 << 8)
79#define SVGA3D_VS_11 (SVGA3D_VS_10 | 1)
80#define SVGA3D_VS_20 ((SVGA3D_VS_TYPE << 16) | 2 << 8)
81#define SVGA3D_VS_21 (SVGA3D_VS_20 | 1)
82#define SVGA3D_VS_30 ((SVGA3D_VS_TYPE << 16) | 3 << 8)
83
84#define SVGA3D_PS_10 ((SVGA3D_PS_TYPE << 16) | 1 << 8)
85#define SVGA3D_PS_11 (SVGA3D_PS_10 | 1)
86#define SVGA3D_PS_12 (SVGA3D_PS_10 | 2)
87#define SVGA3D_PS_13 (SVGA3D_PS_10 | 3)
88#define SVGA3D_PS_14 (SVGA3D_PS_10 | 4)
89#define SVGA3D_PS_20 ((SVGA3D_PS_TYPE << 16) | 2 << 8)
90#define SVGA3D_PS_21 (SVGA3D_PS_20 | 1)
91#define SVGA3D_PS_30 ((SVGA3D_PS_TYPE << 16) | 3 << 8)
92
93/* The *_ENABLED are for backwards compatibility with old drivers */
94typedef enum {
95 SVGA3DPSVERSION_NONE = 0,
96 SVGA3DPSVERSION_ENABLED = 1,
97 SVGA3DPSVERSION_11 = 3,
98 SVGA3DPSVERSION_12 = 5,
99 SVGA3DPSVERSION_13 = 7,
100 SVGA3DPSVERSION_14 = 9,
101 SVGA3DPSVERSION_20 = 11,
102 SVGA3DPSVERSION_30 = 13,
103 SVGA3DPSVERSION_40 = 15,
104 SVGA3DPSVERSION_MAX
105} SVGA3dPixelShaderVersion;
106
107typedef enum {
108 SVGA3DVSVERSION_NONE = 0,
109 SVGA3DVSVERSION_ENABLED = 1,
110 SVGA3DVSVERSION_11 = 3,
111 SVGA3DVSVERSION_20 = 5,
112 SVGA3DVSVERSION_30 = 7,
113 SVGA3DVSVERSION_40 = 9,
114 SVGA3DVSVERSION_MAX
115} SVGA3dVertexShaderVersion;
116
117/* SVGA3D instruction op codes. */
118
119typedef enum {
120 SVGA3DOP_NOP = 0,
121 SVGA3DOP_MOV,
122 SVGA3DOP_ADD,
123 SVGA3DOP_SUB,
124 SVGA3DOP_MAD,
125 SVGA3DOP_MUL,
126 SVGA3DOP_RCP,
127 SVGA3DOP_RSQ,
128 SVGA3DOP_DP3,
129 SVGA3DOP_DP4,
130 SVGA3DOP_MIN,
131 SVGA3DOP_MAX,
132 SVGA3DOP_SLT,
133 SVGA3DOP_SGE,
134 SVGA3DOP_EXP,
135 SVGA3DOP_LOG,
136 SVGA3DOP_LIT,
137 SVGA3DOP_DST,
138 SVGA3DOP_LRP,
139 SVGA3DOP_FRC,
140 SVGA3DOP_M4x4,
141 SVGA3DOP_M4x3,
142 SVGA3DOP_M3x4,
143 SVGA3DOP_M3x3,
144 SVGA3DOP_M3x2,
145 SVGA3DOP_CALL,
146 SVGA3DOP_CALLNZ,
147 SVGA3DOP_LOOP,
148 SVGA3DOP_RET,
149 SVGA3DOP_ENDLOOP,
150 SVGA3DOP_LABEL,
151 SVGA3DOP_DCL,
152 SVGA3DOP_POW,
153 SVGA3DOP_CRS,
154 SVGA3DOP_SGN,
155 SVGA3DOP_ABS,
156 SVGA3DOP_NRM,
157 SVGA3DOP_SINCOS,
158 SVGA3DOP_REP,
159 SVGA3DOP_ENDREP,
160 SVGA3DOP_IF,
161 SVGA3DOP_IFC,
162 SVGA3DOP_ELSE,
163 SVGA3DOP_ENDIF,
164 SVGA3DOP_BREAK,
165 SVGA3DOP_BREAKC,
166 SVGA3DOP_MOVA,
167 SVGA3DOP_DEFB,
168 SVGA3DOP_DEFI,
169 SVGA3DOP_TEXCOORD = 64,
170 SVGA3DOP_TEXKILL,
171 SVGA3DOP_TEX,
172 SVGA3DOP_TEXBEM,
173 SVGA3DOP_TEXBEML,
174 SVGA3DOP_TEXREG2AR,
175 SVGA3DOP_TEXREG2GB = 70,
176 SVGA3DOP_TEXM3x2PAD,
177 SVGA3DOP_TEXM3x2TEX,
178 SVGA3DOP_TEXM3x3PAD,
179 SVGA3DOP_TEXM3x3TEX,
180 SVGA3DOP_RESERVED0,
181 SVGA3DOP_TEXM3x3SPEC,
182 SVGA3DOP_TEXM3x3VSPEC,
183 SVGA3DOP_EXPP,
184 SVGA3DOP_LOGP,
185 SVGA3DOP_CND = 80,
186 SVGA3DOP_DEF,
187 SVGA3DOP_TEXREG2RGB,
188 SVGA3DOP_TEXDP3TEX,
189 SVGA3DOP_TEXM3x2DEPTH,
190 SVGA3DOP_TEXDP3,
191 SVGA3DOP_TEXM3x3,
192 SVGA3DOP_TEXDEPTH,
193 SVGA3DOP_CMP,
194 SVGA3DOP_BEM,
195 SVGA3DOP_DP2ADD = 90,
196 SVGA3DOP_DSX,
197 SVGA3DOP_DSY,
198 SVGA3DOP_TEXLDD,
199 SVGA3DOP_SETP,
200 SVGA3DOP_TEXLDL,
201 SVGA3DOP_BREAKP = 96,
202 SVGA3DOP_LAST_INST,
203 SVGA3DOP_PHASE = 0xFFFD,
204 SVGA3DOP_COMMENT = 0xFFFE,
205 SVGA3DOP_END = 0xFFFF,
206} SVGA3dShaderOpCodeType;
207
208/* SVGA3D operation control/comparison function types */
209
210typedef enum {
211 SVGA3DOPCONT_NONE,
212 SVGA3DOPCONT_PROJECT, /* Projective texturing */
213 SVGA3DOPCONT_BIAS, /* Texturing with a LOD bias */
214} SVGA3dShaderOpCodeControlFnType;
215
216typedef enum {
217 SVGA3DOPCOMP_RESERVED0 = 0,
218 SVGA3DOPCOMP_GT,
219 SVGA3DOPCOMP_EQ,
220 SVGA3DOPCOMP_GE,
221 SVGA3DOPCOMP_LT,
222 SVGA3DOPCOMPC_NE,
223 SVGA3DOPCOMP_LE,
224 SVGA3DOPCOMP_RESERVED1
225} SVGA3dShaderOpCodeCompFnType;
226
227/* SVGA3D register types */
228
229typedef enum {
230 SVGA3DREG_TEMP = 0, /* Temporary register file */
231 SVGA3DREG_INPUT, /* Input register file */
232 SVGA3DREG_CONST, /* Constant register file */
233 SVGA3DREG_ADDR, /* Address register for VS */
234 SVGA3DREG_TEXTURE = 3, /* Texture register file for PS */
235 SVGA3DREG_RASTOUT, /* Rasterizer register file */
236 SVGA3DREG_ATTROUT, /* Attribute output register file */
237 SVGA3DREG_TEXCRDOUT, /* Texture coordinate output register file */
238 SVGA3DREG_OUTPUT = 6, /* Output register file for VS 3.0+ */
239 SVGA3DREG_CONSTINT, /* Constant integer vector register file */
240 SVGA3DREG_COLOROUT, /* Color output register file */
241 SVGA3DREG_DEPTHOUT, /* Depth output register file */
242 SVGA3DREG_SAMPLER, /* Sampler state register file */
243 SVGA3DREG_CONST2, /* Constant register file 2048 - 4095 */
244 SVGA3DREG_CONST3, /* Constant register file 4096 - 6143 */
245 SVGA3DREG_CONST4, /* Constant register file 6144 - 8191 */
246 SVGA3DREG_CONSTBOOL, /* Constant boolean register file */
247 SVGA3DREG_LOOP, /* Loop counter register file */
248 SVGA3DREG_TEMPFLOAT16, /* 16-bit float temp register file */
249 SVGA3DREG_MISCTYPE, /* Miscellaneous (single) registers */
250 SVGA3DREG_LABEL, /* Label */
251 SVGA3DREG_PREDICATE, /* Predicate register */
252} SVGA3dShaderRegType;
253
254/* SVGA3D rasterizer output register types */
255
256typedef enum {
257 SVGA3DRASTOUT_POSITION = 0,
258 SVGA3DRASTOUT_FOG,
259 SVGA3DRASTOUT_PSIZE
260} SVGA3dShaderRastOutRegType;
261
262/* SVGA3D miscellaneous register types */
263
264typedef enum {
265 SVGA3DMISCREG_POSITION = 0, /* Input position x,y,z,rhw (PS) */
266 SVGA3DMISCREG_FACE /* Floating point primitive area (PS) */
267} SVGA3DShaderMiscRegType;
268
269/* SVGA3D sampler types */
270
271typedef enum {
272 SVGA3DSAMP_UNKNOWN = 0, /* Uninitialized value */
273 SVGA3DSAMP_2D = 2, /* dcl_2d s# (for declaring a 2D texture) */
274 SVGA3DSAMP_CUBE, /* dcl_cube s# (for declaring a cube texture) */
275 SVGA3DSAMP_VOLUME, /* dcl_volume s# (for declaring a volume texture) */
276 SVGA3DSAMP_2D_SHADOW, /* dcl_2d s# (for declaring a 2D shadow texture) */
277 SVGA3DSAMP_MAX,
278} SVGA3dShaderSamplerType;
279
280/* SVGA3D write mask */
281
282#define SVGA3DWRITEMASK_0 1 /* Component 0 (X;Red) */
283#define SVGA3DWRITEMASK_1 2 /* Component 1 (Y;Green) */
284#define SVGA3DWRITEMASK_2 4 /* Component 2 (Z;Blue) */
285#define SVGA3DWRITEMASK_3 8 /* Component 3 (W;Alpha) */
286#define SVGA3DWRITEMASK_ALL 15 /* All components */
287
288/* SVGA3D destination modifiers */
289
290#define SVGA3DDSTMOD_NONE 0 /* nop */
291#define SVGA3DDSTMOD_SATURATE 1 /* clamp to [0, 1] */
292#define SVGA3DDSTMOD_PARTIALPRECISION 2 /* Partial precision hint */
293
294/*
295 * Relevant to multisampling only:
296 * When the pixel center is not covered, sample
297 * attribute or compute gradients/LOD
298 * using multisample "centroid" location.
299 * "Centroid" is some location within the covered
300 * region of the pixel.
301 */
302
303#define SVGA3DDSTMOD_MSAMPCENTROID 4
304
305/* SVGA3D destination shift scale */
306
307typedef enum {
308 SVGA3DDSTSHFSCALE_X1 = 0, /* 1.0 */
309 SVGA3DDSTSHFSCALE_X2 = 1, /* 2.0 */
310 SVGA3DDSTSHFSCALE_X4 = 2, /* 4.0 */
311 SVGA3DDSTSHFSCALE_X8 = 3, /* 8.0 */
312 SVGA3DDSTSHFSCALE_D8 = 13, /* 0.125 */
313 SVGA3DDSTSHFSCALE_D4 = 14, /* 0.25 */
314 SVGA3DDSTSHFSCALE_D2 = 15 /* 0.5 */
315} SVGA3dShaderDstShfScaleType;
316
317/* SVGA3D source swizzle */
318
319#define SVGA3DSWIZZLE_REPLICATEX 0x00
320#define SVGA3DSWIZZLE_REPLICATEY 0x55
321#define SVGA3DSWIZZLE_REPLICATEZ 0xAA
322#define SVGA3DSWIZZLE_REPLICATEW 0xFF
323#define SVGA3DSWIZZLE_NONE 0xE4
324#define SVGA3DSWIZZLE_YZXW 0xC9
325#define SVGA3DSWIZZLE_ZXYW 0xD2
326#define SVGA3DSWIZZLE_WXYZ 0x1B
327
328/* SVGA3D source modifiers */
329
330typedef enum {
331 SVGA3DSRCMOD_NONE = 0, /* nop */
332 SVGA3DSRCMOD_NEG, /* negate */
333 SVGA3DSRCMOD_BIAS, /* bias */
334 SVGA3DSRCMOD_BIASNEG, /* bias and negate */
335 SVGA3DSRCMOD_SIGN, /* sign */
336 SVGA3DSRCMOD_SIGNNEG, /* sign and negate */
337 SVGA3DSRCMOD_COMP, /* complement */
338 SVGA3DSRCMOD_X2, /* x2 */
339 SVGA3DSRCMOD_X2NEG, /* x2 and negate */
340 SVGA3DSRCMOD_DZ, /* divide through by z component */
341 SVGA3DSRCMOD_DW, /* divide through by w component */
342 SVGA3DSRCMOD_ABS, /* abs() */
343 SVGA3DSRCMOD_ABSNEG, /* -abs() */
344 SVGA3DSRCMOD_NOT, /* ! (for predicate register) */
345} SVGA3dShaderSrcModType;
346
347/* SVGA3D instruction token */
348
349typedef struct {
350 union {
351 struct {
352 uint32 comment_op : 16;
353 uint32 comment_size : 16;
354 };
355
356 struct {
357 uint32 op : 16;
358 uint32 control : 3;
359 uint32 reserved2 : 5;
360 uint32 size : 4;
361 uint32 predicated : 1;
362 uint32 reserved1 : 1;
363 uint32 coissue : 1;
364 uint32 reserved0 : 1;
365 };
366
367 uint32 value;
368 };
369} SVGA3dShaderInstToken;
370
371/* SVGA3D destination parameter token */
372
373typedef struct {
374 union {
375 struct {
376 uint32 num : 11;
377 uint32 type_upper : 2;
378 uint32 relAddr : 1;
379 uint32 reserved1 : 2;
380 uint32 mask : 4;
381 uint32 dstMod : 4;
382 uint32 shfScale : 4;
383 uint32 type_lower : 3;
384 uint32 reserved0 : 1;
385 };
386
387 uint32 value;
388 };
389} SVGA3dShaderDestToken;
390
391/* SVGA3D source parameter token */
392
393typedef struct {
394 union {
395 struct {
396 uint32 num : 11;
397 uint32 type_upper : 2;
398 uint32 relAddr : 1;
399 uint32 reserved1 : 2;
400 uint32 swizzle : 8;
401 uint32 srcMod : 4;
402 uint32 type_lower : 3;
403 uint32 reserved0 : 1;
404 };
405
406 uint32 value;
407 };
408} SVGA3dShaderSrcToken;
409
410/* SVGA3DOP_DCL parameter tokens */
411
412typedef struct {
413 union {
414 struct {
415 union {
416 struct {
417 uint32 usage : 5;
418 uint32 reserved1 : 11;
419 uint32 index : 4;
420 uint32 reserved0 : 12;
421 }; /* input / output declaration */
422
423 struct {
424 uint32 reserved3 : 27;
425 uint32 type : 4;
426 uint32 reserved2 : 1;
427 }; /* sampler declaration */
428 };
429
430 SVGA3dShaderDestToken dst;
431 };
432
433 uint32 values[2];
434 };
435} SVGA3DOpDclArgs;
436
437/* SVGA3DOP_DEF parameter tokens */
438
439typedef struct {
440 union {
441 struct {
442 SVGA3dShaderDestToken dst;
443
444 union {
445 float constValues[4];
446 int constIValues[4];
447 Bool constBValue;
448 };
449 };
450
451 uint32 values[5];
452 };
453} SVGA3DOpDefArgs;
454
455/* SVGA3D shader token */
456
457typedef union {
458 uint32 value;
459 SVGA3dShaderInstToken inst;
460 SVGA3dShaderDestToken dest;
461 SVGA3dShaderSrcToken src;
462} SVGA3dShaderToken;
463
464/* SVGA3D shader program */
465
466typedef struct {
467 SVGA3dShaderVersion version;
468 /* SVGA3dShaderToken stream */
469} SVGA3dShaderProgram;
470
471/* SVGA3D version specific register assignments */
472
473static const uint32 SVGA3D_INPUT_REG_POSITION_VS11 = 0;
474static const uint32 SVGA3D_INPUT_REG_PSIZE_VS11 = 1;
475static const uint32 SVGA3D_INPUT_REG_FOG_VS11 = 3;
476static const uint32 SVGA3D_INPUT_REG_FOG_MASK_VS11 = SVGA3DWRITEMASK_3;
477static const uint32 SVGA3D_INPUT_REG_COLOR_BASE_VS11 = 2;
478static const uint32 SVGA3D_INPUT_REG_TEXCOORD_BASE_VS11 = 4;
479
480static const uint32 SVGA3D_INPUT_REG_COLOR_BASE_PS11 = 0;
481static const uint32 SVGA3D_INPUT_REG_TEXCOORD_BASE_PS11 = 2;
482static const uint32 SVGA3D_OUTPUT_REG_DEPTH_PS11 = 0;
483static const uint32 SVGA3D_OUTPUT_REG_COLOR_PS11 = 1;
484
485static const uint32 SVGA3D_INPUT_REG_COLOR_BASE_PS20 = 0;
486static const uint32 SVGA3D_INPUT_REG_COLOR_NUM_PS20 = 2;
487static const uint32 SVGA3D_INPUT_REG_TEXCOORD_BASE_PS20 = 2;
488static const uint32 SVGA3D_INPUT_REG_TEXCOORD_NUM_PS20 = 8;
489static const uint32 SVGA3D_OUTPUT_REG_COLOR_BASE_PS20 = 1;
490static const uint32 SVGA3D_OUTPUT_REG_COLOR_NUM_PS20 = 4;
491static const uint32 SVGA3D_OUTPUT_REG_DEPTH_BASE_PS20 = 0;
492static const uint32 SVGA3D_OUTPUT_REG_DEPTH_NUM_PS20 = 1;
493
494/*
495 *----------------------------------------------------------------------
496 *
497 * SVGA3dShaderGetRegType --
498 *
499 * As the register type is split into two non sequential fields,
500 * this function provides an useful way of accessing the actual
501 * register type without having to manually concatenate the
502 * type_upper and type_lower fields.
503 *
504 * Results:
505 * Returns the register type.
506 *
507 *----------------------------------------------------------------------
508 */
509
510static inline SVGA3dShaderRegType
511SVGA3dShaderGetRegType(uint32 token)
512{
513 SVGA3dShaderSrcToken src;
514 src.value = token;
515 return (SVGA3dShaderRegType)(src.type_upper << 3 | src.type_lower);
516}
517
518#endif /* __SVGA3D_SHADER_DEFS__ */
Note: See TracBrowser for help on using the repository browser.

© 2024 Oracle Support Privacy / Do Not Sell My Info Terms of Use Trademark Policy Automated Access Etiquette