VGPU10ShaderTokens.h@ 86900

Last change on this file since 86900 was 86899, checked in by vboxsync, 4 years ago
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1	/**********************************************************
2	* Copyright 2007-2015 VMware, Inc. All rights reserved.
3	*
4	* Permission is hereby granted, free of charge, to any person
5	* obtaining a copy of this software and associated documentation
6	* files (the "Software"), to deal in the Software without
7	* restriction, including without limitation the rights to use, copy,
8	* modify, merge, publish, distribute, sublicense, and/or sell copies
9	* of the Software, and to permit persons to whom the Software is
10	* furnished to do so, subject to the following conditions:
11	*
12	* The above copyright notice and this permission notice shall be
13	* included in all copies or substantial portions of the Software.
14	*
15	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
16	* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
17	* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
18	* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
19	* BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
20	* ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
21	* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
22	* SOFTWARE.
23	*
24	**********************************************************/
25
26	/*
27	* VGPU10ShaderTokens.h --
28	*
29	* VGPU10 shader token definitions.
30	*
31	*/
32
33	#ifndef VGPU10SHADERTOKENS_H
34	#define VGPU10SHADERTOKENS_H
35
36	/* Shader limits */
37	#define VGPU10_MAX_VS_INPUTS 16
38	#define VGPU10_MAX_VS_OUTPUTS 16
39	#define VGPU10_MAX_GS_INPUTS 16
40	#define VGPU10_MAX_GS_OUTPUTS 32
41	#define VGPU10_MAX_FS_INPUTS 32
42	#define VGPU10_MAX_FS_OUTPUTS 8
43	#define VGPU10_MAX_TEMPS 4096
44	#define VGPU10_MAX_CONSTANT_BUFFERS (14 + 1)
45	#define VGPU10_MAX_CONSTANT_BUFFER_ELEMENT_COUNT 4096
46	#define VGPU10_MAX_IMMEDIATE_CONSTANT_BUFFER_ELEMENT_COUNT 4096
47	#define VGPU10_MAX_SAMPLERS 16
48	#define VGPU10_MAX_RESOURCES 128
49	#define VGPU10_MIN_TEXEL_FETCH_OFFSET -8
50	#define VGPU10_MAX_TEXEL_FETCH_OFFSET 7
51
52	/* Shader Model 4.1 limits */
53	#define VGPU10_1_MAX_VS_INPUTS 32
54	#define VGPU10_1_MAX_VS_OUTPUTS 32
55	#define VGPU10_1_MAX_GS_INPUTS 32
56
57	/* Shader Model 5.0 limits */
58	#define VGPU11_MAX_HS_INPUTS 32
59	#define VGPU11_MAX_HS_INPUT_CONTROL_POINTS 32
60	#define VGPU11_MAX_HS_INPUT_PATCH_CONSTANTS 32
61	#define VGPU11_MAX_HS_OUTPUTS 32
62	#define VGPU11_MAX_DS_INPUT_CONTROL_POINTS 32
63	#define VGPU11_MAX_DS_INPUT_PATCH_CONSTANTS 32
64	#define VGPU11_MAX_DS_OUTPUTS 32
65	#define VGPU11_MAX_GS_STREAMS 4
66
67	/* Maximums of limits for all stages */
68	#define VGPU10_MAX_INPUTS 32
69	#define VGPU10_MAX_OUTPUTS 32
70	#define VGPU10_MAX_INPUT_PATCH_CONSTANTS 32
71
72	typedef enum {
73	VGPU10_PIXEL_SHADER = 0,
74	VGPU10_VERTEX_SHADER = 1,
75	VGPU10_GEOMETRY_SHADER = 2,
76
77	/* DX11 */
78	VGPU10_HULL_SHADER = 3,
79	VGPU10_DOMAIN_SHADER = 4,
80	VGPU10_COMPUTE_SHADER = 5
81	} VGPU10_PROGRAM_TYPE;
82
83	typedef union {
84	struct {
85	unsigned int minorVersion : 4;
86	unsigned int majorVersion : 4;
87	unsigned int : 8;
88	unsigned int programType : 16; /* VGPU10_PROGRAM_TYPE */
89	};
90	uint32 value;
91	} VGPU10ProgramToken;
92
93
94	typedef enum {
95	VGPU10_OPCODE_ADD = 0,
96	VGPU10_OPCODE_AND = 1,
97	VGPU10_OPCODE_BREAK = 2,
98	VGPU10_OPCODE_BREAKC = 3,
99	VGPU10_OPCODE_CALL = 4,
100	VGPU10_OPCODE_CALLC = 5,
101	VGPU10_OPCODE_CASE = 6,
102	VGPU10_OPCODE_CONTINUE = 7,
103	VGPU10_OPCODE_CONTINUEC = 8,
104	VGPU10_OPCODE_CUT = 9,
105	VGPU10_OPCODE_DEFAULT = 10,
106	VGPU10_OPCODE_DERIV_RTX = 11,
107	VGPU10_OPCODE_DERIV_RTY = 12,
108	VGPU10_OPCODE_DISCARD = 13,
109	VGPU10_OPCODE_DIV = 14,
110	VGPU10_OPCODE_DP2 = 15,
111	VGPU10_OPCODE_DP3 = 16,
112	VGPU10_OPCODE_DP4 = 17,
113	VGPU10_OPCODE_ELSE = 18,
114	VGPU10_OPCODE_EMIT = 19,
115	VGPU10_OPCODE_EMITTHENCUT = 20,
116	VGPU10_OPCODE_ENDIF = 21,
117	VGPU10_OPCODE_ENDLOOP = 22,
118	VGPU10_OPCODE_ENDSWITCH = 23,
119	VGPU10_OPCODE_EQ = 24,
120	VGPU10_OPCODE_EXP = 25,
121	VGPU10_OPCODE_FRC = 26,
122	VGPU10_OPCODE_FTOI = 27,
123	VGPU10_OPCODE_FTOU = 28,
124	VGPU10_OPCODE_GE = 29,
125	VGPU10_OPCODE_IADD = 30,
126	VGPU10_OPCODE_IF = 31,
127	VGPU10_OPCODE_IEQ = 32,
128	VGPU10_OPCODE_IGE = 33,
129	VGPU10_OPCODE_ILT = 34,
130	VGPU10_OPCODE_IMAD = 35,
131	VGPU10_OPCODE_IMAX = 36,
132	VGPU10_OPCODE_IMIN = 37,
133	VGPU10_OPCODE_IMUL = 38,
134	VGPU10_OPCODE_INE = 39,
135	VGPU10_OPCODE_INEG = 40,
136	VGPU10_OPCODE_ISHL = 41,
137	VGPU10_OPCODE_ISHR = 42,
138	VGPU10_OPCODE_ITOF = 43,
139	VGPU10_OPCODE_LABEL = 44,
140	VGPU10_OPCODE_LD = 45,
141	VGPU10_OPCODE_LD_MS = 46,
142	VGPU10_OPCODE_LOG = 47,
143	VGPU10_OPCODE_LOOP = 48,
144	VGPU10_OPCODE_LT = 49,
145	VGPU10_OPCODE_MAD = 50,
146	VGPU10_OPCODE_MIN = 51,
147	VGPU10_OPCODE_MAX = 52,
148	VGPU10_OPCODE_CUSTOMDATA = 53,
149	VGPU10_OPCODE_MOV = 54,
150	VGPU10_OPCODE_MOVC = 55,
151	VGPU10_OPCODE_MUL = 56,
152	VGPU10_OPCODE_NE = 57,
153	VGPU10_OPCODE_NOP = 58,
154	VGPU10_OPCODE_NOT = 59,
155	VGPU10_OPCODE_OR = 60,
156	VGPU10_OPCODE_RESINFO = 61,
157	VGPU10_OPCODE_RET = 62,
158	VGPU10_OPCODE_RETC = 63,
159	VGPU10_OPCODE_ROUND_NE = 64,
160	VGPU10_OPCODE_ROUND_NI = 65,
161	VGPU10_OPCODE_ROUND_PI = 66,
162	VGPU10_OPCODE_ROUND_Z = 67,
163	VGPU10_OPCODE_RSQ = 68,
164	VGPU10_OPCODE_SAMPLE = 69,
165	VGPU10_OPCODE_SAMPLE_C = 70,
166	VGPU10_OPCODE_SAMPLE_C_LZ = 71,
167	VGPU10_OPCODE_SAMPLE_L = 72,
168	VGPU10_OPCODE_SAMPLE_D = 73,
169	VGPU10_OPCODE_SAMPLE_B = 74,
170	VGPU10_OPCODE_SQRT = 75,
171	VGPU10_OPCODE_SWITCH = 76,
172	VGPU10_OPCODE_SINCOS = 77,
173	VGPU10_OPCODE_UDIV = 78,
174	VGPU10_OPCODE_ULT = 79,
175	VGPU10_OPCODE_UGE = 80,
176	VGPU10_OPCODE_UMUL = 81,
177	VGPU10_OPCODE_UMAD = 82,
178	VGPU10_OPCODE_UMAX = 83,
179	VGPU10_OPCODE_UMIN = 84,
180	VGPU10_OPCODE_USHR = 85,
181	VGPU10_OPCODE_UTOF = 86,
182	VGPU10_OPCODE_XOR = 87,
183	VGPU10_OPCODE_DCL_RESOURCE = 88,
184	VGPU10_OPCODE_DCL_CONSTANT_BUFFER = 89,
185	VGPU10_OPCODE_DCL_SAMPLER = 90,
186	VGPU10_OPCODE_DCL_INDEX_RANGE = 91,
187	VGPU10_OPCODE_DCL_GS_OUTPUT_PRIMITIVE_TOPOLOGY = 92,
188	VGPU10_OPCODE_DCL_GS_INPUT_PRIMITIVE = 93,
189	VGPU10_OPCODE_DCL_MAX_OUTPUT_VERTEX_COUNT = 94,
190	VGPU10_OPCODE_DCL_INPUT = 95,
191	VGPU10_OPCODE_DCL_INPUT_SGV = 96,
192	VGPU10_OPCODE_DCL_INPUT_SIV = 97,
193	VGPU10_OPCODE_DCL_INPUT_PS = 98,
194	VGPU10_OPCODE_DCL_INPUT_PS_SGV = 99,
195	VGPU10_OPCODE_DCL_INPUT_PS_SIV = 100,
196	VGPU10_OPCODE_DCL_OUTPUT = 101,
197	VGPU10_OPCODE_DCL_OUTPUT_SGV = 102,
198	VGPU10_OPCODE_DCL_OUTPUT_SIV = 103,
199	VGPU10_OPCODE_DCL_TEMPS = 104,
200	VGPU10_OPCODE_DCL_INDEXABLE_TEMP = 105,
201	VGPU10_OPCODE_DCL_GLOBAL_FLAGS = 106,
202
203	/* GL guest */
204	VGPU10_OPCODE_VMWARE = 107,
205
206	/* DX10.1 */
207	VGPU10_OPCODE_LOD = 108,
208	VGPU10_OPCODE_GATHER4 = 109,
209	VGPU10_OPCODE_SAMPLE_POS = 110,
210	VGPU10_OPCODE_SAMPLE_INFO = 111,
211
212	/* DX11 */
213	VGPU10_OPCODE_RESERVED1 = 112,
214	VGPU10_OPCODE_HS_DECLS = 113,
215	VGPU10_OPCODE_HS_CONTROL_POINT_PHASE = 114,
216	VGPU10_OPCODE_HS_FORK_PHASE = 115,
217	VGPU10_OPCODE_HS_JOIN_PHASE = 116,
218	VGPU10_OPCODE_EMIT_STREAM = 117,
219	VGPU10_OPCODE_CUT_STREAM = 118,
220	VGPU10_OPCODE_EMITTHENCUT_STREAM = 119,
221	VGPU10_OPCODE_INTERFACE_CALL = 120,
222	VGPU10_OPCODE_BUFINFO = 121,
223	VGPU10_OPCODE_DERIV_RTX_COARSE = 122,
224	VGPU10_OPCODE_DERIV_RTX_FINE = 123,
225	VGPU10_OPCODE_DERIV_RTY_COARSE = 124,
226	VGPU10_OPCODE_DERIV_RTY_FINE = 125,
227	VGPU10_OPCODE_GATHER4_C = 126,
228	VGPU10_OPCODE_GATHER4_PO = 127,
229	VGPU10_OPCODE_GATHER4_PO_C = 128,
230	VGPU10_OPCODE_RCP = 129,
231	VGPU10_OPCODE_F32TOF16 = 130,
232	VGPU10_OPCODE_F16TOF32 = 131,
233	VGPU10_OPCODE_UADDC = 132,
234	VGPU10_OPCODE_USUBB = 133,
235	VGPU10_OPCODE_COUNTBITS = 134,
236	VGPU10_OPCODE_FIRSTBIT_HI = 135,
237	VGPU10_OPCODE_FIRSTBIT_LO = 136,
238	VGPU10_OPCODE_FIRSTBIT_SHI = 137,
239	VGPU10_OPCODE_UBFE = 138,
240	VGPU10_OPCODE_IBFE = 139,
241	VGPU10_OPCODE_BFI = 140,
242	VGPU10_OPCODE_BFREV = 141,
243	VGPU10_OPCODE_SWAPC = 142,
244	VGPU10_OPCODE_DCL_STREAM = 143,
245	VGPU10_OPCODE_DCL_FUNCTION_BODY = 144,
246	VGPU10_OPCODE_DCL_FUNCTION_TABLE = 145,
247	VGPU10_OPCODE_DCL_INTERFACE = 146,
248	VGPU10_OPCODE_DCL_INPUT_CONTROL_POINT_COUNT = 147,
249	VGPU10_OPCODE_DCL_OUTPUT_CONTROL_POINT_COUNT = 148,
250	VGPU10_OPCODE_DCL_TESS_DOMAIN = 149,
251	VGPU10_OPCODE_DCL_TESS_PARTITIONING = 150,
252	VGPU10_OPCODE_DCL_TESS_OUTPUT_PRIMITIVE = 151,
253	VGPU10_OPCODE_DCL_HS_MAX_TESSFACTOR = 152,
254	VGPU10_OPCODE_DCL_HS_FORK_PHASE_INSTANCE_COUNT = 153,
255	VGPU10_OPCODE_DCL_HS_JOIN_PHASE_INSTANCE_COUNT = 154,
256	VGPU10_OPCODE_DCL_THREAD_GROUP = 155,
257	VGPU10_OPCODE_DCL_UAV_TYPED = 156,
258	VGPU10_OPCODE_DCL_UAV_RAW = 157,
259	VGPU10_OPCODE_DCL_UAV_STRUCTURED = 158,
260	VGPU10_OPCODE_DCL_TGSM_RAW = 159,
261	VGPU10_OPCODE_DCL_TGSM_STRUCTURED = 160,
262	VGPU10_OPCODE_DCL_RESOURCE_RAW = 161,
263	VGPU10_OPCODE_DCL_RESOURCE_STRUCTURED = 162,
264	VGPU10_OPCODE_LD_UAV_TYPED = 163,
265	VGPU10_OPCODE_STORE_UAV_TYPED = 164,
266	VGPU10_OPCODE_LD_RAW = 165,
267	VGPU10_OPCODE_STORE_RAW = 166,
268	VGPU10_OPCODE_LD_STRUCTURED = 167,
269	VGPU10_OPCODE_STORE_STRUCTURED = 168,
270	VGPU10_OPCODE_ATOMIC_AND = 169,
271	VGPU10_OPCODE_ATOMIC_OR = 170,
272	VGPU10_OPCODE_ATOMIC_XOR = 171,
273	VGPU10_OPCODE_ATOMIC_CMP_STORE = 172,
274	VGPU10_OPCODE_ATOMIC_IADD = 173,
275	VGPU10_OPCODE_ATOMIC_IMAX = 174,
276	VGPU10_OPCODE_ATOMIC_IMIN = 175,
277	VGPU10_OPCODE_ATOMIC_UMAX = 176,
278	VGPU10_OPCODE_ATOMIC_UMIN = 177,
279	VGPU10_OPCODE_IMM_ATOMIC_ALLOC = 178,
280	VGPU10_OPCODE_IMM_ATOMIC_CONSUME = 179,
281	VGPU10_OPCODE_IMM_ATOMIC_IADD = 180,
282	VGPU10_OPCODE_IMM_ATOMIC_AND = 181,
283	VGPU10_OPCODE_IMM_ATOMIC_OR = 182,
284	VGPU10_OPCODE_IMM_ATOMIC_XOR = 183,
285	VGPU10_OPCODE_IMM_ATOMIC_EXCH = 184,
286	VGPU10_OPCODE_IMM_ATOMIC_CMP_EXCH = 185,
287	VGPU10_OPCODE_IMM_ATOMIC_IMAX = 186,
288	VGPU10_OPCODE_IMM_ATOMIC_IMIN = 187,
289	VGPU10_OPCODE_IMM_ATOMIC_UMAX = 188,
290	VGPU10_OPCODE_IMM_ATOMIC_UMIN = 189,
291	VGPU10_OPCODE_SYNC = 190,
292	VGPU10_OPCODE_DADD = 191,
293	VGPU10_OPCODE_DMAX = 192,
294	VGPU10_OPCODE_DMIN = 193,
295	VGPU10_OPCODE_DMUL = 194,
296	VGPU10_OPCODE_DEQ = 195,
297	VGPU10_OPCODE_DGE = 196,
298	VGPU10_OPCODE_DLT = 197,
299	VGPU10_OPCODE_DNE = 198,
300	VGPU10_OPCODE_DMOV = 199,
301	VGPU10_OPCODE_DMOVC = 200,
302	VGPU10_OPCODE_DTOF = 201,
303	VGPU10_OPCODE_FTOD = 202,
304	VGPU10_OPCODE_EVAL_SNAPPED = 203,
305	VGPU10_OPCODE_EVAL_SAMPLE_INDEX = 204,
306	VGPU10_OPCODE_EVAL_CENTROID = 205,
307	VGPU10_OPCODE_DCL_GS_INSTANCE_COUNT = 206,
308	VGPU10_OPCODE_ABORT = 207,
309	VGPU10_OPCODE_DEBUG_BREAK = 208,
310
311	/* DX11.1 */
312	VGPU10_OPCODE_RESERVED0 = 209,
313	VGPU10_OPCODE_DDIV = 210,
314	VGPU10_OPCODE_DFMA = 211,
315	VGPU10_OPCODE_DRCP = 212,
316	VGPU10_OPCODE_MSAD = 213,
317	VGPU10_OPCODE_DTOI = 214,
318	VGPU10_OPCODE_DTOU = 215,
319	VGPU10_OPCODE_ITOD = 216,
320	VGPU10_OPCODE_UTOD = 217,
321
322	VGPU10_NUM_OPCODES /* Should be the last entry. */
323	} VGPU10_OPCODE_TYPE;
324
325	/* Sub-opcode of VGPU10_OPCODE_VMWARE. */
326	typedef enum {
327	VGPU10_VMWARE_OPCODE_IDIV = 0,
328	VGPU10_VMWARE_OPCODE_DFRC = 1,
329	VGPU10_VMWARE_OPCODE_DRSQ = 2,
330	VGPU10_VMWARE_NUM_OPCODES /* Should be the last entry. */
331	} VGPU10_VMWARE_OPCODE_TYPE;
332
333	typedef enum {
334	VGPU10_INTERPOLATION_UNDEFINED = 0,
335	VGPU10_INTERPOLATION_CONSTANT = 1,
336	VGPU10_INTERPOLATION_LINEAR = 2,
337	VGPU10_INTERPOLATION_LINEAR_CENTROID = 3,
338	VGPU10_INTERPOLATION_LINEAR_NOPERSPECTIVE = 4,
339	VGPU10_INTERPOLATION_LINEAR_NOPERSPECTIVE_CENTROID = 5,
340	VGPU10_INTERPOLATION_LINEAR_SAMPLE = 6, /* DX10.1 */
341	VGPU10_INTERPOLATION_LINEAR_NOPERSPECTIVE_SAMPLE = 7 /* DX10.1 */
342	} VGPU10_INTERPOLATION_MODE;
343
344	typedef enum {
345	VGPU10_RESOURCE_DIMENSION_UNKNOWN = 0,
346	VGPU10_RESOURCE_DIMENSION_BUFFER = 1,
347	VGPU10_RESOURCE_DIMENSION_TEXTURE1D = 2,
348	VGPU10_RESOURCE_DIMENSION_TEXTURE2D = 3,
349	VGPU10_RESOURCE_DIMENSION_TEXTURE2DMS = 4,
350	VGPU10_RESOURCE_DIMENSION_TEXTURE3D = 5,
351	VGPU10_RESOURCE_DIMENSION_TEXTURECUBE = 6,
352	VGPU10_RESOURCE_DIMENSION_TEXTURE1DARRAY = 7,
353	VGPU10_RESOURCE_DIMENSION_TEXTURE2DARRAY = 8,
354	VGPU10_RESOURCE_DIMENSION_TEXTURE2DMSARRAY = 9,
355	VGPU10_RESOURCE_DIMENSION_TEXTURECUBEARRAY = 10
356	} VGPU10_RESOURCE_DIMENSION;
357
358	typedef enum {
359	VGPU10_SAMPLER_MODE_DEFAULT = 0,
360	VGPU10_SAMPLER_MODE_COMPARISON = 1,
361	VGPU10_SAMPLER_MODE_MONO = 2
362	} VGPU10_SAMPLER_MODE;
363
364	typedef enum {
365	VGPU10_INSTRUCTION_TEST_ZERO = 0,
366	VGPU10_INSTRUCTION_TEST_NONZERO = 1
367	} VGPU10_INSTRUCTION_TEST_BOOLEAN;
368
369	typedef enum {
370	VGPU10_CB_IMMEDIATE_INDEXED = 0,
371	VGPU10_CB_DYNAMIC_INDEXED = 1
372	} VGPU10_CB_ACCESS_PATTERN;
373
374	typedef enum {
375	VGPU10_PRIMITIVE_UNDEFINED = 0,
376	VGPU10_PRIMITIVE_POINT = 1,
377	VGPU10_PRIMITIVE_LINE = 2,
378	VGPU10_PRIMITIVE_TRIANGLE = 3,
379	VGPU10_PRIMITIVE_LINE_ADJ = 6,
380	VGPU10_PRIMITIVE_TRIANGLE_ADJ = 7,
381	VGPU10_PRIMITIVE_SM40_MAX = 7,
382
383	/* DX11 */
384	VGPU10_PRIMITIVE_1_CONTROL_POINT_PATCH = 8,
385	VGPU10_PRIMITIVE_2_CONTROL_POINT_PATCH = 9,
386	VGPU10_PRIMITIVE_3_CONTROL_POINT_PATCH = 10,
387	VGPU10_PRIMITIVE_4_CONTROL_POINT_PATCH = 11,
388	VGPU10_PRIMITIVE_5_CONTROL_POINT_PATCH = 12,
389	VGPU10_PRIMITIVE_6_CONTROL_POINT_PATCH = 13,
390	VGPU10_PRIMITIVE_7_CONTROL_POINT_PATCH = 14,
391	VGPU10_PRIMITIVE_8_CONTROL_POINT_PATCH = 15,
392	VGPU10_PRIMITIVE_9_CONTROL_POINT_PATCH = 16,
393	VGPU10_PRIMITIVE_10_CONTROL_POINT_PATCH = 17,
394	VGPU10_PRIMITIVE_11_CONTROL_POINT_PATCH = 18,
395	VGPU10_PRIMITIVE_12_CONTROL_POINT_PATCH = 19,
396	VGPU10_PRIMITIVE_13_CONTROL_POINT_PATCH = 20,
397	VGPU10_PRIMITIVE_14_CONTROL_POINT_PATCH = 21,
398	VGPU10_PRIMITIVE_15_CONTROL_POINT_PATCH = 22,
399	VGPU10_PRIMITIVE_16_CONTROL_POINT_PATCH = 23,
400	VGPU10_PRIMITIVE_17_CONTROL_POINT_PATCH = 24,
401	VGPU10_PRIMITIVE_18_CONTROL_POINT_PATCH = 25,
402	VGPU10_PRIMITIVE_19_CONTROL_POINT_PATCH = 26,
403	VGPU10_PRIMITIVE_20_CONTROL_POINT_PATCH = 27,
404	VGPU10_PRIMITIVE_21_CONTROL_POINT_PATCH = 28,
405	VGPU10_PRIMITIVE_22_CONTROL_POINT_PATCH = 29,
406	VGPU10_PRIMITIVE_23_CONTROL_POINT_PATCH = 30,
407	VGPU10_PRIMITIVE_24_CONTROL_POINT_PATCH = 31,
408	VGPU10_PRIMITIVE_25_CONTROL_POINT_PATCH = 32,
409	VGPU10_PRIMITIVE_26_CONTROL_POINT_PATCH = 33,
410	VGPU10_PRIMITIVE_27_CONTROL_POINT_PATCH = 34,
411	VGPU10_PRIMITIVE_28_CONTROL_POINT_PATCH = 35,
412	VGPU10_PRIMITIVE_29_CONTROL_POINT_PATCH = 36,
413	VGPU10_PRIMITIVE_30_CONTROL_POINT_PATCH = 37,
414	VGPU10_PRIMITIVE_31_CONTROL_POINT_PATCH = 38,
415	VGPU10_PRIMITIVE_32_CONTROL_POINT_PATCH = 39,
416	VGPU10_PRIMITIVE_MAX = 39
417	} VGPU10_PRIMITIVE;
418
419	typedef enum {
420	VGPU10_PRIMITIVE_TOPOLOGY_UNDEFINED = 0,
421	VGPU10_PRIMITIVE_TOPOLOGY_POINTLIST = 1,
422	VGPU10_PRIMITIVE_TOPOLOGY_LINELIST = 2,
423	VGPU10_PRIMITIVE_TOPOLOGY_LINESTRIP = 3,
424	VGPU10_PRIMITIVE_TOPOLOGY_TRIANGLELIST = 4,
425	VGPU10_PRIMITIVE_TOPOLOGY_TRIANGLESTRIP = 5,
426	VGPU10_PRIMITIVE_TOPOLOGY_LINELIST_ADJ = 10,
427	VGPU10_PRIMITIVE_TOPOLOGY_LINESTRIP_ADJ = 11,
428	VGPU10_PRIMITIVE_TOPOLOGY_TRIANGLELIST_ADJ = 12,
429	VGPU10_PRIMITIVE_TOPOLOGY_TRIANGLESTRIP_ADJ = 13
430	} VGPU10_PRIMITIVE_TOPOLOGY;
431
432	typedef enum {
433	VGPU10_CUSTOMDATA_COMMENT = 0,
434	VGPU10_CUSTOMDATA_DEBUGINFO = 1,
435	VGPU10_CUSTOMDATA_OPAQUE = 2,
436	VGPU10_CUSTOMDATA_DCL_IMMEDIATE_CONSTANT_BUFFER = 3
437	} VGPU10_CUSTOMDATA_CLASS;
438
439	typedef enum {
440	VGPU10_RESINFO_RETURN_FLOAT = 0,
441	VGPU10_RESINFO_RETURN_RCPFLOAT = 1,
442	VGPU10_RESINFO_RETURN_UINT = 2
443	} VGPU10_RESINFO_RETURN_TYPE;
444
445
446	typedef enum {
447	VGPU10_INSTRUCTION_RETURN_FLOAT = 0,
448	VGPU10_INSTRUCTION_RETURN_UINT = 1
449	} VGPU10_INSTRUCTION_RETURN_TYPE;
450
451	/* DX11 */
452	typedef enum {
453	VGPU10_TESSELLATOR_DOMAIN_UNDEFINED = 0,
454	VGPU10_TESSELLATOR_DOMAIN_ISOLINE = 1,
455	VGPU10_TESSELLATOR_DOMAIN_TRI = 2,
456	VGPU10_TESSELLATOR_DOMAIN_QUAD = 3,
457	VGPU10_TESSELLATOR_DOMAIN_MAX = 3
458	} VGPU10_TESSELLATOR_DOMAIN;
459
460	/* DX11 */
461	typedef enum {
462	VGPU10_TESSELLATOR_PARTITIONING_UNDEFINED = 0,
463	VGPU10_TESSELLATOR_PARTITIONING_INTEGER = 1,
464	VGPU10_TESSELLATOR_PARTITIONING_POW2 = 2,
465	VGPU10_TESSELLATOR_PARTITIONING_FRACTIONAL_ODD = 3,
466	VGPU10_TESSELLATOR_PARTITIONING_FRACTIONAL_EVEN = 4,
467	VGPU10_TESSELLATOR_PARTITIONING_MAX = 4
468	} VGPU10_TESSELLATOR_PARTITIONING;
469
470	/* DX11 */
471	typedef enum {
472	VGPU10_TESSELLATOR_OUTPUT_UNDEFINED = 0,
473	VGPU10_TESSELLATOR_OUTPUT_POINT = 1,
474	VGPU10_TESSELLATOR_OUTPUT_LINE = 2,
475	VGPU10_TESSELLATOR_OUTPUT_TRIANGLE_CW = 3,
476	VGPU10_TESSELLATOR_OUTPUT_TRIANGLE_CCW = 4,
477	VGPU10_TESSELLATOR_OUTPUT_MAX = 4
478	} VGPU10_TESSELLATOR_OUTPUT_PRIMITIVE;
479
480	typedef union {
481	struct {
482	unsigned int opcodeType : 11; /* VGPU10_OPCODE_TYPE */
483	unsigned int interpolationMode : 4; /* VGPU10_INTERPOLATION_MODE */
484	unsigned int : 3;
485	unsigned int testBoolean : 1; /* VGPU10_INSTRUCTION_TEST_BOOLEAN */
486	unsigned int preciseValues : 4; /* DX11 VGPU10_OPERAND_4_COMPONENT_MASK_* */
487	unsigned int : 1;
488	unsigned int instructionLength : 7;
489	unsigned int extended : 1;
490	};
491	/* VGPU10_OPCODE_VMWARE */
492	struct {
493	unsigned int : 11;
494	unsigned int vmwareOpcodeType : 4; /* VGPU10_VMWARE_OPCODE_TYPE */
495	};
496	struct {
497	unsigned int : 11;
498	unsigned int resourceDimension : 5; /* VGPU10_RESOURCE_DIMENSION */
499	unsigned int sampleCount : 7;
500	};
501	struct {
502	unsigned int : 11;
503	unsigned int samplerMode : 4; /* VGPU10_SAMPLER_MODE */
504	};
505	struct {
506	unsigned int : 11;
507	unsigned int accessPattern : 1; /* VGPU10_CB_ACCESS_PATTERN */
508	};
509	struct {
510	unsigned int : 11;
511	unsigned int primitive : 6; /* VGPU10_PRIMITIVE */
512	};
513	struct {
514	unsigned int : 11;
515	unsigned int primitiveTopology : 6; /* VGPU10_PRIMITIVE_TOPOLOGY */
516	};
517	struct {
518	unsigned int : 11;
519	unsigned int customDataClass : 21; /* VGPU10_CUSTOMDATA_CLASS */
520	};
521	struct {
522	unsigned int : 11;
523	unsigned int resinfoReturnType : 2; /* VGPU10_RESINFO_RETURN_TYPE */
524	unsigned int saturate : 1;
525	};
526	struct {
527	unsigned int : 11;
528	unsigned int refactoringAllowed : 1;
529
530	/* DX11 */
531	unsigned int enableDoublePrecisionFloatOps : 1;
532	unsigned int forceEarlyDepthStencil : 1;
533	unsigned int enableRawAndStructuredBuffers : 1;
534	};
535	struct {
536	unsigned int : 11;
537	unsigned int instReturnType : 2; /* VGPU10_INSTRUCTION_RETURN_TYPE */
538	};
539
540	/* DX11 */
541	struct {
542	unsigned int : 11;
543	unsigned int syncThreadsInGroup : 1;
544	unsigned int syncThreadGroupShared : 1;
545	unsigned int syncUAVMemoryGroup : 1;
546	unsigned int syncUAVMemoryGlobal : 1;
547	};
548	struct {
549	unsigned int : 11; /* VGPU10_OPCODE_DCL_INPUT_CONTROL_POINT_COUNT
550	* VGPU10_OPCODE_DCL_OUTPUT_CONTROL_POINT_COUNT */
551	unsigned int controlPointCount : 6;
552	};
553	struct {
554	unsigned int : 11; /* VGPU10_OPCODE_DCL_TESS_DOMAIN */
555	unsigned int tessDomain : 2; /* VGPU10_TESSELLATOR_DOMAIN */
556	};
557	struct {
558	unsigned int : 11; /* VGPU10_OPCODE_DCL_TESS_PARTITIONING */
559	unsigned int tessPartitioning : 3; /* VGPU10_TESSELLATOR_PARTITIONING */
560	};
561	struct {
562	unsigned int : 11; /* VGPU10_OPCODE_DCL_TESS_OUTPUT_PRIMITIVE */
563	unsigned int tessOutputPrimitive : 3; /* VGPU10_TESSELLATOR_OUTPUT_PRIMITIVE */
564	};
565	struct {
566	unsigned int : 11; /* VGPU10_OPCODE_DCL_INTERFACE */
567	unsigned int interfaceIndexedDynamically : 1;
568	};
569	struct {
570	unsigned int : 11; /* VGPU10_OPCODE_DCL_UAV_* */
571	unsigned int uavResourceDimension : 5; /* VGPU10_RESOURCE_DIMENSION */
572	unsigned int globallyCoherent : 1;
573	unsigned int : 6;
574	unsigned int uavHasCounter : 1;
575	};
576	uint32 value;
577	} VGPU10OpcodeToken0;
578
579
580	typedef enum {
581	VGPU10_EXTENDED_OPCODE_EMPTY = 0,
582	VGPU10_EXTENDED_OPCODE_SAMPLE_CONTROLS
583	} VGPU10_EXTENDED_OPCODE_TYPE;
584
585	typedef union {
586	struct {
587	unsigned int opcodeType : 6; /* VGPU10_EXTENDED_OPCODE_TYPE */
588	unsigned int : 3;
589	unsigned int offsetU : 4; /* Two's complement. */
590	unsigned int offsetV : 4; /* Two's complement. */
591	unsigned int offsetW : 4; /* Two's complement. */
592	unsigned int : 10;
593	unsigned int extended : 1;
594	};
595	uint32 value;
596	} VGPU10OpcodeToken1;
597
598
599	typedef enum {
600	VGPU10_OPERAND_0_COMPONENT = 0,
601	VGPU10_OPERAND_1_COMPONENT = 1,
602	VGPU10_OPERAND_4_COMPONENT = 2,
603	VGPU10_OPERAND_N_COMPONENT = 3 /* Unused for now. */
604	} VGPU10_OPERAND_NUM_COMPONENTS;
605
606	typedef enum {
607	VGPU10_OPERAND_4_COMPONENT_MASK_MODE = 0,
608	VGPU10_OPERAND_4_COMPONENT_SWIZZLE_MODE = 1,
609	VGPU10_OPERAND_4_COMPONENT_SELECT_1_MODE = 2
610	} VGPU10_OPERAND_4_COMPONENT_SELECTION_MODE;
611
612	#define VGPU10_OPERAND_4_COMPONENT_MASK_X 0x1
613	#define VGPU10_OPERAND_4_COMPONENT_MASK_Y 0x2
614	#define VGPU10_OPERAND_4_COMPONENT_MASK_Z 0x4
615	#define VGPU10_OPERAND_4_COMPONENT_MASK_W 0x8
616
617	#define VGPU10_OPERAND_4_COMPONENT_MASK_XY (VGPU10_OPERAND_4_COMPONENT_MASK_X \| VGPU10_OPERAND_4_COMPONENT_MASK_Y)
618	#define VGPU10_OPERAND_4_COMPONENT_MASK_XZ (VGPU10_OPERAND_4_COMPONENT_MASK_X \| VGPU10_OPERAND_4_COMPONENT_MASK_Z)
619	#define VGPU10_OPERAND_4_COMPONENT_MASK_XW (VGPU10_OPERAND_4_COMPONENT_MASK_X \| VGPU10_OPERAND_4_COMPONENT_MASK_W)
620	#define VGPU10_OPERAND_4_COMPONENT_MASK_YZ (VGPU10_OPERAND_4_COMPONENT_MASK_Y \| VGPU10_OPERAND_4_COMPONENT_MASK_Z)
621	#define VGPU10_OPERAND_4_COMPONENT_MASK_YW (VGPU10_OPERAND_4_COMPONENT_MASK_Y \| VGPU10_OPERAND_4_COMPONENT_MASK_W)
622	#define VGPU10_OPERAND_4_COMPONENT_MASK_ZW (VGPU10_OPERAND_4_COMPONENT_MASK_Z \| VGPU10_OPERAND_4_COMPONENT_MASK_W)
623	#define VGPU10_OPERAND_4_COMPONENT_MASK_XYZ (VGPU10_OPERAND_4_COMPONENT_MASK_XY \| VGPU10_OPERAND_4_COMPONENT_MASK_Z)
624	#define VGPU10_OPERAND_4_COMPONENT_MASK_XYW (VGPU10_OPERAND_4_COMPONENT_MASK_XY \| VGPU10_OPERAND_4_COMPONENT_MASK_W)
625	#define VGPU10_OPERAND_4_COMPONENT_MASK_XZW (VGPU10_OPERAND_4_COMPONENT_MASK_XZ \| VGPU10_OPERAND_4_COMPONENT_MASK_W)
626	#define VGPU10_OPERAND_4_COMPONENT_MASK_YZW (VGPU10_OPERAND_4_COMPONENT_MASK_YZ \| VGPU10_OPERAND_4_COMPONENT_MASK_W)
627	#define VGPU10_OPERAND_4_COMPONENT_MASK_XYZW (VGPU10_OPERAND_4_COMPONENT_MASK_XYZ \| VGPU10_OPERAND_4_COMPONENT_MASK_W)
628	#define VGPU10_OPERAND_4_COMPONENT_MASK_ALL VGPU10_OPERAND_4_COMPONENT_MASK_XYZW
629
630	#define VGPU10_REGISTER_INDEX_FROM_SEMANTIC 0xffffffff
631
632	typedef enum {
633	VGPU10_COMPONENT_X = 0,
634	VGPU10_COMPONENT_Y = 1,
635	VGPU10_COMPONENT_Z = 2,
636	VGPU10_COMPONENT_W = 3
637	} VGPU10_COMPONENT_NAME;
638
639	typedef enum {
640	VGPU10_OPERAND_TYPE_TEMP = 0,
641	VGPU10_OPERAND_TYPE_INPUT = 1,
642	VGPU10_OPERAND_TYPE_OUTPUT = 2,
643	VGPU10_OPERAND_TYPE_INDEXABLE_TEMP = 3,
644	VGPU10_OPERAND_TYPE_IMMEDIATE32 = 4,
645	VGPU10_OPERAND_TYPE_IMMEDIATE64 = 5,
646	VGPU10_OPERAND_TYPE_SAMPLER = 6,
647	VGPU10_OPERAND_TYPE_RESOURCE = 7,
648	VGPU10_OPERAND_TYPE_CONSTANT_BUFFER = 8,
649	VGPU10_OPERAND_TYPE_IMMEDIATE_CONSTANT_BUFFER = 9,
650	VGPU10_OPERAND_TYPE_LABEL = 10,
651	VGPU10_OPERAND_TYPE_INPUT_PRIMITIVEID = 11,
652	VGPU10_OPERAND_TYPE_OUTPUT_DEPTH = 12,
653	VGPU10_OPERAND_TYPE_NULL = 13,
654	VGPU10_OPERAND_TYPE_SM40_MAX = 13,
655
656	/* DX10.1 */
657	VGPU10_OPERAND_TYPE_RASTERIZER = 14,
658	VGPU10_OPERAND_TYPE_OUTPUT_COVERAGE_MASK = 15,
659	VGPU10_OPERAND_TYPE_SM41_MAX = 15,
660
661	/* DX11 */
662	VGPU10_OPERAND_TYPE_STREAM = 16,
663	VGPU10_OPERAND_TYPE_FUNCTION_BODY = 17,
664	VGPU10_OPERAND_TYPE_FUNCTION_TABLE = 18,
665	VGPU10_OPERAND_TYPE_INTERFACE = 19,
666	VGPU10_OPERAND_TYPE_FUNCTION_INPUT = 20,
667	VGPU10_OPERAND_TYPE_FUNCTION_OUTPUT = 21,
668	VGPU10_OPERAND_TYPE_OUTPUT_CONTROL_POINT_ID = 22,
669	VGPU10_OPERAND_TYPE_INPUT_FORK_INSTANCE_ID = 23,
670	VGPU10_OPERAND_TYPE_INPUT_JOIN_INSTANCE_ID = 24,
671	VGPU10_OPERAND_TYPE_INPUT_CONTROL_POINT = 25,
672	VGPU10_OPERAND_TYPE_OUTPUT_CONTROL_POINT = 26,
673	VGPU10_OPERAND_TYPE_INPUT_PATCH_CONSTANT = 27,
674	VGPU10_OPERAND_TYPE_INPUT_DOMAIN_POINT = 28,
675	VGPU10_OPERAND_TYPE_THIS_POINTER = 29,
676	VGPU10_OPERAND_TYPE_UAV = 30,
677	VGPU10_OPERAND_TYPE_THREAD_GROUP_SHARED_MEMORY = 31,
678	VGPU10_OPERAND_TYPE_INPUT_THREAD_ID = 32,
679	VGPU10_OPERAND_TYPE_INPUT_THREAD_GROUP_ID = 33,
680	VGPU10_OPERAND_TYPE_INPUT_THREAD_ID_IN_GROUP = 34,
681	VGPU10_OPERAND_TYPE_INPUT_COVERAGE_MASK = 35,
682	VGPU10_OPERAND_TYPE_INPUT_THREAD_ID_IN_GROUP_FLATTENED = 36,
683	VGPU10_OPERAND_TYPE_INPUT_GS_INSTANCE_ID = 37,
684	VGPU10_OPERAND_TYPE_OUTPUT_DEPTH_GREATER_EQUAL = 38,
685	VGPU10_OPERAND_TYPE_OUTPUT_DEPTH_LESS_EQUAL = 39,
686	VGPU10_OPERAND_TYPE_CYCLE_COUNTER = 40,
687	VGPU10_OPERAND_TYPE_SM50_MAX = 40,
688
689	VGPU10_NUM_OPERANDS
690	} VGPU10_OPERAND_TYPE;
691
692	typedef enum {
693	VGPU10_OPERAND_INDEX_0D = 0,
694	VGPU10_OPERAND_INDEX_1D = 1,
695	VGPU10_OPERAND_INDEX_2D = 2,
696	VGPU10_OPERAND_INDEX_3D = 3
697	} VGPU10_OPERAND_INDEX_DIMENSION;
698
699	typedef enum {
700	VGPU10_OPERAND_INDEX_IMMEDIATE32 = 0,
701	VGPU10_OPERAND_INDEX_IMMEDIATE64 = 1,
702	VGPU10_OPERAND_INDEX_RELATIVE = 2,
703	VGPU10_OPERAND_INDEX_IMMEDIATE32_PLUS_RELATIVE = 3,
704	VGPU10_OPERAND_INDEX_IMMEDIATE64_PLUS_RELATIVE = 4
705	} VGPU10_OPERAND_INDEX_REPRESENTATION;
706
707	typedef union {
708	struct {
709	unsigned int numComponents : 2; /* VGPU10_OPERAND_NUM_COMPONENTS */
710	unsigned int selectionMode : 2; /* VGPU10_OPERAND_4_COMPONENT_SELECTION_MODE */
711	unsigned int mask : 4; /* D3D10_SB_OPERAND_4_COMPONENT_MASK_* */
712	unsigned int : 4;
713	unsigned int operandType : 8; /* VGPU10_OPERAND_TYPE */
714	unsigned int indexDimension : 2; /* VGPU10_OPERAND_INDEX_DIMENSION */
715	unsigned int index0Representation : 3; /* VGPU10_OPERAND_INDEX_REPRESENTATION */
716	unsigned int index1Representation : 3; /* VGPU10_OPERAND_INDEX_REPRESENTATION */
717	unsigned int : 3;
718	unsigned int extended : 1;
719	};
720	struct {
721	unsigned int : 4;
722	unsigned int swizzleX : 2; /* VGPU10_COMPONENT_NAME */
723	unsigned int swizzleY : 2; /* VGPU10_COMPONENT_NAME */
724	unsigned int swizzleZ : 2; /* VGPU10_COMPONENT_NAME */
725	unsigned int swizzleW : 2; /* VGPU10_COMPONENT_NAME */
726	};
727	struct {
728	unsigned int : 4;
729	unsigned int selectMask : 2; /* VGPU10_COMPONENT_NAME */
730	};
731	uint32 value;
732	} VGPU10OperandToken0;
733
734
735	typedef enum {
736	VGPU10_EXTENDED_OPERAND_EMPTY = 0,
737	VGPU10_EXTENDED_OPERAND_MODIFIER = 1
738	} VGPU10_EXTENDED_OPERAND_TYPE;
739
740	typedef enum {
741	VGPU10_OPERAND_MODIFIER_NONE = 0,
742	VGPU10_OPERAND_MODIFIER_NEG = 1,
743	VGPU10_OPERAND_MODIFIER_ABS = 2,
744	VGPU10_OPERAND_MODIFIER_ABSNEG = 3
745	} VGPU10_OPERAND_MODIFIER;
746
747	typedef union {
748	struct {
749	unsigned int extendedOperandType : 6; /* VGPU10_EXTENDED_OPERAND_TYPE */
750	unsigned int operandModifier : 8; /* VGPU10_OPERAND_MODIFIER */
751	unsigned int : 17;
752	unsigned int extended : 1;
753	};
754	uint32 value;
755	} VGPU10OperandToken1;
756
757
758	typedef enum {
759	VGPU10_RETURN_TYPE_MIN = 1,
760	VGPU10_RETURN_TYPE_UNORM = 1,
761	VGPU10_RETURN_TYPE_SNORM = 2,
762	VGPU10_RETURN_TYPE_SINT = 3,
763	VGPU10_RETURN_TYPE_UINT = 4,
764	VGPU10_RETURN_TYPE_FLOAT = 5,
765	VGPU10_RETURN_TYPE_MIXED = 6,
766	VGPU10_RETURN_TYPE_MAX = 6
767	} VGPU10_RESOURCE_RETURN_TYPE;
768
769	typedef union {
770	struct {
771	unsigned int component0 : 4; /* VGPU10_RESOURCE_RETURN_TYPE */
772	unsigned int component1 : 4; /* VGPU10_RESOURCE_RETURN_TYPE */
773	unsigned int component2 : 4; /* VGPU10_RESOURCE_RETURN_TYPE */
774	unsigned int component3 : 4; /* VGPU10_RESOURCE_RETURN_TYPE */
775	};
776	uint32 value;
777	} VGPU10ResourceReturnTypeToken;
778
779
780	typedef enum {
781	VGPU10_NAME_MIN = 0,
782	VGPU10_NAME_UNDEFINED = 0,
783	VGPU10_NAME_POSITION = 1,
784	VGPU10_NAME_CLIP_DISTANCE = 2,
785	VGPU10_NAME_CULL_DISTANCE = 3,
786	VGPU10_NAME_RENDER_TARGET_ARRAY_INDEX = 4,
787	VGPU10_NAME_VIEWPORT_ARRAY_INDEX = 5,
788	VGPU10_NAME_VERTEX_ID = 6,
789	VGPU10_NAME_PRIMITIVE_ID = 7,
790	VGPU10_NAME_INSTANCE_ID = 8,
791	VGPU10_NAME_IS_FRONT_FACE = 9,
792	VGPU10_NAME_SAMPLE_INDEX = 10,
793	VGPU10_NAME_SM40_MAX = 10,
794
795	/* DX11 */
796	VGPU10_NAME_FINAL_QUAD_U_EQ_0_EDGE_TESSFACTOR = 11,
797	VGPU10_NAME_FINAL_QUAD_V_EQ_0_EDGE_TESSFACTOR = 12,
798	VGPU10_NAME_FINAL_QUAD_U_EQ_1_EDGE_TESSFACTOR = 13,
799	VGPU10_NAME_FINAL_QUAD_V_EQ_1_EDGE_TESSFACTOR = 14,
800	VGPU10_NAME_FINAL_QUAD_U_INSIDE_TESSFACTOR = 15,
801	VGPU10_NAME_FINAL_QUAD_V_INSIDE_TESSFACTOR = 16,
802	VGPU10_NAME_FINAL_TRI_U_EQ_0_EDGE_TESSFACTOR = 17,
803	VGPU10_NAME_FINAL_TRI_V_EQ_0_EDGE_TESSFACTOR = 18,
804	VGPU10_NAME_FINAL_TRI_W_EQ_0_EDGE_TESSFACTOR = 19,
805	VGPU10_NAME_FINAL_TRI_INSIDE_TESSFACTOR = 20,
806	VGPU10_NAME_FINAL_LINE_DETAIL_TESSFACTOR = 21,
807	VGPU10_NAME_FINAL_LINE_DENSITY_TESSFACTOR = 22,
808
809	VGPU10_NAME_MAX = 22
810	} VGPU10_SYSTEM_NAME;
811
812	typedef union {
813	struct {
814	unsigned int name : 16; /* VGPU10_SYSTEM_NAME */
815	};
816	uint32 value;
817	} VGPU10NameToken;
818
819	#endif

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source: vbox/trunk/src/VBox/Devices/Graphics/vmsvga_include/VGPU10ShaderTokens.h@ 86900

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