DevVGA.cpp@ 87766

Last change on this file since 87766 was 87760, checked in by vboxsync, 4 years ago
VMM/TM,VMM/DevHlp: Require flag on timers that are to be used in ring-0 (and while refactoring a counte flag to check that all timers have been checked). Removed obsolete timer device helpers. bugref:9943
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File size: 258.5 KB

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1	/* $Id: DevVGA.cpp 87760 2021-02-15 22:45:27Z vboxsync $ */
2	/** @file
3	* DevVGA - VBox VGA/VESA device.
4	*/
5
6	/*
7	* Copyright (C) 2006-2020 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	* --------------------------------------------------------------------
17	*
18	* This code is based on:
19	*
20	* QEMU VGA Emulator.
21	*
22	* Copyright (c) 2003 Fabrice Bellard
23	*
24	* Permission is hereby granted, free of charge, to any person obtaining a copy
25	* of this software and associated documentation files (the "Software"), to deal
26	* in the Software without restriction, including without limitation the rights
27	* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
28	* copies of the Software, and to permit persons to whom the Software is
29	* furnished to do so, subject to the following conditions:
30	*
31	* The above copyright notice and this permission notice shall be included in
32	* all copies or substantial portions of the Software.
33	*
34	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
35	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
36	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
37	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
38	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
39	* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
40	* THE SOFTWARE.
41	*/
42
43
44	/*********************************************************************************************************************************
45	* Defined Constants And Macros *
46	*********************************************************************************************************************************/
47
48	/* WARNING!!! All defines that affect VGAState should be placed in DevVGA.h !!!
49	* NEVER place them here as this would lead to VGASTATE inconsistency
50	* across different .cpp files !!!
51	*/
52
53	#ifdef VBOX_WITH_HGSMI
54	#define PCIDEV_2_VGASTATE(pPciDev) ((PVGASTATE)((uintptr_t)pPciDev - RT_OFFSETOF(VGASTATE, Dev)))
55	#endif /* VBOX_WITH_HGSMI */
56
57	/* VGA text mode blinking constants (cursor and blinking chars). */
58	#define VGA_BLINK_PERIOD_FULL (RT_NS_100MS * 4) /*< Blink cycle length. /
59	#define VGA_BLINK_PERIOD_ON (RT_NS_100MS * 2) /*< How long cursor/text is visible. /
60
61	/* EGA compatible switch values (in high nibble).
62	* XENIX 2.1.x/2.2.x is known to rely on the switch values.
63	*/
64	#define EGA_SWITCHES 0x90 /* Off-on-on-off, high-res color EGA display. */
65
66
67	/*********************************************************************************************************************************
68	* Header Files *
69	*********************************************************************************************************************************/
70	#define LOG_GROUP LOG_GROUP_DEV_VGA
71	#include <VBox/vmm/pdmdev.h>
72	#include <VBox/vmm/pgm.h>
73	#include <VBox/AssertGuest.h>
74	#ifdef IN_RING3
75	# include <iprt/mem.h>
76	# include <iprt/ctype.h>
77	#endif /* IN_RING3 */
78	#include <iprt/assert.h>
79	#include <iprt/asm.h>
80	#include <iprt/file.h>
81	#include <iprt/time.h>
82	#include <iprt/string.h>
83	#include <iprt/uuid.h>
84
85	#include <iprt/formats/bmp.h>
86
87	#include <VBox/VMMDev.h>
88	#include <VBoxVideo.h>
89	#include <VBox/bioslogo.h>
90
91	/* should go BEFORE any other DevVGA include to make all DevVGA.h config defines be visible */
92	#include "DevVGA.h"
93
94	#if defined(IN_RING3) && !defined(VBOX_DEVICE_STRUCT_TESTCASE)
95	# include "DevVGAModes.h"
96	# include <stdio.h> /* sscan */
97	#endif
98
99	#include "VBoxDD.h"
100	#include "VBoxDD2.h"
101
102	#ifdef VBOX_WITH_VMSVGA
103	#include "DevVGA-SVGA.h"
104	#endif
105
106
107	/*********************************************************************************************************************************
108	* Structures and Typedefs *
109	*********************************************************************************************************************************/
110
111	/** The BIOS boot menu text position, X. */
112	#define LOGO_F12TEXT_X 304
113	/** The BIOS boot menu text position, Y. */
114	#define LOGO_F12TEXT_Y 460
115
116	/** Width of the "Press F12 to select boot device." bitmap.
117	Anything that exceeds the limit of F12BootText below is filled with
118	background. */
119	#define LOGO_F12TEXT_WIDTH 286
120	/** Height of the boot device selection bitmap, see LOGO_F12TEXT_WIDTH. */
121	#define LOGO_F12TEXT_HEIGHT 12
122
123	/** The BIOS logo delay time (msec). */
124	#define LOGO_DELAY_TIME 2000
125
126	#define LOGO_MAX_WIDTH 640
127	#define LOGO_MAX_HEIGHT 480
128	#define LOGO_MAX_SIZE LOGO_MAX_WIDTH * LOGO_MAX_HEIGHT * 4
129
130
131	/*********************************************************************************************************************************
132	* Global Variables *
133	*********************************************************************************************************************************/
134	#ifdef IN_RING3
135	/* "Press F12 to select boot device." bitmap. */
136	static const uint8_t g_abLogoF12BootText[] =
137	{
138	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
139	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
140	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x07, 0x0F, 0x7C,
141	0xF8, 0xF0, 0x01, 0xE0, 0x81, 0x9F, 0x3F, 0x00, 0x70, 0xF8, 0x00, 0xE0, 0xC3,
142	0x07, 0x0F, 0x1F, 0x3E, 0x70, 0x00, 0xF0, 0xE1, 0xC3, 0x07, 0x0E, 0x00, 0x6E,
143	0x7C, 0x60, 0xE0, 0xE1, 0xC3, 0x07, 0xC6, 0x80, 0x81, 0x31, 0x63, 0xC6, 0x00,
144	0x30, 0x80, 0x61, 0x0C, 0x00, 0x36, 0x63, 0x00, 0x8C, 0x19, 0x83, 0x61, 0xCC,
145	0x18, 0x36, 0x00, 0xCC, 0x8C, 0x19, 0xC3, 0x06, 0xC0, 0x8C, 0x31, 0x3C, 0x30,
146	0x8C, 0x19, 0x83, 0x31, 0x60, 0x60, 0x00, 0x0C, 0x18, 0x00, 0x0C, 0x60, 0x18,
147	0x00, 0x80, 0xC1, 0x18, 0x00, 0x30, 0x06, 0x60, 0x18, 0x30, 0x80, 0x01, 0x00,
148	0x33, 0x63, 0xC6, 0x30, 0x00, 0x30, 0x63, 0x80, 0x19, 0x0C, 0x03, 0x06, 0x00,
149	0x0C, 0x18, 0x18, 0xC0, 0x81, 0x03, 0x00, 0x03, 0x18, 0x0C, 0x00, 0x60, 0x30,
150	0x06, 0x00, 0x87, 0x01, 0x18, 0x06, 0x0C, 0x60, 0x00, 0xC0, 0xCC, 0x98, 0x31,
151	0x0C, 0x00, 0xCC, 0x18, 0x30, 0x0C, 0xC3, 0x80, 0x01, 0x00, 0x03, 0x66, 0xFE,
152	0x18, 0x30, 0x00, 0xC0, 0x02, 0x06, 0x06, 0x00, 0x18, 0x8C, 0x01, 0x60, 0xE0,
153	0x0F, 0x86, 0x3F, 0x03, 0x18, 0x00, 0x30, 0x33, 0x66, 0x0C, 0x03, 0x00, 0x33,
154	0xFE, 0x0C, 0xC3, 0x30, 0xE0, 0x0F, 0xC0, 0x87, 0x9B, 0x31, 0x63, 0xC6, 0x00,
155	0xF0, 0x80, 0x01, 0x03, 0x00, 0x06, 0x63, 0x00, 0x8C, 0x19, 0x83, 0x61, 0xCC,
156	0x18, 0x06, 0x00, 0x6C, 0x8C, 0x19, 0xC3, 0x00, 0x80, 0x8D, 0x31, 0xC3, 0x30,
157	0x8C, 0x19, 0x03, 0x30, 0xB3, 0xC3, 0x87, 0x0F, 0x1F, 0x00, 0x2C, 0x60, 0x80,
158	0x01, 0xE0, 0x87, 0x0F, 0x00, 0x3E, 0x7C, 0x60, 0xF0, 0xE1, 0xE3, 0x07, 0x00,
159	0x0F, 0x3E, 0x7C, 0xFC, 0x00, 0xC0, 0xC3, 0xC7, 0x30, 0x0E, 0x3E, 0x7C, 0x00,
160	0xCC, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x23, 0x1E, 0xC0, 0x00, 0x60, 0x00,
161	0x00, 0x00, 0x00, 0x00, 0x18, 0x00, 0x00, 0x60, 0x00, 0xC0, 0x00, 0x00, 0x00,
162	0x0C, 0x00, 0xC0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x33, 0x00, 0x00,
163	0x00, 0x00, 0x00, 0xC0, 0x0C, 0x87, 0x31, 0x00, 0x18, 0x00, 0x00, 0x00, 0x00,
164	0x00, 0x06, 0x00, 0x00, 0x18, 0x00, 0x30, 0x00, 0x00, 0x00, 0x03, 0x00, 0x30,
165	0x00, 0x00, 0xC0, 0x00, 0x00, 0x00, 0xE0, 0x07, 0x00, 0x00, 0x00, 0x00, 0x00,
166	0xF8, 0x83, 0xC1, 0x07, 0x00, 0x04, 0x00, 0x00, 0x00, 0x00, 0xC0, 0x01, 0x00,
167	0x00, 0x04, 0x00, 0x0E, 0x00, 0x00, 0x80, 0x00, 0x00, 0x0E, 0x00, 0x00, 0x30,
168	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
169	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
170	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
171	};
172	#endif /* IN_RING3 */
173
174	#ifndef VBOX_DEVICE_STRUCT_TESTCASE /* Till the end of the file - doesn't count indent wise. */
175
176	#ifdef _MSC_VER
177	# pragma warning(push)
178	# pragma warning(disable:4310 4245) /* Buggy warnings: cast truncates constant value; conversion from 'int' to 'const uint8_t', signed/unsigned mismatch */
179	#endif
180
181	/* force some bits to zero */
182	static const uint8_t sr_mask[8] = {
183	(uint8_t)~0xfc,
184	(uint8_t)~0xc2,
185	(uint8_t)~0xf0,
186	(uint8_t)~0xc0,
187	(uint8_t)~0xf1,
188	(uint8_t)~0xff,
189	(uint8_t)~0xff,
190	(uint8_t)~0x01,
191	};
192
193	static const uint8_t gr_mask[16] = {
194	(uint8_t)~0xf0, /* 0x00 */
195	(uint8_t)~0xf0, /* 0x01 */
196	(uint8_t)~0xf0, /* 0x02 */
197	(uint8_t)~0xe0, /* 0x03 */
198	(uint8_t)~0xfc, /* 0x04 */
199	(uint8_t)~0x84, /* 0x05 */
200	(uint8_t)~0xf0, /* 0x06 */
201	(uint8_t)~0xf0, /* 0x07 */
202	(uint8_t)~0x00, /* 0x08 */
203	(uint8_t)~0xff, /* 0x09 */
204	(uint8_t)~0xff, /* 0x0a */
205	(uint8_t)~0xff, /* 0x0b */
206	(uint8_t)~0xff, /* 0x0c */
207	(uint8_t)~0xff, /* 0x0d */
208	(uint8_t)~0xff, /* 0x0e */
209	(uint8_t)~0xff, /* 0x0f */
210	};
211
212	#ifdef _MSC_VER
213	# pragma warning(pop)
214	#endif
215
216	#define cbswap_32(__x) \
217	((uint32_t)((((uint32_t)(__x) & (uint32_t)0x000000ffUL) << 24) \| \
218	(((uint32_t)(__x) & (uint32_t)0x0000ff00UL) << 8) \| \
219	(((uint32_t)(__x) & (uint32_t)0x00ff0000UL) >> 8) \| \
220	(((uint32_t)(__x) & (uint32_t)0xff000000UL) >> 24) ))
221
222	#ifdef WORDS_BIGENDIAN
223	# define PAT(x) cbswap_32(x)
224	#else
225	# define PAT(x) (x)
226	#endif
227
228	#ifdef WORDS_BIGENDIAN
229	# define BIG 1
230	#else
231	# define BIG 0
232	#endif
233
234	#ifdef WORDS_BIGENDIAN
235	#define GET_PLANE(data, p) (((data) >> (24 - (p) * 8)) & 0xff)
236	#else
237	#define GET_PLANE(data, p) (((data) >> ((p) * 8)) & 0xff)
238	#endif
239
240	static const uint32_t mask16[16] = {
241	PAT(0x00000000),
242	PAT(0x000000ff),
243	PAT(0x0000ff00),
244	PAT(0x0000ffff),
245	PAT(0x00ff0000),
246	PAT(0x00ff00ff),
247	PAT(0x00ffff00),
248	PAT(0x00ffffff),
249	PAT(0xff000000),
250	PAT(0xff0000ff),
251	PAT(0xff00ff00),
252	PAT(0xff00ffff),
253	PAT(0xffff0000),
254	PAT(0xffff00ff),
255	PAT(0xffffff00),
256	PAT(0xffffffff),
257	};
258
259	#undef PAT
260
261	#ifdef WORDS_BIGENDIAN
262	# define PAT(x) (x)
263	#else
264	# define PAT(x) cbswap_32(x)
265	#endif
266
267	#ifdef IN_RING3
268
269	static const uint32_t dmask16[16] = {
270	PAT(0x00000000),
271	PAT(0x000000ff),
272	PAT(0x0000ff00),
273	PAT(0x0000ffff),
274	PAT(0x00ff0000),
275	PAT(0x00ff00ff),
276	PAT(0x00ffff00),
277	PAT(0x00ffffff),
278	PAT(0xff000000),
279	PAT(0xff0000ff),
280	PAT(0xff00ff00),
281	PAT(0xff00ffff),
282	PAT(0xffff0000),
283	PAT(0xffff00ff),
284	PAT(0xffffff00),
285	PAT(0xffffffff),
286	};
287
288	static const uint32_t dmask4[4] = {
289	PAT(0x00000000),
290	PAT(0x0000ffff),
291	PAT(0xffff0000),
292	PAT(0xffffffff),
293	};
294
295	static uint32_t expand4[256];
296	static uint16_t expand2[256];
297	static uint8_t expand4to8[16];
298
299	#endif /* IN_RING3 */
300
301
302	/**
303	* Set a VRAM page dirty.
304	*
305	* @param pThis VGA instance data.
306	* @param offVRAM The VRAM offset of the page to set.
307	*/
308	DECLINLINE(void) vgaR3MarkDirty(PVGASTATE pThis, RTGCPHYS offVRAM)
309	{
310	AssertMsg(offVRAM < pThis->vram_size, ("offVRAM = %p, pThis->vram_size = %p\n", offVRAM, pThis->vram_size));
311	ASMBitSet(&pThis->au32DirtyBitmap[0], offVRAM >> PAGE_SHIFT);
312	pThis->fHasDirtyBits = true;
313	}
314
315	/**
316	* Tests if a VRAM page is dirty.
317	*
318	* @returns true if dirty.
319	* @returns false if clean.
320	* @param pThis VGA instance data.
321	* @param offVRAM The VRAM offset of the page to check.
322	*/
323	DECLINLINE(bool) vgaIsDirty(PVGASTATE pThis, RTGCPHYS offVRAM)
324	{
325	AssertMsg(offVRAM < pThis->vram_size, ("offVRAM = %p, pThis->vram_size = %p\n", offVRAM, pThis->vram_size));
326	return ASMBitTest(&pThis->au32DirtyBitmap[0], offVRAM >> PAGE_SHIFT);
327	}
328
329	#ifdef IN_RING3
330	/**
331	* Reset dirty flags in a give range.
332	*
333	* @param pThis VGA instance data.
334	* @param offVRAMStart Offset into the VRAM buffer of the first page.
335	* @param offVRAMEnd Offset into the VRAM buffer of the last page - exclusive.
336	*/
337	DECLINLINE(void) vgaR3ResetDirty(PVGASTATE pThis, RTGCPHYS offVRAMStart, RTGCPHYS offVRAMEnd)
338	{
339	Assert(offVRAMStart < pThis->vram_size);
340	Assert(offVRAMEnd <= pThis->vram_size);
341	Assert(offVRAMStart < offVRAMEnd);
342	ASMBitClearRange(&pThis->au32DirtyBitmap[0], offVRAMStart >> PAGE_SHIFT, offVRAMEnd >> PAGE_SHIFT);
343	}
344	#endif /* IN_RING3 */
345
346	/* Update the values needed for calculating Vertical Retrace and
347	* Display Enable status bits more or less accurately. The Display Enable
348	* bit is set (indicating disabled display signal) when either the
349	* horizontal (hblank) or vertical (vblank) blanking is active. The
350	* Vertical Retrace bit is set when vertical retrace (vsync) is active.
351	* Unless the CRTC is horribly misprogrammed, vsync implies vblank.
352	*/
353	static void vga_update_retrace_state(PVGASTATE pThis)
354	{
355	unsigned htotal_cclks, vtotal_lines, chars_per_sec;
356	unsigned hblank_start_cclk, hblank_end_cclk, hblank_width, hblank_skew_cclks;
357	unsigned vsync_start_line, vsync_end, vsync_width;
358	unsigned vblank_start_line, vblank_end, vblank_width;
359	unsigned char_dots, clock_doubled, clock_index;
360	const int clocks[] = {25175000, 28322000, 25175000, 25175000};
361	vga_retrace_s *r = &pThis->retrace_state;
362
363	/* For horizontal timings, we only care about the blanking start/end. */
364	htotal_cclks = pThis->cr[0x00] + 5;
365	hblank_start_cclk = pThis->cr[0x02];
366	hblank_end_cclk = (pThis->cr[0x03] & 0x1f) + ((pThis->cr[0x05] & 0x80) >> 2);
367	hblank_skew_cclks = (pThis->cr[0x03] >> 5) & 3;
368
369	/* For vertical timings, we need both the blanking start/end... */
370	vtotal_lines = pThis->cr[0x06] + ((pThis->cr[0x07] & 1) << 8) + ((pThis->cr[0x07] & 0x20) << 4) + 2;
371	vblank_start_line = pThis->cr[0x15] + ((pThis->cr[0x07] & 8) << 5) + ((pThis->cr[0x09] & 0x20) << 4);
372	vblank_end = pThis->cr[0x16];
373	/* ... and the vertical retrace (vsync) start/end. */
374	vsync_start_line = pThis->cr[0x10] + ((pThis->cr[0x07] & 4) << 6) + ((pThis->cr[0x07] & 0x80) << 2);
375	vsync_end = pThis->cr[0x11] & 0xf;
376
377	/* Calculate the blanking and sync widths. The way it's implemented in
378	* the VGA with limited-width compare counters is quite a piece of work.
379	*/
380	hblank_width = (hblank_end_cclk - hblank_start_cclk) & 0x3f;/* 6 bits */
381	vblank_width = (vblank_end - vblank_start_line) & 0xff; /* 8 bits */
382	vsync_width = (vsync_end - vsync_start_line) & 0xf; /* 4 bits */
383
384	/* Calculate the dot and character clock rates. */
385	clock_doubled = (pThis->sr[0x01] >> 3) & 1; /* Clock doubling bit. */
386	clock_index = (pThis->msr >> 2) & 3;
387	char_dots = (pThis->sr[0x01] & 1) ? 8 : 9; /* 8 or 9 dots per cclk. */
388
389	chars_per_sec = clocks[clock_index] / char_dots;
390	Assert(chars_per_sec); /* Can't possibly be zero. */
391
392	htotal_cclks <<= clock_doubled;
393
394	/* Calculate the number of cclks per entire frame. */
395	r->frame_cclks = vtotal_lines * htotal_cclks;
396	Assert(r->frame_cclks); /* Can't possibly be zero. */
397
398	if (r->v_freq_hz) { /* Could be set to emulate a specific rate. */
399	r->cclk_ns = 1000000000 / (r->frame_cclks * r->v_freq_hz);
400	} else {
401	r->cclk_ns = 1000000000 / chars_per_sec;
402	}
403	Assert(r->cclk_ns);
404	r->frame_ns = r->frame_cclks * r->cclk_ns;
405
406	/* Calculate timings in cclks/lines. Stored but not directly used. */
407	r->hb_start = hblank_start_cclk + hblank_skew_cclks;
408	r->hb_end = hblank_start_cclk + hblank_width + hblank_skew_cclks;
409	r->h_total = htotal_cclks;
410	Assert(r->h_total); /* Can't possibly be zero. */
411
412	r->vb_start = vblank_start_line;
413	r->vb_end = vblank_start_line + vblank_width + 1;
414	r->vs_start = vsync_start_line;
415	r->vs_end = vsync_start_line + vsync_width + 1;
416
417	/* Calculate timings in nanoseconds. For easier comparisons, the frame
418	* is considered to start at the beginning of the vertical and horizontal
419	* blanking period.
420	*/
421	r->h_total_ns = htotal_cclks * r->cclk_ns;
422	r->hb_end_ns = hblank_width * r->cclk_ns;
423	r->vb_end_ns = vblank_width * r->h_total_ns;
424	r->vs_start_ns = (r->vs_start - r->vb_start) * r->h_total_ns;
425	r->vs_end_ns = (r->vs_end - r->vb_start) * r->h_total_ns;
426	Assert(r->h_total_ns); /* See h_total. */
427	}
428
429	static uint8_t vga_retrace(PPDMDEVINS pDevIns, PVGASTATE pThis)
430	{
431	vga_retrace_s *r = &pThis->retrace_state;
432
433	if (r->frame_ns) {
434	uint8_t val = pThis->st01 & ~(ST01_V_RETRACE \| ST01_DISP_ENABLE);
435	unsigned cur_frame_ns, cur_line_ns;
436	uint64_t time_ns;
437
438	time_ns = PDMDevHlpTMTimeVirtGetNano(pDevIns);
439
440	/* Determine the time within the frame. */
441	cur_frame_ns = time_ns % r->frame_ns;
442
443	/* See if we're in the vertical blanking period... */
444	if (cur_frame_ns < r->vb_end_ns) {
445	val \|= ST01_DISP_ENABLE;
446	/* ... and additionally in the vertical sync period. */
447	if (cur_frame_ns >= r->vs_start_ns && cur_frame_ns <= r->vs_end_ns)
448	val \|= ST01_V_RETRACE;
449	} else {
450	/* Determine the time within the current scanline. */
451	cur_line_ns = cur_frame_ns % r->h_total_ns;
452	/* See if we're in the horizontal blanking period. */
453	if (cur_line_ns < r->hb_end_ns)
454	val \|= ST01_DISP_ENABLE;
455	}
456	return val;
457	} else {
458	return pThis->st01 ^ (ST01_V_RETRACE \| ST01_DISP_ENABLE);
459	}
460	}
461
462	int vga_ioport_invalid(PVGASTATE pThis, uint32_t addr)
463	{
464	if (pThis->msr & MSR_COLOR_EMULATION) {
465	/* Color */
466	return (addr >= 0x3b0 && addr <= 0x3bf);
467	} else {
468	/* Monochrome */
469	return (addr >= 0x3d0 && addr <= 0x3df);
470	}
471	}
472
473	static uint32_t vga_ioport_read(PPDMDEVINS pDevIns, PVGASTATE pThis, uint32_t addr)
474	{
475	int val, index;
476
477	/* check port range access depending on color/monochrome mode */
478	if (vga_ioport_invalid(pThis, addr)) {
479	val = 0xff;
480	Log(("VGA: following read ignored\n"));
481	} else {
482	switch(addr) {
483	case 0x3c0:
484	if (pThis->ar_flip_flop == 0) {
485	val = pThis->ar_index;
486	} else {
487	val = 0;
488	}
489	break;
490	case 0x3c1:
491	index = pThis->ar_index & 0x1f;
492	if (index < 21)
493	val = pThis->ar[index];
494	else
495	val = 0;
496	break;
497	case 0x3c2:
498	val = pThis->st00;
499	break;
500	case 0x3c4:
501	val = pThis->sr_index;
502	break;
503	case 0x3c5:
504	val = pThis->sr[pThis->sr_index];
505	Log2(("vga: read SR%x = 0x%02x\n", pThis->sr_index, val));
506	break;
507	case 0x3c7:
508	val = pThis->dac_state;
509	break;
510	case 0x3c8:
511	val = pThis->dac_write_index;
512	break;
513	case 0x3c9:
514	Assert(pThis->dac_sub_index < 3);
515	val = pThis->palette[pThis->dac_read_index * 3 + pThis->dac_sub_index];
516	if (++pThis->dac_sub_index == 3) {
517	pThis->dac_sub_index = 0;
518	pThis->dac_read_index++;
519	}
520	break;
521	case 0x3ca:
522	val = pThis->fcr;
523	break;
524	case 0x3cc:
525	val = pThis->msr;
526	break;
527	case 0x3ce:
528	val = pThis->gr_index;
529	break;
530	case 0x3cf:
531	val = pThis->gr[pThis->gr_index];
532	Log2(("vga: read GR%x = 0x%02x\n", pThis->gr_index, val));
533	break;
534	case 0x3b4:
535	case 0x3d4:
536	val = pThis->cr_index;
537	break;
538	case 0x3b5:
539	case 0x3d5:
540	val = pThis->cr[pThis->cr_index];
541	Log2(("vga: read CR%x = 0x%02x\n", pThis->cr_index, val));
542	break;
543	case 0x3ba:
544	case 0x3da:
545	val = pThis->st01 = vga_retrace(pDevIns, pThis);
546	pThis->ar_flip_flop = 0;
547	break;
548	default:
549	val = 0x00;
550	break;
551	}
552	}
553	Log(("VGA: read addr=0x%04x data=0x%02x\n", addr, val));
554	return val;
555	}
556
557	static void vga_ioport_write(PPDMDEVINS pDevIns, PVGASTATE pThis, uint32_t addr, uint32_t val)
558	{
559	int index;
560
561	Log(("VGA: write addr=0x%04x data=0x%02x\n", addr, val));
562
563	/* check port range access depending on color/monochrome mode */
564	if (vga_ioport_invalid(pThis, addr)) {
565	Log(("VGA: previous write ignored\n"));
566	return;
567	}
568
569	switch(addr) {
570	case 0x3c0:
571	case 0x3c1:
572	if (pThis->ar_flip_flop == 0) {
573	val &= 0x3f;
574	pThis->ar_index = val;
575	} else {
576	index = pThis->ar_index & 0x1f;
577	switch(index) {
578	case 0x00: case 0x01: case 0x02: case 0x03: case 0x04: case 0x05: case 0x06: case 0x07:
579	case 0x08: case 0x09: case 0x0a: case 0x0b: case 0x0c: case 0x0d: case 0x0e: case 0x0f:
580	pThis->ar[index] = val & 0x3f;
581	break;
582	case 0x10:
583	pThis->ar[index] = val & ~0x10;
584	break;
585	case 0x11:
586	pThis->ar[index] = val;
587	break;
588	case 0x12:
589	pThis->ar[index] = val & ~0xc0;
590	break;
591	case 0x13:
592	pThis->ar[index] = val & ~0xf0;
593	break;
594	case 0x14:
595	pThis->ar[index] = val & ~0xf0;
596	break;
597	default:
598	break;
599	}
600	}
601	pThis->ar_flip_flop ^= 1;
602	break;
603	case 0x3c2:
604	pThis->msr = val & ~0x10;
605	if (pThis->fRealRetrace)
606	vga_update_retrace_state(pThis);
607	/* The two clock select bits also determine which of the four switches
608	* is reflected in bit 4 of Input Status Register 0.
609	* This is EGA compatible behavior. See the IBM EGA Tech Ref.
610	*/
611	pThis->st00 = (pThis->st00 & ~0x10) \| ((EGA_SWITCHES >> ((val >> 2) & 0x3) & 0x10));
612	break;
613	case 0x3c4:
614	pThis->sr_index = val & 7;
615	break;
616	case 0x3c5:
617	Log2(("vga: write SR%x = 0x%02x\n", pThis->sr_index, val));
618	pThis->sr[pThis->sr_index] = val & sr_mask[pThis->sr_index];
619	/* Allow SR07 to disable VBE. */
620	if (pThis->sr_index == 0x07 && !(val & 1))
621	{
622	pThis->vbe_regs[VBE_DISPI_INDEX_ENABLE] = VBE_DISPI_DISABLED;
623	pThis->bank_offset = 0;
624	}
625	if (pThis->fRealRetrace && pThis->sr_index == 0x01)
626	vga_update_retrace_state(pThis);
627	#ifndef IN_RC
628	/* The VGA region is (could be) affected by this change; reset all aliases we've created. */
629	if ( pThis->sr_index == 4 /* mode */
630	\|\| pThis->sr_index == 2 /* plane mask */)
631	{
632	if (pThis->fRemappedVGA)
633	{
634	IOMMmioResetRegion(PDMDevHlpGetVM(pDevIns), pDevIns, pThis->hMmioLegacy);
635	pThis->fRemappedVGA = false;
636	}
637	}
638	#endif
639	break;
640	case 0x3c7:
641	pThis->dac_read_index = val;
642	pThis->dac_sub_index = 0;
643	pThis->dac_state = 3;
644	break;
645	case 0x3c8:
646	pThis->dac_write_index = val;
647	pThis->dac_sub_index = 0;
648	pThis->dac_state = 0;
649	break;
650	case 0x3c9:
651	Assert(pThis->dac_sub_index < 3);
652	pThis->dac_cache[pThis->dac_sub_index] = val;
653	if (++pThis->dac_sub_index == 3) {
654	memcpy(&pThis->palette[pThis->dac_write_index * 3], pThis->dac_cache, 3);
655	pThis->dac_sub_index = 0;
656	pThis->dac_write_index++;
657	}
658	break;
659	case 0x3ce:
660	pThis->gr_index = val & 0x0f;
661	break;
662	case 0x3cf:
663	Log2(("vga: write GR%x = 0x%02x\n", pThis->gr_index, val));
664	Assert(pThis->gr_index < RT_ELEMENTS(gr_mask));
665	pThis->gr[pThis->gr_index] = val & gr_mask[pThis->gr_index];
666
667	#ifndef IN_RC
668	/* The VGA region is (could be) affected by this change; reset all aliases we've created. */
669	if (pThis->gr_index == 6 /* memory map mode */)
670	{
671	if (pThis->fRemappedVGA)
672	{
673	IOMMmioResetRegion(PDMDevHlpGetVM(pDevIns), pDevIns, pThis->hMmioLegacy);
674	pThis->fRemappedVGA = false;
675	}
676	}
677	#endif
678	break;
679
680	case 0x3b4:
681	case 0x3d4:
682	pThis->cr_index = val;
683	break;
684	case 0x3b5:
685	case 0x3d5:
686	Log2(("vga: write CR%x = 0x%02x\n", pThis->cr_index, val));
687	/* handle CR0-7 protection */
688	if ((pThis->cr[0x11] & 0x80) && pThis->cr_index <= 7) {
689	/* can always write bit 4 of CR7 */
690	if (pThis->cr_index == 7)
691	pThis->cr[7] = (pThis->cr[7] & ~0x10) \| (val & 0x10);
692	return;
693	}
694	pThis->cr[pThis->cr_index] = val;
695
696	if (pThis->fRealRetrace) {
697	/* The following registers are only updated during a mode set. */
698	switch(pThis->cr_index) {
699	case 0x00:
700	case 0x02:
701	case 0x03:
702	case 0x05:
703	case 0x06:
704	case 0x07:
705	case 0x09:
706	case 0x10:
707	case 0x11:
708	case 0x15:
709	case 0x16:
710	vga_update_retrace_state(pThis);
711	break;
712	}
713	}
714	break;
715	case 0x3ba:
716	case 0x3da:
717	pThis->fcr = val & 0x10;
718	break;
719	}
720	}
721
722	#ifdef CONFIG_BOCHS_VBE
723
724	static uint32_t vbe_read_cfg(PVGASTATE pThis)
725	{
726	const uint16_t u16Cfg = pThis->vbe_regs[VBE_DISPI_INDEX_CFG];
727	const uint16_t u16Id = u16Cfg & VBE_DISPI_CFG_MASK_ID;
728	const bool fQuerySupport = RT_BOOL(u16Cfg & VBE_DISPI_CFG_MASK_SUPPORT);
729
730	uint32_t val = 0;
731	switch (u16Id)
732	{
733	case VBE_DISPI_CFG_ID_VERSION: val = 1; break;
734	case VBE_DISPI_CFG_ID_VRAM_SIZE: val = pThis->vram_size; break;
735	case VBE_DISPI_CFG_ID_3D: val = pThis->f3DEnabled; break;
736	# ifdef VBOX_WITH_VMSVGA
737	case VBE_DISPI_CFG_ID_VMSVGA: val = pThis->fVMSVGAEnabled; break;
738	# endif
739	default:
740	return 0; /* Not supported. */
741	}
742
743	return fQuerySupport ? 1 : val;
744	}
745
746	static uint32_t vbe_ioport_read_index(PVGASTATE pThis, uint32_t addr)
747	{
748	uint32_t val = pThis->vbe_index;
749	NOREF(addr);
750	return val;
751	}
752
753	static uint32_t vbe_ioport_read_data(PVGASTATE pThis, uint32_t addr)
754	{
755	uint32_t val;
756	NOREF(addr);
757
758	uint16_t const idxVbe = pThis->vbe_index;
759	if (idxVbe < VBE_DISPI_INDEX_NB)
760	{
761	RT_UNTRUSTED_VALIDATED_FENCE();
762	if (pThis->vbe_regs[VBE_DISPI_INDEX_ENABLE] & VBE_DISPI_GETCAPS)
763	{
764	switch (idxVbe)
765	{
766	/* XXX: do not hardcode ? */
767	case VBE_DISPI_INDEX_XRES:
768	val = VBE_DISPI_MAX_XRES;
769	break;
770	case VBE_DISPI_INDEX_YRES:
771	val = VBE_DISPI_MAX_YRES;
772	break;
773	case VBE_DISPI_INDEX_BPP:
774	val = VBE_DISPI_MAX_BPP;
775	break;
776	default:
777	Assert(idxVbe < VBE_DISPI_INDEX_NB);
778	val = pThis->vbe_regs[idxVbe];
779	break;
780	}
781	}
782	else
783	{
784	switch (idxVbe)
785	{
786	case VBE_DISPI_INDEX_VBOX_VIDEO:
787	/* Reading from the port means that the old additions are requesting the number of monitors. */
788	val = 1;
789	break;
790	case VBE_DISPI_INDEX_CFG:
791	val = vbe_read_cfg(pThis);
792	break;
793	default:
794	Assert(idxVbe < VBE_DISPI_INDEX_NB);
795	val = pThis->vbe_regs[idxVbe];
796	break;
797	}
798	}
799	}
800	else
801	val = 0;
802	Log(("VBE: read index=0x%x val=0x%x\n", idxVbe, val));
803	return val;
804	}
805
806	# define VBE_PITCH_ALIGN 4 /* Align pitch to 32 bits - Qt requires that. */
807
808	/* Calculate scanline pitch based on bit depth and width in pixels. */
809	static uint32_t calc_line_pitch(uint16_t bpp, uint16_t width)
810	{
811	uint32_t pitch, aligned_pitch;
812
813	if (bpp <= 4)
814	pitch = width >> 1;
815	else
816	pitch = width * ((bpp + 7) >> 3);
817
818	/* Align the pitch to some sensible value. */
819	aligned_pitch = (pitch + (VBE_PITCH_ALIGN - 1)) & ~(VBE_PITCH_ALIGN - 1);
820	if (aligned_pitch != pitch)
821	Log(("VBE: Line pitch %d aligned to %d bytes\n", pitch, aligned_pitch));
822
823	return aligned_pitch;
824	}
825
826	static void recalculate_data(PVGASTATE pThis)
827	{
828	uint16_t cBPP = pThis->vbe_regs[VBE_DISPI_INDEX_BPP];
829	uint16_t cVirtWidth = pThis->vbe_regs[VBE_DISPI_INDEX_VIRT_WIDTH];
830	uint16_t cX = pThis->vbe_regs[VBE_DISPI_INDEX_XRES];
831	if (!cBPP \|\| !cX)
832	return; /* Not enough data has been set yet. */
833	uint32_t cbLinePitch = calc_line_pitch(cBPP, cVirtWidth);
834	if (!cbLinePitch)
835	cbLinePitch = calc_line_pitch(cBPP, cX);
836	if (!cbLinePitch)
837	return;
838	uint32_t cVirtHeight = pThis->vram_size / cbLinePitch;
839	uint16_t offX = pThis->vbe_regs[VBE_DISPI_INDEX_X_OFFSET];
840	uint16_t offY = pThis->vbe_regs[VBE_DISPI_INDEX_Y_OFFSET];
841	uint32_t offStart = cbLinePitch * offY;
842	if (cBPP == 4)
843	offStart += offX >> 1;
844	else
845	offStart += offX * ((cBPP + 7) >> 3);
846	offStart >>= 2;
847	pThis->vbe_line_offset = RT_MIN(cbLinePitch, pThis->vram_size);
848	pThis->vbe_start_addr = RT_MIN(offStart, pThis->vram_size);
849
850	/* The VBE_DISPI_INDEX_VIRT_HEIGHT is used to prevent setting resolution bigger than
851	* the VRAM size permits. It is used instead of VBE_DISPI_INDEX_YRES only in case
852	* pThis->vbe_regs[VBE_DISPI_INDEX_VIRT_HEIGHT] < pThis->vbe_regs[VBE_DISPI_INDEX_YRES].
853	* Note that VBE_DISPI_INDEX_VIRT_HEIGHT has to be clipped to UINT16_MAX, which happens
854	* with small resolutions and big VRAM. */
855	pThis->vbe_regs[VBE_DISPI_INDEX_VIRT_HEIGHT] = cVirtHeight >= UINT16_MAX ? UINT16_MAX : (uint16_t)cVirtHeight;
856	}
857
858	static void vbe_ioport_write_index(PVGASTATE pThis, uint32_t addr, uint32_t val)
859	{
860	pThis->vbe_index = val;
861	NOREF(addr);
862	}
863
864	static VBOXSTRICTRC vbe_ioport_write_data(PPDMDEVINS pDevIns, PVGASTATE pThis, PVGASTATECC pThisCC, uint32_t addr, uint32_t val)
865	{
866	uint32_t max_bank;
867	RT_NOREF(pThisCC, addr);
868
869	if (pThis->vbe_index <= VBE_DISPI_INDEX_NB) {
870	bool fRecalculate = false;
871	Log(("VBE: write index=0x%x val=0x%x\n", pThis->vbe_index, val));
872	switch(pThis->vbe_index) {
873	case VBE_DISPI_INDEX_ID:
874	if (val == VBE_DISPI_ID0 \|\|
875	val == VBE_DISPI_ID1 \|\|
876	val == VBE_DISPI_ID2 \|\|
877	val == VBE_DISPI_ID3 \|\|
878	val == VBE_DISPI_ID4 \|\|
879	/* VBox extensions. */
880	val == VBE_DISPI_ID_VBOX_VIDEO \|\|
881	val == VBE_DISPI_ID_ANYX \|\|
882	# ifdef VBOX_WITH_HGSMI
883	val == VBE_DISPI_ID_HGSMI \|\|
884	# endif
885	val == VBE_DISPI_ID_CFG)
886	{
887	pThis->vbe_regs[pThis->vbe_index] = val;
888	}
889	break;
890	case VBE_DISPI_INDEX_XRES:
891	if (val <= VBE_DISPI_MAX_XRES)
892	{
893	pThis->vbe_regs[pThis->vbe_index] = val;
894	pThis->vbe_regs[VBE_DISPI_INDEX_VIRT_WIDTH] = val;
895	fRecalculate = true;
896	}
897	break;
898	case VBE_DISPI_INDEX_YRES:
899	if (val <= VBE_DISPI_MAX_YRES)
900	pThis->vbe_regs[pThis->vbe_index] = val;
901	break;
902	case VBE_DISPI_INDEX_BPP:
903	if (val == 0)
904	val = 8;
905	if (val == 4 \|\| val == 8 \|\| val == 15 \|\|
906	val == 16 \|\| val == 24 \|\| val == 32) {
907	pThis->vbe_regs[pThis->vbe_index] = val;
908	fRecalculate = true;
909	}
910	break;
911	case VBE_DISPI_INDEX_BANK:
912	if (pThis->vbe_regs[VBE_DISPI_INDEX_BPP] <= 4)
913	max_bank = pThis->vbe_bank_max >> 2; /* Each bank really covers 256K */
914	else
915	max_bank = pThis->vbe_bank_max;
916	/* Old software may pass garbage in the high byte of bank. If the maximum
917	* bank fits into a single byte, toss the high byte the user supplied.
918	*/
919	if (max_bank < 0x100)
920	val &= 0xff;
921	if (val > max_bank)
922	val = max_bank;
923	pThis->vbe_regs[pThis->vbe_index] = val;
924	pThis->bank_offset = (val << 16);
925
926	# ifndef IN_RC
927	/* The VGA region is (could be) affected by this change; reset all aliases we've created. */
928	if (pThis->fRemappedVGA)
929	{
930	IOMMmioResetRegion(PDMDevHlpGetVM(pDevIns), pDevIns, pThis->hMmioLegacy);
931	pThis->fRemappedVGA = false;
932	}
933	# endif
934	break;
935
936	case VBE_DISPI_INDEX_ENABLE:
937	# ifndef IN_RING3
938	return VINF_IOM_R3_IOPORT_WRITE;
939	# else
940	{
941	if ((val & VBE_DISPI_ENABLED) &&
942	!(pThis->vbe_regs[VBE_DISPI_INDEX_ENABLE] & VBE_DISPI_ENABLED)) {
943	int h, shift_control;
944	/* Check the values before we screw up with a resolution which is too big or small. */
945	size_t cb = pThis->vbe_regs[VBE_DISPI_INDEX_XRES];
946	if (pThis->vbe_regs[VBE_DISPI_INDEX_BPP] == 4)
947	cb = pThis->vbe_regs[VBE_DISPI_INDEX_XRES] >> 1;
948	else
949	cb = pThis->vbe_regs[VBE_DISPI_INDEX_XRES] * ((pThis->vbe_regs[VBE_DISPI_INDEX_BPP] + 7) >> 3);
950	cb *= pThis->vbe_regs[VBE_DISPI_INDEX_YRES];
951	uint16_t cVirtWidth = pThis->vbe_regs[VBE_DISPI_INDEX_VIRT_WIDTH];
952	if (!cVirtWidth)
953	cVirtWidth = pThis->vbe_regs[VBE_DISPI_INDEX_XRES];
954	if ( !cVirtWidth
955	\|\| !pThis->vbe_regs[VBE_DISPI_INDEX_YRES]
956	\|\| cb > pThis->vram_size)
957	{
958	AssertMsgFailed(("VIRT WIDTH=%d YRES=%d cb=%d vram_size=%d\n",
959	pThis->vbe_regs[VBE_DISPI_INDEX_VIRT_WIDTH], pThis->vbe_regs[VBE_DISPI_INDEX_YRES], cb, pThis->vram_size));
960	return VINF_SUCCESS; /* Note: silent failure like before */
961	}
962
963	/* When VBE interface is enabled, it is reset. */
964	pThis->vbe_regs[VBE_DISPI_INDEX_X_OFFSET] = 0;
965	pThis->vbe_regs[VBE_DISPI_INDEX_Y_OFFSET] = 0;
966	fRecalculate = true;
967
968	/* clear the screen (should be done in BIOS) */
969	if (!(val & VBE_DISPI_NOCLEARMEM)) {
970	uint16_t cY = RT_MIN(pThis->vbe_regs[VBE_DISPI_INDEX_YRES],
971	pThis->vbe_regs[VBE_DISPI_INDEX_VIRT_HEIGHT]);
972	uint16_t cbLinePitch = pThis->vbe_line_offset;
973	memset(pThisCC->pbVRam, 0,
974	cY * cbLinePitch);
975	}
976
977	/* we initialize the VGA graphic mode (should be done
978	in BIOS) */
979	pThis->gr[0x06] = (pThis->gr[0x06] & ~0x0c) \| 0x05; /* graphic mode + memory map 1 */
980	pThis->cr[0x17] \|= 3; /* no CGA modes */
981	pThis->cr[0x13] = pThis->vbe_line_offset >> 3;
982	/* width */
983	pThis->cr[0x01] = (cVirtWidth >> 3) - 1;
984	/* height (only meaningful if < 1024) */
985	h = pThis->vbe_regs[VBE_DISPI_INDEX_YRES] - 1;
986	pThis->cr[0x12] = h;
987	pThis->cr[0x07] = (pThis->cr[0x07] & ~0x42) \|
988	((h >> 7) & 0x02) \| ((h >> 3) & 0x40);
989	/* line compare to 1023 */
990	pThis->cr[0x18] = 0xff;
991	pThis->cr[0x07] \|= 0x10;
992	pThis->cr[0x09] \|= 0x40;
993
994	if (pThis->vbe_regs[VBE_DISPI_INDEX_BPP] == 4) {
995	shift_control = 0;
996	pThis->sr[0x01] &= ~8; /* no double line */
997	} else {
998	shift_control = 2;
999	pThis->sr[4] \|= 0x08; /* set chain 4 mode */
1000	pThis->sr[2] \|= 0x0f; /* activate all planes */
1001	/* Indicate non-VGA mode in SR07. */
1002	pThis->sr[7] \|= 1;
1003	}
1004	pThis->gr[0x05] = (pThis->gr[0x05] & ~0x60) \| (shift_control << 5);
1005	pThis->cr[0x09] &= ~0x9f; /* no double scan */
1006	/* sunlover 30.05.2007
1007	* The ar_index remains with bit 0x20 cleared after a switch from fullscreen
1008	* DOS mode on Windows XP guest. That leads to GMODE_BLANK in vgaR3UpdateDisplay.
1009	* But the VBE mode is graphics, so not a blank anymore.
1010	*/
1011	pThis->ar_index \|= 0x20;
1012	} else {
1013	/* XXX: the bios should do that */
1014	/* sunlover 21.12.2006
1015	* Here is probably more to reset. When this was executed in GC
1016	* then the update functions could not detect a mode change.
1017	* Or may be these update function should take the pThis->vbe_regs[pThis->vbe_index]
1018	* into account when detecting a mode change.
1019	*
1020	* The 'mode reset not detected' problem is now fixed by executing the
1021	* VBE_DISPI_INDEX_ENABLE case always in RING3 in order to call the
1022	* LFBChange callback.
1023	*/
1024	pThis->bank_offset = 0;
1025	}
1026	pThis->vbe_regs[pThis->vbe_index] = val;
1027	/*
1028	* LFB video mode is either disabled or changed. Notify the display
1029	* and reset VBVA.
1030	*/
1031	pThisCC->pDrv->pfnLFBModeChange(pThisCC->pDrv, (val & VBE_DISPI_ENABLED) != 0);
1032	# ifdef VBOX_WITH_HGSMI
1033	VBVAOnVBEChanged(pThis, pThisCC);
1034	# endif
1035
1036	/* The VGA region is (could be) affected by this change; reset all aliases we've created. */
1037	if (pThis->fRemappedVGA)
1038	{
1039	IOMMmioResetRegion(PDMDevHlpGetVM(pDevIns), pDevIns, pThis->hMmioLegacy);
1040	pThis->fRemappedVGA = false;
1041	}
1042	break;
1043	}
1044	# endif /* IN_RING3 */
1045	case VBE_DISPI_INDEX_VIRT_WIDTH:
1046	case VBE_DISPI_INDEX_X_OFFSET:
1047	case VBE_DISPI_INDEX_Y_OFFSET:
1048	{
1049	pThis->vbe_regs[pThis->vbe_index] = val;
1050	fRecalculate = true;
1051	}
1052	break;
1053	case VBE_DISPI_INDEX_VBOX_VIDEO:
1054	# ifndef IN_RING3
1055	return VINF_IOM_R3_IOPORT_WRITE;
1056	# else
1057	/* Changes in the VGA device are minimal. The device is bypassed. The driver does all work. */
1058	if (val == VBOX_VIDEO_DISABLE_ADAPTER_MEMORY)
1059	pThisCC->pDrv->pfnProcessAdapterData(pThisCC->pDrv, NULL, 0);
1060	else if (val == VBOX_VIDEO_INTERPRET_ADAPTER_MEMORY)
1061	pThisCC->pDrv->pfnProcessAdapterData(pThisCC->pDrv, pThisCC->pbVRam, pThis->vram_size);
1062	else if ((val & 0xFFFF0000) == VBOX_VIDEO_INTERPRET_DISPLAY_MEMORY_BASE)
1063	pThisCC->pDrv->pfnProcessDisplayData(pThisCC->pDrv, pThisCC->pbVRam, val & 0xFFFF);
1064	# endif /* IN_RING3 */
1065	break;
1066	case VBE_DISPI_INDEX_CFG:
1067	pThis->vbe_regs[pThis->vbe_index] = val;
1068	break;
1069	default:
1070	break;
1071	}
1072
1073	if (fRecalculate)
1074	recalculate_data(pThis);
1075	}
1076	return VINF_SUCCESS;
1077	}
1078
1079	#endif /* CONFIG_BOCHS_VBE */
1080
1081	/* called for accesses between 0xa0000 and 0xc0000 */
1082	static uint32_t vga_mem_readb(PPDMDEVINS pDevIns, PVGASTATE pThis, PVGASTATECC pThisCC, RTGCPHYS addr, int *prc)
1083	{
1084	int plane;
1085	uint32_t ret;
1086
1087	Log3(("vga: read [0x%x] -> ", addr));
1088
1089	#ifdef VMSVGA_WITH_VGA_FB_BACKUP_AND_IN_RZ
1090	/* VMSVGA keeps the VGA and SVGA framebuffers separate unlike this boch-based
1091	VGA implementation, so we fake it by going to ring-3 and using a heap buffer. */
1092	if (!pThis->svga.fEnabled)
1093	{ /likely/ }
1094	else
1095	{
1096	*prc = VINF_IOM_R3_MMIO_READ;
1097	return 0;
1098	}
1099	#endif
1100
1101
1102	/* convert to VGA memory offset */
1103	#ifndef IN_RC
1104	RTGCPHYS GCPhys = addr; /* save original address */
1105	#endif
1106	addr &= 0x1ffff;
1107
1108	int const memory_map_mode = (pThis->gr[6] >> 2) & 3;
1109	switch(memory_map_mode) {
1110	case 0:
1111	break;
1112	case 1:
1113	if (addr >= 0x10000)
1114	return 0xff;
1115	addr += pThis->bank_offset;
1116	break;
1117	case 2:
1118	addr -= 0x10000;
1119	if (addr >= 0x8000)
1120	return 0xff;
1121	break;
1122	default:
1123	case 3:
1124	addr -= 0x18000;
1125	if (addr >= 0x8000)
1126	return 0xff;
1127	break;
1128	}
1129
1130	if (pThis->sr[4] & 0x08) {
1131	/* chain 4 mode : simplest access */
1132	#ifndef IN_RC
1133	/* If all planes are accessible, then map the page to the frame buffer and make it writable. */
1134	if ( (pThis->sr[2] & 3) == 3
1135	&& !vgaIsDirty(pThis, addr)
1136	&& pThis->GCPhysVRAM)
1137	{
1138	/** @todo only allow read access (doesn't work now) */
1139	STAM_COUNTER_INC(&pThis->StatMapPage);
1140	IOMMmioMapMmio2Page(PDMDevHlpGetVM(pDevIns), pDevIns, pThis->hMmioLegacy, GCPhys - 0xa0000,
1141	pThis->hMmio2VRam, addr, X86_PTE_RW \| X86_PTE_P);
1142	/* Set as dirty as write accesses won't be noticed now. */
1143	vgaR3MarkDirty(pThis, addr);
1144	pThis->fRemappedVGA = true;
1145	}
1146	#endif /* !IN_RC */
1147	VERIFY_VRAM_READ_OFF_RETURN(pThis, addr, *prc);
1148	#ifdef VMSVGA_WITH_VGA_FB_BACKUP_AND_IN_RING3
1149	ret = !pThis->svga.fEnabled ? pThisCC->pbVRam[addr]
1150	: addr < VMSVGA_VGA_FB_BACKUP_SIZE ? pThisCC->svga.pbVgaFrameBufferR3[addr] : 0xff;
1151	#else
1152	ret = pThisCC->pbVRam[addr];
1153	#endif
1154	} else if (!(pThis->sr[4] & 0x04)) { /* Host access is controlled by SR4, not GR5! */
1155	/* odd/even mode (aka text mode mapping) */
1156	plane = (pThis->gr[4] & 2) \| (addr & 1);
1157	/* See the comment for a similar line in vga_mem_writeb. */
1158	RTGCPHYS off = ((addr & ~1) * 4) \| plane;
1159	VERIFY_VRAM_READ_OFF_RETURN(pThis, off, *prc);
1160	#ifdef VMSVGA_WITH_VGA_FB_BACKUP_AND_IN_RING3
1161	ret = !pThis->svga.fEnabled ? pThisCC->pbVRam[off]
1162	: off < VMSVGA_VGA_FB_BACKUP_SIZE ? pThisCC->svga.pbVgaFrameBufferR3[off] : 0xff;
1163	#else
1164	ret = pThisCC->pbVRam[off];
1165	#endif
1166	} else {
1167	/* standard VGA latched access */
1168	VERIFY_VRAM_READ_OFF_RETURN(pThis, addr * 4 + 3, *prc);
1169	#ifdef VMSVGA_WITH_VGA_FB_BACKUP_AND_IN_RING3
1170	pThis->latch = !pThis->svga.fEnabled ? ((uint32_t *)pThisCC->pbVRam)[addr]
1171	: addr < VMSVGA_VGA_FB_BACKUP_SIZE ? ((uint32_t *)pThisCC->svga.pbVgaFrameBufferR3)[addr] : UINT32_MAX;
1172	#else
1173	pThis->latch = ((uint32_t *)pThisCC->pbVRam)[addr];
1174	#endif
1175	if (!(pThis->gr[5] & 0x08)) {
1176	/* read mode 0 */
1177	plane = pThis->gr[4];
1178	ret = GET_PLANE(pThis->latch, plane);
1179	} else {
1180	/* read mode 1 */
1181	ret = (pThis->latch ^ mask16[pThis->gr[2]]) & mask16[pThis->gr[7]];
1182	ret \|= ret >> 16;
1183	ret \|= ret >> 8;
1184	ret = (~ret) & 0xff;
1185	}
1186	}
1187	Log3((" 0x%02x\n", ret));
1188	return ret;
1189	}
1190
1191	/**
1192	* called for accesses between 0xa0000 and 0xc0000
1193	*/
1194	static VBOXSTRICTRC vga_mem_writeb(PPDMDEVINS pDevIns, PVGASTATE pThis, PVGASTATECC pThisCC, RTGCPHYS addr, uint32_t val)
1195	{
1196	int plane, write_mode, b, func_select, mask;
1197	uint32_t write_mask, bit_mask, set_mask;
1198
1199	Log3(("vga: [0x%x] = 0x%02x\n", addr, val));
1200
1201	#ifdef VMSVGA_WITH_VGA_FB_BACKUP_AND_IN_RZ
1202	/* VMSVGA keeps the VGA and SVGA framebuffers separate unlike this boch-based
1203	VGA implementation, so we fake it by going to ring-3 and using a heap buffer. */
1204	if (!pThis->svga.fEnabled) { /likely/ }
1205	else return VINF_IOM_R3_MMIO_WRITE;
1206	#endif
1207
1208	/* convert to VGA memory offset */
1209	#ifndef IN_RC
1210	RTGCPHYS const GCPhys = addr; /* save original address */
1211	#endif
1212	addr &= 0x1ffff;
1213
1214	int const memory_map_mode = (pThis->gr[6] >> 2) & 3;
1215	switch(memory_map_mode) {
1216	case 0:
1217	break;
1218	case 1:
1219	if (addr >= 0x10000)
1220	return VINF_SUCCESS;
1221	addr += pThis->bank_offset;
1222	break;
1223	case 2:
1224	addr -= 0x10000;
1225	if (addr >= 0x8000)
1226	return VINF_SUCCESS;
1227	break;
1228	default:
1229	case 3:
1230	addr -= 0x18000;
1231	if (addr >= 0x8000)
1232	return VINF_SUCCESS;
1233	break;
1234	}
1235
1236	if (pThis->sr[4] & 0x08) {
1237	/* chain 4 mode : simplest access */
1238	plane = addr & 3;
1239	mask = (1 << plane);
1240	if (pThis->sr[2] & mask) {
1241	#ifndef IN_RC
1242	/* If all planes are accessible, then map the page to the frame buffer and make it writable. */
1243	if ( (pThis->sr[2] & 3) == 3
1244	&& !vgaIsDirty(pThis, addr)
1245	&& pThis->GCPhysVRAM)
1246	{
1247	STAM_COUNTER_INC(&pThis->StatMapPage);
1248	IOMMmioMapMmio2Page(PDMDevHlpGetVM(pDevIns), pDevIns, pThis->hMmioLegacy, GCPhys - 0xa0000,
1249	pThis->hMmio2VRam, addr, X86_PTE_RW \| X86_PTE_P);
1250	pThis->fRemappedVGA = true;
1251	}
1252	#endif /* !IN_RC */
1253
1254	VERIFY_VRAM_WRITE_OFF_RETURN(pThis, addr);
1255	#ifdef VMSVGA_WITH_VGA_FB_BACKUP_AND_IN_RING3
1256	if (!pThis->svga.fEnabled)
1257	pThisCC->pbVRam[addr] = val;
1258	else if (addr < VMSVGA_VGA_FB_BACKUP_SIZE)
1259	pThisCC->svga.pbVgaFrameBufferR3[addr] = val;
1260	else
1261	{
1262	Log(("vga: chain4: out of vmsvga VGA framebuffer bounds! addr=%#x\n", addr));
1263	return VINF_SUCCESS;
1264	}
1265	#else
1266	pThisCC->pbVRam[addr] = val;
1267	#endif
1268	Log3(("vga: chain4: [0x%x]\n", addr));
1269	pThis->plane_updated \|= mask; /* only used to detect font change */
1270	vgaR3MarkDirty(pThis, addr);
1271	}
1272	} else if (!(pThis->sr[4] & 0x04)) { /* Host access is controlled by SR4, not GR5! */
1273	/* odd/even mode (aka text mode mapping) */
1274	plane = (pThis->gr[4] & 2) \| (addr & 1);
1275	mask = (1 << plane);
1276	if (pThis->sr[2] & mask) {
1277	/* 'addr' is offset in a plane, bit 0 selects the plane.
1278	* Mask the bit 0, convert plane index to vram offset,
1279	* that is multiply by the number of planes,
1280	* and select the plane byte in the vram offset.
1281	*/
1282	addr = ((addr & ~1) * 4) \| plane;
1283	VERIFY_VRAM_WRITE_OFF_RETURN(pThis, addr);
1284	#ifdef VMSVGA_WITH_VGA_FB_BACKUP_AND_IN_RING3
1285	if (!pThis->svga.fEnabled)
1286	pThisCC->pbVRam[addr] = val;
1287	else if (addr < VMSVGA_VGA_FB_BACKUP_SIZE)
1288	pThisCC->svga.pbVgaFrameBufferR3[addr] = val;
1289	else
1290	{
1291	Log(("vga: odd/even: out of vmsvga VGA framebuffer bounds! addr=%#x\n", addr));
1292	return VINF_SUCCESS;
1293	}
1294	#else
1295	pThisCC->pbVRam[addr] = val;
1296	#endif
1297	Log3(("vga: odd/even: [0x%x]\n", addr));
1298	pThis->plane_updated \|= mask; /* only used to detect font change */
1299	vgaR3MarkDirty(pThis, addr);
1300	}
1301	} else {
1302	/* standard VGA latched access */
1303	VERIFY_VRAM_WRITE_OFF_RETURN(pThis, addr * 4 + 3);
1304
1305	write_mode = pThis->gr[5] & 3;
1306	switch(write_mode) {
1307	default:
1308	case 0:
1309	/* rotate */
1310	b = pThis->gr[3] & 7;
1311	val = ((val >> b) \| (val << (8 - b))) & 0xff;
1312	val \|= val << 8;
1313	val \|= val << 16;
1314
1315	/* apply set/reset mask */
1316	set_mask = mask16[pThis->gr[1]];
1317	val = (val & ~set_mask) \| (mask16[pThis->gr[0]] & set_mask);
1318	bit_mask = pThis->gr[8];
1319	break;
1320	case 1:
1321	val = pThis->latch;
1322	goto do_write;
1323	case 2:
1324	val = mask16[val & 0x0f];
1325	bit_mask = pThis->gr[8];
1326	break;
1327	case 3:
1328	/* rotate */
1329	b = pThis->gr[3] & 7;
1330	val = (val >> b) \| (val << (8 - b));
1331
1332	bit_mask = pThis->gr[8] & val;
1333	val = mask16[pThis->gr[0]];
1334	break;
1335	}
1336
1337	/* apply logical operation */
1338	func_select = pThis->gr[3] >> 3;
1339	switch(func_select) {
1340	case 0:
1341	default:
1342	/* nothing to do */
1343	break;
1344	case 1:
1345	/* and */
1346	val &= pThis->latch;
1347	break;
1348	case 2:
1349	/* or */
1350	val \|= pThis->latch;
1351	break;
1352	case 3:
1353	/* xor */
1354	val ^= pThis->latch;
1355	break;
1356	}
1357
1358	/* apply bit mask */
1359	bit_mask \|= bit_mask << 8;
1360	bit_mask \|= bit_mask << 16;
1361	val = (val & bit_mask) \| (pThis->latch & ~bit_mask);
1362
1363	do_write:
1364	/* mask data according to sr[2] */
1365	mask = pThis->sr[2];
1366	pThis->plane_updated \|= mask; /* only used to detect font change */
1367	write_mask = mask16[mask];
1368	#ifdef VMSVGA_WITH_VGA_FB_BACKUP_AND_IN_RING3
1369	uint32_t *pu32Dst;
1370	if (!pThis->svga.fEnabled)
1371	pu32Dst = &((uint32_t *)pThisCC->pbVRam)[addr];
1372	else if (addr * 4 + 3 < VMSVGA_VGA_FB_BACKUP_SIZE)
1373	pu32Dst = &((uint32_t *)pThisCC->svga.pbVgaFrameBufferR3)[addr];
1374	else
1375	{
1376	Log(("vga: latch: out of vmsvga VGA framebuffer bounds! addr=%#x\n", addr));
1377	return VINF_SUCCESS;
1378	}
1379	pu32Dst = (pu32Dst & ~write_mask) \| (val & write_mask);
1380	#else
1381	((uint32_t )pThisCC->pbVRam)[addr] = (((uint32_t )pThisCC->pbVRam)[addr] & ~write_mask)
1382	\| (val & write_mask);
1383	#endif
1384	Log3(("vga: latch: [0x%x] mask=0x%08x val=0x%08x\n", addr * 4, write_mask, val));
1385	vgaR3MarkDirty(pThis, (addr * 4));
1386	}
1387
1388	return VINF_SUCCESS;
1389	}
1390
1391	#ifdef IN_RING3
1392
1393	typedef void vga_draw_glyph8_func(uint8_t *d, int linesize,
1394	const uint8_t *font_ptr, int h,
1395	uint32_t fgcol, uint32_t bgcol,
1396	int dscan);
1397	typedef void vga_draw_glyph9_func(uint8_t *d, int linesize,
1398	const uint8_t *font_ptr, int h,
1399	uint32_t fgcol, uint32_t bgcol, int dup9);
1400	typedef void vga_draw_line_func(PVGASTATE pThis, PVGASTATECC pThisCC, uint8_t pbDst, const uint8_t pbSrc, int width);
1401
1402	static inline unsigned int rgb_to_pixel8(unsigned int r, unsigned int g, unsigned b)
1403	{
1404	return ((r >> 5) << 5) \| ((g >> 5) << 2) \| (b >> 6);
1405	}
1406
1407	static inline unsigned int rgb_to_pixel15(unsigned int r, unsigned int g, unsigned b)
1408	{
1409	return ((r >> 3) << 10) \| ((g >> 3) << 5) \| (b >> 3);
1410	}
1411
1412	static inline unsigned int rgb_to_pixel16(unsigned int r, unsigned int g, unsigned b)
1413	{
1414	return ((r >> 3) << 11) \| ((g >> 2) << 5) \| (b >> 3);
1415	}
1416
1417	static inline unsigned int rgb_to_pixel32(unsigned int r, unsigned int g, unsigned b)
1418	{
1419	return (r << 16) \| (g << 8) \| b;
1420	}
1421
1422	#define DEPTH 8
1423	#include "DevVGATmpl.h"
1424
1425	#define DEPTH 15
1426	#include "DevVGATmpl.h"
1427
1428	#define DEPTH 16
1429	#include "DevVGATmpl.h"
1430
1431	#define DEPTH 32
1432	#include "DevVGATmpl.h"
1433
1434	static unsigned int rgb_to_pixel8_dup(unsigned int r, unsigned int g, unsigned b)
1435	{
1436	unsigned int col;
1437	col = rgb_to_pixel8(r, g, b);
1438	col \|= col << 8;
1439	col \|= col << 16;
1440	return col;
1441	}
1442
1443	static unsigned int rgb_to_pixel15_dup(unsigned int r, unsigned int g, unsigned b)
1444	{
1445	unsigned int col;
1446	col = rgb_to_pixel15(r, g, b);
1447	col \|= col << 16;
1448	return col;
1449	}
1450
1451	static unsigned int rgb_to_pixel16_dup(unsigned int r, unsigned int g, unsigned b)
1452	{
1453	unsigned int col;
1454	col = rgb_to_pixel16(r, g, b);
1455	col \|= col << 16;
1456	return col;
1457	}
1458
1459	static unsigned int rgb_to_pixel32_dup(unsigned int r, unsigned int g, unsigned b)
1460	{
1461	return rgb_to_pixel32(r, g, b);
1462	}
1463
1464	/** return true if the palette was modified */
1465	static bool vgaR3UpdatePalette16(PVGASTATE pThis, PVGASTATER3 pThisCC)
1466	{
1467	bool full_update = false;
1468	int i;
1469	uint32_t v, col, *palette;
1470
1471	palette = pThis->last_palette;
1472	for(i = 0; i < 16; i++) {
1473	v = pThis->ar[i];
1474	if (pThis->ar[0x10] & 0x80)
1475	v = ((pThis->ar[0x14] & 0xf) << 4) \| (v & 0xf);
1476	else
1477	v = ((pThis->ar[0x14] & 0xc) << 4) \| (v & 0x3f);
1478	v = v * 3;
1479	col = pThisCC->rgb_to_pixel(c6_to_8(pThis->palette[v]),
1480	c6_to_8(pThis->palette[v + 1]),
1481	c6_to_8(pThis->palette[v + 2]));
1482	if (col != palette[i]) {
1483	full_update = true;
1484	palette[i] = col;
1485	}
1486	}
1487	return full_update;
1488	}
1489
1490	/** return true if the palette was modified */
1491	static bool vgaR3UpdatePalette256(PVGASTATE pThis, PVGASTATER3 pThisCC)
1492	{
1493	bool full_update = false;
1494	int i;
1495	uint32_t v, col, *palette;
1496	int wide_dac;
1497
1498	palette = pThis->last_palette;
1499	v = 0;
1500	wide_dac = (pThis->vbe_regs[VBE_DISPI_INDEX_ENABLE] & (VBE_DISPI_ENABLED \| VBE_DISPI_8BIT_DAC))
1501	== (VBE_DISPI_ENABLED \| VBE_DISPI_8BIT_DAC);
1502	for(i = 0; i < 256; i++) {
1503	if (wide_dac)
1504	col = pThisCC->rgb_to_pixel(pThis->palette[v],
1505	pThis->palette[v + 1],
1506	pThis->palette[v + 2]);
1507	else
1508	col = pThisCC->rgb_to_pixel(c6_to_8(pThis->palette[v]),
1509	c6_to_8(pThis->palette[v + 1]),
1510	c6_to_8(pThis->palette[v + 2]));
1511	if (col != palette[i]) {
1512	full_update = true;
1513	palette[i] = col;
1514	}
1515	v += 3;
1516	}
1517	return full_update;
1518	}
1519
1520	static void vgaR3GetOffsets(PVGASTATE pThis,
1521	uint32_t *pline_offset,
1522	uint32_t *pstart_addr,
1523	uint32_t *pline_compare)
1524	{
1525	uint32_t start_addr, line_offset, line_compare;
1526	#ifdef CONFIG_BOCHS_VBE
1527	if (pThis->vbe_regs[VBE_DISPI_INDEX_ENABLE] & VBE_DISPI_ENABLED) {
1528	line_offset = pThis->vbe_line_offset;
1529	start_addr = pThis->vbe_start_addr;
1530	line_compare = 65535;
1531	} else
1532	#endif
1533	{
1534	/* compute line_offset in bytes */
1535	line_offset = pThis->cr[0x13];
1536	line_offset <<= 3;
1537	if (!(pThis->cr[0x14] & 0x40) && !(pThis->cr[0x17] & 0x40))
1538	{
1539	/* Word mode. Used for odd/even modes. */
1540	line_offset *= 2;
1541	}
1542
1543	/* starting address */
1544	start_addr = pThis->cr[0x0d] \| (pThis->cr[0x0c] << 8);
1545
1546	/* line compare */
1547	line_compare = pThis->cr[0x18] \|
1548	((pThis->cr[0x07] & 0x10) << 4) \|
1549	((pThis->cr[0x09] & 0x40) << 3);
1550	}
1551	*pline_offset = line_offset;
1552	*pstart_addr = start_addr;
1553	*pline_compare = line_compare;
1554	}
1555
1556	/** update start_addr and line_offset. Return TRUE if modified */
1557	static bool vgaR3UpdateBasicParams(PVGASTATE pThis, PVGASTATER3 pThisCC)
1558	{
1559	bool full_update = false;
1560	uint32_t start_addr, line_offset, line_compare;
1561
1562	pThisCC->get_offsets(pThis, &line_offset, &start_addr, &line_compare);
1563
1564	if (line_offset != pThis->line_offset \|\|
1565	start_addr != pThis->start_addr \|\|
1566	line_compare != pThis->line_compare) {
1567	pThis->line_offset = line_offset;
1568	pThis->start_addr = start_addr;
1569	pThis->line_compare = line_compare;
1570	full_update = true;
1571	}
1572	return full_update;
1573	}
1574
1575	static inline int vgaR3GetDepthIndex(int depth)
1576	{
1577	switch(depth) {
1578	default:
1579	case 8:
1580	return 0;
1581	case 15:
1582	return 1;
1583	case 16:
1584	return 2;
1585	case 32:
1586	return 3;
1587	}
1588	}
1589
1590	static vga_draw_glyph8_func * const vga_draw_glyph8_table[4] = {
1591	vga_draw_glyph8_8,
1592	vga_draw_glyph8_16,
1593	vga_draw_glyph8_16,
1594	vga_draw_glyph8_32,
1595	};
1596
1597	static vga_draw_glyph8_func * const vga_draw_glyph16_table[4] = {
1598	vga_draw_glyph16_8,
1599	vga_draw_glyph16_16,
1600	vga_draw_glyph16_16,
1601	vga_draw_glyph16_32,
1602	};
1603
1604	static vga_draw_glyph9_func * const vga_draw_glyph9_table[4] = {
1605	vga_draw_glyph9_8,
1606	vga_draw_glyph9_16,
1607	vga_draw_glyph9_16,
1608	vga_draw_glyph9_32,
1609	};
1610
1611	static const uint8_t cursor_glyph[32 * 4] = {
1612	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1613	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1614	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1615	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1616	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1617	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1618	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1619	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1620	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1621	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1622	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1623	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1624	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1625	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1626	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1627	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1628	};
1629
1630	static const uint8_t empty_glyph[32 * 4] = { 0 };
1631
1632	/**
1633	* Text mode update
1634	* Missing:
1635	* - underline
1636	*/
1637	static int vgaR3DrawText(PPDMDEVINS pDevIns, PVGASTATE pThis, PVGASTATER3 pThisCC, bool full_update,
1638	bool fFailOnResize, bool reset_dirty, PDMIDISPLAYCONNECTOR *pDrv)
1639	{
1640	int cx, cy, cheight, cw, ch, cattr, height, width, ch_attr;
1641	int cx_min, cx_max, linesize, x_incr;
1642	int cx_min_upd, cx_max_upd, cy_start;
1643	uint32_t offset, fgcol, bgcol, v, cursor_offset;
1644	uint8_t d1, d, src, s1, dest, cursor_ptr;
1645	const uint8_t font_ptr, font_base[2];
1646	int dup9, line_offset, depth_index, dscan;
1647	uint32_t *palette;
1648	uint32_t *ch_attr_ptr;
1649	vga_draw_glyph8_func *vga_draw_glyph8;
1650	vga_draw_glyph9_func *vga_draw_glyph9;
1651	uint64_t time_ns;
1652	bool blink_on, chr_blink_flip, cur_blink_flip;
1653	bool blink_enabled, blink_do_redraw;
1654
1655	full_update \|= vgaR3UpdatePalette16(pThis, pThisCC);
1656	palette = pThis->last_palette;
1657
1658	/* compute font data address (in plane 2) */
1659	v = pThis->sr[3];
1660	offset = (((v >> 4) & 1) \| ((v << 1) & 6)) * 8192 * 4 + 2;
1661	if (offset != pThis->font_offsets[0]) {
1662	pThis->font_offsets[0] = offset;
1663	full_update = true;
1664	}
1665	font_base[0] = pThisCC->pbVRam + offset;
1666
1667	offset = (((v >> 5) & 1) \| ((v >> 1) & 6)) * 8192 * 4 + 2;
1668	font_base[1] = pThisCC->pbVRam + offset;
1669	if (offset != pThis->font_offsets[1]) {
1670	pThis->font_offsets[1] = offset;
1671	full_update = true;
1672	}
1673	if (pThis->plane_updated & (1 << 2)) {
1674	/* if the plane 2 was modified since the last display, it
1675	indicates the font may have been modified */
1676	pThis->plane_updated = 0;
1677	full_update = true;
1678	}
1679	full_update \|= vgaR3UpdateBasicParams(pThis, pThisCC);
1680
1681	line_offset = pThis->line_offset;
1682	s1 = pThisCC->pbVRam + (pThis->start_addr * 8); /** @todo r=bird: Add comment why we do 8 instead of 4, it's not so obvious... */
1683
1684	/* double scanning - not for 9-wide modes */
1685	dscan = (pThis->cr[9] >> 7) & 1;
1686
1687	/* total width & height */
1688	cheight = (pThis->cr[9] & 0x1f) + 1;
1689	cw = 8;
1690	if (!(pThis->sr[1] & 0x01))
1691	cw = 9;
1692	if (pThis->sr[1] & 0x08)
1693	cw = 16; /* NOTE: no 18 pixel wide */
1694	x_incr = cw * ((pDrv->cBits + 7) >> 3);
1695	width = (pThis->cr[0x01] + 1);
1696	if (pThis->cr[0x06] == 100) {
1697	/* ugly hack for CGA 160x100x16 - explain me the logic */
1698	height = 100;
1699	} else {
1700	height = pThis->cr[0x12] \|
1701	((pThis->cr[0x07] & 0x02) << 7) \|
1702	((pThis->cr[0x07] & 0x40) << 3);
1703	height = (height + 1) / cheight;
1704	}
1705	if ((height * width) > CH_ATTR_SIZE) {
1706	/* better than nothing: exit if transient size is too big */
1707	return VINF_SUCCESS;
1708	}
1709
1710	if (width != (int)pThis->last_width \|\| height != (int)pThis->last_height \|\|
1711	cw != pThis->last_cw \|\| cheight != pThis->last_ch) {
1712	if (fFailOnResize)
1713	{
1714	/* The caller does not want to call the pfnResize. */
1715	return VERR_TRY_AGAIN;
1716	}
1717	pThis->last_scr_width = width * cw;
1718	pThis->last_scr_height = height * cheight;
1719	/* For text modes the direct use of guest VRAM is not implemented, so bpp and cbLine are 0 here. */
1720	int rc = pDrv->pfnResize(pDrv, 0, NULL, 0, pThis->last_scr_width, pThis->last_scr_height);
1721	pThis->last_width = width;
1722	pThis->last_height = height;
1723	pThis->last_ch = cheight;
1724	pThis->last_cw = cw;
1725	full_update = true;
1726	if (rc == VINF_VGA_RESIZE_IN_PROGRESS)
1727	return rc;
1728	AssertRC(rc);
1729	}
1730	cursor_offset = ((pThis->cr[0x0e] << 8) \| pThis->cr[0x0f]) - pThis->start_addr;
1731	if (cursor_offset != pThis->cursor_offset \|\|
1732	pThis->cr[0xa] != pThis->cursor_start \|\|
1733	pThis->cr[0xb] != pThis->cursor_end) {
1734	/* if the cursor position changed, we update the old and new
1735	chars */
1736	if (pThis->cursor_offset < CH_ATTR_SIZE)
1737	pThis->last_ch_attr[pThis->cursor_offset] = UINT32_MAX;
1738	if (cursor_offset < CH_ATTR_SIZE)
1739	pThis->last_ch_attr[cursor_offset] = UINT32_MAX;
1740	pThis->cursor_offset = cursor_offset;
1741	pThis->cursor_start = pThis->cr[0xa];
1742	pThis->cursor_end = pThis->cr[0xb];
1743	}
1744	cursor_ptr = pThisCC->pbVRam + (pThis->start_addr + cursor_offset) * 8;
1745	depth_index = vgaR3GetDepthIndex(pDrv->cBits);
1746	if (cw == 16)
1747	vga_draw_glyph8 = vga_draw_glyph16_table[depth_index];
1748	else
1749	vga_draw_glyph8 = vga_draw_glyph8_table[depth_index];
1750	vga_draw_glyph9 = vga_draw_glyph9_table[depth_index];
1751
1752	dest = pDrv->pbData;
1753	linesize = pDrv->cbScanline;
1754	ch_attr_ptr = pThis->last_ch_attr;
1755	cy_start = -1;
1756	cx_max_upd = -1;
1757	cx_min_upd = width;
1758
1759	/* Figure out if we're in the visible period of the blink cycle. */
1760	time_ns = PDMDevHlpTMTimeVirtGetNano(pDevIns);
1761	blink_on = (time_ns % VGA_BLINK_PERIOD_FULL) < VGA_BLINK_PERIOD_ON;
1762	chr_blink_flip = false;
1763	cur_blink_flip = false;
1764	if (pThis->last_chr_blink != blink_on)
1765	{
1766	/* Currently cursor and characters blink at the same rate, but they might not. */
1767	pThis->last_chr_blink = blink_on;
1768	pThis->last_cur_blink = blink_on;
1769	chr_blink_flip = true;
1770	cur_blink_flip = true;
1771	}
1772	blink_enabled = !!(pThis->ar[0x10] & 0x08); /* Attribute controller blink enable. */
1773
1774	for(cy = 0; cy < (height - dscan); cy = cy + (1 << dscan)) {
1775	d1 = dest;
1776	src = s1;
1777	cx_min = width;
1778	cx_max = -1;
1779	for(cx = 0; cx < width; cx++) {
1780	ch_attr = (uint16_t )src;
1781	/* Figure out if character needs redrawing due to blink state change. */
1782	blink_do_redraw = blink_enabled && chr_blink_flip && (ch_attr & 0x8000);
1783	if (full_update \|\| ch_attr != (int)*ch_attr_ptr \|\| blink_do_redraw \|\| (src == cursor_ptr && cur_blink_flip)) {
1784	if (cx < cx_min)
1785	cx_min = cx;
1786	if (cx > cx_max)
1787	cx_max = cx;
1788	if (reset_dirty)
1789	*ch_attr_ptr = ch_attr;
1790	#ifdef WORDS_BIGENDIAN
1791	ch = ch_attr >> 8;
1792	cattr = ch_attr & 0xff;
1793	#else
1794	ch = ch_attr & 0xff;
1795	cattr = ch_attr >> 8;
1796	#endif
1797	font_ptr = font_base[(cattr >> 3) & 1];
1798	font_ptr += 32 * 4 * ch;
1799	bgcol = palette[cattr >> 4];
1800	fgcol = palette[cattr & 0x0f];
1801
1802	if (blink_enabled && (cattr & 0x80))
1803	{
1804	bgcol = palette[(cattr >> 4) & 7];
1805	if (!blink_on)
1806	font_ptr = empty_glyph;
1807	}
1808
1809	if (cw != 9) {
1810	if (pThis->fRenderVRAM)
1811	vga_draw_glyph8(d1, linesize, font_ptr, cheight, fgcol, bgcol, dscan);
1812	} else {
1813	dup9 = 0;
1814	if (ch >= 0xb0 && ch <= 0xdf && (pThis->ar[0x10] & 0x04))
1815	dup9 = 1;
1816	if (pThis->fRenderVRAM)
1817	vga_draw_glyph9(d1, linesize, font_ptr, cheight, fgcol, bgcol, dup9);
1818	}
1819	if (src == cursor_ptr &&
1820	!(pThis->cr[0x0a] & 0x20)) {
1821	int line_start, line_last, h;
1822
1823	/* draw the cursor if within the visible period */
1824	if (blink_on) {
1825	line_start = pThis->cr[0x0a] & 0x1f;
1826	line_last = pThis->cr[0x0b] & 0x1f;
1827	/* XXX: check that */
1828	if (line_last > cheight - 1)
1829	line_last = cheight - 1;
1830	if (line_last >= line_start && line_start < cheight) {
1831	h = line_last - line_start + 1;
1832	d = d1 + (linesize * line_start << dscan);
1833	if (cw != 9) {
1834	if (pThis->fRenderVRAM)
1835	vga_draw_glyph8(d, linesize, cursor_glyph, h, fgcol, bgcol, dscan);
1836	} else {
1837	if (pThis->fRenderVRAM)
1838	vga_draw_glyph9(d, linesize, cursor_glyph, h, fgcol, bgcol, 1);
1839	}
1840	}
1841	}
1842	}
1843	}
1844	d1 += x_incr;
1845	src += 8; /* Every second byte of a plane is used in text mode. */
1846	ch_attr_ptr++;
1847	}
1848	if (cx_max != -1) {
1849	/* Keep track of the bounding rectangle for updates. */
1850	if (cy_start == -1)
1851	cy_start = cy;
1852	if (cx_min_upd > cx_min)
1853	cx_min_upd = cx_min;
1854	if (cx_max_upd < cx_max)
1855	cx_max_upd = cx_max;
1856	} else if (cy_start >= 0) {
1857	/* Flush updates to display. */
1858	pDrv->pfnUpdateRect(pDrv, cx_min_upd * cw, cy_start * cheight,
1859	(cx_max_upd - cx_min_upd + 1) * cw, (cy - cy_start) * cheight);
1860	cy_start = -1;
1861	cx_max_upd = -1;
1862	cx_min_upd = width;
1863	}
1864	dest += linesize * cheight << dscan;
1865	s1 += line_offset;
1866	}
1867	if (cy_start >= 0)
1868	/* Flush any remaining changes to display. */
1869	pDrv->pfnUpdateRect(pDrv, cx_min_upd * cw, cy_start * cheight,
1870	(cx_max_upd - cx_min_upd + 1) * cw, (cy - cy_start) * cheight);
1871	return VINF_SUCCESS;
1872	}
1873
1874	enum {
1875	VGA_DRAW_LINE2,
1876	VGA_DRAW_LINE2D2,
1877	VGA_DRAW_LINE4,
1878	VGA_DRAW_LINE4D2,
1879	VGA_DRAW_LINE8D2,
1880	VGA_DRAW_LINE8,
1881	VGA_DRAW_LINE15,
1882	VGA_DRAW_LINE16,
1883	VGA_DRAW_LINE24,
1884	VGA_DRAW_LINE32,
1885	VGA_DRAW_LINE_NB
1886	};
1887
1888	static vga_draw_line_func * const vga_draw_line_table[4 * VGA_DRAW_LINE_NB] = {
1889	vga_draw_line2_8,
1890	vga_draw_line2_16,
1891	vga_draw_line2_16,
1892	vga_draw_line2_32,
1893
1894	vga_draw_line2d2_8,
1895	vga_draw_line2d2_16,
1896	vga_draw_line2d2_16,
1897	vga_draw_line2d2_32,
1898
1899	vga_draw_line4_8,
1900	vga_draw_line4_16,
1901	vga_draw_line4_16,
1902	vga_draw_line4_32,
1903
1904	vga_draw_line4d2_8,
1905	vga_draw_line4d2_16,
1906	vga_draw_line4d2_16,
1907	vga_draw_line4d2_32,
1908
1909	vga_draw_line8d2_8,
1910	vga_draw_line8d2_16,
1911	vga_draw_line8d2_16,
1912	vga_draw_line8d2_32,
1913
1914	vga_draw_line8_8,
1915	vga_draw_line8_16,
1916	vga_draw_line8_16,
1917	vga_draw_line8_32,
1918
1919	vga_draw_line15_8,
1920	vga_draw_line15_15,
1921	vga_draw_line15_16,
1922	vga_draw_line15_32,
1923
1924	vga_draw_line16_8,
1925	vga_draw_line16_15,
1926	vga_draw_line16_16,
1927	vga_draw_line16_32,
1928
1929	vga_draw_line24_8,
1930	vga_draw_line24_15,
1931	vga_draw_line24_16,
1932	vga_draw_line24_32,
1933
1934	vga_draw_line32_8,
1935	vga_draw_line32_15,
1936	vga_draw_line32_16,
1937	vga_draw_line32_32,
1938	};
1939
1940	static int vgaR3GetBpp(PVGASTATE pThis)
1941	{
1942	int ret;
1943	#ifdef CONFIG_BOCHS_VBE
1944	if (pThis->vbe_regs[VBE_DISPI_INDEX_ENABLE] & VBE_DISPI_ENABLED) {
1945	ret = pThis->vbe_regs[VBE_DISPI_INDEX_BPP];
1946	} else
1947	#endif
1948	{
1949	ret = 0;
1950	}
1951	return ret;
1952	}
1953
1954	static void vgaR3GetResolution(PVGASTATE pThis, int pwidth, int pheight)
1955	{
1956	int width, height;
1957	#ifdef CONFIG_BOCHS_VBE
1958	if (pThis->vbe_regs[VBE_DISPI_INDEX_ENABLE] & VBE_DISPI_ENABLED) {
1959	width = pThis->vbe_regs[VBE_DISPI_INDEX_XRES];
1960	height = RT_MIN(pThis->vbe_regs[VBE_DISPI_INDEX_YRES],
1961	pThis->vbe_regs[VBE_DISPI_INDEX_VIRT_HEIGHT]);
1962	} else
1963	#endif
1964	{
1965	width = (pThis->cr[0x01] + 1) * 8;
1966	height = pThis->cr[0x12] \|
1967	((pThis->cr[0x07] & 0x02) << 7) \|
1968	((pThis->cr[0x07] & 0x40) << 3);
1969	height = (height + 1);
1970	}
1971	*pwidth = width;
1972	*pheight = height;
1973	}
1974
1975
1976	/**
1977	* Performs the display driver resizing when in graphics mode.
1978	*
1979	* This will recalc / update any status data depending on the driver
1980	* properties (bit depth mostly).
1981	*
1982	* @returns VINF_SUCCESS on success.
1983	* @returns VINF_VGA_RESIZE_IN_PROGRESS if the operation wasn't complete.
1984	* @param pThis Pointer to the shared VGA state.
1985	* @param pThisCC Pointer to the ring-3 VGA state.
1986	* @param cx The width.
1987	* @param cy The height.
1988	* @param pDrv The display connector.
1989	*/
1990	static int vgaR3ResizeGraphic(PVGASTATE pThis, PVGASTATER3 pThisCC, int cx, int cy, PDMIDISPLAYCONNECTOR *pDrv)
1991	{
1992	const unsigned cBits = pThisCC->get_bpp(pThis);
1993
1994	int rc;
1995	AssertReturn(cx, VERR_INVALID_PARAMETER);
1996	AssertReturn(cy, VERR_INVALID_PARAMETER);
1997	AssertPtrReturn(pThis, VERR_INVALID_POINTER);
1998
1999	if (!pThis->line_offset)
2000	return VERR_INTERNAL_ERROR;
2001
2002	#if 0 //def VBOX_WITH_VDMA
2003	/** @todo we get a second resize here when VBVA is on, while we actually should not */
2004	/* do not do pfnResize in case VBVA is on since all mode changes are performed over VBVA
2005	* we are checking for VDMA state here to ensure this code works only for WDDM driver,
2006	* although we should avoid calling pfnResize for XPDM as well, since pfnResize is actually an extra resize
2007	* event and generally only pfnVBVAxxx calls should be used with HGSMI + VBVA
2008	*
2009	* The reason for doing this for WDDM driver only now is to avoid regressions of the current code */
2010	PVBOXVDMAHOST pVdma = pThisCC->pVdma;
2011	if (pVdma && vboxVDMAIsEnabled(pVdma))
2012	rc = VINF_SUCCESS;
2013	else
2014	#endif
2015	{
2016	/* Skip the resize if the values are not valid. */
2017	if (pThis->start_addr * 4 + pThis->line_offset * cy < pThis->vram_size)
2018	/* Take into account the programmed start address (in DWORDs) of the visible screen. */
2019	rc = pDrv->pfnResize(pDrv, cBits, pThisCC->pbVRam + pThis->start_addr * 4, pThis->line_offset, cx, cy);
2020	else
2021	{
2022	/* Change nothing in the VGA state. Lets hope the guest will eventually programm correct values. */
2023	return VERR_TRY_AGAIN;
2024	}
2025	}
2026
2027	/* last stuff */
2028	pThis->last_bpp = cBits;
2029	pThis->last_scr_width = cx;
2030	pThis->last_scr_height = cy;
2031	pThis->last_width = cx;
2032	pThis->last_height = cy;
2033
2034	if (rc == VINF_VGA_RESIZE_IN_PROGRESS)
2035	return rc;
2036	AssertRC(rc);
2037
2038	/* update palette */
2039	switch (pDrv->cBits)
2040	{
2041	case 32: pThisCC->rgb_to_pixel = rgb_to_pixel32_dup; break;
2042	case 16:
2043	default: pThisCC->rgb_to_pixel = rgb_to_pixel16_dup; break;
2044	case 15: pThisCC->rgb_to_pixel = rgb_to_pixel15_dup; break;
2045	case 8: pThisCC->rgb_to_pixel = rgb_to_pixel8_dup; break;
2046	}
2047	if (pThis->shift_control == 0)
2048	vgaR3UpdatePalette16(pThis, pThisCC);
2049	else if (pThis->shift_control == 1)
2050	vgaR3UpdatePalette16(pThis, pThisCC);
2051	return VINF_SUCCESS;
2052	}
2053
2054	# ifdef VBOX_WITH_VMSVGA
2055
2056	# if 0 /* unused? */
2057	int vgaR3UpdateDisplay(PVGASTATE pThis, PVGASTATER3 pThisCC, unsigned xStart, unsigned yStart, unsigned cx, unsigned cy, PDMIDISPLAYCONNECTOR *pDrv)
2058	{
2059	uint32_t v;
2060	vga_draw_line_func *vga_draw_line;
2061
2062	if (!pThis->fRenderVRAM)
2063	{
2064	pDrv->pfnUpdateRect(pDrv, xStart, yStart, cx, cy);
2065	return VINF_SUCCESS;
2066	}
2067	/** @todo might crash if a blit follows a resolution change very quickly (seen this many times!) */
2068
2069	if ( pThis->svga.uWidth == VMSVGA_VAL_UNINITIALIZED
2070	\|\| pThis->svga.uHeight == VMSVGA_VAL_UNINITIALIZED
2071	\|\| pThis->svga.uBpp == VMSVGA_VAL_UNINITIALIZED)
2072	{
2073	/* Intermediate state; skip redraws. */
2074	AssertFailed();
2075	return VINF_SUCCESS;
2076	}
2077
2078	uint32_t cBits;
2079	switch (pThis->svga.uBpp) {
2080	default:
2081	case 0:
2082	case 8:
2083	AssertFailed();
2084	return VERR_NOT_IMPLEMENTED;
2085	case 15:
2086	v = VGA_DRAW_LINE15;
2087	cBits = 16;
2088	break;
2089	case 16:
2090	v = VGA_DRAW_LINE16;
2091	cBits = 16;
2092	break;
2093	case 24:
2094	v = VGA_DRAW_LINE24;
2095	cBits = 24;
2096	break;
2097	case 32:
2098	v = VGA_DRAW_LINE32;
2099	cBits = 32;
2100	break;
2101	}
2102	vga_draw_line = vga_draw_line_table[v * 4 + vgaR3GetDepthIndex(pDrv->cBits)];
2103
2104	uint32_t offSrc = (xStart * cBits) / 8 + pThis->svga.cbScanline * yStart;
2105	uint32_t offDst = (xStart * RT_ALIGN(pDrv->cBits, 8)) / 8 + pDrv->cbScanline * yStart;
2106
2107	uint8_t *pbDst = pDrv->pbData + offDst;
2108	uint8_t const *pbSrc = pThisCC->pbVRam + offSrc;
2109
2110	for (unsigned y = yStart; y < yStart + cy; y++)
2111	{
2112	vga_draw_line(pThis, pThisCC, pbDst, pbSrc, cx);
2113
2114	pbDst += pDrv->cbScanline;
2115	pbSrc += pThis->svga.cbScanline;
2116	}
2117	pDrv->pfnUpdateRect(pDrv, xStart, yStart, cx, cy);
2118
2119	return VINF_SUCCESS;
2120	}
2121	# endif
2122
2123	/**
2124	* graphic modes
2125	*/
2126	static int vmsvgaR3DrawGraphic(PVGASTATE pThis, PVGASTATER3 pThisCC, bool fFullUpdate,
2127	bool fFailOnResize, bool reset_dirty, PDMIDISPLAYCONNECTOR *pDrv)
2128	{
2129	RT_NOREF1(fFailOnResize);
2130
2131	uint32_t const cx = pThis->last_scr_width;
2132	uint32_t const cxDisplay = cx;
2133	uint32_t const cy = pThis->last_scr_height;
2134	uint32_t cBits = pThis->last_bpp;
2135
2136	if ( cx == VMSVGA_VAL_UNINITIALIZED
2137	\|\| cx == 0
2138	\|\| cy == VMSVGA_VAL_UNINITIALIZED
2139	\|\| cy == 0
2140	\|\| cBits == VMSVGA_VAL_UNINITIALIZED
2141	\|\| cBits == 0)
2142	{
2143	/* Intermediate state; skip redraws. */
2144	return VINF_SUCCESS;
2145	}
2146
2147	unsigned v;
2148	switch (cBits)
2149	{
2150	case 8:
2151	/* Note! experimental, not sure if this really works... */
2152	/** @todo fFullUpdate \|= vgaR3UpdatePalette256(pThis); - need fFullUpdate but not
2153	* copying anything to last_palette. */
2154	v = VGA_DRAW_LINE8;
2155	break;
2156	case 15:
2157	v = VGA_DRAW_LINE15;
2158	cBits = 16;
2159	break;
2160	case 16:
2161	v = VGA_DRAW_LINE16;
2162	break;
2163	case 24:
2164	v = VGA_DRAW_LINE24;
2165	break;
2166	case 32:
2167	v = VGA_DRAW_LINE32;
2168	break;
2169	default:
2170	case 0:
2171	AssertFailed();
2172	return VERR_NOT_IMPLEMENTED;
2173	}
2174	vga_draw_line_func pfnVgaDrawLine = vga_draw_line_table[v 4 + vgaR3GetDepthIndex(pDrv->cBits)];
2175
2176	Assert(!pThisCC->cursor_invalidate);
2177	Assert(!pThisCC->cursor_draw_line);
2178	//not used// if (pThisCC->cursor_invalidate)
2179	//not used// pThisCC->cursor_invalidate(pThis);
2180
2181	uint8_t *pbDst = pDrv->pbData;
2182	uint32_t cbDstScanline = pDrv->cbScanline;
2183	uint32_t offSrcStart = 0; /* always start at the beginning of the framebuffer */
2184	uint32_t cbScanline = (cx * cBits + 7) / 8; /* The visible width of a scanline. */
2185	uint32_t yUpdateRectTop = UINT32_MAX;
2186	uint32_t offPageMin = UINT32_MAX;
2187	int32_t offPageMax = -1;
2188	uint32_t y;
2189	for (y = 0; y < cy; y++)
2190	{
2191	uint32_t offSrcLine = offSrcStart + y * cbScanline;
2192	uint32_t offPage0 = offSrcLine & ~PAGE_OFFSET_MASK;
2193	uint32_t offPage1 = (offSrcLine + cbScanline - 1) & ~PAGE_OFFSET_MASK;
2194	/** @todo r=klaus this assumes that a line is fully covered by 3 pages,
2195	* irrespective of alignment. Not guaranteed for high res modes, i.e.
2196	* anything wider than 2050 pixels @32bpp. Need to check all pages
2197	* between the first and last one. */
2198	bool fUpdate = fFullUpdate \| vgaIsDirty(pThis, offPage0) \| vgaIsDirty(pThis, offPage1);
2199	if (offPage1 - offPage0 > PAGE_SIZE)
2200	/* if wide line, can use another page */
2201	fUpdate \|= vgaIsDirty(pThis, offPage0 + PAGE_SIZE);
2202	/* explicit invalidation for the hardware cursor */
2203	fUpdate \|= (pThis->invalidated_y_table[y >> 5] >> (y & 0x1f)) & 1;
2204	if (fUpdate)
2205	{
2206	if (yUpdateRectTop == UINT32_MAX)
2207	yUpdateRectTop = y;
2208	if (offPage0 < offPageMin)
2209	offPageMin = offPage0;
2210	if ((int32_t)offPage1 > offPageMax)
2211	offPageMax = offPage1;
2212	if (pThis->fRenderVRAM)
2213	pfnVgaDrawLine(pThis, pThisCC, pbDst, pThisCC->pbVRam + offSrcLine, cx);
2214	//not used// if (pThisCC->cursor_draw_line)
2215	//not used// pThisCC->cursor_draw_line(pThis, pbDst, y);
2216	}
2217	else if (yUpdateRectTop != UINT32_MAX)
2218	{
2219	/* flush to display */
2220	Log(("Flush to display (%d,%d)(%d,%d)\n", 0, yUpdateRectTop, cxDisplay, y - yUpdateRectTop));
2221	pDrv->pfnUpdateRect(pDrv, 0, yUpdateRectTop, cxDisplay, y - yUpdateRectTop);
2222	yUpdateRectTop = UINT32_MAX;
2223	}
2224	pbDst += cbDstScanline;
2225	}
2226	if (yUpdateRectTop != UINT32_MAX)
2227	{
2228	/* flush to display */
2229	Log(("Flush to display (%d,%d)(%d,%d)\n", 0, yUpdateRectTop, cxDisplay, y - yUpdateRectTop));
2230	pDrv->pfnUpdateRect(pDrv, 0, yUpdateRectTop, cxDisplay, y - yUpdateRectTop);
2231	}
2232
2233	/* reset modified pages */
2234	if (offPageMax != -1 && reset_dirty)
2235	vgaR3ResetDirty(pThis, offPageMin, offPageMax + PAGE_SIZE);
2236	memset(pThis->invalidated_y_table, 0, ((cy + 31) >> 5) * 4);
2237
2238	return VINF_SUCCESS;
2239	}
2240
2241	# endif /* VBOX_WITH_VMSVGA */
2242
2243	/**
2244	* graphic modes
2245	*/
2246	static int vgaR3DrawGraphic(PVGASTATE pThis, PVGASTATER3 pThisCC, bool full_update, bool fFailOnResize, bool reset_dirty,
2247	PDMIDISPLAYCONNECTOR *pDrv)
2248	{
2249	int y1, y2, y, page_min, page_max, linesize, y_start, double_scan;
2250	int width, height, shift_control, line_offset, page0, page1, bwidth, bits;
2251	int disp_width, multi_run;
2252	uint8_t *d;
2253	uint32_t v, addr1, addr;
2254	vga_draw_line_func *pfnVgaDrawLine;
2255
2256	bool offsets_changed = vgaR3UpdateBasicParams(pThis, pThisCC);
2257
2258	full_update \|= offsets_changed;
2259
2260	pThisCC->get_resolution(pThis, &width, &height);
2261	disp_width = width;
2262
2263	shift_control = (pThis->gr[0x05] >> 5) & 3;
2264	double_scan = (pThis->cr[0x09] >> 7);
2265	multi_run = double_scan;
2266	if (shift_control != pThis->shift_control \|\|
2267	double_scan != pThis->double_scan) {
2268	full_update = true;
2269	pThis->shift_control = shift_control;
2270	pThis->double_scan = double_scan;
2271	}
2272
2273	if (shift_control == 0) {
2274	full_update \|= vgaR3UpdatePalette16(pThis, pThisCC);
2275	if (pThis->sr[0x01] & 8) {
2276	v = VGA_DRAW_LINE4D2;
2277	disp_width <<= 1;
2278	} else {
2279	v = VGA_DRAW_LINE4;
2280	}
2281	bits = 4;
2282	} else if (shift_control == 1) {
2283	full_update \|= vgaR3UpdatePalette16(pThis, pThisCC);
2284	if (pThis->sr[0x01] & 8) {
2285	v = VGA_DRAW_LINE2D2;
2286	disp_width <<= 1;
2287	} else {
2288	v = VGA_DRAW_LINE2;
2289	}
2290	bits = 4;
2291	} else {
2292	switch(pThisCC->get_bpp(pThis)) {
2293	default:
2294	case 0:
2295	full_update \|= vgaR3UpdatePalette256(pThis, pThisCC);
2296	v = VGA_DRAW_LINE8D2;
2297	bits = 4;
2298	break;
2299	case 8:
2300	full_update \|= vgaR3UpdatePalette256(pThis, pThisCC);
2301	v = VGA_DRAW_LINE8;
2302	bits = 8;
2303	break;
2304	case 15:
2305	v = VGA_DRAW_LINE15;
2306	bits = 16;
2307	break;
2308	case 16:
2309	v = VGA_DRAW_LINE16;
2310	bits = 16;
2311	break;
2312	case 24:
2313	v = VGA_DRAW_LINE24;
2314	bits = 24;
2315	break;
2316	case 32:
2317	v = VGA_DRAW_LINE32;
2318	bits = 32;
2319	break;
2320	}
2321	}
2322	if ( disp_width != (int)pThis->last_width
2323	\|\| height != (int)pThis->last_height
2324	\|\| pThisCC->get_bpp(pThis) != (int)pThis->last_bpp
2325	\|\| (offsets_changed && !pThis->fRenderVRAM))
2326	{
2327	if (fFailOnResize)
2328	{
2329	/* The caller does not want to call the pfnResize. */
2330	return VERR_TRY_AGAIN;
2331	}
2332	int rc = vgaR3ResizeGraphic(pThis, pThisCC, disp_width, height, pDrv);
2333	if (rc != VINF_SUCCESS) /* Return any rc, particularly VINF_VGA_RESIZE_IN_PROGRESS, to the caller. */
2334	return rc;
2335	full_update = true;
2336	}
2337
2338	if (pThis->fRenderVRAM)
2339	{
2340	/* Do not update the destination buffer if it is not big enough.
2341	* Can happen if the resize request was ignored by the driver.
2342	* Compare with 'disp_width', because it is what the framebuffer has been resized to.
2343	*/
2344	if ( pDrv->cx != (uint32_t)disp_width
2345	\|\| pDrv->cy != (uint32_t)height)
2346	{
2347	LogRel(("Framebuffer mismatch: vga %dx%d, drv %dx%d!!!\n",
2348	disp_width, height,
2349	pDrv->cx, pDrv->cy));
2350	return VINF_SUCCESS;
2351	}
2352	}
2353
2354	pfnVgaDrawLine = vga_draw_line_table[v * 4 + vgaR3GetDepthIndex(pDrv->cBits)];
2355
2356	if (pThisCC->cursor_invalidate)
2357	pThisCC->cursor_invalidate(pThis);
2358
2359	line_offset = pThis->line_offset;
2360	#if 0
2361	Log(("w=%d h=%d v=%d line_offset=%d cr[0x09]=0x%02x cr[0x17]=0x%02x linecmp=%d sr[0x01]=0x%02x\n",
2362	width, height, v, line_offset, pThis->cr[9], pThis->cr[0x17], pThis->line_compare, pThis->sr[0x01]));
2363	#endif
2364	addr1 = (pThis->start_addr * 4);
2365	bwidth = (width * bits + 7) / 8; /* The visible width of a scanline. */
2366	y_start = -1;
2367	page_min = 0x7fffffff;
2368	page_max = -1;
2369	d = pDrv->pbData;
2370	linesize = pDrv->cbScanline;
2371
2372	if (!(pThis->vbe_regs[VBE_DISPI_INDEX_ENABLE] & VBE_DISPI_ENABLED))
2373	pThis->vga_addr_mask = 0x3ffff;
2374	else
2375	pThis->vga_addr_mask = UINT32_MAX;
2376
2377	y1 = 0;
2378	y2 = pThis->cr[0x09] & 0x1F; /* starting row scan count */
2379	for(y = 0; y < height; y++) {
2380	addr = addr1;
2381	/* CGA/MDA compatibility. Note that these addresses are all
2382	* shifted left by two compared to VGA specs.
2383	*/
2384	if (!(pThis->cr[0x17] & 1)) {
2385	addr = (addr & ~(1 << 15)) \| ((y1 & 1) << 15);
2386	}
2387	if (!(pThis->cr[0x17] & 2)) {
2388	addr = (addr & ~(1 << 16)) \| ((y1 & 2) << 15);
2389	}
2390	addr &= pThis->vga_addr_mask;
2391	page0 = addr & ~PAGE_OFFSET_MASK;
2392	page1 = (addr + bwidth - 1) & ~PAGE_OFFSET_MASK;
2393	/** @todo r=klaus this assumes that a line is fully covered by 3 pages,
2394	* irrespective of alignment. Not guaranteed for high res modes, i.e.
2395	* anything wider than 2050 pixels @32bpp. Need to check all pages
2396	* between the first and last one. */
2397	bool update = full_update \| vgaIsDirty(pThis, page0) \| vgaIsDirty(pThis, page1);
2398	if (page1 - page0 > PAGE_SIZE) {
2399	/* if wide line, can use another page */
2400	update \|= vgaIsDirty(pThis, page0 + PAGE_SIZE);
2401	}
2402	/* explicit invalidation for the hardware cursor */
2403	update \|= (pThis->invalidated_y_table[y >> 5] >> (y & 0x1f)) & 1;
2404	if (update) {
2405	if (y_start < 0)
2406	y_start = y;
2407	if (page0 < page_min)
2408	page_min = page0;
2409	if (page1 > page_max)
2410	page_max = page1;
2411	if (pThis->fRenderVRAM)
2412	pfnVgaDrawLine(pThis, pThisCC, d, pThisCC->pbVRam + addr, width);
2413	if (pThisCC->cursor_draw_line)
2414	pThisCC->cursor_draw_line(pThis, d, y);
2415	} else {
2416	if (y_start >= 0) {
2417	/* flush to display */
2418	pDrv->pfnUpdateRect(pDrv, 0, y_start, disp_width, y - y_start);
2419	y_start = -1;
2420	}
2421	}
2422	if (!multi_run) {
2423	y1++;
2424	multi_run = double_scan;
2425
2426	if (y2 == 0) {
2427	y2 = pThis->cr[0x09] & 0x1F;
2428	addr1 += line_offset;
2429	} else {
2430	--y2;
2431	}
2432	} else {
2433	multi_run--;
2434	}
2435	/* line compare acts on the displayed lines */
2436	if ((uint32_t)y == pThis->line_compare)
2437	addr1 = 0;
2438	d += linesize;
2439	}
2440	if (y_start >= 0) {
2441	/* flush to display */
2442	pDrv->pfnUpdateRect(pDrv, 0, y_start, disp_width, y - y_start);
2443	}
2444	/* reset modified pages */
2445	if (page_max != -1 && reset_dirty) {
2446	vgaR3ResetDirty(pThis, page_min, page_max + PAGE_SIZE);
2447	}
2448	memset(pThis->invalidated_y_table, 0, ((height + 31) >> 5) * 4);
2449	return VINF_SUCCESS;
2450	}
2451
2452	/**
2453	* blanked modes
2454	*/
2455	static int vgaR3DrawBlank(PVGASTATE pThis, PVGASTATER3 pThisCC, bool full_update,
2456	bool fFailOnResize, bool reset_dirty, PDMIDISPLAYCONNECTOR *pDrv)
2457	{
2458	int i, w, val;
2459	uint8_t *d;
2460	uint32_t cbScanline = pDrv->cbScanline;
2461	uint32_t page_min, page_max;
2462
2463	if (pThis->last_width != 0)
2464	{
2465	if (fFailOnResize)
2466	{
2467	/* The caller does not want to call the pfnResize. */
2468	return VERR_TRY_AGAIN;
2469	}
2470	pThis->last_width = 0;
2471	pThis->last_height = 0;
2472	/* For blanking signal width=0, height=0, bpp=0 and cbLine=0 here.
2473	* There is no screen content, which distinguishes it from text mode. */
2474	pDrv->pfnResize(pDrv, 0, NULL, 0, 0, 0);
2475	}
2476	/* reset modified pages, i.e. everything */
2477	if (reset_dirty && pThis->last_scr_height > 0)
2478	{
2479	page_min = (pThis->start_addr * 4) & ~PAGE_OFFSET_MASK;
2480	/* round up page_max by one page, as otherwise this can be -PAGE_SIZE,
2481	* which causes assertion trouble in vgaR3ResetDirty. */
2482	page_max = ( pThis->start_addr * 4 + pThis->line_offset * pThis->last_scr_height
2483	- 1 + PAGE_SIZE) & ~PAGE_OFFSET_MASK;
2484	vgaR3ResetDirty(pThis, page_min, page_max + PAGE_SIZE);
2485	}
2486	if (pDrv->pbData == pThisCC->pbVRam) /* Do not clear the VRAM itself. */
2487	return VINF_SUCCESS;
2488	if (!full_update)
2489	return VINF_SUCCESS;
2490	if (pThis->last_scr_width <= 0 \|\| pThis->last_scr_height <= 0)
2491	return VINF_SUCCESS;
2492	if (pDrv->cBits == 8)
2493	val = pThisCC->rgb_to_pixel(0, 0, 0);
2494	else
2495	val = 0;
2496	w = pThis->last_scr_width * ((pDrv->cBits + 7) >> 3);
2497	d = pDrv->pbData;
2498	if (pThis->fRenderVRAM)
2499	{
2500	for(i = 0; i < (int)pThis->last_scr_height; i++) {
2501	memset(d, val, w);
2502	d += cbScanline;
2503	}
2504	}
2505	pDrv->pfnUpdateRect(pDrv, 0, 0, pThis->last_scr_width, pThis->last_scr_height);
2506	return VINF_SUCCESS;
2507	}
2508
2509
2510	#define GMODE_TEXT 0
2511	#define GMODE_GRAPH 1
2512	#define GMODE_BLANK 2
2513	#ifdef VBOX_WITH_VMSVGA
2514	#define GMODE_SVGA 3
2515	#endif
2516
2517	/**
2518	* Worker for vgaR3PortUpdateDisplay(), vboxR3UpdateDisplayAllInternal() and
2519	* vgaR3PortTakeScreenshot().
2520	*/
2521	static int vgaR3UpdateDisplay(PPDMDEVINS pDevIns, PVGASTATE pThis, PVGASTATER3 pThisCC, bool fUpdateAll,
2522	bool fFailOnResize, bool reset_dirty, PDMIDISPLAYCONNECTOR pDrv, int32_t pcur_graphic_mode)
2523	{
2524	int rc = VINF_SUCCESS;
2525	int graphic_mode;
2526
2527	if (pDrv->cBits == 0) {
2528	/* nothing to do */
2529	} else {
2530	switch(pDrv->cBits) {
2531	case 8:
2532	pThisCC->rgb_to_pixel = rgb_to_pixel8_dup;
2533	break;
2534	case 15:
2535	pThisCC->rgb_to_pixel = rgb_to_pixel15_dup;
2536	break;
2537	default:
2538	case 16:
2539	pThisCC->rgb_to_pixel = rgb_to_pixel16_dup;
2540	break;
2541	case 32:
2542	pThisCC->rgb_to_pixel = rgb_to_pixel32_dup;
2543	break;
2544	}
2545
2546	#ifdef VBOX_WITH_VMSVGA
2547	if (pThis->svga.fEnabled) {
2548	graphic_mode = GMODE_SVGA;
2549	}
2550	else
2551	#endif
2552	if (!(pThis->ar_index & 0x20) \|\| (pThis->sr[0x01] & 0x20)) {
2553	graphic_mode = GMODE_BLANK;
2554	} else {
2555	graphic_mode = pThis->gr[6] & 1 ? GMODE_GRAPH : GMODE_TEXT;
2556	}
2557	bool full_update = fUpdateAll \|\| graphic_mode != *pcur_graphic_mode;
2558	if (full_update) {
2559	*pcur_graphic_mode = graphic_mode;
2560	}
2561	switch(graphic_mode) {
2562	case GMODE_TEXT:
2563	rc = vgaR3DrawText(pDevIns, pThis, pThisCC, full_update, fFailOnResize, reset_dirty, pDrv);
2564	break;
2565	case GMODE_GRAPH:
2566	rc = vgaR3DrawGraphic(pThis, pThisCC, full_update, fFailOnResize, reset_dirty, pDrv);
2567	break;
2568	#ifdef VBOX_WITH_VMSVGA
2569	case GMODE_SVGA:
2570	rc = vmsvgaR3DrawGraphic(pThis, pThisCC, full_update, fFailOnResize, reset_dirty, pDrv);
2571	break;
2572	#endif
2573	case GMODE_BLANK:
2574	default:
2575	rc = vgaR3DrawBlank(pThis, pThisCC, full_update, fFailOnResize, reset_dirty, pDrv);
2576	break;
2577	}
2578	}
2579	return rc;
2580	}
2581
2582	/**
2583	* Worker for vgaR3SaveExec().
2584	*/
2585	static void vga_save(PCPDMDEVHLPR3 pHlp, PSSMHANDLE pSSM, PVGASTATE pThis)
2586	{
2587	int i;
2588
2589	pHlp->pfnSSMPutU32(pSSM, pThis->latch);
2590	pHlp->pfnSSMPutU8(pSSM, pThis->sr_index);
2591	pHlp->pfnSSMPutMem(pSSM, pThis->sr, 8);
2592	pHlp->pfnSSMPutU8(pSSM, pThis->gr_index);
2593	pHlp->pfnSSMPutMem(pSSM, pThis->gr, 16);
2594	pHlp->pfnSSMPutU8(pSSM, pThis->ar_index);
2595	pHlp->pfnSSMPutMem(pSSM, pThis->ar, 21);
2596	pHlp->pfnSSMPutU32(pSSM, pThis->ar_flip_flop);
2597	pHlp->pfnSSMPutU8(pSSM, pThis->cr_index);
2598	pHlp->pfnSSMPutMem(pSSM, pThis->cr, 256);
2599	pHlp->pfnSSMPutU8(pSSM, pThis->msr);
2600	pHlp->pfnSSMPutU8(pSSM, pThis->fcr);
2601	pHlp->pfnSSMPutU8(pSSM, pThis->st00);
2602	pHlp->pfnSSMPutU8(pSSM, pThis->st01);
2603
2604	pHlp->pfnSSMPutU8(pSSM, pThis->dac_state);
2605	pHlp->pfnSSMPutU8(pSSM, pThis->dac_sub_index);
2606	pHlp->pfnSSMPutU8(pSSM, pThis->dac_read_index);
2607	pHlp->pfnSSMPutU8(pSSM, pThis->dac_write_index);
2608	pHlp->pfnSSMPutMem(pSSM, pThis->dac_cache, 3);
2609	pHlp->pfnSSMPutMem(pSSM, pThis->palette, 768);
2610
2611	pHlp->pfnSSMPutU32(pSSM, pThis->bank_offset);
2612	#ifdef CONFIG_BOCHS_VBE
2613	AssertCompile(RT_ELEMENTS(pThis->vbe_regs) < 256);
2614	pHlp->pfnSSMPutU8(pSSM, (uint8_t)RT_ELEMENTS(pThis->vbe_regs));
2615	pHlp->pfnSSMPutU16(pSSM, pThis->vbe_index);
2616	for(i = 0; i < (int)RT_ELEMENTS(pThis->vbe_regs); i++)
2617	pHlp->pfnSSMPutU16(pSSM, pThis->vbe_regs[i]);
2618	pHlp->pfnSSMPutU32(pSSM, pThis->vbe_start_addr);
2619	pHlp->pfnSSMPutU32(pSSM, pThis->vbe_line_offset);
2620	#else
2621	pHlp->pfnSSMPutU8(pSSM, 0);
2622	#endif
2623	}
2624
2625
2626	/**
2627	* Worker for vgaR3LoadExec().
2628	*/
2629	static int vga_load(PCPDMDEVHLPR3 pHlp, PSSMHANDLE pSSM, PVGASTATE pThis, int version_id)
2630	{
2631	int is_vbe, i;
2632	uint32_t u32Dummy;
2633	uint8_t u8;
2634
2635	pHlp->pfnSSMGetU32(pSSM, &pThis->latch);
2636	pHlp->pfnSSMGetU8(pSSM, &pThis->sr_index);
2637	pHlp->pfnSSMGetMem(pSSM, pThis->sr, 8);
2638	pHlp->pfnSSMGetU8(pSSM, &pThis->gr_index);
2639	pHlp->pfnSSMGetMem(pSSM, pThis->gr, 16);
2640	pHlp->pfnSSMGetU8(pSSM, &pThis->ar_index);
2641	pHlp->pfnSSMGetMem(pSSM, pThis->ar, 21);
2642	pHlp->pfnSSMGetS32(pSSM, &pThis->ar_flip_flop);
2643	pHlp->pfnSSMGetU8(pSSM, &pThis->cr_index);
2644	pHlp->pfnSSMGetMem(pSSM, pThis->cr, 256);
2645	pHlp->pfnSSMGetU8(pSSM, &pThis->msr);
2646	pHlp->pfnSSMGetU8(pSSM, &pThis->fcr);
2647	pHlp->pfnSSMGetU8(pSSM, &pThis->st00);
2648	pHlp->pfnSSMGetU8(pSSM, &pThis->st01);
2649
2650	pHlp->pfnSSMGetU8(pSSM, &pThis->dac_state);
2651	pHlp->pfnSSMGetU8(pSSM, &pThis->dac_sub_index);
2652	pHlp->pfnSSMGetU8(pSSM, &pThis->dac_read_index);
2653	pHlp->pfnSSMGetU8(pSSM, &pThis->dac_write_index);
2654	pHlp->pfnSSMGetMem(pSSM, pThis->dac_cache, 3);
2655	pHlp->pfnSSMGetMem(pSSM, pThis->palette, 768);
2656
2657	pHlp->pfnSSMGetS32(pSSM, &pThis->bank_offset);
2658	pHlp->pfnSSMGetU8(pSSM, &u8);
2659	is_vbe = !!u8;
2660	#ifdef CONFIG_BOCHS_VBE
2661	if (!is_vbe)
2662	{
2663	Log(("vga_load: !is_vbe !!\n"));
2664	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
2665	}
2666
2667	if (u8 == 1)
2668	u8 = VBE_DISPI_INDEX_NB_SAVED; /* Used to save so many registers. */
2669	if (u8 > RT_ELEMENTS(pThis->vbe_regs))
2670	{
2671	Log(("vga_load: saved %d, expected %d!!\n", u8, RT_ELEMENTS(pThis->vbe_regs)));
2672	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
2673	}
2674
2675	pHlp->pfnSSMGetU16(pSSM, &pThis->vbe_index);
2676	for(i = 0; i < (int)u8; i++)
2677	pHlp->pfnSSMGetU16(pSSM, &pThis->vbe_regs[i]);
2678	if (version_id <= VGA_SAVEDSTATE_VERSION_INV_VHEIGHT)
2679	recalculate_data(pThis); /* <- re-calculate the pThis->vbe_regs[VBE_DISPI_INDEX_VIRT_HEIGHT] since it might be invalid */
2680	pHlp->pfnSSMGetU32(pSSM, &pThis->vbe_start_addr);
2681	pHlp->pfnSSMGetU32(pSSM, &pThis->vbe_line_offset);
2682	if (version_id < 2)
2683	pHlp->pfnSSMGetU32(pSSM, &u32Dummy);
2684	pThis->vbe_bank_max = (pThis->vram_size >> 16) - 1;
2685	#else
2686	if (is_vbe)
2687	{
2688	Log(("vga_load: is_vbe !!\n"));
2689	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
2690	}
2691	#endif
2692
2693	/* force refresh */
2694	pThis->graphic_mode = -1;
2695	return 0;
2696	}
2697
2698
2699	/**
2700	* Worker for vgaR3Construct().
2701	*/
2702	static void vgaR3InitExpand(void)
2703	{
2704	int i, j, v, b;
2705
2706	for(i = 0;i < 256; i++) {
2707	v = 0;
2708	for(j = 0; j < 8; j++) {
2709	v \|= ((i >> j) & 1) << (j * 4);
2710	}
2711	expand4[i] = v;
2712
2713	v = 0;
2714	for(j = 0; j < 4; j++) {
2715	v \|= ((i >> (2 * j)) & 3) << (j * 4);
2716	}
2717	expand2[i] = v;
2718	}
2719	for(i = 0; i < 16; i++) {
2720	v = 0;
2721	for(j = 0; j < 4; j++) {
2722	b = ((i >> j) & 1);
2723	v \|= b << (2 * j);
2724	v \|= b << (2 * j + 1);
2725	}
2726	expand4to8[i] = v;
2727	}
2728	}
2729
2730	#endif /* IN_RING3 */
2731
2732
2733
2734	/* -=-=-=-=-=- all contexts -=-=-=-=-=- */
2735
2736	#define VGA_IOPORT_WRITE_PLACEHOLDER(a_uPort, a_cPorts) do {\
2737	PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE); \
2738	Assert(PDMDevHlpCritSectIsOwner(pDevIns, pDevIns->CTX_SUFF(pCritSectRo))); \
2739	AssertCompile(RT_IS_POWER_OF_TWO(a_cPorts)); \
2740	Assert((unsigned)offPort - (unsigned)(a_uPort) < (unsigned)(a_cPorts)); \
2741	NOREF(pvUser); \
2742	if (cb == 1) \
2743	vga_ioport_write(pDevIns, pThis, offPort, u32); \
2744	else if (cb == 2) \
2745	{ \
2746	vga_ioport_write(pDevIns, pThis, offPort, u32 & 0xff); \
2747	vga_ioport_write(pDevIns, pThis, offPort + 1, u32 >> 8); \
2748	} \
2749	return VINF_SUCCESS; \
2750	} while (0)
2751
2752	#define VGA_IOPORT_READ_PLACEHOLDER(a_uPort, a_cPorts) do {\
2753	PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE); \
2754	Assert(PDMDevHlpCritSectIsOwner(pDevIns, pDevIns->CTX_SUFF(pCritSectRo))); \
2755	AssertCompile(RT_IS_POWER_OF_TWO(a_cPorts)); \
2756	Assert((unsigned)offPort - (unsigned)(a_uPort) < (unsigned)(a_cPorts)); \
2757	NOREF(pvUser); \
2758	if (cb == 1) \
2759	*pu32 = vga_ioport_read(pDevIns, pThis, offPort); \
2760	else if (cb == 2) \
2761	{ \
2762	uint32_t u32 = vga_ioport_read(pDevIns, pThis, offPort); \
2763	u32 \|= vga_ioport_read(pDevIns, pThis, offPort + 1) << 8; \
2764	*pu32 = u32; \
2765	} \
2766	else \
2767	return VERR_IOM_IOPORT_UNUSED; \
2768	return VINF_SUCCESS; \
2769	} while (0)
2770
2771	/**
2772	* @callback_method_impl{FNIOMIOPORTNEWOUT,0x3c0-0x3c1 Attribute Controller.}
2773	*/
2774	static DECLCALLBACK(VBOXSTRICTRC) vgaIoPortArWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT offPort, uint32_t u32, unsigned cb)
2775	{
2776	VGA_IOPORT_WRITE_PLACEHOLDER(0x3c0, 2);
2777	}
2778
2779	/**
2780	* @callback_method_impl{FNIOMIOPORTNEWIN,0x3c0-0x3c1 Attribute Controller.}
2781	*/
2782	static DECLCALLBACK(VBOXSTRICTRC) vgaIoPortArRead(PPDMDEVINS pDevIns, void pvUser, RTIOPORT offPort, uint32_t pu32, unsigned cb)
2783	{
2784	VGA_IOPORT_READ_PLACEHOLDER(0x3c0, 2);
2785	}
2786
2787
2788	/**
2789	* @callback_method_impl{FNIOMIOPORTNEWOUT,0x3c2 Miscellaneous Register.}
2790	*/
2791	static DECLCALLBACK(VBOXSTRICTRC) vgaIoPortMsrWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT offPort, uint32_t u32, unsigned cb)
2792	{
2793	VGA_IOPORT_WRITE_PLACEHOLDER(0x3c2, 1);
2794	}
2795
2796	/**
2797	* @callback_method_impl{FNIOMIOPORTNEWIN,0x3c2 Status register 0.}
2798	*/
2799	static DECLCALLBACK(VBOXSTRICTRC) vgaIoPortSt00Read(PPDMDEVINS pDevIns, void pvUser, RTIOPORT offPort, uint32_t pu32, unsigned cb)
2800	{
2801	VGA_IOPORT_READ_PLACEHOLDER(0x3c2, 1);
2802	}
2803
2804
2805	/**
2806	* @callback_method_impl{FNIOMIOPORTNEWOUT,0x3c3 Unused.}
2807	*/
2808	static DECLCALLBACK(VBOXSTRICTRC) vgaIoPortUnusedWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT offPort, uint32_t u32, unsigned cb)
2809	{
2810	VGA_IOPORT_WRITE_PLACEHOLDER(0x3c3, 1);
2811	}
2812
2813	/**
2814	* @callback_method_impl{FNIOMIOPORTNEWIN,0x3c3 Unused.}
2815	*/
2816	static DECLCALLBACK(VBOXSTRICTRC) vgaIoPortUnusedRead(PPDMDEVINS pDevIns, void pvUser, RTIOPORT offPort, uint32_t pu32, unsigned cb)
2817	{
2818	VGA_IOPORT_READ_PLACEHOLDER(0x3c3, 1);
2819	}
2820
2821
2822	/**
2823	* @callback_method_impl{FNIOMIOPORTNEWOUT,0x3c4-0x3c5 Sequencer.}
2824	*/
2825	static DECLCALLBACK(VBOXSTRICTRC) vgaIoPortSrWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT offPort, uint32_t u32, unsigned cb)
2826	{
2827	VGA_IOPORT_WRITE_PLACEHOLDER(0x3c4, 2);
2828	}
2829
2830	/**
2831	* @callback_method_impl{FNIOMIOPORTNEWIN,0x3c4-0x3c5 Sequencer.}
2832	*/
2833	static DECLCALLBACK(VBOXSTRICTRC) vgaIoPortSrRead(PPDMDEVINS pDevIns, void pvUser, RTIOPORT offPort, uint32_t pu32, unsigned cb)
2834	{
2835	VGA_IOPORT_READ_PLACEHOLDER(0x3c4, 2);
2836	}
2837
2838
2839	/**
2840	* @callback_method_impl{FNIOMIOPORTNEWOUT,0x3c6-0x3c9 DAC.}
2841	*/
2842	static DECLCALLBACK(VBOXSTRICTRC) vgaIoPortDacWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT offPort, uint32_t u32, unsigned cb)
2843	{
2844	VGA_IOPORT_WRITE_PLACEHOLDER(0x3c6, 4);
2845	}
2846
2847	/**
2848	* @callback_method_impl{FNIOMIOPORTNEWIN,0x3c6-0x3c9 DAC.}
2849	*/
2850	static DECLCALLBACK(VBOXSTRICTRC) vgaIoPortDacRead(PPDMDEVINS pDevIns, void pvUser, RTIOPORT offPort, uint32_t pu32, unsigned cb)
2851	{
2852	VGA_IOPORT_READ_PLACEHOLDER(0x3c6, 4);
2853	}
2854
2855
2856	/**
2857	* @callback_method_impl{FNIOMIOPORTNEWOUT,0x3ca-0x3cd Graphics Position?}
2858	*/
2859	static DECLCALLBACK(VBOXSTRICTRC) vgaIoPortPosWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT offPort, uint32_t u32, unsigned cb)
2860	{
2861	VGA_IOPORT_WRITE_PLACEHOLDER(0x3ca, 4);
2862	}
2863
2864	/**
2865	* @callback_method_impl{FNIOMIOPORTNEWIN,0x3ca-0x3cd Graphics Position?}
2866	*/
2867	static DECLCALLBACK(VBOXSTRICTRC) vgaIoPortPosRead(PPDMDEVINS pDevIns, void pvUser, RTIOPORT offPort, uint32_t pu32, unsigned cb)
2868	{
2869	VGA_IOPORT_READ_PLACEHOLDER(0x3ca, 4);
2870	}
2871
2872
2873	/**
2874	* @callback_method_impl{FNIOMIOPORTNEWOUT,0x3ce-0x3cf Graphics Controller.}
2875	*/
2876	static DECLCALLBACK(VBOXSTRICTRC) vgaIoPortGrWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT offPort, uint32_t u32, unsigned cb)
2877	{
2878	VGA_IOPORT_WRITE_PLACEHOLDER(0x3ce, 2);
2879	}
2880
2881	/**
2882	* @callback_method_impl{FNIOMIOPORTNEWIN,0x3ca-0x3cf Graphics Controller.}
2883	*/
2884	static DECLCALLBACK(VBOXSTRICTRC) vgaIoPortGrRead(PPDMDEVINS pDevIns, void pvUser, RTIOPORT offPort, uint32_t pu32, unsigned cb)
2885	{
2886	VGA_IOPORT_READ_PLACEHOLDER(0x3ce, 2);
2887	}
2888
2889
2890	/**
2891	* @callback_method_impl{FNIOMIOPORTNEWOUT,0x3b4-0x3b5 MDA CRT control.}
2892	*/
2893	static DECLCALLBACK(VBOXSTRICTRC) vgaIoPortMdaCrtWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT offPort, uint32_t u32, unsigned cb)
2894	{
2895	/** @todo do vga_ioport_invalid here */
2896	VGA_IOPORT_WRITE_PLACEHOLDER(0x3b4, 2);
2897	}
2898
2899	/**
2900	* @callback_method_impl{FNIOMIOPORTNEWIN,0x3b4-0x3b5 MDA CRT control.}
2901	*/
2902	static DECLCALLBACK(VBOXSTRICTRC) vgaIoPortMdaCrtRead(PPDMDEVINS pDevIns, void pvUser, RTIOPORT offPort, uint32_t pu32, unsigned cb)
2903	{
2904	/** @todo do vga_ioport_invalid here */
2905	VGA_IOPORT_READ_PLACEHOLDER(0x3b4, 2);
2906	}
2907
2908
2909	/**
2910	* @callback_method_impl{FNIOMIOPORTNEWOUT,0x3ba MDA feature/status.}
2911	*/
2912	static DECLCALLBACK(VBOXSTRICTRC) vgaIoPortMdaFcrWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT offPort, uint32_t u32, unsigned cb)
2913	{
2914	/** @todo do vga_ioport_invalid here */
2915	VGA_IOPORT_WRITE_PLACEHOLDER(0x3ba, 1);
2916	}
2917
2918	/**
2919	* @callback_method_impl{FNIOMIOPORTNEWIN,0x3ba MDA feature/status.}
2920	*/
2921	static DECLCALLBACK(VBOXSTRICTRC) vgaIoPortMdaStRead(PPDMDEVINS pDevIns, void pvUser, RTIOPORT offPort, uint32_t pu32, unsigned cb)
2922	{
2923	/** @todo do vga_ioport_invalid here */
2924	VGA_IOPORT_READ_PLACEHOLDER(0x3ba, 1);
2925	}
2926
2927
2928	/**
2929	* @callback_method_impl{FNIOMIOPORTNEWOUT,0x3d4-0x3d5 CGA CRT control.}
2930	*/
2931	static DECLCALLBACK(VBOXSTRICTRC) vgaIoPortCgaCrtWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT offPort, uint32_t u32, unsigned cb)
2932	{
2933	/** @todo do vga_ioport_invalid here */
2934	VGA_IOPORT_WRITE_PLACEHOLDER(0x3d4, 2);
2935	}
2936
2937	/**
2938	* @callback_method_impl{FNIOMIOPORTNEWIN,0x3d4-0x3d5 CGA CRT control.}
2939	*/
2940	static DECLCALLBACK(VBOXSTRICTRC) vgaIoPortCgaCrtRead(PPDMDEVINS pDevIns, void pvUser, RTIOPORT offPort, uint32_t pu32, unsigned cb)
2941	{
2942	/** @todo do vga_ioport_invalid here */
2943	VGA_IOPORT_READ_PLACEHOLDER(0x3d4, 2);
2944	}
2945
2946
2947	/**
2948	* @callback_method_impl{FNIOMIOPORTNEWOUT,0x3da CGA feature/status.}
2949	*/
2950	static DECLCALLBACK(VBOXSTRICTRC) vgaIoPortCgaFcrWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT offPort, uint32_t u32, unsigned cb)
2951	{
2952	/** @todo do vga_ioport_invalid here */
2953	VGA_IOPORT_WRITE_PLACEHOLDER(0x3da, 1);
2954	}
2955
2956	/**
2957	* @callback_method_impl{FNIOMIOPORTNEWIN,0x3da CGA feature/status.}
2958	*/
2959	static DECLCALLBACK(VBOXSTRICTRC) vgaIoPortCgaStRead(PPDMDEVINS pDevIns, void pvUser, RTIOPORT offPort, uint32_t pu32, unsigned cb)
2960	{
2961	/** @todo do vga_ioport_invalid here */
2962	VGA_IOPORT_READ_PLACEHOLDER(0x3da, 1);
2963	}
2964
2965
2966	/**
2967	* @callback_method_impl{FNIOMIOPORTNEWOUT,VBE Data Port OUT handler (0x1ce).}
2968	*/
2969	static DECLCALLBACK(VBOXSTRICTRC)
2970	vgaIoPortWriteVbeData(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT offPort, uint32_t u32, unsigned cb)
2971	{
2972	PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE);
2973	PVGASTATECC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PVGASTATECC);
2974	Assert(PDMDevHlpCritSectIsOwner(pDevIns, pDevIns->CTX_SUFF(pCritSectRo)));
2975
2976	NOREF(pvUser);
2977
2978	#ifndef IN_RING3
2979	/*
2980	* This has to be done on the host in order to execute the connector callbacks.
2981	*/
2982	if ( pThis->vbe_index == VBE_DISPI_INDEX_ENABLE
2983	\|\| pThis->vbe_index == VBE_DISPI_INDEX_VBOX_VIDEO)
2984	{
2985	Log(("vgaIoPortWriteVbeData: VBE_DISPI_INDEX_ENABLE - Switching to host...\n"));
2986	return VINF_IOM_R3_IOPORT_WRITE;
2987	}
2988	#endif
2989	#ifdef VBE_BYTEWISE_IO
2990	if (cb == 1)
2991	{
2992	if (!pThis->fWriteVBEData)
2993	{
2994	if ( (pThis->vbe_index == VBE_DISPI_INDEX_ENABLE)
2995	&& (u32 & VBE_DISPI_ENABLED))
2996	{
2997	pThis->fWriteVBEData = false;
2998	return vbe_ioport_write_data(pDevIns, pThis, pThisCC, offPort, u32 & 0xFF);
2999	}
3000
3001	pThis->cbWriteVBEData = u32 & 0xFF;
3002	pThis->fWriteVBEData = true;
3003	return VINF_SUCCESS;
3004	}
3005
3006	u32 = (pThis->cbWriteVBEData << 8) \| (u32 & 0xFF);
3007	pThis->fWriteVBEData = false;
3008	cb = 2;
3009	}
3010	#endif
3011	if (cb == 2 \|\| cb == 4)
3012	return vbe_ioport_write_data(pDevIns, pThis, pThisCC, offPort, u32);
3013	AssertMsgFailed(("vgaIoPortWriteVbeData: offPort=%#x cb=%d u32=%#x\n", offPort, cb, u32));
3014
3015	return VINF_SUCCESS;
3016	}
3017
3018
3019	/**
3020	* @callback_method_impl{FNIOMIOPORTNEWOUT,VBE Index Port OUT handler (0x1ce).}
3021	*/
3022	static DECLCALLBACK(VBOXSTRICTRC)
3023	vgaIoPortWriteVbeIndex(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT offPort, uint32_t u32, unsigned cb)
3024	{
3025	PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE); NOREF(pvUser);
3026	Assert(PDMDevHlpCritSectIsOwner(pDevIns, pDevIns->CTX_SUFF(pCritSectRo)));
3027
3028	#ifdef VBE_BYTEWISE_IO
3029	if (cb == 1)
3030	{
3031	if (!pThis->fWriteVBEIndex)
3032	{
3033	pThis->cbWriteVBEIndex = u32 & 0x00FF;
3034	pThis->fWriteVBEIndex = true;
3035	return VINF_SUCCESS;
3036	}
3037	pThis->fWriteVBEIndex = false;
3038	vbe_ioport_write_index(pThis, offPort, (pThis->cbWriteVBEIndex << 8) \| (u32 & 0x00FF));
3039	return VINF_SUCCESS;
3040	}
3041	#endif
3042
3043	if (cb == 2)
3044	vbe_ioport_write_index(pThis, offPort, u32);
3045	else
3046	ASSERT_GUEST_MSG_FAILED(("vgaIoPortWriteVbeIndex: offPort=%#x cb=%d u32=%#x\n", offPort, cb, u32));
3047	return VINF_SUCCESS;
3048	}
3049
3050
3051	/**
3052	* @callback_method_impl{FNIOMIOPORTNEWOUT,VBE Data Port IN handler (0x1cf).}
3053	*/
3054	static DECLCALLBACK(VBOXSTRICTRC)
3055	vgaIoPortReadVbeData(PPDMDEVINS pDevIns, void pvUser, RTIOPORT offPort, uint32_t pu32, unsigned cb)
3056	{
3057	PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE); NOREF(pvUser);
3058	Assert(PDMDevHlpCritSectIsOwner(pDevIns, pDevIns->CTX_SUFF(pCritSectRo)));
3059
3060	#ifdef VBE_BYTEWISE_IO
3061	if (cb == 1)
3062	{
3063	if (!pThis->fReadVBEData)
3064	{
3065	*pu32 = (vbe_ioport_read_data(pThis, offPort) >> 8) & 0xFF;
3066	pThis->fReadVBEData = true;
3067	return VINF_SUCCESS;
3068	}
3069	*pu32 = vbe_ioport_read_data(pThis, offPort) & 0xFF;
3070	pThis->fReadVBEData = false;
3071	return VINF_SUCCESS;
3072	}
3073	#endif
3074	if (cb == 2)
3075	{
3076	*pu32 = vbe_ioport_read_data(pThis, offPort);
3077	return VINF_SUCCESS;
3078	}
3079	if (cb == 4)
3080	{
3081	if (pThis->vbe_regs[VBE_DISPI_INDEX_ID] == VBE_DISPI_ID_CFG)
3082	pu32 = vbe_ioport_read_data(pThis, offPort); / New interface. */
3083	else
3084	pu32 = pThis->vram_size; / Quick hack for getting the vram size. */
3085	return VINF_SUCCESS;
3086	}
3087	AssertMsgFailed(("vgaIoPortReadVbeData: offPort=%#x cb=%d\n", offPort, cb));
3088	return VERR_IOM_IOPORT_UNUSED;
3089	}
3090
3091
3092	/**
3093	* @callback_method_impl{FNIOMIOPORTNEWOUT,VBE Index Port IN handler (0x1cf).}
3094	*/
3095	static DECLCALLBACK(VBOXSTRICTRC)
3096	vgaIoPortReadVbeIndex(PPDMDEVINS pDevIns, void pvUser, RTIOPORT offPort, uint32_t pu32, unsigned cb)
3097	{
3098	NOREF(pvUser);
3099	PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE);
3100	Assert(PDMDevHlpCritSectIsOwner(pDevIns, pDevIns->CTX_SUFF(pCritSectRo)));
3101
3102	#ifdef VBE_BYTEWISE_IO
3103	if (cb == 1)
3104	{
3105	if (!pThis->fReadVBEIndex)
3106	{
3107	*pu32 = (vbe_ioport_read_index(pThis, offPort) >> 8) & 0xFF;
3108	pThis->fReadVBEIndex = true;
3109	return VINF_SUCCESS;
3110	}
3111	*pu32 = vbe_ioport_read_index(pThis, offPort) & 0xFF;
3112	pThis->fReadVBEIndex = false;
3113	return VINF_SUCCESS;
3114	}
3115	#endif
3116	if (cb == 2)
3117	{
3118	*pu32 = vbe_ioport_read_index(pThis, offPort);
3119	return VINF_SUCCESS;
3120	}
3121	AssertMsgFailed(("vgaIoPortReadVbeIndex: offPort=%#x cb=%d\n", offPort, cb));
3122	return VERR_IOM_IOPORT_UNUSED;
3123	}
3124
3125	#if defined(VBOX_WITH_HGSMI) && defined(IN_RING3)
3126
3127	/**
3128	* @callback_method_impl{FNIOMIOPORTNEWOUT,HGSMI OUT handler.}
3129	*/
3130	static DECLCALLBACK(VBOXSTRICTRC)
3131	vgaR3IOPortHgsmiWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT offPort, uint32_t u32, unsigned cb)
3132	{
3133	PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE);
3134	PVGASTATECC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PVGASTATECC);
3135	Assert(PDMDevHlpCritSectIsOwner(pDevIns, pDevIns->CTX_SUFF(pCritSectRo)));
3136	LogFlowFunc(("offPort=0x%x u32=0x%x cb=%u\n", offPort, u32, cb));
3137
3138	NOREF(pvUser);
3139
3140	if (cb == 4)
3141	{
3142	switch (offPort)
3143	{
3144	case VGA_PORT_HGSMI_HOST: /* Host */
3145	{
3146	# if defined(VBOX_WITH_VIDEOHWACCEL) \|\| defined(VBOX_WITH_VDMA) \|\| defined(VBOX_WITH_WDDM)
3147	if (u32 == HGSMIOFFSET_VOID)
3148	{
3149	PDMDevHlpCritSectEnter(pDevIns, &pThis->CritSectIRQ, VERR_SEM_BUSY);
3150
3151	if (pThis->fu32PendingGuestFlags == 0)
3152	{
3153	PDMDevHlpPCISetIrqNoWait(pDevIns, 0, PDM_IRQ_LEVEL_LOW);
3154	HGSMIClearHostGuestFlags(pThisCC->pHGSMI,
3155	HGSMIHOSTFLAGS_IRQ
3156	\| HGSMIHOSTFLAGS_VSYNC
3157	\| HGSMIHOSTFLAGS_HOTPLUG
3158	\| HGSMIHOSTFLAGS_CURSOR_CAPABILITIES);
3159	}
3160	else
3161	{
3162	HGSMISetHostGuestFlags(pThisCC->pHGSMI, HGSMIHOSTFLAGS_IRQ \| pThis->fu32PendingGuestFlags);
3163	pThis->fu32PendingGuestFlags = 0;
3164	/* Keep the IRQ unchanged. */
3165	}
3166
3167	PDMDevHlpCritSectLeave(pDevIns, &pThis->CritSectIRQ);
3168	}
3169	else
3170	# endif
3171	{
3172	HGSMIHostWrite(pThisCC->pHGSMI, u32);
3173	}
3174	break;
3175	}
3176
3177	case VGA_PORT_HGSMI_GUEST: /* Guest */
3178	HGSMIGuestWrite(pThisCC->pHGSMI, u32);
3179	break;
3180
3181	default:
3182	# ifdef DEBUG_sunlover
3183	AssertMsgFailed(("vgaR3IOPortHgsmiWrite: offPort=%#x cb=%d u32=%#x\n", offPort, cb, u32));
3184	# endif
3185	break;
3186	}
3187	}
3188	else
3189	{
3190	/** @todo r=bird: According to Ralf Brown, one and two byte accesses to the
3191	* 0x3b0-0x3b1 and 0x3b2-0x3b3 I/O port pairs should work the same as
3192	* 0x3b4-0x3b5 (MDA CRT control). */
3193	Log(("vgaR3IOPortHgsmiWrite: offPort=%#x cb=%d u32=%#x - possible valid MDA CRT access\n", offPort, cb, u32));
3194	# ifdef DEBUG_sunlover
3195	AssertMsgFailed(("vgaR3IOPortHgsmiWrite: offPort=%#x cb=%d u32=%#x\n", offPort, cb, u32));
3196	# endif
3197	STAM_REL_COUNTER_INC(&pThis->StatHgsmiMdaCgaAccesses);
3198	}
3199
3200	return VINF_SUCCESS;
3201	}
3202
3203
3204	/**
3205	* @callback_method_impl{FNIOMIOPORTNEWOUT,HGSMI IN handler.}
3206	*/
3207	static DECLCALLBACK(VBOXSTRICTRC)
3208	vgaR3IOPortHgmsiRead(PPDMDEVINS pDevIns, void pvUser, RTIOPORT offPort, uint32_t pu32, unsigned cb)
3209	{
3210	PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE);
3211	PVGASTATECC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PVGASTATECC);
3212	Assert(PDMDevHlpCritSectIsOwner(pDevIns, pDevIns->CTX_SUFF(pCritSectRo)));
3213	LogFlowFunc(("offPort=0x%x cb=%d\n", offPort, cb));
3214
3215	NOREF(pvUser);
3216
3217	VBOXSTRICTRC rc = VINF_SUCCESS;
3218	if (cb == 4)
3219	{
3220	switch (offPort)
3221	{
3222	case VGA_PORT_HGSMI_HOST: /* Host */
3223	*pu32 = HGSMIHostRead(pThisCC->pHGSMI);
3224	break;
3225	case VGA_PORT_HGSMI_GUEST: /* Guest */
3226	*pu32 = HGSMIGuestRead(pThisCC->pHGSMI);
3227	break;
3228	default:
3229	rc = VERR_IOM_IOPORT_UNUSED;
3230	break;
3231	}
3232	}
3233	else
3234	{
3235	/** @todo r=bird: According to Ralf Brown, one and two byte accesses to the
3236	* 0x3b0-0x3b1 and 0x3b2-0x3b3 I/O port pairs should work the same as
3237	* 0x3b4-0x3b5 (MDA CRT control). */
3238	Log(("vgaR3IOPortHgmsiRead: offPort=%#x cb=%d - possible valid MDA CRT access\n", offPort, cb));
3239	STAM_REL_COUNTER_INC(&pThis->StatHgsmiMdaCgaAccesses);
3240	rc = VERR_IOM_IOPORT_UNUSED;
3241	}
3242
3243	return rc;
3244	}
3245
3246	#endif /* VBOX_WITH_HGSMI && IN_RING3*/
3247
3248
3249
3250
3251	/* -=-=-=-=-=- All Contexts -=-=-=-=-=- */
3252
3253	/**
3254	* @internal. For use inside VGAGCMemoryFillWrite only.
3255	* Macro for apply logical operation and bit mask.
3256	*/
3257	#define APPLY_LOGICAL_AND_MASK(pThis, val, bit_mask) \
3258	/* apply logical operation */ \
3259	switch (pThis->gr[3] >> 3)\
3260	{ \
3261	case 0: \
3262	default:\
3263	/* nothing to do */ \
3264	break; \
3265	case 1: \
3266	/* and */ \
3267	val &= pThis->latch; \
3268	break; \
3269	case 2: \
3270	/* or */ \
3271	val \|= pThis->latch; \
3272	break; \
3273	case 3: \
3274	/* xor */ \
3275	val ^= pThis->latch; \
3276	break; \
3277	} \
3278	/* apply bit mask */ \
3279	val = (val & bit_mask) \| (pThis->latch & ~bit_mask)
3280
3281	/**
3282	* Legacy VGA memory (0xa0000 - 0xbffff) write hook, to be called from IOM and from the inside of VGADeviceGC.cpp.
3283	* This is the advanced version of vga_mem_writeb function.
3284	*
3285	* @returns VBox status code.
3286	* @param pThis The shared VGA instance data.
3287	* @param pThisCC The VGA instance data for the current context.
3288	* @param pvUser User argument - ignored.
3289	* @param GCPhysAddr Physical address of memory to write.
3290	* @param u32Item Data to write, up to 4 bytes.
3291	* @param cbItem Size of data Item, only 1/2/4 bytes is allowed for now.
3292	* @param cItems Number of data items to write.
3293	*/
3294	static int vgaInternalMMIOFill(PVGASTATE pThis, PVGASTATECC pThisCC, void *pvUser, RTGCPHYS GCPhysAddr,
3295	uint32_t u32Item, unsigned cbItem, unsigned cItems)
3296	{
3297	uint32_t b;
3298	uint32_t write_mask, bit_mask, set_mask;
3299	uint32_t aVal[4];
3300	unsigned i;
3301	NOREF(pvUser);
3302
3303	for (i = 0; i < cbItem; i++)
3304	{
3305	aVal[i] = u32Item & 0xff;
3306	u32Item >>= 8;
3307	}
3308
3309	/* convert to VGA memory offset */
3310	/// @todo add check for the end of region
3311	GCPhysAddr &= 0x1ffff;
3312	switch((pThis->gr[6] >> 2) & 3) {
3313	case 0:
3314	break;
3315	case 1:
3316	if (GCPhysAddr >= 0x10000)
3317	return VINF_SUCCESS;
3318	GCPhysAddr += pThis->bank_offset;
3319	break;
3320	case 2:
3321	GCPhysAddr -= 0x10000;
3322	if (GCPhysAddr >= 0x8000)
3323	return VINF_SUCCESS;
3324	break;
3325	default:
3326	case 3:
3327	GCPhysAddr -= 0x18000;
3328	if (GCPhysAddr >= 0x8000)
3329	return VINF_SUCCESS;
3330	break;
3331	}
3332
3333	if (pThis->sr[4] & 0x08) {
3334	/* chain 4 mode : simplest access */
3335	VERIFY_VRAM_WRITE_OFF_RETURN(pThis, GCPhysAddr + cItems * cbItem - 1);
3336
3337	while (cItems-- > 0)
3338	for (i = 0; i < cbItem; i++)
3339	{
3340	if (pThis->sr[2] & (1 << (GCPhysAddr & 3)))
3341	{
3342	pThisCC->pbVRam[GCPhysAddr] = aVal[i];
3343	vgaR3MarkDirty(pThis, GCPhysAddr);
3344	}
3345	GCPhysAddr++;
3346	}
3347	} else if (pThis->gr[5] & 0x10) {
3348	/* odd/even mode (aka text mode mapping) */
3349	VERIFY_VRAM_WRITE_OFF_RETURN(pThis, (GCPhysAddr + cItems * cbItem) * 4 - 1);
3350	while (cItems-- > 0)
3351	for (i = 0; i < cbItem; i++)
3352	{
3353	unsigned plane = (pThis->gr[4] & 2) \| (GCPhysAddr & 1);
3354	if (pThis->sr[2] & (1 << plane)) {
3355	RTGCPHYS PhysAddr2 = ((GCPhysAddr & ~1) * 4) \| plane;
3356	pThisCC->pbVRam[PhysAddr2] = aVal[i];
3357	vgaR3MarkDirty(pThis, PhysAddr2);
3358	}
3359	GCPhysAddr++;
3360	}
3361	} else {
3362	/* standard VGA latched access */
3363	VERIFY_VRAM_WRITE_OFF_RETURN(pThis, (GCPhysAddr + cItems * cbItem) * 4 - 1);
3364
3365	switch(pThis->gr[5] & 3) {
3366	default:
3367	case 0:
3368	/* rotate */
3369	b = pThis->gr[3] & 7;
3370	bit_mask = pThis->gr[8];
3371	bit_mask \|= bit_mask << 8;
3372	bit_mask \|= bit_mask << 16;
3373	set_mask = mask16[pThis->gr[1]];
3374
3375	for (i = 0; i < cbItem; i++)
3376	{
3377	aVal[i] = ((aVal[i] >> b) \| (aVal[i] << (8 - b))) & 0xff;
3378	aVal[i] \|= aVal[i] << 8;
3379	aVal[i] \|= aVal[i] << 16;
3380
3381	/* apply set/reset mask */
3382	aVal[i] = (aVal[i] & ~set_mask) \| (mask16[pThis->gr[0]] & set_mask);
3383
3384	APPLY_LOGICAL_AND_MASK(pThis, aVal[i], bit_mask);
3385	}
3386	break;
3387	case 1:
3388	for (i = 0; i < cbItem; i++)
3389	aVal[i] = pThis->latch;
3390	break;
3391	case 2:
3392	bit_mask = pThis->gr[8];
3393	bit_mask \|= bit_mask << 8;
3394	bit_mask \|= bit_mask << 16;
3395	for (i = 0; i < cbItem; i++)
3396	{
3397	aVal[i] = mask16[aVal[i] & 0x0f];
3398
3399	APPLY_LOGICAL_AND_MASK(pThis, aVal[i], bit_mask);
3400	}
3401	break;
3402	case 3:
3403	/* rotate */
3404	b = pThis->gr[3] & 7;
3405
3406	for (i = 0; i < cbItem; i++)
3407	{
3408	aVal[i] = (aVal[i] >> b) \| (aVal[i] << (8 - b));
3409	bit_mask = pThis->gr[8] & aVal[i];
3410	bit_mask \|= bit_mask << 8;
3411	bit_mask \|= bit_mask << 16;
3412	aVal[i] = mask16[pThis->gr[0]];
3413
3414	APPLY_LOGICAL_AND_MASK(pThis, aVal[i], bit_mask);
3415	}
3416	break;
3417	}
3418
3419	/* mask data according to sr[2] */
3420	write_mask = mask16[pThis->sr[2]];
3421
3422	/* actually write data */
3423	if (cbItem == 1)
3424	{
3425	/* The most frequently case is 1 byte I/O. */
3426	while (cItems-- > 0)
3427	{
3428	((uint32_t )pThisCC->pbVRam)[GCPhysAddr] = (((uint32_t )pThisCC->pbVRam)[GCPhysAddr] & ~write_mask) \| (aVal[0] & write_mask);
3429	vgaR3MarkDirty(pThis, GCPhysAddr * 4);
3430	GCPhysAddr++;
3431	}
3432	}
3433	else if (cbItem == 2)
3434	{
3435	/* The second case is 2 bytes I/O. */
3436	while (cItems-- > 0)
3437	{
3438	((uint32_t )pThisCC->pbVRam)[GCPhysAddr] = (((uint32_t )pThisCC->pbVRam)[GCPhysAddr] & ~write_mask) \| (aVal[0] & write_mask);
3439	vgaR3MarkDirty(pThis, GCPhysAddr * 4);
3440	GCPhysAddr++;
3441
3442	((uint32_t )pThisCC->pbVRam)[GCPhysAddr] = (((uint32_t )pThisCC->pbVRam)[GCPhysAddr] & ~write_mask) \| (aVal[1] & write_mask);
3443	vgaR3MarkDirty(pThis, GCPhysAddr * 4);
3444	GCPhysAddr++;
3445	}
3446	}
3447	else
3448	{
3449	/* And the rest is 4 bytes. */
3450	Assert(cbItem == 4);
3451	while (cItems-- > 0)
3452	for (i = 0; i < cbItem; i++)
3453	{
3454	((uint32_t )pThisCC->pbVRam)[GCPhysAddr] = (((uint32_t )pThisCC->pbVRam)[GCPhysAddr] & ~write_mask) \| (aVal[i] & write_mask);
3455	vgaR3MarkDirty(pThis, GCPhysAddr * 4);
3456	GCPhysAddr++;
3457	}
3458	}
3459	}
3460	return VINF_SUCCESS;
3461	}
3462
3463	#undef APPLY_LOGICAL_AND_MASK
3464
3465	/**
3466	* @callback_method_impl{FNIOMMMIONEWFILL,
3467	* Legacy VGA memory (0xa0000 - 0xbffff) write hook\, to be called from IOM and
3468	* from the inside of VGADeviceGC.cpp. This is the advanced version of
3469	* vga_mem_writeb function.}
3470	*/
3471	static DECLCALLBACK(VBOXSTRICTRC)
3472	vgaMmioFill(PPDMDEVINS pDevIns, void *pvUser, RTGCPHYS off, uint32_t u32Item, unsigned cbItem, unsigned cItems)
3473	{
3474	PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE);
3475	PVGASTATECC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PVGASTATECC);
3476	Assert(PDMDevHlpCritSectIsOwner(pDevIns, pDevIns->CTX_SUFF(pCritSectRo)));
3477
3478	return vgaInternalMMIOFill(pThis, pThisCC, pvUser, off, u32Item, cbItem, cItems);
3479	}
3480
3481
3482	/**
3483	* @callback_method_impl{FNIOMMMIONEWREAD,
3484	* Legacy VGA memory (0xa0000 - 0xbffff) read hook\, to be called from IOM.}
3485	*/
3486	static DECLCALLBACK(VBOXSTRICTRC) vgaMmioRead(PPDMDEVINS pDevIns, void pvUser, RTGCPHYS off, void pv, unsigned cb)
3487	{
3488	PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE);
3489	PVGASTATECC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PVGASTATECC);
3490	STAM_PROFILE_START(&pThis->CTX_MID_Z(Stat,MemoryRead), a);
3491	Assert(PDMDevHlpCritSectIsOwner(pDevIns, pDevIns->CTX_SUFF(pCritSectRo)));
3492	NOREF(pvUser);
3493
3494	int rc = VINF_SUCCESS;
3495	switch (cb)
3496	{
3497	case 1:
3498	(uint8_t )pv = vga_mem_readb(pDevIns, pThis, pThisCC, off, &rc);
3499	break;
3500	case 2:
3501	/** @todo This and the wider accesses maybe misbehave when accessing bytes
3502	* crossing the 512KB VRAM boundrary if the access is handled in
3503	* ring-0 and operating in latched mode. */
3504	(uint16_t )pv = vga_mem_readb(pDevIns, pThis, pThisCC, off, &rc)
3505	\| (vga_mem_readb(pDevIns, pThis, pThisCC, off + 1, &rc) << 8);
3506	break;
3507	case 4:
3508	(uint32_t )pv = vga_mem_readb(pDevIns, pThis, pThisCC, off, &rc)
3509	\| (vga_mem_readb(pDevIns, pThis, pThisCC, off + 1, &rc) << 8)
3510	\| (vga_mem_readb(pDevIns, pThis, pThisCC, off + 2, &rc) << 16)
3511	\| (vga_mem_readb(pDevIns, pThis, pThisCC, off + 3, &rc) << 24);
3512	break;
3513
3514	case 8:
3515	(uint64_t )pv = (uint64_t)vga_mem_readb(pDevIns, pThis, pThisCC, off, &rc)
3516	\| ((uint64_t)vga_mem_readb(pDevIns, pThis, pThisCC, off + 1, &rc) << 8)
3517	\| ((uint64_t)vga_mem_readb(pDevIns, pThis, pThisCC, off + 2, &rc) << 16)
3518	\| ((uint64_t)vga_mem_readb(pDevIns, pThis, pThisCC, off + 3, &rc) << 24)
3519	\| ((uint64_t)vga_mem_readb(pDevIns, pThis, pThisCC, off + 4, &rc) << 32)
3520	\| ((uint64_t)vga_mem_readb(pDevIns, pThis, pThisCC, off + 5, &rc) << 40)
3521	\| ((uint64_t)vga_mem_readb(pDevIns, pThis, pThisCC, off + 6, &rc) << 48)
3522	\| ((uint64_t)vga_mem_readb(pDevIns, pThis, pThisCC, off + 7, &rc) << 56);
3523	break;
3524
3525	default:
3526	{
3527	uint8_t pbData = (uint8_t )pv;
3528	while (cb-- > 0)
3529	{
3530	*pbData++ = vga_mem_readb(pDevIns, pThis, pThisCC, off++, &rc);
3531	if (RT_UNLIKELY(rc != VINF_SUCCESS))
3532	break;
3533	}
3534	}
3535	}
3536
3537	STAM_PROFILE_STOP(&pThis->CTX_MID_Z(Stat,MemoryRead), a);
3538	return rc;
3539	}
3540
3541	/**
3542	* @callback_method_impl{FNIOMMMIONEWWRITE,
3543	* Legacy VGA memory (0xa0000 - 0xbffff) write hook\, to be called from IOM.}
3544	*/
3545	static DECLCALLBACK(VBOXSTRICTRC) vgaMmioWrite(PPDMDEVINS pDevIns, void pvUser, RTGCPHYS off, void const pv, unsigned cb)
3546	{
3547	PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE);
3548	PVGASTATECC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PVGASTATECC);
3549	uint8_t const pbSrc = (uint8_t const )pv;
3550	NOREF(pvUser);
3551	STAM_PROFILE_START(&pThis->CTX_MID_Z(Stat,MemoryWrite), a);
3552	Assert(PDMDevHlpCritSectIsOwner(pDevIns, pDevIns->CTX_SUFF(pCritSectRo)));
3553
3554	VBOXSTRICTRC rc;
3555	switch (cb)
3556	{
3557	case 1:
3558	rc = vga_mem_writeb(pDevIns, pThis, pThisCC, off, *pbSrc);
3559	break;
3560	#if 1
3561	case 2:
3562	rc = vga_mem_writeb(pDevIns, pThis, pThisCC, off + 0, pbSrc[0]);
3563	if (RT_LIKELY(rc == VINF_SUCCESS))
3564	rc = vga_mem_writeb(pDevIns, pThis, pThisCC, off + 1, pbSrc[1]);
3565	break;
3566	case 4:
3567	rc = vga_mem_writeb(pDevIns, pThis, pThisCC, off + 0, pbSrc[0]);
3568	if (RT_LIKELY(rc == VINF_SUCCESS))
3569	rc = vga_mem_writeb(pDevIns, pThis, pThisCC, off + 1, pbSrc[1]);
3570	if (RT_LIKELY(rc == VINF_SUCCESS))
3571	rc = vga_mem_writeb(pDevIns, pThis, pThisCC, off + 2, pbSrc[2]);
3572	if (RT_LIKELY(rc == VINF_SUCCESS))
3573	rc = vga_mem_writeb(pDevIns, pThis, pThisCC, off + 3, pbSrc[3]);
3574	break;
3575	case 8:
3576	rc = vga_mem_writeb(pDevIns, pThis, pThisCC, off + 0, pbSrc[0]);
3577	if (RT_LIKELY(rc == VINF_SUCCESS))
3578	rc = vga_mem_writeb(pDevIns, pThis, pThisCC, off + 1, pbSrc[1]);
3579	if (RT_LIKELY(rc == VINF_SUCCESS))
3580	rc = vga_mem_writeb(pDevIns, pThis, pThisCC, off + 2, pbSrc[2]);
3581	if (RT_LIKELY(rc == VINF_SUCCESS))
3582	rc = vga_mem_writeb(pDevIns, pThis, pThisCC, off + 3, pbSrc[3]);
3583	if (RT_LIKELY(rc == VINF_SUCCESS))
3584	rc = vga_mem_writeb(pDevIns, pThis, pThisCC, off + 4, pbSrc[4]);
3585	if (RT_LIKELY(rc == VINF_SUCCESS))
3586	rc = vga_mem_writeb(pDevIns, pThis, pThisCC, off + 5, pbSrc[5]);
3587	if (RT_LIKELY(rc == VINF_SUCCESS))
3588	rc = vga_mem_writeb(pDevIns, pThis, pThisCC, off + 6, pbSrc[6]);
3589	if (RT_LIKELY(rc == VINF_SUCCESS))
3590	rc = vga_mem_writeb(pDevIns, pThis, pThisCC, off + 7, pbSrc[7]);
3591	break;
3592	#else
3593	case 2:
3594	rc = vgaMmioFill(pDevIns, off, (uint16_t )pv, 2, 1);
3595	break;
3596	case 4:
3597	rc = vgaMmioFill(pDevIns, off, (uint32_t )pv, 4, 1);
3598	break;
3599	case 8:
3600	rc = vgaMmioFill(pDevIns, off, (uint64_t )pv, 8, 1);
3601	break;
3602	#endif
3603	default:
3604	rc = VINF_SUCCESS;
3605	while (cb-- > 0 && rc == VINF_SUCCESS)
3606	rc = vga_mem_writeb(pDevIns, pThis, pThisCC, off++, *pbSrc++);
3607	break;
3608
3609	}
3610	STAM_PROFILE_STOP(&pThis->CTX_MID_Z(Stat,MemoryWrite), a);
3611	return rc;
3612	}
3613
3614
3615	/**
3616	* Handle LFB access.
3617	*
3618	* @returns Strict VBox status code.
3619	* @param pVM VM handle.
3620	* @param pDevIns The device instance.
3621	* @param pThis The shared VGA instance data.
3622	* @param GCPhys The access physical address.
3623	* @param GCPtr The access virtual address (only GC).
3624	*/
3625	static VBOXSTRICTRC vgaLFBAccess(PVMCC pVM, PPDMDEVINS pDevIns, PVGASTATE pThis, RTGCPHYS GCPhys, RTGCPTR GCPtr)
3626	{
3627	VBOXSTRICTRC rc = PDMDevHlpCritSectEnter(pDevIns, &pThis->CritSect, VINF_EM_RAW_EMULATE_INSTR);
3628	if (rc == VINF_SUCCESS)
3629	{
3630	/*
3631	* Set page dirty bit.
3632	*/
3633	vgaR3MarkDirty(pThis, GCPhys - pThis->GCPhysVRAM);
3634	pThis->fLFBUpdated = true;
3635
3636	/*
3637	* Turn of the write handler for this particular page and make it R/W.
3638	* Then return telling the caller to restart the guest instruction.
3639	* ASSUME: the guest always maps video memory RW.
3640	*/
3641	rc = PGMHandlerPhysicalPageTempOff(pVM, pThis->GCPhysVRAM, GCPhys);
3642	if (RT_SUCCESS(rc))
3643	{
3644	#ifndef IN_RING3
3645	rc = PGMShwMakePageWritable(PDMDevHlpGetVMCPU(pDevIns), GCPtr,
3646	PGM_MK_PG_IS_MMIO2 \| PGM_MK_PG_IS_WRITE_FAULT);
3647	PDMDevHlpCritSectLeave(pDevIns, &pThis->CritSect);
3648	AssertMsgReturn( rc == VINF_SUCCESS
3649	/* In the SMP case the page table might be removed while we wait for the PGM lock in the trap handler. */
3650	\|\| rc == VERR_PAGE_TABLE_NOT_PRESENT
3651	\|\| rc == VERR_PAGE_NOT_PRESENT,
3652	("PGMShwModifyPage -> GCPtr=%RGv rc=%d\n", GCPtr, VBOXSTRICTRC_VAL(rc)),
3653	rc);
3654	#else /* IN_RING3 - We don't have any virtual page address of the access here. */
3655	PDMDevHlpCritSectLeave(pDevIns, &pThis->CritSect);
3656	Assert(GCPtr == 0);
3657	RT_NOREF1(GCPtr);
3658	#endif
3659	return VINF_SUCCESS;
3660	}
3661
3662	PDMDevHlpCritSectLeave(pDevIns, &pThis->CritSect);
3663	AssertMsgFailed(("PGMHandlerPhysicalPageTempOff -> rc=%d\n", VBOXSTRICTRC_VAL(rc)));
3664	}
3665	return rc;
3666	}
3667
3668
3669	#ifndef IN_RING3
3670	/**
3671	* @callback_method_impl{FNPGMRCPHYSHANDLER, \#PF Handler for VBE LFB access.}
3672	*/
3673	PDMBOTHCBDECL(VBOXSTRICTRC) vgaLbfAccessPfHandler(PVMCC pVM, PVMCPUCC pVCpu, RTGCUINT uErrorCode, PCPUMCTXCORE pRegFrame,
3674	RTGCPTR pvFault, RTGCPHYS GCPhysFault, void *pvUser)
3675	{
3676	PPDMDEVINS pDevIns = (PPDMDEVINS)pvUser;
3677	PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE);
3678	//PVGASTATECC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PVGASTATECC);
3679	Assert(GCPhysFault >= pThis->GCPhysVRAM);
3680	AssertMsg(uErrorCode & X86_TRAP_PF_RW, ("uErrorCode=%#x\n", uErrorCode));
3681	RT_NOREF3(pVCpu, pRegFrame, uErrorCode);
3682
3683	return vgaLFBAccess(pVM, pDevIns, pThis, GCPhysFault, pvFault);
3684	}
3685	#endif /* !IN_RING3 */
3686
3687
3688	/**
3689	* @callback_method_impl{FNPGMPHYSHANDLER,
3690	* VBE LFB write access handler for the dirty tracking.}
3691	*/
3692	PGM_ALL_CB_DECL(VBOXSTRICTRC) vgaLFBAccessHandler(PVMCC pVM, PVMCPUCC pVCpu, RTGCPHYS GCPhys, void *pvPhys,
3693	void *pvBuf, size_t cbBuf, PGMACCESSTYPE enmAccessType,
3694	PGMACCESSORIGIN enmOrigin, void *pvUser)
3695	{
3696	PPDMDEVINS pDevIns = (PPDMDEVINS)pvUser;
3697	PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE);
3698	//PVGASTATECC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PVGASTATECC);
3699	Assert(GCPhys >= pThis->GCPhysVRAM);
3700	RT_NOREF(pVCpu, pvPhys, pvBuf, cbBuf, enmAccessType, enmOrigin);
3701
3702	VBOXSTRICTRC rc = vgaLFBAccess(pVM, pDevIns, pThis, GCPhys, 0);
3703	if (rc == VINF_SUCCESS)
3704	rc = VINF_PGM_HANDLER_DO_DEFAULT;
3705	#ifdef IN_RING3
3706	else
3707	AssertMsg(rc < VINF_SUCCESS, ("rc=%Rrc\n", VBOXSTRICTRC_VAL(rc)));
3708	#endif
3709	return rc;
3710	}
3711
3712
3713	/* -=-=-=-=-=- All rings: VGA BIOS I/Os -=-=-=-=-=- */
3714
3715	/**
3716	* @callback_method_impl{FNIOMIOPORTNEWIN,
3717	* Port I/O Handler for VGA BIOS IN operations.}
3718	*/
3719	static DECLCALLBACK(VBOXSTRICTRC) vgaIoPortReadBios(PPDMDEVINS pDevIns, void pvUser, RTIOPORT offPort, uint32_t pu32, unsigned cb)
3720	{
3721	RT_NOREF(pDevIns, pvUser, offPort, pu32, cb);
3722	return VERR_IOM_IOPORT_UNUSED;
3723	}
3724
3725	/**
3726	* @callback_method_impl{FNIOMIOPORTNEWOUT,
3727	* Port I/O Handler for VGA BIOS IN operations.}
3728	*/
3729	static DECLCALLBACK(VBOXSTRICTRC) vgaIoPortWriteBios(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT offPort, uint32_t u32, unsigned cb)
3730	{
3731	RT_NOREF2(pDevIns, pvUser);
3732	Assert(PDMDevHlpCritSectIsOwner(pDevIns, pDevIns->CTX_SUFF(pCritSectRo)));
3733	Assert(offPort == 0); RT_NOREF(offPort);
3734
3735	/*
3736	* VGA BIOS char printing.
3737	*/
3738	if (cb == 1)
3739	{
3740	#if 0
3741	switch (u32)
3742	{
3743	case '\r': Log(("vgabios: <return>\n")); break;
3744	case '\n': Log(("vgabios: <newline>\n")); break;
3745	case '\t': Log(("vgabios: <tab>\n")); break;
3746	default:
3747	Log(("vgabios: %c\n", u32));
3748	}
3749	#else
3750	static int s_fLastWasNotNewline = 0; /* We are only called in a single-threaded way */
3751	if (s_fLastWasNotNewline == 0)
3752	Log(("vgabios: "));
3753	if (u32 != '\r') /* return - is only sent in conjunction with '\n' */
3754	Log(("%c", u32));
3755	if (u32 == '\n')
3756	s_fLastWasNotNewline = 0;
3757	else
3758	s_fLastWasNotNewline = 1;
3759	#endif
3760	return VINF_SUCCESS;
3761	}
3762
3763	/* not in use. */
3764	return VERR_IOM_IOPORT_UNUSED;
3765	}
3766
3767
3768	/* -=-=-=-=-=- Ring 3 -=-=-=-=-=- */
3769
3770	#ifdef IN_RING3
3771
3772	/**
3773	* @callback_method_impl{FNIOMIOPORTNEWOUT,
3774	* Port I/O Handler for VBE Extra OUT operations.}
3775	*/
3776	static DECLCALLBACK(VBOXSTRICTRC)
3777	vbeR3IOPortWriteVbeExtra(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT offPort, uint32_t u32, unsigned cb)
3778	{
3779	PVGASTATECC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PVGASTATECC);
3780	Assert(PDMDevHlpCritSectIsOwner(pDevIns, pDevIns->CTX_SUFF(pCritSectRo)));
3781	RT_NOREF(offPort, pvUser);
3782
3783	if (cb == 2)
3784	{
3785	Log(("vbeR3IOPortWriteVbeExtra: addr=%#RX32\n", u32));
3786	pThisCC->u16VBEExtraAddress = u32;
3787	}
3788	else
3789	Log(("vbeR3IOPortWriteVbeExtra: Ignoring invalid cb=%d writes to the VBE Extra port!!!\n", cb));
3790
3791	return VINF_SUCCESS;
3792	}
3793
3794
3795	/**
3796	* @callback_method_impl{FNIOMIOPORTNEWIN,
3797	* Port I/O Handler for VBE Extra IN operations.}
3798	*/
3799	static DECLCALLBACK(VBOXSTRICTRC)
3800	vbeR3IoPortReadVbeExtra(PPDMDEVINS pDevIns, void pvUser, RTIOPORT offPort, uint32_t pu32, unsigned cb)
3801	{
3802	PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE);
3803	PVGASTATECC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PVGASTATECC);
3804	Assert(PDMDevHlpCritSectIsOwner(pDevIns, pDevIns->CTX_SUFF(pCritSectRo)));
3805	RT_NOREF(offPort, pvUser);
3806
3807	int rc = VINF_SUCCESS;
3808	if (pThisCC->u16VBEExtraAddress == 0xffff)
3809	{
3810	Log(("vbeR3IoPortReadVbeExtra: Requested number of 64k video banks\n"));
3811	*pu32 = pThis->vram_size / _64K;
3812	}
3813	else if ( pThisCC->u16VBEExtraAddress >= pThisCC->cbVBEExtraData
3814	\|\| pThisCC->u16VBEExtraAddress + cb > pThisCC->cbVBEExtraData)
3815	{
3816	*pu32 = 0;
3817	Log(("vbeR3IoPortReadVbeExtra: Requested address is out of VBE data!!! Address=%#x(%d) cbVBEExtraData=%#x(%d)\n",
3818	pThisCC->u16VBEExtraAddress, pThisCC->u16VBEExtraAddress, pThisCC->cbVBEExtraData, pThisCC->cbVBEExtraData));
3819	}
3820	else
3821	{
3822	RT_UNTRUSTED_VALIDATED_FENCE();
3823	if (cb == 1)
3824	{
3825	*pu32 = pThisCC->pbVBEExtraData[pThisCC->u16VBEExtraAddress] & 0xFF;
3826
3827	Log(("vbeR3IoPortReadVbeExtra: cb=%#x %.*Rhxs\n", cb, cb, pu32));
3828	}
3829	else if (cb == 2)
3830	{
3831	*pu32 = pThisCC->pbVBEExtraData[pThisCC->u16VBEExtraAddress]
3832	\| (uint32_t)pThisCC->pbVBEExtraData[pThisCC->u16VBEExtraAddress + 1] << 8;
3833
3834	Log(("vbeR3IoPortReadVbeExtra: cb=%#x %.*Rhxs\n", cb, cb, pu32));
3835	}
3836	else
3837	{
3838	Log(("vbeR3IoPortReadVbeExtra: Invalid cb=%d read from the VBE Extra port!!!\n", cb));
3839	rc = VERR_IOM_IOPORT_UNUSED;
3840	}
3841	}
3842
3843	return rc;
3844	}
3845
3846
3847	/**
3848	* Parse the logo bitmap data at init time.
3849	*
3850	* @returns VBox status code.
3851	*
3852	* @param pThisCC The VGA instance data for ring-3.
3853	*/
3854	static int vbeR3ParseBitmap(PVGASTATECC pThisCC)
3855	{
3856	/*
3857	* Get bitmap header data
3858	*/
3859	PBMPFILEHDR pFileHdr = (PBMPFILEHDR)(pThisCC->pbLogo + sizeof(LOGOHDR));
3860	PBMPWIN3XINFOHDR pCoreHdr = (PBMPWIN3XINFOHDR)(pThisCC->pbLogo + sizeof(LOGOHDR) + sizeof(BMPFILEHDR));
3861
3862	if (pFileHdr->uType == BMP_HDR_MAGIC)
3863	{
3864	switch (pCoreHdr->cbSize)
3865	{
3866	case BMP_HDR_SIZE_OS21:
3867	{
3868	PBMPOS2COREHDR pOs2Hdr = (PBMPOS2COREHDR)pCoreHdr;
3869	pThisCC->cxLogo = pOs2Hdr->uWidth;
3870	pThisCC->cyLogo = pOs2Hdr->uHeight;
3871	pThisCC->cLogoPlanes = pOs2Hdr->cPlanes;
3872	pThisCC->cLogoBits = pOs2Hdr->cBits;
3873	pThisCC->LogoCompression = BMP_COMPRESSION_TYPE_NONE;
3874	pThisCC->cLogoUsedColors = 0;
3875	break;
3876	}
3877
3878	case BMP_HDR_SIZE_OS22:
3879	{
3880	PBMPOS2COREHDR2 pOs22Hdr = (PBMPOS2COREHDR2)pCoreHdr;
3881	pThisCC->cxLogo = pOs22Hdr->uWidth;
3882	pThisCC->cyLogo = pOs22Hdr->uHeight;
3883	pThisCC->cLogoPlanes = pOs22Hdr->cPlanes;
3884	pThisCC->cLogoBits = pOs22Hdr->cBits;
3885	pThisCC->LogoCompression = pOs22Hdr->enmCompression;
3886	pThisCC->cLogoUsedColors = pOs22Hdr->cClrUsed;
3887	break;
3888	}
3889
3890	case BMP_HDR_SIZE_WIN3X:
3891	pThisCC->cxLogo = pCoreHdr->uWidth;
3892	pThisCC->cyLogo = pCoreHdr->uHeight;
3893	pThisCC->cLogoPlanes = pCoreHdr->cPlanes;
3894	pThisCC->cLogoBits = pCoreHdr->cBits;
3895	pThisCC->LogoCompression = pCoreHdr->enmCompression;
3896	pThisCC->cLogoUsedColors = pCoreHdr->cClrUsed;
3897	break;
3898
3899	default:
3900	AssertLogRelMsgFailedReturn(("Unsupported bitmap header size %u.\n", pCoreHdr->cbSize),
3901	VERR_INVALID_PARAMETER);
3902	break;
3903	}
3904
3905	AssertLogRelMsgReturn(pThisCC->cxLogo <= LOGO_MAX_WIDTH && pThisCC->cyLogo <= LOGO_MAX_HEIGHT,
3906	("Bitmap %ux%u is too big.\n", pThisCC->cxLogo, pThisCC->cyLogo),
3907	VERR_INVALID_PARAMETER);
3908
3909	AssertLogRelMsgReturn(pThisCC->cLogoPlanes == 1,
3910	("Bitmap planes %u != 1.\n", pThisCC->cLogoPlanes),
3911	VERR_INVALID_PARAMETER);
3912
3913	AssertLogRelMsgReturn(pThisCC->cLogoBits == 4 \|\| pThisCC->cLogoBits == 8 \|\| pThisCC->cLogoBits == 24,
3914	("Unsupported %u depth.\n", pThisCC->cLogoBits),
3915	VERR_INVALID_PARAMETER);
3916
3917	AssertLogRelMsgReturn(pThisCC->cLogoUsedColors <= 256,
3918	("Unsupported %u colors.\n", pThisCC->cLogoUsedColors),
3919	VERR_INVALID_PARAMETER);
3920
3921	AssertLogRelMsgReturn(pThisCC->LogoCompression == BMP_COMPRESSION_TYPE_NONE,
3922	("Unsupported %u compression.\n", pThisCC->LogoCompression),
3923	VERR_INVALID_PARAMETER);
3924
3925	/*
3926	* Read bitmap palette
3927	*/
3928	if (!pThisCC->cLogoUsedColors)
3929	pThisCC->cLogoPalEntries = 1 << (pThisCC->cLogoPlanes * pThisCC->cLogoBits);
3930	else
3931	pThisCC->cLogoPalEntries = pThisCC->cLogoUsedColors;
3932
3933	if (pThisCC->cLogoPalEntries)
3934	{
3935	const uint8_t pbPal = pThisCC->pbLogo + sizeof(LOGOHDR) + sizeof(BMPFILEHDR) + pCoreHdr->cbSize; / ASSUMES Size location (safe) */
3936
3937	for (uint16_t i = 0; i < pThisCC->cLogoPalEntries; i++)
3938	{
3939	uint16_t j;
3940	uint32_t u32Pal = 0;
3941
3942	for (j = 0; j < 3; j++)
3943	{
3944	uint8_t b = *pbPal++;
3945	u32Pal <<= 8;
3946	u32Pal \|= b;
3947	}
3948
3949	pbPal++; /* skip unused byte */
3950	pThisCC->au32LogoPalette[i] = u32Pal;
3951	}
3952	}
3953
3954	/*
3955	* Bitmap data offset
3956	*/
3957	pThisCC->pbLogoBitmap = pThisCC->pbLogo + sizeof(LOGOHDR) + pFileHdr->offBits;
3958	}
3959	else
3960	AssertLogRelMsgFailedReturn(("Not a BMP file.\n"), VERR_INVALID_PARAMETER);
3961
3962	return VINF_SUCCESS;
3963	}
3964
3965
3966	/**
3967	* Show logo bitmap data.
3968	*
3969	* @returns VBox status code.
3970	*
3971	* @param cBits Logo depth.
3972	* @param xLogo Logo X position.
3973	* @param yLogo Logo Y position.
3974	* @param cxLogo Logo width.
3975	* @param cyLogo Logo height.
3976	* @param fInverse True if the bitmask is black on white (only for 1bpp)
3977	* @param iStep Fade in/fade out step.
3978	* @param pu32Palette Palette data.
3979	* @param pbSrc Source buffer.
3980	* @param pbDst Destination buffer.
3981	*/
3982	static void vbeR3ShowBitmap(uint16_t cBits, uint16_t xLogo, uint16_t yLogo, uint16_t cxLogo, uint16_t cyLogo,
3983	bool fInverse, uint8_t iStep, const uint32_t pu32Palette, const uint8_t pbSrc, uint8_t *pbDst)
3984	{
3985	uint16_t i;
3986	size_t cbPadBytes = 0;
3987	size_t cbLineDst = LOGO_MAX_WIDTH * 4;
3988	uint16_t cyLeft = cyLogo;
3989
3990	pbDst += xLogo * 4 + yLogo * cbLineDst;
3991
3992	switch (cBits)
3993	{
3994	case 1:
3995	pbDst += cyLogo * cbLineDst;
3996	cbPadBytes = 0;
3997	break;
3998
3999	case 4:
4000	if (((cxLogo % 8) == 0) \|\| ((cxLogo % 8) > 6))
4001	cbPadBytes = 0;
4002	else if ((cxLogo % 8) <= 2)
4003	cbPadBytes = 3;
4004	else if ((cxLogo % 8) <= 4)
4005	cbPadBytes = 2;
4006	else
4007	cbPadBytes = 1;
4008	break;
4009
4010	case 8:
4011	cbPadBytes = ((cxLogo % 4) == 0) ? 0 : (4 - (cxLogo % 4));
4012	break;
4013
4014	case 24:
4015	cbPadBytes = cxLogo % 4;
4016	break;
4017	}
4018
4019	uint8_t j = 0, c = 0;
4020
4021	while (cyLeft-- > 0)
4022	{
4023	uint8_t *pbTmpDst = pbDst;
4024
4025	if (cBits != 1)
4026	j = 0;
4027
4028	for (i = 0; i < cxLogo; i++)
4029	{
4030	switch (cBits)
4031	{
4032	case 1:
4033	{
4034	if (!j)
4035	c = *pbSrc++;
4036
4037	if (c & 1)
4038	{
4039	if (fInverse)
4040	{
4041	*pbTmpDst++ = 0;
4042	*pbTmpDst++ = 0;
4043	*pbTmpDst++ = 0;
4044	pbTmpDst++;
4045	}
4046	else
4047	{
4048	uint8_t pix = 0xFF * iStep / LOGO_SHOW_STEPS;
4049	*pbTmpDst++ = pix;
4050	*pbTmpDst++ = pix;
4051	*pbTmpDst++ = pix;
4052	pbTmpDst++;
4053	}
4054	}
4055	else
4056	pbTmpDst += 4;
4057	c >>= 1;
4058	j = (j + 1) % 8;
4059	break;
4060	}
4061
4062	case 4:
4063	{
4064	if (!j)
4065	c = *pbSrc++;
4066
4067	uint8_t pix = (c >> 4) & 0xF;
4068	c <<= 4;
4069
4070	uint32_t u32Pal = pu32Palette[pix];
4071
4072	pix = (u32Pal >> 16) & 0xFF;
4073	pbTmpDst++ = pix iStep / LOGO_SHOW_STEPS;
4074	pix = (u32Pal >> 8) & 0xFF;
4075	pbTmpDst++ = pix iStep / LOGO_SHOW_STEPS;
4076	pix = u32Pal & 0xFF;
4077	pbTmpDst++ = pix iStep / LOGO_SHOW_STEPS;
4078	pbTmpDst++;
4079
4080	j = (j + 1) % 2;
4081	break;
4082	}
4083
4084	case 8:
4085	{
4086	uint32_t u32Pal = pu32Palette[*pbSrc++];
4087
4088	uint8_t pix = (u32Pal >> 16) & 0xFF;
4089	pbTmpDst++ = pix iStep / LOGO_SHOW_STEPS;
4090	pix = (u32Pal >> 8) & 0xFF;
4091	pbTmpDst++ = pix iStep / LOGO_SHOW_STEPS;
4092	pix = u32Pal & 0xFF;
4093	pbTmpDst++ = pix iStep / LOGO_SHOW_STEPS;
4094	pbTmpDst++;
4095	break;
4096	}
4097
4098	case 24:
4099	pbTmpDst++ = pbSrc++ * iStep / LOGO_SHOW_STEPS;
4100	pbTmpDst++ = pbSrc++ * iStep / LOGO_SHOW_STEPS;
4101	pbTmpDst++ = pbSrc++ * iStep / LOGO_SHOW_STEPS;
4102	pbTmpDst++;
4103	break;
4104	}
4105	}
4106
4107	pbDst -= cbLineDst;
4108	pbSrc += cbPadBytes;
4109	}
4110	}
4111
4112
4113	/**
4114	* @callback_method_impl{FNIOMIOPORTNEWOUT,
4115	* Port I/O Handler for BIOS Logo OUT operations.}
4116	*/
4117	static DECLCALLBACK(VBOXSTRICTRC)
4118	vbeR3IoPortWriteCmdLogo(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT offPort, uint32_t u32, unsigned cb)
4119	{
4120	PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE);
4121	PVGASTATECC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PVGASTATECC);
4122	RT_NOREF(pvUser, offPort);
4123
4124	Log(("vbeR3IoPortWriteCmdLogo: cb=%d u32=%#04x(%#04d) (byte)\n", cb, u32, u32));
4125
4126	if (cb == 2)
4127	{
4128	/* Get the logo command */
4129	switch (u32 & 0xFF00)
4130	{
4131	case LOGO_CMD_SET_OFFSET:
4132	pThisCC->offLogoData = u32 & 0xFF;
4133	break;
4134
4135	case LOGO_CMD_SHOW_BMP:
4136	{
4137	uint8_t iStep = u32 & 0xFF;
4138	const uint8_t *pbSrc = pThisCC->pbLogoBitmap;
4139	uint8_t *pbDst;
4140	PCLOGOHDR pLogoHdr = (PCLOGOHDR)pThisCC->pbLogo;
4141	uint32_t offDirty = 0;
4142	uint16_t xLogo = (LOGO_MAX_WIDTH - pThisCC->cxLogo) / 2;
4143	uint16_t yLogo = LOGO_MAX_HEIGHT - (LOGO_MAX_HEIGHT - pThisCC->cyLogo) / 2;
4144
4145	/* Check VRAM size */
4146	if (pThis->vram_size < LOGO_MAX_SIZE)
4147	break;
4148
4149	if (pThis->vram_size >= LOGO_MAX_SIZE * 2)
4150	pbDst = pThisCC->pbVRam + LOGO_MAX_SIZE;
4151	else
4152	pbDst = pThisCC->pbVRam;
4153
4154	/* Clear screen - except on power on... */
4155	if (!pThisCC->fLogoClearScreen)
4156	{
4157	/* Clear vram */
4158	uint32_t pu32Dst = (uint32_t )pbDst;
4159	for (int i = 0; i < LOGO_MAX_WIDTH; i++)
4160	for (int j = 0; j < LOGO_MAX_HEIGHT; j++)
4161	*pu32Dst++ = 0;
4162	pThisCC->fLogoClearScreen = true;
4163	}
4164
4165	/* Show the bitmap. */
4166	vbeR3ShowBitmap(pThisCC->cLogoBits, xLogo, yLogo,
4167	pThisCC->cxLogo, pThisCC->cyLogo,
4168	false, iStep, &pThisCC->au32LogoPalette[0],
4169	pbSrc, pbDst);
4170
4171	/* Show the 'Press F12...' text. */
4172	if (pLogoHdr->fu8ShowBootMenu == 2)
4173	vbeR3ShowBitmap(1, LOGO_F12TEXT_X, LOGO_F12TEXT_Y,
4174	LOGO_F12TEXT_WIDTH, LOGO_F12TEXT_HEIGHT,
4175	pThisCC->fBootMenuInverse, iStep, &pThisCC->au32LogoPalette[0],
4176	&g_abLogoF12BootText[0], pbDst);
4177
4178	/* Blit the offscreen buffer. */
4179	if (pThis->vram_size >= LOGO_MAX_SIZE * 2)
4180	{
4181	uint32_t pu32TmpDst = (uint32_t )pThisCC->pbVRam;
4182	uint32_t pu32TmpSrc = (uint32_t )(pThisCC->pbVRam + LOGO_MAX_SIZE);
4183	for (int i = 0; i < LOGO_MAX_WIDTH; i++)
4184	{
4185	for (int j = 0; j < LOGO_MAX_HEIGHT; j++)
4186	pu32TmpDst++ = pu32TmpSrc++;
4187	}
4188	}
4189
4190	/* Set the dirty flags. */
4191	while (offDirty <= LOGO_MAX_SIZE)
4192	{
4193	vgaR3MarkDirty(pThis, offDirty);
4194	offDirty += PAGE_SIZE;
4195	}
4196	break;
4197	}
4198
4199	default:
4200	Log(("vbeR3IoPortWriteCmdLogo: invalid command %d\n", u32));
4201	pThisCC->LogoCommand = LOGO_CMD_NOP;
4202	break;
4203	}
4204
4205	return VINF_SUCCESS;
4206	}
4207
4208	Log(("vbeR3IoPortWriteCmdLogo: Ignoring invalid cb=%d writes to the VBE Extra port!!!\n", cb));
4209	return VINF_SUCCESS;
4210	}
4211
4212
4213	/**
4214	* @callback_method_impl{FNIOMIOPORTIN,
4215	* Port I/O Handler for BIOS Logo IN operations.}
4216	*/
4217	static DECLCALLBACK(VBOXSTRICTRC)
4218	vbeR3IoPortReadCmdLogo(PPDMDEVINS pDevIns, void pvUser, RTIOPORT offPort, uint32_t pu32, unsigned cb)
4219	{
4220	PVGASTATECC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PVGASTATECC);
4221	RT_NOREF(pvUser, offPort);
4222
4223	if (pThisCC->offLogoData + cb > pThisCC->cbLogo)
4224	{
4225	Log(("vbeR3IoPortReadCmdLogo: Requested address is out of Logo data!!! offLogoData=%#x(%d) cbLogo=%#x(%d)\n",
4226	pThisCC->offLogoData, pThisCC->offLogoData, pThisCC->cbLogo, pThisCC->cbLogo));
4227	return VINF_SUCCESS;
4228	}
4229	RT_UNTRUSTED_VALIDATED_FENCE();
4230
4231	PCRTUINT64U p = (PCRTUINT64U)&pThisCC->pbLogo[pThisCC->offLogoData];
4232	switch (cb)
4233	{
4234	case 1: *pu32 = p->au8[0]; break;
4235	case 2: *pu32 = p->au16[0]; break;
4236	case 4: *pu32 = p->au32[0]; break;
4237	//case 8: *pu32 = p->au64[0]; break;
4238	default: AssertFailed(); break;
4239	}
4240	Log(("vbeR3IoPortReadCmdLogo: LogoOffset=%#x(%d) cb=%#x %.*Rhxs\n", pThisCC->offLogoData, pThisCC->offLogoData, cb, cb, pu32));
4241
4242	pThisCC->LogoCommand = LOGO_CMD_NOP;
4243	pThisCC->offLogoData += cb;
4244
4245	return VINF_SUCCESS;
4246	}
4247
4248
4249	/* -=-=-=-=-=- Ring 3: Debug Info Handlers -=-=-=-=-=- */
4250
4251	/**
4252	* @callback_method_impl{FNDBGFHANDLERDEV,
4253	* Dumps several interesting bits of the VGA state that are difficult to
4254	* decode from the registers.}
4255	*/
4256	static DECLCALLBACK(void) vgaR3InfoState(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
4257	{
4258	PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE);
4259	int is_graph, double_scan;
4260	int w, h, char_height, char_dots;
4261	int val, vfreq_hz, hfreq_hz;
4262	vga_retrace_s *r = &pThis->retrace_state;
4263	const char *clocks[] = { "25.175 MHz", "28.322 MHz", "External", "Reserved?!" };
4264	NOREF(pszArgs);
4265
4266	is_graph = pThis->gr[6] & 1;
4267	char_dots = (pThis->sr[0x01] & 1) ? 8 : 9;
4268	double_scan = pThis->cr[9] >> 7;
4269	pHlp->pfnPrintf(pHlp, "pixel clock: %s\n", clocks[(pThis->msr >> 2) & 3]);
4270	pHlp->pfnPrintf(pHlp, "double scanning %s\n", double_scan ? "on" : "off");
4271	pHlp->pfnPrintf(pHlp, "double clocking %s\n", pThis->sr[1] & 0x08 ? "on" : "off");
4272	val = pThis->cr[0] + 5;
4273	pHlp->pfnPrintf(pHlp, "htotal: %d px (%d cclk)\n", val * char_dots, val);
4274	val = pThis->cr[6] + ((pThis->cr[7] & 1) << 8) + ((pThis->cr[7] & 0x20) << 4) + 2;
4275	pHlp->pfnPrintf(pHlp, "vtotal: %d px\n", val);
4276	val = pThis->cr[1] + 1;
4277	w = val * char_dots;
4278	pHlp->pfnPrintf(pHlp, "hdisp : %d px (%d cclk)\n", w, val);
4279	val = pThis->cr[0x12] + ((pThis->cr[7] & 2) << 7) + ((pThis->cr[7] & 0x40) << 4) + 1;
4280	h = val;
4281	pHlp->pfnPrintf(pHlp, "vdisp : %d px\n", val);
4282	val = ((pThis->cr[9] & 0x40) << 3) + ((pThis->cr[7] & 0x10) << 4) + pThis->cr[0x18];
4283	pHlp->pfnPrintf(pHlp, "split : %d ln\n", val);
4284	val = (pThis->cr[0xc] << 8) + pThis->cr[0xd];
4285	pHlp->pfnPrintf(pHlp, "start : %#x\n", val);
4286	if (!is_graph)
4287	{
4288	val = (pThis->cr[9] & 0x1f) + 1;
4289	char_height = val;
4290	pHlp->pfnPrintf(pHlp, "char height %d\n", val);
4291	pHlp->pfnPrintf(pHlp, "text mode %dx%d\n", w / char_dots, h / (char_height << double_scan));
4292
4293	uint32_t cbLine;
4294	uint32_t offStart;
4295	uint32_t uLineCompareIgn;
4296	vgaR3GetOffsets(pThis, &cbLine, &offStart, &uLineCompareIgn);
4297	if (!cbLine)
4298	cbLine = 80 * 8;
4299	offStart *= 8;
4300	pHlp->pfnPrintf(pHlp, "cbLine: %#x\n", cbLine);
4301	pHlp->pfnPrintf(pHlp, "offStart: %#x (line %#x)\n", offStart, offStart / cbLine);
4302	}
4303	if (pThis->fRealRetrace)
4304	{
4305	val = r->hb_start;
4306	pHlp->pfnPrintf(pHlp, "hblank start: %d px (%d cclk)\n", val * char_dots, val);
4307	val = r->hb_end;
4308	pHlp->pfnPrintf(pHlp, "hblank end : %d px (%d cclk)\n", val * char_dots, val);
4309	pHlp->pfnPrintf(pHlp, "vblank start: %d px, end: %d px\n", r->vb_start, r->vb_end);
4310	pHlp->pfnPrintf(pHlp, "vsync start : %d px, end: %d px\n", r->vs_start, r->vs_end);
4311	pHlp->pfnPrintf(pHlp, "cclks per frame: %d\n", r->frame_cclks);
4312	pHlp->pfnPrintf(pHlp, "cclk time (ns) : %d\n", r->cclk_ns);
4313	if (r->frame_ns && r->h_total_ns) /* Careful in case state is temporarily invalid. */
4314	{
4315	vfreq_hz = 1000000000 / r->frame_ns;
4316	hfreq_hz = 1000000000 / r->h_total_ns;
4317	pHlp->pfnPrintf(pHlp, "vfreq: %d Hz, hfreq: %d.%03d kHz\n",
4318	vfreq_hz, hfreq_hz / 1000, hfreq_hz % 1000);
4319	}
4320	}
4321	pHlp->pfnPrintf(pHlp, "display refresh interval: %u ms\n", pThis->cMilliesRefreshInterval);
4322
4323	# ifdef VBOX_WITH_VMSVGA
4324	if (pThis->svga.fEnabled)
4325	pHlp->pfnPrintf(pHlp, pThis->svga.f3DEnabled ? "VMSVGA 3D enabled: %ux%ux%u\n" : "VMSVGA enabled: %ux%ux%u",
4326	pThis->svga.uWidth, pThis->svga.uHeight, pThis->svga.uBpp);
4327	# endif
4328	}
4329
4330
4331	/**
4332	* Prints a separator line.
4333	*
4334	* @param pHlp Callback functions for doing output.
4335	* @param cCols The number of columns.
4336	* @param pszTitle The title text, NULL if none.
4337	*/
4338	static void vgaR3InfoTextPrintSeparatorLine(PCDBGFINFOHLP pHlp, size_t cCols, const char *pszTitle)
4339	{
4340	if (pszTitle)
4341	{
4342	size_t cchTitle = strlen(pszTitle);
4343	if (cchTitle + 6 >= cCols)
4344	{
4345	pHlp->pfnPrintf(pHlp, "-- %s --", pszTitle);
4346	cCols = 0;
4347	}
4348	else
4349	{
4350	size_t cchLeft = (cCols - cchTitle - 2) / 2;
4351	cCols -= cchLeft + cchTitle + 2;
4352	while (cchLeft-- > 0)
4353	pHlp->pfnPrintf(pHlp, "-");
4354	pHlp->pfnPrintf(pHlp, " %s ", pszTitle);
4355	}
4356	}
4357
4358	while (cCols-- > 0)
4359	pHlp->pfnPrintf(pHlp, "-");
4360	pHlp->pfnPrintf(pHlp, "\n");
4361	}
4362
4363
4364	/**
4365	* Worker for vgaR3InfoText.
4366	*
4367	* @param pThis The shared VGA state.
4368	* @param pThisCC The VGA state for ring-3.
4369	* @param pHlp Callback functions for doing output.
4370	* @param offStart Where to start dumping (relative to the VRAM).
4371	* @param cbLine The source line length (aka line_offset).
4372	* @param cCols The number of columns on the screen.
4373	* @param cRows The number of rows to dump.
4374	* @param iScrBegin The row at which the current screen output starts.
4375	* @param iScrEnd The row at which the current screen output end
4376	* (exclusive).
4377	*/
4378	static void vgaR3InfoTextWorker(PVGASTATE pThis, PVGASTATER3 pThisCC, PCDBGFINFOHLP pHlp,
4379	uint32_t offStart, uint32_t cbLine,
4380	uint32_t cCols, uint32_t cRows,
4381	uint32_t iScrBegin, uint32_t iScrEnd)
4382	{
4383	/* Title, */
4384	char szTitle[32];
4385	if (iScrBegin \|\| iScrEnd < cRows)
4386	RTStrPrintf(szTitle, sizeof(szTitle), "%ux%u (+%u before, +%u after)",
4387	cCols, iScrEnd - iScrBegin, iScrBegin, cRows - iScrEnd);
4388	else
4389	RTStrPrintf(szTitle, sizeof(szTitle), "%ux%u", cCols, iScrEnd - iScrBegin);
4390
4391	/* Do the dumping. */
4392	uint8_t const *pbSrcOuter = pThisCC->pbVRam + offStart;
4393	uint32_t iRow;
4394	for (iRow = 0; iRow < cRows; iRow++, pbSrcOuter += cbLine)
4395	{
4396	if ((uintptr_t)(pbSrcOuter + cbLine - pThisCC->pbVRam) > pThis->vram_size) {
4397	pHlp->pfnPrintf(pHlp, "The last %u row/rows is/are outside the VRAM.\n", cRows - iRow);
4398	break;
4399	}
4400
4401	if (iRow == 0)
4402	vgaR3InfoTextPrintSeparatorLine(pHlp, cCols, szTitle);
4403	else if (iRow == iScrBegin)
4404	vgaR3InfoTextPrintSeparatorLine(pHlp, cCols, "screen start");
4405	else if (iRow == iScrEnd)
4406	vgaR3InfoTextPrintSeparatorLine(pHlp, cCols, "screen end");
4407
4408	uint8_t const *pbSrc = pbSrcOuter;
4409	for (uint32_t iCol = 0; iCol < cCols; ++iCol)
4410	{
4411	if (RT_C_IS_PRINT(*pbSrc))
4412	pHlp->pfnPrintf(pHlp, "%c", *pbSrc);
4413	else
4414	pHlp->pfnPrintf(pHlp, ".");
4415	pbSrc += 8; /* chars are spaced 8 bytes apart */
4416	}
4417	pHlp->pfnPrintf(pHlp, "\n");
4418	}
4419
4420	/* Final separator. */
4421	vgaR3InfoTextPrintSeparatorLine(pHlp, cCols, NULL);
4422	}
4423
4424
4425	/**
4426	* @callback_method_impl{FNDBGFHANDLERDEV,
4427	* Dumps VGA memory formatted as ASCII text\, no attributes. Only looks at
4428	* the first page.}
4429	*/
4430	static DECLCALLBACK(void) vgaR3InfoText(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
4431	{
4432	PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE);
4433	PVGASTATECC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PVGASTATECC);
4434
4435	/*
4436	* Parse args.
4437	*/
4438	bool fAll = true;
4439	if (pszArgs && *pszArgs)
4440	{
4441	if (!strcmp(pszArgs, "all"))
4442	fAll = true;
4443	else if (!strcmp(pszArgs, "scr") \|\| !strcmp(pszArgs, "screen"))
4444	fAll = false;
4445	else
4446	{
4447	pHlp->pfnPrintf(pHlp, "Invalid argument: '%s'\n", pszArgs);
4448	return;
4449	}
4450	}
4451
4452	/*
4453	* Check that we're in text mode and that the VRAM is accessible.
4454	*/
4455	if (!(pThis->gr[6] & 1))
4456	{
4457	uint8_t *pbSrc = pThisCC->pbVRam;
4458	if (pbSrc)
4459	{
4460	/*
4461	* Figure out the display size and where the text is.
4462	*
4463	* Note! We're cutting quite a few corners here and this code could
4464	* do with some brushing up. Dumping from the start of the
4465	* frame buffer is done intentionally so that we're more
4466	* likely to obtain the full scrollback of a linux panic.
4467	* windbg> .printf "------ start -----\n"; .for (r $t0 = 0; @$t0 < 25; r $t0 = @$t0 + 1) { .for (r $t1 = 0; @$t1 < 80; r $t1 = @$t1 + 1) { .printf "%c", by( (@$t0 * 80 + @$t1) * 8 + 100f0000) }; .printf "\n" }; .printf "------ end -----\n";
4468	*/
4469	uint32_t cbLine;
4470	uint32_t offStart;
4471	uint32_t uLineCompareIgn;
4472	vgaR3GetOffsets(pThis, &cbLine, &offStart, &uLineCompareIgn);
4473	if (!cbLine)
4474	cbLine = 80 * 8;
4475	offStart *= 8;
4476
4477	uint32_t uVDisp = pThis->cr[0x12] + ((pThis->cr[7] & 2) << 7) + ((pThis->cr[7] & 0x40) << 4) + 1;
4478	uint32_t uCharHeight = (pThis->cr[9] & 0x1f) + 1;
4479	uint32_t uDblScan = pThis->cr[9] >> 7;
4480	uint32_t cScrRows = uVDisp / (uCharHeight << uDblScan);
4481	if (cScrRows < 25)
4482	cScrRows = 25;
4483	uint32_t iScrBegin = offStart / cbLine;
4484	uint32_t cRows = iScrBegin + cScrRows;
4485	uint32_t cCols = cbLine / 8;
4486
4487	if (fAll)
4488	vgaR3InfoTextWorker(pThis, pThisCC, pHlp, offStart - iScrBegin * cbLine, cbLine,
4489	cCols, cRows, iScrBegin, iScrBegin + cScrRows);
4490	else
4491	vgaR3InfoTextWorker(pThis, pThisCC, pHlp, offStart, cbLine, cCols, cScrRows, 0, cScrRows);
4492	}
4493	else
4494	pHlp->pfnPrintf(pHlp, "VGA memory not available!\n");
4495	}
4496	else
4497	pHlp->pfnPrintf(pHlp, "Not in text mode!\n");
4498	}
4499
4500
4501	/**
4502	* @callback_method_impl{FNDBGFHANDLERDEV, Dumps VGA Sequencer registers.}
4503	*/
4504	static DECLCALLBACK(void) vgaR3InfoSR(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
4505	{
4506	PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE);
4507	NOREF(pszArgs);
4508
4509	pHlp->pfnPrintf(pHlp, "VGA Sequencer (3C5): SR index 3C4:%02X\n", pThis->sr_index);
4510	Assert(sizeof(pThis->sr) >= 8);
4511	for (unsigned i = 0; i < 8; ++i)
4512	pHlp->pfnPrintf(pHlp, " SR%02X:%02X", i, pThis->sr[i]);
4513	pHlp->pfnPrintf(pHlp, "\n");
4514	}
4515
4516
4517	/**
4518	* @callback_method_impl{FNDBGFHANDLERDEV, Dumps VGA CRTC registers.}
4519	*/
4520	static DECLCALLBACK(void) vgaR3InfoCR(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
4521	{
4522	PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE);
4523	unsigned i;
4524	NOREF(pszArgs);
4525
4526	pHlp->pfnPrintf(pHlp, "VGA CRTC (3D5): CRTC index 3D4:%02X\n", pThis->cr_index);
4527	Assert(sizeof(pThis->cr) >= 24);
4528	for (i = 0; i < 10; ++i)
4529	pHlp->pfnPrintf(pHlp, " CR%02X:%02X", i, pThis->cr[i]);
4530	pHlp->pfnPrintf(pHlp, "\n");
4531	for (i = 10; i < 20; ++i)
4532	pHlp->pfnPrintf(pHlp, " CR%02X:%02X", i, pThis->cr[i]);
4533	pHlp->pfnPrintf(pHlp, "\n");
4534	for (i = 20; i < 25; ++i)
4535	pHlp->pfnPrintf(pHlp, " CR%02X:%02X", i, pThis->cr[i]);
4536	pHlp->pfnPrintf(pHlp, "\n");
4537	}
4538
4539
4540	/**
4541	* @callback_method_impl{FNDBGFHANDLERDEV,
4542	* Dumps VGA Graphics Controller registers.}
4543	*/
4544	static DECLCALLBACK(void) vgaR3InfoGR(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
4545	{
4546	PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE);
4547	NOREF(pszArgs);
4548
4549	pHlp->pfnPrintf(pHlp, "VGA Graphics Controller (3CF): GR index 3CE:%02X\n", pThis->gr_index);
4550	Assert(sizeof(pThis->gr) >= 9);
4551	for (unsigned i = 0; i < 9; ++i)
4552	pHlp->pfnPrintf(pHlp, " GR%02X:%02X", i, pThis->gr[i]);
4553	pHlp->pfnPrintf(pHlp, "\n");
4554	}
4555
4556
4557	/**
4558	* @callback_method_impl{FNDBGFHANDLERDEV,
4559	* Dumps VGA Attribute Controller registers.}
4560	*/
4561	static DECLCALLBACK(void) vgaR3InfoAR(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
4562	{
4563	PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE);
4564	unsigned i;
4565	NOREF(pszArgs);
4566
4567	pHlp->pfnPrintf(pHlp, "VGA Attribute Controller (3C0): index reg %02X, flip-flop: %d (%s)\n",
4568	pThis->ar_index, pThis->ar_flip_flop, pThis->ar_flip_flop ? "data" : "index" );
4569	Assert(sizeof(pThis->ar) >= 0x14);
4570	pHlp->pfnPrintf(pHlp, " Palette:");
4571	for (i = 0; i < 0x10; ++i)
4572	pHlp->pfnPrintf(pHlp, " %02X", pThis->ar[i]);
4573	pHlp->pfnPrintf(pHlp, "\n");
4574	for (i = 0x10; i <= 0x14; ++i)
4575	pHlp->pfnPrintf(pHlp, " AR%02X:%02X", i, pThis->ar[i]);
4576	pHlp->pfnPrintf(pHlp, "\n");
4577	}
4578
4579
4580	/**
4581	* @callback_method_impl{FNDBGFHANDLERDEV, Dumps VGA DAC registers.}
4582	*/
4583	static DECLCALLBACK(void) vgaR3InfoDAC(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
4584	{
4585	PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE);
4586	NOREF(pszArgs);
4587
4588	pHlp->pfnPrintf(pHlp, "VGA DAC contents:\n");
4589	for (unsigned i = 0; i < 0x100; ++i)
4590	pHlp->pfnPrintf(pHlp, " %02X: %02X %02X %02X\n",
4591	i, pThis->palette[i3+0], pThis->palette[i3+1], pThis->palette[i*3+2]);
4592	}
4593
4594
4595	/**
4596	* @callback_method_impl{FNDBGFHANDLERDEV, Dumps VBE registers.}
4597	*/
4598	static DECLCALLBACK(void) vgaR3InfoVBE(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
4599	{
4600	PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE);
4601	NOREF(pszArgs);
4602
4603	pHlp->pfnPrintf(pHlp, "LFB at %RGp\n", pThis->GCPhysVRAM);
4604	if (!(pThis->vbe_regs[VBE_DISPI_INDEX_ENABLE] & VBE_DISPI_ENABLED))
4605	pHlp->pfnPrintf(pHlp, "VBE disabled\n");
4606	else
4607	{
4608	pHlp->pfnPrintf(pHlp, "VBE state (chip ID 0x%04x):\n", pThis->vbe_regs[VBE_DISPI_INDEX_ID]);
4609	pHlp->pfnPrintf(pHlp, " Display resolution: %d x %d @ %dbpp\n",
4610	pThis->vbe_regs[VBE_DISPI_INDEX_XRES], pThis->vbe_regs[VBE_DISPI_INDEX_YRES],
4611	pThis->vbe_regs[VBE_DISPI_INDEX_BPP]);
4612	pHlp->pfnPrintf(pHlp, " Virtual resolution: %d x %d\n",
4613	pThis->vbe_regs[VBE_DISPI_INDEX_VIRT_WIDTH], pThis->vbe_regs[VBE_DISPI_INDEX_VIRT_HEIGHT]);
4614	pHlp->pfnPrintf(pHlp, " Display start addr: %d, %d\n",
4615	pThis->vbe_regs[VBE_DISPI_INDEX_X_OFFSET], pThis->vbe_regs[VBE_DISPI_INDEX_Y_OFFSET]);
4616	pHlp->pfnPrintf(pHlp, " Linear scanline pitch: 0x%04x\n", pThis->vbe_line_offset);
4617	pHlp->pfnPrintf(pHlp, " Linear display start : 0x%04x\n", pThis->vbe_start_addr);
4618	pHlp->pfnPrintf(pHlp, " Selected bank: 0x%04x\n", pThis->vbe_regs[VBE_DISPI_INDEX_BANK]);
4619	}
4620	}
4621
4622
4623	/**
4624	* @callback_method_impl{FNDBGFHANDLERDEV,
4625	* Dumps register state relevant to 16-color planar graphics modes (GR/SR)
4626	* in human-readable form.}
4627	*/
4628	static DECLCALLBACK(void) vgaR3InfoPlanar(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
4629	{
4630	PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE);
4631	NOREF(pszArgs);
4632
4633	unsigned val1 = (pThis->gr[5] >> 3) & 1;
4634	unsigned val2 = pThis->gr[5] & 3;
4635	pHlp->pfnPrintf(pHlp, "read mode : %u write mode: %u\n", val1, val2);
4636	val1 = pThis->gr[0];
4637	val2 = pThis->gr[1];
4638	pHlp->pfnPrintf(pHlp, "set/reset data: %02X S/R enable: %02X\n", val1, val2);
4639	val1 = pThis->gr[2];
4640	val2 = pThis->gr[4] & 3;
4641	pHlp->pfnPrintf(pHlp, "color compare : %02X read map : %u\n", val1, val2);
4642	val1 = pThis->gr[3] & 7;
4643	val2 = (pThis->gr[3] >> 3) & 3;
4644	pHlp->pfnPrintf(pHlp, "rotate : %u function : %u\n", val1, val2);
4645	val1 = pThis->gr[7];
4646	val2 = pThis->gr[8];
4647	pHlp->pfnPrintf(pHlp, "don't care : %02X bit mask : %02X\n", val1, val2);
4648	val1 = pThis->sr[2];
4649	val2 = pThis->sr[4] & 8;
4650	pHlp->pfnPrintf(pHlp, "seq plane mask: %02X chain-4 : %s\n", val1, val2 ? "on" : "off");
4651	}
4652
4653
4654	/* -=-=-=-=-=- Ring 3: IBase -=-=-=-=-=- */
4655
4656	/**
4657	* @interface_method_impl{PDMIBASE,pfnQueryInterface}
4658	*/
4659	static DECLCALLBACK(void ) vgaR3PortQueryInterface(PPDMIBASE pInterface, const char pszIID)
4660	{
4661	PVGASTATECC pThisCC = RT_FROM_MEMBER(pInterface, VGASTATECC, IBase);
4662	PDMIBASE_RETURN_INTERFACE(pszIID, PDMIBASE, &pThisCC->IBase);
4663	PDMIBASE_RETURN_INTERFACE(pszIID, PDMIDISPLAYPORT, &pThisCC->IPort);
4664	# if defined(VBOX_WITH_HGSMI) && defined(VBOX_WITH_VIDEOHWACCEL)
4665	PDMIBASE_RETURN_INTERFACE(pszIID, PDMIDISPLAYVBVACALLBACKS, &pThisCC->IVBVACallbacks);
4666	# endif
4667	PDMIBASE_RETURN_INTERFACE(pszIID, PDMILEDPORTS, &pThisCC->ILeds);
4668	return NULL;
4669	}
4670
4671
4672	/* -=-=-=-=-=- Ring 3: ILeds -=-=-=-=-=- */
4673
4674	/**
4675	* @interface_method_impl{PDMILEDPORTS,pfnQueryStatusLed}
4676	*/
4677	static DECLCALLBACK(int) vgaR3PortQueryStatusLed(PPDMILEDPORTS pInterface, unsigned iLUN, PPDMLED *ppLed)
4678	{
4679	PVGASTATECC pThisCC = RT_FROM_MEMBER(pInterface, VGASTATECC, ILeds);
4680	PPDMDEVINS pDevIns = pThisCC->pDevIns;
4681	PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE);
4682	switch (iLUN)
4683	{
4684	/* LUN #0 is the only one for which we have a status LED. */
4685	case 0:
4686	{
4687	*ppLed = &pThis->Led3D;
4688	Assert((*ppLed)->u32Magic == PDMLED_MAGIC);
4689	return VINF_SUCCESS;
4690	}
4691
4692	default:
4693	AssertMsgFailed(("Invalid LUN #%u\n", iLUN));
4694	return VERR_PDM_NO_SUCH_LUN;
4695	}
4696	}
4697
4698
4699	/* -=-=-=-=-=- Ring 3: Dummy IDisplayConnector -=-=-=-=-=- */
4700
4701	/**
4702	* @interface_method_impl{PDMIDISPLAYCONNECTOR,pfnResize}
4703	*/
4704	static DECLCALLBACK(int) vgaR3DummyResize(PPDMIDISPLAYCONNECTOR pInterface, uint32_t cBits, void *pvVRAM,
4705	uint32_t cbLine, uint32_t cx, uint32_t cy)
4706	{
4707	RT_NOREF(pInterface, cBits, pvVRAM, cbLine, cx, cy);
4708	return VINF_SUCCESS;
4709	}
4710
4711
4712	/**
4713	* @interface_method_impl{PDMIDISPLAYCONNECTOR,pfnUpdateRect}
4714	*/
4715	static DECLCALLBACK(void) vgaR3DummyUpdateRect(PPDMIDISPLAYCONNECTOR pInterface, uint32_t x, uint32_t y, uint32_t cx, uint32_t cy)
4716	{
4717	RT_NOREF(pInterface, x, y, cx, cy);
4718	}
4719
4720
4721	/**
4722	* @interface_method_impl{PDMIDISPLAYCONNECTOR,pfnRefresh}
4723	*/
4724	static DECLCALLBACK(void) vgaR3DummyRefresh(PPDMIDISPLAYCONNECTOR pInterface)
4725	{
4726	NOREF(pInterface);
4727	}
4728
4729
4730	/* -=-=-=-=-=- Ring 3: IDisplayPort -=-=-=-=-=- */
4731
4732	/**
4733	* @interface_method_impl{PDMIDISPLAYPORT,pfnUpdateDisplay}
4734	*/
4735	static DECLCALLBACK(int) vgaR3PortUpdateDisplay(PPDMIDISPLAYPORT pInterface)
4736	{
4737	PVGASTATECC pThisCC = RT_FROM_MEMBER(pInterface, VGASTATECC, IPort);
4738	PPDMDEVINS pDevIns = pThisCC->pDevIns;
4739	PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE);
4740	PDMDEV_ASSERT_EMT(pDevIns);
4741
4742	int rc = PDMDevHlpCritSectEnter(pDevIns, &pThis->CritSect, VERR_SEM_BUSY);
4743	AssertRC(rc);
4744
4745	# ifdef VBOX_WITH_VMSVGA
4746	if ( pThis->svga.fEnabled
4747	&& !pThis->svga.fTraces)
4748	{
4749	/* Nothing to do as the guest will explicitely update us about frame buffer changes. */
4750	PDMDevHlpCritSectLeave(pDevIns, &pThis->CritSect);
4751	return VINF_SUCCESS;
4752	}
4753	#endif
4754
4755	# ifndef VBOX_WITH_HGSMI
4756	/* This should be called only in non VBVA mode. */
4757	# else
4758	if (VBVAUpdateDisplay(pThis, pThisCC) == VINF_SUCCESS)
4759	{
4760	PDMDevHlpCritSectLeave(pDevIns, &pThis->CritSect);
4761	return VINF_SUCCESS;
4762	}
4763	# endif /* VBOX_WITH_HGSMI */
4764
4765	STAM_COUNTER_INC(&pThis->StatUpdateDisp);
4766	if (pThis->fHasDirtyBits && pThis->GCPhysVRAM && pThis->GCPhysVRAM != NIL_RTGCPHYS)
4767	{
4768	PGMHandlerPhysicalReset(PDMDevHlpGetVM(pDevIns), pThis->GCPhysVRAM);
4769	pThis->fHasDirtyBits = false;
4770	}
4771	if (pThis->fRemappedVGA)
4772	{
4773	IOMMmioResetRegion(PDMDevHlpGetVM(pDevIns), pDevIns, pThis->hMmioLegacy);
4774	pThis->fRemappedVGA = false;
4775	}
4776
4777	rc = vgaR3UpdateDisplay(pDevIns, pThis, pThisCC, false /fUpdateAll/, false /fFailOnResize/, true /reset_dirty/,
4778	pThisCC->pDrv, &pThis->graphic_mode);
4779	PDMDevHlpCritSectLeave(pDevIns, &pThis->CritSect);
4780	return rc;
4781	}
4782
4783
4784	/**
4785	* Internal vgaR3PortUpdateDisplayAll worker called under pThis->CritSect.
4786	*/
4787	static int vboxR3UpdateDisplayAllInternal(PPDMDEVINS pDevIns, PVGASTATE pThis, PVGASTATECC pThisCC, bool fFailOnResize)
4788	{
4789	# ifdef VBOX_WITH_VMSVGA
4790	if ( !pThis->svga.fEnabled
4791	\|\| pThis->svga.fTraces)
4792	{
4793	# endif
4794	/* The dirty bits array has been just cleared, reset handlers as well. */
4795	if (pThis->GCPhysVRAM && pThis->GCPhysVRAM != NIL_RTGCPHYS)
4796	PGMHandlerPhysicalReset(PDMDevHlpGetVM(pDevIns), pThis->GCPhysVRAM);
4797	# ifdef VBOX_WITH_VMSVGA
4798	}
4799	# endif
4800	if (pThis->fRemappedVGA)
4801	{
4802	IOMMmioResetRegion(PDMDevHlpGetVM(pDevIns), pDevIns, pThis->hMmioLegacy);
4803	pThis->fRemappedVGA = false;
4804	}
4805
4806	pThis->graphic_mode = -1; /* force full update */
4807
4808	return vgaR3UpdateDisplay(pDevIns, pThis, pThisCC, true /fUpdateAll/, fFailOnResize,
4809	true /reset_dirty/, pThisCC->pDrv, &pThis->graphic_mode);
4810	}
4811
4812
4813	/**
4814	* @interface_method_impl{PDMIDISPLAYPORT,pfnUpdateDisplayAll}
4815	*/
4816	static DECLCALLBACK(int) vgaR3PortUpdateDisplayAll(PPDMIDISPLAYPORT pInterface, bool fFailOnResize)
4817	{
4818	PVGASTATECC pThisCC = RT_FROM_MEMBER(pInterface, VGASTATECC, IPort);
4819	PPDMDEVINS pDevIns = pThisCC->pDevIns;
4820	PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE);
4821	PDMDEV_ASSERT_EMT(pDevIns);
4822
4823	/* This is called both in VBVA mode and normal modes. */
4824
4825	# ifdef DEBUG_sunlover
4826	LogFlow(("vgaR3PortUpdateDisplayAll\n"));
4827	# endif /* DEBUG_sunlover */
4828
4829	int rc = PDMDevHlpCritSectEnter(pDevIns, &pThis->CritSect, VERR_SEM_BUSY);
4830	AssertRC(rc);
4831
4832	rc = vboxR3UpdateDisplayAllInternal(pDevIns, pThis, pThisCC, fFailOnResize);
4833
4834	PDMDevHlpCritSectLeave(pDevIns, &pThis->CritSect);
4835	return rc;
4836	}
4837
4838
4839	/**
4840	* @interface_method_impl{PDMIDISPLAYPORT,pfnSetRefreshRate}
4841	*/
4842	static DECLCALLBACK(int) vgaR3PortSetRefreshRate(PPDMIDISPLAYPORT pInterface, uint32_t cMilliesInterval)
4843	{
4844	PVGASTATECC pThisCC = RT_FROM_MEMBER(pInterface, VGASTATECC, IPort);
4845	PPDMDEVINS pDevIns = pThisCC->pDevIns;
4846	PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE);
4847
4848	/*
4849	* Update the interval, notify the VMSVGA FIFO thread if sleeping,
4850	* then restart or stop the timer.
4851	*/
4852	ASMAtomicWriteU32(&pThis->cMilliesRefreshInterval, cMilliesInterval);
4853
4854	# ifdef VBOX_WITH_VMSVGA
4855	if (pThis->svga.fFIFOThreadSleeping)
4856	PDMDevHlpSUPSemEventSignal(pDevIns, pThis->svga.hFIFORequestSem);
4857	# endif
4858
4859	if (cMilliesInterval)
4860	return PDMDevHlpTimerSetMillies(pDevIns, pThis->hRefreshTimer, cMilliesInterval);
4861	return PDMDevHlpTimerStop(pDevIns, pThis->hRefreshTimer);
4862	}
4863
4864
4865	/**
4866	* @interface_method_impl{PDMIDISPLAYPORT,pfnQueryVideoMode}
4867	*/
4868	static DECLCALLBACK(int) vgaR3PortQueryVideoMode(PPDMIDISPLAYPORT pInterface, uint32_t pcBits, uint32_t pcx, uint32_t *pcy)
4869	{
4870	PVGASTATECC pThisCC = RT_FROM_MEMBER(pInterface, VGASTATECC, IPort);
4871	PPDMDEVINS pDevIns = pThisCC->pDevIns;
4872	PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE);
4873
4874	AssertReturn(pcBits, VERR_INVALID_PARAMETER);
4875
4876	*pcBits = vgaR3GetBpp(pThis);
4877	if (pcx)
4878	*pcx = pThis->last_scr_width;
4879	if (pcy)
4880	*pcy = pThis->last_scr_height;
4881	return VINF_SUCCESS;
4882	}
4883
4884
4885	/**
4886	* @interface_method_impl{PDMIDISPLAYPORT,pfnTakeScreenshot}
4887	*/
4888	static DECLCALLBACK(int) vgaR3PortTakeScreenshot(PPDMIDISPLAYPORT pInterface, uint8_t *ppbData, size_t pcbData,
4889	uint32_t pcx, uint32_t pcy)
4890	{
4891	PVGASTATECC pThisCC = RT_FROM_MEMBER(pInterface, VGASTATECC, IPort);
4892	PPDMDEVINS pDevIns = pThisCC->pDevIns;
4893	PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE);
4894	PDMDEV_ASSERT_EMT(pDevIns);
4895
4896	LogFlow(("vgaR3PortTakeScreenshot: ppbData=%p pcbData=%p pcx=%p pcy=%p\n", ppbData, pcbData, pcx, pcy));
4897
4898	/*
4899	* Validate input.
4900	*/
4901	if (!RT_VALID_PTR(ppbData) \|\| !RT_VALID_PTR(pcbData) \|\| !RT_VALID_PTR(pcx) \|\| !RT_VALID_PTR(pcy))
4902	return VERR_INVALID_PARAMETER;
4903
4904	int rc = PDMDevHlpCritSectEnter(pDevIns, &pThis->CritSect, VERR_SEM_BUSY);
4905	AssertRCReturn(rc, rc);
4906
4907	/*
4908	* Get screenshot. This function will fail if a resize is required.
4909	* So there is not need to do a 'vboxR3UpdateDisplayAllInternal' before taking screenshot.
4910	*/
4911
4912	/*
4913	* Allocate the buffer for 32 bits per pixel bitmap
4914	*
4915	* Note! The size can't be zero or greater than the size of the VRAM.
4916	* Inconsistent VGA device state can cause the incorrect size values.
4917	*/
4918	size_t cbRequired = pThis->last_scr_width * 4 * pThis->last_scr_height;
4919	if (cbRequired && cbRequired <= pThis->vram_size)
4920	{
4921	uint8_t pbData = (uint8_t )RTMemAlloc(cbRequired);
4922	if (pbData != NULL)
4923	{
4924	/*
4925	* Only 3 methods, assigned below, will be called during the screenshot update.
4926	* All other are already set to NULL.
4927	*/
4928	/* The display connector interface is temporarily replaced with the fake one. */
4929	PDMIDISPLAYCONNECTOR Connector;
4930	RT_ZERO(Connector);
4931	Connector.pbData = pbData;
4932	Connector.cBits = 32;
4933	Connector.cx = pThis->last_scr_width;
4934	Connector.cy = pThis->last_scr_height;
4935	Connector.cbScanline = Connector.cx * 4;
4936	Connector.pfnRefresh = vgaR3DummyRefresh;
4937	Connector.pfnResize = vgaR3DummyResize;
4938	Connector.pfnUpdateRect = vgaR3DummyUpdateRect;
4939
4940	int32_t cur_graphic_mode = -1;
4941
4942	bool fSavedRenderVRAM = pThis->fRenderVRAM;
4943	pThis->fRenderVRAM = true;
4944
4945	/*
4946	* Take the screenshot.
4947	*
4948	* The second parameter is 'false' because the current display state is being rendered to an
4949	* external buffer using a fake connector. That is if display is blanked, we expect a black
4950	* screen in the external buffer.
4951	* If there is a pending resize, the function will fail.
4952	*/
4953	rc = vgaR3UpdateDisplay(pDevIns, pThis, pThisCC, false /fUpdateAll/, true /fFailOnResize/,
4954	false /reset_dirty/, &Connector, &cur_graphic_mode);
4955
4956	pThis->fRenderVRAM = fSavedRenderVRAM;
4957
4958	if (rc == VINF_SUCCESS)
4959	{
4960	/*
4961	* Return the result.
4962	*/
4963	*ppbData = pbData;
4964	*pcbData = cbRequired;
4965	*pcx = Connector.cx;
4966	*pcy = Connector.cy;
4967	}
4968	else
4969	{
4970	/* If we do not return a success, then the data buffer must be freed. */
4971	RTMemFree(pbData);
4972	if (RT_SUCCESS_NP(rc))
4973	{
4974	AssertMsgFailed(("%Rrc\n", rc));
4975	rc = VERR_INTERNAL_ERROR_5;
4976	}
4977	}
4978	}
4979	else
4980	rc = VERR_NO_MEMORY;
4981	}
4982	else
4983	rc = VERR_NOT_SUPPORTED;
4984
4985	PDMDevHlpCritSectLeave(pDevIns, &pThis->CritSect);
4986
4987	LogFlow(("vgaR3PortTakeScreenshot: returns %Rrc (cbData=%d cx=%d cy=%d)\n", rc, pcbData, pcx, *pcy));
4988	return rc;
4989	}
4990
4991
4992	/**
4993	* @interface_method_impl{PDMIDISPLAYPORT,pfnFreeScreenshot}
4994	*/
4995	static DECLCALLBACK(void) vgaR3PortFreeScreenshot(PPDMIDISPLAYPORT pInterface, uint8_t *pbData)
4996	{
4997	NOREF(pInterface);
4998
4999	LogFlow(("vgaR3PortFreeScreenshot: pbData=%p\n", pbData));
5000
5001	RTMemFree(pbData);
5002	}
5003
5004
5005	/**
5006	* @interface_method_impl{PDMIDISPLAYPORT,pfnDisplayBlt}
5007	*/
5008	static DECLCALLBACK(int) vgaR3PortDisplayBlt(PPDMIDISPLAYPORT pInterface, const void *pvData,
5009	uint32_t x, uint32_t y, uint32_t cx, uint32_t cy)
5010	{
5011	PVGASTATECC pThisCC = RT_FROM_MEMBER(pInterface, VGASTATECC, IPort);
5012	PPDMDEVINS pDevIns = pThisCC->pDevIns;
5013	PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE);
5014	PDMDEV_ASSERT_EMT(pDevIns);
5015	LogFlow(("vgaR3PortDisplayBlt: pvData=%p x=%d y=%d cx=%d cy=%d\n", pvData, x, y, cx, cy));
5016
5017	int rc = PDMDevHlpCritSectEnter(pDevIns, &pThis->CritSect, VERR_SEM_BUSY);
5018	AssertRC(rc);
5019
5020	/*
5021	* Validate input.
5022	*/
5023	if ( pvData
5024	&& x < pThisCC->pDrv->cx
5025	&& cx <= pThisCC->pDrv->cx
5026	&& cx + x <= pThisCC->pDrv->cx
5027	&& y < pThisCC->pDrv->cy
5028	&& cy <= pThisCC->pDrv->cy
5029	&& cy + y <= pThisCC->pDrv->cy)
5030	{
5031	/*
5032	* Determine bytes per pixel in the destination buffer.
5033	*/
5034	size_t cbPixelDst = 0;
5035	switch (pThisCC->pDrv->cBits)
5036	{
5037	case 8:
5038	cbPixelDst = 1;
5039	break;
5040	case 15:
5041	case 16:
5042	cbPixelDst = 2;
5043	break;
5044	case 24:
5045	cbPixelDst = 3;
5046	break;
5047	case 32:
5048	cbPixelDst = 4;
5049	break;
5050	default:
5051	rc = VERR_INVALID_PARAMETER;
5052	break;
5053	}
5054	if (RT_SUCCESS(rc))
5055	{
5056	/*
5057	* The blitting loop.
5058	*/
5059	size_t cbLineSrc = cx * 4; /* 32 bits per pixel. */
5060	uint8_t pbSrc = (uint8_t )pvData;
5061	size_t cbLineDst = pThisCC->pDrv->cbScanline;
5062	uint8_t pbDst = pThisCC->pDrv->pbData + y cbLineDst + x * cbPixelDst;
5063	uint32_t cyLeft = cy;
5064	vga_draw_line_func pfnVgaDrawLine = vga_draw_line_table[VGA_DRAW_LINE32 4 + vgaR3GetDepthIndex(pThisCC->pDrv->cBits)];
5065	Assert(pfnVgaDrawLine);
5066	while (cyLeft-- > 0)
5067	{
5068	pfnVgaDrawLine(pThis, pThisCC, pbDst, pbSrc, cx);
5069	pbDst += cbLineDst;
5070	pbSrc += cbLineSrc;
5071	}
5072
5073	/*
5074	* Invalidate the area.
5075	*/
5076	pThisCC->pDrv->pfnUpdateRect(pThisCC->pDrv, x, y, cx, cy);
5077	}
5078	}
5079	else
5080	rc = VERR_INVALID_PARAMETER;
5081
5082	PDMDevHlpCritSectLeave(pDevIns, &pThis->CritSect);
5083
5084	LogFlow(("vgaR3PortDisplayBlt: returns %Rrc\n", rc));
5085	return rc;
5086	}
5087
5088
5089	/**
5090	* @interface_method_impl{PDMIDISPLAYPORT,pfnUpdateDisplayRect}
5091	*/
5092	static DECLCALLBACK(void) vgaR3PortUpdateDisplayRect(PPDMIDISPLAYPORT pInterface, int32_t x, int32_t y, uint32_t cx, uint32_t cy)
5093	{
5094	PVGASTATECC pThisCC = RT_FROM_MEMBER(pInterface, VGASTATECC, IPort);
5095	PPDMDEVINS pDevIns = pThisCC->pDevIns;
5096	PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE);
5097	uint32_t v;
5098
5099	uint32_t cbPixelDst;
5100	uint32_t cbLineDst;
5101	uint8_t *pbDst;
5102
5103	uint32_t cbPixelSrc;
5104	uint32_t cbLineSrc;
5105	uint8_t *pbSrc;
5106
5107
5108	# ifdef DEBUG_sunlover
5109	LogFlow(("vgaR3PortUpdateDisplayRect: %d,%d %dx%d\n", x, y, cx, cy));
5110	# endif /* DEBUG_sunlover */
5111
5112	Assert(pInterface);
5113
5114	int rc = PDMDevHlpCritSectEnter(pDevIns, &pThis->CritSect, VERR_SEM_BUSY);
5115	AssertRC(rc);
5116
5117	/* Check if there is something to do at all. */
5118	if (!pThis->fRenderVRAM)
5119	{
5120	/* The framebuffer uses the guest VRAM directly. */
5121	# ifdef DEBUG_sunlover
5122	LogFlow(("vgaR3PortUpdateDisplayRect: nothing to do fRender is false.\n"));
5123	# endif /* DEBUG_sunlover */
5124	PDMDevHlpCritSectLeave(pDevIns, &pThis->CritSect);
5125	return;
5126	}
5127
5128	Assert(pThisCC->pDrv);
5129	Assert(pThisCC->pDrv->pbData);
5130
5131	/* Correct negative x and y coordinates. */
5132	if (x < 0)
5133	{
5134	x += cx; /* Compute xRight which is also the new width. */
5135	cx = (x < 0) ? 0 : x;
5136	x = 0;
5137	}
5138
5139	if (y < 0)
5140	{
5141	y += cy; /* Compute yBottom, which is also the new height. */
5142	cy = (y < 0) ? 0 : y;
5143	y = 0;
5144	}
5145
5146	/* Also check if coords are greater than the display resolution. */
5147	if (x + cx > pThisCC->pDrv->cx)
5148	{
5149	// x < 0 is not possible here
5150	cx = pThisCC->pDrv->cx > (uint32_t)x? pThisCC->pDrv->cx - x: 0;
5151	}
5152
5153	if (y + cy > pThisCC->pDrv->cy)
5154	{
5155	// y < 0 is not possible here
5156	cy = pThisCC->pDrv->cy > (uint32_t)y? pThisCC->pDrv->cy - y: 0;
5157	}
5158
5159	# ifdef DEBUG_sunlover
5160	LogFlow(("vgaR3PortUpdateDisplayRect: %d,%d %dx%d (corrected coords)\n", x, y, cx, cy));
5161	# endif
5162
5163	/* Check if there is something to do at all. */
5164	if (cx == 0 \|\| cy == 0)
5165	{
5166	/* Empty rectangle. */
5167	# ifdef DEBUG_sunlover
5168	LogFlow(("vgaR3PortUpdateDisplayRect: nothing to do: %dx%d\n", cx, cy));
5169	#endif
5170	PDMDevHlpCritSectLeave(pDevIns, &pThis->CritSect);
5171	return;
5172	}
5173
5174	/** @todo This method should be made universal and not only for VBVA.
5175	* VGA_DRAW_LINE* must be selected and src/dst address calculation
5176	* changed.
5177	*/
5178
5179	/* Choose the rendering function. */
5180	switch(pThisCC->get_bpp(pThis))
5181	{
5182	default:
5183	case 0:
5184	/* A LFB mode is already disabled, but the callback is still called
5185	* by Display because VBVA buffer is being flushed.
5186	* Nothing to do, just return.
5187	*/
5188	PDMDevHlpCritSectLeave(pDevIns, &pThis->CritSect);
5189	return;
5190	case 8:
5191	v = VGA_DRAW_LINE8;
5192	break;
5193	case 15:
5194	v = VGA_DRAW_LINE15;
5195	break;
5196	case 16:
5197	v = VGA_DRAW_LINE16;
5198	break;
5199	case 24:
5200	v = VGA_DRAW_LINE24;
5201	break;
5202	case 32:
5203	v = VGA_DRAW_LINE32;
5204	break;
5205	}
5206
5207	vga_draw_line_func pfnVgaDrawLine = vga_draw_line_table[v 4 + vgaR3GetDepthIndex(pThisCC->pDrv->cBits)];
5208
5209	/* Compute source and destination addresses and pitches. */
5210	cbPixelDst = (pThisCC->pDrv->cBits + 7) / 8;
5211	cbLineDst = pThisCC->pDrv->cbScanline;
5212	pbDst = pThisCC->pDrv->pbData + y * cbLineDst + x * cbPixelDst;
5213
5214	cbPixelSrc = (pThisCC->get_bpp(pThis) + 7) / 8;
5215	uint32_t offSrc, u32Dummy;
5216	pThisCC->get_offsets(pThis, &cbLineSrc, &offSrc, &u32Dummy);
5217
5218	/* Assume that rendering is performed only on visible part of VRAM.
5219	* This is true because coordinates were verified.
5220	*/
5221	pbSrc = pThisCC->pbVRam;
5222	pbSrc += offSrc * 4 + y * cbLineSrc + x * cbPixelSrc;
5223
5224	/* Render VRAM to framebuffer. */
5225
5226	# ifdef DEBUG_sunlover
5227	LogFlow(("vgaR3PortUpdateDisplayRect: dst: %p, %d, %d. src: %p, %d, %d\n", pbDst, cbLineDst, cbPixelDst, pbSrc, cbLineSrc, cbPixelSrc));
5228	# endif
5229
5230	while (cy-- > 0)
5231	{
5232	pfnVgaDrawLine(pThis, pThisCC, pbDst, pbSrc, cx);
5233	pbDst += cbLineDst;
5234	pbSrc += cbLineSrc;
5235	}
5236
5237	PDMDevHlpCritSectLeave(pDevIns, &pThis->CritSect);
5238	# ifdef DEBUG_sunlover
5239	LogFlow(("vgaR3PortUpdateDisplayRect: completed.\n"));
5240	# endif
5241	}
5242
5243
5244	/**
5245	* @interface_method_impl{PDMIDISPLAYPORT,pfnCopyRect}
5246	*/
5247	static DECLCALLBACK(int)
5248	vgaR3PortCopyRect(PPDMIDISPLAYPORT pInterface,
5249	uint32_t cx, uint32_t cy,
5250	const uint8_t *pbSrc, int32_t xSrc, int32_t ySrc, uint32_t cxSrc, uint32_t cySrc,
5251	uint32_t cbSrcLine, uint32_t cSrcBitsPerPixel,
5252	uint8_t *pbDst, int32_t xDst, int32_t yDst, uint32_t cxDst, uint32_t cyDst,
5253	uint32_t cbDstLine, uint32_t cDstBitsPerPixel)
5254	{
5255	PVGASTATECC pThisCC = RT_FROM_MEMBER(pInterface, VGASTATECC, IPort);
5256	PPDMDEVINS pDevIns = pThisCC->pDevIns;
5257	PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE);
5258	uint32_t v;
5259
5260	# ifdef DEBUG_sunlover
5261	LogFlow(("vgaR3PortCopyRect: %d,%d %dx%d -> %d,%d\n", xSrc, ySrc, cx, cy, xDst, yDst));
5262	# endif
5263
5264	Assert(pInterface);
5265	Assert(pThisCC->pDrv);
5266
5267	int32_t xSrcCorrected = xSrc;
5268	int32_t ySrcCorrected = ySrc;
5269	uint32_t cxCorrected = cx;
5270	uint32_t cyCorrected = cy;
5271
5272	/* Correct source coordinates to be within the source bitmap. */
5273	if (xSrcCorrected < 0)
5274	{
5275	xSrcCorrected += cxCorrected; /* Compute xRight which is also the new width. */
5276	cxCorrected = (xSrcCorrected < 0) ? 0 : xSrcCorrected;
5277	xSrcCorrected = 0;
5278	}
5279
5280	if (ySrcCorrected < 0)
5281	{
5282	ySrcCorrected += cyCorrected; /* Compute yBottom, which is also the new height. */
5283	cyCorrected = (ySrcCorrected < 0) ? 0 : ySrcCorrected;
5284	ySrcCorrected = 0;
5285	}
5286
5287	/* Also check if coords are greater than the display resolution. */
5288	if (xSrcCorrected + cxCorrected > cxSrc)
5289	{
5290	/* xSrcCorrected < 0 is not possible here */
5291	cxCorrected = cxSrc > (uint32_t)xSrcCorrected ? cxSrc - xSrcCorrected : 0;
5292	}
5293
5294	if (ySrcCorrected + cyCorrected > cySrc)
5295	{
5296	/* y < 0 is not possible here */
5297	cyCorrected = cySrc > (uint32_t)ySrcCorrected ? cySrc - ySrcCorrected : 0;
5298	}
5299
5300	# ifdef DEBUG_sunlover
5301	LogFlow(("vgaR3PortCopyRect: %d,%d %dx%d (corrected coords)\n", xSrcCorrected, ySrcCorrected, cxCorrected, cyCorrected));
5302	# endif
5303
5304	/* Check if there is something to do at all. */
5305	if (cxCorrected == 0 \|\| cyCorrected == 0)
5306	{
5307	/* Empty rectangle. */
5308	# ifdef DEBUG_sunlover
5309	LogFlow(("vgaPortUpdateDisplayRectEx: nothing to do: %dx%d\n", cxCorrected, cyCorrected));
5310	# endif
5311	return VINF_SUCCESS;
5312	}
5313
5314	/* Check that the corrected source rectangle is within the destination.
5315	* Note: source rectangle is adjusted, but the target must be large enough.
5316	*/
5317	if ( xDst < 0
5318	\|\| yDst < 0
5319	\|\| xDst + cxCorrected > cxDst
5320	\|\| yDst + cyCorrected > cyDst)
5321	{
5322	return VERR_INVALID_PARAMETER;
5323	}
5324
5325	int rc = PDMDevHlpCritSectEnter(pDevIns, &pThis->CritSect, VERR_SEM_BUSY);
5326	AssertRC(rc);
5327
5328	/* This method only works if the VGA device is in a VBE mode or not paused VBVA mode.
5329	* VGA modes are reported to the caller by returning VERR_INVALID_STATE.
5330	*
5331	* If VBE_DISPI_ENABLED is set, then it is a VBE or VBE compatible VBVA mode. Both of them can be handled.
5332	*
5333	* If VBE_DISPI_ENABLED is clear, then it is either a VGA mode or a VBVA mode set by guest additions
5334	* which have VBVACAPS_USE_VBVA_ONLY capability.
5335	* When VBE_DISPI_ENABLED is being cleared and VBVACAPS_USE_VBVA_ONLY is not set (i.e. guest wants a VGA mode),
5336	* then VBVAOnVBEChanged makes sure that VBVA is paused.
5337	* That is a not paused VBVA means that the video mode can be handled even if VBE_DISPI_ENABLED is clear.
5338	*/
5339	if ( (pThis->vbe_regs[VBE_DISPI_INDEX_ENABLE] & VBE_DISPI_ENABLED) == 0
5340	&& VBVAIsPaused(pThisCC)
5341	# ifdef VBOX_WITH_VMSVGA
5342	&& !pThis->svga.fEnabled
5343	# endif
5344	)
5345	{
5346	PDMDevHlpCritSectLeave(pDevIns, &pThis->CritSect);
5347	return VERR_INVALID_STATE;
5348	}
5349
5350	/* Choose the rendering function. */
5351	switch (cSrcBitsPerPixel)
5352	{
5353	default:
5354	case 0:
5355	/* Nothing to do, just return. */
5356	PDMDevHlpCritSectLeave(pDevIns, &pThis->CritSect);
5357	return VINF_SUCCESS;
5358	case 8:
5359	v = VGA_DRAW_LINE8;
5360	break;
5361	case 15:
5362	v = VGA_DRAW_LINE15;
5363	break;
5364	case 16:
5365	v = VGA_DRAW_LINE16;
5366	break;
5367	case 24:
5368	v = VGA_DRAW_LINE24;
5369	break;
5370	case 32:
5371	v = VGA_DRAW_LINE32;
5372	break;
5373	}
5374
5375	vga_draw_line_func pfnVgaDrawLine = vga_draw_line_table[v 4 + vgaR3GetDepthIndex(cDstBitsPerPixel)];
5376
5377	/* Compute source and destination addresses and pitches. */
5378	uint32_t cbPixelDst = (cDstBitsPerPixel + 7) / 8;
5379	uint32_t cbLineDst = cbDstLine;
5380	uint8_t pbDstCur = pbDst + yDst cbLineDst + xDst * cbPixelDst;
5381
5382	uint32_t cbPixelSrc = (cSrcBitsPerPixel + 7) / 8;
5383	uint32_t cbLineSrc = cbSrcLine;
5384	const uint8_t pbSrcCur = pbSrc + ySrcCorrected cbLineSrc + xSrcCorrected * cbPixelSrc;
5385
5386	# ifdef DEBUG_sunlover
5387	LogFlow(("vgaR3PortCopyRect: dst: %p, %d, %d. src: %p, %d, %d\n", pbDstCur, cbLineDst, cbPixelDst, pbSrcCur, cbLineSrc, cbPixelSrc));
5388	# endif
5389
5390	while (cyCorrected-- > 0)
5391	{
5392	pfnVgaDrawLine(pThis, pThisCC, pbDstCur, pbSrcCur, cxCorrected);
5393	pbDstCur += cbLineDst;
5394	pbSrcCur += cbLineSrc;
5395	}
5396
5397	PDMDevHlpCritSectLeave(pDevIns, &pThis->CritSect);
5398	# ifdef DEBUG_sunlover
5399	LogFlow(("vgaR3PortCopyRect: completed.\n"));
5400	# endif
5401	return VINF_SUCCESS;
5402	}
5403
5404
5405	/**
5406	* @interface_method_impl{PDMIDISPLAYPORT,pfnSetRenderVRAM}
5407	*/
5408	static DECLCALLBACK(void) vgaR3PortSetRenderVRAM(PPDMIDISPLAYPORT pInterface, bool fRender)
5409	{
5410	PVGASTATECC pThisCC = RT_FROM_MEMBER(pInterface, VGASTATECC, IPort);
5411	PPDMDEVINS pDevIns = pThisCC->pDevIns;
5412	PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE);
5413
5414	LogFlow(("vgaR3PortSetRenderVRAM: fRender = %d\n", fRender));
5415
5416	int rc = PDMDevHlpCritSectEnter(pDevIns, &pThis->CritSect, VERR_SEM_BUSY);
5417	AssertRC(rc);
5418
5419	pThis->fRenderVRAM = fRender;
5420
5421	PDMDevHlpCritSectLeave(pDevIns, &pThis->CritSect);
5422	}
5423
5424
5425	/**
5426	* @interface_method_impl{PDMIDISPLAYPORT,pfnReportHostCursorCapabilities}
5427	*/
5428	static DECLCALLBACK(void) vgaR3PortReportHostCursorCapabilities(PPDMIDISPLAYPORT pInterface, bool fSupportsRenderCursor,
5429	bool fSupportsMoveCursor)
5430	{
5431	RT_NOREF(pInterface, fSupportsRenderCursor, fSupportsMoveCursor);
5432	}
5433
5434
5435	/**
5436	* @interface_method_impl{PDMIDISPLAYPORT,pfnReportHostCursorPosition}
5437	*/
5438	static DECLCALLBACK(void) vgaR3PortReportHostCursorPosition(PPDMIDISPLAYPORT pInterface, uint32_t x, uint32_t y, bool fOutOfRange)
5439	{
5440	RT_NOREF(pInterface, x, y, fOutOfRange);
5441	}
5442
5443
5444	/**
5445	* @callback_method_impl{FNTMTIMERDEV, VGA Refresh Timer}
5446	*/
5447	static DECLCALLBACK(void) vgaR3TimerRefresh(PPDMDEVINS pDevIns, PTMTIMER pTimer, void *pvUser)
5448	{
5449	PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE);
5450	PVGASTATECC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PVGASTATECC);
5451	RT_NOREF(pvUser, pTimer);
5452
5453	if (pThis->fScanLineCfg & VBVASCANLINECFG_ENABLE_VSYNC_IRQ)
5454	VBVARaiseIrq(pDevIns, pThis, pThisCC, HGSMIHOSTFLAGS_VSYNC);
5455
5456	if (pThisCC->pDrv)
5457	pThisCC->pDrv->pfnRefresh(pThisCC->pDrv);
5458
5459	if (pThis->cMilliesRefreshInterval)
5460	PDMDevHlpTimerSetMillies(pDevIns, pThis->hRefreshTimer, pThis->cMilliesRefreshInterval);
5461
5462	# ifdef VBOX_WITH_VIDEOHWACCEL
5463	vbvaTimerCb(pDevIns, pThis, pThisCC);
5464	# endif
5465
5466	# ifdef VBOX_WITH_VMSVGA
5467	/*
5468	* Call the VMSVGA FIFO poller/watchdog so we can wake up the thread if
5469	* there is work to be done.
5470	*/
5471	if (pThis->svga.fFIFOThreadSleeping && pThis->svga.fEnabled && pThis->svga.fConfigured)
5472	vmsvgaR3FifoWatchdogTimer(pDevIns, pThis, pThisCC);
5473	# endif
5474	}
5475
5476	# ifdef VBOX_WITH_VMSVGA
5477
5478	/**
5479	* Helper for VMSVGA.
5480	*/
5481	int vgaR3RegisterVRAMHandler(PPDMDEVINS pDevIns, PVGASTATE pThis, uint64_t cbFrameBuffer)
5482	{
5483	Assert(pThis->GCPhysVRAM);
5484	int rc = PGMHandlerPhysicalRegister(PDMDevHlpGetVM(pDevIns),
5485	pThis->GCPhysVRAM, pThis->GCPhysVRAM + (cbFrameBuffer - 1),
5486	pThis->hLfbAccessHandlerType, pDevIns, pDevIns->pDevInsR0RemoveMe,
5487	pDevIns->pDevInsForRC, "VGA LFB");
5488
5489	AssertRC(rc);
5490	return rc;
5491	}
5492
5493
5494	/**
5495	* Helper for VMSVGA.
5496	*/
5497	int vgaR3UnregisterVRAMHandler(PPDMDEVINS pDevIns, PVGASTATE pThis)
5498	{
5499	Assert(pThis->GCPhysVRAM);
5500	int rc = PGMHandlerPhysicalDeregister(PDMDevHlpGetVM(pDevIns), pThis->GCPhysVRAM);
5501	AssertRC(rc);
5502	return rc;
5503	}
5504
5505	# endif /* VBOX_WITH_VMSVGA */
5506
5507
5508	/* -=-=-=-=-=- Ring 3: PCI Device -=-=-=-=-=- */
5509
5510	/**
5511	* @callback_method_impl{FNPCIIOREGIONMAP, Mapping/unmapping the VRAM MMI2 region}
5512	*/
5513	static DECLCALLBACK(int) vgaR3PciIORegionVRamMapUnmap(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t iRegion,
5514	RTGCPHYS GCPhysAddress, RTGCPHYS cb, PCIADDRESSSPACE enmType)
5515	{
5516	PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE);
5517	Log(("vgaR3PciIORegionVRamMapUnmap: iRegion=%d GCPhysAddress=%RGp cb=%RGp enmType=%d\n", iRegion, GCPhysAddress, cb, enmType));
5518	RT_NOREF(pPciDev, cb);
5519
5520	# ifdef VBOX_WITH_VMSVGA
5521	AssertReturn( iRegion == pThis->pciRegions.iVRAM
5522	&& ( enmType == PCI_ADDRESS_SPACE_MEM_PREFETCH
5523	\|\| (enmType == PCI_ADDRESS_SPACE_MEM && pThis->fVMSVGAEnabled && pThis->fStateLoaded)), VERR_INTERNAL_ERROR);
5524	# else
5525	AssertReturn( iRegion == pThis->pciRegions.iVRAM
5526	&& enmType == PCI_ADDRESS_SPACE_MEM_PREFETCH, VERR_INTERNAL_ERROR);
5527	# endif
5528
5529	Assert(pPciDev == pDevIns->apPciDevs[0]);
5530
5531	/* Note! We cannot take the device lock here as that would create a lock order
5532	problem as the caller has taken the PDM lock prior to calling us. If
5533	we did, we will get trouble later when raising interrupts while owning
5534	the device lock (e.g. vmsvgaR3FifoLoop). */
5535
5536	int rc;
5537	if (GCPhysAddress != NIL_RTGCPHYS)
5538	{
5539	/*
5540	* Mapping the VRAM.
5541	*/
5542	rc = PDMDevHlpMmio2Map(pDevIns, pThis->hMmio2VRam, GCPhysAddress);
5543	AssertLogRelRC(rc);
5544	if (RT_SUCCESS(rc))
5545	{
5546	# ifdef VBOX_WITH_VMSVGA
5547	if ( !pThis->svga.fEnabled
5548	\|\| ( pThis->svga.fEnabled
5549	&& pThis->svga.fVRAMTracking
5550	)
5551	)
5552	# endif
5553	{
5554	rc = PGMHandlerPhysicalRegister(PDMDevHlpGetVM(pDevIns), GCPhysAddress, GCPhysAddress + (pThis->vram_size - 1),
5555	pThis->hLfbAccessHandlerType, pDevIns, pDevIns->pDevInsR0RemoveMe,
5556	pDevIns->pDevInsForRC, "VGA LFB");
5557	AssertLogRelRC(rc);
5558	}
5559
5560	pThis->GCPhysVRAM = GCPhysAddress;
5561	pThis->vbe_regs[VBE_DISPI_INDEX_FB_BASE_HI] = GCPhysAddress >> 16;
5562
5563	rc = VINF_PCI_MAPPING_DONE; /* caller doesn't care about any other status, so no problem overwriting error here */
5564	}
5565	}
5566	else
5567	{
5568	/*
5569	* Unmapping of the VRAM in progress (caller will do that).
5570	* Deregister the access handler so PGM doesn't get upset.
5571	*/
5572	Assert(pThis->GCPhysVRAM);
5573	# ifdef VBOX_WITH_VMSVGA
5574	if ( !pThis->svga.fEnabled
5575	\|\| ( pThis->svga.fEnabled
5576	&& pThis->svga.fVRAMTracking
5577	)
5578	)
5579	# endif
5580	{
5581	rc = PGMHandlerPhysicalDeregister(PDMDevHlpGetVM(pDevIns), pThis->GCPhysVRAM);
5582	AssertRC(rc);
5583	}
5584	# ifdef VBOX_WITH_VMSVGA
5585	else
5586	rc = VINF_SUCCESS;
5587	# endif
5588	pThis->GCPhysVRAM = 0;
5589	/* NB: VBE_DISPI_INDEX_FB_BASE_HI is left unchanged here. */
5590	}
5591	return rc;
5592	}
5593
5594
5595	# ifdef VBOX_WITH_VMSVGA /* Currently not needed in the non-VMSVGA mode, but keeping it flexible for later. */
5596	/**
5597	* @interface_method_impl{PDMPCIDEV,pfnRegionLoadChangeHookR3}
5598	*/
5599	static DECLCALLBACK(int) vgaR3PciRegionLoadChangeHook(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t iRegion,
5600	uint64_t cbRegion, PCIADDRESSSPACE enmType,
5601	PFNPCIIOREGIONOLDSETTER pfnOldSetter, PFNPCIIOREGIONSWAP pfnSwapRegions)
5602	{
5603	PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE);
5604
5605	# ifdef VBOX_WITH_VMSVGA
5606	if (pThis->fVMSVGAEnabled)
5607	{
5608	/*
5609	* We messed up BAR order for the hybrid devices in 6.0 (see #9359).
5610	* It should have been compatible with the VBox VGA device and had the
5611	* VRAM region first and I/O second, but instead the I/O region ended
5612	* up first and VRAM second like the VMSVGA device.
5613	*
5614	* So, we have to detect that here and reconfigure the memory regions.
5615	* Region numbers are used in our (and the PCI bus') interfaction with
5616	* PGM, so PGM needs to be informed too.
5617	*/
5618	if ( iRegion == 0
5619	&& iRegion == pThis->pciRegions.iVRAM
5620	&& (enmType & PCI_ADDRESS_SPACE_IO))
5621	{
5622	LogRel(("VGA: Detected old BAR config, making adjustments.\n"));
5623
5624	/* Update the entries. */
5625	pThis->pciRegions.iIO = 0;
5626	pThis->pciRegions.iVRAM = 1;
5627
5628	/* Update PGM on the region number change so it won't barf when restoring state. */
5629	AssertLogRelReturn(pDevIns->CTX_SUFF(pHlp)->pfnMmio2ChangeRegionNo, VERR_VERSION_MISMATCH);
5630	int rc = pDevIns->CTX_SUFF(pHlp)->pfnMmio2ChangeRegionNo(pDevIns, pThis->hMmio2VRam, 1);
5631	AssertLogRelRCReturn(rc, rc);
5632	/** @todo Update the I/O port too, only currently we don't give a hoot about
5633	* the region number in the I/O port registrations so it can wait...
5634	* (Only visible in the 'info ioport' output IIRC). */
5635
5636	/* Update the calling PCI device. */
5637	AssertLogRelReturn(pfnSwapRegions, VERR_INTERNAL_ERROR_2);
5638	rc = pfnSwapRegions(pPciDev, 0, 1);
5639	AssertLogRelRCReturn(rc, rc);
5640
5641	return rc;
5642	}
5643
5644	/*
5645	* The VMSVGA changed the default FIFO size from 128KB to 2MB after 5.1.
5646	*/
5647	if (iRegion == pThis->pciRegions.iFIFO)
5648	{
5649	/* Make sure it's still 32-bit memory. Ignore fluxtuations in the prefetch flag. */
5650	AssertLogRelMsgReturn(!(enmType & (PCI_ADDRESS_SPACE_IO \| PCI_ADDRESS_SPACE_BAR64)), ("enmType=%#x\n", enmType),
5651	VERR_VGA_UNEXPECTED_PCI_REGION_LOAD_CHANGE);
5652
5653	/* If the size didn't change we're fine, so just return already. */
5654	if (cbRegion == pThis->svga.cbFIFO)
5655	return VINF_SUCCESS;
5656
5657	/* If the size is larger than the current configuration, refuse to load. */
5658	AssertLogRelMsgReturn(cbRegion <= pThis->svga.cbFIFOConfig,
5659	("cbRegion=%#RGp cbFIFOConfig=%#x cbFIFO=%#x\n",
5660	cbRegion, pThis->svga.cbFIFOConfig, pThis->svga.cbFIFO),
5661	VERR_SSM_LOAD_CONFIG_MISMATCH);
5662
5663	/* Adjust the size down. */
5664	int rc = PDMDevHlpMmio2Reduce(pDevIns, pThis->hMmio2VmSvgaFifo, cbRegion);
5665	AssertLogRelMsgRCReturn(rc,
5666	("cbRegion=%#RGp cbFIFOConfig=%#x cbFIFO=%#x: %Rrc\n",
5667	cbRegion, pThis->svga.cbFIFOConfig, pThis->svga.cbFIFO, rc),
5668	rc);
5669	pThis->svga.cbFIFO = cbRegion;
5670	return rc;
5671
5672	}
5673
5674	/*
5675	* VRAM used to be non-prefetchable till 6.1.0, so we end up here when restoring
5676	* states older than that with 6.1.0 and later. We just have to check that
5677	* the size and basic type matches, then return VINF_SUCCESS to ACK it.
5678	*/
5679	if (iRegion == pThis->pciRegions.iVRAM)
5680	{
5681	/* Make sure it's still 32-bit memory. Ignore fluxtuations in the prefetch flag. */
5682	AssertLogRelMsgReturn(!(enmType & (PCI_ADDRESS_SPACE_IO \| PCI_ADDRESS_SPACE_BAR64)), ("enmType=%#x\n", enmType),
5683	VERR_VGA_UNEXPECTED_PCI_REGION_LOAD_CHANGE);
5684	/* The size must be the same. */
5685	AssertLogRelMsgReturn(cbRegion == pThis->vram_size,
5686	("cbRegion=%#RGp vram_size=%#x\n", cbRegion, pThis->vram_size),
5687	VERR_SSM_LOAD_CONFIG_MISMATCH);
5688	return VINF_SUCCESS;
5689	}
5690
5691	/* Emulate callbacks for 5.1 and older saved states by recursion. */
5692	if (iRegion == UINT32_MAX)
5693	{
5694	int rc = vgaR3PciRegionLoadChangeHook(pDevIns, pPciDev, pThis->pciRegions.iFIFO, VMSVGA_FIFO_SIZE_OLD,
5695	PCI_ADDRESS_SPACE_MEM, NULL, NULL);
5696	if (RT_SUCCESS(rc))
5697	rc = pfnOldSetter(pPciDev, pThis->pciRegions.iFIFO, VMSVGA_FIFO_SIZE_OLD, PCI_ADDRESS_SPACE_MEM);
5698	return rc;
5699	}
5700	}
5701	# endif /* VBOX_WITH_VMSVGA */
5702
5703	return VERR_VGA_UNEXPECTED_PCI_REGION_LOAD_CHANGE;
5704	}
5705	# endif /* VBOX_WITH_VMSVGA */
5706
5707
5708	/* -=-=-=-=-=- Ring3: Misc Wrappers & Sidekicks -=-=-=-=-=- */
5709
5710	/**
5711	* Saves a important bits of the VGA device config.
5712	*
5713	* @param pHlp The device helpers (for SSM functions).
5714	* @param pThis The shared VGA instance data.
5715	* @param pSSM The saved state handle.
5716	*/
5717	static void vgaR3SaveConfig(PCPDMDEVHLPR3 pHlp, PVGASTATE pThis, PSSMHANDLE pSSM)
5718	{
5719	pHlp->pfnSSMPutU32(pSSM, pThis->vram_size);
5720	pHlp->pfnSSMPutU32(pSSM, pThis->cMonitors);
5721	}
5722
5723
5724	/**
5725	* @callback_method_impl{FNSSMDEVLIVEEXEC}
5726	*/
5727	static DECLCALLBACK(int) vgaR3LiveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t uPass)
5728	{
5729	PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE);
5730	Assert(uPass == 0); NOREF(uPass);
5731	vgaR3SaveConfig(pDevIns->pHlpR3, pThis, pSSM);
5732	return VINF_SSM_DONT_CALL_AGAIN;
5733	}
5734
5735
5736	/**
5737	* @callback_method_impl{FNSSMDEVSAVEPREP}
5738	*/
5739	static DECLCALLBACK(int) vgaR3SavePrep(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
5740	{
5741	# ifdef VBOX_WITH_VIDEOHWACCEL
5742	RT_NOREF(pSSM);
5743	return vboxVBVASaveStatePrep(pDevIns);
5744	# else
5745	RT_NOREF(pDevIns, pSSM);
5746	return VINF_SUCCESS;
5747	# endif
5748	}
5749
5750
5751	/**
5752	* @callback_method_impl{FNSSMDEVSAVEDONE}
5753	*/
5754	static DECLCALLBACK(int) vgaR3SaveDone(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
5755	{
5756	# ifdef VBOX_WITH_VIDEOHWACCEL
5757	RT_NOREF(pSSM);
5758	return vboxVBVASaveStateDone(pDevIns);
5759	# else
5760	RT_NOREF(pDevIns, pSSM);
5761	return VINF_SUCCESS;
5762	# endif
5763	}
5764
5765
5766	/**
5767	* @callback_method_impl{FNSSMDEVSAVEEXEC}
5768	*/
5769	static DECLCALLBACK(int) vgaR3SaveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
5770	{
5771	PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE);
5772	PVGASTATECC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PVGASTATECC);
5773	PCPDMDEVHLPR3 pHlp = pDevIns->pHlpR3;
5774
5775	# ifdef VBOX_WITH_VDMA
5776	vboxVDMASaveStateExecPrep(pThisCC->pVdma);
5777	# endif
5778
5779	vgaR3SaveConfig(pHlp, pThis, pSSM);
5780	vga_save(pHlp, pSSM, PDMDEVINS_2_DATA(pDevIns, PVGASTATE));
5781
5782	VGA_SAVED_STATE_PUT_MARKER(pSSM, 1);
5783	# ifdef VBOX_WITH_HGSMI
5784	pHlp->pfnSSMPutBool(pSSM, true);
5785	int rc = vboxVBVASaveStateExec(pDevIns, pSSM);
5786	# else
5787	int rc = pHlp->pfnSSMPutBool(pSSM, false);
5788	# endif
5789
5790	AssertRCReturn(rc, rc);
5791
5792	VGA_SAVED_STATE_PUT_MARKER(pSSM, 3);
5793	# ifdef VBOX_WITH_VDMA
5794	rc = pHlp->pfnSSMPutU32(pSSM, 1);
5795	AssertRCReturn(rc, rc);
5796	rc = vboxVDMASaveStateExecPerform(pHlp, pThisCC->pVdma, pSSM);
5797	# else
5798	rc = pHlp->pfnSSMPutU32(pSSM, 0);
5799	# endif
5800	AssertRCReturn(rc, rc);
5801
5802	# ifdef VBOX_WITH_VDMA
5803	vboxVDMASaveStateExecDone(pThisCC->pVdma);
5804	# endif
5805
5806	VGA_SAVED_STATE_PUT_MARKER(pSSM, 5);
5807	# ifdef VBOX_WITH_VMSVGA
5808	if (pThis->fVMSVGAEnabled)
5809	{
5810	rc = vmsvgaR3SaveExec(pDevIns, pSSM);
5811	AssertRCReturn(rc, rc);
5812	}
5813	# endif
5814	VGA_SAVED_STATE_PUT_MARKER(pSSM, 6);
5815
5816	return rc;
5817	}
5818
5819
5820	/**
5821	* @callback_method_impl{FNSSMDEVLOADPREP}
5822	*/
5823	static DECLCALLBACK(int) vgaR3LoadPrep(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
5824	{
5825	PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE);
5826	RT_NOREF(pSSM);
5827	pThis->fStateLoaded = true;
5828	return VINF_SUCCESS;
5829	}
5830
5831
5832	/**
5833	* @callback_method_impl{FNSSMDEVLOADEXEC}
5834	*/
5835	static DECLCALLBACK(int) vgaR3LoadExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
5836	{
5837	PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE);
5838	PVGASTATECC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PVGASTATECC);
5839	PCPDMDEVHLPR3 pHlp = pDevIns->pHlpR3;
5840	int rc;
5841
5842	pThis->fStateLoaded = true;
5843
5844	if (uVersion < VGA_SAVEDSTATE_VERSION_ANCIENT \|\| uVersion > VGA_SAVEDSTATE_VERSION)
5845	return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
5846
5847	if (uVersion > VGA_SAVEDSTATE_VERSION_HGSMI)
5848	{
5849	/* Check the config */
5850	uint32_t cbVRam;
5851	rc = pHlp->pfnSSMGetU32(pSSM, &cbVRam);
5852	AssertRCReturn(rc, rc);
5853	if (pThis->vram_size != cbVRam)
5854	return pHlp->pfnSSMSetCfgError(pSSM, RT_SRC_POS, N_("VRAM size changed: config=%#x state=%#x"), pThis->vram_size, cbVRam);
5855
5856	uint32_t cMonitors;
5857	rc = pHlp->pfnSSMGetU32(pSSM, &cMonitors);
5858	AssertRCReturn(rc, rc);
5859	if (pThis->cMonitors != cMonitors)
5860	return pHlp->pfnSSMSetCfgError(pSSM, RT_SRC_POS, N_("Monitor count changed: config=%u state=%u"), pThis->cMonitors, cMonitors);
5861	}
5862
5863	if (uPass == SSM_PASS_FINAL)
5864	{
5865	rc = vga_load(pHlp, pSSM, pThis, uVersion);
5866	if (RT_FAILURE(rc))
5867	return rc;
5868
5869	/*
5870	* Restore the HGSMI state, if present.
5871	*/
5872	VGA_SAVED_STATE_GET_MARKER_RETURN_ON_MISMATCH(pSSM, uVersion, 1);
5873	bool fWithHgsmi = uVersion == VGA_SAVEDSTATE_VERSION_HGSMI;
5874	if (uVersion > VGA_SAVEDSTATE_VERSION_HGSMI)
5875	{
5876	rc = pHlp->pfnSSMGetBool(pSSM, &fWithHgsmi);
5877	AssertRCReturn(rc, rc);
5878	}
5879	if (fWithHgsmi)
5880	{
5881	# ifdef VBOX_WITH_HGSMI
5882	rc = vboxVBVALoadStateExec(pDevIns, pSSM, uVersion);
5883	AssertRCReturn(rc, rc);
5884	# else
5885	return pHlp->pfnSSMSetCfgError(pSSM, RT_SRC_POS, N_("HGSMI is not compiled in, but it is present in the saved state"));
5886	# endif
5887	}
5888
5889	VGA_SAVED_STATE_GET_MARKER_RETURN_ON_MISMATCH(pSSM, uVersion, 3);
5890	if (uVersion >= VGA_SAVEDSTATE_VERSION_3D)
5891	{
5892	uint32_t u32;
5893	rc = pHlp->pfnSSMGetU32(pSSM, &u32);
5894	if (u32)
5895	{
5896	# ifdef VBOX_WITH_VDMA
5897	if (u32 == 1)
5898	{
5899	rc = vboxVDMASaveLoadExecPerform(pHlp, pThisCC->pVdma, pSSM, uVersion);
5900	AssertRCReturn(rc, rc);
5901	}
5902	else
5903	# endif
5904	{
5905	LogRel(("invalid CmdVbva version info\n"));
5906	return VERR_VERSION_MISMATCH;
5907	}
5908	}
5909	}
5910
5911	VGA_SAVED_STATE_GET_MARKER_RETURN_ON_MISMATCH(pSSM, uVersion, 5);
5912	# ifdef VBOX_WITH_VMSVGA
5913	if (pThis->fVMSVGAEnabled)
5914	{
5915	rc = vmsvgaR3LoadExec(pDevIns, pSSM, uVersion, uPass);
5916	AssertRCReturn(rc, rc);
5917	}
5918	# endif
5919	VGA_SAVED_STATE_GET_MARKER_RETURN_ON_MISMATCH(pSSM, uVersion, 6);
5920	}
5921	return VINF_SUCCESS;
5922	}
5923
5924
5925	/**
5926	* @@callback_method_impl{FNSSMDEVLOADDONE}
5927	*/
5928	static DECLCALLBACK(int) vgaR3LoadDone(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
5929	{
5930	PVGASTATECC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PVGASTATECC);
5931	PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE);
5932	int rc;
5933	RT_NOREF(pThisCC, pThis, pSSM);
5934
5935	# ifdef VBOX_WITH_HGSMI
5936	rc = vboxVBVALoadStateDone(pDevIns);
5937	AssertRCReturn(rc, rc);
5938	# ifdef VBOX_WITH_VDMA
5939	rc = vboxVDMASaveLoadDone(pThisCC->pVdma);
5940	AssertRCReturn(rc, rc);
5941	# endif
5942	/* Now update the current VBVA state which depends on VBE registers. vboxVBVALoadStateDone cleared the state. */
5943	VBVAOnVBEChanged(pThis, pThisCC);
5944	# endif
5945	# ifdef VBOX_WITH_VMSVGA
5946	if (pThis->fVMSVGAEnabled)
5947	{
5948	rc = vmsvgaR3LoadDone(pDevIns);
5949	AssertRCReturn(rc, rc);
5950	}
5951	# endif
5952	return VINF_SUCCESS;
5953	}
5954
5955
5956	/* -=-=-=-=-=- Ring 3: Device callbacks -=-=-=-=-=- */
5957
5958	/**
5959	* @interface_method_impl{PDMDEVREG,pfnResume}
5960	*/
5961	static DECLCALLBACK(void) vgaR3Resume(PPDMDEVINS pDevIns)
5962	{
5963	PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE);
5964	PVGASTATECC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PVGASTATECC);
5965	VBVAOnResume(pDevIns, pThis, pThisCC);
5966	}
5967
5968
5969	/**
5970	* @interface_method_impl{PDMDEVREG,pfnReset}
5971	*/
5972	static DECLCALLBACK(void) vgaR3Reset(PPDMDEVINS pDevIns)
5973	{
5974	PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE);
5975	PVGASTATECC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PVGASTATECC);
5976	char *pchStart;
5977	char *pchEnd;
5978	LogFlow(("vgaReset\n"));
5979
5980	if (pThisCC->pVdma)
5981	vboxVDMAReset(pThisCC->pVdma);
5982
5983	# ifdef VBOX_WITH_VMSVGA
5984	if (pThis->fVMSVGAEnabled)
5985	vmsvgaR3Reset(pDevIns);
5986	# endif
5987
5988	# ifdef VBOX_WITH_HGSMI
5989	VBVAReset(pDevIns, pThis, pThisCC);
5990	# endif
5991
5992
5993	/* Clear the VRAM ourselves. */
5994	if (pThisCC->pbVRam && pThis->vram_size)
5995	memset(pThisCC->pbVRam, 0, pThis->vram_size);
5996
5997	/*
5998	* Zero most of it.
5999	*
6000	* Unlike vga_reset we're leaving out a few members which we believe
6001	* must remain unchanged....
6002	*/
6003	/* 1st part. */
6004	pchStart = (char *)&pThis->latch;
6005	pchEnd = (char *)&pThis->invalidated_y_table;
6006	memset(pchStart, 0, pchEnd - pchStart);
6007
6008	/* 2nd part. */
6009	pchStart = (char *)&pThis->last_palette;
6010	pchEnd = (char *)&pThis->u32Marker;
6011	memset(pchStart, 0, pchEnd - pchStart);
6012
6013
6014	/*
6015	* Restore and re-init some bits.
6016	*/
6017	pThisCC->get_bpp = vgaR3GetBpp;
6018	pThisCC->get_offsets = vgaR3GetOffsets;
6019	pThisCC->get_resolution = vgaR3GetResolution;
6020	pThis->graphic_mode = -1; /* Force full update. */
6021	# ifdef CONFIG_BOCHS_VBE
6022	pThis->vbe_regs[VBE_DISPI_INDEX_ID] = VBE_DISPI_ID0;
6023	pThis->vbe_regs[VBE_DISPI_INDEX_VBOX_VIDEO] = 0;
6024	pThis->vbe_regs[VBE_DISPI_INDEX_FB_BASE_HI] = pThis->GCPhysVRAM >> 16;
6025	pThis->vbe_bank_max = (pThis->vram_size >> 16) - 1;
6026	# endif /* CONFIG_BOCHS_VBE */
6027	pThis->st00 = 0x70; /* Static except for bit 4. */
6028
6029	/*
6030	* Reset the LFB mapping.
6031	*/
6032	pThis->fLFBUpdated = false;
6033	if ( ( pDevIns->fRCEnabled
6034	\|\| pDevIns->fR0Enabled)
6035	&& pThis->GCPhysVRAM
6036	&& pThis->GCPhysVRAM != NIL_RTGCPHYS)
6037	{
6038	int rc = PGMHandlerPhysicalReset(PDMDevHlpGetVM(pDevIns), pThis->GCPhysVRAM);
6039	AssertRC(rc);
6040	}
6041	if (pThis->fRemappedVGA)
6042	{
6043	IOMMmioResetRegion(PDMDevHlpGetVM(pDevIns), pDevIns, pThis->hMmioLegacy);
6044	pThis->fRemappedVGA = false;
6045	}
6046
6047	/*
6048	* Reset the logo data.
6049	*/
6050	pThisCC->LogoCommand = LOGO_CMD_NOP;
6051	pThisCC->offLogoData = 0;
6052
6053	/* notify port handler */
6054	if (pThisCC->pDrv)
6055	{
6056	PDMDevHlpCritSectLeave(pDevIns, &pThis->CritSect); /* hack around lock order issue. */
6057	pThisCC->pDrv->pfnReset(pThisCC->pDrv);
6058	pThisCC->pDrv->pfnVBVAMousePointerShape(pThisCC->pDrv, false, false, 0, 0, 0, 0, NULL);
6059	PDMDevHlpCritSectEnter(pDevIns, &pThis->CritSect, VERR_IGNORED);
6060	}
6061
6062	/* Reset latched access mask. */
6063	pThis->uMaskLatchAccess = 0x3ff;
6064	pThis->cLatchAccesses = 0;
6065	pThis->u64LastLatchedAccess = 0;
6066	pThis->iMask = 0;
6067
6068	/* Reset retrace emulation. */
6069	memset(&pThis->retrace_state, 0, sizeof(pThis->retrace_state));
6070	}
6071
6072
6073	/**
6074	* @interface_method_impl{PDMDEVREG,pfnPowerOn}
6075	*/
6076	static DECLCALLBACK(void) vgaR3PowerOn(PPDMDEVINS pDevIns)
6077	{
6078	PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE);
6079	PVGASTATECC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PVGASTATECC);
6080	# ifdef VBOX_WITH_VMSVGA
6081	vmsvgaR3PowerOn(pDevIns);
6082	# endif
6083	VBVAOnResume(pDevIns, pThis, pThisCC);
6084	}
6085
6086
6087	/**
6088	* @interface_method_impl{PDMDEVREG,pfnPowerOff}
6089	*/
6090	static DECLCALLBACK(void) vgaR3PowerOff(PPDMDEVINS pDevIns)
6091	{
6092	PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE);
6093	PVGASTATECC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PVGASTATECC);
6094	RT_NOREF(pThis, pThisCC);
6095	# ifdef VBOX_WITH_VMSVGA
6096	vmsvgaR3PowerOff(pDevIns);
6097	# endif
6098	}
6099
6100
6101	/**
6102	* @interface_method_impl{PDMDEVREG,pfnRelocate}
6103	*/
6104	static DECLCALLBACK(void) vgaR3Relocate(PPDMDEVINS pDevIns, RTGCINTPTR offDelta)
6105	{
6106	# ifdef VBOX_WITH_RAW_MODE_KEEP
6107	if (offDelta)
6108	{
6109	PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE);
6110	LogFlow(("vgaRelocate: offDelta = %08X\n", offDelta));
6111
6112	pThisRC->pbVRam += offDelta;
6113	pThis->pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
6114	}
6115	# else
6116	RT_NOREF(pDevIns, offDelta);
6117	# endif
6118	}
6119
6120
6121	/**
6122	* @interface_method_impl{PDMDEVREG,pfnAttach}
6123	*
6124	* This is like plugging in the monitor after turning on the PC.
6125	*/
6126	static DECLCALLBACK(int) vgaAttach(PPDMDEVINS pDevIns, unsigned iLUN, uint32_t fFlags)
6127	{
6128	PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE);
6129	PVGASTATECC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PVGASTATECC);
6130
6131	RT_NOREF(pThis);
6132
6133	AssertMsgReturn(fFlags & PDM_TACH_FLAGS_NOT_HOT_PLUG,
6134	("VGA device does not support hotplugging\n"),
6135	VERR_INVALID_PARAMETER);
6136
6137	switch (iLUN)
6138	{
6139	/* LUN #0: Display port. */
6140	case 0:
6141	{
6142	int rc = PDMDevHlpDriverAttach(pDevIns, iLUN, &pThisCC->IBase, &pThisCC->pDrvBase, "Display Port");
6143	if (RT_SUCCESS(rc))
6144	{
6145	pThisCC->pDrv = PDMIBASE_QUERY_INTERFACE(pThisCC->pDrvBase, PDMIDISPLAYCONNECTOR);
6146	if (pThisCC->pDrv)
6147	{
6148	/* pThisCC->pDrv->pbData can be NULL when there is no framebuffer. */
6149	if ( pThisCC->pDrv->pfnRefresh
6150	&& pThisCC->pDrv->pfnResize
6151	&& pThisCC->pDrv->pfnUpdateRect)
6152	rc = VINF_SUCCESS;
6153	else
6154	{
6155	Assert(pThisCC->pDrv->pfnRefresh);
6156	Assert(pThisCC->pDrv->pfnResize);
6157	Assert(pThisCC->pDrv->pfnUpdateRect);
6158	pThisCC->pDrv = NULL;
6159	pThisCC->pDrvBase = NULL;
6160	rc = VERR_INTERNAL_ERROR;
6161	}
6162	# ifdef VBOX_WITH_VIDEOHWACCEL
6163	if(rc == VINF_SUCCESS)
6164	{
6165	rc = vbvaVHWAConstruct(pDevIns, pThis, pThisCC);
6166	if (rc != VERR_NOT_IMPLEMENTED)
6167	AssertRC(rc);
6168	}
6169	# endif
6170	}
6171	else
6172	{
6173	AssertMsgFailed(("LUN #0 doesn't have a display connector interface! rc=%Rrc\n", rc));
6174	pThisCC->pDrvBase = NULL;
6175	rc = VERR_PDM_MISSING_INTERFACE;
6176	}
6177	}
6178	else if (rc == VERR_PDM_NO_ATTACHED_DRIVER)
6179	{
6180	Log(("%s/%d: warning: no driver attached to LUN #0!\n", pDevIns->pReg->szName, pDevIns->iInstance));
6181	rc = VINF_SUCCESS;
6182	}
6183	else
6184	AssertLogRelMsgFailed(("Failed to attach LUN #0! rc=%Rrc\n", rc));
6185	return rc;
6186	}
6187
6188	default:
6189	AssertMsgFailed(("Invalid LUN #%d\n", iLUN));
6190	return VERR_PDM_NO_SUCH_LUN;
6191	}
6192	}
6193
6194
6195	/**
6196	* @interface_method_impl{PDMDEVREG,pfnDetach}
6197	*
6198	* This is like unplugging the monitor while the PC is still running.
6199	*/
6200	static DECLCALLBACK(void) vgaDetach(PPDMDEVINS pDevIns, unsigned iLUN, uint32_t fFlags)
6201	{
6202	PVGASTATECC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PVGASTATECC);
6203	AssertMsg(fFlags & PDM_TACH_FLAGS_NOT_HOT_PLUG, ("VGA device does not support hotplugging\n"));
6204	RT_NOREF(fFlags);
6205
6206	/*
6207	* Reset the interfaces and update the controller state.
6208	*/
6209	switch (iLUN)
6210	{
6211	/* LUN #0: Display port. */
6212	case 0:
6213	pThisCC->pDrv = NULL;
6214	pThisCC->pDrvBase = NULL;
6215	break;
6216
6217	default:
6218	AssertMsgFailed(("Invalid LUN #%d\n", iLUN));
6219	break;
6220	}
6221	}
6222
6223
6224	/**
6225	* @interface_method_impl{PDMDEVREG,pfnDestruct}
6226	*/
6227	static DECLCALLBACK(int) vgaR3Destruct(PPDMDEVINS pDevIns)
6228	{
6229	PDMDEV_CHECK_VERSIONS_RETURN_QUIET(pDevIns);
6230	PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE);
6231	PVGASTATECC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PVGASTATECC);
6232	LogFlow(("vgaR3Destruct:\n"));
6233
6234	# ifdef VBOX_WITH_VDMA
6235	if (pThisCC->pVdma)
6236	vboxVDMADestruct(pThisCC->pVdma);
6237	# endif
6238
6239	# ifdef VBOX_WITH_VMSVGA
6240	if (pThis->fVMSVGAEnabled)
6241	vmsvgaR3Destruct(pDevIns);
6242	# endif
6243
6244	# ifdef VBOX_WITH_HGSMI
6245	VBVADestroy(pThisCC);
6246	# endif
6247
6248	/*
6249	* Free MM heap pointers.
6250	*/
6251	if (pThisCC->pbVBEExtraData)
6252	{
6253	PDMDevHlpMMHeapFree(pDevIns, pThisCC->pbVBEExtraData);
6254	pThisCC->pbVBEExtraData = NULL;
6255	}
6256	if (pThisCC->pbVgaBios)
6257	{
6258	PDMDevHlpMMHeapFree(pDevIns, pThisCC->pbVgaBios);
6259	pThisCC->pbVgaBios = NULL;
6260	}
6261
6262	if (pThisCC->pszVgaBiosFile)
6263	{
6264	PDMDevHlpMMHeapFree(pDevIns, pThisCC->pszVgaBiosFile);
6265	pThisCC->pszVgaBiosFile = NULL;
6266	}
6267
6268	if (pThisCC->pszLogoFile)
6269	{
6270	PDMDevHlpMMHeapFree(pDevIns, pThisCC->pszLogoFile);
6271	pThisCC->pszLogoFile = NULL;
6272	}
6273
6274	if (pThisCC->pbLogo)
6275	{
6276	PDMDevHlpMMHeapFree(pDevIns, pThisCC->pbLogo);
6277	pThisCC->pbLogo = NULL;
6278	}
6279
6280	# if defined(VBOX_WITH_VIDEOHWACCEL) \|\| defined(VBOX_WITH_VDMA) \|\| defined(VBOX_WITH_WDDM)
6281	PDMDevHlpCritSectDelete(pDevIns, &pThis->CritSectIRQ);
6282	# endif
6283	PDMDevHlpCritSectDelete(pDevIns, &pThis->CritSect);
6284	return VINF_SUCCESS;
6285	}
6286
6287
6288	/**
6289	* Adjust VBE mode information
6290	*
6291	* Depending on the configured VRAM size, certain parts of VBE mode
6292	* information must be updated.
6293	*
6294	* @param pThis The device instance data.
6295	* @param pMode The mode information structure.
6296	*/
6297	static void vgaR3AdjustModeInfo(PVGASTATE pThis, ModeInfoListItem *pMode)
6298	{
6299	/* For 4bpp modes, the planes are "stacked" on top of each other. */
6300	unsigned bpl = pMode->info.BytesPerScanLine * pMode->info.NumberOfPlanes;
6301	/* The "number of image pages" is really the max page index... */
6302	unsigned maxPage = pThis->vram_size / (pMode->info.YResolution * bpl) - 1;
6303	if (maxPage > 255)
6304	maxPage = 255; /* 8-bit value. */
6305	pMode->info.NumberOfImagePages = maxPage;
6306	pMode->info.LinNumberOfPages = maxPage;
6307	}
6308
6309
6310	/**
6311	* @interface_method_impl{PDMDEVREG,pfnConstruct}
6312	*/
6313	static DECLCALLBACK(int) vgaR3Construct(PPDMDEVINS pDevIns, int iInstance, PCFGMNODE pCfg)
6314	{
6315	PDMDEV_CHECK_VERSIONS_RETURN(pDevIns);
6316	PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE);
6317	PVGASTATECC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PVGASTATECC);
6318	PCPDMDEVHLPR3 pHlp = pDevIns->pHlpR3;
6319	int rc;
6320	unsigned i;
6321	uint32_t cCustomModes;
6322	uint32_t cyReduction;
6323	uint32_t cbPitch;
6324	PVBEHEADER pVBEDataHdr;
6325	ModeInfoListItem *pCurMode;
6326	unsigned cb;
6327
6328	Assert(iInstance == 0);
6329
6330	/*
6331	* Init static data.
6332	*/
6333	static bool s_fExpandDone = false;
6334	if (!s_fExpandDone)
6335	{
6336	s_fExpandDone = true;
6337	vgaR3InitExpand();
6338	}
6339
6340	/*
6341	* Validate configuration.
6342	*/
6343	static const char s_szMscWorkaround[] = "VRamSize"
6344	"\|MonitorCount"
6345	"\|FadeIn"
6346	"\|FadeOut"
6347	"\|LogoTime"
6348	"\|LogoFile"
6349	"\|ShowBootMenu"
6350	"\|BiosRom"
6351	"\|RealRetrace"
6352	"\|CustomVideoModes"
6353	"\|HeightReduction"
6354	"\|CustomVideoMode1"
6355	"\|CustomVideoMode2"
6356	"\|CustomVideoMode3"
6357	"\|CustomVideoMode4"
6358	"\|CustomVideoMode5"
6359	"\|CustomVideoMode6"
6360	"\|CustomVideoMode7"
6361	"\|CustomVideoMode8"
6362	"\|CustomVideoMode9"
6363	"\|CustomVideoMode10"
6364	"\|CustomVideoMode11"
6365	"\|CustomVideoMode12"
6366	"\|CustomVideoMode13"
6367	"\|CustomVideoMode14"
6368	"\|CustomVideoMode15"
6369	"\|CustomVideoMode16"
6370	"\|MaxBiosXRes"
6371	"\|MaxBiosYRes"
6372	# ifdef VBOX_WITH_VMSVGA
6373	"\|VMSVGAEnabled"
6374	"\|VMSVGA10"
6375	"\|VMSVGAPciId"
6376	"\|VMSVGAPciBarLayout"
6377	"\|VMSVGAFifoSize"
6378	# endif
6379	# ifdef VBOX_WITH_VMSVGA3D
6380	"\|VMSVGA3dEnabled"
6381	"\|VMSVGA3dOverlayEnabled"
6382	# endif
6383	"\|SuppressNewYearSplash"
6384	"\|3DEnabled";
6385
6386	PDMDEV_VALIDATE_CONFIG_RETURN(pDevIns, s_szMscWorkaround, "");
6387
6388	/*
6389	* Init state data.
6390	*/
6391	rc = pHlp->pfnCFGMQueryU32Def(pCfg, "VRamSize", &pThis->vram_size, VGA_VRAM_DEFAULT);
6392	AssertLogRelRCReturn(rc, rc);
6393	if (pThis->vram_size > VGA_VRAM_MAX)
6394	return PDMDevHlpVMSetError(pDevIns, VERR_INVALID_PARAMETER, RT_SRC_POS,
6395	"VRamSize is too large, %#x, max %#x", pThis->vram_size, VGA_VRAM_MAX);
6396	if (pThis->vram_size < VGA_VRAM_MIN)
6397	return PDMDevHlpVMSetError(pDevIns, VERR_INVALID_PARAMETER, RT_SRC_POS,
6398	"VRamSize is too small, %#x, max %#x", pThis->vram_size, VGA_VRAM_MIN);
6399	if (pThis->vram_size & (_256K - 1)) /* Make sure there are no partial banks even in planar modes. */
6400	return PDMDevHlpVMSetError(pDevIns, VERR_INVALID_PARAMETER, RT_SRC_POS,
6401	"VRamSize is not a multiple of 256K (%#x)", pThis->vram_size);
6402
6403	rc = pHlp->pfnCFGMQueryU32Def(pCfg, "MonitorCount", &pThis->cMonitors, 1);
6404	AssertLogRelRCReturn(rc, rc);
6405
6406	Log(("VGA: VRamSize=%#x fGCenabled=%RTbool fR0Enabled=%RTbool\n", pThis->vram_size, pDevIns->fRCEnabled, pDevIns->fR0Enabled));
6407
6408	rc = pHlp->pfnCFGMQueryBoolDef(pCfg, "3DEnabled", &pThis->f3DEnabled, false);
6409	AssertLogRelRCReturn(rc, rc);
6410	Log(("VGA: f3DEnabled=%RTbool\n", pThis->f3DEnabled));
6411
6412	# ifdef VBOX_WITH_VMSVGA
6413	rc = pHlp->pfnCFGMQueryBoolDef(pCfg, "VMSVGAEnabled", &pThis->fVMSVGAEnabled, false);
6414	AssertLogRelRCReturn(rc, rc);
6415	Log(("VMSVGA: VMSVGAEnabled = %d\n", pThis->fVMSVGAEnabled));
6416
6417	rc = pHlp->pfnCFGMQueryBoolDef(pCfg, "VMSVGA10", &pThis->fVMSVGA10, false);
6418	AssertLogRelRCReturn(rc, rc);
6419	Log(("VMSVGA: VMSVGA10 = %d\n", pThis->fVMSVGA10));
6420
6421	rc = pHlp->pfnCFGMQueryBoolDef(pCfg, "VMSVGAPciId", &pThis->fVMSVGAPciId, false);
6422	AssertLogRelRCReturn(rc, rc);
6423	Log(("VMSVGA: VMSVGAPciId = %d\n", pThis->fVMSVGAPciId));
6424
6425	rc = pHlp->pfnCFGMQueryBoolDef(pCfg, "VMSVGAPciBarLayout", &pThis->fVMSVGAPciBarLayout, pThis->fVMSVGAPciId);
6426	AssertLogRelRCReturn(rc, rc);
6427	Log(("VMSVGA: VMSVGAPciBarLayout = %d\n", pThis->fVMSVGAPciBarLayout));
6428
6429	rc = pHlp->pfnCFGMQueryU32Def(pCfg, "VMSVGAFifoSize", &pThis->svga.cbFIFO, VMSVGA_FIFO_SIZE);
6430	AssertLogRelRCReturn(rc, rc);
6431	AssertLogRelMsgReturn(pThis->svga.cbFIFO >= _128K, ("cbFIFO=%#x\n", pThis->svga.cbFIFO), VERR_OUT_OF_RANGE);
6432	AssertLogRelMsgReturn(pThis->svga.cbFIFO <= _16M, ("cbFIFO=%#x\n", pThis->svga.cbFIFO), VERR_OUT_OF_RANGE);
6433	AssertLogRelMsgReturn(RT_IS_POWER_OF_TWO(pThis->svga.cbFIFO), ("cbFIFO=%#x\n", pThis->svga.cbFIFO), VERR_NOT_POWER_OF_TWO);
6434	pThis->svga.cbFIFOConfig = pThis->svga.cbFIFO;
6435	Log(("VMSVGA: VMSVGAFifoSize = %#x (%'u)\n", pThis->svga.cbFIFO, pThis->svga.cbFIFO));
6436	# endif
6437	# ifdef VBOX_WITH_VMSVGA3D
6438	rc = pHlp->pfnCFGMQueryBoolDef(pCfg, "VMSVGA3dEnabled", &pThis->svga.f3DEnabled, false);
6439	AssertLogRelRCReturn(rc, rc);
6440	Log(("VMSVGA: VMSVGA3dEnabled = %d\n", pThis->svga.f3DEnabled));
6441
6442	rc = pHlp->pfnCFGMQueryBoolDef(pCfg, "VMSVGA3dOverlayEnabled", &pThis->svga.f3DOverlayEnabled, false);
6443	AssertLogRelRCReturn(rc, rc);
6444	Log(("VMSVGA: VMSVGA3dOverlayEnabled = %d\n", pThis->svga.f3DOverlayEnabled));
6445	# endif
6446
6447	# ifdef VBOX_WITH_VMSVGA
6448	if (pThis->fVMSVGAPciBarLayout)
6449	{
6450	pThis->pciRegions.iIO = 0;
6451	pThis->pciRegions.iVRAM = 1;
6452	}
6453	else
6454	{
6455	pThis->pciRegions.iVRAM = 0;
6456	pThis->pciRegions.iIO = 1;
6457	}
6458	pThis->pciRegions.iFIFO = 2;
6459	# else
6460	pThis->pciRegions.iVRAM = 0;
6461	# endif
6462
6463	pThisCC->pDevIns = pDevIns;
6464
6465	vgaR3Reset(pDevIns);
6466
6467	/* The PCI devices configuration. */
6468	PPDMPCIDEV pPciDev = pDevIns->apPciDevs[0];
6469	PDMPCIDEV_ASSERT_VALID(pDevIns, pPciDev);
6470
6471	# ifdef VBOX_WITH_VMSVGA
6472	if (pThis->fVMSVGAEnabled)
6473	{
6474	/* Extend our VGA device with VMWare SVGA functionality. */
6475	if (pThis->fVMSVGAPciId)
6476	{
6477	PDMPciDevSetVendorId(pPciDev, PCI_VENDOR_ID_VMWARE);
6478	PDMPciDevSetDeviceId(pPciDev, PCI_DEVICE_ID_VMWARE_SVGA2);
6479	}
6480	else
6481	{
6482	PDMPciDevSetVendorId(pPciDev, 0x80ee); /* PCI vendor, just a free bogus value */
6483	PDMPciDevSetDeviceId(pPciDev, 0xbeef);
6484	}
6485	PDMPciDevSetSubSystemVendorId(pPciDev, PCI_VENDOR_ID_VMWARE);
6486	PDMPciDevSetSubSystemId(pPciDev, PCI_DEVICE_ID_VMWARE_SVGA2);
6487	}
6488	else
6489	# endif /* VBOX_WITH_VMSVGA */
6490	{
6491	PDMPciDevSetVendorId(pPciDev, 0x80ee); /* PCI vendor, just a free bogus value */
6492	PDMPciDevSetDeviceId(pPciDev, 0xbeef);
6493	}
6494	PDMPciDevSetClassSub(pPciDev, 0x00); /* VGA controller */
6495	PDMPciDevSetClassBase(pPciDev, 0x03);
6496	PDMPciDevSetHeaderType(pPciDev, 0x00);
6497	# if defined(VBOX_WITH_HGSMI) && (defined(VBOX_WITH_VIDEOHWACCEL) \|\| defined(VBOX_WITH_VDMA) \|\| defined(VBOX_WITH_WDDM))
6498	PDMPciDevSetInterruptPin(pPciDev, 1);
6499	# endif
6500
6501	/* the interfaces. */
6502	pThisCC->IBase.pfnQueryInterface = vgaR3PortQueryInterface;
6503
6504	pThisCC->IPort.pfnUpdateDisplay = vgaR3PortUpdateDisplay;
6505	pThisCC->IPort.pfnUpdateDisplayAll = vgaR3PortUpdateDisplayAll;
6506	pThisCC->IPort.pfnQueryVideoMode = vgaR3PortQueryVideoMode;
6507	pThisCC->IPort.pfnSetRefreshRate = vgaR3PortSetRefreshRate;
6508	pThisCC->IPort.pfnTakeScreenshot = vgaR3PortTakeScreenshot;
6509	pThisCC->IPort.pfnFreeScreenshot = vgaR3PortFreeScreenshot;
6510	pThisCC->IPort.pfnDisplayBlt = vgaR3PortDisplayBlt;
6511	pThisCC->IPort.pfnUpdateDisplayRect = vgaR3PortUpdateDisplayRect;
6512	pThisCC->IPort.pfnCopyRect = vgaR3PortCopyRect;
6513	pThisCC->IPort.pfnSetRenderVRAM = vgaR3PortSetRenderVRAM;
6514	pThisCC->IPort.pfnSetViewport = NULL;
6515	pThisCC->IPort.pfnReportMonitorPositions = NULL;
6516	# ifdef VBOX_WITH_VMSVGA
6517	if (pThis->fVMSVGAEnabled)
6518	{
6519	pThisCC->IPort.pfnSetViewport = vmsvgaR3PortSetViewport;
6520	pThisCC->IPort.pfnReportMonitorPositions = vmsvgaR3PortReportMonitorPositions;
6521	}
6522	# endif
6523	pThisCC->IPort.pfnSendModeHint = vbvaR3PortSendModeHint;
6524	pThisCC->IPort.pfnReportHostCursorCapabilities = vgaR3PortReportHostCursorCapabilities;
6525	pThisCC->IPort.pfnReportHostCursorPosition = vgaR3PortReportHostCursorPosition;
6526
6527	# if defined(VBOX_WITH_HGSMI) && defined(VBOX_WITH_VIDEOHWACCEL)
6528	pThisCC->IVBVACallbacks.pfnVHWACommandCompleteAsync = vbvaR3VHWACommandCompleteAsync;
6529	# endif
6530
6531	pThisCC->ILeds.pfnQueryStatusLed = vgaR3PortQueryStatusLed;
6532	pThis->Led3D.u32Magic = PDMLED_MAGIC;
6533
6534	/*
6535	* We use our own critical section to avoid unncessary pointer indirections
6536	* in interface methods (as well as for historical reasons).
6537	*/
6538	rc = PDMDevHlpCritSectInit(pDevIns, &pThis->CritSect, RT_SRC_POS, "VGA#%u", iInstance);
6539	AssertRCReturn(rc, rc);
6540	rc = PDMDevHlpSetDeviceCritSect(pDevIns, &pThis->CritSect);
6541	AssertRCReturn(rc, rc);
6542
6543	# ifdef VBOX_WITH_HGSMI
6544	/*
6545	* This critical section is used by vgaR3IOPortHgsmiWrite, VBVARaiseIrq and VBVAOnResume
6546	* for some IRQ related synchronization.
6547	*/
6548	rc = PDMDevHlpCritSectInit(pDevIns, &pThis->CritSectIRQ, RT_SRC_POS, "VGA#%u_IRQ", iInstance);
6549	AssertRCReturn(rc, rc);
6550	# endif
6551
6552	/*
6553	* PCI device registration.
6554	*/
6555	rc = PDMDevHlpPCIRegister(pDevIns, pPciDev);
6556	if (RT_FAILURE(rc))
6557	return rc;
6558	/AssertMsg(pThis->Dev.uDevFn == 16 \|\| iInstance != 0, ("pThis->Dev.uDevFn=%d\n", pThis->Dev.uDevFn));/
6559	if (pPciDev->uDevFn != 16 && iInstance == 0)
6560	Log(("!!WARNING!!: pThis->dev.uDevFn=%d (ignore if testcase or not started by Main)\n", pPciDev->uDevFn));
6561
6562	# ifdef VBOX_WITH_VMSVGA
6563	pThis->hIoPortVmSvga = NIL_IOMIOPORTHANDLE;
6564	pThis->hMmio2VmSvgaFifo = NIL_PGMMMIO2HANDLE;
6565	if (pThis->fVMSVGAEnabled)
6566	{
6567	/* Register the io command ports. */
6568	rc = PDMDevHlpPCIIORegionCreateIo(pDevIns, pThis->pciRegions.iIO, 0x10, vmsvgaIOWrite, vmsvgaIORead, NULL /pvUser/,
6569	"VMSVGA", NULL /paExtDescs/, &pThis->hIoPortVmSvga);
6570	AssertRCReturn(rc, rc);
6571
6572	rc = PDMDevHlpPCIIORegionCreateMmio2Ex(pDevIns, pThis->pciRegions.iFIFO, pThis->svga.cbFIFO,
6573	PCI_ADDRESS_SPACE_MEM, 0 /fFlags/, vmsvgaR3PciIORegionFifoMapUnmap,
6574	"VMSVGA-FIFO", (void **)&pThisCC->svga.pau32FIFO, &pThis->hMmio2VmSvgaFifo);
6575	AssertRCReturn(rc, PDMDevHlpVMSetError(pDevIns, rc, RT_SRC_POS,
6576	N_("Failed to create VMSVGA FIFO (%u bytes)"), pThis->svga.cbFIFO));
6577
6578	pPciDev->pfnRegionLoadChangeHookR3 = vgaR3PciRegionLoadChangeHook;
6579	}
6580	# endif /* VBOX_WITH_VMSVGA */
6581
6582	/*
6583	* Allocate VRAM and create a PCI region for it.
6584	*/
6585	rc = PDMDevHlpPCIIORegionCreateMmio2Ex(pDevIns, pThis->pciRegions.iVRAM, pThis->vram_size,
6586	PCI_ADDRESS_SPACE_MEM_PREFETCH, 0 /fFlags/, vgaR3PciIORegionVRamMapUnmap,
6587	"VRam", (void **)&pThisCC->pbVRam, &pThis->hMmio2VRam);
6588	AssertLogRelRCReturn(rc, PDMDevHlpVMSetError(pDevIns, rc, RT_SRC_POS,
6589	N_("Failed to allocate %u bytes of VRAM"), pThis->vram_size));
6590
6591	/*
6592	* Register access handler types for tracking dirty VRAM pages.
6593	*/
6594	rc = PDMDevHlpPGMHandlerPhysicalTypeRegister(pDevIns, PGMPHYSHANDLERKIND_WRITE,
6595	vgaLFBAccessHandler,
6596	"vgaLFBAccessHandler", "vgaLbfAccessPfHandler",
6597	"vgaLFBAccessHandler", "vgaLbfAccessPfHandler",
6598	"VGA LFB", &pThis->hLfbAccessHandlerType);
6599	AssertRCReturn(rc, rc);
6600
6601	/*
6602	* Register I/O ports.
6603	*/
6604	# define REG_PORT(a_uPort, a_cPorts, a_pfnWrite, a_pfnRead, a_szDesc, a_phIoPort) do { \
6605	rc = PDMDevHlpIoPortCreateFlagsAndMap(pDevIns, a_uPort, a_cPorts, IOM_IOPORT_F_ABS, \
6606	a_pfnWrite, a_pfnRead, "VGA - " a_szDesc, NULL /paExtDescs/, a_phIoPort); \
6607	AssertRCReturn(rc, rc); \
6608	} while (0)
6609	REG_PORT(0x3c0, 2, vgaIoPortArWrite, vgaIoPortArRead, "Attribute Controller", &pThis->hIoPortAr);
6610	REG_PORT(0x3c2, 1, vgaIoPortMsrWrite, vgaIoPortSt00Read, "MSR / ST00", &pThis->hIoPortMsrSt00);
6611	REG_PORT(0x3c3, 1, vgaIoPortUnusedWrite, vgaIoPortUnusedRead, "0x3c3", &pThis->hIoPort3c3);
6612	REG_PORT(0x3c4, 2, vgaIoPortSrWrite, vgaIoPortSrRead, "Sequencer", &pThis->hIoPortSr);
6613	REG_PORT(0x3c6, 4, vgaIoPortDacWrite, vgaIoPortDacRead, "DAC", &pThis->hIoPortDac);
6614	REG_PORT(0x3ca, 4, vgaIoPortPosWrite, vgaIoPortPosRead, "Graphics Position", /?/ &pThis->hIoPortPos);
6615	REG_PORT(0x3ce, 2, vgaIoPortGrWrite, vgaIoPortGrRead, "Graphics Controller", &pThis->hIoPortGr);
6616
6617	/* Note! Ralf Brown lists 0x3b0-0x3b1, 0x3b2-0x3b3 and 0x3b6-0x3b7 as "the same as" 0x3b4-0x3b5. */
6618	REG_PORT(0x3b4, 2, vgaIoPortMdaCrtWrite, vgaIoPortMdaCrtRead, "MDA CRT control", &pThis->hIoPortMdaCrt);
6619	REG_PORT(0x3ba, 1, vgaIoPortMdaFcrWrite, vgaIoPortMdaStRead, "MDA feature/status", &pThis->hIoPortMdaFcrSt);
6620	REG_PORT(0x3d4, 2, vgaIoPortCgaCrtWrite, vgaIoPortCgaCrtRead, "CGA CRT control", &pThis->hIoPortCgaCrt);
6621	REG_PORT(0x3da, 1, vgaIoPortCgaFcrWrite, vgaIoPortCgaStRead, "CGA Feature / status", &pThis->hIoPortCgaFcrSt);
6622
6623	# ifdef CONFIG_BOCHS_VBE
6624	REG_PORT(0x1ce, 1, vgaIoPortWriteVbeIndex, vgaIoPortReadVbeIndex, "VBE Index", &pThis->hIoPortVbeIndex);
6625	REG_PORT(0x1cf, 1, vgaIoPortWriteVbeData, vgaIoPortReadVbeData, "VBE Data", &pThis->hIoPortVbeData);
6626	# endif /* CONFIG_BOCHS_VBE */
6627
6628	# ifdef VBOX_WITH_HGSMI
6629	/* Use reserved VGA IO ports for HGSMI. */
6630	REG_PORT(VGA_PORT_HGSMI_HOST, 4, vgaR3IOPortHgsmiWrite, vgaR3IOPortHgmsiRead, "HGSMI host (3b0-3b3)", &pThis->hIoPortHgsmiHost);
6631	REG_PORT(VGA_PORT_HGSMI_GUEST, 4, vgaR3IOPortHgsmiWrite, vgaR3IOPortHgmsiRead, "HGSMI guest (3d0-3d3)", &pThis->hIoPortHgsmiGuest);
6632	# endif /* VBOX_WITH_HGSMI */
6633
6634	# undef REG_PORT
6635
6636	/* vga bios */
6637	rc = PDMDevHlpIoPortCreateAndMap(pDevIns, VBE_PRINTF_PORT, 1 /cPorts/, vgaIoPortWriteBios, vgaIoPortReadBios,
6638	"VGA BIOS debug/panic", NULL /paExtDescs/, &pThis->hIoPortBios);
6639	AssertRCReturn(rc, rc);
6640
6641	/*
6642	* The MDA/CGA/EGA/VGA/whatever fixed MMIO area.
6643	*/
6644	rc = PDMDevHlpMmioCreateExAndMap(pDevIns, 0x000a0000, 0x00020000,
6645	IOMMMIO_FLAGS_READ_PASSTHRU \| IOMMMIO_FLAGS_WRITE_PASSTHRU \| IOMMMIO_FLAGS_ABS,
6646	NULL /pPciDev/, UINT32_MAX /iPciRegion/,
6647	vgaMmioWrite, vgaMmioRead, vgaMmioFill, NULL /pvUser/,
6648	"VGA - VGA Video Buffer", &pThis->hMmioLegacy);
6649	AssertRCReturn(rc, rc);
6650
6651	/*
6652	* Get the VGA BIOS ROM file name.
6653	*/
6654	rc = pHlp->pfnCFGMQueryStringAlloc(pCfg, "BiosRom", &pThisCC->pszVgaBiosFile);
6655	if (rc == VERR_CFGM_VALUE_NOT_FOUND)
6656	{
6657	pThisCC->pszVgaBiosFile = NULL;
6658	rc = VINF_SUCCESS;
6659	}
6660	else if (RT_FAILURE(rc))
6661	return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Querying \"BiosRom\" as a string failed"));
6662	else if (!*pThisCC->pszVgaBiosFile)
6663	{
6664	PDMDevHlpMMHeapFree(pDevIns, pThisCC->pszVgaBiosFile);
6665	pThisCC->pszVgaBiosFile = NULL;
6666	}
6667
6668	/*
6669	* Determine the VGA BIOS ROM size, open specified ROM file in the process.
6670	*/
6671	RTFILE FileVgaBios = NIL_RTFILE;
6672	if (pThisCC->pszVgaBiosFile)
6673	{
6674	rc = RTFileOpen(&FileVgaBios, pThisCC->pszVgaBiosFile, RTFILE_O_READ \| RTFILE_O_OPEN \| RTFILE_O_DENY_WRITE);
6675	if (RT_SUCCESS(rc))
6676	{
6677	rc = RTFileQuerySize(FileVgaBios, &pThisCC->cbVgaBios);
6678	if (RT_SUCCESS(rc))
6679	{
6680	if ( RT_ALIGN(pThisCC->cbVgaBios, _4K) != pThisCC->cbVgaBios
6681	\|\| pThisCC->cbVgaBios > _64K
6682	\|\| pThisCC->cbVgaBios < 16 * _1K)
6683	rc = VERR_TOO_MUCH_DATA;
6684	}
6685	}
6686	if (RT_FAILURE(rc))
6687	{
6688	/*
6689	* In case of failure simply fall back to the built-in VGA BIOS ROM.
6690	*/
6691	Log(("vgaConstruct: Failed to open VGA BIOS ROM file '%s', rc=%Rrc!\n", pThisCC->pszVgaBiosFile, rc));
6692	RTFileClose(FileVgaBios);
6693	FileVgaBios = NIL_RTFILE;
6694	PDMDevHlpMMHeapFree(pDevIns, pThisCC->pszVgaBiosFile);
6695	pThisCC->pszVgaBiosFile = NULL;
6696	}
6697	}
6698
6699	/*
6700	* Attempt to get the VGA BIOS ROM data from file.
6701	*/
6702	if (pThisCC->pszVgaBiosFile)
6703	{
6704	/*
6705	* Allocate buffer for the VGA BIOS ROM data.
6706	*/
6707	pThisCC->pbVgaBios = (uint8_t *)PDMDevHlpMMHeapAlloc(pDevIns, pThisCC->cbVgaBios);
6708	if (pThisCC->pbVgaBios)
6709	{
6710	rc = RTFileRead(FileVgaBios, pThisCC->pbVgaBios, pThisCC->cbVgaBios, NULL);
6711	if (RT_FAILURE(rc))
6712	{
6713	AssertMsgFailed(("RTFileRead(,,%d,NULL) -> %Rrc\n", pThisCC->cbVgaBios, rc));
6714	PDMDevHlpMMHeapFree(pDevIns, pThisCC->pbVgaBios);
6715	pThisCC->pbVgaBios = NULL;
6716	}
6717	rc = VINF_SUCCESS;
6718	}
6719	else
6720	rc = VERR_NO_MEMORY;
6721	}
6722	else
6723	pThisCC->pbVgaBios = NULL;
6724
6725	/* cleanup */
6726	if (FileVgaBios != NIL_RTFILE)
6727	RTFileClose(FileVgaBios);
6728
6729	/* If we were unable to get the data from file for whatever reason, fall
6730	back to the built-in ROM image. */
6731	const uint8_t *pbVgaBiosBinary;
6732	uint64_t cbVgaBiosBinary;
6733	uint32_t fFlags = 0;
6734	if (pThisCC->pbVgaBios == NULL)
6735	{
6736	CPUMMICROARCH enmMicroarch = PDMDevHlpCpuGetGuestMicroarch(pDevIns);
6737	if ( enmMicroarch == kCpumMicroarch_Intel_8086
6738	\|\| enmMicroarch == kCpumMicroarch_Intel_80186
6739	\|\| enmMicroarch == kCpumMicroarch_NEC_V20
6740	\|\| enmMicroarch == kCpumMicroarch_NEC_V30)
6741	{
6742	pbVgaBiosBinary = g_abVgaBiosBinary8086;
6743	cbVgaBiosBinary = g_cbVgaBiosBinary8086;
6744	LogRel(("VGA: Using the 8086 BIOS image!\n"));
6745	}
6746	else if (enmMicroarch == kCpumMicroarch_Intel_80286)
6747	{
6748	pbVgaBiosBinary = g_abVgaBiosBinary286;
6749	cbVgaBiosBinary = g_cbVgaBiosBinary286;
6750	LogRel(("VGA: Using the 286 BIOS image!\n"));
6751	}
6752	else
6753	{
6754	pbVgaBiosBinary = g_abVgaBiosBinary386;
6755	cbVgaBiosBinary = g_cbVgaBiosBinary386;
6756	LogRel(("VGA: Using the 386+ BIOS image.\n"));
6757	}
6758	fFlags = PGMPHYS_ROM_FLAGS_PERMANENT_BINARY;
6759	}
6760	else
6761	{
6762	pbVgaBiosBinary = pThisCC->pbVgaBios;
6763	cbVgaBiosBinary = pThisCC->cbVgaBios;
6764	}
6765
6766	AssertReleaseMsg(cbVgaBiosBinary <= _64K && cbVgaBiosBinary >= 32*_1K, ("cbVgaBiosBinary=%#x\n", cbVgaBiosBinary));
6767	AssertReleaseMsg(RT_ALIGN_Z(cbVgaBiosBinary, PAGE_SIZE) == cbVgaBiosBinary, ("cbVgaBiosBinary=%#x\n", cbVgaBiosBinary));
6768	/* Note! Because of old saved states we'll always register at least 36KB of ROM. */
6769	rc = PDMDevHlpROMRegister(pDevIns, 0x000c0000, RT_MAX(cbVgaBiosBinary, 36*_1K), pbVgaBiosBinary, cbVgaBiosBinary,
6770	fFlags, "VGA BIOS");
6771	AssertRCReturn(rc, rc);
6772
6773	/*
6774	* Saved state.
6775	*/
6776	rc = PDMDevHlpSSMRegisterEx(pDevIns, VGA_SAVEDSTATE_VERSION, sizeof(*pThis), NULL,
6777	NULL, vgaR3LiveExec, NULL,
6778	vgaR3SavePrep, vgaR3SaveExec, vgaR3SaveDone,
6779	vgaR3LoadPrep, vgaR3LoadExec, vgaR3LoadDone);
6780	AssertRCReturn(rc, rc);
6781
6782	/*
6783	* Create the refresh timer.
6784	*/
6785	rc = PDMDevHlpTimerCreate(pDevIns, TMCLOCK_REAL, vgaR3TimerRefresh, NULL,
6786	TMTIMER_FLAGS_NO_CRIT_SECT \| TMTIMER_FLAGS_NO_RING0, "VGA Refresh Timer", &pThis->hRefreshTimer);
6787	AssertRCReturn(rc, rc);
6788
6789	/*
6790	* Attach to the display.
6791	*/
6792	rc = vgaAttach(pDevIns, 0 /* display LUN # */, PDM_TACH_FLAGS_NOT_HOT_PLUG);
6793	AssertRCReturn(rc, rc);
6794
6795	/*
6796	* Initialize the retrace flag.
6797	*/
6798	rc = pHlp->pfnCFGMQueryBoolDef(pCfg, "RealRetrace", &pThis->fRealRetrace, false);
6799	AssertLogRelRCReturn(rc, rc);
6800
6801	uint16_t maxBiosXRes;
6802	rc = pHlp->pfnCFGMQueryU16Def(pCfg, "MaxBiosXRes", &maxBiosXRes, UINT16_MAX);
6803	AssertLogRelRCReturn(rc, rc);
6804	uint16_t maxBiosYRes;
6805	rc = pHlp->pfnCFGMQueryU16Def(pCfg, "MaxBiosYRes", &maxBiosYRes, UINT16_MAX);
6806	AssertLogRelRCReturn(rc, rc);
6807
6808	/*
6809	* Compute buffer size for the VBE BIOS Extra Data.
6810	*/
6811	cb = sizeof(mode_info_list) + sizeof(ModeInfoListItem);
6812
6813	rc = pHlp->pfnCFGMQueryU32(pCfg, "HeightReduction", &cyReduction);
6814	if (RT_SUCCESS(rc) && cyReduction)
6815	cb = 2; / Default mode list will be twice long */
6816	else
6817	cyReduction = 0;
6818
6819	rc = pHlp->pfnCFGMQueryU32(pCfg, "CustomVideoModes", &cCustomModes);
6820	if (RT_SUCCESS(rc) && cCustomModes)
6821	cb += sizeof(ModeInfoListItem) * cCustomModes;
6822	else
6823	cCustomModes = 0;
6824
6825	/*
6826	* Allocate and initialize buffer for the VBE BIOS Extra Data.
6827	*/
6828	AssertRelease(sizeof(VBEHEADER) + cb < 65536);
6829	pThisCC->cbVBEExtraData = (uint16_t)(sizeof(VBEHEADER) + cb);
6830	pThisCC->pbVBEExtraData = (uint8_t *)PDMDevHlpMMHeapAllocZ(pDevIns, pThisCC->cbVBEExtraData);
6831	if (!pThisCC->pbVBEExtraData)
6832	return VERR_NO_MEMORY;
6833
6834	pVBEDataHdr = (PVBEHEADER)pThisCC->pbVBEExtraData;
6835	pVBEDataHdr->u16Signature = VBEHEADER_MAGIC;
6836	pVBEDataHdr->cbData = cb;
6837
6838	pCurMode = (ModeInfoListItem *)(pVBEDataHdr + 1);
6839	for (i = 0; i < MODE_INFO_SIZE; i++)
6840	{
6841	uint32_t pixelWidth, reqSize;
6842	if (mode_info_list[i].info.MemoryModel == VBE_MEMORYMODEL_TEXT_MODE)
6843	pixelWidth = 2;
6844	else
6845	pixelWidth = (mode_info_list[i].info.BitsPerPixel +7) / 8;
6846	reqSize = mode_info_list[i].info.XResolution
6847	* mode_info_list[i].info.YResolution
6848	* pixelWidth;
6849	if (reqSize >= pThis->vram_size)
6850	continue;
6851	if (!reqSize)
6852	continue;
6853	if ( mode_info_list[i].info.XResolution > maxBiosXRes
6854	\|\| mode_info_list[i].info.YResolution > maxBiosYRes)
6855	continue;
6856	*pCurMode = mode_info_list[i];
6857	vgaR3AdjustModeInfo(pThis, pCurMode);
6858	pCurMode++;
6859	}
6860
6861	/*
6862	* Copy default modes with subtracted YResolution.
6863	*/
6864	if (cyReduction)
6865	{
6866	ModeInfoListItem *pDefMode = mode_info_list;
6867	Log(("vgaR3Construct: cyReduction=%u\n", cyReduction));
6868	for (i = 0; i < MODE_INFO_SIZE; i++, pDefMode++)
6869	{
6870	uint32_t pixelWidth, reqSize;
6871	if (pDefMode->info.MemoryModel == VBE_MEMORYMODEL_TEXT_MODE)
6872	pixelWidth = 2;
6873	else
6874	pixelWidth = (pDefMode->info.BitsPerPixel + 7) / 8;
6875	reqSize = pDefMode->info.XResolution * pDefMode->info.YResolution * pixelWidth;
6876	if (reqSize >= pThis->vram_size)
6877	continue;
6878	if ( pDefMode->info.XResolution > maxBiosXRes
6879	\|\| pDefMode->info.YResolution - cyReduction > maxBiosYRes)
6880	continue;
6881	pCurMode = pDefMode;
6882	pCurMode->mode += 0x30;
6883	pCurMode->info.YResolution -= cyReduction;
6884	pCurMode++;
6885	}
6886	}
6887
6888
6889	/*
6890	* Add custom modes.
6891	*/
6892	if (cCustomModes)
6893	{
6894	uint16_t u16CurMode = VBE_VBOX_MODE_CUSTOM1;
6895	for (i = 1; i <= cCustomModes; i++)
6896	{
6897	char szExtraDataKey[sizeof("CustomVideoModeXX")];
6898	char *pszExtraData = NULL;
6899
6900	/* query and decode the custom mode string. */
6901	RTStrPrintf(szExtraDataKey, sizeof(szExtraDataKey), "CustomVideoMode%d", i);
6902	rc = pHlp->pfnCFGMQueryStringAlloc(pCfg, szExtraDataKey, &pszExtraData);
6903	if (RT_SUCCESS(rc))
6904	{
6905	ModeInfoListItem *pDefMode = mode_info_list;
6906	unsigned int cx, cy, cBits, cParams, j;
6907	uint16_t u16DefMode;
6908
6909	cParams = sscanf(pszExtraData, "%ux%ux%u", &cx, &cy, &cBits);
6910	if ( cParams != 3
6911	\|\| (cBits != 8 && cBits != 16 && cBits != 24 && cBits != 32))
6912	{
6913	AssertMsgFailed(("Configuration error: Invalid mode data '%s' for '%s'! cBits=%d\n", pszExtraData, szExtraDataKey, cBits));
6914	return VERR_VGA_INVALID_CUSTOM_MODE;
6915	}
6916	if (!cx \|\| !cy)
6917	{
6918	AssertMsgFailed(("Configuration error: Invalid mode data '%s' for '%s'! cx=%u, cy=%u\n", pszExtraData, szExtraDataKey, cx, cy));
6919	return VERR_VGA_INVALID_CUSTOM_MODE;
6920	}
6921	cbPitch = calc_line_pitch(cBits, cx);
6922	if (cy * cbPitch >= pThis->vram_size)
6923	{
6924	AssertMsgFailed(("Configuration error: custom video mode %dx%dx%dbits is too large for the virtual video memory of %dMb. Please increase the video memory size.\n",
6925	cx, cy, cBits, pThis->vram_size / _1M));
6926	return VERR_VGA_INVALID_CUSTOM_MODE;
6927	}
6928	PDMDevHlpMMHeapFree(pDevIns, pszExtraData);
6929
6930	/* Use defaults from max@bpp mode. */
6931	switch (cBits)
6932	{
6933	case 8:
6934	u16DefMode = VBE_VESA_MODE_1024X768X8;
6935	break;
6936
6937	case 16:
6938	u16DefMode = VBE_VESA_MODE_1024X768X565;
6939	break;
6940
6941	case 24:
6942	u16DefMode = VBE_VESA_MODE_1024X768X888;
6943	break;
6944
6945	case 32:
6946	u16DefMode = VBE_OWN_MODE_1024X768X8888;
6947	break;
6948
6949	default: /* gcc, shut up! */
6950	AssertMsgFailed(("gone postal!\n"));
6951	continue;
6952	}
6953
6954	/* mode_info_list is not terminated */
6955	for (j = 0; j < MODE_INFO_SIZE && pDefMode->mode != u16DefMode; j++)
6956	pDefMode++;
6957	Assert(j < MODE_INFO_SIZE);
6958
6959	pCurMode = pDefMode;
6960	pCurMode->mode = u16CurMode++;
6961
6962	/* adjust defaults */
6963	pCurMode->info.XResolution = cx;
6964	pCurMode->info.YResolution = cy;
6965	pCurMode->info.BytesPerScanLine = cbPitch;
6966	pCurMode->info.LinBytesPerScanLine = cbPitch;
6967	vgaR3AdjustModeInfo(pThis, pCurMode);
6968
6969	/* commit it */
6970	pCurMode++;
6971	}
6972	else if (rc != VERR_CFGM_VALUE_NOT_FOUND)
6973	{
6974	AssertMsgFailed(("pHlp->pfnCFGMQueryStringAlloc(,'%s',) -> %Rrc\n", szExtraDataKey, rc));
6975	return rc;
6976	}
6977	} /* foreach custom mode key */
6978	}
6979
6980	/*
6981	* Add the "End of list" mode.
6982	*/
6983	memset(pCurMode, 0, sizeof(*pCurMode));
6984	pCurMode->mode = VBE_VESA_MODE_END_OF_LIST;
6985
6986	/*
6987	* Register I/O Port for the VBE BIOS Extra Data.
6988	*/
6989	rc = PDMDevHlpIoPortCreateAndMap(pDevIns, VBE_EXTRA_PORT, 1 /cPorts/, vbeR3IOPortWriteVbeExtra, vbeR3IoPortReadVbeExtra,
6990	"VBE BIOS Extra Data", NULL /paExtDesc/, &pThis->hIoPortVbeExtra);
6991	AssertRCReturn(rc, rc);
6992
6993	/*
6994	* Register I/O Port for the BIOS Logo.
6995	*/
6996	rc = PDMDevHlpIoPortCreateAndMap(pDevIns, LOGO_IO_PORT, 1 /cPorts/, vbeR3IoPortWriteCmdLogo, vbeR3IoPortReadCmdLogo,
6997	"BIOS Logo", NULL /paExtDesc/, &pThis->hIoPortCmdLogo);
6998	AssertRCReturn(rc, rc);
6999
7000	/*
7001	* Register debugger info callbacks.
7002	*/
7003	PDMDevHlpDBGFInfoRegister(pDevIns, "vga", "Display basic VGA state.", vgaR3InfoState);
7004	PDMDevHlpDBGFInfoRegister(pDevIns, "vgatext", "Display VGA memory formatted as text.", vgaR3InfoText);
7005	PDMDevHlpDBGFInfoRegister(pDevIns, "vgacr", "Dump VGA CRTC registers.", vgaR3InfoCR);
7006	PDMDevHlpDBGFInfoRegister(pDevIns, "vgagr", "Dump VGA Graphics Controller registers.", vgaR3InfoGR);
7007	PDMDevHlpDBGFInfoRegister(pDevIns, "vgasr", "Dump VGA Sequencer registers.", vgaR3InfoSR);
7008	PDMDevHlpDBGFInfoRegister(pDevIns, "vgaar", "Dump VGA Attribute Controller registers.", vgaR3InfoAR);
7009	PDMDevHlpDBGFInfoRegister(pDevIns, "vgapl", "Dump planar graphics state.", vgaR3InfoPlanar);
7010	PDMDevHlpDBGFInfoRegister(pDevIns, "vgadac", "Dump VGA DAC registers.", vgaR3InfoDAC);
7011	PDMDevHlpDBGFInfoRegister(pDevIns, "vbe", "Dump VGA VBE registers.", vgaR3InfoVBE);
7012
7013	/*
7014	* Construct the logo header.
7015	*/
7016	LOGOHDR LogoHdr = { LOGO_HDR_MAGIC, 0, 0, 0, 0, 0, 0 };
7017
7018	rc = pHlp->pfnCFGMQueryU8(pCfg, "FadeIn", &LogoHdr.fu8FadeIn);
7019	if (rc == VERR_CFGM_VALUE_NOT_FOUND)
7020	LogoHdr.fu8FadeIn = 1;
7021	else if (RT_FAILURE(rc))
7022	return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Querying \"FadeIn\" as integer failed"));
7023
7024	rc = pHlp->pfnCFGMQueryU8(pCfg, "FadeOut", &LogoHdr.fu8FadeOut);
7025	if (rc == VERR_CFGM_VALUE_NOT_FOUND)
7026	LogoHdr.fu8FadeOut = 1;
7027	else if (RT_FAILURE(rc))
7028	return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Querying \"FadeOut\" as integer failed"));
7029
7030	rc = pHlp->pfnCFGMQueryU16(pCfg, "LogoTime", &LogoHdr.u16LogoMillies);
7031	if (rc == VERR_CFGM_VALUE_NOT_FOUND)
7032	LogoHdr.u16LogoMillies = 0;
7033	else if (RT_FAILURE(rc))
7034	return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Querying \"LogoTime\" as integer failed"));
7035
7036	rc = pHlp->pfnCFGMQueryU8(pCfg, "ShowBootMenu", &LogoHdr.fu8ShowBootMenu);
7037	if (rc == VERR_CFGM_VALUE_NOT_FOUND)
7038	LogoHdr.fu8ShowBootMenu = 0;
7039	else if (RT_FAILURE(rc))
7040	return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Querying \"ShowBootMenu\" as integer failed"));
7041
7042	# if defined(DEBUG) && !defined(DEBUG_sunlover) && !defined(DEBUG_michael)
7043	/* Disable the logo abd menu if all default settings. */
7044	if ( LogoHdr.fu8FadeIn
7045	&& LogoHdr.fu8FadeOut
7046	&& LogoHdr.u16LogoMillies == 0
7047	&& LogoHdr.fu8ShowBootMenu == 2)
7048	{
7049	LogoHdr.fu8FadeIn = LogoHdr.fu8FadeOut = 0;
7050	LogoHdr.u16LogoMillies = 500;
7051	}
7052	# endif
7053
7054	/* Delay the logo a little bit */
7055	if (LogoHdr.fu8FadeIn && LogoHdr.fu8FadeOut && !LogoHdr.u16LogoMillies)
7056	LogoHdr.u16LogoMillies = RT_MAX(LogoHdr.u16LogoMillies, LOGO_DELAY_TIME);
7057
7058	/*
7059	* Get the Logo file name.
7060	*/
7061	rc = pHlp->pfnCFGMQueryStringAlloc(pCfg, "LogoFile", &pThisCC->pszLogoFile);
7062	if (rc == VERR_CFGM_VALUE_NOT_FOUND)
7063	pThisCC->pszLogoFile = NULL;
7064	else if (RT_FAILURE(rc))
7065	return PDMDEV_SET_ERROR(pDevIns, rc,
7066	N_("Configuration error: Querying \"LogoFile\" as a string failed"));
7067	else if (!*pThisCC->pszLogoFile)
7068	{
7069	PDMDevHlpMMHeapFree(pDevIns, pThisCC->pszLogoFile);
7070	pThisCC->pszLogoFile = NULL;
7071	}
7072
7073	/*
7074	* Determine the logo size, open any specified logo file in the process.
7075	*/
7076	LogoHdr.cbLogo = g_cbVgaDefBiosLogo;
7077	RTFILE FileLogo = NIL_RTFILE;
7078	if (pThisCC->pszLogoFile)
7079	{
7080	rc = RTFileOpen(&FileLogo, pThisCC->pszLogoFile,
7081	RTFILE_O_READ \| RTFILE_O_OPEN \| RTFILE_O_DENY_WRITE);
7082	if (RT_SUCCESS(rc))
7083	{
7084	uint64_t cbFile;
7085	rc = RTFileQuerySize(FileLogo, &cbFile);
7086	if (RT_SUCCESS(rc))
7087	{
7088	if (cbFile > 0 && cbFile < 32*_1M)
7089	LogoHdr.cbLogo = (uint32_t)cbFile;
7090	else
7091	rc = VERR_TOO_MUCH_DATA;
7092	}
7093	}
7094	if (RT_FAILURE(rc))
7095	{
7096	/*
7097	* Ignore failure and fall back to the default logo.
7098	*/
7099	LogRel(("vgaR3Construct: Failed to open logo file '%s', rc=%Rrc!\n", pThisCC->pszLogoFile, rc));
7100	if (FileLogo != NIL_RTFILE)
7101	RTFileClose(FileLogo);
7102	FileLogo = NIL_RTFILE;
7103	PDMDevHlpMMHeapFree(pDevIns, pThisCC->pszLogoFile);
7104	pThisCC->pszLogoFile = NULL;
7105	}
7106	}
7107
7108	/*
7109	* Disable graphic splash screen if it doesn't fit into VRAM.
7110	*/
7111	if (pThis->vram_size < LOGO_MAX_SIZE)
7112	LogoHdr.fu8FadeIn = LogoHdr.fu8FadeOut = LogoHdr.u16LogoMillies = 0;
7113
7114	/*
7115	* Allocate buffer for the logo data.
7116	* Let us fall back to default logo on read failure.
7117	*/
7118	pThisCC->cbLogo = LogoHdr.cbLogo;
7119	if (g_cbVgaDefBiosLogo)
7120	pThisCC->cbLogo = g_cbVgaDefBiosLogo;
7121	# ifndef VBOX_OSE
7122	if (g_cbVgaDefBiosLogoNY)
7123	pThisCC->cbLogo = g_cbVgaDefBiosLogoNY;
7124	# endif
7125	pThisCC->cbLogo += sizeof(LogoHdr);
7126
7127	pThisCC->pbLogo = (uint8_t *)PDMDevHlpMMHeapAlloc(pDevIns, pThisCC->cbLogo);
7128	if (pThisCC->pbLogo)
7129	{
7130	/*
7131	* Write the logo header.
7132	*/
7133	PLOGOHDR pLogoHdr = (PLOGOHDR)pThisCC->pbLogo;
7134	*pLogoHdr = LogoHdr;
7135
7136	/*
7137	* Write the logo bitmap.
7138	*/
7139	if (pThisCC->pszLogoFile)
7140	{
7141	rc = RTFileRead(FileLogo, pLogoHdr + 1, LogoHdr.cbLogo, NULL);
7142	if (RT_SUCCESS(rc))
7143	rc = vbeR3ParseBitmap(pThisCC);
7144	if (RT_FAILURE(rc))
7145	{
7146	LogRel(("Error %Rrc reading logo file '%s', using internal logo\n",
7147	rc, pThisCC->pszLogoFile));
7148	pLogoHdr->cbLogo = LogoHdr.cbLogo = g_cbVgaDefBiosLogo;
7149	}
7150	}
7151	if ( !pThisCC->pszLogoFile
7152	\|\| RT_FAILURE(rc))
7153	{
7154	# ifndef VBOX_OSE
7155	RTTIMESPEC Now;
7156	RTTimeLocalNow(&Now);
7157	RTTIME T;
7158	RTTimeLocalExplode(&T, &Now);
7159	bool fSuppressNewYearSplash = false;
7160	rc = pHlp->pfnCFGMQueryBoolDef(pCfg, "SuppressNewYearSplash", &fSuppressNewYearSplash, true);
7161	if ( !fSuppressNewYearSplash
7162	&& (T.u16YearDay > 353 \|\| T.u16YearDay < 10))
7163	{
7164	pLogoHdr->cbLogo = LogoHdr.cbLogo = g_cbVgaDefBiosLogoNY;
7165	memcpy(pLogoHdr + 1, g_abVgaDefBiosLogoNY, LogoHdr.cbLogo);
7166	pThisCC->fBootMenuInverse = true;
7167	}
7168	else
7169	# endif
7170	memcpy(pLogoHdr + 1, g_abVgaDefBiosLogo, LogoHdr.cbLogo);
7171	rc = vbeR3ParseBitmap(pThisCC);
7172	AssertLogRelMsgReturn(RT_SUCCESS(rc), ("Parsing of internal bitmap failed! vbeR3ParseBitmap() -> %Rrc\n", rc), rc);
7173	}
7174
7175	rc = VINF_SUCCESS;
7176	}
7177	else
7178	rc = VERR_NO_MEMORY;
7179
7180	/*
7181	* Cleanup.
7182	*/
7183	if (FileLogo != NIL_RTFILE)
7184	RTFileClose(FileLogo);
7185
7186	# ifdef VBOX_WITH_HGSMI
7187	VBVAInit(pDevIns, pThis, pThisCC);
7188	# endif
7189
7190	# ifdef VBOX_WITH_VDMA
7191	if (rc == VINF_SUCCESS)
7192	{
7193	rc = vboxVDMAConstruct(pThis, pThisCC, 1024);
7194	AssertRC(rc);
7195	}
7196	# endif
7197
7198	# ifdef VBOX_WITH_VMSVGA
7199	if ( rc == VINF_SUCCESS
7200	&& pThis->fVMSVGAEnabled)
7201	rc = vmsvgaR3Init(pDevIns);
7202	# endif
7203
7204	/*
7205	* Statistics.
7206	*/
7207	# ifdef VBOX_WITH_STATISTICS
7208	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatRZMemoryRead, STAMTYPE_PROFILE, "RZ/MMIO-Read", STAMUNIT_TICKS_PER_CALL, "Profiling of the VGAGCMemoryRead() body.");
7209	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatR3MemoryRead, STAMTYPE_PROFILE, "R3/MMIO-Read", STAMUNIT_TICKS_PER_CALL, "Profiling of the VGAGCMemoryRead() body.");
7210	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatRZMemoryWrite, STAMTYPE_PROFILE, "RZ/MMIO-Write", STAMUNIT_TICKS_PER_CALL, "Profiling of the VGAGCMemoryWrite() body.");
7211	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatR3MemoryWrite, STAMTYPE_PROFILE, "R3/MMIO-Write", STAMUNIT_TICKS_PER_CALL, "Profiling of the VGAGCMemoryWrite() body.");
7212	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMapPage, STAMTYPE_COUNTER, "MapPageCalls", STAMUNIT_OCCURENCES, "Calls to IOMMmioMapMmio2Page.");
7213	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatUpdateDisp, STAMTYPE_COUNTER, "UpdateDisplay", STAMUNIT_OCCURENCES, "Calls to vgaR3PortUpdateDisplay().");
7214	# endif
7215	# ifdef VBOX_WITH_HGSMI
7216	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatHgsmiMdaCgaAccesses, STAMTYPE_COUNTER, "HgmsiMdaCgaAccesses", STAMUNIT_OCCURENCES, "Number of non-HGMSI accesses for 03b0-3b3 and 03d0-3d3.");
7217	# endif
7218
7219	/* Init latched access mask. */
7220	pThis->uMaskLatchAccess = 0x3ff;
7221
7222	if (RT_SUCCESS(rc))
7223	{
7224	PPDMIBASE pBase;
7225	/*
7226	* Attach status driver (optional).
7227	*/
7228	rc = PDMDevHlpDriverAttach(pDevIns, PDM_STATUS_LUN, &pThisCC->IBase, &pBase, "Status Port");
7229	if (RT_SUCCESS(rc))
7230	pThisCC->pLedsConnector = PDMIBASE_QUERY_INTERFACE(pBase, PDMILEDCONNECTORS);
7231	else if (rc == VERR_PDM_NO_ATTACHED_DRIVER)
7232	{
7233	Log(("%s/%d: warning: no driver attached to LUN #0!\n", pDevIns->pReg->szName, pDevIns->iInstance));
7234	rc = VINF_SUCCESS;
7235	}
7236	else
7237	{
7238	AssertMsgFailed(("Failed to attach to status driver. rc=%Rrc\n", rc));
7239	rc = PDMDEV_SET_ERROR(pDevIns, rc, N_("VGA cannot attach to status driver"));
7240	}
7241	}
7242	return rc;
7243	}
7244
7245	#else /* !IN_RING3 */
7246
7247	/**
7248	* @callback_method_impl{PDMDEVREGR0,pfnConstruct}
7249	*/
7250	static DECLCALLBACK(int) vgaRZConstruct(PPDMDEVINS pDevIns)
7251	{
7252	PDMDEV_CHECK_VERSIONS_RETURN(pDevIns);
7253	PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE);
7254	PVGASTATECC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PVGASTATECC);
7255
7256	int rc = PDMDevHlpSetDeviceCritSect(pDevIns, &pThis->CritSect);
7257	AssertRCReturn(rc, rc);
7258
7259	/*
7260	* Set I/O port callbacks for this context.
7261	* We just copy the ring-3 registration bits and remove the '&' before the handle.
7262	*/
7263	# define REG_PORT(a_uPort, a_cPorts, a_pfnWrite, a_pfnRead, a_szDesc, a_hIoPort) do { \
7264	rc = PDMDevHlpIoPortSetUpContext(pDevIns, a_hIoPort, a_pfnWrite, a_pfnRead, NULL /pvUser/); \
7265	AssertRCReturn(rc, rc); \
7266	} while (0)
7267
7268	REG_PORT(0x3c0, 2, vgaIoPortArWrite, vgaIoPortArRead, "Attribute Controller", pThis->hIoPortAr);
7269	REG_PORT(0x3c2, 1, vgaIoPortMsrWrite, vgaIoPortSt00Read, "MSR / ST00", pThis->hIoPortMsrSt00);
7270	REG_PORT(0x3c3, 1, vgaIoPortUnusedWrite, vgaIoPortUnusedRead, "0x3c3", pThis->hIoPort3c3);
7271	REG_PORT(0x3c4, 2, vgaIoPortSrWrite, vgaIoPortSrRead, "Sequencer", pThis->hIoPortSr);
7272	REG_PORT(0x3c6, 4, vgaIoPortDacWrite, vgaIoPortDacRead, "DAC", pThis->hIoPortDac);
7273	REG_PORT(0x3ca, 4, vgaIoPortPosWrite, vgaIoPortPosRead, "Graphics Position", /?/ pThis->hIoPortPos);
7274	REG_PORT(0x3ce, 2, vgaIoPortGrWrite, vgaIoPortGrRead, "Graphics Controller", pThis->hIoPortGr);
7275
7276	REG_PORT(0x3b4, 2, vgaIoPortMdaCrtWrite, vgaIoPortMdaCrtRead, "MDA CRT control", pThis->hIoPortMdaCrt);
7277	REG_PORT(0x3ba, 1, vgaIoPortMdaFcrWrite, vgaIoPortMdaStRead, "MDA feature/status", pThis->hIoPortMdaFcrSt);
7278	REG_PORT(0x3d4, 2, vgaIoPortCgaCrtWrite, vgaIoPortCgaCrtRead, "CGA CRT control", pThis->hIoPortCgaCrt);
7279	REG_PORT(0x3da, 1, vgaIoPortCgaFcrWrite, vgaIoPortCgaStRead, "CGA Feature / status", pThis->hIoPortCgaFcrSt);
7280
7281	# ifdef CONFIG_BOCHS_VBE
7282	REG_PORT(0x1ce, 1, vgaIoPortWriteVbeIndex, vgaIoPortReadVbeIndex, "VBE Index", pThis->hIoPortVbeIndex);
7283	REG_PORT(0x1cf, 1, vgaIoPortWriteVbeData, vgaIoPortReadVbeData, "VBE Data", pThis->hIoPortVbeData);
7284	# endif /* CONFIG_BOCHS_VBE */
7285
7286	# undef REG_PORT
7287
7288	/* BIOS port: */
7289	rc = PDMDevHlpIoPortSetUpContext(pDevIns, pThis->hIoPortBios, vgaIoPortWriteBios, vgaIoPortReadBios, NULL /pvUser/);
7290	AssertRCReturn(rc, rc);
7291
7292	# ifdef VBOX_WITH_VMSVGA
7293	if (pThis->hIoPortVmSvga != NIL_IOMIOPORTHANDLE)
7294	{
7295	AssertReturn(pThis->fVMSVGAEnabled, VERR_INVALID_STATE);
7296	rc = PDMDevHlpIoPortSetUpContext(pDevIns, pThis->hIoPortVmSvga, vmsvgaIOWrite, vmsvgaIORead, NULL /pvUser/);
7297	AssertRCReturn(rc, rc);
7298	}
7299	else
7300	AssertReturn(!pThis->fVMSVGAEnabled, VERR_INVALID_STATE);
7301	# endif
7302
7303	/*
7304	* MMIO.
7305	*/
7306	rc = PDMDevHlpMmioSetUpContextEx(pDevIns, pThis->hMmioLegacy, vgaMmioWrite, vgaMmioRead, vgaMmioFill, NULL /pvUser/);
7307	AssertRCReturn(rc, rc);
7308
7309	/*
7310	* Map the start of the VRAM into this context.
7311	*/
7312	# if defined(VBOX_WITH_2X_4GB_ADDR_SPACE) \|\| (defined(IN_RING0) && defined(VGA_WITH_PARTIAL_RING0_MAPPING))
7313	rc = PDMDevHlpMmio2SetUpContext(pDevIns, pThis->hMmio2VRam, 0 /* off /, VGA_MAPPING_SIZE, (void *)&pThisCC->pbVRam);
7314	AssertLogRelMsgRCReturn(rc, ("PDMDevHlpMmio2SetUpContext(,VRAM,0,%#x,) -> %Rrc\n", VGA_MAPPING_SIZE, rc), rc);
7315	# endif
7316
7317	/*
7318	* Map the first page of the VMSVGA FIFO into this context (not raw-mode).
7319	* We currently only access SVGA_FIFO_MIN, SVGA_FIFO_PITCHLOCK, and SVGA_FIFO_BUSY.
7320	*/
7321	# if defined(VBOX_WITH_VMSVGA) && !defined(IN_RC)
7322	AssertCompile((RT_MAX(SVGA_FIFO_MIN, RT_MAX(SVGA_FIFO_PITCHLOCK, SVGA_FIFO_BUSY)) + 1) * sizeof(uint32_t) < PAGE_SIZE);
7323	if (pThis->fVMSVGAEnabled)
7324	{
7325	rc = PDMDevHlpMmio2SetUpContext(pDevIns, pThis->hMmio2VmSvgaFifo, 0 /* off */, PAGE_SIZE,
7326	(void **)&pThisCC->svga.pau32FIFO);
7327	AssertLogRelMsgRCReturn(rc, ("PDMDevHlpMapMMIO2IntoR0(%#x,) -> %Rrc\n", pThis->svga.cbFIFO, rc), rc);
7328	}
7329	else
7330	AssertReturn(pThis->hMmio2VmSvgaFifo == NIL_PGMMMIO2HANDLE, VERR_INVALID_STATE);
7331	# endif
7332
7333	return VINF_SUCCESS;
7334	}
7335
7336	#endif /* !IN_RING3 */
7337
7338	/**
7339	* The device registration structure.
7340	*/
7341	const PDMDEVREG g_DeviceVga =
7342	{
7343	/* .u32Version = */ PDM_DEVREG_VERSION,
7344	/* .uReserved0 = */ 0,
7345	/* .szName = */ "vga",
7346	/* .fFlags = */ PDM_DEVREG_FLAGS_DEFAULT_BITS \| PDM_DEVREG_FLAGS_RZ \| PDM_DEVREG_FLAGS_NEW_STYLE,
7347	/* .fClass = */ PDM_DEVREG_CLASS_GRAPHICS,
7348	/* .cMaxInstances = */ 1,
7349	/* .uSharedVersion = */ 42,
7350	/* .cbInstanceShared = */ sizeof(VGASTATE),
7351	/* .cbInstanceCC = */ sizeof(VGASTATECC),
7352	/* .cbInstanceRC = */ sizeof(VGASTATERC),
7353	/* .cMaxPciDevices = */ 1,
7354	/* .cMaxMsixVectors = */ 0,
7355	/* .pszDescription = */ "VGA Adaptor with VESA extensions.",
7356	#if defined(IN_RING3)
7357	/* .pszRCMod = */ "VBoxDDRC.rc",
7358	/* .pszR0Mod = */ "VBoxDDR0.r0",
7359	/* .pfnConstruct = */ vgaR3Construct,
7360	/* .pfnDestruct = */ vgaR3Destruct,
7361	/* .pfnRelocate = */ vgaR3Relocate,
7362	/* .pfnMemSetup = */ NULL,
7363	/* .pfnPowerOn = */ vgaR3PowerOn,
7364	/* .pfnReset = */ vgaR3Reset,
7365	/* .pfnSuspend = */ NULL,
7366	/* .pfnResume = */ vgaR3Resume,
7367	/* .pfnAttach = */ vgaAttach,
7368	/* .pfnDetach = */ vgaDetach,
7369	/* .pfnQueryInterface = */ NULL,
7370	/* .pfnInitComplete = */ NULL,
7371	/* .pfnPowerOff = */ vgaR3PowerOff,
7372	/* .pfnSoftReset = */ NULL,
7373	/* .pfnReserved0 = */ NULL,
7374	/* .pfnReserved1 = */ NULL,
7375	/* .pfnReserved2 = */ NULL,
7376	/* .pfnReserved3 = */ NULL,
7377	/* .pfnReserved4 = */ NULL,
7378	/* .pfnReserved5 = */ NULL,
7379	/* .pfnReserved6 = */ NULL,
7380	/* .pfnReserved7 = */ NULL,
7381	#elif defined(IN_RING0)
7382	/* .pfnEarlyConstruct = */ NULL,
7383	/* .pfnConstruct = */ vgaRZConstruct,
7384	/* .pfnDestruct = */ NULL,
7385	/* .pfnFinalDestruct = */ NULL,
7386	/* .pfnRequest = */ NULL,
7387	/* .pfnReserved0 = */ NULL,
7388	/* .pfnReserved1 = */ NULL,
7389	/* .pfnReserved2 = */ NULL,
7390	/* .pfnReserved3 = */ NULL,
7391	/* .pfnReserved4 = */ NULL,
7392	/* .pfnReserved5 = */ NULL,
7393	/* .pfnReserved6 = */ NULL,
7394	/* .pfnReserved7 = */ NULL,
7395	#elif defined(IN_RC)
7396	/* .pfnConstruct = */ vgaRZConstruct,
7397	/* .pfnReserved0 = */ NULL,
7398	/* .pfnReserved1 = */ NULL,
7399	/* .pfnReserved2 = */ NULL,
7400	/* .pfnReserved3 = */ NULL,
7401	/* .pfnReserved4 = */ NULL,
7402	/* .pfnReserved5 = */ NULL,
7403	/* .pfnReserved6 = */ NULL,
7404	/* .pfnReserved7 = */ NULL,
7405	#else
7406	# error "Not in IN_RING3, IN_RING0 or IN_RC!"
7407	#endif
7408	/* .u32VersionEnd = */ PDM_DEVREG_VERSION
7409	};
7410
7411	#endif /* !VBOX_DEVICE_STRUCT_TESTCASE */
7412
7413	/*
7414	* Local Variables:
7415	* nuke-trailing-whitespace-p:nil
7416	* End:
7417	*/

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source: vbox/trunk/src/VBox/Devices/Graphics/DevVGA.cpp@ 87766

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